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fe56b9e6 | 1 | /* QLogic qed NIC Driver |
e8f1cb50 | 2 | * Copyright (c) 2015-2017 QLogic Corporation |
fe56b9e6 | 3 | * |
e8f1cb50 MY |
4 | * This software is available to you under a choice of one of two |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and /or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
fe56b9e6 YM |
31 | */ |
32 | ||
33 | #ifndef _QED_H | |
34 | #define _QED_H | |
35 | ||
36 | #include <linux/types.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/firmware.h> | |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/list.h> | |
42 | #include <linux/mutex.h> | |
43 | #include <linux/pci.h> | |
44 | #include <linux/slab.h> | |
45 | #include <linux/string.h> | |
46 | #include <linux/workqueue.h> | |
47 | #include <linux/zlib.h> | |
48 | #include <linux/hashtable.h> | |
49 | #include <linux/qed/qed_if.h> | |
c965db44 | 50 | #include "qed_debug.h" |
fe56b9e6 YM |
51 | #include "qed_hsi.h" |
52 | ||
25c089d7 | 53 | extern const struct qed_common_ops qed_common_ops_pass; |
5d24bcf1 TT |
54 | |
55 | #define QED_MAJOR_VERSION 8 | |
56 | #define QED_MINOR_VERSION 10 | |
57 | #define QED_REVISION_VERSION 10 | |
58 | #define QED_ENGINEERING_VERSION 21 | |
59 | ||
60 | #define QED_VERSION \ | |
61 | ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ | |
62 | (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) | |
63 | ||
64 | #define STORM_FW_VERSION \ | |
65 | ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ | |
66 | (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) | |
fe56b9e6 YM |
67 | |
68 | #define MAX_HWFNS_PER_DEVICE (4) | |
69 | #define NAME_SIZE 16 | |
70 | #define VER_SIZE 16 | |
71 | ||
bcd197c8 MC |
72 | #define QED_WFQ_UNIT 100 |
73 | ||
51ff1725 RA |
74 | #define QED_WID_SIZE (1024) |
75 | #define QED_PF_DEMS_SIZE (4) | |
76 | ||
fe56b9e6 YM |
77 | /* cau states */ |
78 | enum qed_coalescing_mode { | |
79 | QED_COAL_MODE_DISABLE, | |
80 | QED_COAL_MODE_ENABLE | |
81 | }; | |
82 | ||
83 | struct qed_eth_cb_ops; | |
84 | struct qed_dev_info; | |
6c754246 SRK |
85 | union qed_mcp_protocol_stats; |
86 | enum qed_mcp_protocol_type; | |
fe56b9e6 YM |
87 | |
88 | /* helpers */ | |
5d24bcf1 TT |
89 | #define QED_MFW_GET_FIELD(name, field) \ |
90 | (((name) & (field ## _MASK)) >> (field ## _SHIFT)) | |
91 | ||
92 | #define QED_MFW_SET_FIELD(name, field, value) \ | |
93 | do { \ | |
94 | (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \ | |
95 | (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ | |
96 | } while (0) | |
97 | ||
fe56b9e6 | 98 | static inline u32 qed_db_addr(u32 cid, u32 DEMS) |
51ff1725 RA |
99 | { |
100 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
101 | (cid * QED_PF_DEMS_SIZE); | |
102 | ||
103 | return db_addr; | |
104 | } | |
105 | ||
106 | static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) | |
fe56b9e6 YM |
107 | { |
108 | u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | | |
109 | FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); | |
110 | ||
111 | return db_addr; | |
112 | } | |
113 | ||
114 | #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ | |
115 | ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ | |
116 | ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) | |
117 | ||
118 | #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) | |
119 | ||
120 | #define D_TRINE(val, cond1, cond2, true1, true2, def) \ | |
121 | (val == (cond1) ? true1 : \ | |
122 | (val == (cond2) ? true2 : def)) | |
123 | ||
124 | /* forward */ | |
125 | struct qed_ptt_pool; | |
126 | struct qed_spq; | |
127 | struct qed_sb_info; | |
128 | struct qed_sb_attn_info; | |
129 | struct qed_cxt_mngr; | |
130 | struct qed_sb_sp_info; | |
0a7fb11c | 131 | struct qed_ll2_info; |
fe56b9e6 YM |
132 | struct qed_mcp_info; |
133 | ||
134 | struct qed_rt_data { | |
fc48b7a6 YM |
135 | u32 *init_val; |
136 | bool *b_valid; | |
fe56b9e6 YM |
137 | }; |
138 | ||
464f6645 MC |
139 | enum qed_tunn_mode { |
140 | QED_MODE_L2GENEVE_TUNN, | |
141 | QED_MODE_IPGENEVE_TUNN, | |
142 | QED_MODE_L2GRE_TUNN, | |
143 | QED_MODE_IPGRE_TUNN, | |
144 | QED_MODE_VXLAN_TUNN, | |
145 | }; | |
146 | ||
147 | enum qed_tunn_clss { | |
148 | QED_TUNN_CLSS_MAC_VLAN, | |
149 | QED_TUNN_CLSS_MAC_VNI, | |
150 | QED_TUNN_CLSS_INNER_MAC_VLAN, | |
151 | QED_TUNN_CLSS_INNER_MAC_VNI, | |
152 | MAX_QED_TUNN_CLSS, | |
153 | }; | |
154 | ||
155 | struct qed_tunn_start_params { | |
156 | unsigned long tunn_mode; | |
157 | u16 vxlan_udp_port; | |
158 | u16 geneve_udp_port; | |
159 | u8 update_vxlan_udp_port; | |
160 | u8 update_geneve_udp_port; | |
161 | u8 tunn_clss_vxlan; | |
162 | u8 tunn_clss_l2geneve; | |
163 | u8 tunn_clss_ipgeneve; | |
164 | u8 tunn_clss_l2gre; | |
165 | u8 tunn_clss_ipgre; | |
166 | }; | |
167 | ||
168 | struct qed_tunn_update_params { | |
169 | unsigned long tunn_mode_update_mask; | |
170 | unsigned long tunn_mode; | |
171 | u16 vxlan_udp_port; | |
172 | u16 geneve_udp_port; | |
173 | u8 update_rx_pf_clss; | |
174 | u8 update_tx_pf_clss; | |
175 | u8 update_vxlan_udp_port; | |
176 | u8 update_geneve_udp_port; | |
177 | u8 tunn_clss_vxlan; | |
178 | u8 tunn_clss_l2geneve; | |
179 | u8 tunn_clss_ipgeneve; | |
180 | u8 tunn_clss_l2gre; | |
181 | u8 tunn_clss_ipgre; | |
182 | }; | |
183 | ||
fe56b9e6 YM |
184 | /* The PCI personality is not quite synonymous to protocol ID: |
185 | * 1. All personalities need CORE connections | |
186 | * 2. The Ethernet personality may support also the RoCE protocol | |
187 | */ | |
188 | enum qed_pci_personality { | |
189 | QED_PCI_ETH, | |
1e128c81 | 190 | QED_PCI_FCOE, |
c5ac9319 YM |
191 | QED_PCI_ISCSI, |
192 | QED_PCI_ETH_ROCE, | |
fe56b9e6 YM |
193 | QED_PCI_DEFAULT /* default in shmem */ |
194 | }; | |
195 | ||
196 | /* All VFs are symmetric, all counters are PF + all VFs */ | |
197 | struct qed_qm_iids { | |
198 | u32 cids; | |
199 | u32 vf_cids; | |
200 | u32 tids; | |
201 | }; | |
202 | ||
2edbff8d TT |
203 | /* HW / FW resources, output of features supported below, most information |
204 | * is received from MFW. | |
205 | */ | |
206 | enum qed_resources { | |
fe56b9e6 | 207 | QED_SB, |
25c089d7 | 208 | QED_L2_QUEUE, |
fe56b9e6 | 209 | QED_VPORT, |
25c089d7 | 210 | QED_RSS_ENG, |
fe56b9e6 YM |
211 | QED_PQ, |
212 | QED_RL, | |
25c089d7 YM |
213 | QED_MAC, |
214 | QED_VLAN, | |
51ff1725 | 215 | QED_RDMA_CNQ_RAM, |
fe56b9e6 | 216 | QED_ILT, |
0a7fb11c | 217 | QED_LL2_QUEUE, |
2edbff8d | 218 | QED_CMDQS_CQS, |
51ff1725 | 219 | QED_RDMA_STATS_QUEUE, |
9c8517c4 | 220 | QED_BDQ, |
fe56b9e6 YM |
221 | QED_MAX_RESC, |
222 | }; | |
223 | ||
25c089d7 YM |
224 | enum QED_FEATURE { |
225 | QED_PF_L2_QUE, | |
32a47e72 | 226 | QED_VF, |
51ff1725 | 227 | QED_RDMA_CNQ, |
08737a3f | 228 | QED_ISCSI_CQ, |
1e128c81 | 229 | QED_FCOE_CQ, |
08737a3f | 230 | QED_VF_L2_QUE, |
25c089d7 YM |
231 | QED_MAX_FEATURES, |
232 | }; | |
233 | ||
cc875c2e YM |
234 | enum QED_PORT_MODE { |
235 | QED_PORT_MODE_DE_2X40G, | |
236 | QED_PORT_MODE_DE_2X50G, | |
237 | QED_PORT_MODE_DE_1X100G, | |
238 | QED_PORT_MODE_DE_4X10G_F, | |
239 | QED_PORT_MODE_DE_4X10G_E, | |
240 | QED_PORT_MODE_DE_4X20G, | |
241 | QED_PORT_MODE_DE_1X40G, | |
242 | QED_PORT_MODE_DE_2X25G, | |
9c79ddaa MY |
243 | QED_PORT_MODE_DE_1X25G, |
244 | QED_PORT_MODE_DE_4X25G, | |
245 | QED_PORT_MODE_DE_2X10G, | |
cc875c2e YM |
246 | }; |
247 | ||
fc48b7a6 YM |
248 | enum qed_dev_cap { |
249 | QED_DEV_CAP_ETH, | |
1e128c81 | 250 | QED_DEV_CAP_FCOE, |
c5ac9319 YM |
251 | QED_DEV_CAP_ISCSI, |
252 | QED_DEV_CAP_ROCE, | |
fc48b7a6 YM |
253 | }; |
254 | ||
14d39648 MY |
255 | enum qed_wol_support { |
256 | QED_WOL_SUPPORT_NONE, | |
257 | QED_WOL_SUPPORT_PME, | |
258 | }; | |
259 | ||
fe56b9e6 YM |
260 | struct qed_hw_info { |
261 | /* PCI personality */ | |
262 | enum qed_pci_personality personality; | |
263 | ||
264 | /* Resource Allocation scheme results */ | |
265 | u32 resc_start[QED_MAX_RESC]; | |
266 | u32 resc_num[QED_MAX_RESC]; | |
25c089d7 | 267 | u32 feat_num[QED_MAX_FEATURES]; |
fe56b9e6 YM |
268 | |
269 | #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) | |
270 | #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) | |
dbb799c3 YM |
271 | #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ |
272 | RESC_NUM(_p_hwfn, resc)) | |
fe56b9e6 YM |
273 | #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) |
274 | ||
b5a9ee7c AE |
275 | /* Amount of traffic classes HW supports */ |
276 | u8 num_hw_tc; | |
277 | ||
278 | /* Amount of TCs which should be active according to DCBx or upper | |
279 | * layer driver configuration. | |
280 | */ | |
281 | u8 num_active_tc; | |
fe56b9e6 | 282 | u8 offload_tc; |
fe56b9e6 YM |
283 | |
284 | u32 concrete_fid; | |
285 | u16 opaque_fid; | |
286 | u16 ovlan; | |
287 | u32 part_num[4]; | |
288 | ||
fe56b9e6 | 289 | unsigned char hw_mac_addr[ETH_ALEN]; |
1e128c81 AE |
290 | u64 node_wwn; |
291 | u64 port_wwn; | |
292 | ||
293 | u16 num_fcoe_conns; | |
fe56b9e6 YM |
294 | |
295 | struct qed_igu_info *p_igu_info; | |
296 | ||
297 | u32 port_mode; | |
298 | u32 hw_mode; | |
fc48b7a6 | 299 | unsigned long device_capabilities; |
0fefbfba | 300 | u16 mtu; |
14d39648 MY |
301 | |
302 | enum qed_wol_support b_wol_support; | |
fe56b9e6 YM |
303 | }; |
304 | ||
fe56b9e6 YM |
305 | /* maximun size of read/write commands (HW limit) */ |
306 | #define DMAE_MAX_RW_SIZE 0x2000 | |
307 | ||
308 | struct qed_dmae_info { | |
309 | /* Mutex for synchronizing access to functions */ | |
310 | struct mutex mutex; | |
311 | ||
312 | u8 channel; | |
313 | ||
314 | dma_addr_t completion_word_phys_addr; | |
315 | ||
316 | /* The memory location where the DMAE writes the completion | |
317 | * value when an operation is finished on this context. | |
318 | */ | |
319 | u32 *p_completion_word; | |
320 | ||
321 | dma_addr_t intermediate_buffer_phys_addr; | |
322 | ||
323 | /* An intermediate buffer for DMAE operations that use virtual | |
324 | * addresses - data is DMA'd to/from this buffer and then | |
325 | * memcpy'd to/from the virtual address | |
326 | */ | |
327 | u32 *p_intermediate_buffer; | |
328 | ||
329 | dma_addr_t dmae_cmd_phys_addr; | |
330 | struct dmae_cmd *p_dmae_cmd; | |
331 | }; | |
332 | ||
bcd197c8 MC |
333 | struct qed_wfq_data { |
334 | /* when feature is configured for at least 1 vport */ | |
335 | u32 min_speed; | |
336 | bool configured; | |
337 | }; | |
338 | ||
fe56b9e6 YM |
339 | struct qed_qm_info { |
340 | struct init_qm_pq_params *qm_pq_params; | |
341 | struct init_qm_vport_params *qm_vport_params; | |
342 | struct init_qm_port_params *qm_port_params; | |
343 | u16 start_pq; | |
344 | u8 start_vport; | |
b5a9ee7c AE |
345 | u16 pure_lb_pq; |
346 | u16 offload_pq; | |
347 | u16 low_latency_pq; | |
348 | u16 pure_ack_pq; | |
349 | u16 ooo_pq; | |
350 | u16 first_vf_pq; | |
351 | u16 first_mcos_pq; | |
352 | u16 first_rl_pq; | |
fe56b9e6 YM |
353 | u16 num_pqs; |
354 | u16 num_vf_pqs; | |
355 | u8 num_vports; | |
356 | u8 max_phys_tcs_per_port; | |
b5a9ee7c | 357 | u8 ooo_tc; |
fe56b9e6 YM |
358 | bool pf_rl_en; |
359 | bool pf_wfq_en; | |
360 | bool vport_rl_en; | |
361 | bool vport_wfq_en; | |
362 | u8 pf_wfq; | |
363 | u32 pf_rl; | |
bcd197c8 | 364 | struct qed_wfq_data *wfq_data; |
dbb799c3 | 365 | u8 num_pf_rls; |
fe56b9e6 YM |
366 | }; |
367 | ||
9df2ed04 MC |
368 | struct storm_stats { |
369 | u32 address; | |
370 | u32 len; | |
371 | }; | |
372 | ||
373 | struct qed_storm_stats { | |
374 | struct storm_stats mstats; | |
375 | struct storm_stats pstats; | |
376 | struct storm_stats tstats; | |
377 | struct storm_stats ustats; | |
378 | }; | |
379 | ||
fe56b9e6 | 380 | struct qed_fw_data { |
9df2ed04 | 381 | struct fw_ver_info *fw_ver_info; |
fe56b9e6 YM |
382 | const u8 *modes_tree_buf; |
383 | union init_op *init_ops; | |
384 | const u32 *arr_data; | |
385 | u32 init_ops_size; | |
386 | }; | |
387 | ||
5d24bcf1 TT |
388 | #define DRV_MODULE_VERSION \ |
389 | __stringify(QED_MAJOR_VERSION) "." \ | |
390 | __stringify(QED_MINOR_VERSION) "." \ | |
391 | __stringify(QED_REVISION_VERSION) "." \ | |
392 | __stringify(QED_ENGINEERING_VERSION) | |
393 | ||
fe56b9e6 YM |
394 | struct qed_simd_fp_handler { |
395 | void *token; | |
396 | void (*func)(void *); | |
397 | }; | |
398 | ||
399 | struct qed_hwfn { | |
400 | struct qed_dev *cdev; | |
401 | u8 my_id; /* ID inside the PF */ | |
402 | #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) | |
403 | u8 rel_pf_id; /* Relative to engine*/ | |
404 | u8 abs_pf_id; | |
9c79ddaa MY |
405 | #define QED_PATH_ID(_p_hwfn) \ |
406 | (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) | |
fe56b9e6 YM |
407 | u8 port_id; |
408 | bool b_active; | |
409 | ||
410 | u32 dp_module; | |
411 | u8 dp_level; | |
412 | char name[NAME_SIZE]; | |
413 | ||
414 | bool first_on_engine; | |
415 | bool hw_init_done; | |
416 | ||
1408cc1f | 417 | u8 num_funcs_on_engine; |
dbb799c3 | 418 | u8 enabled_func_idx; |
1408cc1f | 419 | |
fe56b9e6 YM |
420 | /* BAR access */ |
421 | void __iomem *regview; | |
422 | void __iomem *doorbells; | |
423 | u64 db_phys_addr; | |
424 | unsigned long db_size; | |
425 | ||
426 | /* PTT pool */ | |
427 | struct qed_ptt_pool *p_ptt_pool; | |
428 | ||
429 | /* HW info */ | |
430 | struct qed_hw_info hw_info; | |
431 | ||
432 | /* rt_array (for init-tool) */ | |
fc48b7a6 | 433 | struct qed_rt_data rt_data; |
fe56b9e6 YM |
434 | |
435 | /* SPQ */ | |
436 | struct qed_spq *p_spq; | |
437 | ||
438 | /* EQ */ | |
439 | struct qed_eq *p_eq; | |
440 | ||
441 | /* Consolidate Q*/ | |
442 | struct qed_consq *p_consq; | |
443 | ||
444 | /* Slow-Path definitions */ | |
445 | struct tasklet_struct *sp_dpc; | |
446 | bool b_sp_dpc_enabled; | |
447 | ||
448 | struct qed_ptt *p_main_ptt; | |
449 | struct qed_ptt *p_dpc_ptt; | |
450 | ||
451 | struct qed_sb_sp_info *p_sp_sb; | |
452 | struct qed_sb_attn_info *p_sb_attn; | |
453 | ||
454 | /* Protocol related */ | |
0a7fb11c YM |
455 | bool using_ll2; |
456 | struct qed_ll2_info *p_ll2_info; | |
1d6cff4f | 457 | struct qed_ooo_info *p_ooo_info; |
51ff1725 | 458 | struct qed_rdma_info *p_rdma_info; |
fc831825 | 459 | struct qed_iscsi_info *p_iscsi_info; |
1e128c81 | 460 | struct qed_fcoe_info *p_fcoe_info; |
fe56b9e6 YM |
461 | struct qed_pf_params pf_params; |
462 | ||
dbb799c3 YM |
463 | bool b_rdma_enabled_in_prs; |
464 | u32 rdma_prs_search_reg; | |
465 | ||
fe56b9e6 YM |
466 | /* Array of sb_info of all status blocks */ |
467 | struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; | |
468 | u16 num_sbs; | |
469 | ||
470 | struct qed_cxt_mngr *p_cxt_mngr; | |
471 | ||
472 | /* Flag indicating whether interrupts are enabled or not*/ | |
473 | bool b_int_enabled; | |
8f16bc97 | 474 | bool b_int_requested; |
fe56b9e6 | 475 | |
fc916ff2 SRK |
476 | /* True if the driver requests for the link */ |
477 | bool b_drv_link_init; | |
478 | ||
1408cc1f | 479 | struct qed_vf_iov *vf_iov_info; |
32a47e72 | 480 | struct qed_pf_iov *pf_iov_info; |
fe56b9e6 YM |
481 | struct qed_mcp_info *mcp_info; |
482 | ||
39651abd SRK |
483 | struct qed_dcbx_info *p_dcbx_info; |
484 | ||
fe56b9e6 YM |
485 | struct qed_dmae_info dmae_info; |
486 | ||
487 | /* QM init */ | |
488 | struct qed_qm_info qm_info; | |
9df2ed04 | 489 | struct qed_storm_stats storm_stats; |
fe56b9e6 YM |
490 | |
491 | /* Buffer for unzipping firmware data */ | |
492 | void *unzip_buf; | |
493 | ||
c965db44 TT |
494 | struct dbg_tools_data dbg_info; |
495 | ||
51ff1725 RA |
496 | /* PWM region specific data */ |
497 | u32 dpi_size; | |
498 | u32 dpi_count; | |
499 | ||
500 | /* This is used to calculate the doorbell address */ | |
501 | u32 dpi_start_offset; | |
502 | ||
503 | /* If one of the following is set then EDPM shouldn't be used */ | |
504 | u8 dcbx_no_edpm; | |
505 | u8 db_bar_no_edpm; | |
506 | ||
c78c70fa SRK |
507 | /* p_ptp_ptt is valid for leading HWFN only */ |
508 | struct qed_ptt *p_ptp_ptt; | |
fe56b9e6 YM |
509 | struct qed_simd_fp_handler simd_proto_handler[64]; |
510 | ||
37bff2b9 YM |
511 | #ifdef CONFIG_QED_SRIOV |
512 | struct workqueue_struct *iov_wq; | |
513 | struct delayed_work iov_task; | |
514 | unsigned long iov_task_flags; | |
515 | #endif | |
516 | ||
fe56b9e6 | 517 | struct z_stream_s *stream; |
abd49676 | 518 | struct qed_roce_ll2_info *ll2; |
fe56b9e6 YM |
519 | }; |
520 | ||
521 | struct pci_params { | |
522 | int pm_cap; | |
523 | ||
524 | unsigned long mem_start; | |
525 | unsigned long mem_end; | |
526 | unsigned int irq; | |
527 | u8 pf_num; | |
528 | }; | |
529 | ||
530 | struct qed_int_param { | |
531 | u32 int_mode; | |
532 | u8 num_vectors; | |
533 | u8 min_msix_cnt; /* for minimal functionality */ | |
534 | }; | |
535 | ||
536 | struct qed_int_params { | |
537 | struct qed_int_param in; | |
538 | struct qed_int_param out; | |
539 | struct msix_entry *msix_table; | |
540 | bool fp_initialized; | |
541 | u8 fp_msix_base; | |
542 | u8 fp_msix_cnt; | |
51ff1725 RA |
543 | u8 rdma_msix_base; |
544 | u8 rdma_msix_cnt; | |
fe56b9e6 YM |
545 | }; |
546 | ||
c965db44 TT |
547 | struct qed_dbg_feature { |
548 | struct dentry *dentry; | |
549 | u8 *dump_buf; | |
550 | u32 buf_size; | |
551 | u32 dumped_dwords; | |
552 | }; | |
553 | ||
554 | struct qed_dbg_params { | |
555 | struct qed_dbg_feature features[DBG_FEATURE_NUM]; | |
556 | u8 engine_for_debug; | |
557 | bool print_data; | |
558 | }; | |
559 | ||
fe56b9e6 YM |
560 | struct qed_dev { |
561 | u32 dp_module; | |
562 | u8 dp_level; | |
563 | char name[NAME_SIZE]; | |
564 | ||
9c79ddaa | 565 | enum qed_dev_type type; |
fc48b7a6 YM |
566 | /* Translate type/revision combo into the proper conditions */ |
567 | #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) | |
568 | #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ | |
569 | CHIP_REV_IS_A0(dev)) | |
570 | #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ | |
571 | CHIP_REV_IS_B0(dev)) | |
c965db44 TT |
572 | #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) |
573 | #define QED_IS_K2(dev) QED_IS_AH(dev) | |
fc48b7a6 YM |
574 | |
575 | #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ | |
576 | QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) | |
577 | ||
578 | u16 vendor_id; | |
579 | u16 device_id; | |
9c79ddaa MY |
580 | #define QED_DEV_ID_MASK 0xff00 |
581 | #define QED_DEV_ID_MASK_BB 0x1600 | |
582 | #define QED_DEV_ID_MASK_AH 0x8000 | |
fe56b9e6 YM |
583 | |
584 | u16 chip_num; | |
585 | #define CHIP_NUM_MASK 0xffff | |
586 | #define CHIP_NUM_SHIFT 16 | |
587 | ||
588 | u16 chip_rev; | |
589 | #define CHIP_REV_MASK 0xf | |
590 | #define CHIP_REV_SHIFT 12 | |
fc48b7a6 YM |
591 | #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) |
592 | #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) | |
fe56b9e6 YM |
593 | |
594 | u16 chip_metal; | |
595 | #define CHIP_METAL_MASK 0xff | |
596 | #define CHIP_METAL_SHIFT 4 | |
597 | ||
598 | u16 chip_bond_id; | |
599 | #define CHIP_BOND_ID_MASK 0xf | |
600 | #define CHIP_BOND_ID_SHIFT 0 | |
601 | ||
602 | u8 num_engines; | |
603 | u8 num_ports_in_engines; | |
604 | u8 num_funcs_in_port; | |
605 | ||
606 | u8 path_id; | |
fc48b7a6 YM |
607 | enum qed_mf_mode mf_mode; |
608 | #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) | |
609 | #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) | |
610 | #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) | |
fe56b9e6 YM |
611 | |
612 | int pcie_width; | |
613 | int pcie_speed; | |
614 | u8 ver_str[VER_SIZE]; | |
615 | ||
616 | /* Add MF related configuration */ | |
617 | u8 mcp_rev; | |
618 | u8 boot_mode; | |
619 | ||
14d39648 MY |
620 | /* WoL related configurations */ |
621 | u8 wol_config; | |
622 | u8 wol_mac[ETH_ALEN]; | |
fe56b9e6 YM |
623 | |
624 | u32 int_mode; | |
625 | enum qed_coalescing_mode int_coalescing_mode; | |
51d99880 SRK |
626 | u16 rx_coalesce_usecs; |
627 | u16 tx_coalesce_usecs; | |
fe56b9e6 YM |
628 | |
629 | /* Start Bar offset of first hwfn */ | |
630 | void __iomem *regview; | |
631 | void __iomem *doorbells; | |
632 | u64 db_phys_addr; | |
633 | unsigned long db_size; | |
634 | ||
635 | /* PCI */ | |
636 | u8 cache_shift; | |
637 | ||
638 | /* Init */ | |
639 | const struct iro *iro_arr; | |
640 | #define IRO (p_hwfn->cdev->iro_arr) | |
641 | ||
642 | /* HW functions */ | |
643 | u8 num_hwfns; | |
644 | struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; | |
645 | ||
32a47e72 YM |
646 | /* SRIOV */ |
647 | struct qed_hw_sriov_info *p_iov_info; | |
648 | #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) | |
649 | ||
464f6645 | 650 | unsigned long tunn_mode; |
1408cc1f YM |
651 | |
652 | bool b_is_vf; | |
fe56b9e6 | 653 | u32 drv_type; |
fe56b9e6 YM |
654 | struct qed_eth_stats *reset_stats; |
655 | struct qed_fw_data *fw_data; | |
656 | ||
657 | u32 mcp_nvm_resp; | |
658 | ||
659 | /* Linux specific here */ | |
660 | struct qede_dev *edev; | |
661 | struct pci_dev *pdev; | |
fc831825 YM |
662 | u32 flags; |
663 | #define QED_FLAG_STORAGE_STARTED (BIT(0)) | |
fe56b9e6 YM |
664 | int msg_enable; |
665 | ||
666 | struct pci_params pci_params; | |
667 | ||
668 | struct qed_int_params int_params; | |
669 | ||
670 | u8 protocol; | |
671 | #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) | |
1e128c81 | 672 | #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) |
fe56b9e6 | 673 | |
cc875c2e YM |
674 | /* Callbacks to protocol driver */ |
675 | union { | |
676 | struct qed_common_cb_ops *common; | |
677 | struct qed_eth_cb_ops *eth; | |
1e128c81 | 678 | struct qed_fcoe_cb_ops *fcoe; |
fc831825 | 679 | struct qed_iscsi_cb_ops *iscsi; |
cc875c2e YM |
680 | } protocol_ops; |
681 | void *ops_cookie; | |
682 | ||
c965db44 TT |
683 | struct qed_dbg_params dbg_params; |
684 | ||
0a7fb11c YM |
685 | #ifdef CONFIG_QED_LL2 |
686 | struct qed_cb_ll2_info *ll2; | |
687 | u8 ll2_mac_address[ETH_ALEN]; | |
688 | #endif | |
fc831825 | 689 | DECLARE_HASHTABLE(connections, 10); |
fe56b9e6 | 690 | const struct firmware *firmware; |
51ff1725 RA |
691 | |
692 | u32 rdma_max_sge; | |
693 | u32 rdma_max_inline; | |
694 | u32 rdma_max_srq_sge; | |
fe56b9e6 YM |
695 | }; |
696 | ||
9c79ddaa MY |
697 | #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ |
698 | : MAX_NUM_VFS_K2) | |
699 | #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ | |
700 | : MAX_NUM_L2_QUEUES_K2) | |
701 | #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ | |
702 | : MAX_NUM_PORTS_K2) | |
703 | #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ | |
704 | : MAX_SB_PER_PATH_K2) | |
705 | #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ | |
706 | : MAX_NUM_PFS_K2) | |
fe56b9e6 YM |
707 | |
708 | /** | |
709 | * @brief qed_concrete_to_sw_fid - get the sw function id from | |
710 | * the concrete value. | |
711 | * | |
712 | * @param concrete_fid | |
713 | * | |
714 | * @return inline u8 | |
715 | */ | |
716 | static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, | |
717 | u32 concrete_fid) | |
718 | { | |
4870e704 | 719 | u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); |
fe56b9e6 | 720 | u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); |
4870e704 YM |
721 | u8 vf_valid = GET_FIELD(concrete_fid, |
722 | PXP_CONCRETE_FID_VFVALID); | |
723 | u8 sw_fid; | |
fe56b9e6 | 724 | |
4870e704 YM |
725 | if (vf_valid) |
726 | sw_fid = vfid + MAX_NUM_PFS; | |
727 | else | |
728 | sw_fid = pfid; | |
729 | ||
730 | return sw_fid; | |
fe56b9e6 YM |
731 | } |
732 | ||
733 | #define PURE_LB_TC 8 | |
dbb799c3 | 734 | #define OOO_LB_TC 9 |
fe56b9e6 | 735 | |
733def6a | 736 | int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); |
6f437d43 MY |
737 | void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, |
738 | struct qed_ptt *p_ptt, | |
739 | u32 min_pf_rate); | |
bcd197c8 | 740 | |
733def6a | 741 | void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); |
9c79ddaa | 742 | int qed_device_num_engines(struct qed_dev *cdev); |
fe56b9e6 | 743 | |
b5a9ee7c AE |
744 | #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) |
745 | ||
746 | /* Flags for indication of required queues */ | |
747 | #define PQ_FLAGS_RLS (BIT(0)) | |
748 | #define PQ_FLAGS_MCOS (BIT(1)) | |
749 | #define PQ_FLAGS_LB (BIT(2)) | |
750 | #define PQ_FLAGS_OOO (BIT(3)) | |
751 | #define PQ_FLAGS_ACK (BIT(4)) | |
752 | #define PQ_FLAGS_OFLD (BIT(5)) | |
753 | #define PQ_FLAGS_VFS (BIT(6)) | |
754 | #define PQ_FLAGS_LLT (BIT(7)) | |
755 | ||
756 | /* physical queue index for cm context intialization */ | |
757 | u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); | |
758 | u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); | |
759 | u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); | |
760 | ||
761 | #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) | |
762 | ||
fe56b9e6 YM |
763 | /* Other Linux specific common definitions */ |
764 | #define DP_NAME(cdev) ((cdev)->name) | |
765 | ||
766 | #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ | |
767 | (cdev->regview) + \ | |
768 | (offset)) | |
769 | ||
770 | #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) | |
771 | #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) | |
772 | #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) | |
773 | ||
774 | #define DOORBELL(cdev, db_addr, val) \ | |
775 | writel((u32)val, (void __iomem *)((u8 __iomem *)\ | |
776 | (cdev->doorbells) + (db_addr))) | |
777 | ||
778 | /* Prototypes */ | |
779 | int qed_fill_dev_info(struct qed_dev *cdev, | |
780 | struct qed_dev_info *dev_info); | |
cc875c2e | 781 | void qed_link_update(struct qed_hwfn *hwfn); |
fe56b9e6 YM |
782 | u32 qed_unzip_data(struct qed_hwfn *p_hwfn, |
783 | u32 input_len, u8 *input_buf, | |
784 | u32 max_size, u8 *unzip_buf); | |
6c754246 SRK |
785 | void qed_get_protocol_stats(struct qed_dev *cdev, |
786 | enum qed_mcp_protocol_type type, | |
787 | union qed_mcp_protocol_stats *stats); | |
8f16bc97 | 788 | int qed_slowpath_irq_req(struct qed_hwfn *hwfn); |
1226337a | 789 | void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); |
8f16bc97 | 790 | |
fe56b9e6 | 791 | #endif /* _QED_H */ |