[linux-2.6-block.git] / drivers / net / ethernet / qlogic / qed / qed.h

/* QLogic qed NIC Driver
 * Copyright (c) 2015 QLogic Corporation
 *
 * This software is available under the terms of the GNU General Public License
 * (GPL) Version 2, available from the file COPYING in the main directory of
 * this source tree.
 */

#ifndef _QED_H
#define _QED_H

#include <linux/types.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/workqueue.h>
#include <linux/zlib.h>
#include <linux/hashtable.h>
#include <linux/qed/qed_if.h>
#include "qed_hsi.h"

extern const struct qed_common_ops qed_common_ops_pass;
#define DRV_MODULE_VERSION "8.7.1.20"

#define MAX_HWFNS_PER_DEVICE    (4)
#define NAME_SIZE 16
#define VER_SIZE 16

/* cau states */
enum qed_coalescing_mode {
	QED_COAL_MODE_DISABLE,
	QED_COAL_MODE_ENABLE
};

struct qed_eth_cb_ops;
struct qed_dev_info;

/* helpers */
static inline u32 qed_db_addr(u32 cid, u32 DEMS)
{
	u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
		      FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);

	return db_addr;
}

#define ALIGNED_TYPE_SIZE(type_name, p_hwfn)				     \
	((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
	 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))

#define for_each_hwfn(cdev, i)  for (i = 0; i < cdev->num_hwfns; i++)

#define D_TRINE(val, cond1, cond2, true1, true2, def) \
	(val == (cond1) ? true1 :		      \
	 (val == (cond2) ? true2 : def))

/* forward */
struct qed_ptt_pool;
struct qed_spq;
struct qed_sb_info;
struct qed_sb_attn_info;
struct qed_cxt_mngr;
struct qed_sb_sp_info;
struct qed_mcp_info;

struct qed_rt_data {
	u32	*init_val;
	bool	*b_valid;
};

enum qed_tunn_mode {
	QED_MODE_L2GENEVE_TUNN,
	QED_MODE_IPGENEVE_TUNN,
	QED_MODE_L2GRE_TUNN,
	QED_MODE_IPGRE_TUNN,
	QED_MODE_VXLAN_TUNN,
};

enum qed_tunn_clss {
	QED_TUNN_CLSS_MAC_VLAN,
	QED_TUNN_CLSS_MAC_VNI,
	QED_TUNN_CLSS_INNER_MAC_VLAN,
	QED_TUNN_CLSS_INNER_MAC_VNI,
	MAX_QED_TUNN_CLSS,
};

struct qed_tunn_start_params {
	unsigned long	tunn_mode;
	u16		vxlan_udp_port;
	u16		geneve_udp_port;
	u8		update_vxlan_udp_port;
	u8		update_geneve_udp_port;
	u8		tunn_clss_vxlan;
	u8		tunn_clss_l2geneve;
	u8		tunn_clss_ipgeneve;
	u8		tunn_clss_l2gre;
	u8		tunn_clss_ipgre;
};

struct qed_tunn_update_params {
	unsigned long	tunn_mode_update_mask;
	unsigned long	tunn_mode;
	u16		vxlan_udp_port;
	u16		geneve_udp_port;
	u8		update_rx_pf_clss;
	u8		update_tx_pf_clss;
	u8		update_vxlan_udp_port;
	u8		update_geneve_udp_port;
	u8		tunn_clss_vxlan;
	u8		tunn_clss_l2geneve;
	u8		tunn_clss_ipgeneve;
	u8		tunn_clss_l2gre;
	u8		tunn_clss_ipgre;
};

/* The PCI personality is not quite synonymous to protocol ID:
 * 1. All personalities need CORE connections
 * 2. The Ethernet personality may support also the RoCE protocol
 */
enum qed_pci_personality {
	QED_PCI_ETH,
	QED_PCI_DEFAULT /* default in shmem */
};

/* All VFs are symmetric, all counters are PF + all VFs */
struct qed_qm_iids {
	u32 cids;
	u32 vf_cids;
	u32 tids;
};

enum QED_RESOURCES {
	QED_SB,
	QED_L2_QUEUE,
	QED_VPORT,
	QED_RSS_ENG,
	QED_PQ,
	QED_RL,
	QED_MAC,
	QED_VLAN,
	QED_ILT,
	QED_MAX_RESC,
};

enum QED_FEATURE {
	QED_PF_L2_QUE,
	QED_MAX_FEATURES,
};

enum QED_PORT_MODE {
	QED_PORT_MODE_DE_2X40G,
	QED_PORT_MODE_DE_2X50G,
	QED_PORT_MODE_DE_1X100G,
	QED_PORT_MODE_DE_4X10G_F,
	QED_PORT_MODE_DE_4X10G_E,
	QED_PORT_MODE_DE_4X20G,
	QED_PORT_MODE_DE_1X40G,
	QED_PORT_MODE_DE_2X25G,
	QED_PORT_MODE_DE_1X25G
};

enum qed_dev_cap {
	QED_DEV_CAP_ETH,
};

struct qed_hw_info {
	/* PCI personality */
	enum qed_pci_personality	personality;

	/* Resource Allocation scheme results */
	u32				resc_start[QED_MAX_RESC];
	u32				resc_num[QED_MAX_RESC];
	u32				feat_num[QED_MAX_FEATURES];

#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])

	u8				num_tc;
	u8				offload_tc;
	u8				non_offload_tc;

	u32				concrete_fid;
	u16				opaque_fid;
	u16				ovlan;
	u32				part_num[4];

	unsigned char			hw_mac_addr[ETH_ALEN];

	struct qed_igu_info		*p_igu_info;

	u32				port_mode;
	u32				hw_mode;
	unsigned long		device_capabilities;
};

struct qed_hw_cid_data {
	u32	cid;
	bool	b_cid_allocated;

	/* Additional identifiers */
	u16	opaque_fid;
	u8	vport_id;
};

/* maximun size of read/write commands (HW limit) */
#define DMAE_MAX_RW_SIZE        0x2000

struct qed_dmae_info {
	/* Mutex for synchronizing access to functions */
	struct mutex	mutex;

	u8		channel;

	dma_addr_t	completion_word_phys_addr;

	/* The memory location where the DMAE writes the completion
	 * value when an operation is finished on this context.
	 */
	u32		*p_completion_word;

	dma_addr_t	intermediate_buffer_phys_addr;

	/* An intermediate buffer for DMAE operations that use virtual
	 * addresses - data is DMA'd to/from this buffer and then
	 * memcpy'd to/from the virtual address
	 */
	u32		*p_intermediate_buffer;

	dma_addr_t	dmae_cmd_phys_addr;
	struct dmae_cmd *p_dmae_cmd;
};

struct qed_qm_info {
	struct init_qm_pq_params	*qm_pq_params;
	struct init_qm_vport_params	*qm_vport_params;
	struct init_qm_port_params	*qm_port_params;
	u16				start_pq;
	u8				start_vport;
	u8				pure_lb_pq;
	u8				offload_pq;
	u8				pure_ack_pq;
	u8				vf_queues_offset;
	u16				num_pqs;
	u16				num_vf_pqs;
	u8				num_vports;
	u8				max_phys_tcs_per_port;
	bool				pf_rl_en;
	bool				pf_wfq_en;
	bool				vport_rl_en;
	bool				vport_wfq_en;
	u8				pf_wfq;
	u32				pf_rl;
};

struct storm_stats {
	u32     address;
	u32     len;
};

struct qed_storm_stats {
	struct storm_stats mstats;
	struct storm_stats pstats;
	struct storm_stats tstats;
	struct storm_stats ustats;
};

struct qed_fw_data {
	struct fw_ver_info	*fw_ver_info;
	const u8		*modes_tree_buf;
	union init_op		*init_ops;
	const u32		*arr_data;
	u32			init_ops_size;
};

struct qed_simd_fp_handler {
	void	*token;
	void	(*func)(void *);
};

struct qed_hwfn {
	struct qed_dev			*cdev;
	u8				my_id;          /* ID inside the PF */
#define IS_LEAD_HWFN(edev)              (!((edev)->my_id))
	u8				rel_pf_id;      /* Relative to engine*/
	u8				abs_pf_id;
#define QED_PATH_ID(_p_hwfn)		((_p_hwfn)->abs_pf_id & 1)
	u8				port_id;
	bool				b_active;

	u32				dp_module;
	u8				dp_level;
	char				name[NAME_SIZE];

	bool				first_on_engine;
	bool				hw_init_done;

	/* BAR access */
	void __iomem			*regview;
	void __iomem			*doorbells;
	u64				db_phys_addr;
	unsigned long			db_size;

	/* PTT pool */
	struct qed_ptt_pool		*p_ptt_pool;

	/* HW info */
	struct qed_hw_info		hw_info;

	/* rt_array (for init-tool) */
	struct qed_rt_data		rt_data;

	/* SPQ */
	struct qed_spq			*p_spq;

	/* EQ */
	struct qed_eq			*p_eq;

	/* Consolidate Q*/
	struct qed_consq		*p_consq;

	/* Slow-Path definitions */
	struct tasklet_struct		*sp_dpc;
	bool				b_sp_dpc_enabled;

	struct qed_ptt			*p_main_ptt;
	struct qed_ptt			*p_dpc_ptt;

	struct qed_sb_sp_info		*p_sp_sb;
	struct qed_sb_attn_info		*p_sb_attn;

	/* Protocol related */
	struct qed_pf_params		pf_params;

	/* Array of sb_info of all status blocks */
	struct qed_sb_info		*sbs_info[MAX_SB_PER_PF_MIMD];
	u16				num_sbs;

	struct qed_cxt_mngr		*p_cxt_mngr;

	/* Flag indicating whether interrupts are enabled or not*/
	bool				b_int_enabled;
	bool				b_int_requested;

	/* True if the driver requests for the link */
	bool				b_drv_link_init;

	struct qed_mcp_info		*mcp_info;

	struct qed_hw_cid_data		*p_tx_cids;
	struct qed_hw_cid_data		*p_rx_cids;

	struct qed_dmae_info		dmae_info;

	/* QM init */
	struct qed_qm_info		qm_info;
	struct qed_storm_stats		storm_stats;

	/* Buffer for unzipping firmware data */
	void				*unzip_buf;

	struct qed_simd_fp_handler	simd_proto_handler[64];

	struct z_stream_s		*stream;
};

struct pci_params {
	int		pm_cap;

	unsigned long	mem_start;
	unsigned long	mem_end;
	unsigned int	irq;
	u8		pf_num;
};

struct qed_int_param {
	u32	int_mode;
	u8	num_vectors;
	u8	min_msix_cnt; /* for minimal functionality */
};

struct qed_int_params {
	struct qed_int_param	in;
	struct qed_int_param	out;
	struct msix_entry	*msix_table;
	bool			fp_initialized;
	u8			fp_msix_base;
	u8			fp_msix_cnt;
};

struct qed_dev {
	u32	dp_module;
	u8	dp_level;
	char	name[NAME_SIZE];

	u8	type;
#define QED_DEV_TYPE_BB (0 << 0)
#define QED_DEV_TYPE_AH BIT(0)
/* Translate type/revision combo into the proper conditions */
#define QED_IS_BB(dev)  ((dev)->type == QED_DEV_TYPE_BB)
#define QED_IS_BB_A0(dev)       (QED_IS_BB(dev) && \
				 CHIP_REV_IS_A0(dev))
#define QED_IS_BB_B0(dev)       (QED_IS_BB(dev) && \
				 CHIP_REV_IS_B0(dev))

#define QED_GET_TYPE(dev)       (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
				 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)

	u16	vendor_id;
	u16	device_id;

	u16	chip_num;
#define CHIP_NUM_MASK                   0xffff
#define CHIP_NUM_SHIFT                  16

	u16	chip_rev;
#define CHIP_REV_MASK                   0xf
#define CHIP_REV_SHIFT                  12
#define CHIP_REV_IS_A0(_cdev)   (!(_cdev)->chip_rev)
#define CHIP_REV_IS_B0(_cdev)   ((_cdev)->chip_rev == 1)

	u16				chip_metal;
#define CHIP_METAL_MASK                 0xff
#define CHIP_METAL_SHIFT                4

	u16				chip_bond_id;
#define CHIP_BOND_ID_MASK               0xf
#define CHIP_BOND_ID_SHIFT              0

	u8				num_engines;
	u8				num_ports_in_engines;
	u8				num_funcs_in_port;

	u8				path_id;
	enum qed_mf_mode		mf_mode;
#define IS_MF_DEFAULT(_p_hwfn)  (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
#define IS_MF_SI(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
#define IS_MF_SD(_p_hwfn)       (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)

	int				pcie_width;
	int				pcie_speed;
	u8				ver_str[VER_SIZE];

	/* Add MF related configuration */
	u8				mcp_rev;
	u8				boot_mode;

	u8				wol;

	u32				int_mode;
	enum qed_coalescing_mode	int_coalescing_mode;
	u8				rx_coalesce_usecs;
	u8				tx_coalesce_usecs;

	/* Start Bar offset of first hwfn */
	void __iomem			*regview;
	void __iomem			*doorbells;
	u64				db_phys_addr;
	unsigned long			db_size;

	/* PCI */
	u8				cache_shift;

	/* Init */
	const struct iro		*iro_arr;
#define IRO (p_hwfn->cdev->iro_arr)

	/* HW functions */
	u8				num_hwfns;
	struct qed_hwfn			hwfns[MAX_HWFNS_PER_DEVICE];

	unsigned long			tunn_mode;
	u32				drv_type;

	struct qed_eth_stats		*reset_stats;
	struct qed_fw_data		*fw_data;

	u32				mcp_nvm_resp;

	/* Linux specific here */
	struct  qede_dev		*edev;
	struct  pci_dev			*pdev;
	int				msg_enable;

	struct pci_params		pci_params;

	struct qed_int_params		int_params;

	u8				protocol;
#define IS_QED_ETH_IF(cdev)     ((cdev)->protocol == QED_PROTOCOL_ETH)

	/* Callbacks to protocol driver */
	union {
		struct qed_common_cb_ops	*common;
		struct qed_eth_cb_ops		*eth;
	} protocol_ops;
	void				*ops_cookie;

	const struct firmware		*firmware;
};

#define NUM_OF_SBS(dev)         MAX_SB_PER_PATH_BB
#define NUM_OF_ENG_PFS(dev)     MAX_NUM_PFS_BB

/**
 * @brief qed_concrete_to_sw_fid - get the sw function id from
 *        the concrete value.
 *
 * @param concrete_fid
 *
 * @return inline u8
 */
static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
					u32 concrete_fid)
{
	u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);

	return pfid;
}

#define PURE_LB_TC 8

#define QED_LEADING_HWFN(dev)   (&dev->hwfns[0])

/* Other Linux specific common definitions */
#define DP_NAME(cdev) ((cdev)->name)

#define REG_ADDR(cdev, offset)          (void __iomem *)((u8 __iomem *)\
						(cdev->regview) + \
							 (offset))

#define REG_RD(cdev, offset)            readl(REG_ADDR(cdev, offset))
#define REG_WR(cdev, offset, val)       writel((u32)val, REG_ADDR(cdev, offset))
#define REG_WR16(cdev, offset, val)     writew((u16)val, REG_ADDR(cdev, offset))

#define DOORBELL(cdev, db_addr, val)			 \
	writel((u32)val, (void __iomem *)((u8 __iomem *)\
					  (cdev->doorbells) + (db_addr)))

/* Prototypes */
int qed_fill_dev_info(struct qed_dev *cdev,
		      struct qed_dev_info *dev_info);
void qed_link_update(struct qed_hwfn *hwfn);
u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
		   u32 input_len, u8 *input_buf,
		   u32 max_size, u8 *unzip_buf);

int qed_slowpath_irq_req(struct qed_hwfn *hwfn);

#endif /* _QED_H */
Commit	Line	Data
fe56b9e6 YM	1	/* QLogic qed NIC Driver
	2	* Copyright (c) 2015 QLogic Corporation
	3	*
	4	* This software is available under the terms of the GNU General Public License
	5	* (GPL) Version 2, available from the file COPYING in the main directory of
	6	* this source tree.
	7	*/
	8
	9	#ifndef _QED_H
	10	#define _QED_H
	11
	12	#include <linux/types.h>
	13	#include <linux/io.h>
	14	#include <linux/delay.h>
	15	#include <linux/firmware.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/list.h>
	18	#include <linux/mutex.h>
	19	#include <linux/pci.h>
	20	#include <linux/slab.h>
	21	#include <linux/string.h>
	22	#include <linux/workqueue.h>
	23	#include <linux/zlib.h>
	24	#include <linux/hashtable.h>
	25	#include <linux/qed/qed_if.h>
	26	#include "qed_hsi.h"
	27
25c089d7	28	extern const struct qed_common_ops qed_common_ops_pass;
7c2d7d74	29	#define DRV_MODULE_VERSION "8.7.1.20"
fe56b9e6 YM	30
	31	#define MAX_HWFNS_PER_DEVICE (4)
	32	#define NAME_SIZE 16
	33	#define VER_SIZE 16
	34
	35	/* cau states */
	36	enum qed_coalescing_mode {
	37	QED_COAL_MODE_DISABLE,
	38	QED_COAL_MODE_ENABLE
	39	};
	40
	41	struct qed_eth_cb_ops;
	42	struct qed_dev_info;
	43
	44	/* helpers */
	45	static inline u32 qed_db_addr(u32 cid, u32 DEMS)
	46	{
	47	u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) \|
	48	FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
	49
	50	return db_addr;
	51	}
	52
	53	#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
	54	((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
	55	~((1 << (p_hwfn->cdev->cache_shift)) - 1))
	56
	57	#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
	58
	59	#define D_TRINE(val, cond1, cond2, true1, true2, def) \
	60	(val == (cond1) ? true1 : \
	61	(val == (cond2) ? true2 : def))
	62
	63	/* forward */
	64	struct qed_ptt_pool;
	65	struct qed_spq;
	66	struct qed_sb_info;
	67	struct qed_sb_attn_info;
	68	struct qed_cxt_mngr;
	69	struct qed_sb_sp_info;
	70	struct qed_mcp_info;
	71
	72	struct qed_rt_data {
fc48b7a6 YM	73	u32 *init_val;
fc48b7a6 YM	74	bool *b_valid;
fe56b9e6 YM	75	};
fe56b9e6 YM	76
464f6645 MC	77	enum qed_tunn_mode {
	78	QED_MODE_L2GENEVE_TUNN,
	79	QED_MODE_IPGENEVE_TUNN,
	80	QED_MODE_L2GRE_TUNN,
	81	QED_MODE_IPGRE_TUNN,
	82	QED_MODE_VXLAN_TUNN,
	83	};
	84
	85	enum qed_tunn_clss {
	86	QED_TUNN_CLSS_MAC_VLAN,
	87	QED_TUNN_CLSS_MAC_VNI,
	88	QED_TUNN_CLSS_INNER_MAC_VLAN,
	89	QED_TUNN_CLSS_INNER_MAC_VNI,
	90	MAX_QED_TUNN_CLSS,
	91	};
	92
	93	struct qed_tunn_start_params {
	94	unsigned long tunn_mode;
	95	u16 vxlan_udp_port;
	96	u16 geneve_udp_port;
	97	u8 update_vxlan_udp_port;
	98	u8 update_geneve_udp_port;
	99	u8 tunn_clss_vxlan;
	100	u8 tunn_clss_l2geneve;
	101	u8 tunn_clss_ipgeneve;
	102	u8 tunn_clss_l2gre;
	103	u8 tunn_clss_ipgre;
	104	};
	105
	106	struct qed_tunn_update_params {
	107	unsigned long tunn_mode_update_mask;
	108	unsigned long tunn_mode;
	109	u16 vxlan_udp_port;
	110	u16 geneve_udp_port;
	111	u8 update_rx_pf_clss;
	112	u8 update_tx_pf_clss;
	113	u8 update_vxlan_udp_port;
	114	u8 update_geneve_udp_port;
	115	u8 tunn_clss_vxlan;
	116	u8 tunn_clss_l2geneve;
	117	u8 tunn_clss_ipgeneve;
	118	u8 tunn_clss_l2gre;
	119	u8 tunn_clss_ipgre;
	120	};
	121
fe56b9e6 YM	122	/* The PCI personality is not quite synonymous to protocol ID:
	123	* 1. All personalities need CORE connections
	124	* 2. The Ethernet personality may support also the RoCE protocol
	125	*/
	126	enum qed_pci_personality {
	127	QED_PCI_ETH,
	128	QED_PCI_DEFAULT /* default in shmem */
	129	};
	130
	131	/* All VFs are symmetric, all counters are PF + all VFs */
	132	struct qed_qm_iids {
	133	u32 cids;
	134	u32 vf_cids;
	135	u32 tids;
	136	};
	137
	138	enum QED_RESOURCES {
	139	QED_SB,
25c089d7	140	QED_L2_QUEUE,
fe56b9e6	141	QED_VPORT,
25c089d7	142	QED_RSS_ENG,
fe56b9e6 YM	143	QED_PQ,
fe56b9e6 YM	144	QED_RL,
25c089d7 YM	145	QED_MAC,
25c089d7 YM	146	QED_VLAN,
fe56b9e6 YM	147	QED_ILT,
	148	QED_MAX_RESC,
	149	};
	150
25c089d7 YM	151	enum QED_FEATURE {
	152	QED_PF_L2_QUE,
	153	QED_MAX_FEATURES,
	154	};
	155
cc875c2e YM	156	enum QED_PORT_MODE {
	157	QED_PORT_MODE_DE_2X40G,
	158	QED_PORT_MODE_DE_2X50G,
	159	QED_PORT_MODE_DE_1X100G,
	160	QED_PORT_MODE_DE_4X10G_F,
	161	QED_PORT_MODE_DE_4X10G_E,
	162	QED_PORT_MODE_DE_4X20G,
	163	QED_PORT_MODE_DE_1X40G,
	164	QED_PORT_MODE_DE_2X25G,
	165	QED_PORT_MODE_DE_1X25G
	166	};
	167
fc48b7a6 YM	168	enum qed_dev_cap {
	169	QED_DEV_CAP_ETH,
	170	};
	171
fe56b9e6 YM	172	struct qed_hw_info {
	173	/* PCI personality */
	174	enum qed_pci_personality personality;
	175
	176	/* Resource Allocation scheme results */
	177	u32 resc_start[QED_MAX_RESC];
	178	u32 resc_num[QED_MAX_RESC];
25c089d7	179	u32 feat_num[QED_MAX_FEATURES];
fe56b9e6 YM	180
	181	#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
	182	#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
	183	#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
	184
	185	u8 num_tc;
	186	u8 offload_tc;
	187	u8 non_offload_tc;
	188
	189	u32 concrete_fid;
	190	u16 opaque_fid;
	191	u16 ovlan;
	192	u32 part_num[4];
	193
fe56b9e6 YM	194	unsigned char hw_mac_addr[ETH_ALEN];
	195
	196	struct qed_igu_info *p_igu_info;
	197
	198	u32 port_mode;
	199	u32 hw_mode;
fc48b7a6	200	unsigned long device_capabilities;
fe56b9e6 YM	201	};
	202
	203	struct qed_hw_cid_data {
	204	u32 cid;
	205	bool b_cid_allocated;
	206
	207	/* Additional identifiers */
	208	u16 opaque_fid;
	209	u8 vport_id;
	210	};
	211
	212	/* maximun size of read/write commands (HW limit) */
	213	#define DMAE_MAX_RW_SIZE 0x2000
	214
	215	struct qed_dmae_info {
	216	/* Mutex for synchronizing access to functions */
	217	struct mutex mutex;
	218
	219	u8 channel;
	220
	221	dma_addr_t completion_word_phys_addr;
	222
	223	/* The memory location where the DMAE writes the completion
	224	* value when an operation is finished on this context.
	225	*/
	226	u32 *p_completion_word;
	227
	228	dma_addr_t intermediate_buffer_phys_addr;
	229
	230	/* An intermediate buffer for DMAE operations that use virtual
	231	* addresses - data is DMA'd to/from this buffer and then
	232	* memcpy'd to/from the virtual address
	233	*/
	234	u32 *p_intermediate_buffer;
	235
	236	dma_addr_t dmae_cmd_phys_addr;
	237	struct dmae_cmd *p_dmae_cmd;
	238	};
	239
	240	struct qed_qm_info {
	241	struct init_qm_pq_params *qm_pq_params;
	242	struct init_qm_vport_params *qm_vport_params;
	243	struct init_qm_port_params *qm_port_params;
	244	u16 start_pq;
	245	u8 start_vport;
	246	u8 pure_lb_pq;
	247	u8 offload_pq;
	248	u8 pure_ack_pq;
	249	u8 vf_queues_offset;
	250	u16 num_pqs;
	251	u16 num_vf_pqs;
	252	u8 num_vports;
	253	u8 max_phys_tcs_per_port;
	254	bool pf_rl_en;
	255	bool pf_wfq_en;
	256	bool vport_rl_en;
	257	bool vport_wfq_en;
	258	u8 pf_wfq;
	259	u32 pf_rl;
	260	};
	261
9df2ed04 MC	262	struct storm_stats {
	263	u32 address;
	264	u32 len;
	265	};
	266
	267	struct qed_storm_stats {
	268	struct storm_stats mstats;
	269	struct storm_stats pstats;
	270	struct storm_stats tstats;
	271	struct storm_stats ustats;
	272	};
	273
fe56b9e6	274	struct qed_fw_data {
9df2ed04	275	struct fw_ver_info *fw_ver_info;
fe56b9e6 YM	276	const u8 *modes_tree_buf;
	277	union init_op *init_ops;
	278	const u32 *arr_data;
	279	u32 init_ops_size;
	280	};
	281
	282	struct qed_simd_fp_handler {
	283	void *token;
	284	void (func)(void );
	285	};
	286
	287	struct qed_hwfn {
	288	struct qed_dev *cdev;
	289	u8 my_id; /* ID inside the PF */
	290	#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
	291	u8 rel_pf_id; /* Relative to engine*/
	292	u8 abs_pf_id;
	293	#define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
	294	u8 port_id;
	295	bool b_active;
	296
	297	u32 dp_module;
	298	u8 dp_level;
	299	char name[NAME_SIZE];
	300
	301	bool first_on_engine;
	302	bool hw_init_done;
	303
	304	/* BAR access */
	305	void __iomem *regview;
	306	void __iomem *doorbells;
	307	u64 db_phys_addr;
	308	unsigned long db_size;
	309
	310	/* PTT pool */
	311	struct qed_ptt_pool *p_ptt_pool;
	312
	313	/* HW info */
	314	struct qed_hw_info hw_info;
	315
	316	/* rt_array (for init-tool) */
fc48b7a6	317	struct qed_rt_data rt_data;
fe56b9e6 YM	318
	319	/* SPQ */
	320	struct qed_spq *p_spq;
	321
	322	/* EQ */
	323	struct qed_eq *p_eq;
	324
	325	/* Consolidate Q*/
	326	struct qed_consq *p_consq;
	327
	328	/* Slow-Path definitions */
	329	struct tasklet_struct *sp_dpc;
	330	bool b_sp_dpc_enabled;
	331
	332	struct qed_ptt *p_main_ptt;
	333	struct qed_ptt *p_dpc_ptt;
	334
	335	struct qed_sb_sp_info *p_sp_sb;
	336	struct qed_sb_attn_info *p_sb_attn;
	337
	338	/* Protocol related */
	339	struct qed_pf_params pf_params;
	340
	341	/* Array of sb_info of all status blocks */
	342	struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
	343	u16 num_sbs;
	344
	345	struct qed_cxt_mngr *p_cxt_mngr;
	346
	347	/* Flag indicating whether interrupts are enabled or not*/
	348	bool b_int_enabled;
8f16bc97	349	bool b_int_requested;
fe56b9e6	350
fc916ff2 SRK	351	/* True if the driver requests for the link */
	352	bool b_drv_link_init;
	353
fe56b9e6 YM	354	struct qed_mcp_info *mcp_info;
fe56b9e6 YM	355
25c089d7 YM	356	struct qed_hw_cid_data *p_tx_cids;
	357	struct qed_hw_cid_data *p_rx_cids;
	358
fe56b9e6 YM	359	struct qed_dmae_info dmae_info;
	360
	361	/* QM init */
	362	struct qed_qm_info qm_info;
9df2ed04	363	struct qed_storm_stats storm_stats;
fe56b9e6 YM	364
	365	/* Buffer for unzipping firmware data */
	366	void *unzip_buf;
	367
	368	struct qed_simd_fp_handler simd_proto_handler[64];
	369
	370	struct z_stream_s *stream;
	371	};
	372
	373	struct pci_params {
	374	int pm_cap;
	375
	376	unsigned long mem_start;
	377	unsigned long mem_end;
	378	unsigned int irq;
	379	u8 pf_num;
	380	};
	381
	382	struct qed_int_param {
	383	u32 int_mode;
	384	u8 num_vectors;
	385	u8 min_msix_cnt; /* for minimal functionality */
	386	};
	387
	388	struct qed_int_params {
	389	struct qed_int_param in;
	390	struct qed_int_param out;
	391	struct msix_entry *msix_table;
	392	bool fp_initialized;
	393	u8 fp_msix_base;
	394	u8 fp_msix_cnt;
	395	};
	396
	397	struct qed_dev {
	398	u32 dp_module;
	399	u8 dp_level;
	400	char name[NAME_SIZE];
	401
	402	u8 type;
fc48b7a6 YM	403	#define QED_DEV_TYPE_BB (0 << 0)
	404	#define QED_DEV_TYPE_AH BIT(0)
	405	/* Translate type/revision combo into the proper conditions */
	406	#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
	407	#define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
	408	CHIP_REV_IS_A0(dev))
	409	#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
	410	CHIP_REV_IS_B0(dev))
	411
	412	#define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
	413	QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
	414
	415	u16 vendor_id;
	416	u16 device_id;
fe56b9e6 YM	417
	418	u16 chip_num;
	419	#define CHIP_NUM_MASK 0xffff
	420	#define CHIP_NUM_SHIFT 16
	421
	422	u16 chip_rev;
	423	#define CHIP_REV_MASK 0xf
	424	#define CHIP_REV_SHIFT 12
fc48b7a6 YM	425	#define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
fc48b7a6 YM	426	#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
fe56b9e6 YM	427
	428	u16 chip_metal;
	429	#define CHIP_METAL_MASK 0xff
	430	#define CHIP_METAL_SHIFT 4
	431
	432	u16 chip_bond_id;
	433	#define CHIP_BOND_ID_MASK 0xf
	434	#define CHIP_BOND_ID_SHIFT 0
	435
	436	u8 num_engines;
	437	u8 num_ports_in_engines;
	438	u8 num_funcs_in_port;
	439
	440	u8 path_id;
fc48b7a6 YM	441	enum qed_mf_mode mf_mode;
	442	#define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
	443	#define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
	444	#define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
fe56b9e6 YM	445
	446	int pcie_width;
	447	int pcie_speed;
	448	u8 ver_str[VER_SIZE];
	449
	450	/* Add MF related configuration */
	451	u8 mcp_rev;
	452	u8 boot_mode;
	453
	454	u8 wol;
	455
	456	u32 int_mode;
	457	enum qed_coalescing_mode int_coalescing_mode;
	458	u8 rx_coalesce_usecs;
	459	u8 tx_coalesce_usecs;
	460
	461	/* Start Bar offset of first hwfn */
	462	void __iomem *regview;
	463	void __iomem *doorbells;
	464	u64 db_phys_addr;
	465	unsigned long db_size;
	466
	467	/* PCI */
	468	u8 cache_shift;
	469
	470	/* Init */
	471	const struct iro *iro_arr;
	472	#define IRO (p_hwfn->cdev->iro_arr)
	473
	474	/* HW functions */
	475	u8 num_hwfns;
	476	struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
	477
464f6645	478	unsigned long tunn_mode;
fe56b9e6 YM	479	u32 drv_type;
	480
	481	struct qed_eth_stats *reset_stats;
	482	struct qed_fw_data *fw_data;
	483
	484	u32 mcp_nvm_resp;
	485
	486	/* Linux specific here */
	487	struct qede_dev *edev;
	488	struct pci_dev *pdev;
	489	int msg_enable;
	490
	491	struct pci_params pci_params;
	492
	493	struct qed_int_params int_params;
	494
	495	u8 protocol;
	496	#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
	497
cc875c2e YM	498	/* Callbacks to protocol driver */
	499	union {
	500	struct qed_common_cb_ops *common;
	501	struct qed_eth_cb_ops *eth;
	502	} protocol_ops;
	503	void *ops_cookie;
	504
fe56b9e6 YM	505	const struct firmware *firmware;
	506	};
	507
fe56b9e6 YM	508	#define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
	509	#define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
	510
	511	/**
	512	* @brief qed_concrete_to_sw_fid - get the sw function id from
	513	* the concrete value.
	514	*
	515	* @param concrete_fid
	516	*
	517	* @return inline u8
	518	*/
	519	static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
	520	u32 concrete_fid)
	521	{
	522	u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
	523
	524	return pfid;
	525	}
	526
	527	#define PURE_LB_TC 8
	528
	529	#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
	530
	531	/* Other Linux specific common definitions */
	532	#define DP_NAME(cdev) ((cdev)->name)
	533
	534	#define REG_ADDR(cdev, offset) (void __iomem )((u8 __iomem )\
	535	(cdev->regview) + \
	536	(offset))
	537
	538	#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
	539	#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
	540	#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
	541
	542	#define DOORBELL(cdev, db_addr, val) \
	543	writel((u32)val, (void __iomem )((u8 __iomem )\
	544	(cdev->doorbells) + (db_addr)))
	545
	546	/* Prototypes */
	547	int qed_fill_dev_info(struct qed_dev *cdev,
	548	struct qed_dev_info *dev_info);
cc875c2e	549	void qed_link_update(struct qed_hwfn *hwfn);
fe56b9e6 YM	550	u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
	551	u32 input_len, u8 *input_buf,
	552	u32 max_size, u8 *unzip_buf);
	553
8f16bc97 SK	554	int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
8f16bc97 SK	555
fe56b9e6	556	#endif /* _QED_H */