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Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
[linux-2.6-block.git] / drivers / net / ethernet / qlogic / netxen / netxen_nic_hw.c
CommitLineData
3d396eb1 1/*
5d242f1c 2 * Copyright (C) 2003 - 2009 NetXen, Inc.
13af7a6e 3 * Copyright (C) 2009 - QLogic Corporation.
3d396eb1 4 * All rights reserved.
80922fbc 5 *
3d396eb1
AK		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
cb8011ad 10 *
3d396eb1
AK		 11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
cb8011ad 15 *
3d396eb1 16 * You should have received a copy of the GNU General Public License
0ab75ae8 17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
80922fbc 18 *
3d396eb1 19 * The full GNU General Public License is included in this distribution
4d21fef4 20 * in the file called "COPYING".
80922fbc 21 *
3d396eb1
AK		 22 */
23
5a0e3ad6 24#include <linux/slab.h>
3d396eb1
AK		 25#include "netxen_nic.h"
26#include "netxen_nic_hw.h"
3d396eb1 27
c9bdd4b5
ACM		 28#include <net/ip.h>
29
3ce06a32
DP		 30#define MASK(n) ((1ULL<<(n))-1)
31#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
32#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
33#define MS_WIN(addr) (addr & 0x0ffc0000)
34
35#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
36
37#define CRB_BLK(off) ((off >> 20) & 0x3f)
38#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
39#define CRB_WINDOW_2M (0x130060)
40#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
41#define CRB_INDIRECT_2M (0x1e0000UL)
42
f03b0ebd
DP		 43static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
44 void __iomem *addr, u32 data);
45static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
46 void __iomem *addr);
e98e3350
DP		 47#ifndef readq
48static inline u64 readq(void __iomem *addr)
49{
50 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
51}
52#endif
53
54#ifndef writeq
55static inline void writeq(u64 val, void __iomem *addr)
56{
57 writel(((u32) (val)), (addr));
58 writel(((u32) (val >> 32)), (addr + 4));
59}
60#endif
61
1fbe6323
DP		 62#define PCI_OFFSET_FIRST_RANGE(adapter, off) \
63 ((adapter)->ahw.pci_base0 + (off))
64#define PCI_OFFSET_SECOND_RANGE(adapter, off) \
65 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
66#define PCI_OFFSET_THIRD_RANGE(adapter, off) \
67 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
68
69static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
70 unsigned long off)
71{
72 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
73 return PCI_OFFSET_FIRST_RANGE(adapter, off);
74
75 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
76 return PCI_OFFSET_SECOND_RANGE(adapter, off);
77
78 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
79 return PCI_OFFSET_THIRD_RANGE(adapter, off);
80
81 return NULL;
82}
83
ea7eaa39
DP		 84static crb_128M_2M_block_map_t
85crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
3ce06a32
DP		 86 {{{0, 0, 0, 0} } }, /* 0: PCI */
87 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
88 {1, 0x0110000, 0x0120000, 0x130000},
89 {1, 0x0120000, 0x0122000, 0x124000},
90 {1, 0x0130000, 0x0132000, 0x126000},
91 {1, 0x0140000, 0x0142000, 0x128000},
92 {1, 0x0150000, 0x0152000, 0x12a000},
93 {1, 0x0160000, 0x0170000, 0x110000},
94 {1, 0x0170000, 0x0172000, 0x12e000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {1, 0x01e0000, 0x01e0800, 0x122000},
102 {0, 0x0000000, 0x0000000, 0x000000} } },
103 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
104 {{{0, 0, 0, 0} } }, /* 3: */
105 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
106 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
107 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
108 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
109 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {1, 0x08f0000, 0x08f2000, 0x172000} } },
125 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {1, 0x09f0000, 0x09f2000, 0x176000} } },
141 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
157 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
173 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
174 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
175 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
176 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
177 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
178 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
179 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
180 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
181 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
182 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
183 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
184 {{{0, 0, 0, 0} } }, /* 23: */
185 {{{0, 0, 0, 0} } }, /* 24: */
186 {{{0, 0, 0, 0} } }, /* 25: */
187 {{{0, 0, 0, 0} } }, /* 26: */
188 {{{0, 0, 0, 0} } }, /* 27: */
189 {{{0, 0, 0, 0} } }, /* 28: */
190 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
191 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
192 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
193 {{{0} } }, /* 32: PCI */
194 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
195 {1, 0x2110000, 0x2120000, 0x130000},
196 {1, 0x2120000, 0x2122000, 0x124000},
197 {1, 0x2130000, 0x2132000, 0x126000},
198 {1, 0x2140000, 0x2142000, 0x128000},
199 {1, 0x2150000, 0x2152000, 0x12a000},
200 {1, 0x2160000, 0x2170000, 0x110000},
201 {1, 0x2170000, 0x2172000, 0x12e000},
202 {0, 0x0000000, 0x0000000, 0x000000},
203 {0, 0x0000000, 0x0000000, 0x000000},
204 {0, 0x0000000, 0x0000000, 0x000000},
205 {0, 0x0000000, 0x0000000, 0x000000},
206 {0, 0x0000000, 0x0000000, 0x000000},
207 {0, 0x0000000, 0x0000000, 0x000000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000} } },
210 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
211 {{{0} } }, /* 35: */
212 {{{0} } }, /* 36: */
213 {{{0} } }, /* 37: */
214 {{{0} } }, /* 38: */
215 {{{0} } }, /* 39: */
216 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
217 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
218 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
219 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
220 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
221 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
222 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
223 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
224 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
225 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
226 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
227 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
228 {{{0} } }, /* 52: */
229 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
230 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
231 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
232 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
233 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
234 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
235 {{{0} } }, /* 59: I2C0 */
236 {{{0} } }, /* 60: I2C1 */
237 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
238 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
239 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
240};
241
242/*
243 * top 12 bits of crb internal address (hub, agent)
244 */
245static unsigned crb_hub_agt[64] =
246{
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
249 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
250 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
251 0,
252 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
253 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
254 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
255 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
256 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
257 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
259 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
260 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
261 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
262 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
264 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
265 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
266 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
277 0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
279 0,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
281 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
282 0,
283 0,
284 0,
285 0,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
288 0,
289 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
290 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
291 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
292 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
293 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
294 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
296 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
297 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
298 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
299 0,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
303 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
304 0,
305 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
306 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
308 0,
309 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
310 0,
311};
312
3d396eb1
AK		 313/* PCI Windowing for DDR regions. */
314
3ce06a32 315#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
3d396eb1 316
c9517e58
DP		 317#define NETXEN_PCIE_SEM_TIMEOUT 10000
318
7e12bb0a 319static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
320
c9517e58
DP		 321int
322netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
323{
324 int done = 0, timeout = 0;
325
326 while (!done) {
327 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
328 if (done == 1)
329 break;
330 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
7cecdca1 331 return -EIO;
c9517e58
DP		 332 msleep(1);
333 }
334
335 if (id_reg)
336 NXWR32(adapter, id_reg, adapter->portnum);
337
338 return 0;
339}
340
341void
342netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
343{
581e8ae4 344 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
c9517e58
DP		 345}
346
7e12bb0a 347static int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
3ad4467c
DP		 348{
349 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
350 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
351 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
352 }
353
354 return 0;
355}
356
357/* Disable an XG interface */
7e12bb0a 358static int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
3ad4467c
DP		 359{
360 __u32 mac_cfg;
361 u32 port = adapter->physical_port;
362
363 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
364 return 0;
365
ed3b856b 366 if (port >= NETXEN_NIU_MAX_XG_PORTS)
3ad4467c
DP		 367 return -EINVAL;
368
369 mac_cfg = 0;
370 if (NXWR32(adapter,
371 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
372 return -EIO;
373 return 0;
374}
375
623621b0
DP		 376#define NETXEN_UNICAST_ADDR(port, index) \
377 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
378#define NETXEN_MCAST_ADDR(port, index) \
379 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
380#define MAC_HI(addr) \
381 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
382#define MAC_LO(addr) \
383 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
384
7e12bb0a 385static int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
3ad4467c 386{
a7483b0a
NK		 387 u32 mac_cfg;
388 u32 cnt = 0;
389 __u32 reg = 0x0200;
3ad4467c 390 u32 port = adapter->physical_port;
a7483b0a 391 u16 board_type = adapter->ahw.board_type;
3ad4467c 392
ed3b856b 393 if (port >= NETXEN_NIU_MAX_XG_PORTS)
3ad4467c
DP		 394 return -EINVAL;
395
a7483b0a
NK		 396 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
397 mac_cfg &= ~0x4;
398 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
3ad4467c 399
a7483b0a
NK		 400 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
401 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
402 reg = (0x20 << port);
3ad4467c 403
a7483b0a
NK		 404 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
405
406 mdelay(10);
407
408 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
409 mdelay(10);
410
411 if (cnt < 20) {
412
413 reg = NXRD32(adapter,
414 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
415
416 if (mode == NETXEN_NIU_PROMISC_MODE)
417 reg = (reg | 0x2000UL);
418 else
419 reg = (reg & ~0x2000UL);
420
421 if (mode == NETXEN_NIU_ALLMULTI_MODE)
422 reg = (reg | 0x1000UL);
423 else
424 reg = (reg & ~0x1000UL);
425
426 NXWR32(adapter,
427 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
428 }
429
430 mac_cfg |= 0x4;
431 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
3ad4467c
DP		 432
433 return 0;
434}
435
7e12bb0a 436static int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
3ad4467c
DP		 437{
438 u32 mac_hi, mac_lo;
439 u32 reg_hi, reg_lo;
440
441 u8 phy = adapter->physical_port;
442
443 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
444 return -EINVAL;
445
446 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
447 mac_hi = addr[2] | ((u32)addr[3] << 8) |
448 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
449
450 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
451 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
452
453 /* write twice to flush */
454 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
455 return -EIO;
456 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
457 return -EIO;
458
459 return 0;
460}
461
623621b0
DP		 462static int
463netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
464{
465 u32 val = 0;
466 u16 port = adapter->physical_port;
5d09e534 467 u8 *addr = adapter->mac_addr;
623621b0
DP		 468
469 if (adapter->mc_enabled)
470 return 0;
471
f98a9f69 472 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 473 val |= (1UL << (28+port));
f98a9f69 474 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 475
476 /* add broadcast addr to filter */
477 val = 0xffffff;
f98a9f69
DP		 478 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
479 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0
DP		 480
481 /* add station addr to filter */
482 val = MAC_HI(addr);
f98a9f69 483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
623621b0 484 val = MAC_LO(addr);
f98a9f69 485 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
623621b0
DP		 486
487 adapter->mc_enabled = 1;
488 return 0;
489}
490
491static int
492netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
493{
494 u32 val = 0;
495 u16 port = adapter->physical_port;
5d09e534 496 u8 *addr = adapter->mac_addr;
623621b0
DP		 497
498 if (!adapter->mc_enabled)
499 return 0;
500
f98a9f69 501 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
623621b0 502 val &= ~(1UL << (28+port));
f98a9f69 503 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
623621b0
DP		 504
505 val = MAC_HI(addr);
f98a9f69 506 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
623621b0 507 val = MAC_LO(addr);
f98a9f69 508 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
623621b0 509
f98a9f69
DP		 510 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
511 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
623621b0
DP		 512
513 adapter->mc_enabled = 0;
514 return 0;
515}
516
517static int
518netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
519 int index, u8 *addr)
520{
521 u32 hi = 0, lo = 0;
522 u16 port = adapter->physical_port;
523
524 lo = MAC_LO(addr);
525 hi = MAC_HI(addr);
526
f98a9f69
DP		 527 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
528 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
623621b0
DP		 529
530 return 0;
531}
532
7e12bb0a 533static void netxen_p2_nic_set_multi(struct net_device *netdev)
3d396eb1 534{
3176ff3e 535 struct netxen_adapter *adapter = netdev_priv(netdev);
22bedad3 536 struct netdev_hw_addr *ha;
1409a932 537 u8 null_addr[ETH_ALEN];
f9dcbcc9 538 int i;
623621b0 539
c7bf7169 540 eth_zero_addr(null_addr);
3d396eb1 541
3d396eb1 542 if (netdev->flags & IFF_PROMISC) {
623621b0
DP		 543
544 adapter->set_promisc(adapter,
545 NETXEN_NIU_PROMISC_MODE);
546
547 /* Full promiscuous mode */
548 netxen_nic_disable_mcast_filter(adapter);
549
550 return;
551 }
552
4cd24eaf 553 if (netdev_mc_empty(netdev)) {
623621b0
DP		 554 adapter->set_promisc(adapter,
555 NETXEN_NIU_NON_PROMISC_MODE);
556 netxen_nic_disable_mcast_filter(adapter);
557 return;
558 }
559
560 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
561 if (netdev->flags & IFF_ALLMULTI ||
4cd24eaf 562 netdev_mc_count(netdev) > adapter->max_mc_count) {
623621b0
DP		 563 netxen_nic_disable_mcast_filter(adapter);
564 return;
3d396eb1 565 }
623621b0
DP		 566
567 netxen_nic_enable_mcast_filter(adapter);
568
f9dcbcc9 569 i = 0;
22bedad3
JP		 570 netdev_for_each_mc_addr(ha, netdev)
571 netxen_nic_set_mcast_addr(adapter, i++, ha->addr);
623621b0
DP		 572
573 /* Clear out remaining addresses */
f9dcbcc9
JP		 574 while (i < adapter->max_mc_count)
575 netxen_nic_set_mcast_addr(adapter, i++, null_addr);
3d396eb1
AK		 576}
577
c9fc891f
DP		 578static int
579netxen_send_cmd_descs(struct netxen_adapter *adapter,
d877f1e3 580 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
c9fc891f 581{
d877f1e3 582 u32 i, producer, consumer;
c9fc891f
DP		 583 struct netxen_cmd_buffer *pbuf;
584 struct cmd_desc_type0 *cmd_desc;
d877f1e3 585 struct nx_host_tx_ring *tx_ring;
c9fc891f
DP		 586
587 i = 0;
588
db4cfd8a
DP		 589 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
590 return -EIO;
591
4ea528a1 592 tx_ring = adapter->tx_ring;
b2af9cb0 593 __netif_tx_lock_bh(tx_ring->txq);
03e678ee 594
d877f1e3
DP		 595 producer = tx_ring->producer;
596 consumer = tx_ring->sw_consumer;
597
b2af9cb0
DP		 598 if (nr_desc >= netxen_tx_avail(tx_ring)) {
599 netif_tx_stop_queue(tx_ring->txq);
7a9905e6
RB		 600 smp_mb();
601 if (netxen_tx_avail(tx_ring) > nr_desc) {
602 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
603 netif_tx_wake_queue(tx_ring->txq);
604 } else {
605 __netif_tx_unlock_bh(tx_ring->txq);
606 return -EBUSY;
607 }
d877f1e3
DP		 608 }
609
c9fc891f
DP		 610 do {
611 cmd_desc = &cmd_desc_arr[i];
612
d877f1e3 613 pbuf = &tx_ring->cmd_buf_arr[producer];
c9fc891f 614 pbuf->skb = NULL;
c9fc891f 615 pbuf->frag_count = 0;
c9fc891f 616
d877f1e3 617 memcpy(&tx_ring->desc_head[producer],
c9fc891f
DP		 618 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
619
d877f1e3 620 producer = get_next_index(producer, tx_ring->num_desc);
c9fc891f
DP		 621 i++;
622
d877f1e3 623 } while (i != nr_desc);
c9fc891f 624
d877f1e3 625 tx_ring->producer = producer;
c9fc891f 626
cb2107be 627 netxen_nic_update_cmd_producer(adapter, tx_ring);
c9fc891f 628
b2af9cb0 629 __netif_tx_unlock_bh(tx_ring->txq);
03e678ee 630
c9fc891f
DP		 631 return 0;
632}
633
5cf4d323
DP		 634static int
635nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
c9fc891f 636{
c9fc891f 637 nx_nic_req_t req;
2edbb454
DP		 638 nx_mac_req_t *mac_req;
639 u64 word;
c9fc891f
DP		 640
641 memset(&req, 0, sizeof(nx_nic_req_t));
2edbb454
DP		 642 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
643
644 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
645 req.req_hdr = cpu_to_le64(word);
646
647 mac_req = (nx_mac_req_t *)&req.words[0];
648 mac_req->op = op;
d458cdf7 649 memcpy(mac_req->mac_addr, addr, ETH_ALEN);
c9fc891f 650
5cf4d323
DP		 651 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
652}
653
654static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
215faf9c 655 const u8 *addr, struct list_head *del_list)
5cf4d323
DP		 656{
657 struct list_head *head;
658 nx_mac_list_t *cur;
659
660 /* look up if already exists */
661 list_for_each(head, del_list) {
662 cur = list_entry(head, nx_mac_list_t, list);
663
202af853 664 if (ether_addr_equal(addr, cur->mac_addr)) {
5cf4d323
DP		 665 list_move_tail(head, &adapter->mac_list);
666 return 0;
667 }
c9fc891f
DP		 668 }
669
5cf4d323 670 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
b2adaca9 671 if (cur == NULL)
5cf4d323 672 return -ENOMEM;
b2adaca9 673
5cf4d323
DP		 674 memcpy(cur->mac_addr, addr, ETH_ALEN);
675 list_add_tail(&cur->list, &adapter->mac_list);
676 return nx_p3_sre_macaddr_change(adapter,
677 cur->mac_addr, NETXEN_MAC_ADD);
c9fc891f
DP		 678}
679
7e12bb0a 680static void netxen_p3_nic_set_multi(struct net_device *netdev)
c9fc891f
DP		 681{
682 struct netxen_adapter *adapter = netdev_priv(netdev);
22bedad3 683 struct netdev_hw_addr *ha;
215faf9c
JP		 684 static const u8 bcast_addr[ETH_ALEN] = {
685 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
686 };
9ad27643 687 u32 mode = VPORT_MISS_MODE_DROP;
5cf4d323
DP		 688 LIST_HEAD(del_list);
689 struct list_head *head;
690 nx_mac_list_t *cur;
c9fc891f 691
d49c9640
AKS		 692 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
693 return;
694
5cf4d323 695 list_splice_tail_init(&adapter->mac_list, &del_list);
c9fc891f 696
5d09e534 697 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
5cf4d323 698 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
9ad27643
DP		 699
700 if (netdev->flags & IFF_PROMISC) {
701 mode = VPORT_MISS_MODE_ACCEPT_ALL;
702 goto send_fw_cmd;
703 }
704
705 if ((netdev->flags & IFF_ALLMULTI) ||
4cd24eaf 706 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
9ad27643
DP		 707 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
708 goto send_fw_cmd;
709 }
710
4cd24eaf 711 if (!netdev_mc_empty(netdev)) {
22bedad3
JP		 712 netdev_for_each_mc_addr(ha, netdev)
713 nx_p3_nic_add_mac(adapter, ha->addr, &del_list);
c9fc891f 714 }
9ad27643
DP		 715
716send_fw_cmd:
717 adapter->set_promisc(adapter, mode);
5cf4d323
DP		 718 head = &del_list;
719 while (!list_empty(head)) {
720 cur = list_entry(head->next, nx_mac_list_t, list);
721
722 nx_p3_sre_macaddr_change(adapter,
723 cur->mac_addr, NETXEN_MAC_DEL);
724 list_del(&cur->list);
c9fc891f 725 kfree(cur);
c9fc891f
DP		 726 }
727}
728
7e12bb0a 729static int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
9ad27643
DP		 730{
731 nx_nic_req_t req;
2edbb454 732 u64 word;
9ad27643
DP		 733
734 memset(&req, 0, sizeof(nx_nic_req_t));
735
2edbb454
DP		 736 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
737
738 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
739 ((u64)adapter->portnum << 16);
740 req.req_hdr = cpu_to_le64(word);
741
9ad27643
DP		 742 req.words[0] = cpu_to_le64(mode);
743
744 return netxen_send_cmd_descs(adapter,
745 (struct cmd_desc_type0 *)&req, 1);
746}
747
06e9d9f9
DP		 748void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
749{
5cf4d323
DP		 750 nx_mac_list_t *cur;
751 struct list_head *head = &adapter->mac_list;
752
753 while (!list_empty(head)) {
754 cur = list_entry(head->next, nx_mac_list_t, list);
755 nx_p3_sre_macaddr_change(adapter,
756 cur->mac_addr, NETXEN_MAC_DEL);
757 list_del(&cur->list);
06e9d9f9 758 kfree(cur);
06e9d9f9
DP		 759 }
760}
761
7e12bb0a 762static int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
3d0a3cc9
DP		 763{
764 /* assuming caller has already copied new addr to netdev */
765 netxen_p3_nic_set_multi(adapter->netdev);
766 return 0;
767}
768
cd1f8160
DP		 769#define NETXEN_CONFIG_INTR_COALESCE 3
770
771/*
772 * Send the interrupt coalescing parameter set by ethtool to the card.
773 */
774int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
775{
776 nx_nic_req_t req;
c0703950
AKS		 777 u64 word[6];
778 int rv, i;
cd1f8160
DP		 779
780 memset(&req, 0, sizeof(nx_nic_req_t));
c0703950 781 memset(word, 0, sizeof(word));
cd1f8160 782
1bb482f8 783 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
2edbb454 784
c0703950
AKS		 785 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
786 req.req_hdr = cpu_to_le64(word[0]);
cd1f8160 787
c0703950
AKS		 788 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
789 for (i = 0; i < 6; i++)
790 req.words[i] = cpu_to_le64(word[i]);
cd1f8160
DP		 791
792 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
793 if (rv != 0) {
794 printk(KERN_ERR "ERROR. Could not send "
795 "interrupt coalescing parameters\n");
796 }
797
798 return rv;
799}
800
1bb482f8
NK		 801int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
802{
803 nx_nic_req_t req;
804 u64 word;
805 int rv = 0;
806
34624d66
SC		 807 if (!test_bit(__NX_FW_ATTACHED, &adapter->state))
808 return 0;
809
1bb482f8
NK		 810 memset(&req, 0, sizeof(nx_nic_req_t));
811
812 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
813
814 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
815 req.req_hdr = cpu_to_le64(word);
816
817 req.words[0] = cpu_to_le64(enable);
818
819 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
820 if (rv != 0) {
821 printk(KERN_ERR "ERROR. Could not send "
822 "configure hw lro request\n");
823 }
824
1bb482f8
NK		 825 return rv;
826}
827
fa3ce355
NK		 828int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
829{
830 nx_nic_req_t req;
831 u64 word;
832 int rv = 0;
833
834 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
835 return rv;
836
837 memset(&req, 0, sizeof(nx_nic_req_t));
838
839 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
840
841 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
842 ((u64)adapter->portnum << 16);
843 req.req_hdr = cpu_to_le64(word);
844
845 req.words[0] = cpu_to_le64(enable);
846
847 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
848 if (rv != 0) {
849 printk(KERN_ERR "ERROR. Could not send "
850 "configure bridge mode request\n");
851 }
852
853 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
854
855 return rv;
856}
857
858
d8b100c5
DP		 859#define RSS_HASHTYPE_IP_TCP 0x3
860
861int netxen_config_rss(struct netxen_adapter *adapter, int enable)
862{
863 nx_nic_req_t req;
864 u64 word;
865 int i, rv;
866
215faf9c
JP		 867 static const u64 key[] = {
868 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
869 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
870 0x255b0ec26d5a56daULL
871 };
d8b100c5
DP		 872
873
874 memset(&req, 0, sizeof(nx_nic_req_t));
875 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
876
877 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
878 req.req_hdr = cpu_to_le64(word);
879
880 /*
881 * RSS request:
882 * bits 3-0: hash_method
883 * 5-4: hash_type_ipv4
884 * 7-6: hash_type_ipv6
885 * 8: enable
886 * 9: use indirection table
887 * 47-10: reserved
888 * 63-48: indirection table mask
889 */
890 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
891 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
892 ((u64)(enable & 0x1) << 8) |
893 ((0x7ULL) << 48);
894 req.words[0] = cpu_to_le64(word);
215faf9c 895 for (i = 0; i < ARRAY_SIZE(key); i++)
d8b100c5
DP		 896 req.words[i+1] = cpu_to_le64(key[i]);
897
898
899 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
900 if (rv != 0) {
901 printk(KERN_ERR "%s: could not configure RSS\n",
902 adapter->netdev->name);
903 }
904
905 return rv;
906}
907
06d6c108 908int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd)
6598b169
DP		 909{
910 nx_nic_req_t req;
911 u64 word;
912 int rv;
913
914 memset(&req, 0, sizeof(nx_nic_req_t));
915 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
916
917 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
918 req.req_hdr = cpu_to_le64(word);
919
920 req.words[0] = cpu_to_le64(cmd);
06d6c108 921 memcpy(&req.words[1], &ip, sizeof(u32));
6598b169
DP		 922
923 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
924 if (rv != 0) {
9b13494c 925 printk(KERN_ERR "%s: could not notify %s IP 0x%x request\n",
6598b169
DP		 926 adapter->netdev->name,
927 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
928 }
929 return rv;
930}
931
3bf26ce3
DP		 932int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
933{
934 nx_nic_req_t req;
935 u64 word;
936 int rv;
937
938 memset(&req, 0, sizeof(nx_nic_req_t));
939 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
940
941 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
942 req.req_hdr = cpu_to_le64(word);
22527864 943 req.words[0] = cpu_to_le64(enable | (enable << 8));
3bf26ce3
DP		 944
945 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
946 if (rv != 0) {
947 printk(KERN_ERR "%s: could not configure link notification\n",
948 adapter->netdev->name);
949 }
950
951 return rv;
952}
953
1bb482f8
NK		 954int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
955{
956 nx_nic_req_t req;
957 u64 word;
958 int rv;
959
34624d66
SC		 960 if (!test_bit(__NX_FW_ATTACHED, &adapter->state))
961 return 0;
962
1bb482f8
NK		 963 memset(&req, 0, sizeof(nx_nic_req_t));
964 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
965
966 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
967 ((u64)adapter->portnum << 16) |
968 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
969
970 req.req_hdr = cpu_to_le64(word);
971
972 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
973 if (rv != 0) {
974 printk(KERN_ERR "%s: could not cleanup lro flows\n",
975 adapter->netdev->name);
976 }
977 return rv;
978}
979
3d396eb1
AK		 980/*
981 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
982 * @returns 0 on success, negative on failure
983 */
c9fc891f
DP		 984
985#define MTU_FUDGE_FACTOR 100
986
3d396eb1
AK		 987int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
988{
3176ff3e 989 struct netxen_adapter *adapter = netdev_priv(netdev);
c9fc891f 990 int max_mtu;
9ad27643 991 int rc = 0;
3d396eb1 992
c9fc891f
DP		 993 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
994 max_mtu = P3_MAX_MTU;
995 else
996 max_mtu = P2_MAX_MTU;
997
998 if (mtu > max_mtu) {
999 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
1000 netdev->name, max_mtu);
3d396eb1
AK		 1001 return -EINVAL;
1002 }
1003
80922fbc 1004 if (adapter->set_mtu)
9ad27643 1005 rc = adapter->set_mtu(adapter, mtu);
3d396eb1 1006
9ad27643
DP		 1007 if (!rc)
1008 netdev->mtu = mtu;
c9fc891f 1009
9ad27643 1010 return rc;
3d396eb1
AK		 1011}
1012
3d396eb1 1013static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
f305f789 1014 int size, __le32 * buf)
3d396eb1 1015{
1e2d0059 1016 int i, v, addr;
f305f789 1017 __le32 *ptr32;
545fea54 1018 int ret;
3d396eb1
AK		 1019
1020 addr = base;
1021 ptr32 = buf;
1022 for (i = 0; i < size / sizeof(u32); i++) {
545fea54
DC		 1023 ret = netxen_rom_fast_read(adapter, addr, &v);
1024 if (ret)
1025 return ret;
1026
f305f789 1027 *ptr32 = cpu_to_le32(v);
3d396eb1
AK		 1028 ptr32++;
1029 addr += sizeof(u32);
1030 }
1031 if ((char *)buf + size > (char *)ptr32) {
f305f789 1032 __le32 local;
545fea54
DC		 1033 ret = netxen_rom_fast_read(adapter, addr, &v);
1034 if (ret)
1035 return ret;
f305f789 1036 local = cpu_to_le32(v);
3d396eb1
AK		 1037 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1038 }
1039
1040 return 0;
1041}
1042
a03d2451 1043int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac)
3d396eb1 1044{
9dc28efe
DP		 1045 __le32 *pmac = (__le32 *) mac;
1046 u32 offset;
3d396eb1 1047
06db58c0 1048 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
9dc28efe
DP		 1049
1050 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
3d396eb1 1051 return -1;
9dc28efe 1052
06d6c108 1053 if (*mac == ~0ULL) {
9dc28efe 1054
06db58c0
DP		 1055 offset = NX_OLD_MAC_ADDR_OFFSET +
1056 (adapter->portnum * sizeof(u64));
9dc28efe 1057
3d396eb1 1058 if (netxen_get_flash_block(adapter,
9dc28efe 1059 offset, sizeof(u64), pmac) == -1)
3d396eb1 1060 return -1;
9dc28efe 1061
06d6c108 1062 if (*mac == ~0ULL)
3d396eb1
AK		 1063 return -1;
1064 }
1065 return 0;
1066}
1067
a03d2451 1068int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac)
9dc28efe
DP		 1069{
1070 uint32_t crbaddr, mac_hi, mac_lo;
1071 int pci_func = adapter->ahw.pci_func;
1072
1073 crbaddr = CRB_MAC_BLOCK_START +
1074 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1075
f98a9f69
DP		 1076 mac_lo = NXRD32(adapter, crbaddr);
1077 mac_hi = NXRD32(adapter, crbaddr+4);
9dc28efe 1078
9dc28efe 1079 if (pci_func & 1)
2edbb454 1080 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
9dc28efe 1081 else
2edbb454 1082 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
9dc28efe
DP		 1083
1084 return 0;
1085}
1086
3d396eb1
AK		 1087/*
1088 * Changes the CRB window to the specified window.
1089 */
195c5f98 1090static void
907fa120
DP		 1091netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1092 u32 window)
3d396eb1
AK		 1093{
1094 void __iomem *offset;
907fa120
DP		 1095 int count = 10;
1096 u8 func = adapter->ahw.pci_func;
3d396eb1 1097
907fa120 1098 if (adapter->ahw.crb_win == window)
3d396eb1 1099 return;
907fa120 1100
e4c93c81
DP		 1101 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1102 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
3d396eb1 1103
907fa120
DP		 1104 writel(window, offset);
1105 do {
1106 if (window == readl(offset))
1107 break;
3d396eb1 1108
907fa120
DP		 1109 if (printk_ratelimit())
1110 dev_warn(&adapter->pdev->dev,
1111 "failed to set CRB window to %d\n",
1112 (window == NETXEN_WINDOW_ONE));
1113 udelay(1);
3d396eb1 1114
907fa120 1115 } while (--count > 0);
3d396eb1 1116
907fa120
DP		 1117 if (count > 0)
1118 adapter->ahw.crb_win = window;
3d396eb1
AK		 1119}
1120
3ce06a32 1121/*
7cecdca1 1122 * Returns < 0 if off is not valid,
3ce06a32
DP		 1123 * 1 if window access is needed. 'off' is set to offset from
1124 * CRB space in 128M pci map
1125 * 0 if no window access is needed. 'off' is set to 2M addr
1126 * In: 'off' is offset from base in 128M pci map
1127 */
1128static int
a9ac07de
DP		 1129netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1130 ulong off, void __iomem **addr)
3ce06a32 1131{
3ce06a32
DP		 1132 crb_128M_2M_sub_block_map_t *m;
1133
1134
a9ac07de 1135 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
7cecdca1 1136 return -EINVAL;
3ce06a32 1137
a9ac07de 1138 off -= NETXEN_PCI_CRBSPACE;
3ce06a32
DP		 1139
1140 /*
1141 * Try direct map
1142 */
a9ac07de 1143 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
3ce06a32 1144
a9ac07de
DP		 1145 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1146 *addr = adapter->ahw.pci_base0 + m->start_2M +
1147 (off - m->start_128M);
3ce06a32
DP		 1148 return 0;
1149 }
1150
1151 /*
1152 * Not in direct map, use crb window
1153 */
a9ac07de
DP		 1154 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1155 (off & MASK(16));
3ce06a32
DP		 1156 return 1;
1157}
1158
1159/*
1160 * In: 'off' is offset from CRB space in 128M pci map
1161 * Out: 'off' is 2M pci map addr
1162 * side effect: lock crb window
1163 */
1164static void
a9ac07de 1165netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32 1166{
907fa120
DP		 1167 u32 window;
1168 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
3ce06a32 1169
a9ac07de
DP		 1170 off -= NETXEN_PCI_CRBSPACE;
1171
1172 window = CRB_HI(off);
907fa120 1173
907fa120
DP		 1174 writel(window, addr);
1175 if (readl(addr) != window) {
1176 if (printk_ratelimit())
1177 dev_warn(&adapter->pdev->dev,
1178 "failed to set CRB window to %d off 0x%lx\n",
a9ac07de 1179 window, off);
3ce06a32 1180 }
3ce06a32
DP		 1181}
1182
f58dbd73
NK		 1183static void __iomem *
1184netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1185 ulong win_off, void __iomem **mem_ptr)
1186{
1187 ulong off = win_off;
1188 void __iomem *addr;
1189 resource_size_t mem_base;
1190
1191 if (ADDR_IN_WINDOW1(win_off))
1192 off = NETXEN_CRB_NORMAL(win_off);
1193
1194 addr = pci_base_offset(adapter, off);
1195 if (addr)
1196 return addr;
1197
1198 if (adapter->ahw.pci_len0 == 0)
1199 off -= NETXEN_PCI_CRBSPACE;
1200
1201 mem_base = pci_resource_start(adapter->pdev, 0);
1202 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1203 if (*mem_ptr)
1204 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1205
1206 return addr;
1207}
1208
195c5f98 1209static int
1fbe6323 1210netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
3d396eb1 1211{
195c5f98 1212 unsigned long flags;
f58dbd73 1213 void __iomem *addr, *mem_ptr = NULL;
3d396eb1 1214
f58dbd73
NK		 1215 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1216 if (!addr)
1217 return -EIO;
195c5f98 1218
f58dbd73 1219 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
f03b0ebd 1220 netxen_nic_io_write_128M(adapter, addr, data);
f58dbd73 1221 } else { /* Window 0 */
f03b0ebd 1222 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
907fa120 1223 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
195c5f98 1224 writel(data, addr);
907fa120
DP		 1225 netxen_nic_pci_set_crbwindow_128M(adapter,
1226 NETXEN_WINDOW_ONE);
f03b0ebd 1227 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
cb8011ad
AK		 1228 }
1229
f58dbd73
NK		 1230 if (mem_ptr)
1231 iounmap(mem_ptr);
1232
3d396eb1
AK		 1233 return 0;
1234}
1235
195c5f98 1236static u32
1fbe6323 1237netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
3d396eb1 1238{
195c5f98 1239 unsigned long flags;
f58dbd73 1240 void __iomem *addr, *mem_ptr = NULL;
1fbe6323 1241 u32 data;
d8313ce0 1242
f58dbd73
NK		 1243 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1244 if (!addr)
1245 return -EIO;
3d396eb1 1246
f58dbd73 1247 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
f03b0ebd 1248 data = netxen_nic_io_read_128M(adapter, addr);
f58dbd73 1249 } else { /* Window 0 */
f03b0ebd 1250 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
907fa120 1251 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
195c5f98 1252 data = readl(addr);
907fa120
DP		 1253 netxen_nic_pci_set_crbwindow_128M(adapter,
1254 NETXEN_WINDOW_ONE);
f03b0ebd 1255 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
195c5f98 1256 }
3d396eb1 1257
f58dbd73
NK		 1258 if (mem_ptr)
1259 iounmap(mem_ptr);
1260
1fbe6323 1261 return data;
3d396eb1
AK		 1262}
1263
195c5f98 1264static int
1fbe6323 1265netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
3ce06a32 1266{
195c5f98 1267 unsigned long flags;
3ce06a32 1268 int rv;
a9ac07de 1269 void __iomem *addr = NULL;
3d396eb1 1270
a9ac07de 1271 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
3d396eb1 1272
7cecdca1 1273 if (rv == 0) {
a9ac07de 1274 writel(data, addr);
7cecdca1 1275 return 0;
3ce06a32
DP		 1276 }
1277
7cecdca1
DP		 1278 if (rv > 0) {
1279 /* indirect access */
f03b0ebd 1280 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
3ce06a32 1281 crb_win_lock(adapter);
a9ac07de
DP		 1282 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1283 writel(data, addr);
3ce06a32 1284 crb_win_unlock(adapter);
f03b0ebd 1285 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
7cecdca1
DP		 1286 return 0;
1287 }
3ce06a32 1288
7cecdca1
DP		 1289 dev_err(&adapter->pdev->dev,
1290 "%s: invalid offset: 0x%016lx\n", __func__, off);
1291 dump_stack();
1292 return -EIO;
3d396eb1
AK		 1293}
1294
195c5f98 1295static u32
1fbe6323 1296netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
3ce06a32 1297{
195c5f98 1298 unsigned long flags;
3ce06a32 1299 int rv;
1fbe6323 1300 u32 data;
a9ac07de 1301 void __iomem *addr = NULL;
3d396eb1 1302
a9ac07de 1303 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
3ce06a32 1304
7cecdca1 1305 if (rv == 0)
a9ac07de 1306 return readl(addr);
3ce06a32 1307
7cecdca1
DP		 1308 if (rv > 0) {
1309 /* indirect access */
f03b0ebd 1310 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
3ce06a32 1311 crb_win_lock(adapter);
a9ac07de
DP		 1312 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1313 data = readl(addr);
3ce06a32 1314 crb_win_unlock(adapter);
f03b0ebd 1315 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
7cecdca1
DP		 1316 return data;
1317 }
3ce06a32 1318
7cecdca1
DP		 1319 dev_err(&adapter->pdev->dev,
1320 "%s: invalid offset: 0x%016lx\n", __func__, off);
1321 dump_stack();
1322 return -1;
3ce06a32
DP		 1323}
1324
195c5f98
AKS		 1325/* window 1 registers only */
1326static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1327 void __iomem *addr, u32 data)
3ce06a32 1328{
f03b0ebd 1329 read_lock(&adapter->ahw.crb_lock);
195c5f98 1330 writel(data, addr);
f03b0ebd 1331 read_unlock(&adapter->ahw.crb_lock);
195c5f98
AKS		 1332}
1333
1334static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1335 void __iomem *addr)
1336{
1337 u32 val;
1338
f03b0ebd 1339 read_lock(&adapter->ahw.crb_lock);
195c5f98 1340 val = readl(addr);
f03b0ebd 1341 read_unlock(&adapter->ahw.crb_lock);
195c5f98
AKS		 1342
1343 return val;
3ce06a32
DP		 1344}
1345
195c5f98
AKS		 1346static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1347 void __iomem *addr, u32 data)
3ce06a32 1348{
195c5f98
AKS		 1349 writel(data, addr);
1350}
1351
1352static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1353 void __iomem *addr)
1354{
1355 return readl(addr);
1356}
1357
1358void __iomem *
1359netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1360{
a9ac07de 1361 void __iomem *addr = NULL;
195c5f98
AKS		 1362
1363 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
a9ac07de
DP		 1364 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1365 (offset > NETXEN_CRB_PCIX_HOST))
1366 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1367 else
1368 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1369 } else {
1370 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1371 offset, &addr));
195c5f98
AKS		 1372 }
1373
a9ac07de 1374 return addr;
3ce06a32
DP		 1375}
1376
47abe356
DP		 1377static int
1378netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1379 u64 addr, u32 *start)
3ce06a32 1380{
47abe356
DP		 1381 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1382 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1383 return 0;
3ce06a32 1384 } else if (ADDR_IN_RANGE(addr,
47abe356
DP		 1385 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1386 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1387 return 0;
1388 }
3ce06a32 1389
47abe356
DP		 1390 return -EIO;
1391}
3ce06a32 1392
47abe356
DP		 1393static int
1394netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1395 u64 addr, u32 *start)
1396{
6abb4b83 1397 u32 window;
3ce06a32 1398
14e2cfbb 1399 window = OCM_WIN(addr);
6abb4b83 1400
47abe356 1401 writel(window, adapter->ahw.ocm_win_crb);
6abb4b83
AKS		 1402 /* read back to flush */
1403 readl(adapter->ahw.ocm_win_crb);
47abe356
DP		 1404
1405 adapter->ahw.ocm_win = window;
1406 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1407 return 0;
3ce06a32 1408}
47abe356
DP		 1409
1410static int
1411netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1412 u64 *data, int op)
1413{
1414 void __iomem *addr, *mem_ptr = NULL;
1415 resource_size_t mem_base;
14e2cfbb 1416 int ret;
47abe356
DP		 1417 u32 start;
1418
f03b0ebd 1419 spin_lock(&adapter->ahw.mem_lock);
47abe356
DP		 1420
1421 ret = adapter->pci_set_window(adapter, off, &start);
1422 if (ret != 0)
1423 goto unlock;
1424
14e2cfbb
SC		 1425 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1426 addr = adapter->ahw.pci_base0 + start;
1427 } else {
1428 addr = pci_base_offset(adapter, start);
1429 if (addr)
1430 goto noremap;
1431
1432 mem_base = pci_resource_start(adapter->pdev, 0) +
1433 (start & PAGE_MASK);
1434 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1435 if (mem_ptr == NULL) {
1436 ret = -EIO;
1437 goto unlock;
1438 }
47abe356 1439
14e2cfbb 1440 addr = mem_ptr + (start & (PAGE_SIZE-1));
3d396eb1 1441 }
47abe356
DP		 1442noremap:
1443 if (op == 0) /* read */
1444 *data = readq(addr);
1445 else /* write */
1446 writeq(*data, addr);
1447
1448unlock:
f03b0ebd
DP		 1449 spin_unlock(&adapter->ahw.mem_lock);
1450
47abe356
DP		 1451 if (mem_ptr)
1452 iounmap(mem_ptr);
1453 return ret;
3d396eb1
AK		 1454}
1455
0b9715e6
AKS		 1456void
1457netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data)
1458{
1459 void __iomem *addr = adapter->ahw.pci_base0 +
1460 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1461
1462 spin_lock(&adapter->ahw.mem_lock);
1463 *data = readq(addr);
1464 spin_unlock(&adapter->ahw.mem_lock);
1465}
1466
1467void
1468netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data)
1469{
1470 void __iomem *addr = adapter->ahw.pci_base0 +
1471 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1472
1473 spin_lock(&adapter->ahw.mem_lock);
1474 writeq(data, addr);
1475 spin_unlock(&adapter->ahw.mem_lock);
1476}
1477
3ce06a32
DP		 1478#define MAX_CTL_CHECK 1000
1479
195c5f98 1480static int
3ce06a32 1481netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1f5e055d 1482 u64 off, u64 data)
3ce06a32 1483{
1f5e055d
AKS		 1484 int j, ret;
1485 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
d8313ce0 1486 void __iomem *mem_crb;
3ce06a32 1487
1f5e055d
AKS		 1488 /* Only 64-bit aligned access */
1489 if (off & 7)
ea6828b8
DP		 1490 return -EIO;
1491
1f5e055d 1492 /* P2 has different SIU and MIU test agent base addr */
ea6828b8
DP		 1493 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1494 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1f5e055d
AKS		 1495 mem_crb = pci_base_offset(adapter,
1496 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1497 addr_hi = SIU_TEST_AGT_ADDR_HI;
1498 data_lo = SIU_TEST_AGT_WRDATA_LO;
1499 data_hi = SIU_TEST_AGT_WRDATA_HI;
1500 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1501 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
ea6828b8
DP		 1502 goto correct;
1503 }
3ce06a32 1504
ea6828b8 1505 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1506 mem_crb = pci_base_offset(adapter,
1507 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1508 addr_hi = MIU_TEST_AGT_ADDR_HI;
1509 data_lo = MIU_TEST_AGT_WRDATA_LO;
1510 data_hi = MIU_TEST_AGT_WRDATA_HI;
1511 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1512 off_hi = 0;
ea6828b8
DP		 1513 goto correct;
1514 }
1515
47abe356
DP		 1516 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1517 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1518 if (adapter->ahw.pci_len0 != 0) {
1519 return netxen_nic_pci_mem_access_direct(adapter,
1520 off, &data, 1);
1521 }
1522 }
1523
ea6828b8
DP		 1524 return -EIO;
1525
1526correct:
f03b0ebd 1527 spin_lock(&adapter->ahw.mem_lock);
907fa120 1528 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
3ce06a32 1529
1f5e055d
AKS		 1530 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1531 writel(off_hi, (mem_crb + addr_hi));
1532 writel(data & 0xffffffff, (mem_crb + data_lo));
1533 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1534 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1535 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1536 (mem_crb + TEST_AGT_CTRL));
1537
1538 for (j = 0; j < MAX_CTL_CHECK; j++) {
1539 temp = readl((mem_crb + TEST_AGT_CTRL));
1540 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1541 break;
3ce06a32
DP		 1542 }
1543
1f5e055d
AKS		 1544 if (j >= MAX_CTL_CHECK) {
1545 if (printk_ratelimit())
1546 dev_err(&adapter->pdev->dev,
1547 "failed to write through agent\n");
1548 ret = -EIO;
1549 } else
1550 ret = 0;
1551
907fa120 1552 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
f03b0ebd 1553 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32
DP		 1554 return ret;
1555}
1556
195c5f98 1557static int
3ce06a32 1558netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1f5e055d 1559 u64 off, u64 *data)
3ce06a32 1560{
1f5e055d
AKS		 1561 int j, ret;
1562 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1563 u64 val;
d8313ce0 1564 void __iomem *mem_crb;
3ce06a32 1565
1f5e055d
AKS		 1566 /* Only 64-bit aligned access */
1567 if (off & 7)
ea6828b8
DP		 1568 return -EIO;
1569
1f5e055d 1570 /* P2 has different SIU and MIU test agent base addr */
ea6828b8
DP		 1571 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1572 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1f5e055d
AKS		 1573 mem_crb = pci_base_offset(adapter,
1574 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1575 addr_hi = SIU_TEST_AGT_ADDR_HI;
1576 data_lo = SIU_TEST_AGT_RDDATA_LO;
1577 data_hi = SIU_TEST_AGT_RDDATA_HI;
1578 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1579 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
ea6828b8
DP		 1580 goto correct;
1581 }
3ce06a32 1582
ea6828b8 1583 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1584 mem_crb = pci_base_offset(adapter,
1585 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1586 addr_hi = MIU_TEST_AGT_ADDR_HI;
1587 data_lo = MIU_TEST_AGT_RDDATA_LO;
1588 data_hi = MIU_TEST_AGT_RDDATA_HI;
1589 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1590 off_hi = 0;
ea6828b8
DP		 1591 goto correct;
1592 }
1593
47abe356
DP		 1594 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1595 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1596 if (adapter->ahw.pci_len0 != 0) {
1597 return netxen_nic_pci_mem_access_direct(adapter,
1598 off, data, 0);
1599 }
1600 }
1601
ea6828b8 1602 return -EIO;
3ce06a32 1603
ea6828b8 1604correct:
f03b0ebd 1605 spin_lock(&adapter->ahw.mem_lock);
907fa120 1606 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
3ce06a32 1607
1f5e055d
AKS		 1608 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1609 writel(off_hi, (mem_crb + addr_hi));
1610 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1611 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
3ce06a32 1612
1f5e055d
AKS		 1613 for (j = 0; j < MAX_CTL_CHECK; j++) {
1614 temp = readl(mem_crb + TEST_AGT_CTRL);
1615 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1616 break;
1f5e055d 1617 }
3ce06a32 1618
1f5e055d
AKS		 1619 if (j >= MAX_CTL_CHECK) {
1620 if (printk_ratelimit())
1621 dev_err(&adapter->pdev->dev,
1622 "failed to read through agent\n");
1623 ret = -EIO;
1624 } else {
1625
1626 temp = readl(mem_crb + data_hi);
1627 val = ((u64)temp << 32);
1628 val |= readl(mem_crb + data_lo);
1629 *data = val;
1630 ret = 0;
3ce06a32
DP		 1631 }
1632
907fa120 1633 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
f03b0ebd 1634 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32 1635
1f5e055d 1636 return ret;
3ce06a32
DP		 1637}
1638
195c5f98 1639static int
3ce06a32 1640netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1f5e055d 1641 u64 off, u64 data)
3ce06a32 1642{
215387a4 1643 int j, ret;
1f5e055d 1644 u32 temp, off8;
ea6828b8 1645 void __iomem *mem_crb;
3ce06a32 1646
1f5e055d
AKS		 1647 /* Only 64-bit aligned access */
1648 if (off & 7)
ea6828b8
DP		 1649 return -EIO;
1650
1f5e055d 1651 /* P3 onward, test agent base for MIU and SIU is same */
ea6828b8
DP		 1652 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1653 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1f5e055d
AKS		 1654 mem_crb = netxen_get_ioaddr(adapter,
1655 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
ea6828b8
DP		 1656 goto correct;
1657 }
1658
1659 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1660 mem_crb = netxen_get_ioaddr(adapter,
1661 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
ea6828b8 1662 goto correct;
3ce06a32
DP		 1663 }
1664
47abe356
DP		 1665 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1666 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1667
ea6828b8
DP		 1668 return -EIO;
1669
1670correct:
215387a4 1671 off8 = off & 0xfffffff8;
3ce06a32 1672
f03b0ebd 1673 spin_lock(&adapter->ahw.mem_lock);
3ce06a32 1674
1f5e055d
AKS		 1675 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1676 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
fb1f6a43 1677
fb1f6a43 1678 writel(data & 0xffffffff,
215387a4 1679 mem_crb + MIU_TEST_AGT_WRDATA_LO);
fb1f6a43 1680 writel((data >> 32) & 0xffffffff,
215387a4 1681 mem_crb + MIU_TEST_AGT_WRDATA_HI);
fb1f6a43 1682
1f5e055d
AKS		 1683 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1684 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1685 (mem_crb + TEST_AGT_CTRL));
1686
1687 for (j = 0; j < MAX_CTL_CHECK; j++) {
1688 temp = readl(mem_crb + TEST_AGT_CTRL);
1689 if ((temp & TA_CTL_BUSY) == 0)
1690 break;
3ce06a32
DP		 1691 }
1692
1f5e055d
AKS		 1693 if (j >= MAX_CTL_CHECK) {
1694 if (printk_ratelimit())
1695 dev_err(&adapter->pdev->dev,
39754f44 1696 "failed to write through agent\n");
1f5e055d
AKS		 1697 ret = -EIO;
1698 } else
1699 ret = 0;
1700
f03b0ebd 1701 spin_unlock(&adapter->ahw.mem_lock);
3ce06a32 1702
3ce06a32
DP		 1703 return ret;
1704}
1705
195c5f98 1706static int
3ce06a32 1707netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1f5e055d 1708 u64 off, u64 *data)
3ce06a32 1709{
1f5e055d
AKS		 1710 int j, ret;
1711 u32 temp, off8;
215387a4 1712 u64 val;
ea6828b8 1713 void __iomem *mem_crb;
3ce06a32 1714
1f5e055d
AKS		 1715 /* Only 64-bit aligned access */
1716 if (off & 7)
ea6828b8 1717 return -EIO;
3ce06a32 1718
1f5e055d 1719 /* P3 onward, test agent base for MIU and SIU is same */
ea6828b8
DP		 1720 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1721 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1f5e055d
AKS		 1722 mem_crb = netxen_get_ioaddr(adapter,
1723 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
ea6828b8 1724 goto correct;
3ce06a32
DP		 1725 }
1726
ea6828b8 1727 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1f5e055d
AKS		 1728 mem_crb = netxen_get_ioaddr(adapter,
1729 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
ea6828b8
DP		 1730 goto correct;
1731 }
1732
907fa120
DP		 1733 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1734 return netxen_nic_pci_mem_access_direct(adapter,
1735 off, data, 0);
1736 }
47abe356 1737
ea6828b8
DP		 1738 return -EIO;
1739
1740correct:
215387a4 1741 off8 = off & 0xfffffff8;
3ce06a32 1742
f03b0ebd 1743 spin_lock(&adapter->ahw.mem_lock);
3ce06a32 1744
1f5e055d
AKS		 1745 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1746 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1747 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1748 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
3ce06a32 1749
1f5e055d
AKS		 1750 for (j = 0; j < MAX_CTL_CHECK; j++) {
1751 temp = readl(mem_crb + TEST_AGT_CTRL);
1752 if ((temp & TA_CTL_BUSY) == 0)
3ce06a32 1753 break;
3ce06a32
DP		 1754 }
1755
1f5e055d
AKS		 1756 if (j >= MAX_CTL_CHECK) {
1757 if (printk_ratelimit())
1758 dev_err(&adapter->pdev->dev,
1759 "failed to read through agent\n");
1760 ret = -EIO;
3ce06a32 1761 } else {
215387a4
SC		 1762 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32;
1763 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);
1f5e055d
AKS		 1764 *data = val;
1765 ret = 0;
3ce06a32
DP		 1766 }
1767
f03b0ebd 1768 spin_unlock(&adapter->ahw.mem_lock);
1f5e055d
AKS		 1769
1770 return ret;
3ce06a32
DP		 1771}
1772
195c5f98
AKS		 1773void
1774netxen_setup_hwops(struct netxen_adapter *adapter)
3ce06a32 1775{
195c5f98
AKS		 1776 adapter->init_port = netxen_niu_xg_init_port;
1777 adapter->stop_port = netxen_niu_disable_xg_port;
3ce06a32 1778
195c5f98
AKS		 1779 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1780 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1781 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1782 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1783 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1784 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1785 adapter->io_read = netxen_nic_io_read_128M,
1786 adapter->io_write = netxen_nic_io_write_128M,
1787
1788 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1789 adapter->set_multi = netxen_p2_nic_set_multi;
1790 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1791 adapter->set_promisc = netxen_p2_nic_set_promisc;
3ce06a32 1792
195c5f98
AKS		 1793 } else {
1794 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1795 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1796 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1797 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1798 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1799 adapter->io_read = netxen_nic_io_read_2M,
1800 adapter->io_write = netxen_nic_io_write_2M,
1801
1802 adapter->set_mtu = nx_fw_cmd_set_mtu;
1803 adapter->set_promisc = netxen_p3_nic_set_promisc;
1804 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1805 adapter->set_multi = netxen_p3_nic_set_multi;
1806
1807 adapter->phy_read = nx_fw_cmd_query_phy;
1808 adapter->phy_write = nx_fw_cmd_set_phy;
1809 }
3ce06a32
DP		 1810}
1811
3d396eb1
AK		 1812int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1813{
0dc6d9cb 1814 int offset, board_type, magic;
1e2d0059 1815 struct pci_dev *pdev = adapter->pdev;
3d396eb1 1816
06db58c0 1817 offset = NX_FW_MAGIC_OFFSET;
1e2d0059
DP		 1818 if (netxen_rom_fast_read(adapter, offset, &magic))
1819 return -EIO;
3d396eb1 1820
0dc6d9cb
DP		 1821 if (magic != NETXEN_BDINFO_MAGIC) {
1822 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1823 magic);
1e2d0059 1824 return -EIO;
3d396eb1
AK		 1825 }
1826
06db58c0 1827 offset = NX_BRDTYPE_OFFSET;
1e2d0059
DP		 1828 if (netxen_rom_fast_read(adapter, offset, &board_type))
1829 return -EIO;
1830
1e2d0059 1831 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
f98a9f69 1832 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
c7860a2a 1833 if ((gpio & 0x8000) == 0)
1e2d0059 1834 board_type = NETXEN_BRDTYPE_P3_10G_TP;
c7860a2a
DP		 1835 }
1836
dce87b96 1837 adapter->ahw.board_type = board_type;
1838
e98e3350 1839 switch (board_type) {
3d396eb1 1840 case NETXEN_BRDTYPE_P2_SB35_4G:
1e2d0059 1841 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1
AK		 1842 break;
1843 case NETXEN_BRDTYPE_P2_SB31_10G:
1844 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1845 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1846 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
e4c93c81
DP		 1847 case NETXEN_BRDTYPE_P3_HMEZ:
1848 case NETXEN_BRDTYPE_P3_XG_LOM:
1849 case NETXEN_BRDTYPE_P3_10G_CX4:
1850 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1851 case NETXEN_BRDTYPE_P3_IMEZ:
1852 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
a70f9393
DP		 1853 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1854 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
e4c93c81
DP		 1855 case NETXEN_BRDTYPE_P3_10G_XFP:
1856 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1e2d0059 1857 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1858 break;
1859 case NETXEN_BRDTYPE_P1_BD:
1860 case NETXEN_BRDTYPE_P1_SB:
1861 case NETXEN_BRDTYPE_P1_SMAX:
1862 case NETXEN_BRDTYPE_P1_SOCK:
e4c93c81
DP		 1863 case NETXEN_BRDTYPE_P3_REF_QG:
1864 case NETXEN_BRDTYPE_P3_4_GB:
1865 case NETXEN_BRDTYPE_P3_4_GB_MM:
1e2d0059 1866 adapter->ahw.port_type = NETXEN_NIC_GBE;
3d396eb1 1867 break;
c7860a2a 1868 case NETXEN_BRDTYPE_P3_10G_TP:
1e2d0059 1869 adapter->ahw.port_type = (adapter->portnum < 2) ?
c7860a2a
DP		 1870 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1871 break;
3d396eb1 1872 default:
1e2d0059
DP		 1873 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1874 adapter->ahw.port_type = NETXEN_NIC_XGBE;
3d396eb1
AK		 1875 break;
1876 }
1877
1e2d0059 1878 return 0;
3d396eb1
AK		 1879}
1880
1881/* NIU access sections */
7e12bb0a 1882static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
3d396eb1 1883{
9ad27643 1884 new_mtu += MTU_FUDGE_FACTOR;
3276fbad 1885 if (adapter->physical_port == 0)
f98a9f69 1886 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
4790654c 1887 else
f98a9f69 1888 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
3d396eb1
AK		 1889 return 0;
1890}
1891
3176ff3e 1892void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
3d396eb1 1893{
a608ab9c
AV		 1894 __u32 status;
1895 __u32 autoneg;
24a7a455 1896 __u32 port_mode;
3d396eb1 1897
c7860a2a
DP		 1898 if (!netif_carrier_ok(adapter->netdev)) {
1899 adapter->link_speed = 0;
1900 adapter->link_duplex = -1;
1901 adapter->link_autoneg = AUTONEG_ENABLE;
1902 return;
1903 }
24a7a455 1904
1e2d0059 1905 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
f98a9f69 1906 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
24a7a455
DP		 1907 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1908 adapter->link_speed = SPEED_1000;
1909 adapter->link_duplex = DUPLEX_FULL;
1910 adapter->link_autoneg = AUTONEG_DISABLE;
1911 return;
1912 }
1913
8e95a202
JP		 1914 if (adapter->phy_read &&
1915 adapter->phy_read(adapter,
1916 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1917 &status) == 0) {
3d396eb1
AK		 1918 if (netxen_get_phy_link(status)) {
1919 switch (netxen_get_phy_speed(status)) {
1920 case 0:
3176ff3e 1921 adapter->link_speed = SPEED_10;
3d396eb1
AK		 1922 break;
1923 case 1:
3176ff3e 1924 adapter->link_speed = SPEED_100;
3d396eb1
AK		 1925 break;
1926 case 2:
3176ff3e 1927 adapter->link_speed = SPEED_1000;
3d396eb1
AK		 1928 break;
1929 default:
c7860a2a 1930 adapter->link_speed = 0;
3d396eb1
AK		 1931 break;
1932 }
1933 switch (netxen_get_phy_duplex(status)) {
1934 case 0:
3176ff3e 1935 adapter->link_duplex = DUPLEX_HALF;
3d396eb1
AK		 1936 break;
1937 case 1:
3176ff3e 1938 adapter->link_duplex = DUPLEX_FULL;
3d396eb1
AK		 1939 break;
1940 default:
3176ff3e 1941 adapter->link_duplex = -1;
3d396eb1
AK		 1942 break;
1943 }
8e95a202
JP		 1944 if (adapter->phy_read &&
1945 adapter->phy_read(adapter,
1946 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1c755ffa 1947 &autoneg) == 0)
3176ff3e 1948 adapter->link_autoneg = autoneg;
3d396eb1
AK		 1949 } else
1950 goto link_down;
1951 } else {
1952 link_down:
c7860a2a 1953 adapter->link_speed = 0;
3176ff3e 1954 adapter->link_duplex = -1;
3d396eb1
AK		 1955 }
1956 }
1957}
1958
0b72e659
DP		 1959int
1960netxen_nic_wol_supported(struct netxen_adapter *adapter)
1961{
1962 u32 wol_cfg;
1963
1964 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1965 return 0;
1966
f98a9f69 1967 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
0b72e659 1968 if (wol_cfg & (1UL << adapter->portnum)) {
f98a9f69 1969 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
0b72e659
DP		 1970 if (wol_cfg & (1 << adapter->portnum))
1971 return 1;
1972 }
1973
1974 return 0;
1975}
83f18a55
M		 1976
1977static u32 netxen_md_cntrl(struct netxen_adapter *adapter,
1978 struct netxen_minidump_template_hdr *template_hdr,
1979 struct netxen_minidump_entry_crb *crtEntry)
1980{
1981 int loop_cnt, i, rv = 0, timeout_flag;
1982 u32 op_count, stride;
1983 u32 opcode, read_value, addr;
1984 unsigned long timeout, timeout_jiffies;
1985 addr = crtEntry->addr;
1986 op_count = crtEntry->op_count;
1987 stride = crtEntry->addr_stride;
1988
1989 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
1990 for (i = 0; i < sizeof(crtEntry->opcode) * 8; i++) {
1991 opcode = (crtEntry->opcode & (0x1 << i));
1992 if (opcode) {
1993 switch (opcode) {
1994 case NX_DUMP_WCRB:
1995 NX_WR_DUMP_REG(addr,
1996 adapter->ahw.pci_base0,
1997 crtEntry->value_1);
1998 break;
1999 case NX_DUMP_RWCRB:
2000 NX_RD_DUMP_REG(addr,
2001 adapter->ahw.pci_base0,
2002 &read_value);
2003 NX_WR_DUMP_REG(addr,
2004 adapter->ahw.pci_base0,
2005 read_value);
2006 break;
2007 case NX_DUMP_ANDCRB:
2008 NX_RD_DUMP_REG(addr,
2009 adapter->ahw.pci_base0,
2010 &read_value);
2011 read_value &= crtEntry->value_2;
2012 NX_WR_DUMP_REG(addr,
2013 adapter->ahw.pci_base0,
2014 read_value);
2015 break;
2016 case NX_DUMP_ORCRB:
2017 NX_RD_DUMP_REG(addr,
2018 adapter->ahw.pci_base0,
2019 &read_value);
2020 read_value |= crtEntry->value_3;
2021 NX_WR_DUMP_REG(addr,
2022 adapter->ahw.pci_base0,
2023 read_value);
2024 break;
2025 case NX_DUMP_POLLCRB:
2026 timeout = crtEntry->poll_timeout;
2027 NX_RD_DUMP_REG(addr,
2028 adapter->ahw.pci_base0,
2029 &read_value);
2030 timeout_jiffies =
2031 msecs_to_jiffies(timeout) + jiffies;
2032 for (timeout_flag = 0;
2033 !timeout_flag
2034 && ((read_value & crtEntry->value_2)
2035 != crtEntry->value_1);) {
2036 if (time_after(jiffies,
2037 timeout_jiffies))
2038 timeout_flag = 1;
2039 NX_RD_DUMP_REG(addr,
2040 adapter->ahw.pci_base0,
2041 &read_value);
2042 }
2043
2044 if (timeout_flag) {
2045 dev_err(&adapter->pdev->dev, "%s : "
2046 "Timeout in poll_crb control operation.\n"
2047 , __func__);
2048 return -1;
2049 }
2050 break;
2051 case NX_DUMP_RD_SAVE:
2052 /* Decide which address to use */
2053 if (crtEntry->state_index_a)
2054 addr =
2055 template_hdr->saved_state_array
2056 [crtEntry->state_index_a];
2057 NX_RD_DUMP_REG(addr,
2058 adapter->ahw.pci_base0,
2059 &read_value);
2060 template_hdr->saved_state_array
2061 [crtEntry->state_index_v]
2062 = read_value;
2063 break;
2064 case NX_DUMP_WRT_SAVED:
2065 /* Decide which value to use */
2066 if (crtEntry->state_index_v)
2067 read_value =
2068 template_hdr->saved_state_array
2069 [crtEntry->state_index_v];
2070 else
2071 read_value = crtEntry->value_1;
2072
2073 /* Decide which address to use */
2074 if (crtEntry->state_index_a)
2075 addr =
2076 template_hdr->saved_state_array
2077 [crtEntry->state_index_a];
2078
2079 NX_WR_DUMP_REG(addr,
2080 adapter->ahw.pci_base0,
2081 read_value);
2082 break;
2083 case NX_DUMP_MOD_SAVE_ST:
2084 read_value =
2085 template_hdr->saved_state_array
2086 [crtEntry->state_index_v];
2087 read_value <<= crtEntry->shl;
2088 read_value >>= crtEntry->shr;
2089 if (crtEntry->value_2)
2090 read_value &=
2091 crtEntry->value_2;
2092 read_value |= crtEntry->value_3;
2093 read_value += crtEntry->value_1;
2094 /* Write value back to state area.*/
2095 template_hdr->saved_state_array
2096 [crtEntry->state_index_v]
2097 = read_value;
2098 break;
2099 default:
2100 rv = 1;
2101 break;
2102 }
2103 }
2104 }
2105 addr = addr + stride;
2106 }
2107 return rv;
2108}
2109
2110/* Read memory or MN */
2111static u32
2112netxen_md_rdmem(struct netxen_adapter *adapter,
2113 struct netxen_minidump_entry_rdmem
2114 *memEntry, u64 *data_buff)
2115{
2116 u64 addr, value = 0;
2117 int i = 0, loop_cnt;
2118
2119 addr = (u64)memEntry->read_addr;
2120 loop_cnt = memEntry->read_data_size; /* This is size in bytes */
2121 loop_cnt /= sizeof(value);
2122
2123 for (i = 0; i < loop_cnt; i++) {
2124 if (netxen_nic_pci_mem_read_2M(adapter, addr, &value))
2125 goto out;
2126 *data_buff++ = value;
2127 addr += sizeof(value);
2128 }
2129out:
2130 return i * sizeof(value);
2131}
2132
2133/* Read CRB operation */
2134static u32 netxen_md_rd_crb(struct netxen_adapter *adapter,
2135 struct netxen_minidump_entry_crb
2136 *crbEntry, u32 *data_buff)
2137{
2138 int loop_cnt;
2139 u32 op_count, addr, stride, value;
2140
2141 addr = crbEntry->addr;
2142 op_count = crbEntry->op_count;
2143 stride = crbEntry->addr_stride;
2144
2145 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
2146 NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0, &value);
2147 *data_buff++ = addr;
2148 *data_buff++ = value;
2149 addr = addr + stride;
2150 }
2151 return loop_cnt * (2 * sizeof(u32));
2152}
2153
2154/* Read ROM */
2155static u32
2156netxen_md_rdrom(struct netxen_adapter *adapter,
2157 struct netxen_minidump_entry_rdrom
06d6c108 2158 *romEntry, __le32 *data_buff)
83f18a55
M		 2159{
2160 int i, count = 0;
2161 u32 size, lck_val;
2162 u32 val;
2163 u32 fl_addr, waddr, raddr;
2164 fl_addr = romEntry->read_addr;
2165 size = romEntry->read_data_size/4;
2166lock_try:
2167 lck_val = readl((void __iomem *)(adapter->ahw.pci_base0 +
2168 NX_FLASH_SEM2_LK));
2169 if (!lck_val && count < MAX_CTL_CHECK) {
2170 msleep(20);
2171 count++;
2172 goto lock_try;
2173 }
2174 writel(adapter->ahw.pci_func, (void __iomem *)(adapter->ahw.pci_base0 +
2175 NX_FLASH_LOCK_ID));
2176 for (i = 0; i < size; i++) {
2177 waddr = fl_addr & 0xFFFF0000;
2178 NX_WR_DUMP_REG(FLASH_ROM_WINDOW, adapter->ahw.pci_base0, waddr);
2179 raddr = FLASH_ROM_DATA + (fl_addr & 0x0000FFFF);
2180 NX_RD_DUMP_REG(raddr, adapter->ahw.pci_base0, &val);
2181 *data_buff++ = cpu_to_le32(val);
2182 fl_addr += sizeof(val);
2183 }
2184 readl((void __iomem *)(adapter->ahw.pci_base0 + NX_FLASH_SEM2_ULK));
2185 return romEntry->read_data_size;
2186}
2187
2188/* Handle L2 Cache */
2189static u32
2190netxen_md_L2Cache(struct netxen_adapter *adapter,
2191 struct netxen_minidump_entry_cache
2192 *cacheEntry, u32 *data_buff)
2193{
2194 int loop_cnt, i, k, timeout_flag = 0;
2195 u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr;
2196 u32 tag_value, read_cnt;
2197 u8 cntl_value_w, cntl_value_r;
2198 unsigned long timeout, timeout_jiffies;
2199
2200 loop_cnt = cacheEntry->op_count;
2201 read_addr = cacheEntry->read_addr;
2202 cntrl_addr = cacheEntry->control_addr;
2203 cntl_value_w = (u32) cacheEntry->write_value;
2204 tag_reg_addr = cacheEntry->tag_reg_addr;
2205 tag_value = cacheEntry->init_tag_value;
2206 read_cnt = cacheEntry->read_addr_cnt;
2207
2208 for (i = 0; i < loop_cnt; i++) {
2209 NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value);
2210 if (cntl_value_w)
2211 NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2212 (u32)cntl_value_w);
2213 if (cacheEntry->poll_mask) {
2214 timeout = cacheEntry->poll_wait;
2215 NX_RD_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2216 &cntl_value_r);
2217 timeout_jiffies = msecs_to_jiffies(timeout) + jiffies;
2218 for (timeout_flag = 0; !timeout_flag &&
2219 ((cntl_value_r & cacheEntry->poll_mask) != 0);) {
2220 if (time_after(jiffies, timeout_jiffies))
2221 timeout_flag = 1;
2222 NX_RD_DUMP_REG(cntrl_addr,
2223 adapter->ahw.pci_base0,
2224 &cntl_value_r);
2225 }
2226 if (timeout_flag) {
2227 dev_err(&adapter->pdev->dev,
2228 "Timeout in processing L2 Tag poll.\n");
2229 return -1;
2230 }
2231 }
2232 addr = read_addr;
2233 for (k = 0; k < read_cnt; k++) {
2234 NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0,
2235 &read_value);
2236 *data_buff++ = read_value;
2237 addr += cacheEntry->read_addr_stride;
2238 }
2239 tag_value += cacheEntry->tag_value_stride;
2240 }
2241 return read_cnt * loop_cnt * sizeof(read_value);
2242}
2243
2244
2245/* Handle L1 Cache */
2246static u32 netxen_md_L1Cache(struct netxen_adapter *adapter,
2247 struct netxen_minidump_entry_cache
2248 *cacheEntry, u32 *data_buff)
2249{
2250 int i, k, loop_cnt;
2251 u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr;
2252 u32 tag_value, read_cnt;
2253 u8 cntl_value_w;
2254
2255 loop_cnt = cacheEntry->op_count;
2256 read_addr = cacheEntry->read_addr;
2257 cntrl_addr = cacheEntry->control_addr;
2258 cntl_value_w = (u32) cacheEntry->write_value;
2259 tag_reg_addr = cacheEntry->tag_reg_addr;
2260 tag_value = cacheEntry->init_tag_value;
2261 read_cnt = cacheEntry->read_addr_cnt;
2262
2263 for (i = 0; i < loop_cnt; i++) {
2264 NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value);
2265 NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2266 (u32) cntl_value_w);
2267 addr = read_addr;
2268 for (k = 0; k < read_cnt; k++) {
2269 NX_RD_DUMP_REG(addr,
2270 adapter->ahw.pci_base0,
2271 &read_value);
2272 *data_buff++ = read_value;
2273 addr += cacheEntry->read_addr_stride;
2274 }
2275 tag_value += cacheEntry->tag_value_stride;
2276 }
2277 return read_cnt * loop_cnt * sizeof(read_value);
2278}
2279
2280/* Reading OCM memory */
2281static u32
2282netxen_md_rdocm(struct netxen_adapter *adapter,
2283 struct netxen_minidump_entry_rdocm
2284 *ocmEntry, u32 *data_buff)
2285{
2286 int i, loop_cnt;
2287 u32 value;
2288 void __iomem *addr;
2289 addr = (ocmEntry->read_addr + adapter->ahw.pci_base0);
2290 loop_cnt = ocmEntry->op_count;
2291
2292 for (i = 0; i < loop_cnt; i++) {
2293 value = readl(addr);
2294 *data_buff++ = value;
2295 addr += ocmEntry->read_addr_stride;
2296 }
2297 return i * sizeof(u32);
2298}
2299
2300/* Read MUX data */
2301static u32
2302netxen_md_rdmux(struct netxen_adapter *adapter, struct netxen_minidump_entry_mux
2303 *muxEntry, u32 *data_buff)
2304{
2305 int loop_cnt = 0;
2306 u32 read_addr, read_value, select_addr, sel_value;
2307
2308 read_addr = muxEntry->read_addr;
2309 sel_value = muxEntry->select_value;
2310 select_addr = muxEntry->select_addr;
2311
2312 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) {
2313 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, sel_value);
2314 NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0, &read_value);
2315 *data_buff++ = sel_value;
2316 *data_buff++ = read_value;
2317 sel_value += muxEntry->select_value_stride;
2318 }
2319 return loop_cnt * (2 * sizeof(u32));
2320}
2321
2322/* Handling Queue State Reads */
2323static u32
2324netxen_md_rdqueue(struct netxen_adapter *adapter,
2325 struct netxen_minidump_entry_queue
2326 *queueEntry, u32 *data_buff)
2327{
2328 int loop_cnt, k;
2329 u32 queue_id, read_addr, read_value, read_stride, select_addr, read_cnt;
2330
2331 read_cnt = queueEntry->read_addr_cnt;
2332 read_stride = queueEntry->read_addr_stride;
2333 select_addr = queueEntry->select_addr;
2334
2335 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count;
2336 loop_cnt++) {
2337 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, queue_id);
2338 read_addr = queueEntry->read_addr;
2339 for (k = 0; k < read_cnt; k--) {
2340 NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0,
2341 &read_value);
2342 *data_buff++ = read_value;
2343 read_addr += read_stride;
2344 }
2345 queue_id += queueEntry->queue_id_stride;
2346 }
2347 return loop_cnt * (read_cnt * sizeof(read_value));
2348}
2349
2350
2351/*
2352* We catch an error where driver does not read
2353* as much data as we expect from the entry.
2354*/
2355
2356static int netxen_md_entry_err_chk(struct netxen_adapter *adapter,
a584b7ae 2357 struct netxen_minidump_entry *entry, int esize)
83f18a55
M		 2358{
2359 if (esize < 0) {
2360 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2361 return esize;
2362 }
2363 if (esize != entry->hdr.entry_capture_size) {
2364 entry->hdr.entry_capture_size = esize;
2365 entry->hdr.driver_flags |= NX_DUMP_SIZE_ERR;
2366 dev_info(&adapter->pdev->dev,
2367 "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
2368 entry->hdr.entry_type, entry->hdr.entry_capture_mask,
2369 esize, entry->hdr.entry_capture_size);
2370 dev_info(&adapter->pdev->dev, "Aborting further dump capture\n");
2371 }
2372 return 0;
2373}
2374
2375static int netxen_parse_md_template(struct netxen_adapter *adapter)
2376{
2377 int num_of_entries, buff_level, e_cnt, esize;
2378 int end_cnt = 0, rv = 0, sane_start = 0, sane_end = 0;
2379 char *dbuff;
2380 void *template_buff = adapter->mdump.md_template;
2381 char *dump_buff = adapter->mdump.md_capture_buff;
2382 int capture_mask = adapter->mdump.md_capture_mask;
2383 struct netxen_minidump_template_hdr *template_hdr;
2384 struct netxen_minidump_entry *entry;
2385
2386 if ((capture_mask & 0x3) != 0x3) {
2387 dev_err(&adapter->pdev->dev, "Capture mask %02x below minimum needed "
2388 "for valid firmware dump\n", capture_mask);
2389 return -EINVAL;
2390 }
2391 template_hdr = (struct netxen_minidump_template_hdr *) template_buff;
2392 num_of_entries = template_hdr->num_of_entries;
2393 entry = (struct netxen_minidump_entry *) ((char *) template_buff +
2394 template_hdr->first_entry_offset);
2395 memcpy(dump_buff, template_buff, adapter->mdump.md_template_size);
2396 dump_buff = dump_buff + adapter->mdump.md_template_size;
2397
2398 if (template_hdr->entry_type == TLHDR)
2399 sane_start = 1;
2400
2401 for (e_cnt = 0, buff_level = 0; e_cnt < num_of_entries; e_cnt++) {
2402 if (!(entry->hdr.entry_capture_mask & capture_mask)) {
2403 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2404 entry = (struct netxen_minidump_entry *)
2405 ((char *) entry + entry->hdr.entry_size);
2406 continue;
2407 }
2408 switch (entry->hdr.entry_type) {
2409 case RDNOP:
2410 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2411 break;
2412 case RDEND:
2413 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2414 if (!sane_end)
2415 end_cnt = e_cnt;
2416 sane_end += 1;
2417 break;
2418 case CNTRL:
2419 rv = netxen_md_cntrl(adapter,
2420 template_hdr, (void *)entry);
2421 if (rv)
2422 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2423 break;
2424 case RDCRB:
2425 dbuff = dump_buff + buff_level;
2426 esize = netxen_md_rd_crb(adapter,
2427 (void *) entry, (void *) dbuff);
2428 rv = netxen_md_entry_err_chk
2429 (adapter, entry, esize);
2430 if (rv < 0)
2431 break;
2432 buff_level += esize;
2433 break;
2434 case RDMN:
2435 case RDMEM:
2436 dbuff = dump_buff + buff_level;
2437 esize = netxen_md_rdmem(adapter,
2438 (void *) entry, (void *) dbuff);
2439 rv = netxen_md_entry_err_chk
2440 (adapter, entry, esize);
2441 if (rv < 0)
2442 break;
2443 buff_level += esize;
2444 break;
2445 case BOARD:
2446 case RDROM:
2447 dbuff = dump_buff + buff_level;
2448 esize = netxen_md_rdrom(adapter,
2449 (void *) entry, (void *) dbuff);
2450 rv = netxen_md_entry_err_chk
2451 (adapter, entry, esize);
2452 if (rv < 0)
2453 break;
2454 buff_level += esize;
2455 break;
2456 case L2ITG:
2457 case L2DTG:
2458 case L2DAT:
2459 case L2INS:
2460 dbuff = dump_buff + buff_level;
2461 esize = netxen_md_L2Cache(adapter,
2462 (void *) entry, (void *) dbuff);
2463 rv = netxen_md_entry_err_chk
2464 (adapter, entry, esize);
2465 if (rv < 0)
2466 break;
2467 buff_level += esize;
2468 break;
2469 case L1DAT:
2470 case L1INS:
2471 dbuff = dump_buff + buff_level;
2472 esize = netxen_md_L1Cache(adapter,
2473 (void *) entry, (void *) dbuff);
2474 rv = netxen_md_entry_err_chk
2475 (adapter, entry, esize);
2476 if (rv < 0)
2477 break;
2478 buff_level += esize;
2479 break;
2480 case RDOCM:
2481 dbuff = dump_buff + buff_level;
2482 esize = netxen_md_rdocm(adapter,
2483 (void *) entry, (void *) dbuff);
2484 rv = netxen_md_entry_err_chk
2485 (adapter, entry, esize);
2486 if (rv < 0)
2487 break;
2488 buff_level += esize;
2489 break;
2490 case RDMUX:
2491 dbuff = dump_buff + buff_level;
2492 esize = netxen_md_rdmux(adapter,
2493 (void *) entry, (void *) dbuff);
2494 rv = netxen_md_entry_err_chk
2495 (adapter, entry, esize);
2496 if (rv < 0)
2497 break;
2498 buff_level += esize;
2499 break;
2500 case QUEUE:
2501 dbuff = dump_buff + buff_level;
2502 esize = netxen_md_rdqueue(adapter,
2503 (void *) entry, (void *) dbuff);
2504 rv = netxen_md_entry_err_chk
2505 (adapter, entry, esize);
2506 if (rv < 0)
2507 break;
2508 buff_level += esize;
2509 break;
2510 default:
2511 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2512 break;
2513 }
2514 /* Next entry in the template */
2515 entry = (struct netxen_minidump_entry *)
2516 ((char *) entry + entry->hdr.entry_size);
2517 }
2518 if (!sane_start || sane_end > 1) {
2519 dev_err(&adapter->pdev->dev,
2520 "Firmware minidump template configuration error.\n");
2521 }
2522 return 0;
2523}
2524
2525static int
2526netxen_collect_minidump(struct netxen_adapter *adapter)
2527{
2528 int ret = 0;
2529 struct netxen_minidump_template_hdr *hdr;
2530 struct timespec val;
2531 hdr = (struct netxen_minidump_template_hdr *)
2532 adapter->mdump.md_template;
2533 hdr->driver_capture_mask = adapter->mdump.md_capture_mask;
2534 jiffies_to_timespec(jiffies, &val);
2535 hdr->driver_timestamp = (u32) val.tv_sec;
2536 hdr->driver_info_word2 = adapter->fw_version;
2537 hdr->driver_info_word3 = NXRD32(adapter, CRB_DRIVER_VERSION);
2538 ret = netxen_parse_md_template(adapter);
2539 if (ret)
2540 return ret;
2541
2542 return ret;
2543}
2544
2545
2546void
2547netxen_dump_fw(struct netxen_adapter *adapter)
2548{
2549 struct netxen_minidump_template_hdr *hdr;
2550 int i, k, data_size = 0;
2551 u32 capture_mask;
2552 hdr = (struct netxen_minidump_template_hdr *)
2553 adapter->mdump.md_template;
2554 capture_mask = adapter->mdump.md_capture_mask;
2555
2556 for (i = 0x2, k = 1; (i & NX_DUMP_MASK_MAX); i <<= 1, k++) {
2557 if (i & capture_mask)
2558 data_size += hdr->capture_size_array[k];
2559 }
2560 if (!data_size) {
2561 dev_err(&adapter->pdev->dev,
2562 "Invalid cap sizes for capture_mask=0x%x\n",
2563 adapter->mdump.md_capture_mask);
2564 return;
2565 }
2566 adapter->mdump.md_capture_size = data_size;
2567 adapter->mdump.md_dump_size = adapter->mdump.md_template_size +
2568 adapter->mdump.md_capture_size;
2569 if (!adapter->mdump.md_capture_buff) {
2570 adapter->mdump.md_capture_buff =
b2adaca9
JP		 2571 vzalloc(adapter->mdump.md_dump_size);
2572 if (!adapter->mdump.md_capture_buff)
83f18a55 2573 return;
b2adaca9 2574
83f18a55
M		 2575 if (netxen_collect_minidump(adapter)) {
2576 adapter->mdump.has_valid_dump = 0;
2577 adapter->mdump.md_dump_size = 0;
2578 vfree(adapter->mdump.md_capture_buff);
2579 adapter->mdump.md_capture_buff = NULL;
2580 dev_err(&adapter->pdev->dev,
2581 "Error in collecting firmware minidump.\n");
2582 } else {
2583 adapter->mdump.md_timestamp = jiffies;
2584 adapter->mdump.has_valid_dump = 1;
2585 adapter->fw_mdump_rdy = 1;
2586 dev_info(&adapter->pdev->dev, "%s Successfully "
2587 "collected fw dump.\n", adapter->netdev->name);
2588 }
2589
2590 } else {
2591 dev_info(&adapter->pdev->dev,
2592 "Cannot overwrite previously collected "
2593 "firmware minidump.\n");
2594 adapter->fw_mdump_rdy = 1;
2595 return;
2596 }
2597}
Linux 6.x block layer and io_uring tree(s)