Commit | Line | Data |
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f5cd7872 OJ |
1 | /* |
2 | * Copyright (C) 2006-2007 PA Semi, Inc | |
3 | * | |
4 | * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
f5cd7872 OJ |
24 | #include <linux/interrupt.h> |
25 | #include <linux/dmaengine.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/netdevice.h> | |
1dd2d06c | 28 | #include <linux/of_mdio.h> |
f5cd7872 OJ |
29 | #include <linux/etherdevice.h> |
30 | #include <asm/dma-mapping.h> | |
31 | #include <linux/in.h> | |
32 | #include <linux/skbuff.h> | |
33 | ||
34 | #include <linux/ip.h> | |
35 | #include <linux/tcp.h> | |
36 | #include <net/checksum.h> | |
28ae79f5 | 37 | #include <linux/inet_lro.h> |
70c71606 | 38 | #include <linux/prefetch.h> |
f5cd7872 | 39 | |
771f7404 | 40 | #include <asm/irq.h> |
af289e80 | 41 | #include <asm/firmware.h> |
40afa531 | 42 | #include <asm/pasemi_dma.h> |
771f7404 | 43 | |
f5cd7872 OJ |
44 | #include "pasemi_mac.h" |
45 | ||
8dc121a4 OJ |
46 | /* We have our own align, since ppc64 in general has it at 0 because |
47 | * of design flaws in some of the server bridge chips. However, for | |
48 | * PWRficient doing the unaligned copies is more expensive than doing | |
49 | * unaligned DMA, so make sure the data is aligned instead. | |
50 | */ | |
51 | #define LOCAL_SKB_ALIGN 2 | |
f5cd7872 OJ |
52 | |
53 | /* TODO list | |
54 | * | |
f5cd7872 OJ |
55 | * - Multicast support |
56 | * - Large MTU support | |
7ddeae2c OJ |
57 | * - SW LRO |
58 | * - Multiqueue RX/TX | |
f5cd7872 OJ |
59 | */ |
60 | ||
28ae79f5 OJ |
61 | #define LRO_MAX_AGGR 64 |
62 | ||
ef1ea0b4 | 63 | #define PE_MIN_MTU 64 |
8d636d8b | 64 | #define PE_MAX_MTU 9000 |
ef1ea0b4 OJ |
65 | #define PE_DEF_MTU ETH_DATA_LEN |
66 | ||
ceb51361 OJ |
67 | #define DEFAULT_MSG_ENABLE \ |
68 | (NETIF_MSG_DRV | \ | |
69 | NETIF_MSG_PROBE | \ | |
70 | NETIF_MSG_LINK | \ | |
71 | NETIF_MSG_TIMER | \ | |
72 | NETIF_MSG_IFDOWN | \ | |
73 | NETIF_MSG_IFUP | \ | |
74 | NETIF_MSG_RX_ERR | \ | |
75 | NETIF_MSG_TX_ERR) | |
76 | ||
ceb51361 OJ |
77 | MODULE_LICENSE("GPL"); |
78 | MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>"); | |
79 | MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver"); | |
80 | ||
81 | static int debug = -1; /* -1 == use DEFAULT_MSG_ENABLE as value */ | |
82 | module_param(debug, int, 0); | |
83 | MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |
f5cd7872 | 84 | |
e37c772e OJ |
85 | extern const struct ethtool_ops pasemi_mac_ethtool_ops; |
86 | ||
af289e80 OJ |
87 | static int translation_enabled(void) |
88 | { | |
89 | #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE) | |
90 | return 1; | |
91 | #else | |
92 | return firmware_has_feature(FW_FEATURE_LPAR); | |
93 | #endif | |
94 | } | |
95 | ||
34c20624 | 96 | static void write_iob_reg(unsigned int reg, unsigned int val) |
a85b9422 | 97 | { |
34c20624 | 98 | pasemi_write_iob_reg(reg, val); |
a85b9422 OJ |
99 | } |
100 | ||
5c15332b | 101 | static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg) |
a85b9422 | 102 | { |
34c20624 | 103 | return pasemi_read_mac_reg(mac->dma_if, reg); |
a85b9422 OJ |
104 | } |
105 | ||
5c15332b | 106 | static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg, |
a85b9422 OJ |
107 | unsigned int val) |
108 | { | |
34c20624 | 109 | pasemi_write_mac_reg(mac->dma_if, reg, val); |
a85b9422 OJ |
110 | } |
111 | ||
34c20624 | 112 | static unsigned int read_dma_reg(unsigned int reg) |
a85b9422 | 113 | { |
34c20624 | 114 | return pasemi_read_dma_reg(reg); |
a85b9422 OJ |
115 | } |
116 | ||
34c20624 | 117 | static void write_dma_reg(unsigned int reg, unsigned int val) |
a85b9422 | 118 | { |
34c20624 | 119 | pasemi_write_dma_reg(reg, val); |
a85b9422 OJ |
120 | } |
121 | ||
5c15332b | 122 | static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
123 | { |
124 | return mac->rx; | |
125 | } | |
126 | ||
5c15332b | 127 | static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac) |
72b05b99 OJ |
128 | { |
129 | return mac->tx; | |
130 | } | |
131 | ||
5c15332b OJ |
132 | static inline void prefetch_skb(const struct sk_buff *skb) |
133 | { | |
134 | const void *d = skb; | |
135 | ||
136 | prefetch(d); | |
137 | prefetch(d+64); | |
138 | prefetch(d+128); | |
139 | prefetch(d+192); | |
140 | } | |
141 | ||
34c20624 OJ |
142 | static int mac_to_intf(struct pasemi_mac *mac) |
143 | { | |
144 | struct pci_dev *pdev = mac->pdev; | |
145 | u32 tmp; | |
146 | int nintf, off, i, j; | |
147 | int devfn = pdev->devfn; | |
148 | ||
149 | tmp = read_dma_reg(PAS_DMA_CAP_IFI); | |
150 | nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S; | |
151 | off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S; | |
152 | ||
153 | /* IOFF contains the offset to the registers containing the | |
154 | * DMA interface-to-MAC-pci-id mappings, and NIN contains number | |
155 | * of total interfaces. Each register contains 4 devfns. | |
156 | * Just do a linear search until we find the devfn of the MAC | |
157 | * we're trying to look up. | |
158 | */ | |
159 | ||
160 | for (i = 0; i < (nintf+3)/4; i++) { | |
161 | tmp = read_dma_reg(off+4*i); | |
162 | for (j = 0; j < 4; j++) { | |
163 | if (((tmp >> (8*j)) & 0xff) == devfn) | |
164 | return i*4 + j; | |
165 | } | |
166 | } | |
167 | return -1; | |
168 | } | |
169 | ||
ef1ea0b4 OJ |
170 | static void pasemi_mac_intf_disable(struct pasemi_mac *mac) |
171 | { | |
172 | unsigned int flags; | |
173 | ||
174 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
175 | flags &= ~PAS_MAC_CFG_PCFG_PE; | |
176 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
177 | } | |
178 | ||
179 | static void pasemi_mac_intf_enable(struct pasemi_mac *mac) | |
180 | { | |
181 | unsigned int flags; | |
182 | ||
183 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); | |
184 | flags |= PAS_MAC_CFG_PCFG_PE; | |
185 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
186 | } | |
187 | ||
f5cd7872 OJ |
188 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) |
189 | { | |
190 | struct pci_dev *pdev = mac->pdev; | |
191 | struct device_node *dn = pci_device_to_OF_node(pdev); | |
1af7f056 | 192 | int len; |
f5cd7872 OJ |
193 | const u8 *maddr; |
194 | u8 addr[6]; | |
195 | ||
196 | if (!dn) { | |
197 | dev_dbg(&pdev->dev, | |
198 | "No device node for mac, not configuring\n"); | |
199 | return -ENOENT; | |
200 | } | |
201 | ||
1af7f056 | 202 | maddr = of_get_property(dn, "local-mac-address", &len); |
203 | ||
204 | if (maddr && len == 6) { | |
205 | memcpy(mac->mac_addr, maddr, 6); | |
206 | return 0; | |
207 | } | |
208 | ||
209 | /* Some old versions of firmware mistakenly uses mac-address | |
210 | * (and as a string) instead of a byte array in local-mac-address. | |
211 | */ | |
a5fd22eb | 212 | |
a5fd22eb | 213 | if (maddr == NULL) |
9028780a | 214 | maddr = of_get_property(dn, "mac-address", NULL); |
a5fd22eb | 215 | |
f5cd7872 OJ |
216 | if (maddr == NULL) { |
217 | dev_warn(&pdev->dev, | |
218 | "no mac address in device tree, not configuring\n"); | |
219 | return -ENOENT; | |
220 | } | |
221 | ||
222 | if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &addr[0], | |
223 | &addr[1], &addr[2], &addr[3], &addr[4], &addr[5]) != 6) { | |
224 | dev_warn(&pdev->dev, | |
225 | "can't parse mac address, not configuring\n"); | |
226 | return -EINVAL; | |
227 | } | |
228 | ||
1af7f056 | 229 | memcpy(mac->mac_addr, addr, 6); |
230 | ||
f5cd7872 OJ |
231 | return 0; |
232 | } | |
233 | ||
5cea73b0 OJ |
234 | static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p) |
235 | { | |
236 | struct pasemi_mac *mac = netdev_priv(dev); | |
237 | struct sockaddr *addr = p; | |
238 | unsigned int adr0, adr1; | |
239 | ||
240 | if (!is_valid_ether_addr(addr->sa_data)) | |
504f9b5a | 241 | return -EADDRNOTAVAIL; |
5cea73b0 OJ |
242 | |
243 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
244 | ||
245 | adr0 = dev->dev_addr[2] << 24 | | |
246 | dev->dev_addr[3] << 16 | | |
247 | dev->dev_addr[4] << 8 | | |
248 | dev->dev_addr[5]; | |
249 | adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1); | |
250 | adr1 &= ~0xffff; | |
251 | adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1]; | |
252 | ||
253 | pasemi_mac_intf_disable(mac); | |
254 | write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0); | |
255 | write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1); | |
256 | pasemi_mac_intf_enable(mac); | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
28ae79f5 OJ |
261 | static int get_skb_hdr(struct sk_buff *skb, void **iphdr, |
262 | void **tcph, u64 *hdr_flags, void *data) | |
263 | { | |
264 | u64 macrx = (u64) data; | |
265 | unsigned int ip_len; | |
266 | struct iphdr *iph; | |
267 | ||
268 | /* IPv4 header checksum failed */ | |
269 | if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK) | |
270 | return -1; | |
271 | ||
272 | /* non tcp packet */ | |
273 | skb_reset_network_header(skb); | |
274 | iph = ip_hdr(skb); | |
275 | if (iph->protocol != IPPROTO_TCP) | |
276 | return -1; | |
277 | ||
278 | ip_len = ip_hdrlen(skb); | |
279 | skb_set_transport_header(skb, ip_len); | |
280 | *tcph = tcp_hdr(skb); | |
281 | ||
282 | /* check if ip header and tcp header are complete */ | |
77321233 | 283 | if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb)) |
28ae79f5 OJ |
284 | return -1; |
285 | ||
286 | *hdr_flags = LRO_IPV4 | LRO_TCP; | |
287 | *iphdr = iph; | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
ad3c20d1 | 292 | static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac, |
7e9916e9 | 293 | const int nfrags, |
ad3c20d1 | 294 | struct sk_buff *skb, |
5c15332b | 295 | const dma_addr_t *dmas) |
ad3c20d1 OJ |
296 | { |
297 | int f; | |
5c15332b | 298 | struct pci_dev *pdev = mac->dma_pdev; |
ad3c20d1 | 299 | |
5c15332b | 300 | pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
301 | |
302 | for (f = 0; f < nfrags; f++) { | |
9e903e08 | 303 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[f]; |
ad3c20d1 | 304 | |
9e903e08 | 305 | pci_unmap_page(pdev, dmas[f+1], skb_frag_size(frag), PCI_DMA_TODEVICE); |
ad3c20d1 OJ |
306 | } |
307 | dev_kfree_skb_irq(skb); | |
308 | ||
309 | /* Freed descriptor slot + main SKB ptr + nfrags additional ptrs, | |
310 | * aligned up to a power of 2 | |
311 | */ | |
312 | return (nfrags + 3) & ~1; | |
313 | } | |
314 | ||
8d636d8b OJ |
315 | static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac) |
316 | { | |
317 | struct pasemi_mac_csring *ring; | |
318 | u32 val; | |
319 | unsigned int cfg; | |
320 | int chno; | |
321 | ||
322 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring), | |
323 | offsetof(struct pasemi_mac_csring, chan)); | |
324 | ||
325 | if (!ring) { | |
326 | dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n"); | |
327 | goto out_chan; | |
328 | } | |
329 | ||
330 | chno = ring->chan.chno; | |
331 | ||
332 | ring->size = CS_RING_SIZE; | |
333 | ring->next_to_fill = 0; | |
334 | ||
335 | /* Allocate descriptors */ | |
336 | if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE)) | |
337 | goto out_ring_desc; | |
338 | ||
339 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), | |
340 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
341 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
342 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3); | |
343 | ||
344 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); | |
345 | ||
346 | ring->events[0] = pasemi_dma_alloc_flag(); | |
347 | ring->events[1] = pasemi_dma_alloc_flag(); | |
348 | if (ring->events[0] < 0 || ring->events[1] < 0) | |
349 | goto out_flags; | |
350 | ||
351 | pasemi_dma_clear_flag(ring->events[0]); | |
352 | pasemi_dma_clear_flag(ring->events[1]); | |
353 | ||
354 | ring->fun = pasemi_dma_alloc_fun(); | |
355 | if (ring->fun < 0) | |
356 | goto out_fun; | |
357 | ||
358 | cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP | | |
359 | PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) | | |
360 | PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ; | |
361 | ||
362 | if (translation_enabled()) | |
363 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
364 | ||
365 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); | |
366 | ||
367 | /* enable channel */ | |
368 | pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | | |
369 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
370 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
371 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
372 | ||
373 | return ring; | |
374 | ||
375 | out_fun: | |
376 | out_flags: | |
377 | if (ring->events[0] >= 0) | |
378 | pasemi_dma_free_flag(ring->events[0]); | |
379 | if (ring->events[1] >= 0) | |
380 | pasemi_dma_free_flag(ring->events[1]); | |
381 | pasemi_dma_free_ring(&ring->chan); | |
382 | out_ring_desc: | |
383 | pasemi_dma_free_chan(&ring->chan); | |
384 | out_chan: | |
385 | ||
386 | return NULL; | |
387 | } | |
388 | ||
389 | static void pasemi_mac_setup_csrings(struct pasemi_mac *mac) | |
390 | { | |
391 | int i; | |
392 | mac->cs[0] = pasemi_mac_setup_csring(mac); | |
393 | if (mac->type == MAC_TYPE_XAUI) | |
394 | mac->cs[1] = pasemi_mac_setup_csring(mac); | |
395 | else | |
396 | mac->cs[1] = 0; | |
397 | ||
398 | for (i = 0; i < MAX_CS; i++) | |
399 | if (mac->cs[i]) | |
400 | mac->num_cs++; | |
401 | } | |
402 | ||
403 | static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring) | |
404 | { | |
405 | pasemi_dma_stop_chan(&csring->chan); | |
406 | pasemi_dma_free_flag(csring->events[0]); | |
407 | pasemi_dma_free_flag(csring->events[1]); | |
408 | pasemi_dma_free_ring(&csring->chan); | |
409 | pasemi_dma_free_chan(&csring->chan); | |
1724ac2e | 410 | pasemi_dma_free_fun(csring->fun); |
8d636d8b OJ |
411 | } |
412 | ||
5c15332b | 413 | static int pasemi_mac_setup_rx_resources(const struct net_device *dev) |
f5cd7872 OJ |
414 | { |
415 | struct pasemi_mac_rxring *ring; | |
416 | struct pasemi_mac *mac = netdev_priv(dev); | |
34c20624 | 417 | int chno; |
af289e80 | 418 | unsigned int cfg; |
f5cd7872 | 419 | |
34c20624 OJ |
420 | ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring), |
421 | offsetof(struct pasemi_mac_rxring, chan)); | |
f5cd7872 | 422 | |
34c20624 OJ |
423 | if (!ring) { |
424 | dev_err(&mac->pdev->dev, "Can't allocate RX channel\n"); | |
425 | goto out_chan; | |
426 | } | |
427 | chno = ring->chan.chno; | |
f5cd7872 OJ |
428 | |
429 | spin_lock_init(&ring->lock); | |
430 | ||
021fa22e | 431 | ring->size = RX_RING_SIZE; |
fc9e4d2a | 432 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 OJ |
433 | RX_RING_SIZE, GFP_KERNEL); |
434 | ||
fc9e4d2a OJ |
435 | if (!ring->ring_info) |
436 | goto out_ring_info; | |
f5cd7872 OJ |
437 | |
438 | /* Allocate descriptors */ | |
34c20624 | 439 | if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE)) |
fc9e4d2a | 440 | goto out_ring_desc; |
f5cd7872 | 441 | |
f5cd7872 OJ |
442 | ring->buffers = dma_alloc_coherent(&mac->dma_pdev->dev, |
443 | RX_RING_SIZE * sizeof(u64), | |
1f9061d2 JP |
444 | &ring->buf_dma, |
445 | GFP_KERNEL | __GFP_ZERO); | |
f5cd7872 | 446 | if (!ring->buffers) |
34c20624 | 447 | goto out_ring_desc; |
f5cd7872 | 448 | |
34c20624 OJ |
449 | write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno), |
450 | PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
f5cd7872 | 451 | |
34c20624 OJ |
452 | write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno), |
453 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) | | |
454 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 455 | |
5c15332b | 456 | cfg = PAS_DMA_RXCHAN_CFG_HBU(2); |
af289e80 OJ |
457 | |
458 | if (translation_enabled()) | |
459 | cfg |= PAS_DMA_RXCHAN_CFG_CTR; | |
460 | ||
34c20624 | 461 | write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg); |
f5cd7872 | 462 | |
34c20624 OJ |
463 | write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if), |
464 | PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma)); | |
f5cd7872 | 465 | |
34c20624 OJ |
466 | write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if), |
467 | PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) | | |
468 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); | |
f5cd7872 | 469 | |
5c15332b | 470 | cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 | |
af289e80 OJ |
471 | PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP | |
472 | PAS_DMA_RXINT_CFG_HEN; | |
473 | ||
474 | if (translation_enabled()) | |
475 | cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR; | |
476 | ||
34c20624 | 477 | write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg); |
c0efd52b | 478 | |
f5cd7872 OJ |
479 | ring->next_to_fill = 0; |
480 | ring->next_to_clean = 0; | |
72b05b99 | 481 | ring->mac = mac; |
f5cd7872 OJ |
482 | mac->rx = ring; |
483 | ||
484 | return 0; | |
485 | ||
fc9e4d2a OJ |
486 | out_ring_desc: |
487 | kfree(ring->ring_info); | |
488 | out_ring_info: | |
34c20624 OJ |
489 | pasemi_dma_free_chan(&ring->chan); |
490 | out_chan: | |
f5cd7872 OJ |
491 | return -ENOMEM; |
492 | } | |
493 | ||
72b05b99 | 494 | static struct pasemi_mac_txring * |
5c15332b | 495 | pasemi_mac_setup_tx_resources(const struct net_device *dev) |
f5cd7872 OJ |
496 | { |
497 | struct pasemi_mac *mac = netdev_priv(dev); | |
498 | u32 val; | |
f5cd7872 | 499 | struct pasemi_mac_txring *ring; |
af289e80 | 500 | unsigned int cfg; |
34c20624 | 501 | int chno; |
f5cd7872 | 502 | |
34c20624 OJ |
503 | ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring), |
504 | offsetof(struct pasemi_mac_txring, chan)); | |
505 | ||
506 | if (!ring) { | |
507 | dev_err(&mac->pdev->dev, "Can't allocate TX channel\n"); | |
508 | goto out_chan; | |
509 | } | |
510 | ||
511 | chno = ring->chan.chno; | |
f5cd7872 OJ |
512 | |
513 | spin_lock_init(&ring->lock); | |
514 | ||
021fa22e | 515 | ring->size = TX_RING_SIZE; |
fc9e4d2a | 516 | ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) * |
f5cd7872 | 517 | TX_RING_SIZE, GFP_KERNEL); |
fc9e4d2a OJ |
518 | if (!ring->ring_info) |
519 | goto out_ring_info; | |
f5cd7872 OJ |
520 | |
521 | /* Allocate descriptors */ | |
34c20624 | 522 | if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE)) |
fc9e4d2a | 523 | goto out_ring_desc; |
f5cd7872 | 524 | |
34c20624 OJ |
525 | write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno), |
526 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma)); | |
527 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32); | |
fc9e4d2a | 528 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3); |
f5cd7872 | 529 | |
34c20624 | 530 | write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val); |
f5cd7872 | 531 | |
af289e80 OJ |
532 | cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE | |
533 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | |
534 | PAS_DMA_TXCHAN_CFG_UP | | |
8d636d8b | 535 | PAS_DMA_TXCHAN_CFG_WT(4); |
af289e80 OJ |
536 | |
537 | if (translation_enabled()) | |
538 | cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR; | |
539 | ||
34c20624 | 540 | write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg); |
f5cd7872 | 541 | |
021fa22e | 542 | ring->next_to_fill = 0; |
f5cd7872 | 543 | ring->next_to_clean = 0; |
72b05b99 | 544 | ring->mac = mac; |
f5cd7872 | 545 | |
72b05b99 | 546 | return ring; |
f5cd7872 | 547 | |
fc9e4d2a OJ |
548 | out_ring_desc: |
549 | kfree(ring->ring_info); | |
550 | out_ring_info: | |
34c20624 OJ |
551 | pasemi_dma_free_chan(&ring->chan); |
552 | out_chan: | |
72b05b99 | 553 | return NULL; |
f5cd7872 OJ |
554 | } |
555 | ||
72b05b99 | 556 | static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac) |
f5cd7872 | 557 | { |
72b05b99 | 558 | struct pasemi_mac_txring *txring = tx_ring(mac); |
ad3c20d1 | 559 | unsigned int i, j; |
f5cd7872 | 560 | struct pasemi_mac_buffer *info; |
ad3c20d1 | 561 | dma_addr_t dmas[MAX_SKB_FRAGS+1]; |
7e9916e9 | 562 | int freed, nfrags; |
ad5da10a | 563 | int start, limit; |
fc9e4d2a | 564 | |
72b05b99 OJ |
565 | start = txring->next_to_clean; |
566 | limit = txring->next_to_fill; | |
ad5da10a OJ |
567 | |
568 | /* Compensate for when fill has wrapped and clean has not */ | |
569 | if (start > limit) | |
570 | limit += TX_RING_SIZE; | |
571 | ||
572 | for (i = start; i < limit; i += freed) { | |
72b05b99 | 573 | info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)]; |
fc9e4d2a | 574 | if (info->dma && info->skb) { |
7e9916e9 OJ |
575 | nfrags = skb_shinfo(info->skb)->nr_frags; |
576 | for (j = 0; j <= nfrags; j++) | |
72b05b99 OJ |
577 | dmas[j] = txring->ring_info[(i+1+j) & |
578 | (TX_RING_SIZE-1)].dma; | |
7e9916e9 OJ |
579 | freed = pasemi_mac_unmap_tx_skb(mac, nfrags, |
580 | info->skb, dmas); | |
ea5cdccc | 581 | } else { |
ad3c20d1 | 582 | freed = 2; |
ea5cdccc | 583 | } |
f5cd7872 OJ |
584 | } |
585 | ||
72b05b99 | 586 | kfree(txring->ring_info); |
34c20624 OJ |
587 | pasemi_dma_free_chan(&txring->chan); |
588 | ||
f5cd7872 OJ |
589 | } |
590 | ||
ef1ea0b4 | 591 | static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac) |
f5cd7872 | 592 | { |
72b05b99 | 593 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
f5cd7872 OJ |
594 | unsigned int i; |
595 | struct pasemi_mac_buffer *info; | |
f5cd7872 OJ |
596 | |
597 | for (i = 0; i < RX_RING_SIZE; i++) { | |
72b05b99 | 598 | info = &RX_DESC_INFO(rx, i); |
fc9e4d2a OJ |
599 | if (info->skb && info->dma) { |
600 | pci_unmap_single(mac->dma_pdev, | |
601 | info->dma, | |
602 | info->skb->len, | |
603 | PCI_DMA_FROMDEVICE); | |
604 | dev_kfree_skb_any(info->skb); | |
f5cd7872 | 605 | } |
fc9e4d2a OJ |
606 | info->dma = 0; |
607 | info->skb = NULL; | |
f5cd7872 OJ |
608 | } |
609 | ||
fc9e4d2a | 610 | for (i = 0; i < RX_RING_SIZE; i++) |
ef1ea0b4 OJ |
611 | RX_BUFF(rx, i) = 0; |
612 | } | |
613 | ||
614 | static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac) | |
615 | { | |
616 | pasemi_mac_free_rx_buffers(mac); | |
fc9e4d2a | 617 | |
f5cd7872 | 618 | dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64), |
72b05b99 | 619 | rx_ring(mac)->buffers, rx_ring(mac)->buf_dma); |
f5cd7872 | 620 | |
72b05b99 | 621 | kfree(rx_ring(mac)->ring_info); |
34c20624 | 622 | pasemi_dma_free_chan(&rx_ring(mac)->chan); |
f5cd7872 OJ |
623 | mac->rx = NULL; |
624 | } | |
625 | ||
5c6239c8 | 626 | static void pasemi_mac_replenish_rx_ring(struct net_device *dev, |
5c15332b | 627 | const int limit) |
f5cd7872 | 628 | { |
5c15332b | 629 | const struct pasemi_mac *mac = netdev_priv(dev); |
72b05b99 | 630 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
b5254eee | 631 | int fill, count; |
f5cd7872 | 632 | |
cd4ceb24 | 633 | if (limit <= 0) |
f5cd7872 OJ |
634 | return; |
635 | ||
72b05b99 | 636 | fill = rx_ring(mac)->next_to_fill; |
928773c2 | 637 | for (count = 0; count < limit; count++) { |
72b05b99 OJ |
638 | struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill); |
639 | u64 *buff = &RX_BUFF(rx, fill); | |
f5cd7872 OJ |
640 | struct sk_buff *skb; |
641 | dma_addr_t dma; | |
642 | ||
fc9e4d2a OJ |
643 | /* Entry in use? */ |
644 | WARN_ON(*buff); | |
645 | ||
dae2e9f4 | 646 | skb = netdev_alloc_skb(dev, mac->bufsz); |
5d894944 | 647 | skb_reserve(skb, LOCAL_SKB_ALIGN); |
f5cd7872 | 648 | |
9f05cfe2 | 649 | if (unlikely(!skb)) |
f5cd7872 | 650 | break; |
f5cd7872 | 651 | |
8dc121a4 | 652 | dma = pci_map_single(mac->dma_pdev, skb->data, |
ef1ea0b4 | 653 | mac->bufsz - LOCAL_SKB_ALIGN, |
f5cd7872 OJ |
654 | PCI_DMA_FROMDEVICE); |
655 | ||
8d8bb39b | 656 | if (unlikely(pci_dma_mapping_error(mac->dma_pdev, dma))) { |
f5cd7872 | 657 | dev_kfree_skb_irq(info->skb); |
f5cd7872 OJ |
658 | break; |
659 | } | |
660 | ||
661 | info->skb = skb; | |
662 | info->dma = dma; | |
ef1ea0b4 | 663 | *buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma); |
fc9e4d2a | 664 | fill++; |
f5cd7872 OJ |
665 | } |
666 | ||
667 | wmb(); | |
668 | ||
34c20624 | 669 | write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count); |
f5cd7872 | 670 | |
72b05b99 | 671 | rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) & |
b5254eee | 672 | (RX_RING_SIZE - 1); |
f5cd7872 OJ |
673 | } |
674 | ||
5c15332b | 675 | static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac) |
1b0335ea | 676 | { |
906674ab | 677 | struct pasemi_mac_rxring *rx = rx_ring(mac); |
52a94351 | 678 | unsigned int reg, pcnt; |
1b0335ea OJ |
679 | /* Re-enable packet count interrupts: finally |
680 | * ack the packet count interrupt we got in rx_intr. | |
681 | */ | |
682 | ||
906674ab | 683 | pcnt = *rx->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 684 | |
52a94351 | 685 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
1b0335ea | 686 | |
906674ab OJ |
687 | if (*rx->chan.status & PAS_STATUS_TIMER) |
688 | reg |= PAS_IOB_DMA_RXCH_RESET_TINTC; | |
689 | ||
34c20624 | 690 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg); |
1b0335ea OJ |
691 | } |
692 | ||
5c15332b | 693 | static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac) |
1b0335ea | 694 | { |
52a94351 | 695 | unsigned int reg, pcnt; |
1b0335ea OJ |
696 | |
697 | /* Re-enable packet count interrupts */ | |
34c20624 | 698 | pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M; |
1b0335ea | 699 | |
52a94351 | 700 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
1b0335ea | 701 | |
34c20624 | 702 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg); |
1b0335ea OJ |
703 | } |
704 | ||
705 | ||
5c15332b OJ |
706 | static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac, |
707 | const u64 macrx) | |
69c29d89 OJ |
708 | { |
709 | unsigned int rcmdsta, ccmdsta; | |
34c20624 | 710 | struct pasemi_dmachan *chan = &rx_ring(mac)->chan; |
69c29d89 OJ |
711 | |
712 | if (!netif_msg_rx_err(mac)) | |
713 | return; | |
714 | ||
34c20624 OJ |
715 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
716 | ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno)); | |
69c29d89 | 717 | |
fe333321 | 718 | printk(KERN_ERR "pasemi_mac: rx error. macrx %016llx, rx status %llx\n", |
34c20624 | 719 | macrx, *chan->status); |
69c29d89 OJ |
720 | |
721 | printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n", | |
722 | rcmdsta, ccmdsta); | |
723 | } | |
724 | ||
5c15332b OJ |
725 | static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac, |
726 | const u64 mactx) | |
69c29d89 OJ |
727 | { |
728 | unsigned int cmdsta; | |
34c20624 | 729 | struct pasemi_dmachan *chan = &tx_ring(mac)->chan; |
69c29d89 OJ |
730 | |
731 | if (!netif_msg_tx_err(mac)) | |
732 | return; | |
733 | ||
34c20624 | 734 | cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno)); |
69c29d89 | 735 | |
fe333321 IM |
736 | printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016llx, "\ |
737 | "tx status 0x%016llx\n", mactx, *chan->status); | |
69c29d89 OJ |
738 | |
739 | printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta); | |
740 | } | |
741 | ||
5c15332b OJ |
742 | static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx, |
743 | const int limit) | |
f5cd7872 | 744 | { |
5c15332b | 745 | const struct pasemi_dmachan *chan = &rx->chan; |
72b05b99 | 746 | struct pasemi_mac *mac = rx->mac; |
5c15332b | 747 | struct pci_dev *pdev = mac->dma_pdev; |
cd4ceb24 | 748 | unsigned int n; |
5c15332b | 749 | int count, buf_index, tot_bytes, packets; |
cd4ceb24 OJ |
750 | struct pasemi_mac_buffer *info; |
751 | struct sk_buff *skb; | |
b5254eee | 752 | unsigned int len; |
5c15332b | 753 | u64 macrx, eval; |
cd4ceb24 | 754 | dma_addr_t dma; |
5c15332b OJ |
755 | |
756 | tot_bytes = 0; | |
757 | packets = 0; | |
f5cd7872 | 758 | |
72b05b99 | 759 | spin_lock(&rx->lock); |
f5cd7872 | 760 | |
72b05b99 | 761 | n = rx->next_to_clean; |
f5cd7872 | 762 | |
72b05b99 | 763 | prefetch(&RX_DESC(rx, n)); |
b5254eee OJ |
764 | |
765 | for (count = 0; count < limit; count++) { | |
72b05b99 | 766 | macrx = RX_DESC(rx, n); |
5c15332b | 767 | prefetch(&RX_DESC(rx, n+4)); |
f5cd7872 | 768 | |
69c29d89 | 769 | if ((macrx & XCT_MACRX_E) || |
34c20624 | 770 | (*chan->status & PAS_STATUS_ERROR)) |
69c29d89 OJ |
771 | pasemi_mac_rx_error(mac, macrx); |
772 | ||
cd4ceb24 | 773 | if (!(macrx & XCT_MACRX_O)) |
f5cd7872 OJ |
774 | break; |
775 | ||
f5cd7872 OJ |
776 | info = NULL; |
777 | ||
b5254eee | 778 | BUG_ON(!(macrx & XCT_MACRX_RR_8BRES)); |
f5cd7872 | 779 | |
72b05b99 | 780 | eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >> |
b5254eee OJ |
781 | XCT_RXRES_8B_EVAL_S; |
782 | buf_index = eval-1; | |
783 | ||
72b05b99 OJ |
784 | dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M); |
785 | info = &RX_DESC_INFO(rx, buf_index); | |
fc9e4d2a | 786 | |
9f05cfe2 | 787 | skb = info->skb; |
f5cd7872 | 788 | |
5c15332b | 789 | prefetch_skb(skb); |
f5cd7872 | 790 | |
cd4ceb24 | 791 | len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S; |
f5cd7872 | 792 | |
ef1ea0b4 | 793 | pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN, |
5c15332b | 794 | PCI_DMA_FROMDEVICE); |
32bee776 OJ |
795 | |
796 | if (macrx & XCT_MACRX_CRC) { | |
797 | /* CRC error flagged */ | |
798 | mac->netdev->stats.rx_errors++; | |
799 | mac->netdev->stats.rx_crc_errors++; | |
4352d826 | 800 | /* No need to free skb, it'll be reused */ |
32bee776 OJ |
801 | goto next; |
802 | } | |
803 | ||
5d894944 | 804 | info->skb = NULL; |
ad5da10a | 805 | info->dma = 0; |
fc9e4d2a | 806 | |
26fcfa95 | 807 | if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) { |
38bf3184 | 808 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
cd4ceb24 | 809 | skb->csum = (macrx & XCT_MACRX_CSUM_M) >> |
f5cd7872 | 810 | XCT_MACRX_CSUM_S; |
ea5cdccc | 811 | } else { |
bc8acf2c | 812 | skb_checksum_none_assert(skb); |
ea5cdccc | 813 | } |
f5cd7872 | 814 | |
5c15332b OJ |
815 | packets++; |
816 | tot_bytes += len; | |
817 | ||
818 | /* Don't include CRC */ | |
819 | skb_put(skb, len-4); | |
f5cd7872 | 820 | |
26fcfa95 | 821 | skb->protocol = eth_type_trans(skb, mac->netdev); |
28ae79f5 | 822 | lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx); |
f5cd7872 | 823 | |
32bee776 | 824 | next: |
72b05b99 OJ |
825 | RX_DESC(rx, n) = 0; |
826 | RX_DESC(rx, n+1) = 0; | |
cd4ceb24 | 827 | |
ad5da10a OJ |
828 | /* Need to zero it out since hardware doesn't, since the |
829 | * replenish loop uses it to tell when it's done. | |
830 | */ | |
72b05b99 | 831 | RX_BUFF(rx, buf_index) = 0; |
ad5da10a | 832 | |
b5254eee | 833 | n += 4; |
f5cd7872 OJ |
834 | } |
835 | ||
9a50bebd OJ |
836 | if (n > RX_RING_SIZE) { |
837 | /* Errata 5971 workaround: L2 target of headers */ | |
34c20624 | 838 | write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0); |
9a50bebd OJ |
839 | n &= (RX_RING_SIZE-1); |
840 | } | |
b5254eee | 841 | |
72b05b99 | 842 | rx_ring(mac)->next_to_clean = n; |
b5254eee | 843 | |
28ae79f5 OJ |
844 | lro_flush_all(&mac->lro_mgr); |
845 | ||
b5254eee OJ |
846 | /* Increase is in number of 16-byte entries, and since each descriptor |
847 | * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with | |
848 | * count*2. | |
849 | */ | |
34c20624 | 850 | write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1); |
b5254eee OJ |
851 | |
852 | pasemi_mac_replenish_rx_ring(mac->netdev, count); | |
f5cd7872 | 853 | |
5c15332b OJ |
854 | mac->netdev->stats.rx_bytes += tot_bytes; |
855 | mac->netdev->stats.rx_packets += packets; | |
856 | ||
72b05b99 | 857 | spin_unlock(&rx_ring(mac)->lock); |
f5cd7872 OJ |
858 | |
859 | return count; | |
860 | } | |
861 | ||
ad3c20d1 OJ |
862 | /* Can't make this too large or we blow the kernel stack limits */ |
863 | #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS) | |
864 | ||
72b05b99 | 865 | static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring) |
f5cd7872 | 866 | { |
34c20624 | 867 | struct pasemi_dmachan *chan = &txring->chan; |
72b05b99 | 868 | struct pasemi_mac *mac = txring->mac; |
ad3c20d1 | 869 | int i, j; |
ad5da10a OJ |
870 | unsigned int start, descr_count, buf_count, batch_limit; |
871 | unsigned int ring_limit; | |
02df6cfa | 872 | unsigned int total_count; |
ca7e235f | 873 | unsigned long flags; |
ad3c20d1 OJ |
874 | struct sk_buff *skbs[TX_CLEAN_BATCHSIZE]; |
875 | dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1]; | |
7e9916e9 OJ |
876 | int nf[TX_CLEAN_BATCHSIZE]; |
877 | int nr_frags; | |
f5cd7872 | 878 | |
02df6cfa | 879 | total_count = 0; |
ad5da10a | 880 | batch_limit = TX_CLEAN_BATCHSIZE; |
02df6cfa | 881 | restart: |
72b05b99 | 882 | spin_lock_irqsave(&txring->lock, flags); |
f5cd7872 | 883 | |
72b05b99 OJ |
884 | start = txring->next_to_clean; |
885 | ring_limit = txring->next_to_fill; | |
ad5da10a | 886 | |
7e9916e9 OJ |
887 | prefetch(&TX_DESC_INFO(txring, start+1).skb); |
888 | ||
ad5da10a OJ |
889 | /* Compensate for when fill has wrapped but clean has not */ |
890 | if (start > ring_limit) | |
891 | ring_limit += TX_RING_SIZE; | |
02df6cfa | 892 | |
ad3c20d1 OJ |
893 | buf_count = 0; |
894 | descr_count = 0; | |
f5cd7872 | 895 | |
ad3c20d1 | 896 | for (i = start; |
ad5da10a | 897 | descr_count < batch_limit && i < ring_limit; |
ad3c20d1 | 898 | i += buf_count) { |
72b05b99 | 899 | u64 mactx = TX_DESC(txring, i); |
ad5da10a | 900 | struct sk_buff *skb; |
ad3c20d1 | 901 | |
fc9e4d2a | 902 | if ((mactx & XCT_MACTX_E) || |
34c20624 | 903 | (*chan->status & PAS_STATUS_ERROR)) |
fc9e4d2a | 904 | pasemi_mac_tx_error(mac, mactx); |
69c29d89 | 905 | |
8d636d8b OJ |
906 | /* Skip over control descriptors */ |
907 | if (!(mactx & XCT_MACTX_LLEN_M)) { | |
908 | TX_DESC(txring, i) = 0; | |
909 | TX_DESC(txring, i+1) = 0; | |
910 | buf_count = 2; | |
911 | continue; | |
912 | } | |
913 | ||
914 | skb = TX_DESC_INFO(txring, i+1).skb; | |
915 | nr_frags = TX_DESC_INFO(txring, i).dma; | |
916 | ||
fc9e4d2a | 917 | if (unlikely(mactx & XCT_MACTX_O)) |
02df6cfa | 918 | /* Not yet transmitted */ |
f5cd7872 OJ |
919 | break; |
920 | ||
7e9916e9 OJ |
921 | buf_count = 2 + nr_frags; |
922 | /* Since we always fill with an even number of entries, make | |
923 | * sure we skip any unused one at the end as well. | |
924 | */ | |
925 | if (buf_count & 1) | |
926 | buf_count++; | |
ad3c20d1 | 927 | |
7e9916e9 | 928 | for (j = 0; j <= nr_frags; j++) |
72b05b99 | 929 | dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma; |
ad3c20d1 | 930 | |
7e9916e9 OJ |
931 | skbs[descr_count] = skb; |
932 | nf[descr_count] = nr_frags; | |
933 | ||
72b05b99 OJ |
934 | TX_DESC(txring, i) = 0; |
935 | TX_DESC(txring, i+1) = 0; | |
fc9e4d2a | 936 | |
ad3c20d1 | 937 | descr_count++; |
f5cd7872 | 938 | } |
72b05b99 | 939 | txring->next_to_clean = i & (TX_RING_SIZE-1); |
ad3c20d1 | 940 | |
72b05b99 | 941 | spin_unlock_irqrestore(&txring->lock, flags); |
0ce68c74 OJ |
942 | netif_wake_queue(mac->netdev); |
943 | ||
ad3c20d1 | 944 | for (i = 0; i < descr_count; i++) |
7e9916e9 | 945 | pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]); |
02df6cfa | 946 | |
ad3c20d1 | 947 | total_count += descr_count; |
02df6cfa OJ |
948 | |
949 | /* If the batch was full, try to clean more */ | |
ad5da10a | 950 | if (descr_count == batch_limit) |
02df6cfa OJ |
951 | goto restart; |
952 | ||
953 | return total_count; | |
f5cd7872 OJ |
954 | } |
955 | ||
956 | ||
957 | static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |
958 | { | |
5c15332b | 959 | const struct pasemi_mac_rxring *rxring = data; |
34c20624 | 960 | struct pasemi_mac *mac = rxring->mac; |
5c15332b | 961 | const struct pasemi_dmachan *chan = &rxring->chan; |
f5cd7872 OJ |
962 | unsigned int reg; |
963 | ||
34c20624 | 964 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
965 | return IRQ_NONE; |
966 | ||
6dfa7522 OJ |
967 | /* Don't reset packet count so it won't fire again but clear |
968 | * all others. | |
969 | */ | |
970 | ||
6dfa7522 | 971 | reg = 0; |
34c20624 | 972 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 973 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; |
34c20624 | 974 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 975 | reg |= PAS_IOB_DMA_RXCH_RESET_DINTC; |
f5cd7872 | 976 | |
288379f0 | 977 | napi_schedule(&mac->napi); |
6dfa7522 | 978 | |
34c20624 | 979 | write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg); |
f5cd7872 OJ |
980 | |
981 | return IRQ_HANDLED; | |
982 | } | |
983 | ||
61cec3bd OJ |
984 | #define TX_CLEAN_INTERVAL HZ |
985 | ||
986 | static void pasemi_mac_tx_timer(unsigned long data) | |
987 | { | |
988 | struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data; | |
989 | struct pasemi_mac *mac = txring->mac; | |
990 | ||
991 | pasemi_mac_clean_tx(txring); | |
992 | ||
993 | mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL); | |
994 | ||
995 | pasemi_mac_restart_tx_intr(mac); | |
996 | } | |
997 | ||
f5cd7872 OJ |
998 | static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) |
999 | { | |
72b05b99 | 1000 | struct pasemi_mac_txring *txring = data; |
5c15332b | 1001 | const struct pasemi_dmachan *chan = &txring->chan; |
61cec3bd OJ |
1002 | struct pasemi_mac *mac = txring->mac; |
1003 | unsigned int reg; | |
f5cd7872 | 1004 | |
34c20624 | 1005 | if (!(*chan->status & PAS_STATUS_CAUSE_M)) |
f5cd7872 OJ |
1006 | return IRQ_NONE; |
1007 | ||
61cec3bd | 1008 | reg = 0; |
6dfa7522 | 1009 | |
34c20624 | 1010 | if (*chan->status & PAS_STATUS_SOFT) |
6dfa7522 | 1011 | reg |= PAS_IOB_DMA_TXCH_RESET_SINTC; |
34c20624 | 1012 | if (*chan->status & PAS_STATUS_ERROR) |
6dfa7522 | 1013 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; |
f5cd7872 | 1014 | |
61cec3bd OJ |
1015 | mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2); |
1016 | ||
288379f0 | 1017 | napi_schedule(&mac->napi); |
61cec3bd OJ |
1018 | |
1019 | if (reg) | |
1020 | write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg); | |
f5cd7872 | 1021 | |
f5cd7872 OJ |
1022 | return IRQ_HANDLED; |
1023 | } | |
1024 | ||
bb6e9590 OJ |
1025 | static void pasemi_adjust_link(struct net_device *dev) |
1026 | { | |
1027 | struct pasemi_mac *mac = netdev_priv(dev); | |
1028 | int msg; | |
1029 | unsigned int flags; | |
1030 | unsigned int new_flags; | |
1031 | ||
1032 | if (!mac->phydev->link) { | |
1033 | /* If no link, MAC speed settings don't matter. Just report | |
1034 | * link down and return. | |
1035 | */ | |
1036 | if (mac->link && netif_msg_link(mac)) | |
1037 | printk(KERN_INFO "%s: Link is down.\n", dev->name); | |
1038 | ||
1039 | netif_carrier_off(dev); | |
b0cd2f90 | 1040 | pasemi_mac_intf_disable(mac); |
bb6e9590 OJ |
1041 | mac->link = 0; |
1042 | ||
1043 | return; | |
b0cd2f90 OJ |
1044 | } else { |
1045 | pasemi_mac_intf_enable(mac); | |
bb6e9590 | 1046 | netif_carrier_on(dev); |
b0cd2f90 | 1047 | } |
bb6e9590 | 1048 | |
a85b9422 | 1049 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
bb6e9590 OJ |
1050 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | |
1051 | PAS_MAC_CFG_PCFG_TSR_M); | |
1052 | ||
1053 | if (!mac->phydev->duplex) | |
1054 | new_flags |= PAS_MAC_CFG_PCFG_HD; | |
1055 | ||
1056 | switch (mac->phydev->speed) { | |
1057 | case 1000: | |
1058 | new_flags |= PAS_MAC_CFG_PCFG_SPD_1G | | |
1059 | PAS_MAC_CFG_PCFG_TSR_1G; | |
1060 | break; | |
1061 | case 100: | |
1062 | new_flags |= PAS_MAC_CFG_PCFG_SPD_100M | | |
1063 | PAS_MAC_CFG_PCFG_TSR_100M; | |
1064 | break; | |
1065 | case 10: | |
1066 | new_flags |= PAS_MAC_CFG_PCFG_SPD_10M | | |
1067 | PAS_MAC_CFG_PCFG_TSR_10M; | |
1068 | break; | |
1069 | default: | |
1070 | printk("Unsupported speed %d\n", mac->phydev->speed); | |
1071 | } | |
1072 | ||
1073 | /* Print on link or speed/duplex change */ | |
1074 | msg = mac->link != mac->phydev->link || flags != new_flags; | |
1075 | ||
1076 | mac->duplex = mac->phydev->duplex; | |
1077 | mac->speed = mac->phydev->speed; | |
1078 | mac->link = mac->phydev->link; | |
1079 | ||
1080 | if (new_flags != flags) | |
a85b9422 | 1081 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); |
bb6e9590 OJ |
1082 | |
1083 | if (msg && netif_msg_link(mac)) | |
1084 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | |
1085 | dev->name, mac->speed, mac->duplex ? "full" : "half"); | |
1086 | } | |
1087 | ||
1088 | static int pasemi_mac_phy_init(struct net_device *dev) | |
1089 | { | |
1090 | struct pasemi_mac *mac = netdev_priv(dev); | |
1091 | struct device_node *dn, *phy_dn; | |
1092 | struct phy_device *phydev; | |
bb6e9590 OJ |
1093 | |
1094 | dn = pci_device_to_OF_node(mac->pdev); | |
1dd2d06c | 1095 | phy_dn = of_parse_phandle(dn, "phy-handle", 0); |
bb6e9590 OJ |
1096 | of_node_put(phy_dn); |
1097 | ||
1098 | mac->link = 0; | |
1099 | mac->speed = 0; | |
1100 | mac->duplex = -1; | |
1101 | ||
1dd2d06c GL |
1102 | phydev = of_phy_connect(dev, phy_dn, &pasemi_adjust_link, 0, |
1103 | PHY_INTERFACE_MODE_SGMII); | |
bb6e9590 | 1104 | |
beb5ac20 | 1105 | if (!phydev) { |
bb6e9590 | 1106 | printk(KERN_ERR "%s: Could not attach to phy\n", dev->name); |
beb5ac20 | 1107 | return -ENODEV; |
bb6e9590 OJ |
1108 | } |
1109 | ||
1110 | mac->phydev = phydev; | |
1111 | ||
1112 | return 0; | |
bb6e9590 OJ |
1113 | } |
1114 | ||
1115 | ||
f5cd7872 OJ |
1116 | static int pasemi_mac_open(struct net_device *dev) |
1117 | { | |
1118 | struct pasemi_mac *mac = netdev_priv(dev); | |
1119 | unsigned int flags; | |
e37c772e | 1120 | int i, ret; |
f5cd7872 OJ |
1121 | |
1122 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | | |
1123 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | |
1124 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | |
1125 | ||
a85b9422 | 1126 | write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); |
f5cd7872 | 1127 | |
f5cd7872 OJ |
1128 | ret = pasemi_mac_setup_rx_resources(dev); |
1129 | if (ret) | |
1130 | goto out_rx_resources; | |
1131 | ||
34c20624 | 1132 | mac->tx = pasemi_mac_setup_tx_resources(dev); |
72b05b99 OJ |
1133 | |
1134 | if (!mac->tx) | |
1135 | goto out_tx_ring; | |
f5cd7872 | 1136 | |
1724ac2e OJ |
1137 | /* We might already have allocated rings in case mtu was changed |
1138 | * before interface was brought up. | |
1139 | */ | |
1140 | if (dev->mtu > 1500 && !mac->num_cs) { | |
8d636d8b OJ |
1141 | pasemi_mac_setup_csrings(mac); |
1142 | if (!mac->num_cs) | |
1143 | goto out_tx_ring; | |
1144 | } | |
1145 | ||
e37c772e OJ |
1146 | /* Zero out rmon counters */ |
1147 | for (i = 0; i < 32; i++) | |
1148 | write_mac_reg(mac, PAS_MAC_RMON(i), 0); | |
1149 | ||
906674ab OJ |
1150 | /* 0x3ff with 33MHz clock is about 31us */ |
1151 | write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG, | |
1152 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff)); | |
1153 | ||
34c20624 | 1154 | write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno), |
28ae79f5 | 1155 | PAS_IOB_DMA_RXCH_CFG_CNTTH(256)); |
34c20624 OJ |
1156 | |
1157 | write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno), | |
61cec3bd | 1158 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); |
34c20624 | 1159 | |
a85b9422 | 1160 | write_mac_reg(mac, PAS_MAC_IPC_CHNL, |
34c20624 OJ |
1161 | PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) | |
1162 | PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno)); | |
f5cd7872 OJ |
1163 | |
1164 | /* enable rx if */ | |
34c20624 OJ |
1165 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
1166 | PAS_DMA_RXINT_RCMDSTA_EN | | |
1167 | PAS_DMA_RXINT_RCMDSTA_DROPS_M | | |
1168 | PAS_DMA_RXINT_RCMDSTA_BP | | |
1169 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1170 | PAS_DMA_RXINT_RCMDSTA_BT); | |
f5cd7872 OJ |
1171 | |
1172 | /* enable rx channel */ | |
34c20624 OJ |
1173 | pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU | |
1174 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1175 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1176 | PAS_DMA_RXCHAN_CCMDSTA_DT); | |
f5cd7872 OJ |
1177 | |
1178 | /* enable tx channel */ | |
34c20624 OJ |
1179 | pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ | |
1180 | PAS_DMA_TXCHAN_TCMDSTA_DB | | |
1181 | PAS_DMA_TXCHAN_TCMDSTA_DE | | |
1182 | PAS_DMA_TXCHAN_TCMDSTA_DA); | |
f5cd7872 | 1183 | |
928773c2 | 1184 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE); |
f5cd7872 | 1185 | |
34c20624 OJ |
1186 | write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno), |
1187 | RX_RING_SIZE>>1); | |
b5254eee | 1188 | |
72b05b99 OJ |
1189 | /* Clear out any residual packet count state from firmware */ |
1190 | pasemi_mac_restart_rx_intr(mac); | |
1191 | pasemi_mac_restart_tx_intr(mac); | |
1192 | ||
b0cd2f90 | 1193 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; |
36033766 OJ |
1194 | |
1195 | if (mac->type == MAC_TYPE_GMAC) | |
1196 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | |
1197 | else | |
1198 | flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G; | |
1199 | ||
1200 | /* Enable interface in MAC */ | |
1201 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); | |
1202 | ||
bb6e9590 | 1203 | ret = pasemi_mac_phy_init(dev); |
b0cd2f90 OJ |
1204 | if (ret) { |
1205 | /* Since we won't get link notification, just enable RX */ | |
1206 | pasemi_mac_intf_enable(mac); | |
1207 | if (mac->type == MAC_TYPE_GMAC) { | |
1208 | /* Warn for missing PHY on SGMII (1Gig) ports */ | |
1209 | dev_warn(&mac->pdev->dev, | |
1210 | "PHY init failed: %d.\n", ret); | |
1211 | dev_warn(&mac->pdev->dev, | |
1212 | "Defaulting to 1Gbit full duplex\n"); | |
1213 | } | |
8304b633 | 1214 | } |
bb6e9590 | 1215 | |
f5cd7872 | 1216 | netif_start_queue(dev); |
bea3348e | 1217 | napi_enable(&mac->napi); |
f5cd7872 | 1218 | |
72b05b99 OJ |
1219 | snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx", |
1220 | dev->name); | |
771f7404 | 1221 | |
a0607fd3 | 1222 | ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, IRQF_DISABLED, |
72b05b99 | 1223 | mac->tx_irq_name, mac->tx); |
f5cd7872 OJ |
1224 | if (ret) { |
1225 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1226 | mac->tx->chan.irq, ret); |
f5cd7872 OJ |
1227 | goto out_tx_int; |
1228 | } | |
1229 | ||
72b05b99 OJ |
1230 | snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx", |
1231 | dev->name); | |
1232 | ||
a0607fd3 | 1233 | ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, IRQF_DISABLED, |
34c20624 | 1234 | mac->rx_irq_name, mac->rx); |
f5cd7872 OJ |
1235 | if (ret) { |
1236 | dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n", | |
34c20624 | 1237 | mac->rx->chan.irq, ret); |
f5cd7872 OJ |
1238 | goto out_rx_int; |
1239 | } | |
1240 | ||
bb6e9590 OJ |
1241 | if (mac->phydev) |
1242 | phy_start(mac->phydev); | |
1243 | ||
61cec3bd OJ |
1244 | init_timer(&mac->tx->clean_timer); |
1245 | mac->tx->clean_timer.function = pasemi_mac_tx_timer; | |
1246 | mac->tx->clean_timer.data = (unsigned long)mac->tx; | |
1247 | mac->tx->clean_timer.expires = jiffies+HZ; | |
1248 | add_timer(&mac->tx->clean_timer); | |
1249 | ||
f5cd7872 OJ |
1250 | return 0; |
1251 | ||
1252 | out_rx_int: | |
34c20624 | 1253 | free_irq(mac->tx->chan.irq, mac->tx); |
f5cd7872 | 1254 | out_tx_int: |
bea3348e | 1255 | napi_disable(&mac->napi); |
f5cd7872 | 1256 | netif_stop_queue(dev); |
72b05b99 OJ |
1257 | out_tx_ring: |
1258 | if (mac->tx) | |
1259 | pasemi_mac_free_tx_resources(mac); | |
1260 | pasemi_mac_free_rx_resources(mac); | |
f5cd7872 OJ |
1261 | out_rx_resources: |
1262 | ||
1263 | return ret; | |
1264 | } | |
1265 | ||
1266 | #define MAX_RETRIES 5000 | |
1267 | ||
ef1ea0b4 OJ |
1268 | static void pasemi_mac_pause_txchan(struct pasemi_mac *mac) |
1269 | { | |
1270 | unsigned int sta, retries; | |
1271 | int txch = tx_ring(mac)->chan.chno; | |
1272 | ||
1273 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), | |
1274 | PAS_DMA_TXCHAN_TCMDSTA_ST); | |
1275 | ||
1276 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1277 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); | |
1278 | if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) | |
1279 | break; | |
1280 | cond_resched(); | |
1281 | } | |
1282 | ||
1283 | if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT) | |
1284 | dev_err(&mac->dma_pdev->dev, | |
1285 | "Failed to stop tx channel, tcmdsta %08x\n", sta); | |
1286 | ||
1287 | write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0); | |
1288 | } | |
1289 | ||
1290 | static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac) | |
1291 | { | |
1292 | unsigned int sta, retries; | |
1293 | int rxch = rx_ring(mac)->chan.chno; | |
1294 | ||
1295 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), | |
1296 | PAS_DMA_RXCHAN_CCMDSTA_ST); | |
1297 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1298 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); | |
1299 | if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) | |
1300 | break; | |
1301 | cond_resched(); | |
1302 | } | |
1303 | ||
1304 | if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT) | |
1305 | dev_err(&mac->dma_pdev->dev, | |
1306 | "Failed to stop rx channel, ccmdsta 08%x\n", sta); | |
1307 | write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0); | |
1308 | } | |
1309 | ||
1310 | static void pasemi_mac_pause_rxint(struct pasemi_mac *mac) | |
1311 | { | |
1312 | unsigned int sta, retries; | |
1313 | ||
1314 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
1315 | PAS_DMA_RXINT_RCMDSTA_ST); | |
1316 | for (retries = 0; retries < MAX_RETRIES; retries++) { | |
1317 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
1318 | if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT)) | |
1319 | break; | |
1320 | cond_resched(); | |
1321 | } | |
1322 | ||
1323 | if (sta & PAS_DMA_RXINT_RCMDSTA_ACT) | |
1324 | dev_err(&mac->dma_pdev->dev, | |
1325 | "Failed to stop rx interface, rcmdsta %08x\n", sta); | |
1326 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | |
1327 | } | |
1328 | ||
f5cd7872 OJ |
1329 | static int pasemi_mac_close(struct net_device *dev) |
1330 | { | |
1331 | struct pasemi_mac *mac = netdev_priv(dev); | |
9e81d331 | 1332 | unsigned int sta; |
8d636d8b | 1333 | int rxch, txch, i; |
34c20624 OJ |
1334 | |
1335 | rxch = rx_ring(mac)->chan.chno; | |
1336 | txch = tx_ring(mac)->chan.chno; | |
f5cd7872 | 1337 | |
bb6e9590 OJ |
1338 | if (mac->phydev) { |
1339 | phy_stop(mac->phydev); | |
1340 | phy_disconnect(mac->phydev); | |
1341 | } | |
1342 | ||
61cec3bd OJ |
1343 | del_timer_sync(&mac->tx->clean_timer); |
1344 | ||
f5cd7872 | 1345 | netif_stop_queue(dev); |
bea3348e | 1346 | napi_disable(&mac->napi); |
f5cd7872 | 1347 | |
34c20624 | 1348 | sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
9e81d331 OJ |
1349 | if (sta & (PAS_DMA_RXINT_RCMDSTA_BP | |
1350 | PAS_DMA_RXINT_RCMDSTA_OO | | |
1351 | PAS_DMA_RXINT_RCMDSTA_BT)) | |
1352 | printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta); | |
1353 | ||
34c20624 | 1354 | sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch)); |
9e81d331 OJ |
1355 | if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU | |
1356 | PAS_DMA_RXCHAN_CCMDSTA_OD | | |
1357 | PAS_DMA_RXCHAN_CCMDSTA_FD | | |
1358 | PAS_DMA_RXCHAN_CCMDSTA_DT)) | |
1359 | printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta); | |
1360 | ||
34c20624 | 1361 | sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch)); |
72b05b99 OJ |
1362 | if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB | |
1363 | PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA)) | |
9e81d331 OJ |
1364 | printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta); |
1365 | ||
f5cd7872 | 1366 | /* Clean out any pending buffers */ |
72b05b99 OJ |
1367 | pasemi_mac_clean_tx(tx_ring(mac)); |
1368 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
f5cd7872 | 1369 | |
ef1ea0b4 OJ |
1370 | pasemi_mac_pause_txchan(mac); |
1371 | pasemi_mac_pause_rxint(mac); | |
1372 | pasemi_mac_pause_rxchan(mac); | |
1145d954 | 1373 | pasemi_mac_intf_disable(mac); |
f5cd7872 | 1374 | |
34c20624 OJ |
1375 | free_irq(mac->tx->chan.irq, mac->tx); |
1376 | free_irq(mac->rx->chan.irq, mac->rx); | |
f5cd7872 | 1377 | |
1724ac2e | 1378 | for (i = 0; i < mac->num_cs; i++) { |
8d636d8b | 1379 | pasemi_mac_free_csring(mac->cs[i]); |
1724ac2e OJ |
1380 | mac->cs[i] = NULL; |
1381 | } | |
1382 | ||
1383 | mac->num_cs = 0; | |
8d636d8b | 1384 | |
f5cd7872 | 1385 | /* Free resources */ |
72b05b99 OJ |
1386 | pasemi_mac_free_rx_resources(mac); |
1387 | pasemi_mac_free_tx_resources(mac); | |
f5cd7872 OJ |
1388 | |
1389 | return 0; | |
1390 | } | |
1391 | ||
8d636d8b OJ |
1392 | static void pasemi_mac_queue_csdesc(const struct sk_buff *skb, |
1393 | const dma_addr_t *map, | |
1394 | const unsigned int *map_size, | |
1395 | struct pasemi_mac_txring *txring, | |
1396 | struct pasemi_mac_csring *csring) | |
1397 | { | |
1398 | u64 fund; | |
1399 | dma_addr_t cs_dest; | |
1400 | const int nh_off = skb_network_offset(skb); | |
1401 | const int nh_len = skb_network_header_len(skb); | |
1402 | const int nfrags = skb_shinfo(skb)->nr_frags; | |
1403 | int cs_size, i, fill, hdr, cpyhdr, evt; | |
1404 | dma_addr_t csdma; | |
1405 | ||
1406 | fund = XCT_FUN_ST | XCT_FUN_RR_8BRES | | |
1407 | XCT_FUN_O | XCT_FUN_FUN(csring->fun) | | |
1408 | XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) | | |
1409 | XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE; | |
1410 | ||
1411 | switch (ip_hdr(skb)->protocol) { | |
1412 | case IPPROTO_TCP: | |
1413 | fund |= XCT_FUN_SIG_TCP4; | |
1414 | /* TCP checksum is 16 bytes into the header */ | |
1415 | cs_dest = map[0] + skb_transport_offset(skb) + 16; | |
1416 | break; | |
1417 | case IPPROTO_UDP: | |
1418 | fund |= XCT_FUN_SIG_UDP4; | |
1419 | /* UDP checksum is 6 bytes into the header */ | |
1420 | cs_dest = map[0] + skb_transport_offset(skb) + 6; | |
1421 | break; | |
1422 | default: | |
1423 | BUG(); | |
1424 | } | |
1425 | ||
1426 | /* Do the checksum offloaded */ | |
1427 | fill = csring->next_to_fill; | |
1428 | hdr = fill; | |
1429 | ||
1430 | CS_DESC(csring, fill++) = fund; | |
1431 | /* Room for 8BRES. Checksum result is really 2 bytes into it */ | |
1432 | csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2; | |
1433 | CS_DESC(csring, fill++) = 0; | |
1434 | ||
1435 | CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off); | |
1436 | for (i = 1; i <= nfrags; i++) | |
1437 | CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); | |
1438 | ||
1439 | fill += i; | |
1440 | if (fill & 1) | |
1441 | fill++; | |
1442 | ||
1443 | /* Copy the result into the TCP packet */ | |
1444 | cpyhdr = fill; | |
1445 | CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) | | |
1446 | XCT_FUN_LLEN(2) | XCT_FUN_SE; | |
1447 | CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T; | |
1448 | CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma); | |
1449 | fill++; | |
1450 | ||
1451 | evt = !csring->last_event; | |
1452 | csring->last_event = evt; | |
1453 | ||
1454 | /* Event handshaking with MAC TX */ | |
1455 | CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1456 | CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]); | |
1457 | CS_DESC(csring, fill++) = 0; | |
1458 | CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1459 | CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]); | |
1460 | CS_DESC(csring, fill++) = 0; | |
1461 | csring->next_to_fill = fill & (CS_RING_SIZE-1); | |
1462 | ||
1463 | cs_size = fill - hdr; | |
1464 | write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1); | |
1465 | ||
1466 | /* TX-side event handshaking */ | |
1467 | fill = txring->next_to_fill; | |
1468 | TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1469 | CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]); | |
1470 | TX_DESC(txring, fill++) = 0; | |
1471 | TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O | | |
1472 | CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]); | |
1473 | TX_DESC(txring, fill++) = 0; | |
1474 | txring->next_to_fill = fill; | |
1475 | ||
1476 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2); | |
8d636d8b OJ |
1477 | } |
1478 | ||
f5cd7872 OJ |
1479 | static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) |
1480 | { | |
8d636d8b OJ |
1481 | struct pasemi_mac * const mac = netdev_priv(dev); |
1482 | struct pasemi_mac_txring * const txring = tx_ring(mac); | |
1483 | struct pasemi_mac_csring *csring; | |
1484 | u64 dflags = 0; | |
1485 | u64 mactx; | |
ad3c20d1 OJ |
1486 | dma_addr_t map[MAX_SKB_FRAGS+1]; |
1487 | unsigned int map_size[MAX_SKB_FRAGS+1]; | |
ca7e235f | 1488 | unsigned long flags; |
ad3c20d1 | 1489 | int i, nfrags; |
5c15332b | 1490 | int fill; |
8d636d8b OJ |
1491 | const int nh_off = skb_network_offset(skb); |
1492 | const int nh_len = skb_network_header_len(skb); | |
f5cd7872 | 1493 | |
8d636d8b | 1494 | prefetch(&txring->ring_info); |
d56f90a7 | 1495 | |
8d636d8b | 1496 | dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD; |
f5cd7872 | 1497 | |
ad3c20d1 OJ |
1498 | nfrags = skb_shinfo(skb)->nr_frags; |
1499 | ||
1500 | map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb), | |
1501 | PCI_DMA_TODEVICE); | |
1502 | map_size[0] = skb_headlen(skb); | |
8d8bb39b | 1503 | if (pci_dma_mapping_error(mac->dma_pdev, map[0])) |
ad3c20d1 OJ |
1504 | goto out_err_nolock; |
1505 | ||
1506 | for (i = 0; i < nfrags; i++) { | |
1507 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
f5cd7872 | 1508 | |
4bb97cae | 1509 | map[i + 1] = skb_frag_dma_map(&mac->dma_pdev->dev, frag, 0, |
9e903e08 ED |
1510 | skb_frag_size(frag), DMA_TO_DEVICE); |
1511 | map_size[i+1] = skb_frag_size(frag); | |
5d6bcdfe | 1512 | if (dma_mapping_error(&mac->dma_pdev->dev, map[i + 1])) { |
ad3c20d1 OJ |
1513 | nfrags = i; |
1514 | goto out_err_nolock; | |
1515 | } | |
1516 | } | |
f5cd7872 | 1517 | |
8d636d8b OJ |
1518 | if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) { |
1519 | switch (ip_hdr(skb)->protocol) { | |
1520 | case IPPROTO_TCP: | |
1521 | dflags |= XCT_MACTX_CSUM_TCP; | |
1522 | dflags |= XCT_MACTX_IPH(nh_len >> 2); | |
1523 | dflags |= XCT_MACTX_IPO(nh_off); | |
1524 | break; | |
1525 | case IPPROTO_UDP: | |
1526 | dflags |= XCT_MACTX_CSUM_UDP; | |
1527 | dflags |= XCT_MACTX_IPH(nh_len >> 2); | |
1528 | dflags |= XCT_MACTX_IPO(nh_off); | |
1529 | break; | |
1530 | default: | |
1531 | WARN_ON(1); | |
1532 | } | |
1533 | } | |
26fcfa95 | 1534 | |
8d636d8b | 1535 | mactx = dflags | XCT_MACTX_LLEN(skb->len); |
f5cd7872 OJ |
1536 | |
1537 | spin_lock_irqsave(&txring->lock, flags); | |
1538 | ||
ad5da10a OJ |
1539 | /* Avoid stepping on the same cache line that the DMA controller |
1540 | * is currently about to send, so leave at least 8 words available. | |
1541 | * Total free space needed is mactx + fragments + 8 | |
1542 | */ | |
8d636d8b | 1543 | if (RING_AVAIL(txring) < nfrags + 14) { |
ad5da10a OJ |
1544 | /* no room -- stop the queue and wait for tx intr */ |
1545 | netif_stop_queue(dev); | |
1546 | goto out_err; | |
f5cd7872 OJ |
1547 | } |
1548 | ||
8d636d8b OJ |
1549 | /* Queue up checksum + event descriptors, if needed */ |
1550 | if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) { | |
1551 | csring = mac->cs[mac->last_cs]; | |
1552 | mac->last_cs = (mac->last_cs + 1) % mac->num_cs; | |
1553 | ||
1554 | pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring); | |
1555 | } | |
1556 | ||
1557 | fill = txring->next_to_fill; | |
5c15332b | 1558 | TX_DESC(txring, fill) = mactx; |
7e9916e9 | 1559 | TX_DESC_INFO(txring, fill).dma = nfrags; |
5c15332b OJ |
1560 | fill++; |
1561 | TX_DESC_INFO(txring, fill).skb = skb; | |
ad3c20d1 | 1562 | for (i = 0; i <= nfrags; i++) { |
5c15332b | 1563 | TX_DESC(txring, fill+i) = |
72b05b99 | 1564 | XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]); |
5c15332b | 1565 | TX_DESC_INFO(txring, fill+i).dma = map[i]; |
ad3c20d1 OJ |
1566 | } |
1567 | ||
1568 | /* We have to add an even number of 8-byte entries to the ring | |
1569 | * even if the last one is unused. That means always an odd number | |
1570 | * of pointers + one mactx descriptor. | |
1571 | */ | |
1572 | if (nfrags & 1) | |
1573 | nfrags++; | |
fc9e4d2a | 1574 | |
5c15332b | 1575 | txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1); |
f5cd7872 | 1576 | |
09f75cd7 JG |
1577 | dev->stats.tx_packets++; |
1578 | dev->stats.tx_bytes += skb->len; | |
f5cd7872 OJ |
1579 | |
1580 | spin_unlock_irqrestore(&txring->lock, flags); | |
1581 | ||
34c20624 | 1582 | write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1); |
f5cd7872 OJ |
1583 | |
1584 | return NETDEV_TX_OK; | |
1585 | ||
1586 | out_err: | |
1587 | spin_unlock_irqrestore(&txring->lock, flags); | |
ad3c20d1 OJ |
1588 | out_err_nolock: |
1589 | while (nfrags--) | |
1590 | pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags], | |
1591 | PCI_DMA_TODEVICE); | |
1592 | ||
f5cd7872 OJ |
1593 | return NETDEV_TX_BUSY; |
1594 | } | |
1595 | ||
f5cd7872 OJ |
1596 | static void pasemi_mac_set_rx_mode(struct net_device *dev) |
1597 | { | |
5c15332b | 1598 | const struct pasemi_mac *mac = netdev_priv(dev); |
f5cd7872 OJ |
1599 | unsigned int flags; |
1600 | ||
a85b9422 | 1601 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
f5cd7872 OJ |
1602 | |
1603 | /* Set promiscuous */ | |
1604 | if (dev->flags & IFF_PROMISC) | |
1605 | flags |= PAS_MAC_CFG_PCFG_PR; | |
1606 | else | |
1607 | flags &= ~PAS_MAC_CFG_PCFG_PR; | |
1608 | ||
a85b9422 | 1609 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
f5cd7872 OJ |
1610 | } |
1611 | ||
1612 | ||
bea3348e | 1613 | static int pasemi_mac_poll(struct napi_struct *napi, int budget) |
f5cd7872 | 1614 | { |
bea3348e | 1615 | struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi); |
bea3348e | 1616 | int pkts; |
f5cd7872 | 1617 | |
72b05b99 OJ |
1618 | pasemi_mac_clean_tx(tx_ring(mac)); |
1619 | pkts = pasemi_mac_clean_rx(rx_ring(mac), budget); | |
bea3348e | 1620 | if (pkts < budget) { |
f5cd7872 | 1621 | /* all done, no more packets present */ |
288379f0 | 1622 | napi_complete(napi); |
f5cd7872 | 1623 | |
1b0335ea | 1624 | pasemi_mac_restart_rx_intr(mac); |
61cec3bd | 1625 | pasemi_mac_restart_tx_intr(mac); |
f5cd7872 | 1626 | } |
bea3348e | 1627 | return pkts; |
f5cd7872 OJ |
1628 | } |
1629 | ||
6e62040c NC |
1630 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1631 | /* | |
1632 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1633 | * without having to re-enable interrupts. It's not called while | |
1634 | * the interrupt routine is executing. | |
1635 | */ | |
1636 | static void pasemi_mac_netpoll(struct net_device *dev) | |
1637 | { | |
1638 | const struct pasemi_mac *mac = netdev_priv(dev); | |
1639 | ||
1640 | disable_irq(mac->tx->chan.irq); | |
1641 | pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx); | |
1642 | enable_irq(mac->tx->chan.irq); | |
1643 | ||
1644 | disable_irq(mac->rx->chan.irq); | |
1645 | pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx); | |
1646 | enable_irq(mac->rx->chan.irq); | |
1647 | } | |
1648 | #endif | |
1649 | ||
ef1ea0b4 OJ |
1650 | static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu) |
1651 | { | |
1652 | struct pasemi_mac *mac = netdev_priv(dev); | |
1653 | unsigned int reg; | |
8d636d8b | 1654 | unsigned int rcmdsta = 0; |
ef1ea0b4 | 1655 | int running; |
8d636d8b | 1656 | int ret = 0; |
ef1ea0b4 OJ |
1657 | |
1658 | if (new_mtu < PE_MIN_MTU || new_mtu > PE_MAX_MTU) | |
1659 | return -EINVAL; | |
1660 | ||
1661 | running = netif_running(dev); | |
1662 | ||
1663 | if (running) { | |
1664 | /* Need to stop the interface, clean out all already | |
1665 | * received buffers, free all unused buffers on the RX | |
1666 | * interface ring, then finally re-fill the rx ring with | |
1667 | * the new-size buffers and restart. | |
1668 | */ | |
1669 | ||
1670 | napi_disable(&mac->napi); | |
1671 | netif_tx_disable(dev); | |
1672 | pasemi_mac_intf_disable(mac); | |
1673 | ||
1674 | rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); | |
1675 | pasemi_mac_pause_rxint(mac); | |
1676 | pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE); | |
1677 | pasemi_mac_free_rx_buffers(mac); | |
8d636d8b OJ |
1678 | |
1679 | } | |
1680 | ||
1681 | /* Setup checksum channels if large MTU and none already allocated */ | |
1682 | if (new_mtu > 1500 && !mac->num_cs) { | |
1683 | pasemi_mac_setup_csrings(mac); | |
1684 | if (!mac->num_cs) { | |
1685 | ret = -ENOMEM; | |
1686 | goto out; | |
1687 | } | |
ef1ea0b4 OJ |
1688 | } |
1689 | ||
1690 | /* Change maxf, i.e. what size frames are accepted. | |
1691 | * Need room for ethernet header and CRC word | |
1692 | */ | |
1693 | reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG); | |
1694 | reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M; | |
1695 | reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4); | |
1696 | write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg); | |
1697 | ||
1698 | dev->mtu = new_mtu; | |
1699 | /* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ | |
1700 | mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; | |
1701 | ||
8d636d8b | 1702 | out: |
ef1ea0b4 OJ |
1703 | if (running) { |
1704 | write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | |
1705 | rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN); | |
1706 | ||
1707 | rx_ring(mac)->next_to_fill = 0; | |
1708 | pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1); | |
1709 | ||
1710 | napi_enable(&mac->napi); | |
1711 | netif_start_queue(dev); | |
1712 | pasemi_mac_intf_enable(mac); | |
1713 | } | |
1714 | ||
8d636d8b | 1715 | return ret; |
ef1ea0b4 OJ |
1716 | } |
1717 | ||
9e0ac841 AB |
1718 | static const struct net_device_ops pasemi_netdev_ops = { |
1719 | .ndo_open = pasemi_mac_open, | |
1720 | .ndo_stop = pasemi_mac_close, | |
1721 | .ndo_start_xmit = pasemi_mac_start_tx, | |
afc4b13d | 1722 | .ndo_set_rx_mode = pasemi_mac_set_rx_mode, |
9e0ac841 AB |
1723 | .ndo_set_mac_address = pasemi_mac_set_mac_addr, |
1724 | .ndo_change_mtu = pasemi_mac_change_mtu, | |
1725 | .ndo_validate_addr = eth_validate_addr, | |
1726 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1727 | .ndo_poll_controller = pasemi_mac_netpoll, | |
1728 | #endif | |
1729 | }; | |
1730 | ||
03c4d832 | 1731 | static int |
f5cd7872 OJ |
1732 | pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
1733 | { | |
f5cd7872 OJ |
1734 | struct net_device *dev; |
1735 | struct pasemi_mac *mac; | |
15b8e191 | 1736 | int err, ret; |
f5cd7872 OJ |
1737 | |
1738 | err = pci_enable_device(pdev); | |
1739 | if (err) | |
1740 | return err; | |
1741 | ||
1742 | dev = alloc_etherdev(sizeof(struct pasemi_mac)); | |
1743 | if (dev == NULL) { | |
f5cd7872 OJ |
1744 | err = -ENOMEM; |
1745 | goto out_disable_device; | |
1746 | } | |
1747 | ||
f5cd7872 OJ |
1748 | pci_set_drvdata(pdev, dev); |
1749 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1750 | ||
1751 | mac = netdev_priv(dev); | |
1752 | ||
1753 | mac->pdev = pdev; | |
1754 | mac->netdev = dev; | |
f5cd7872 | 1755 | |
bea3348e SH |
1756 | netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64); |
1757 | ||
5c15332b | 1758 | dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG | |
25156784 | 1759 | NETIF_F_HIGHDMA | NETIF_F_GSO; |
bea3348e | 1760 | |
28ae79f5 OJ |
1761 | mac->lro_mgr.max_aggr = LRO_MAX_AGGR; |
1762 | mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS; | |
1763 | mac->lro_mgr.lro_arr = mac->lro_desc; | |
1764 | mac->lro_mgr.get_skb_header = get_skb_hdr; | |
1765 | mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID; | |
1766 | mac->lro_mgr.dev = mac->netdev; | |
1767 | mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY; | |
1768 | mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY; | |
1769 | ||
1770 | ||
34c20624 OJ |
1771 | mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); |
1772 | if (!mac->dma_pdev) { | |
1773 | dev_err(&mac->pdev->dev, "Can't find DMA Controller\n"); | |
1774 | err = -ENODEV; | |
1775 | goto out; | |
1776 | } | |
f5cd7872 | 1777 | |
34c20624 OJ |
1778 | mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); |
1779 | if (!mac->iob_pdev) { | |
1780 | dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n"); | |
1781 | err = -ENODEV; | |
1782 | goto out; | |
1783 | } | |
1784 | ||
1785 | /* get mac addr from device tree */ | |
1786 | if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) { | |
1787 | err = -ENODEV; | |
1788 | goto out; | |
1789 | } | |
1790 | memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr)); | |
1791 | ||
15b8e191 | 1792 | ret = mac_to_intf(mac); |
1793 | if (ret < 0) { | |
34c20624 OJ |
1794 | dev_err(&mac->pdev->dev, "Can't map DMA interface\n"); |
1795 | err = -ENODEV; | |
1796 | goto out; | |
1797 | } | |
15b8e191 | 1798 | mac->dma_if = ret; |
f5cd7872 OJ |
1799 | |
1800 | switch (pdev->device) { | |
1801 | case 0xa005: | |
1802 | mac->type = MAC_TYPE_GMAC; | |
1803 | break; | |
1804 | case 0xa006: | |
1805 | mac->type = MAC_TYPE_XAUI; | |
1806 | break; | |
1807 | default: | |
1808 | err = -ENODEV; | |
1809 | goto out; | |
1810 | } | |
1811 | ||
9e0ac841 | 1812 | dev->netdev_ops = &pasemi_netdev_ops; |
ef1ea0b4 OJ |
1813 | dev->mtu = PE_DEF_MTU; |
1814 | /* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */ | |
1815 | mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128; | |
1816 | ||
e37c772e | 1817 | dev->ethtool_ops = &pasemi_mac_ethtool_ops; |
f5cd7872 | 1818 | |
b6e05a1b OJ |
1819 | if (err) |
1820 | goto out; | |
f5cd7872 | 1821 | |
ceb51361 OJ |
1822 | mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
1823 | ||
bb6e9590 OJ |
1824 | /* Enable most messages by default */ |
1825 | mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1; | |
1826 | ||
f5cd7872 OJ |
1827 | err = register_netdev(dev); |
1828 | ||
1829 | if (err) { | |
1830 | dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n", | |
1831 | err); | |
1832 | goto out; | |
ea5cdccc | 1833 | } else if (netif_msg_probe(mac)) { |
e174961c | 1834 | printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n", |
f5cd7872 | 1835 | dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI", |
e174961c | 1836 | mac->dma_if, dev->dev_addr); |
ea5cdccc | 1837 | } |
f5cd7872 OJ |
1838 | |
1839 | return err; | |
1840 | ||
1841 | out: | |
b6e05a1b OJ |
1842 | if (mac->iob_pdev) |
1843 | pci_dev_put(mac->iob_pdev); | |
1844 | if (mac->dma_pdev) | |
1845 | pci_dev_put(mac->dma_pdev); | |
b6e05a1b | 1846 | |
f5cd7872 OJ |
1847 | free_netdev(dev); |
1848 | out_disable_device: | |
1849 | pci_disable_device(pdev); | |
1850 | return err; | |
1851 | ||
1852 | } | |
1853 | ||
03c4d832 | 1854 | static void pasemi_mac_remove(struct pci_dev *pdev) |
f5cd7872 OJ |
1855 | { |
1856 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1857 | struct pasemi_mac *mac; | |
1858 | ||
1859 | if (!netdev) | |
1860 | return; | |
1861 | ||
1862 | mac = netdev_priv(netdev); | |
1863 | ||
1864 | unregister_netdev(netdev); | |
1865 | ||
1866 | pci_disable_device(pdev); | |
1867 | pci_dev_put(mac->dma_pdev); | |
1868 | pci_dev_put(mac->iob_pdev); | |
1869 | ||
34c20624 OJ |
1870 | pasemi_dma_free_chan(&mac->tx->chan); |
1871 | pasemi_dma_free_chan(&mac->rx->chan); | |
b6e05a1b | 1872 | |
f5cd7872 OJ |
1873 | pci_set_drvdata(pdev, NULL); |
1874 | free_netdev(netdev); | |
1875 | } | |
1876 | ||
a3aa1884 | 1877 | static DEFINE_PCI_DEVICE_TABLE(pasemi_mac_pci_tbl) = { |
f5cd7872 OJ |
1878 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) }, |
1879 | { PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) }, | |
fd178254 | 1880 | { }, |
f5cd7872 OJ |
1881 | }; |
1882 | ||
1883 | MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl); | |
1884 | ||
1885 | static struct pci_driver pasemi_mac_driver = { | |
1886 | .name = "pasemi_mac", | |
1887 | .id_table = pasemi_mac_pci_tbl, | |
1888 | .probe = pasemi_mac_probe, | |
03c4d832 | 1889 | .remove = pasemi_mac_remove, |
f5cd7872 OJ |
1890 | }; |
1891 | ||
1892 | static void __exit pasemi_mac_cleanup_module(void) | |
1893 | { | |
1894 | pci_unregister_driver(&pasemi_mac_driver); | |
f5cd7872 OJ |
1895 | } |
1896 | ||
1897 | int pasemi_mac_init_module(void) | |
1898 | { | |
34c20624 OJ |
1899 | int err; |
1900 | ||
1901 | err = pasemi_dma_init(); | |
1902 | if (err) | |
1903 | return err; | |
1904 | ||
f5cd7872 OJ |
1905 | return pci_register_driver(&pasemi_mac_driver); |
1906 | } | |
1907 | ||
f5cd7872 OJ |
1908 | module_init(pasemi_mac_init_module); |
1909 | module_exit(pasemi_mac_cleanup_module); |