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b7370112 | 1 | /* |
2 | * drivers/net/ethernet/nxp/lpc_eth.c | |
3 | * | |
4 | * Author: Kevin Wells <kevin.wells@nxp.com> | |
5 | * | |
6 | * Copyright (C) 2010 NXP Semiconductors | |
7 | * Copyright (C) 2012 Roland Stigge <stigge@antcom.de> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | */ | |
19 | ||
20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
21 | ||
b7370112 | 22 | #include <linux/clk.h> |
1d948209 | 23 | #include <linux/crc32.h> |
b7370112 | 24 | #include <linux/etherdevice.h> |
1d948209 | 25 | #include <linux/module.h> |
b7370112 | 26 | #include <linux/of_net.h> |
1d948209 VZ |
27 | #include <linux/phy.h> |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/spinlock.h> | |
b7370112 | 30 | |
b7370112 | 31 | #include <mach/board.h> |
b7370112 | 32 | #include <mach/hardware.h> |
1d948209 | 33 | #include <mach/platform.h> |
b7370112 | 34 | |
35 | #define MODNAME "lpc-eth" | |
36 | #define DRV_VERSION "1.00" | |
b7370112 | 37 | |
38 | #define ENET_MAXF_SIZE 1536 | |
39 | #define ENET_RX_DESC 48 | |
40 | #define ENET_TX_DESC 16 | |
41 | ||
42 | #define NAPI_WEIGHT 16 | |
43 | ||
44 | /* | |
45 | * Ethernet MAC controller Register offsets | |
46 | */ | |
47 | #define LPC_ENET_MAC1(x) (x + 0x000) | |
48 | #define LPC_ENET_MAC2(x) (x + 0x004) | |
49 | #define LPC_ENET_IPGT(x) (x + 0x008) | |
50 | #define LPC_ENET_IPGR(x) (x + 0x00C) | |
51 | #define LPC_ENET_CLRT(x) (x + 0x010) | |
52 | #define LPC_ENET_MAXF(x) (x + 0x014) | |
53 | #define LPC_ENET_SUPP(x) (x + 0x018) | |
54 | #define LPC_ENET_TEST(x) (x + 0x01C) | |
55 | #define LPC_ENET_MCFG(x) (x + 0x020) | |
56 | #define LPC_ENET_MCMD(x) (x + 0x024) | |
57 | #define LPC_ENET_MADR(x) (x + 0x028) | |
58 | #define LPC_ENET_MWTD(x) (x + 0x02C) | |
59 | #define LPC_ENET_MRDD(x) (x + 0x030) | |
60 | #define LPC_ENET_MIND(x) (x + 0x034) | |
61 | #define LPC_ENET_SA0(x) (x + 0x040) | |
62 | #define LPC_ENET_SA1(x) (x + 0x044) | |
63 | #define LPC_ENET_SA2(x) (x + 0x048) | |
64 | #define LPC_ENET_COMMAND(x) (x + 0x100) | |
65 | #define LPC_ENET_STATUS(x) (x + 0x104) | |
66 | #define LPC_ENET_RXDESCRIPTOR(x) (x + 0x108) | |
67 | #define LPC_ENET_RXSTATUS(x) (x + 0x10C) | |
68 | #define LPC_ENET_RXDESCRIPTORNUMBER(x) (x + 0x110) | |
69 | #define LPC_ENET_RXPRODUCEINDEX(x) (x + 0x114) | |
70 | #define LPC_ENET_RXCONSUMEINDEX(x) (x + 0x118) | |
71 | #define LPC_ENET_TXDESCRIPTOR(x) (x + 0x11C) | |
72 | #define LPC_ENET_TXSTATUS(x) (x + 0x120) | |
73 | #define LPC_ENET_TXDESCRIPTORNUMBER(x) (x + 0x124) | |
74 | #define LPC_ENET_TXPRODUCEINDEX(x) (x + 0x128) | |
75 | #define LPC_ENET_TXCONSUMEINDEX(x) (x + 0x12C) | |
76 | #define LPC_ENET_TSV0(x) (x + 0x158) | |
77 | #define LPC_ENET_TSV1(x) (x + 0x15C) | |
78 | #define LPC_ENET_RSV(x) (x + 0x160) | |
79 | #define LPC_ENET_FLOWCONTROLCOUNTER(x) (x + 0x170) | |
80 | #define LPC_ENET_FLOWCONTROLSTATUS(x) (x + 0x174) | |
81 | #define LPC_ENET_RXFILTER_CTRL(x) (x + 0x200) | |
82 | #define LPC_ENET_RXFILTERWOLSTATUS(x) (x + 0x204) | |
83 | #define LPC_ENET_RXFILTERWOLCLEAR(x) (x + 0x208) | |
84 | #define LPC_ENET_HASHFILTERL(x) (x + 0x210) | |
85 | #define LPC_ENET_HASHFILTERH(x) (x + 0x214) | |
86 | #define LPC_ENET_INTSTATUS(x) (x + 0xFE0) | |
87 | #define LPC_ENET_INTENABLE(x) (x + 0xFE4) | |
88 | #define LPC_ENET_INTCLEAR(x) (x + 0xFE8) | |
89 | #define LPC_ENET_INTSET(x) (x + 0xFEC) | |
90 | #define LPC_ENET_POWERDOWN(x) (x + 0xFF4) | |
91 | ||
92 | /* | |
93 | * mac1 register definitions | |
94 | */ | |
95 | #define LPC_MAC1_RECV_ENABLE (1 << 0) | |
96 | #define LPC_MAC1_PASS_ALL_RX_FRAMES (1 << 1) | |
97 | #define LPC_MAC1_RX_FLOW_CONTROL (1 << 2) | |
98 | #define LPC_MAC1_TX_FLOW_CONTROL (1 << 3) | |
99 | #define LPC_MAC1_LOOPBACK (1 << 4) | |
100 | #define LPC_MAC1_RESET_TX (1 << 8) | |
101 | #define LPC_MAC1_RESET_MCS_TX (1 << 9) | |
102 | #define LPC_MAC1_RESET_RX (1 << 10) | |
103 | #define LPC_MAC1_RESET_MCS_RX (1 << 11) | |
104 | #define LPC_MAC1_SIMULATION_RESET (1 << 14) | |
105 | #define LPC_MAC1_SOFT_RESET (1 << 15) | |
106 | ||
107 | /* | |
108 | * mac2 register definitions | |
109 | */ | |
110 | #define LPC_MAC2_FULL_DUPLEX (1 << 0) | |
111 | #define LPC_MAC2_FRAME_LENGTH_CHECKING (1 << 1) | |
112 | #define LPC_MAC2_HUGH_LENGTH_CHECKING (1 << 2) | |
113 | #define LPC_MAC2_DELAYED_CRC (1 << 3) | |
114 | #define LPC_MAC2_CRC_ENABLE (1 << 4) | |
115 | #define LPC_MAC2_PAD_CRC_ENABLE (1 << 5) | |
116 | #define LPC_MAC2_VLAN_PAD_ENABLE (1 << 6) | |
117 | #define LPC_MAC2_AUTO_DETECT_PAD_ENABLE (1 << 7) | |
118 | #define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT (1 << 8) | |
119 | #define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT (1 << 9) | |
120 | #define LPC_MAC2_NO_BACKOFF (1 << 12) | |
121 | #define LPC_MAC2_BACK_PRESSURE (1 << 13) | |
122 | #define LPC_MAC2_EXCESS_DEFER (1 << 14) | |
123 | ||
124 | /* | |
125 | * ipgt register definitions | |
126 | */ | |
127 | #define LPC_IPGT_LOAD(n) ((n) & 0x7F) | |
128 | ||
129 | /* | |
130 | * ipgr register definitions | |
131 | */ | |
132 | #define LPC_IPGR_LOAD_PART2(n) ((n) & 0x7F) | |
133 | #define LPC_IPGR_LOAD_PART1(n) (((n) & 0x7F) << 8) | |
134 | ||
135 | /* | |
136 | * clrt register definitions | |
137 | */ | |
138 | #define LPC_CLRT_LOAD_RETRY_MAX(n) ((n) & 0xF) | |
139 | #define LPC_CLRT_LOAD_COLLISION_WINDOW(n) (((n) & 0x3F) << 8) | |
140 | ||
141 | /* | |
142 | * maxf register definitions | |
143 | */ | |
144 | #define LPC_MAXF_LOAD_MAX_FRAME_LEN(n) ((n) & 0xFFFF) | |
145 | ||
146 | /* | |
147 | * supp register definitions | |
148 | */ | |
149 | #define LPC_SUPP_SPEED (1 << 8) | |
150 | #define LPC_SUPP_RESET_RMII (1 << 11) | |
151 | ||
152 | /* | |
153 | * test register definitions | |
154 | */ | |
155 | #define LPC_TEST_SHORTCUT_PAUSE_QUANTA (1 << 0) | |
156 | #define LPC_TEST_PAUSE (1 << 1) | |
157 | #define LPC_TEST_BACKPRESSURE (1 << 2) | |
158 | ||
159 | /* | |
160 | * mcfg register definitions | |
161 | */ | |
162 | #define LPC_MCFG_SCAN_INCREMENT (1 << 0) | |
163 | #define LPC_MCFG_SUPPRESS_PREAMBLE (1 << 1) | |
164 | #define LPC_MCFG_CLOCK_SELECT(n) (((n) & 0x7) << 2) | |
165 | #define LPC_MCFG_CLOCK_HOST_DIV_4 0 | |
166 | #define LPC_MCFG_CLOCK_HOST_DIV_6 2 | |
167 | #define LPC_MCFG_CLOCK_HOST_DIV_8 3 | |
168 | #define LPC_MCFG_CLOCK_HOST_DIV_10 4 | |
169 | #define LPC_MCFG_CLOCK_HOST_DIV_14 5 | |
170 | #define LPC_MCFG_CLOCK_HOST_DIV_20 6 | |
171 | #define LPC_MCFG_CLOCK_HOST_DIV_28 7 | |
172 | #define LPC_MCFG_RESET_MII_MGMT (1 << 15) | |
173 | ||
174 | /* | |
175 | * mcmd register definitions | |
176 | */ | |
177 | #define LPC_MCMD_READ (1 << 0) | |
178 | #define LPC_MCMD_SCAN (1 << 1) | |
179 | ||
180 | /* | |
181 | * madr register definitions | |
182 | */ | |
183 | #define LPC_MADR_REGISTER_ADDRESS(n) ((n) & 0x1F) | |
184 | #define LPC_MADR_PHY_0ADDRESS(n) (((n) & 0x1F) << 8) | |
185 | ||
186 | /* | |
187 | * mwtd register definitions | |
188 | */ | |
189 | #define LPC_MWDT_WRITE(n) ((n) & 0xFFFF) | |
190 | ||
191 | /* | |
192 | * mrdd register definitions | |
193 | */ | |
194 | #define LPC_MRDD_READ_MASK 0xFFFF | |
195 | ||
196 | /* | |
197 | * mind register definitions | |
198 | */ | |
199 | #define LPC_MIND_BUSY (1 << 0) | |
200 | #define LPC_MIND_SCANNING (1 << 1) | |
201 | #define LPC_MIND_NOT_VALID (1 << 2) | |
202 | #define LPC_MIND_MII_LINK_FAIL (1 << 3) | |
203 | ||
204 | /* | |
205 | * command register definitions | |
206 | */ | |
207 | #define LPC_COMMAND_RXENABLE (1 << 0) | |
208 | #define LPC_COMMAND_TXENABLE (1 << 1) | |
209 | #define LPC_COMMAND_REG_RESET (1 << 3) | |
210 | #define LPC_COMMAND_TXRESET (1 << 4) | |
211 | #define LPC_COMMAND_RXRESET (1 << 5) | |
212 | #define LPC_COMMAND_PASSRUNTFRAME (1 << 6) | |
213 | #define LPC_COMMAND_PASSRXFILTER (1 << 7) | |
214 | #define LPC_COMMAND_TXFLOWCONTROL (1 << 8) | |
215 | #define LPC_COMMAND_RMII (1 << 9) | |
216 | #define LPC_COMMAND_FULLDUPLEX (1 << 10) | |
217 | ||
218 | /* | |
219 | * status register definitions | |
220 | */ | |
221 | #define LPC_STATUS_RXACTIVE (1 << 0) | |
222 | #define LPC_STATUS_TXACTIVE (1 << 1) | |
223 | ||
224 | /* | |
225 | * tsv0 register definitions | |
226 | */ | |
227 | #define LPC_TSV0_CRC_ERROR (1 << 0) | |
228 | #define LPC_TSV0_LENGTH_CHECK_ERROR (1 << 1) | |
229 | #define LPC_TSV0_LENGTH_OUT_OF_RANGE (1 << 2) | |
230 | #define LPC_TSV0_DONE (1 << 3) | |
231 | #define LPC_TSV0_MULTICAST (1 << 4) | |
232 | #define LPC_TSV0_BROADCAST (1 << 5) | |
233 | #define LPC_TSV0_PACKET_DEFER (1 << 6) | |
234 | #define LPC_TSV0_ESCESSIVE_DEFER (1 << 7) | |
235 | #define LPC_TSV0_ESCESSIVE_COLLISION (1 << 8) | |
236 | #define LPC_TSV0_LATE_COLLISION (1 << 9) | |
237 | #define LPC_TSV0_GIANT (1 << 10) | |
238 | #define LPC_TSV0_UNDERRUN (1 << 11) | |
239 | #define LPC_TSV0_TOTAL_BYTES(n) (((n) >> 12) & 0xFFFF) | |
240 | #define LPC_TSV0_CONTROL_FRAME (1 << 28) | |
241 | #define LPC_TSV0_PAUSE (1 << 29) | |
242 | #define LPC_TSV0_BACKPRESSURE (1 << 30) | |
243 | #define LPC_TSV0_VLAN (1 << 31) | |
244 | ||
245 | /* | |
246 | * tsv1 register definitions | |
247 | */ | |
248 | #define LPC_TSV1_TRANSMIT_BYTE_COUNT(n) ((n) & 0xFFFF) | |
249 | #define LPC_TSV1_COLLISION_COUNT(n) (((n) >> 16) & 0xF) | |
250 | ||
251 | /* | |
252 | * rsv register definitions | |
253 | */ | |
254 | #define LPC_RSV_RECEIVED_BYTE_COUNT(n) ((n) & 0xFFFF) | |
255 | #define LPC_RSV_RXDV_EVENT_IGNORED (1 << 16) | |
256 | #define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN (1 << 17) | |
257 | #define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN (1 << 18) | |
258 | #define LPC_RSV_RECEIVE_CODE_VIOLATION (1 << 19) | |
259 | #define LPC_RSV_CRC_ERROR (1 << 20) | |
260 | #define LPC_RSV_LENGTH_CHECK_ERROR (1 << 21) | |
261 | #define LPC_RSV_LENGTH_OUT_OF_RANGE (1 << 22) | |
262 | #define LPC_RSV_RECEIVE_OK (1 << 23) | |
263 | #define LPC_RSV_MULTICAST (1 << 24) | |
264 | #define LPC_RSV_BROADCAST (1 << 25) | |
265 | #define LPC_RSV_DRIBBLE_NIBBLE (1 << 26) | |
266 | #define LPC_RSV_CONTROL_FRAME (1 << 27) | |
267 | #define LPC_RSV_PAUSE (1 << 28) | |
268 | #define LPC_RSV_UNSUPPORTED_OPCODE (1 << 29) | |
269 | #define LPC_RSV_VLAN (1 << 30) | |
270 | ||
271 | /* | |
272 | * flowcontrolcounter register definitions | |
273 | */ | |
274 | #define LPC_FCCR_MIRRORCOUNTER(n) ((n) & 0xFFFF) | |
275 | #define LPC_FCCR_PAUSETIMER(n) (((n) >> 16) & 0xFFFF) | |
276 | ||
277 | /* | |
278 | * flowcontrolstatus register definitions | |
279 | */ | |
280 | #define LPC_FCCR_MIRRORCOUNTERCURRENT(n) ((n) & 0xFFFF) | |
281 | ||
282 | /* | |
d59da3fb | 283 | * rxfilterctrl, rxfilterwolstatus, and rxfilterwolclear shared |
b7370112 | 284 | * register definitions |
285 | */ | |
286 | #define LPC_RXFLTRW_ACCEPTUNICAST (1 << 0) | |
287 | #define LPC_RXFLTRW_ACCEPTUBROADCAST (1 << 1) | |
288 | #define LPC_RXFLTRW_ACCEPTUMULTICAST (1 << 2) | |
289 | #define LPC_RXFLTRW_ACCEPTUNICASTHASH (1 << 3) | |
290 | #define LPC_RXFLTRW_ACCEPTUMULTICASTHASH (1 << 4) | |
291 | #define LPC_RXFLTRW_ACCEPTPERFECT (1 << 5) | |
292 | ||
293 | /* | |
d59da3fb | 294 | * rxfilterctrl register definitions |
b7370112 | 295 | */ |
296 | #define LPC_RXFLTRWSTS_MAGICPACKETENWOL (1 << 12) | |
297 | #define LPC_RXFLTRWSTS_RXFILTERENWOL (1 << 13) | |
298 | ||
299 | /* | |
300 | * rxfilterwolstatus/rxfilterwolclear register definitions | |
301 | */ | |
302 | #define LPC_RXFLTRWSTS_RXFILTERWOL (1 << 7) | |
303 | #define LPC_RXFLTRWSTS_MAGICPACKETWOL (1 << 8) | |
304 | ||
305 | /* | |
306 | * intstatus, intenable, intclear, and Intset shared register | |
307 | * definitions | |
308 | */ | |
309 | #define LPC_MACINT_RXOVERRUNINTEN (1 << 0) | |
310 | #define LPC_MACINT_RXERRORONINT (1 << 1) | |
311 | #define LPC_MACINT_RXFINISHEDINTEN (1 << 2) | |
312 | #define LPC_MACINT_RXDONEINTEN (1 << 3) | |
313 | #define LPC_MACINT_TXUNDERRUNINTEN (1 << 4) | |
314 | #define LPC_MACINT_TXERRORINTEN (1 << 5) | |
315 | #define LPC_MACINT_TXFINISHEDINTEN (1 << 6) | |
316 | #define LPC_MACINT_TXDONEINTEN (1 << 7) | |
317 | #define LPC_MACINT_SOFTINTEN (1 << 12) | |
318 | #define LPC_MACINT_WAKEUPINTEN (1 << 13) | |
319 | ||
320 | /* | |
321 | * powerdown register definitions | |
322 | */ | |
323 | #define LPC_POWERDOWN_MACAHB (1 << 31) | |
324 | ||
4de02e4a | 325 | static phy_interface_t lpc_phy_interface_mode(struct device *dev) |
b7370112 | 326 | { |
4de02e4a RS |
327 | if (dev && dev->of_node) { |
328 | const char *mode = of_get_property(dev->of_node, | |
329 | "phy-mode", NULL); | |
330 | if (mode && !strcmp(mode, "mii")) | |
331 | return PHY_INTERFACE_MODE_MII; | |
4de02e4a | 332 | } |
b7370112 | 333 | return PHY_INTERFACE_MODE_RMII; |
b7370112 | 334 | } |
335 | ||
4de02e4a | 336 | static bool use_iram_for_net(struct device *dev) |
b7370112 | 337 | { |
4de02e4a RS |
338 | if (dev && dev->of_node) |
339 | return of_property_read_bool(dev->of_node, "use-iram"); | |
4de02e4a | 340 | return false; |
b7370112 | 341 | } |
342 | ||
343 | /* Receive Status information word */ | |
344 | #define RXSTATUS_SIZE 0x000007FF | |
345 | #define RXSTATUS_CONTROL (1 << 18) | |
346 | #define RXSTATUS_VLAN (1 << 19) | |
347 | #define RXSTATUS_FILTER (1 << 20) | |
348 | #define RXSTATUS_MULTICAST (1 << 21) | |
349 | #define RXSTATUS_BROADCAST (1 << 22) | |
350 | #define RXSTATUS_CRC (1 << 23) | |
351 | #define RXSTATUS_SYMBOL (1 << 24) | |
352 | #define RXSTATUS_LENGTH (1 << 25) | |
353 | #define RXSTATUS_RANGE (1 << 26) | |
354 | #define RXSTATUS_ALIGN (1 << 27) | |
355 | #define RXSTATUS_OVERRUN (1 << 28) | |
356 | #define RXSTATUS_NODESC (1 << 29) | |
357 | #define RXSTATUS_LAST (1 << 30) | |
358 | #define RXSTATUS_ERROR (1 << 31) | |
359 | ||
360 | #define RXSTATUS_STATUS_ERROR \ | |
361 | (RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | \ | |
362 | RXSTATUS_RANGE | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC) | |
363 | ||
364 | /* Receive Descriptor control word */ | |
365 | #define RXDESC_CONTROL_SIZE 0x000007FF | |
366 | #define RXDESC_CONTROL_INT (1 << 31) | |
367 | ||
368 | /* Transmit Status information word */ | |
369 | #define TXSTATUS_COLLISIONS_GET(x) (((x) >> 21) & 0xF) | |
370 | #define TXSTATUS_DEFER (1 << 25) | |
371 | #define TXSTATUS_EXCESSDEFER (1 << 26) | |
372 | #define TXSTATUS_EXCESSCOLL (1 << 27) | |
373 | #define TXSTATUS_LATECOLL (1 << 28) | |
374 | #define TXSTATUS_UNDERRUN (1 << 29) | |
375 | #define TXSTATUS_NODESC (1 << 30) | |
376 | #define TXSTATUS_ERROR (1 << 31) | |
377 | ||
378 | /* Transmit Descriptor control word */ | |
379 | #define TXDESC_CONTROL_SIZE 0x000007FF | |
380 | #define TXDESC_CONTROL_OVERRIDE (1 << 26) | |
381 | #define TXDESC_CONTROL_HUGE (1 << 27) | |
382 | #define TXDESC_CONTROL_PAD (1 << 28) | |
383 | #define TXDESC_CONTROL_CRC (1 << 29) | |
384 | #define TXDESC_CONTROL_LAST (1 << 30) | |
385 | #define TXDESC_CONTROL_INT (1 << 31) | |
386 | ||
b7370112 | 387 | /* |
388 | * Structure of a TX/RX descriptors and RX status | |
389 | */ | |
390 | struct txrx_desc_t { | |
391 | __le32 packet; | |
392 | __le32 control; | |
393 | }; | |
394 | struct rx_status_t { | |
395 | __le32 statusinfo; | |
396 | __le32 statushashcrc; | |
397 | }; | |
398 | ||
399 | /* | |
400 | * Device driver data structure | |
401 | */ | |
402 | struct netdata_local { | |
403 | struct platform_device *pdev; | |
404 | struct net_device *ndev; | |
405 | spinlock_t lock; | |
406 | void __iomem *net_base; | |
407 | u32 msg_enable; | |
a7e2eaad | 408 | unsigned int skblen[ENET_TX_DESC]; |
b7370112 | 409 | unsigned int last_tx_idx; |
410 | unsigned int num_used_tx_buffs; | |
411 | struct mii_bus *mii_bus; | |
b7370112 | 412 | struct clk *clk; |
413 | dma_addr_t dma_buff_base_p; | |
414 | void *dma_buff_base_v; | |
415 | size_t dma_buff_size; | |
416 | struct txrx_desc_t *tx_desc_v; | |
417 | u32 *tx_stat_v; | |
418 | void *tx_buff_v; | |
419 | struct txrx_desc_t *rx_desc_v; | |
420 | struct rx_status_t *rx_stat_v; | |
421 | void *rx_buff_v; | |
422 | int link; | |
423 | int speed; | |
424 | int duplex; | |
425 | struct napi_struct napi; | |
426 | }; | |
427 | ||
428 | /* | |
429 | * MAC support functions | |
430 | */ | |
431 | static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac) | |
432 | { | |
433 | u32 tmp; | |
434 | ||
435 | /* Set station address */ | |
436 | tmp = mac[0] | ((u32)mac[1] << 8); | |
437 | writel(tmp, LPC_ENET_SA2(pldat->net_base)); | |
438 | tmp = mac[2] | ((u32)mac[3] << 8); | |
439 | writel(tmp, LPC_ENET_SA1(pldat->net_base)); | |
440 | tmp = mac[4] | ((u32)mac[5] << 8); | |
441 | writel(tmp, LPC_ENET_SA0(pldat->net_base)); | |
442 | ||
443 | netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac); | |
444 | } | |
445 | ||
446 | static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac) | |
447 | { | |
448 | u32 tmp; | |
449 | ||
450 | /* Get station address */ | |
451 | tmp = readl(LPC_ENET_SA2(pldat->net_base)); | |
452 | mac[0] = tmp & 0xFF; | |
453 | mac[1] = tmp >> 8; | |
454 | tmp = readl(LPC_ENET_SA1(pldat->net_base)); | |
455 | mac[2] = tmp & 0xFF; | |
456 | mac[3] = tmp >> 8; | |
457 | tmp = readl(LPC_ENET_SA0(pldat->net_base)); | |
458 | mac[4] = tmp & 0xFF; | |
459 | mac[5] = tmp >> 8; | |
460 | } | |
461 | ||
b7370112 | 462 | static void __lpc_params_setup(struct netdata_local *pldat) |
463 | { | |
464 | u32 tmp; | |
465 | ||
466 | if (pldat->duplex == DUPLEX_FULL) { | |
467 | tmp = readl(LPC_ENET_MAC2(pldat->net_base)); | |
468 | tmp |= LPC_MAC2_FULL_DUPLEX; | |
469 | writel(tmp, LPC_ENET_MAC2(pldat->net_base)); | |
470 | tmp = readl(LPC_ENET_COMMAND(pldat->net_base)); | |
471 | tmp |= LPC_COMMAND_FULLDUPLEX; | |
472 | writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); | |
473 | writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base)); | |
474 | } else { | |
475 | tmp = readl(LPC_ENET_MAC2(pldat->net_base)); | |
476 | tmp &= ~LPC_MAC2_FULL_DUPLEX; | |
477 | writel(tmp, LPC_ENET_MAC2(pldat->net_base)); | |
478 | tmp = readl(LPC_ENET_COMMAND(pldat->net_base)); | |
479 | tmp &= ~LPC_COMMAND_FULLDUPLEX; | |
480 | writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); | |
481 | writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base)); | |
482 | } | |
483 | ||
484 | if (pldat->speed == SPEED_100) | |
485 | writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base)); | |
486 | else | |
487 | writel(0, LPC_ENET_SUPP(pldat->net_base)); | |
488 | } | |
489 | ||
490 | static void __lpc_eth_reset(struct netdata_local *pldat) | |
491 | { | |
492 | /* Reset all MAC logic */ | |
493 | writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX | | |
494 | LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET | | |
495 | LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base)); | |
496 | writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET | | |
497 | LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base)); | |
498 | } | |
499 | ||
500 | static int __lpc_mii_mngt_reset(struct netdata_local *pldat) | |
501 | { | |
502 | /* Reset MII management hardware */ | |
503 | writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base)); | |
504 | ||
505 | /* Setup MII clock to slowest rate with a /28 divider */ | |
506 | writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28), | |
507 | LPC_ENET_MCFG(pldat->net_base)); | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat) | |
513 | { | |
514 | phys_addr_t phaddr; | |
515 | ||
516 | phaddr = addr - pldat->dma_buff_base_v; | |
517 | phaddr += pldat->dma_buff_base_p; | |
518 | ||
519 | return phaddr; | |
520 | } | |
521 | ||
522 | static void lpc_eth_enable_int(void __iomem *regbase) | |
523 | { | |
524 | writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN), | |
525 | LPC_ENET_INTENABLE(regbase)); | |
526 | } | |
527 | ||
528 | static void lpc_eth_disable_int(void __iomem *regbase) | |
529 | { | |
530 | writel(0, LPC_ENET_INTENABLE(regbase)); | |
531 | } | |
532 | ||
533 | /* Setup TX/RX descriptors */ | |
534 | static void __lpc_txrx_desc_setup(struct netdata_local *pldat) | |
535 | { | |
536 | u32 *ptxstat; | |
537 | void *tbuff; | |
538 | int i; | |
539 | struct txrx_desc_t *ptxrxdesc; | |
540 | struct rx_status_t *prxstat; | |
541 | ||
542 | tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16); | |
543 | ||
544 | /* Setup TX descriptors, status, and buffers */ | |
545 | pldat->tx_desc_v = tbuff; | |
546 | tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC; | |
547 | ||
548 | pldat->tx_stat_v = tbuff; | |
549 | tbuff += sizeof(u32) * ENET_TX_DESC; | |
550 | ||
551 | tbuff = PTR_ALIGN(tbuff, 16); | |
552 | pldat->tx_buff_v = tbuff; | |
553 | tbuff += ENET_MAXF_SIZE * ENET_TX_DESC; | |
554 | ||
555 | /* Setup RX descriptors, status, and buffers */ | |
556 | pldat->rx_desc_v = tbuff; | |
557 | tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC; | |
558 | ||
559 | tbuff = PTR_ALIGN(tbuff, 16); | |
560 | pldat->rx_stat_v = tbuff; | |
561 | tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC; | |
562 | ||
563 | tbuff = PTR_ALIGN(tbuff, 16); | |
564 | pldat->rx_buff_v = tbuff; | |
565 | tbuff += ENET_MAXF_SIZE * ENET_RX_DESC; | |
566 | ||
567 | /* Map the TX descriptors to the TX buffers in hardware */ | |
568 | for (i = 0; i < ENET_TX_DESC; i++) { | |
569 | ptxstat = &pldat->tx_stat_v[i]; | |
570 | ptxrxdesc = &pldat->tx_desc_v[i]; | |
571 | ||
572 | ptxrxdesc->packet = __va_to_pa( | |
573 | pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat); | |
574 | ptxrxdesc->control = 0; | |
575 | *ptxstat = 0; | |
576 | } | |
577 | ||
578 | /* Map the RX descriptors to the RX buffers in hardware */ | |
579 | for (i = 0; i < ENET_RX_DESC; i++) { | |
580 | prxstat = &pldat->rx_stat_v[i]; | |
581 | ptxrxdesc = &pldat->rx_desc_v[i]; | |
582 | ||
583 | ptxrxdesc->packet = __va_to_pa( | |
584 | pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat); | |
585 | ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1); | |
586 | prxstat->statusinfo = 0; | |
587 | prxstat->statushashcrc = 0; | |
588 | } | |
589 | ||
590 | /* Setup base addresses in hardware to point to buffers and | |
591 | * descriptors | |
592 | */ | |
593 | writel((ENET_TX_DESC - 1), | |
594 | LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base)); | |
595 | writel(__va_to_pa(pldat->tx_desc_v, pldat), | |
596 | LPC_ENET_TXDESCRIPTOR(pldat->net_base)); | |
597 | writel(__va_to_pa(pldat->tx_stat_v, pldat), | |
598 | LPC_ENET_TXSTATUS(pldat->net_base)); | |
599 | writel((ENET_RX_DESC - 1), | |
600 | LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base)); | |
601 | writel(__va_to_pa(pldat->rx_desc_v, pldat), | |
602 | LPC_ENET_RXDESCRIPTOR(pldat->net_base)); | |
603 | writel(__va_to_pa(pldat->rx_stat_v, pldat), | |
604 | LPC_ENET_RXSTATUS(pldat->net_base)); | |
605 | } | |
606 | ||
607 | static void __lpc_eth_init(struct netdata_local *pldat) | |
608 | { | |
609 | u32 tmp; | |
610 | ||
611 | /* Disable controller and reset */ | |
612 | tmp = readl(LPC_ENET_COMMAND(pldat->net_base)); | |
613 | tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE; | |
614 | writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); | |
615 | tmp = readl(LPC_ENET_MAC1(pldat->net_base)); | |
616 | tmp &= ~LPC_MAC1_RECV_ENABLE; | |
617 | writel(tmp, LPC_ENET_MAC1(pldat->net_base)); | |
618 | ||
619 | /* Initial MAC setup */ | |
620 | writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base)); | |
621 | writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE), | |
622 | LPC_ENET_MAC2(pldat->net_base)); | |
623 | writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base)); | |
624 | ||
625 | /* Collision window, gap */ | |
626 | writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) | | |
627 | LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)), | |
628 | LPC_ENET_CLRT(pldat->net_base)); | |
629 | writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base)); | |
630 | ||
4de02e4a | 631 | if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) |
b7370112 | 632 | writel(LPC_COMMAND_PASSRUNTFRAME, |
633 | LPC_ENET_COMMAND(pldat->net_base)); | |
634 | else { | |
635 | writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII), | |
636 | LPC_ENET_COMMAND(pldat->net_base)); | |
637 | writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base)); | |
638 | } | |
639 | ||
640 | __lpc_params_setup(pldat); | |
641 | ||
642 | /* Setup TX and RX descriptors */ | |
643 | __lpc_txrx_desc_setup(pldat); | |
644 | ||
645 | /* Setup packet filtering */ | |
646 | writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT), | |
647 | LPC_ENET_RXFILTER_CTRL(pldat->net_base)); | |
648 | ||
649 | /* Get the next TX buffer output index */ | |
650 | pldat->num_used_tx_buffs = 0; | |
651 | pldat->last_tx_idx = | |
652 | readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base)); | |
653 | ||
654 | /* Clear and enable interrupts */ | |
655 | writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base)); | |
656 | smp_wmb(); | |
657 | lpc_eth_enable_int(pldat->net_base); | |
658 | ||
659 | /* Enable controller */ | |
660 | tmp = readl(LPC_ENET_COMMAND(pldat->net_base)); | |
661 | tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE; | |
662 | writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); | |
663 | tmp = readl(LPC_ENET_MAC1(pldat->net_base)); | |
664 | tmp |= LPC_MAC1_RECV_ENABLE; | |
665 | writel(tmp, LPC_ENET_MAC1(pldat->net_base)); | |
666 | } | |
667 | ||
668 | static void __lpc_eth_shutdown(struct netdata_local *pldat) | |
669 | { | |
670 | /* Reset ethernet and power down PHY */ | |
671 | __lpc_eth_reset(pldat); | |
672 | writel(0, LPC_ENET_MAC1(pldat->net_base)); | |
673 | writel(0, LPC_ENET_MAC2(pldat->net_base)); | |
674 | } | |
675 | ||
676 | /* | |
677 | * MAC<--->PHY support functions | |
678 | */ | |
679 | static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg) | |
680 | { | |
681 | struct netdata_local *pldat = bus->priv; | |
682 | unsigned long timeout = jiffies + msecs_to_jiffies(100); | |
683 | int lps; | |
684 | ||
685 | writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base)); | |
686 | writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base)); | |
687 | ||
688 | /* Wait for unbusy status */ | |
689 | while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) { | |
690 | if (time_after(jiffies, timeout)) | |
691 | return -EIO; | |
692 | cpu_relax(); | |
693 | } | |
694 | ||
695 | lps = readl(LPC_ENET_MRDD(pldat->net_base)); | |
696 | writel(0, LPC_ENET_MCMD(pldat->net_base)); | |
697 | ||
698 | return lps; | |
699 | } | |
700 | ||
701 | static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg, | |
702 | u16 phydata) | |
703 | { | |
704 | struct netdata_local *pldat = bus->priv; | |
705 | unsigned long timeout = jiffies + msecs_to_jiffies(100); | |
706 | ||
707 | writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base)); | |
708 | writel(phydata, LPC_ENET_MWTD(pldat->net_base)); | |
709 | ||
710 | /* Wait for completion */ | |
711 | while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) { | |
712 | if (time_after(jiffies, timeout)) | |
713 | return -EIO; | |
714 | cpu_relax(); | |
715 | } | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | static int lpc_mdio_reset(struct mii_bus *bus) | |
721 | { | |
722 | return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv); | |
723 | } | |
724 | ||
725 | static void lpc_handle_link_change(struct net_device *ndev) | |
726 | { | |
727 | struct netdata_local *pldat = netdev_priv(ndev); | |
f786f356 | 728 | struct phy_device *phydev = ndev->phydev; |
b7370112 | 729 | unsigned long flags; |
730 | ||
731 | bool status_change = false; | |
732 | ||
733 | spin_lock_irqsave(&pldat->lock, flags); | |
734 | ||
735 | if (phydev->link) { | |
736 | if ((pldat->speed != phydev->speed) || | |
737 | (pldat->duplex != phydev->duplex)) { | |
738 | pldat->speed = phydev->speed; | |
739 | pldat->duplex = phydev->duplex; | |
740 | status_change = true; | |
741 | } | |
742 | } | |
743 | ||
744 | if (phydev->link != pldat->link) { | |
745 | if (!phydev->link) { | |
746 | pldat->speed = 0; | |
747 | pldat->duplex = -1; | |
748 | } | |
749 | pldat->link = phydev->link; | |
750 | ||
751 | status_change = true; | |
752 | } | |
753 | ||
754 | spin_unlock_irqrestore(&pldat->lock, flags); | |
755 | ||
756 | if (status_change) | |
757 | __lpc_params_setup(pldat); | |
758 | } | |
759 | ||
760 | static int lpc_mii_probe(struct net_device *ndev) | |
761 | { | |
762 | struct netdata_local *pldat = netdev_priv(ndev); | |
763 | struct phy_device *phydev = phy_find_first(pldat->mii_bus); | |
764 | ||
765 | if (!phydev) { | |
766 | netdev_err(ndev, "no PHY found\n"); | |
767 | return -ENODEV; | |
768 | } | |
769 | ||
770 | /* Attach to the PHY */ | |
4de02e4a | 771 | if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) |
b7370112 | 772 | netdev_info(ndev, "using MII interface\n"); |
773 | else | |
774 | netdev_info(ndev, "using RMII interface\n"); | |
84eff6d1 | 775 | phydev = phy_connect(ndev, phydev_name(phydev), |
f9a8f83b | 776 | &lpc_handle_link_change, |
4de02e4a | 777 | lpc_phy_interface_mode(&pldat->pdev->dev)); |
b7370112 | 778 | |
779 | if (IS_ERR(phydev)) { | |
780 | netdev_err(ndev, "Could not attach to PHY\n"); | |
781 | return PTR_ERR(phydev); | |
782 | } | |
783 | ||
58056c1e | 784 | phy_set_max_speed(phydev, SPEED_100); |
b7370112 | 785 | |
b7370112 | 786 | pldat->link = 0; |
787 | pldat->speed = 0; | |
788 | pldat->duplex = -1; | |
b7370112 | 789 | |
2220943a AL |
790 | phy_attached_info(phydev); |
791 | ||
b7370112 | 792 | return 0; |
793 | } | |
794 | ||
795 | static int lpc_mii_init(struct netdata_local *pldat) | |
796 | { | |
541b8e29 | 797 | int err = -ENXIO; |
b7370112 | 798 | |
799 | pldat->mii_bus = mdiobus_alloc(); | |
800 | if (!pldat->mii_bus) { | |
801 | err = -ENOMEM; | |
802 | goto err_out; | |
803 | } | |
804 | ||
805 | /* Setup MII mode */ | |
4de02e4a | 806 | if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) |
b7370112 | 807 | writel(LPC_COMMAND_PASSRUNTFRAME, |
808 | LPC_ENET_COMMAND(pldat->net_base)); | |
809 | else { | |
810 | writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII), | |
811 | LPC_ENET_COMMAND(pldat->net_base)); | |
812 | writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base)); | |
813 | } | |
814 | ||
815 | pldat->mii_bus->name = "lpc_mii_bus"; | |
816 | pldat->mii_bus->read = &lpc_mdio_read; | |
817 | pldat->mii_bus->write = &lpc_mdio_write; | |
818 | pldat->mii_bus->reset = &lpc_mdio_reset; | |
819 | snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", | |
820 | pldat->pdev->name, pldat->pdev->id); | |
821 | pldat->mii_bus->priv = pldat; | |
822 | pldat->mii_bus->parent = &pldat->pdev->dev; | |
823 | ||
b7370112 | 824 | platform_set_drvdata(pldat->pdev, pldat->mii_bus); |
825 | ||
826 | if (mdiobus_register(pldat->mii_bus)) | |
e7f4dc35 | 827 | goto err_out_unregister_bus; |
b7370112 | 828 | |
829 | if (lpc_mii_probe(pldat->ndev) != 0) | |
830 | goto err_out_unregister_bus; | |
831 | ||
832 | return 0; | |
833 | ||
834 | err_out_unregister_bus: | |
835 | mdiobus_unregister(pldat->mii_bus); | |
b7370112 | 836 | mdiobus_free(pldat->mii_bus); |
837 | err_out: | |
838 | return err; | |
839 | } | |
840 | ||
841 | static void __lpc_handle_xmit(struct net_device *ndev) | |
842 | { | |
843 | struct netdata_local *pldat = netdev_priv(ndev); | |
b7370112 | 844 | u32 txcidx, *ptxstat, txstat; |
845 | ||
846 | txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base)); | |
847 | while (pldat->last_tx_idx != txcidx) { | |
a7e2eaad | 848 | unsigned int skblen = pldat->skblen[pldat->last_tx_idx]; |
b7370112 | 849 | |
850 | /* A buffer is available, get buffer status */ | |
851 | ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx]; | |
852 | txstat = *ptxstat; | |
853 | ||
854 | /* Next buffer and decrement used buffer counter */ | |
855 | pldat->num_used_tx_buffs--; | |
856 | pldat->last_tx_idx++; | |
857 | if (pldat->last_tx_idx >= ENET_TX_DESC) | |
858 | pldat->last_tx_idx = 0; | |
859 | ||
860 | /* Update collision counter */ | |
861 | ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat); | |
862 | ||
863 | /* Any errors occurred? */ | |
864 | if (txstat & TXSTATUS_ERROR) { | |
865 | if (txstat & TXSTATUS_UNDERRUN) { | |
866 | /* FIFO underrun */ | |
867 | ndev->stats.tx_fifo_errors++; | |
868 | } | |
869 | if (txstat & TXSTATUS_LATECOLL) { | |
870 | /* Late collision */ | |
871 | ndev->stats.tx_aborted_errors++; | |
872 | } | |
873 | if (txstat & TXSTATUS_EXCESSCOLL) { | |
874 | /* Excessive collision */ | |
875 | ndev->stats.tx_aborted_errors++; | |
876 | } | |
877 | if (txstat & TXSTATUS_EXCESSDEFER) { | |
878 | /* Defer limit */ | |
879 | ndev->stats.tx_aborted_errors++; | |
880 | } | |
881 | ndev->stats.tx_errors++; | |
882 | } else { | |
883 | /* Update stats */ | |
884 | ndev->stats.tx_packets++; | |
a7e2eaad | 885 | ndev->stats.tx_bytes += skblen; |
b7370112 | 886 | } |
887 | ||
888 | txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base)); | |
889 | } | |
890 | ||
3f16da51 ED |
891 | if (pldat->num_used_tx_buffs <= ENET_TX_DESC/2) { |
892 | if (netif_queue_stopped(ndev)) | |
893 | netif_wake_queue(ndev); | |
894 | } | |
b7370112 | 895 | } |
896 | ||
897 | static int __lpc_handle_recv(struct net_device *ndev, int budget) | |
898 | { | |
899 | struct netdata_local *pldat = netdev_priv(ndev); | |
900 | struct sk_buff *skb; | |
901 | u32 rxconsidx, len, ethst; | |
902 | struct rx_status_t *prxstat; | |
b7370112 | 903 | int rx_done = 0; |
904 | ||
905 | /* Get the current RX buffer indexes */ | |
906 | rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base)); | |
907 | while (rx_done < budget && rxconsidx != | |
908 | readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) { | |
909 | /* Get pointer to receive status */ | |
910 | prxstat = &pldat->rx_stat_v[rxconsidx]; | |
911 | len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1; | |
912 | ||
913 | /* Status error? */ | |
914 | ethst = prxstat->statusinfo; | |
915 | if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) == | |
916 | (RXSTATUS_ERROR | RXSTATUS_RANGE)) | |
917 | ethst &= ~RXSTATUS_ERROR; | |
918 | ||
919 | if (ethst & RXSTATUS_ERROR) { | |
920 | int si = prxstat->statusinfo; | |
921 | /* Check statuses */ | |
922 | if (si & RXSTATUS_OVERRUN) { | |
923 | /* Overrun error */ | |
924 | ndev->stats.rx_fifo_errors++; | |
925 | } else if (si & RXSTATUS_CRC) { | |
926 | /* CRC error */ | |
927 | ndev->stats.rx_crc_errors++; | |
928 | } else if (si & RXSTATUS_LENGTH) { | |
929 | /* Length error */ | |
930 | ndev->stats.rx_length_errors++; | |
931 | } else if (si & RXSTATUS_ERROR) { | |
932 | /* Other error */ | |
933 | ndev->stats.rx_length_errors++; | |
934 | } | |
935 | ndev->stats.rx_errors++; | |
936 | } else { | |
937 | /* Packet is good */ | |
e7f8c1fe ED |
938 | skb = dev_alloc_skb(len); |
939 | if (!skb) { | |
b7370112 | 940 | ndev->stats.rx_dropped++; |
e7f8c1fe | 941 | } else { |
b7370112 | 942 | /* Copy packet from buffer */ |
b952f4df | 943 | skb_put_data(skb, |
944 | pldat->rx_buff_v + rxconsidx * ENET_MAXF_SIZE, | |
945 | len); | |
b7370112 | 946 | |
947 | /* Pass to upper layer */ | |
948 | skb->protocol = eth_type_trans(skb, ndev); | |
949 | netif_receive_skb(skb); | |
950 | ndev->stats.rx_packets++; | |
951 | ndev->stats.rx_bytes += len; | |
952 | } | |
953 | } | |
954 | ||
955 | /* Increment consume index */ | |
956 | rxconsidx = rxconsidx + 1; | |
957 | if (rxconsidx >= ENET_RX_DESC) | |
958 | rxconsidx = 0; | |
959 | writel(rxconsidx, | |
960 | LPC_ENET_RXCONSUMEINDEX(pldat->net_base)); | |
961 | rx_done++; | |
962 | } | |
963 | ||
964 | return rx_done; | |
965 | } | |
966 | ||
967 | static int lpc_eth_poll(struct napi_struct *napi, int budget) | |
968 | { | |
969 | struct netdata_local *pldat = container_of(napi, | |
970 | struct netdata_local, napi); | |
971 | struct net_device *ndev = pldat->ndev; | |
972 | int rx_done = 0; | |
973 | struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0); | |
974 | ||
975 | __netif_tx_lock(txq, smp_processor_id()); | |
976 | __lpc_handle_xmit(ndev); | |
977 | __netif_tx_unlock(txq); | |
978 | rx_done = __lpc_handle_recv(ndev, budget); | |
979 | ||
980 | if (rx_done < budget) { | |
6ad20165 | 981 | napi_complete_done(napi, rx_done); |
b7370112 | 982 | lpc_eth_enable_int(pldat->net_base); |
983 | } | |
984 | ||
985 | return rx_done; | |
986 | } | |
987 | ||
988 | static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id) | |
989 | { | |
990 | struct net_device *ndev = dev_id; | |
991 | struct netdata_local *pldat = netdev_priv(ndev); | |
992 | u32 tmp; | |
993 | ||
994 | spin_lock(&pldat->lock); | |
995 | ||
996 | tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base)); | |
997 | /* Clear interrupts */ | |
998 | writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base)); | |
999 | ||
1000 | lpc_eth_disable_int(pldat->net_base); | |
1001 | if (likely(napi_schedule_prep(&pldat->napi))) | |
1002 | __napi_schedule(&pldat->napi); | |
1003 | ||
1004 | spin_unlock(&pldat->lock); | |
1005 | ||
1006 | return IRQ_HANDLED; | |
1007 | } | |
1008 | ||
1009 | static int lpc_eth_close(struct net_device *ndev) | |
1010 | { | |
1011 | unsigned long flags; | |
1012 | struct netdata_local *pldat = netdev_priv(ndev); | |
1013 | ||
1014 | if (netif_msg_ifdown(pldat)) | |
1015 | dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name); | |
1016 | ||
1017 | napi_disable(&pldat->napi); | |
1018 | netif_stop_queue(ndev); | |
1019 | ||
f786f356 PR |
1020 | if (ndev->phydev) |
1021 | phy_stop(ndev->phydev); | |
b7370112 | 1022 | |
1023 | spin_lock_irqsave(&pldat->lock, flags); | |
1024 | __lpc_eth_reset(pldat); | |
1025 | netif_carrier_off(ndev); | |
1026 | writel(0, LPC_ENET_MAC1(pldat->net_base)); | |
1027 | writel(0, LPC_ENET_MAC2(pldat->net_base)); | |
1028 | spin_unlock_irqrestore(&pldat->lock, flags); | |
1029 | ||
53080fe9 | 1030 | clk_disable_unprepare(pldat->clk); |
b7370112 | 1031 | |
1032 | return 0; | |
1033 | } | |
1034 | ||
1035 | static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
1036 | { | |
1037 | struct netdata_local *pldat = netdev_priv(ndev); | |
1038 | u32 len, txidx; | |
1039 | u32 *ptxstat; | |
1040 | struct txrx_desc_t *ptxrxdesc; | |
1041 | ||
1042 | len = skb->len; | |
1043 | ||
1044 | spin_lock_irq(&pldat->lock); | |
1045 | ||
1046 | if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) { | |
1047 | /* This function should never be called when there are no | |
1048 | buffers */ | |
1049 | netif_stop_queue(ndev); | |
1050 | spin_unlock_irq(&pldat->lock); | |
1051 | WARN(1, "BUG! TX request when no free TX buffers!\n"); | |
1052 | return NETDEV_TX_BUSY; | |
1053 | } | |
1054 | ||
1055 | /* Get the next TX descriptor index */ | |
1056 | txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base)); | |
1057 | ||
1058 | /* Setup control for the transfer */ | |
1059 | ptxstat = &pldat->tx_stat_v[txidx]; | |
1060 | *ptxstat = 0; | |
1061 | ptxrxdesc = &pldat->tx_desc_v[txidx]; | |
1062 | ptxrxdesc->control = | |
1063 | (len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT; | |
1064 | ||
1065 | /* Copy data to the DMA buffer */ | |
1066 | memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len); | |
1067 | ||
1068 | /* Save the buffer and increment the buffer counter */ | |
a7e2eaad | 1069 | pldat->skblen[txidx] = len; |
b7370112 | 1070 | pldat->num_used_tx_buffs++; |
1071 | ||
1072 | /* Start transmit */ | |
1073 | txidx++; | |
1074 | if (txidx >= ENET_TX_DESC) | |
1075 | txidx = 0; | |
1076 | writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base)); | |
1077 | ||
1078 | /* Stop queue if no more TX buffers */ | |
1079 | if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) | |
1080 | netif_stop_queue(ndev); | |
1081 | ||
1082 | spin_unlock_irq(&pldat->lock); | |
1083 | ||
a7e2eaad | 1084 | dev_kfree_skb(skb); |
b7370112 | 1085 | return NETDEV_TX_OK; |
1086 | } | |
1087 | ||
1088 | static int lpc_set_mac_address(struct net_device *ndev, void *p) | |
1089 | { | |
1090 | struct sockaddr *addr = p; | |
1091 | struct netdata_local *pldat = netdev_priv(ndev); | |
1092 | unsigned long flags; | |
1093 | ||
1094 | if (!is_valid_ether_addr(addr->sa_data)) | |
1095 | return -EADDRNOTAVAIL; | |
1096 | memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN); | |
1097 | ||
1098 | spin_lock_irqsave(&pldat->lock, flags); | |
1099 | ||
1100 | /* Set station address */ | |
1101 | __lpc_set_mac(pldat, ndev->dev_addr); | |
1102 | ||
1103 | spin_unlock_irqrestore(&pldat->lock, flags); | |
1104 | ||
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | static void lpc_eth_set_multicast_list(struct net_device *ndev) | |
1109 | { | |
1110 | struct netdata_local *pldat = netdev_priv(ndev); | |
1111 | struct netdev_hw_addr_list *mcptr = &ndev->mc; | |
1112 | struct netdev_hw_addr *ha; | |
1113 | u32 tmp32, hash_val, hashlo, hashhi; | |
1114 | unsigned long flags; | |
1115 | ||
1116 | spin_lock_irqsave(&pldat->lock, flags); | |
1117 | ||
1118 | /* Set station address */ | |
1119 | __lpc_set_mac(pldat, ndev->dev_addr); | |
1120 | ||
1121 | tmp32 = LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT; | |
1122 | ||
1123 | if (ndev->flags & IFF_PROMISC) | |
1124 | tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST | | |
1125 | LPC_RXFLTRW_ACCEPTUMULTICAST; | |
1126 | if (ndev->flags & IFF_ALLMULTI) | |
1127 | tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST; | |
1128 | ||
1129 | if (netdev_hw_addr_list_count(mcptr)) | |
1130 | tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH; | |
1131 | ||
1132 | writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base)); | |
1133 | ||
1134 | ||
1135 | /* Set initial hash table */ | |
1136 | hashlo = 0x0; | |
1137 | hashhi = 0x0; | |
1138 | ||
1139 | /* 64 bits : multicast address in hash table */ | |
1140 | netdev_hw_addr_list_for_each(ha, mcptr) { | |
1141 | hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F; | |
1142 | ||
1143 | if (hash_val >= 32) | |
1144 | hashhi |= 1 << (hash_val - 32); | |
1145 | else | |
1146 | hashlo |= 1 << hash_val; | |
1147 | } | |
1148 | ||
1149 | writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base)); | |
1150 | writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base)); | |
1151 | ||
1152 | spin_unlock_irqrestore(&pldat->lock, flags); | |
1153 | } | |
1154 | ||
1155 | static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) | |
1156 | { | |
f786f356 | 1157 | struct phy_device *phydev = ndev->phydev; |
b7370112 | 1158 | |
1159 | if (!netif_running(ndev)) | |
1160 | return -EINVAL; | |
1161 | ||
1162 | if (!phydev) | |
1163 | return -ENODEV; | |
1164 | ||
1165 | return phy_mii_ioctl(phydev, req, cmd); | |
1166 | } | |
1167 | ||
1168 | static int lpc_eth_open(struct net_device *ndev) | |
1169 | { | |
1170 | struct netdata_local *pldat = netdev_priv(ndev); | |
53080fe9 | 1171 | int ret; |
b7370112 | 1172 | |
1173 | if (netif_msg_ifup(pldat)) | |
1174 | dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name); | |
1175 | ||
53080fe9 FE |
1176 | ret = clk_prepare_enable(pldat->clk); |
1177 | if (ret) | |
1178 | return ret; | |
b7370112 | 1179 | |
aff88a06 | 1180 | /* Suspended PHY makes LPC ethernet core block, so resume now */ |
f786f356 | 1181 | phy_resume(ndev->phydev); |
aff88a06 | 1182 | |
b7370112 | 1183 | /* Reset and initialize */ |
1184 | __lpc_eth_reset(pldat); | |
1185 | __lpc_eth_init(pldat); | |
1186 | ||
1187 | /* schedule a link state check */ | |
f786f356 | 1188 | phy_start(ndev->phydev); |
b7370112 | 1189 | netif_start_queue(ndev); |
1190 | napi_enable(&pldat->napi); | |
1191 | ||
1192 | return 0; | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * Ethtool ops | |
1197 | */ | |
1198 | static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev, | |
1199 | struct ethtool_drvinfo *info) | |
1200 | { | |
7826d43f JP |
1201 | strlcpy(info->driver, MODNAME, sizeof(info->driver)); |
1202 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
1203 | strlcpy(info->bus_info, dev_name(ndev->dev.parent), | |
1204 | sizeof(info->bus_info)); | |
b7370112 | 1205 | } |
1206 | ||
1207 | static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev) | |
1208 | { | |
1209 | struct netdata_local *pldat = netdev_priv(ndev); | |
1210 | ||
1211 | return pldat->msg_enable; | |
1212 | } | |
1213 | ||
1214 | static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level) | |
1215 | { | |
1216 | struct netdata_local *pldat = netdev_priv(ndev); | |
1217 | ||
1218 | pldat->msg_enable = level; | |
1219 | } | |
1220 | ||
b7370112 | 1221 | static const struct ethtool_ops lpc_eth_ethtool_ops = { |
1222 | .get_drvinfo = lpc_eth_ethtool_getdrvinfo, | |
b7370112 | 1223 | .get_msglevel = lpc_eth_ethtool_getmsglevel, |
1224 | .set_msglevel = lpc_eth_ethtool_setmsglevel, | |
1225 | .get_link = ethtool_op_get_link, | |
cb90d3e1 PR |
1226 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
1227 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
b7370112 | 1228 | }; |
1229 | ||
1230 | static const struct net_device_ops lpc_netdev_ops = { | |
1231 | .ndo_open = lpc_eth_open, | |
1232 | .ndo_stop = lpc_eth_close, | |
1233 | .ndo_start_xmit = lpc_eth_hard_start_xmit, | |
1234 | .ndo_set_rx_mode = lpc_eth_set_multicast_list, | |
1235 | .ndo_do_ioctl = lpc_eth_ioctl, | |
1236 | .ndo_set_mac_address = lpc_set_mac_address, | |
c867b55e | 1237 | .ndo_validate_addr = eth_validate_addr, |
b7370112 | 1238 | }; |
1239 | ||
1240 | static int lpc_eth_drv_probe(struct platform_device *pdev) | |
1241 | { | |
b5b4185c VZ |
1242 | struct device *dev = &pdev->dev; |
1243 | struct device_node *np = dev->of_node; | |
b7370112 | 1244 | struct netdata_local *pldat; |
b5b4185c | 1245 | struct net_device *ndev; |
b7370112 | 1246 | dma_addr_t dma_handle; |
b5b4185c | 1247 | struct resource *res; |
b7370112 | 1248 | int irq, ret; |
4de02e4a RS |
1249 | u32 tmp; |
1250 | ||
1251 | /* Setup network interface for RMII or MII mode */ | |
1252 | tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); | |
1253 | tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; | |
b5b4185c | 1254 | if (lpc_phy_interface_mode(dev) == PHY_INTERFACE_MODE_MII) |
4de02e4a RS |
1255 | tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; |
1256 | else | |
1257 | tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; | |
1258 | __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); | |
b7370112 | 1259 | |
1260 | /* Get platform resources */ | |
1261 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b7370112 | 1262 | irq = platform_get_irq(pdev, 0); |
39198ec9 | 1263 | if (!res || irq < 0) { |
b5b4185c | 1264 | dev_err(dev, "error getting resources.\n"); |
b7370112 | 1265 | ret = -ENXIO; |
1266 | goto err_exit; | |
1267 | } | |
1268 | ||
1269 | /* Allocate net driver data structure */ | |
1270 | ndev = alloc_etherdev(sizeof(struct netdata_local)); | |
1271 | if (!ndev) { | |
b5b4185c | 1272 | dev_err(dev, "could not allocate device.\n"); |
b7370112 | 1273 | ret = -ENOMEM; |
1274 | goto err_exit; | |
1275 | } | |
1276 | ||
b5b4185c | 1277 | SET_NETDEV_DEV(ndev, dev); |
b7370112 | 1278 | |
1279 | pldat = netdev_priv(ndev); | |
1280 | pldat->pdev = pdev; | |
1281 | pldat->ndev = ndev; | |
1282 | ||
1283 | spin_lock_init(&pldat->lock); | |
1284 | ||
1285 | /* Save resources */ | |
1286 | ndev->irq = irq; | |
1287 | ||
1288 | /* Get clock for the device */ | |
b5b4185c | 1289 | pldat->clk = clk_get(dev, NULL); |
b7370112 | 1290 | if (IS_ERR(pldat->clk)) { |
b5b4185c | 1291 | dev_err(dev, "error getting clock.\n"); |
b7370112 | 1292 | ret = PTR_ERR(pldat->clk); |
1293 | goto err_out_free_dev; | |
1294 | } | |
1295 | ||
1296 | /* Enable network clock */ | |
53080fe9 FE |
1297 | ret = clk_prepare_enable(pldat->clk); |
1298 | if (ret) | |
1299 | goto err_out_clk_put; | |
b7370112 | 1300 | |
1301 | /* Map IO space */ | |
9323b239 | 1302 | pldat->net_base = ioremap(res->start, resource_size(res)); |
b7370112 | 1303 | if (!pldat->net_base) { |
b5b4185c | 1304 | dev_err(dev, "failed to map registers\n"); |
b7370112 | 1305 | ret = -ENOMEM; |
1306 | goto err_out_disable_clocks; | |
1307 | } | |
1308 | ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0, | |
1309 | ndev->name, ndev); | |
1310 | if (ret) { | |
b5b4185c | 1311 | dev_err(dev, "error requesting interrupt.\n"); |
b7370112 | 1312 | goto err_out_iounmap; |
1313 | } | |
1314 | ||
b7370112 | 1315 | /* Setup driver functions */ |
1316 | ndev->netdev_ops = &lpc_netdev_ops; | |
1317 | ndev->ethtool_ops = &lpc_eth_ethtool_ops; | |
1318 | ndev->watchdog_timeo = msecs_to_jiffies(2500); | |
1319 | ||
1320 | /* Get size of DMA buffers/descriptors region */ | |
1321 | pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE + | |
1322 | sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t)); | |
1323 | pldat->dma_buff_base_v = 0; | |
1324 | ||
b5b4185c | 1325 | if (use_iram_for_net(dev)) { |
4de02e4a | 1326 | dma_handle = LPC32XX_IRAM_BASE; |
b7370112 | 1327 | if (pldat->dma_buff_size <= lpc32xx_return_iram_size()) |
1328 | pldat->dma_buff_base_v = | |
4de02e4a | 1329 | io_p2v(LPC32XX_IRAM_BASE); |
b7370112 | 1330 | else |
1331 | netdev_err(ndev, | |
1332 | "IRAM not big enough for net buffers, using SDRAM instead.\n"); | |
1333 | } | |
1334 | ||
1335 | if (pldat->dma_buff_base_v == 0) { | |
b5b4185c | 1336 | ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
b469357f RK |
1337 | if (ret) |
1338 | goto err_out_free_irq; | |
1339 | ||
b7370112 | 1340 | pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size); |
1341 | ||
1342 | /* Allocate a chunk of memory for the DMA ethernet buffers | |
1343 | and descriptors */ | |
1344 | pldat->dma_buff_base_v = | |
b5b4185c | 1345 | dma_alloc_coherent(dev, |
b7370112 | 1346 | pldat->dma_buff_size, &dma_handle, |
1347 | GFP_KERNEL); | |
b7370112 | 1348 | if (pldat->dma_buff_base_v == NULL) { |
b7370112 | 1349 | ret = -ENOMEM; |
1350 | goto err_out_free_irq; | |
1351 | } | |
1352 | } | |
1353 | pldat->dma_buff_base_p = dma_handle; | |
1354 | ||
9323b239 BT |
1355 | netdev_dbg(ndev, "IO address space :%pR\n", res); |
1356 | netdev_dbg(ndev, "IO address size :%d\n", resource_size(res)); | |
b31525d1 | 1357 | netdev_dbg(ndev, "IO address (mapped) :0x%p\n", |
b7370112 | 1358 | pldat->net_base); |
1359 | netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq); | |
1360 | netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size); | |
1361 | netdev_dbg(ndev, "DMA buffer P address :0x%08x\n", | |
1362 | pldat->dma_buff_base_p); | |
1363 | netdev_dbg(ndev, "DMA buffer V address :0x%p\n", | |
1364 | pldat->dma_buff_base_v); | |
1365 | ||
1366 | /* Get MAC address from current HW setting (POR state is all zeros) */ | |
1367 | __lpc_get_mac(pldat, ndev->dev_addr); | |
1368 | ||
b7370112 | 1369 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
b5b4185c | 1370 | const char *macaddr = of_get_mac_address(np); |
a51645f7 | 1371 | if (!IS_ERR(macaddr)) |
2d2924af | 1372 | ether_addr_copy(ndev->dev_addr, macaddr); |
b7370112 | 1373 | } |
b7370112 | 1374 | if (!is_valid_ether_addr(ndev->dev_addr)) |
cdaf0b83 | 1375 | eth_hw_addr_random(ndev); |
b7370112 | 1376 | |
1377 | /* Reset the ethernet controller */ | |
1378 | __lpc_eth_reset(pldat); | |
1379 | ||
1380 | /* then shut everything down to save power */ | |
1381 | __lpc_eth_shutdown(pldat); | |
1382 | ||
1383 | /* Set default parameters */ | |
1384 | pldat->msg_enable = NETIF_MSG_LINK; | |
1385 | ||
1386 | /* Force an MII interface reset and clock setup */ | |
1387 | __lpc_mii_mngt_reset(pldat); | |
1388 | ||
1389 | /* Force default PHY interface setup in chip, this will probably be | |
1390 | changed by the PHY driver */ | |
1391 | pldat->link = 0; | |
1392 | pldat->speed = 100; | |
1393 | pldat->duplex = DUPLEX_FULL; | |
1394 | __lpc_params_setup(pldat); | |
1395 | ||
1396 | netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT); | |
1397 | ||
1398 | ret = register_netdev(ndev); | |
1399 | if (ret) { | |
b5b4185c | 1400 | dev_err(dev, "Cannot register net device, aborting.\n"); |
b7370112 | 1401 | goto err_out_dma_unmap; |
1402 | } | |
1403 | platform_set_drvdata(pdev, ndev); | |
1404 | ||
fa90b077 WY |
1405 | ret = lpc_mii_init(pldat); |
1406 | if (ret) | |
b7370112 | 1407 | goto err_out_unregister_netdev; |
1408 | ||
1409 | netdev_info(ndev, "LPC mac at 0x%08x irq %d\n", | |
1410 | res->start, ndev->irq); | |
1411 | ||
b5b4185c VZ |
1412 | device_init_wakeup(dev, 1); |
1413 | device_set_wakeup_enable(dev, 0); | |
b7370112 | 1414 | |
1415 | return 0; | |
1416 | ||
1417 | err_out_unregister_netdev: | |
b7370112 | 1418 | unregister_netdev(ndev); |
1419 | err_out_dma_unmap: | |
b5b4185c | 1420 | if (!use_iram_for_net(dev) || |
b7370112 | 1421 | pldat->dma_buff_size > lpc32xx_return_iram_size()) |
b5b4185c | 1422 | dma_free_coherent(dev, pldat->dma_buff_size, |
b7370112 | 1423 | pldat->dma_buff_base_v, |
1424 | pldat->dma_buff_base_p); | |
1425 | err_out_free_irq: | |
1426 | free_irq(ndev->irq, ndev); | |
1427 | err_out_iounmap: | |
1428 | iounmap(pldat->net_base); | |
1429 | err_out_disable_clocks: | |
33a8316d | 1430 | clk_disable_unprepare(pldat->clk); |
53080fe9 | 1431 | err_out_clk_put: |
b7370112 | 1432 | clk_put(pldat->clk); |
1433 | err_out_free_dev: | |
1434 | free_netdev(ndev); | |
1435 | err_exit: | |
1436 | pr_err("%s: not found (%d).\n", MODNAME, ret); | |
1437 | return ret; | |
1438 | } | |
1439 | ||
1440 | static int lpc_eth_drv_remove(struct platform_device *pdev) | |
1441 | { | |
1442 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1443 | struct netdata_local *pldat = netdev_priv(ndev); | |
1444 | ||
1445 | unregister_netdev(ndev); | |
b7370112 | 1446 | |
4de02e4a | 1447 | if (!use_iram_for_net(&pldat->pdev->dev) || |
b7370112 | 1448 | pldat->dma_buff_size > lpc32xx_return_iram_size()) |
1449 | dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, | |
1450 | pldat->dma_buff_base_v, | |
1451 | pldat->dma_buff_base_p); | |
1452 | free_irq(ndev->irq, ndev); | |
1453 | iounmap(pldat->net_base); | |
57c10b61 | 1454 | mdiobus_unregister(pldat->mii_bus); |
b7370112 | 1455 | mdiobus_free(pldat->mii_bus); |
33a8316d | 1456 | clk_disable_unprepare(pldat->clk); |
b7370112 | 1457 | clk_put(pldat->clk); |
1458 | free_netdev(ndev); | |
1459 | ||
1460 | return 0; | |
1461 | } | |
1462 | ||
1463 | #ifdef CONFIG_PM | |
1464 | static int lpc_eth_drv_suspend(struct platform_device *pdev, | |
1465 | pm_message_t state) | |
1466 | { | |
1467 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1468 | struct netdata_local *pldat = netdev_priv(ndev); | |
1469 | ||
1470 | if (device_may_wakeup(&pdev->dev)) | |
1471 | enable_irq_wake(ndev->irq); | |
1472 | ||
1473 | if (ndev) { | |
1474 | if (netif_running(ndev)) { | |
1475 | netif_device_detach(ndev); | |
1476 | __lpc_eth_shutdown(pldat); | |
33a8316d | 1477 | clk_disable_unprepare(pldat->clk); |
b7370112 | 1478 | |
1479 | /* | |
1480 | * Reset again now clock is disable to be sure | |
1481 | * EMC_MDC is down | |
1482 | */ | |
1483 | __lpc_eth_reset(pldat); | |
1484 | } | |
1485 | } | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
1490 | static int lpc_eth_drv_resume(struct platform_device *pdev) | |
1491 | { | |
1492 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1493 | struct netdata_local *pldat; | |
1494 | ||
1495 | if (device_may_wakeup(&pdev->dev)) | |
1496 | disable_irq_wake(ndev->irq); | |
1497 | ||
1498 | if (ndev) { | |
1499 | if (netif_running(ndev)) { | |
1500 | pldat = netdev_priv(ndev); | |
1501 | ||
1502 | /* Enable interface clock */ | |
1503 | clk_enable(pldat->clk); | |
1504 | ||
1505 | /* Reset and initialize */ | |
1506 | __lpc_eth_reset(pldat); | |
1507 | __lpc_eth_init(pldat); | |
1508 | ||
1509 | netif_device_attach(ndev); | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | #endif | |
1516 | ||
4de02e4a RS |
1517 | static const struct of_device_id lpc_eth_match[] = { |
1518 | { .compatible = "nxp,lpc-eth" }, | |
1519 | { } | |
1520 | }; | |
1521 | MODULE_DEVICE_TABLE(of, lpc_eth_match); | |
4de02e4a | 1522 | |
b7370112 | 1523 | static struct platform_driver lpc_eth_driver = { |
1524 | .probe = lpc_eth_drv_probe, | |
21524526 | 1525 | .remove = lpc_eth_drv_remove, |
b7370112 | 1526 | #ifdef CONFIG_PM |
1527 | .suspend = lpc_eth_drv_suspend, | |
1528 | .resume = lpc_eth_drv_resume, | |
1529 | #endif | |
1530 | .driver = { | |
1531 | .name = MODNAME, | |
643d813a | 1532 | .of_match_table = lpc_eth_match, |
b7370112 | 1533 | }, |
1534 | }; | |
1535 | ||
1536 | module_platform_driver(lpc_eth_driver); | |
1537 | ||
1538 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); | |
1539 | MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); | |
1540 | MODULE_DESCRIPTION("LPC Ethernet Driver"); | |
1541 | MODULE_LICENSE("GPL"); |