Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * forcedeth: Ethernet driver for NVIDIA nForce media access controllers. | |
3 | * | |
4 | * Note: This driver is a cleanroom reimplementation based on reverse | |
5 | * engineered documentation written by Carl-Daniel Hailfinger | |
87046e50 | 6 | * and Andrew de Quincey. |
1da177e4 LT |
7 | * |
8 | * NVIDIA, nForce and other NVIDIA marks are trademarks or registered | |
9 | * trademarks of NVIDIA Corporation in the United States and other | |
10 | * countries. | |
11 | * | |
1836098f | 12 | * Copyright (C) 2003,4,5 Manfred Spraul |
1da177e4 LT |
13 | * Copyright (C) 2004 Andrew de Quincey (wol support) |
14 | * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane | |
15 | * IRQ rate fixes, bigendian fixes, cleanups, verification) | |
f1405d32 | 16 | * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation |
1da177e4 LT |
17 | * |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
0ab75ae8 | 29 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 | 30 | * |
1da177e4 LT |
31 | * Known bugs: |
32 | * We suspect that on some hardware no TX done interrupts are generated. | |
33 | * This means recovery from netif_stop_queue only happens if the hw timer | |
34 | * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) | |
35 | * and the timer is active in the IRQMask, or if a rx packet arrives by chance. | |
36 | * If your hardware reliably generates tx done interrupts, then you can remove | |
37 | * DEV_NEED_TIMERIRQ from the driver_data flags. | |
38 | * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few | |
39 | * superfluous timer interrupts from the nic. | |
40 | */ | |
294a554e JP |
41 | |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
43 | ||
3e1a3ce2 | 44 | #define FORCEDETH_VERSION "0.64" |
1da177e4 LT |
45 | #define DRV_NAME "forcedeth" |
46 | ||
47 | #include <linux/module.h> | |
48 | #include <linux/types.h> | |
49 | #include <linux/pci.h> | |
50 | #include <linux/interrupt.h> | |
51 | #include <linux/netdevice.h> | |
52 | #include <linux/etherdevice.h> | |
53 | #include <linux/delay.h> | |
d43c36dc | 54 | #include <linux/sched.h> |
1da177e4 LT |
55 | #include <linux/spinlock.h> |
56 | #include <linux/ethtool.h> | |
57 | #include <linux/timer.h> | |
58 | #include <linux/skbuff.h> | |
59 | #include <linux/mii.h> | |
60 | #include <linux/random.h> | |
22c6d143 | 61 | #include <linux/if_vlan.h> |
910638ae | 62 | #include <linux/dma-mapping.h> |
5a0e3ad6 | 63 | #include <linux/slab.h> |
5504e139 | 64 | #include <linux/uaccess.h> |
70c71606 | 65 | #include <linux/prefetch.h> |
f5d827ae | 66 | #include <linux/u64_stats_sync.h> |
67 | #include <linux/io.h> | |
1da177e4 LT |
68 | |
69 | #include <asm/irq.h> | |
1da177e4 | 70 | |
bea3348e SH |
71 | #define TX_WORK_PER_LOOP 64 |
72 | #define RX_WORK_PER_LOOP 64 | |
1da177e4 LT |
73 | |
74 | /* | |
75 | * Hardware access: | |
76 | */ | |
77 | ||
3c2e1c11 AA |
78 | #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */ |
79 | #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */ | |
80 | #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */ | |
81 | #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */ | |
82 | #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */ | |
83 | #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */ | |
84 | #define DEV_HAS_MSI 0x0000040 /* device supports MSI */ | |
85 | #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */ | |
86 | #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */ | |
87 | #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */ | |
7b5e078c MD |
88 | #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */ |
89 | #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */ | |
90 | #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */ | |
91 | #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */ | |
3c2e1c11 AA |
92 | #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */ |
93 | #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */ | |
94 | #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */ | |
95 | #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */ | |
96 | #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */ | |
97 | #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */ | |
98 | #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */ | |
99 | #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */ | |
100 | #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */ | |
101 | #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */ | |
102 | #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */ | |
103 | #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */ | |
104 | #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */ | |
1da177e4 LT |
105 | |
106 | enum { | |
107 | NvRegIrqStatus = 0x000, | |
108 | #define NVREG_IRQSTAT_MIIEVENT 0x040 | |
daa91a9d | 109 | #define NVREG_IRQSTAT_MASK 0x83ff |
1da177e4 LT |
110 | NvRegIrqMask = 0x004, |
111 | #define NVREG_IRQ_RX_ERROR 0x0001 | |
112 | #define NVREG_IRQ_RX 0x0002 | |
113 | #define NVREG_IRQ_RX_NOBUF 0x0004 | |
114 | #define NVREG_IRQ_TX_ERR 0x0008 | |
c2dba06d | 115 | #define NVREG_IRQ_TX_OK 0x0010 |
1da177e4 LT |
116 | #define NVREG_IRQ_TIMER 0x0020 |
117 | #define NVREG_IRQ_LINK 0x0040 | |
d33a73c8 AA |
118 | #define NVREG_IRQ_RX_FORCED 0x0080 |
119 | #define NVREG_IRQ_TX_FORCED 0x0100 | |
daa91a9d | 120 | #define NVREG_IRQ_RECOVER_ERROR 0x8200 |
a971c324 | 121 | #define NVREG_IRQMASK_THROUGHPUT 0x00df |
096a458c | 122 | #define NVREG_IRQMASK_CPU 0x0060 |
d33a73c8 AA |
123 | #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) |
124 | #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) | |
c5cf9101 | 125 | #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) |
c2dba06d | 126 | |
1da177e4 LT |
127 | NvRegUnknownSetupReg6 = 0x008, |
128 | #define NVREG_UNKSETUP6_VAL 3 | |
129 | ||
130 | /* | |
131 | * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic | |
132 | * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms | |
133 | */ | |
134 | NvRegPollingInterval = 0x00c, | |
6cef67a0 | 135 | #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */ |
a971c324 | 136 | #define NVREG_POLL_DEFAULT_CPU 13 |
d33a73c8 AA |
137 | NvRegMSIMap0 = 0x020, |
138 | NvRegMSIMap1 = 0x024, | |
139 | NvRegMSIIrqMask = 0x030, | |
140 | #define NVREG_MSI_VECTOR_0_ENABLED 0x01 | |
1da177e4 | 141 | NvRegMisc1 = 0x080, |
eb91f61b | 142 | #define NVREG_MISC1_PAUSE_TX 0x01 |
1da177e4 LT |
143 | #define NVREG_MISC1_HD 0x02 |
144 | #define NVREG_MISC1_FORCE 0x3b0f3c | |
145 | ||
0a62677b | 146 | NvRegMacReset = 0x34, |
86a0f043 | 147 | #define NVREG_MAC_RESET_ASSERT 0x0F3 |
1da177e4 LT |
148 | NvRegTransmitterControl = 0x084, |
149 | #define NVREG_XMITCTL_START 0x01 | |
7e680c22 AA |
150 | #define NVREG_XMITCTL_MGMT_ST 0x40000000 |
151 | #define NVREG_XMITCTL_SYNC_MASK 0x000f0000 | |
152 | #define NVREG_XMITCTL_SYNC_NOT_READY 0x0 | |
153 | #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 | |
154 | #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 | |
155 | #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 | |
156 | #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 | |
157 | #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 | |
158 | #define NVREG_XMITCTL_HOST_LOADED 0x00004000 | |
f35723ec | 159 | #define NVREG_XMITCTL_TX_PATH_EN 0x01000000 |
cac1c52c AA |
160 | #define NVREG_XMITCTL_DATA_START 0x00100000 |
161 | #define NVREG_XMITCTL_DATA_READY 0x00010000 | |
162 | #define NVREG_XMITCTL_DATA_ERROR 0x00020000 | |
1da177e4 LT |
163 | NvRegTransmitterStatus = 0x088, |
164 | #define NVREG_XMITSTAT_BUSY 0x01 | |
165 | ||
166 | NvRegPacketFilterFlags = 0x8c, | |
eb91f61b AA |
167 | #define NVREG_PFF_PAUSE_RX 0x08 |
168 | #define NVREG_PFF_ALWAYS 0x7F0000 | |
1da177e4 LT |
169 | #define NVREG_PFF_PROMISC 0x80 |
170 | #define NVREG_PFF_MYADDR 0x20 | |
9589c77a | 171 | #define NVREG_PFF_LOOPBACK 0x10 |
1da177e4 LT |
172 | |
173 | NvRegOffloadConfig = 0x90, | |
174 | #define NVREG_OFFLOAD_HOMEPHY 0x601 | |
175 | #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE | |
176 | NvRegReceiverControl = 0x094, | |
177 | #define NVREG_RCVCTL_START 0x01 | |
f35723ec | 178 | #define NVREG_RCVCTL_RX_PATH_EN 0x01000000 |
1da177e4 LT |
179 | NvRegReceiverStatus = 0x98, |
180 | #define NVREG_RCVSTAT_BUSY 0x01 | |
181 | ||
a433686c AA |
182 | NvRegSlotTime = 0x9c, |
183 | #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000 | |
184 | #define NVREG_SLOTTIME_10_100_FULL 0x00007f00 | |
78aea4fc | 185 | #define NVREG_SLOTTIME_1000_FULL 0x0003ff00 |
a433686c | 186 | #define NVREG_SLOTTIME_HALF 0x0000ff00 |
78aea4fc | 187 | #define NVREG_SLOTTIME_DEFAULT 0x00007f00 |
a433686c | 188 | #define NVREG_SLOTTIME_MASK 0x000000ff |
1da177e4 | 189 | |
9744e218 | 190 | NvRegTxDeferral = 0xA0, |
fd9b558c AA |
191 | #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f |
192 | #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f | |
193 | #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f | |
194 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f | |
195 | #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f | |
196 | #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 | |
9744e218 AA |
197 | NvRegRxDeferral = 0xA4, |
198 | #define NVREG_RX_DEFERRAL_DEFAULT 0x16 | |
1da177e4 LT |
199 | NvRegMacAddrA = 0xA8, |
200 | NvRegMacAddrB = 0xAC, | |
201 | NvRegMulticastAddrA = 0xB0, | |
202 | #define NVREG_MCASTADDRA_FORCE 0x01 | |
203 | NvRegMulticastAddrB = 0xB4, | |
204 | NvRegMulticastMaskA = 0xB8, | |
bb9a4fd1 | 205 | #define NVREG_MCASTMASKA_NONE 0xffffffff |
1da177e4 | 206 | NvRegMulticastMaskB = 0xBC, |
bb9a4fd1 | 207 | #define NVREG_MCASTMASKB_NONE 0xffff |
1da177e4 LT |
208 | |
209 | NvRegPhyInterface = 0xC0, | |
210 | #define PHY_RGMII 0x10000000 | |
a433686c AA |
211 | NvRegBackOffControl = 0xC4, |
212 | #define NVREG_BKOFFCTRL_DEFAULT 0x70000000 | |
213 | #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff | |
214 | #define NVREG_BKOFFCTRL_SELECT 24 | |
215 | #define NVREG_BKOFFCTRL_GEAR 12 | |
1da177e4 LT |
216 | |
217 | NvRegTxRingPhysAddr = 0x100, | |
218 | NvRegRxRingPhysAddr = 0x104, | |
219 | NvRegRingSizes = 0x108, | |
220 | #define NVREG_RINGSZ_TXSHIFT 0 | |
221 | #define NVREG_RINGSZ_RXSHIFT 16 | |
5070d340 AA |
222 | NvRegTransmitPoll = 0x10c, |
223 | #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 | |
1da177e4 LT |
224 | NvRegLinkSpeed = 0x110, |
225 | #define NVREG_LINKSPEED_FORCE 0x10000 | |
226 | #define NVREG_LINKSPEED_10 1000 | |
227 | #define NVREG_LINKSPEED_100 100 | |
228 | #define NVREG_LINKSPEED_1000 50 | |
229 | #define NVREG_LINKSPEED_MASK (0xFFF) | |
230 | NvRegUnknownSetupReg5 = 0x130, | |
231 | #define NVREG_UNKSETUP5_BIT31 (1<<31) | |
95d161cb AA |
232 | NvRegTxWatermark = 0x13c, |
233 | #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 | |
234 | #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 | |
235 | #define NVREG_TX_WM_DESC2_3_1000 0xfe08000 | |
1da177e4 LT |
236 | NvRegTxRxControl = 0x144, |
237 | #define NVREG_TXRXCTL_KICK 0x0001 | |
238 | #define NVREG_TXRXCTL_BIT1 0x0002 | |
239 | #define NVREG_TXRXCTL_BIT2 0x0004 | |
240 | #define NVREG_TXRXCTL_IDLE 0x0008 | |
241 | #define NVREG_TXRXCTL_RESET 0x0010 | |
242 | #define NVREG_TXRXCTL_RXCHECK 0x0400 | |
8a4ae7f2 | 243 | #define NVREG_TXRXCTL_DESC_1 0 |
d2f78412 AA |
244 | #define NVREG_TXRXCTL_DESC_2 0x002100 |
245 | #define NVREG_TXRXCTL_DESC_3 0xc02200 | |
ee407b02 AA |
246 | #define NVREG_TXRXCTL_VLANSTRIP 0x00040 |
247 | #define NVREG_TXRXCTL_VLANINS 0x00080 | |
0832b25a AA |
248 | NvRegTxRingPhysAddrHigh = 0x148, |
249 | NvRegRxRingPhysAddrHigh = 0x14C, | |
eb91f61b | 250 | NvRegTxPauseFrame = 0x170, |
5289b4c4 AA |
251 | #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 |
252 | #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 | |
253 | #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 | |
254 | #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 | |
9a33e883 AA |
255 | NvRegTxPauseFrameLimit = 0x174, |
256 | #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000 | |
1da177e4 LT |
257 | NvRegMIIStatus = 0x180, |
258 | #define NVREG_MIISTAT_ERROR 0x0001 | |
259 | #define NVREG_MIISTAT_LINKCHANGE 0x0008 | |
eb798428 AA |
260 | #define NVREG_MIISTAT_MASK_RW 0x0007 |
261 | #define NVREG_MIISTAT_MASK_ALL 0x000f | |
7e680c22 AA |
262 | NvRegMIIMask = 0x184, |
263 | #define NVREG_MII_LINKCHANGE 0x0008 | |
1da177e4 LT |
264 | |
265 | NvRegAdapterControl = 0x188, | |
266 | #define NVREG_ADAPTCTL_START 0x02 | |
267 | #define NVREG_ADAPTCTL_LINKUP 0x04 | |
268 | #define NVREG_ADAPTCTL_PHYVALID 0x40000 | |
269 | #define NVREG_ADAPTCTL_RUNNING 0x100000 | |
270 | #define NVREG_ADAPTCTL_PHYSHIFT 24 | |
271 | NvRegMIISpeed = 0x18c, | |
272 | #define NVREG_MIISPEED_BIT8 (1<<8) | |
273 | #define NVREG_MIIDELAY 5 | |
274 | NvRegMIIControl = 0x190, | |
275 | #define NVREG_MIICTL_INUSE 0x08000 | |
276 | #define NVREG_MIICTL_WRITE 0x00400 | |
277 | #define NVREG_MIICTL_ADDRSHIFT 5 | |
278 | NvRegMIIData = 0x194, | |
9c662435 AA |
279 | NvRegTxUnicast = 0x1a0, |
280 | NvRegTxMulticast = 0x1a4, | |
281 | NvRegTxBroadcast = 0x1a8, | |
1da177e4 LT |
282 | NvRegWakeUpFlags = 0x200, |
283 | #define NVREG_WAKEUPFLAGS_VAL 0x7770 | |
284 | #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 | |
285 | #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 | |
286 | #define NVREG_WAKEUPFLAGS_D3SHIFT 12 | |
287 | #define NVREG_WAKEUPFLAGS_D2SHIFT 8 | |
288 | #define NVREG_WAKEUPFLAGS_D1SHIFT 4 | |
289 | #define NVREG_WAKEUPFLAGS_D0SHIFT 0 | |
290 | #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 | |
291 | #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 | |
292 | #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 | |
293 | #define NVREG_WAKEUPFLAGS_ENABLE 0x1111 | |
294 | ||
cac1c52c | 295 | NvRegMgmtUnitGetVersion = 0x204, |
78aea4fc | 296 | #define NVREG_MGMTUNITGETVERSION 0x01 |
cac1c52c AA |
297 | NvRegMgmtUnitVersion = 0x208, |
298 | #define NVREG_MGMTUNITVERSION 0x08 | |
1da177e4 LT |
299 | NvRegPowerCap = 0x268, |
300 | #define NVREG_POWERCAP_D3SUPP (1<<30) | |
301 | #define NVREG_POWERCAP_D2SUPP (1<<26) | |
302 | #define NVREG_POWERCAP_D1SUPP (1<<25) | |
303 | NvRegPowerState = 0x26c, | |
304 | #define NVREG_POWERSTATE_POWEREDUP 0x8000 | |
305 | #define NVREG_POWERSTATE_VALID 0x0100 | |
306 | #define NVREG_POWERSTATE_MASK 0x0003 | |
307 | #define NVREG_POWERSTATE_D0 0x0000 | |
308 | #define NVREG_POWERSTATE_D1 0x0001 | |
309 | #define NVREG_POWERSTATE_D2 0x0002 | |
310 | #define NVREG_POWERSTATE_D3 0x0003 | |
cac1c52c AA |
311 | NvRegMgmtUnitControl = 0x278, |
312 | #define NVREG_MGMTUNITCONTROL_INUSE 0x20000 | |
52da3578 AA |
313 | NvRegTxCnt = 0x280, |
314 | NvRegTxZeroReXmt = 0x284, | |
315 | NvRegTxOneReXmt = 0x288, | |
316 | NvRegTxManyReXmt = 0x28c, | |
317 | NvRegTxLateCol = 0x290, | |
318 | NvRegTxUnderflow = 0x294, | |
319 | NvRegTxLossCarrier = 0x298, | |
320 | NvRegTxExcessDef = 0x29c, | |
321 | NvRegTxRetryErr = 0x2a0, | |
322 | NvRegRxFrameErr = 0x2a4, | |
323 | NvRegRxExtraByte = 0x2a8, | |
324 | NvRegRxLateCol = 0x2ac, | |
325 | NvRegRxRunt = 0x2b0, | |
326 | NvRegRxFrameTooLong = 0x2b4, | |
327 | NvRegRxOverflow = 0x2b8, | |
328 | NvRegRxFCSErr = 0x2bc, | |
329 | NvRegRxFrameAlignErr = 0x2c0, | |
330 | NvRegRxLenErr = 0x2c4, | |
331 | NvRegRxUnicast = 0x2c8, | |
332 | NvRegRxMulticast = 0x2cc, | |
333 | NvRegRxBroadcast = 0x2d0, | |
334 | NvRegTxDef = 0x2d4, | |
335 | NvRegTxFrame = 0x2d8, | |
336 | NvRegRxCnt = 0x2dc, | |
337 | NvRegTxPause = 0x2e0, | |
338 | NvRegRxPause = 0x2e4, | |
339 | NvRegRxDropFrame = 0x2e8, | |
ee407b02 AA |
340 | NvRegVlanControl = 0x300, |
341 | #define NVREG_VLANCONTROL_ENABLE 0x2000 | |
d33a73c8 AA |
342 | NvRegMSIXMap0 = 0x3e0, |
343 | NvRegMSIXMap1 = 0x3e4, | |
344 | NvRegMSIXIrqStatus = 0x3f0, | |
86a0f043 AA |
345 | |
346 | NvRegPowerState2 = 0x600, | |
1545e205 | 347 | #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15 |
86a0f043 | 348 | #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 |
22ae03a1 | 349 | #define NVREG_POWERSTATE2_PHY_RESET 0x0004 |
88d7d8b0 | 350 | #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00 |
1da177e4 LT |
351 | }; |
352 | ||
353 | /* Big endian: should work, but is untested */ | |
354 | struct ring_desc { | |
a8bed49e SH |
355 | __le32 buf; |
356 | __le32 flaglen; | |
1da177e4 LT |
357 | }; |
358 | ||
ee73362c | 359 | struct ring_desc_ex { |
a8bed49e SH |
360 | __le32 bufhigh; |
361 | __le32 buflow; | |
362 | __le32 txvlan; | |
363 | __le32 flaglen; | |
ee73362c MS |
364 | }; |
365 | ||
f82a9352 | 366 | union ring_type { |
78aea4fc SJ |
367 | struct ring_desc *orig; |
368 | struct ring_desc_ex *ex; | |
f82a9352 | 369 | }; |
ee73362c | 370 | |
1da177e4 LT |
371 | #define FLAG_MASK_V1 0xffff0000 |
372 | #define FLAG_MASK_V2 0xffffc000 | |
373 | #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) | |
374 | #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) | |
375 | ||
376 | #define NV_TX_LASTPACKET (1<<16) | |
377 | #define NV_TX_RETRYERROR (1<<19) | |
a433686c | 378 | #define NV_TX_RETRYCOUNT_MASK (0xF<<20) |
c2dba06d | 379 | #define NV_TX_FORCED_INTERRUPT (1<<24) |
1da177e4 LT |
380 | #define NV_TX_DEFERRED (1<<26) |
381 | #define NV_TX_CARRIERLOST (1<<27) | |
382 | #define NV_TX_LATECOLLISION (1<<28) | |
383 | #define NV_TX_UNDERFLOW (1<<29) | |
384 | #define NV_TX_ERROR (1<<30) | |
385 | #define NV_TX_VALID (1<<31) | |
386 | ||
387 | #define NV_TX2_LASTPACKET (1<<29) | |
388 | #define NV_TX2_RETRYERROR (1<<18) | |
a433686c | 389 | #define NV_TX2_RETRYCOUNT_MASK (0xF<<19) |
c2dba06d | 390 | #define NV_TX2_FORCED_INTERRUPT (1<<30) |
1da177e4 LT |
391 | #define NV_TX2_DEFERRED (1<<25) |
392 | #define NV_TX2_CARRIERLOST (1<<26) | |
393 | #define NV_TX2_LATECOLLISION (1<<27) | |
394 | #define NV_TX2_UNDERFLOW (1<<28) | |
395 | /* error and valid are the same for both */ | |
396 | #define NV_TX2_ERROR (1<<30) | |
397 | #define NV_TX2_VALID (1<<31) | |
ac9c1897 AA |
398 | #define NV_TX2_TSO (1<<28) |
399 | #define NV_TX2_TSO_SHIFT 14 | |
fa45459e AA |
400 | #define NV_TX2_TSO_MAX_SHIFT 14 |
401 | #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT) | |
8a4ae7f2 MS |
402 | #define NV_TX2_CHECKSUM_L3 (1<<27) |
403 | #define NV_TX2_CHECKSUM_L4 (1<<26) | |
1da177e4 | 404 | |
ee407b02 AA |
405 | #define NV_TX3_VLAN_TAG_PRESENT (1<<18) |
406 | ||
1da177e4 LT |
407 | #define NV_RX_DESCRIPTORVALID (1<<16) |
408 | #define NV_RX_MISSEDFRAME (1<<17) | |
cef33c81 | 409 | #define NV_RX_SUBTRACT1 (1<<18) |
1da177e4 LT |
410 | #define NV_RX_ERROR1 (1<<23) |
411 | #define NV_RX_ERROR2 (1<<24) | |
412 | #define NV_RX_ERROR3 (1<<25) | |
413 | #define NV_RX_ERROR4 (1<<26) | |
414 | #define NV_RX_CRCERR (1<<27) | |
415 | #define NV_RX_OVERFLOW (1<<28) | |
416 | #define NV_RX_FRAMINGERR (1<<29) | |
417 | #define NV_RX_ERROR (1<<30) | |
418 | #define NV_RX_AVAIL (1<<31) | |
1ef6841b | 419 | #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR) |
1da177e4 LT |
420 | |
421 | #define NV_RX2_CHECKSUMMASK (0x1C000000) | |
bfaffe8f AA |
422 | #define NV_RX2_CHECKSUM_IP (0x10000000) |
423 | #define NV_RX2_CHECKSUM_IP_TCP (0x14000000) | |
424 | #define NV_RX2_CHECKSUM_IP_UDP (0x18000000) | |
1da177e4 | 425 | #define NV_RX2_DESCRIPTORVALID (1<<29) |
cef33c81 | 426 | #define NV_RX2_SUBTRACT1 (1<<25) |
1da177e4 LT |
427 | #define NV_RX2_ERROR1 (1<<18) |
428 | #define NV_RX2_ERROR2 (1<<19) | |
429 | #define NV_RX2_ERROR3 (1<<20) | |
430 | #define NV_RX2_ERROR4 (1<<21) | |
431 | #define NV_RX2_CRCERR (1<<22) | |
432 | #define NV_RX2_OVERFLOW (1<<23) | |
433 | #define NV_RX2_FRAMINGERR (1<<24) | |
434 | /* error and avail are the same for both */ | |
435 | #define NV_RX2_ERROR (1<<30) | |
436 | #define NV_RX2_AVAIL (1<<31) | |
1ef6841b | 437 | #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR) |
1da177e4 | 438 | |
ee407b02 AA |
439 | #define NV_RX3_VLAN_TAG_PRESENT (1<<16) |
440 | #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF) | |
441 | ||
25985edc | 442 | /* Miscellaneous hardware related defines: */ |
78aea4fc SJ |
443 | #define NV_PCI_REGSZ_VER1 0x270 |
444 | #define NV_PCI_REGSZ_VER2 0x2d4 | |
445 | #define NV_PCI_REGSZ_VER3 0x604 | |
446 | #define NV_PCI_REGSZ_MAX 0x604 | |
1da177e4 LT |
447 | |
448 | /* various timeout delays: all in usec */ | |
449 | #define NV_TXRX_RESET_DELAY 4 | |
450 | #define NV_TXSTOP_DELAY1 10 | |
451 | #define NV_TXSTOP_DELAY1MAX 500000 | |
452 | #define NV_TXSTOP_DELAY2 100 | |
453 | #define NV_RXSTOP_DELAY1 10 | |
454 | #define NV_RXSTOP_DELAY1MAX 500000 | |
455 | #define NV_RXSTOP_DELAY2 100 | |
456 | #define NV_SETUP5_DELAY 5 | |
457 | #define NV_SETUP5_DELAYMAX 50000 | |
458 | #define NV_POWERUP_DELAY 5 | |
459 | #define NV_POWERUP_DELAYMAX 5000 | |
460 | #define NV_MIIBUSY_DELAY 50 | |
461 | #define NV_MIIPHY_DELAY 10 | |
462 | #define NV_MIIPHY_DELAYMAX 10000 | |
86a0f043 | 463 | #define NV_MAC_RESET_DELAY 64 |
1da177e4 LT |
464 | |
465 | #define NV_WAKEUPPATTERNS 5 | |
466 | #define NV_WAKEUPMASKENTRIES 4 | |
467 | ||
468 | /* General driver defaults */ | |
469 | #define NV_WATCHDOG_TIMEO (5*HZ) | |
470 | ||
6cef67a0 | 471 | #define RX_RING_DEFAULT 512 |
eafa59f6 AA |
472 | #define TX_RING_DEFAULT 256 |
473 | #define RX_RING_MIN 128 | |
474 | #define TX_RING_MIN 64 | |
475 | #define RING_MAX_DESC_VER_1 1024 | |
476 | #define RING_MAX_DESC_VER_2_3 16384 | |
1da177e4 LT |
477 | |
478 | /* rx/tx mac addr + type + vlan + align + slack*/ | |
d81c0983 MS |
479 | #define NV_RX_HEADERS (64) |
480 | /* even more slack. */ | |
481 | #define NV_RX_ALLOC_PAD (64) | |
482 | ||
483 | /* maximum mtu size */ | |
484 | #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */ | |
485 | #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */ | |
1da177e4 LT |
486 | |
487 | #define OOM_REFILL (1+HZ/20) | |
488 | #define POLL_WAIT (1+HZ/100) | |
489 | #define LINK_TIMEOUT (3*HZ) | |
52da3578 | 490 | #define STATS_INTERVAL (10*HZ) |
1da177e4 | 491 | |
f3b197ac | 492 | /* |
1da177e4 | 493 | * desc_ver values: |
8a4ae7f2 MS |
494 | * The nic supports three different descriptor types: |
495 | * - DESC_VER_1: Original | |
496 | * - DESC_VER_2: support for jumbo frames. | |
497 | * - DESC_VER_3: 64-bit format. | |
1da177e4 | 498 | */ |
8a4ae7f2 MS |
499 | #define DESC_VER_1 1 |
500 | #define DESC_VER_2 2 | |
501 | #define DESC_VER_3 3 | |
1da177e4 LT |
502 | |
503 | /* PHY defines */ | |
9f3f7910 AA |
504 | #define PHY_OUI_MARVELL 0x5043 |
505 | #define PHY_OUI_CICADA 0x03f1 | |
506 | #define PHY_OUI_VITESSE 0x01c1 | |
507 | #define PHY_OUI_REALTEK 0x0732 | |
508 | #define PHY_OUI_REALTEK2 0x0020 | |
1da177e4 LT |
509 | #define PHYID1_OUI_MASK 0x03ff |
510 | #define PHYID1_OUI_SHFT 6 | |
511 | #define PHYID2_OUI_MASK 0xfc00 | |
512 | #define PHYID2_OUI_SHFT 10 | |
edf7e5ec | 513 | #define PHYID2_MODEL_MASK 0x03f0 |
9f3f7910 AA |
514 | #define PHY_MODEL_REALTEK_8211 0x0110 |
515 | #define PHY_REV_MASK 0x0001 | |
516 | #define PHY_REV_REALTEK_8211B 0x0000 | |
517 | #define PHY_REV_REALTEK_8211C 0x0001 | |
518 | #define PHY_MODEL_REALTEK_8201 0x0200 | |
519 | #define PHY_MODEL_MARVELL_E3016 0x0220 | |
edf7e5ec | 520 | #define PHY_MARVELL_E3016_INITMASK 0x0300 |
14a67f3c AA |
521 | #define PHY_CICADA_INIT1 0x0f000 |
522 | #define PHY_CICADA_INIT2 0x0e00 | |
523 | #define PHY_CICADA_INIT3 0x01000 | |
524 | #define PHY_CICADA_INIT4 0x0200 | |
525 | #define PHY_CICADA_INIT5 0x0004 | |
526 | #define PHY_CICADA_INIT6 0x02000 | |
d215d8a2 AA |
527 | #define PHY_VITESSE_INIT_REG1 0x1f |
528 | #define PHY_VITESSE_INIT_REG2 0x10 | |
529 | #define PHY_VITESSE_INIT_REG3 0x11 | |
530 | #define PHY_VITESSE_INIT_REG4 0x12 | |
531 | #define PHY_VITESSE_INIT_MSK1 0xc | |
532 | #define PHY_VITESSE_INIT_MSK2 0x0180 | |
533 | #define PHY_VITESSE_INIT1 0x52b5 | |
534 | #define PHY_VITESSE_INIT2 0xaf8a | |
535 | #define PHY_VITESSE_INIT3 0x8 | |
536 | #define PHY_VITESSE_INIT4 0x8f8a | |
537 | #define PHY_VITESSE_INIT5 0xaf86 | |
538 | #define PHY_VITESSE_INIT6 0x8f86 | |
539 | #define PHY_VITESSE_INIT7 0xaf82 | |
540 | #define PHY_VITESSE_INIT8 0x0100 | |
541 | #define PHY_VITESSE_INIT9 0x8f82 | |
542 | #define PHY_VITESSE_INIT10 0x0 | |
c5e3ae88 AA |
543 | #define PHY_REALTEK_INIT_REG1 0x1f |
544 | #define PHY_REALTEK_INIT_REG2 0x19 | |
545 | #define PHY_REALTEK_INIT_REG3 0x13 | |
9f3f7910 AA |
546 | #define PHY_REALTEK_INIT_REG4 0x14 |
547 | #define PHY_REALTEK_INIT_REG5 0x18 | |
548 | #define PHY_REALTEK_INIT_REG6 0x11 | |
22ae03a1 | 549 | #define PHY_REALTEK_INIT_REG7 0x01 |
c5e3ae88 AA |
550 | #define PHY_REALTEK_INIT1 0x0000 |
551 | #define PHY_REALTEK_INIT2 0x8e00 | |
552 | #define PHY_REALTEK_INIT3 0x0001 | |
553 | #define PHY_REALTEK_INIT4 0xad17 | |
9f3f7910 AA |
554 | #define PHY_REALTEK_INIT5 0xfb54 |
555 | #define PHY_REALTEK_INIT6 0xf5c7 | |
556 | #define PHY_REALTEK_INIT7 0x1000 | |
557 | #define PHY_REALTEK_INIT8 0x0003 | |
22ae03a1 AA |
558 | #define PHY_REALTEK_INIT9 0x0008 |
559 | #define PHY_REALTEK_INIT10 0x0005 | |
560 | #define PHY_REALTEK_INIT11 0x0200 | |
9f3f7910 | 561 | #define PHY_REALTEK_INIT_MSK1 0x0003 |
d215d8a2 | 562 | |
1da177e4 LT |
563 | #define PHY_GIGABIT 0x0100 |
564 | ||
565 | #define PHY_TIMEOUT 0x1 | |
566 | #define PHY_ERROR 0x2 | |
567 | ||
568 | #define PHY_100 0x1 | |
569 | #define PHY_1000 0x2 | |
570 | #define PHY_HALF 0x100 | |
571 | ||
eb91f61b AA |
572 | #define NV_PAUSEFRAME_RX_CAPABLE 0x0001 |
573 | #define NV_PAUSEFRAME_TX_CAPABLE 0x0002 | |
574 | #define NV_PAUSEFRAME_RX_ENABLE 0x0004 | |
575 | #define NV_PAUSEFRAME_TX_ENABLE 0x0008 | |
b6d0773f AA |
576 | #define NV_PAUSEFRAME_RX_REQ 0x0010 |
577 | #define NV_PAUSEFRAME_TX_REQ 0x0020 | |
578 | #define NV_PAUSEFRAME_AUTONEG 0x0040 | |
1da177e4 | 579 | |
d33a73c8 AA |
580 | /* MSI/MSI-X defines */ |
581 | #define NV_MSI_X_MAX_VECTORS 8 | |
582 | #define NV_MSI_X_VECTORS_MASK 0x000f | |
583 | #define NV_MSI_CAPABLE 0x0010 | |
584 | #define NV_MSI_X_CAPABLE 0x0020 | |
585 | #define NV_MSI_ENABLED 0x0040 | |
586 | #define NV_MSI_X_ENABLED 0x0080 | |
587 | ||
588 | #define NV_MSI_X_VECTOR_ALL 0x0 | |
589 | #define NV_MSI_X_VECTOR_RX 0x0 | |
590 | #define NV_MSI_X_VECTOR_TX 0x1 | |
591 | #define NV_MSI_X_VECTOR_OTHER 0x2 | |
1da177e4 | 592 | |
b6e4405b AA |
593 | #define NV_MSI_PRIV_OFFSET 0x68 |
594 | #define NV_MSI_PRIV_VALUE 0xffffffff | |
595 | ||
b2976d23 AA |
596 | #define NV_RESTART_TX 0x1 |
597 | #define NV_RESTART_RX 0x2 | |
598 | ||
3b446c3e AA |
599 | #define NV_TX_LIMIT_COUNT 16 |
600 | ||
4145ade2 AA |
601 | #define NV_DYNAMIC_THRESHOLD 4 |
602 | #define NV_DYNAMIC_MAX_QUIET_COUNT 2048 | |
603 | ||
52da3578 AA |
604 | /* statistics */ |
605 | struct nv_ethtool_str { | |
606 | char name[ETH_GSTRING_LEN]; | |
607 | }; | |
608 | ||
609 | static const struct nv_ethtool_str nv_estats_str[] = { | |
674aee3b | 610 | { "tx_bytes" }, /* includes Ethernet FCS CRC */ |
52da3578 AA |
611 | { "tx_zero_rexmt" }, |
612 | { "tx_one_rexmt" }, | |
613 | { "tx_many_rexmt" }, | |
614 | { "tx_late_collision" }, | |
615 | { "tx_fifo_errors" }, | |
616 | { "tx_carrier_errors" }, | |
617 | { "tx_excess_deferral" }, | |
618 | { "tx_retry_error" }, | |
52da3578 AA |
619 | { "rx_frame_error" }, |
620 | { "rx_extra_byte" }, | |
621 | { "rx_late_collision" }, | |
622 | { "rx_runt" }, | |
623 | { "rx_frame_too_long" }, | |
624 | { "rx_over_errors" }, | |
625 | { "rx_crc_errors" }, | |
626 | { "rx_frame_align_error" }, | |
627 | { "rx_length_error" }, | |
628 | { "rx_unicast" }, | |
629 | { "rx_multicast" }, | |
630 | { "rx_broadcast" }, | |
57fff698 AA |
631 | { "rx_packets" }, |
632 | { "rx_errors_total" }, | |
633 | { "tx_errors_total" }, | |
634 | ||
635 | /* version 2 stats */ | |
636 | { "tx_deferral" }, | |
637 | { "tx_packets" }, | |
674aee3b | 638 | { "rx_bytes" }, /* includes Ethernet FCS CRC */ |
57fff698 | 639 | { "tx_pause" }, |
52da3578 | 640 | { "rx_pause" }, |
9c662435 AA |
641 | { "rx_drop_frame" }, |
642 | ||
643 | /* version 3 stats */ | |
644 | { "tx_unicast" }, | |
645 | { "tx_multicast" }, | |
646 | { "tx_broadcast" } | |
52da3578 AA |
647 | }; |
648 | ||
649 | struct nv_ethtool_stats { | |
674aee3b | 650 | u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */ |
52da3578 AA |
651 | u64 tx_zero_rexmt; |
652 | u64 tx_one_rexmt; | |
653 | u64 tx_many_rexmt; | |
654 | u64 tx_late_collision; | |
655 | u64 tx_fifo_errors; | |
656 | u64 tx_carrier_errors; | |
657 | u64 tx_excess_deferral; | |
658 | u64 tx_retry_error; | |
52da3578 AA |
659 | u64 rx_frame_error; |
660 | u64 rx_extra_byte; | |
661 | u64 rx_late_collision; | |
662 | u64 rx_runt; | |
663 | u64 rx_frame_too_long; | |
664 | u64 rx_over_errors; | |
665 | u64 rx_crc_errors; | |
666 | u64 rx_frame_align_error; | |
667 | u64 rx_length_error; | |
668 | u64 rx_unicast; | |
669 | u64 rx_multicast; | |
670 | u64 rx_broadcast; | |
674aee3b | 671 | u64 rx_packets; /* should be ifconfig->rx_packets */ |
57fff698 AA |
672 | u64 rx_errors_total; |
673 | u64 tx_errors_total; | |
674 | ||
675 | /* version 2 stats */ | |
676 | u64 tx_deferral; | |
674aee3b | 677 | u64 tx_packets; /* should be ifconfig->tx_packets */ |
678 | u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */ | |
57fff698 | 679 | u64 tx_pause; |
52da3578 AA |
680 | u64 rx_pause; |
681 | u64 rx_drop_frame; | |
9c662435 AA |
682 | |
683 | /* version 3 stats */ | |
684 | u64 tx_unicast; | |
685 | u64 tx_multicast; | |
686 | u64 tx_broadcast; | |
52da3578 AA |
687 | }; |
688 | ||
9c662435 AA |
689 | #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64)) |
690 | #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3) | |
57fff698 AA |
691 | #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6) |
692 | ||
9589c77a AA |
693 | /* diagnostics */ |
694 | #define NV_TEST_COUNT_BASE 3 | |
695 | #define NV_TEST_COUNT_EXTENDED 4 | |
696 | ||
697 | static const struct nv_ethtool_str nv_etests_str[] = { | |
698 | { "link (online/offline)" }, | |
699 | { "register (offline) " }, | |
700 | { "interrupt (offline) " }, | |
701 | { "loopback (offline) " } | |
702 | }; | |
703 | ||
704 | struct register_test { | |
5bb7ea26 AV |
705 | __u32 reg; |
706 | __u32 mask; | |
9589c77a AA |
707 | }; |
708 | ||
709 | static const struct register_test nv_registers_test[] = { | |
710 | { NvRegUnknownSetupReg6, 0x01 }, | |
711 | { NvRegMisc1, 0x03c }, | |
712 | { NvRegOffloadConfig, 0x03ff }, | |
713 | { NvRegMulticastAddrA, 0xffffffff }, | |
95d161cb | 714 | { NvRegTxWatermark, 0x0ff }, |
9589c77a | 715 | { NvRegWakeUpFlags, 0x07777 }, |
78aea4fc | 716 | { 0, 0 } |
9589c77a AA |
717 | }; |
718 | ||
761fcd9e AA |
719 | struct nv_skb_map { |
720 | struct sk_buff *skb; | |
721 | dma_addr_t dma; | |
73a37079 ED |
722 | unsigned int dma_len:31; |
723 | unsigned int dma_single:1; | |
3b446c3e AA |
724 | struct ring_desc_ex *first_tx_desc; |
725 | struct nv_skb_map *next_tx_ctx; | |
761fcd9e AA |
726 | }; |
727 | ||
1da177e4 LT |
728 | /* |
729 | * SMP locking: | |
b74ca3a8 | 730 | * All hardware access under netdev_priv(dev)->lock, except the performance |
1da177e4 LT |
731 | * critical parts: |
732 | * - rx is (pseudo-) lockless: it relies on the single-threading provided | |
733 | * by the arch code for interrupts. | |
932ff279 | 734 | * - tx setup is lockless: it relies on netif_tx_lock. Actual submission |
b74ca3a8 | 735 | * needs netdev_priv(dev)->lock :-( |
932ff279 | 736 | * - set_multicast_list: preparation lockless, relies on netif_tx_lock. |
f5d827ae | 737 | * |
738 | * Hardware stats updates are protected by hwstats_lock: | |
739 | * - updated by nv_do_stats_poll (timer). This is meant to avoid | |
740 | * integer wraparound in the NIC stats registers, at low frequency | |
741 | * (0.1 Hz) | |
742 | * - updated by nv_get_ethtool_stats + nv_get_stats64 | |
743 | * | |
744 | * Software stats are accessed only through 64b synchronization points | |
745 | * and are not subject to other synchronization techniques (single | |
746 | * update thread on the TX or RX paths). | |
1da177e4 LT |
747 | */ |
748 | ||
749 | /* in dev: base, irq */ | |
750 | struct fe_priv { | |
751 | spinlock_t lock; | |
752 | ||
bea3348e SH |
753 | struct net_device *dev; |
754 | struct napi_struct napi; | |
755 | ||
f5d827ae | 756 | /* hardware stats are updated in syscall and timer */ |
757 | spinlock_t hwstats_lock; | |
52da3578 | 758 | struct nv_ethtool_stats estats; |
f5d827ae | 759 | |
1da177e4 LT |
760 | int in_shutdown; |
761 | u32 linkspeed; | |
762 | int duplex; | |
763 | int autoneg; | |
764 | int fixed_mode; | |
765 | int phyaddr; | |
766 | int wolenabled; | |
767 | unsigned int phy_oui; | |
edf7e5ec | 768 | unsigned int phy_model; |
9f3f7910 | 769 | unsigned int phy_rev; |
1da177e4 | 770 | u16 gigabit; |
9589c77a | 771 | int intr_test; |
c5cf9101 | 772 | int recover_error; |
4145ade2 | 773 | int quiet_count; |
1da177e4 LT |
774 | |
775 | /* General data: RO fields */ | |
776 | dma_addr_t ring_addr; | |
777 | struct pci_dev *pci_dev; | |
778 | u32 orig_mac[2]; | |
582806be | 779 | u32 events; |
1da177e4 LT |
780 | u32 irqmask; |
781 | u32 desc_ver; | |
8a4ae7f2 | 782 | u32 txrxctl_bits; |
ee407b02 | 783 | u32 vlanctl_bits; |
86a0f043 | 784 | u32 driver_data; |
9f3f7910 | 785 | u32 device_id; |
86a0f043 | 786 | u32 register_size; |
7e680c22 | 787 | u32 mac_in_use; |
cac1c52c AA |
788 | int mgmt_version; |
789 | int mgmt_sema; | |
1da177e4 LT |
790 | |
791 | void __iomem *base; | |
792 | ||
793 | /* rx specific fields. | |
794 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
795 | */ | |
64f26abb | 796 | union ring_type get_rx, put_rx, last_rx; |
761fcd9e | 797 | struct nv_skb_map *get_rx_ctx, *put_rx_ctx; |
a9124ec4 | 798 | struct nv_skb_map *last_rx_ctx; |
761fcd9e AA |
799 | struct nv_skb_map *rx_skb; |
800 | ||
f82a9352 | 801 | union ring_type rx_ring; |
1da177e4 | 802 | unsigned int rx_buf_sz; |
d81c0983 | 803 | unsigned int pkt_limit; |
1da177e4 LT |
804 | struct timer_list oom_kick; |
805 | struct timer_list nic_poll; | |
52da3578 | 806 | struct timer_list stats_poll; |
d33a73c8 | 807 | u32 nic_poll_irq; |
eafa59f6 | 808 | int rx_ring_size; |
1da177e4 | 809 | |
f5d827ae | 810 | /* RX software stats */ |
811 | struct u64_stats_sync swstats_rx_syncp; | |
812 | u64 stat_rx_packets; | |
813 | u64 stat_rx_bytes; /* not always available in HW */ | |
814 | u64 stat_rx_missed_errors; | |
0a1f222d | 815 | u64 stat_rx_dropped; |
f5d827ae | 816 | |
1da177e4 LT |
817 | /* media detection workaround. |
818 | * Locking: Within irq hander or disable_irq+spin_lock(&np->lock); | |
819 | */ | |
820 | int need_linktimer; | |
821 | unsigned long link_timeout; | |
822 | /* | |
823 | * tx specific fields. | |
824 | */ | |
c360f2b5 | 825 | union ring_type get_tx, put_tx, last_tx; |
761fcd9e | 826 | struct nv_skb_map *get_tx_ctx, *put_tx_ctx; |
41b0cd36 | 827 | struct nv_skb_map *last_tx_ctx; |
761fcd9e AA |
828 | struct nv_skb_map *tx_skb; |
829 | ||
f82a9352 | 830 | union ring_type tx_ring; |
1da177e4 | 831 | u32 tx_flags; |
eafa59f6 | 832 | int tx_ring_size; |
3b446c3e AA |
833 | int tx_limit; |
834 | u32 tx_pkts_in_progress; | |
835 | struct nv_skb_map *tx_change_owner; | |
836 | struct nv_skb_map *tx_end_flip; | |
aaa37d2d | 837 | int tx_stop; |
ee407b02 | 838 | |
f5d827ae | 839 | /* TX software stats */ |
840 | struct u64_stats_sync swstats_tx_syncp; | |
841 | u64 stat_tx_packets; /* not always available in HW */ | |
842 | u64 stat_tx_bytes; | |
843 | u64 stat_tx_dropped; | |
844 | ||
d33a73c8 AA |
845 | /* msi/msi-x fields */ |
846 | u32 msi_flags; | |
847 | struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS]; | |
eb91f61b AA |
848 | |
849 | /* flow control */ | |
850 | u32 pause_flags; | |
1a1ca861 TD |
851 | |
852 | /* power saved state */ | |
853 | u32 saved_config_space[NV_PCI_REGSZ_MAX/4]; | |
ddb213f0 YL |
854 | |
855 | /* for different msi-x irq type */ | |
856 | char name_rx[IFNAMSIZ + 3]; /* -rx */ | |
857 | char name_tx[IFNAMSIZ + 3]; /* -tx */ | |
858 | char name_other[IFNAMSIZ + 6]; /* -other */ | |
1da177e4 LT |
859 | }; |
860 | ||
861 | /* | |
862 | * Maximum number of loops until we assume that a bit in the irq mask | |
863 | * is stuck. Overridable with module param. | |
864 | */ | |
4145ade2 | 865 | static int max_interrupt_work = 4; |
1da177e4 | 866 | |
a971c324 AA |
867 | /* |
868 | * Optimization can be either throuput mode or cpu mode | |
f3b197ac | 869 | * |
a971c324 AA |
870 | * Throughput Mode: Every tx and rx packet will generate an interrupt. |
871 | * CPU Mode: Interrupts are controlled by a timer. | |
872 | */ | |
69fe3fd7 AA |
873 | enum { |
874 | NV_OPTIMIZATION_MODE_THROUGHPUT, | |
9e184767 AA |
875 | NV_OPTIMIZATION_MODE_CPU, |
876 | NV_OPTIMIZATION_MODE_DYNAMIC | |
69fe3fd7 | 877 | }; |
9e184767 | 878 | static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC; |
a971c324 AA |
879 | |
880 | /* | |
881 | * Poll interval for timer irq | |
882 | * | |
883 | * This interval determines how frequent an interrupt is generated. | |
884 | * The is value is determined by [(time_in_micro_secs * 100) / (2^10)] | |
885 | * Min = 0, and Max = 65535 | |
886 | */ | |
887 | static int poll_interval = -1; | |
888 | ||
d33a73c8 | 889 | /* |
69fe3fd7 | 890 | * MSI interrupts |
d33a73c8 | 891 | */ |
69fe3fd7 AA |
892 | enum { |
893 | NV_MSI_INT_DISABLED, | |
894 | NV_MSI_INT_ENABLED | |
895 | }; | |
896 | static int msi = NV_MSI_INT_ENABLED; | |
d33a73c8 AA |
897 | |
898 | /* | |
69fe3fd7 | 899 | * MSIX interrupts |
d33a73c8 | 900 | */ |
69fe3fd7 AA |
901 | enum { |
902 | NV_MSIX_INT_DISABLED, | |
903 | NV_MSIX_INT_ENABLED | |
904 | }; | |
39482791 | 905 | static int msix = NV_MSIX_INT_ENABLED; |
69fe3fd7 AA |
906 | |
907 | /* | |
908 | * DMA 64bit | |
909 | */ | |
910 | enum { | |
911 | NV_DMA_64BIT_DISABLED, | |
912 | NV_DMA_64BIT_ENABLED | |
913 | }; | |
914 | static int dma_64bit = NV_DMA_64BIT_ENABLED; | |
d33a73c8 | 915 | |
1ec4f2d3 SN |
916 | /* |
917 | * Debug output control for tx_timeout | |
918 | */ | |
919 | static bool debug_tx_timeout = false; | |
920 | ||
9f3f7910 AA |
921 | /* |
922 | * Crossover Detection | |
923 | * Realtek 8201 phy + some OEM boards do not work properly. | |
924 | */ | |
925 | enum { | |
926 | NV_CROSSOVER_DETECTION_DISABLED, | |
927 | NV_CROSSOVER_DETECTION_ENABLED | |
928 | }; | |
929 | static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED; | |
930 | ||
5a9a8e32 ES |
931 | /* |
932 | * Power down phy when interface is down (persists through reboot; | |
933 | * older Linux and other OSes may not power it up again) | |
934 | */ | |
78aea4fc | 935 | static int phy_power_down; |
5a9a8e32 | 936 | |
1da177e4 LT |
937 | static inline struct fe_priv *get_nvpriv(struct net_device *dev) |
938 | { | |
939 | return netdev_priv(dev); | |
940 | } | |
941 | ||
942 | static inline u8 __iomem *get_hwbase(struct net_device *dev) | |
943 | { | |
ac9c1897 | 944 | return ((struct fe_priv *)netdev_priv(dev))->base; |
1da177e4 LT |
945 | } |
946 | ||
947 | static inline void pci_push(u8 __iomem *base) | |
948 | { | |
949 | /* force out pending posted writes */ | |
950 | readl(base); | |
951 | } | |
952 | ||
953 | static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v) | |
954 | { | |
f82a9352 | 955 | return le32_to_cpu(prd->flaglen) |
1da177e4 LT |
956 | & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2); |
957 | } | |
958 | ||
ee73362c MS |
959 | static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v) |
960 | { | |
f82a9352 | 961 | return le32_to_cpu(prd->flaglen) & LEN_MASK_V2; |
ee73362c MS |
962 | } |
963 | ||
36b30ea9 JG |
964 | static bool nv_optimized(struct fe_priv *np) |
965 | { | |
966 | if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) | |
967 | return false; | |
968 | return true; | |
969 | } | |
970 | ||
1da177e4 | 971 | static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target, |
344d0dce | 972 | int delay, int delaymax) |
1da177e4 LT |
973 | { |
974 | u8 __iomem *base = get_hwbase(dev); | |
975 | ||
976 | pci_push(base); | |
977 | do { | |
978 | udelay(delay); | |
979 | delaymax -= delay; | |
344d0dce | 980 | if (delaymax < 0) |
1da177e4 | 981 | return 1; |
1da177e4 LT |
982 | } while ((readl(base + offset) & mask) != target); |
983 | return 0; | |
984 | } | |
985 | ||
0832b25a AA |
986 | #define NV_SETUP_RX_RING 0x01 |
987 | #define NV_SETUP_TX_RING 0x02 | |
988 | ||
5bb7ea26 AV |
989 | static inline u32 dma_low(dma_addr_t addr) |
990 | { | |
991 | return addr; | |
992 | } | |
993 | ||
994 | static inline u32 dma_high(dma_addr_t addr) | |
995 | { | |
996 | return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */ | |
997 | } | |
998 | ||
0832b25a AA |
999 | static void setup_hw_rings(struct net_device *dev, int rxtx_flags) |
1000 | { | |
1001 | struct fe_priv *np = get_nvpriv(dev); | |
1002 | u8 __iomem *base = get_hwbase(dev); | |
1003 | ||
36b30ea9 | 1004 | if (!nv_optimized(np)) { |
78aea4fc | 1005 | if (rxtx_flags & NV_SETUP_RX_RING) |
5bb7ea26 | 1006 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
78aea4fc | 1007 | if (rxtx_flags & NV_SETUP_TX_RING) |
5bb7ea26 | 1008 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr); |
0832b25a AA |
1009 | } else { |
1010 | if (rxtx_flags & NV_SETUP_RX_RING) { | |
5bb7ea26 AV |
1011 | writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); |
1012 | writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); | |
0832b25a AA |
1013 | } |
1014 | if (rxtx_flags & NV_SETUP_TX_RING) { | |
5bb7ea26 AV |
1015 | writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr); |
1016 | writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh); | |
0832b25a AA |
1017 | } |
1018 | } | |
1019 | } | |
1020 | ||
eafa59f6 AA |
1021 | static void free_rings(struct net_device *dev) |
1022 | { | |
1023 | struct fe_priv *np = get_nvpriv(dev); | |
1024 | ||
36b30ea9 | 1025 | if (!nv_optimized(np)) { |
f82a9352 | 1026 | if (np->rx_ring.orig) |
e8992e40 ZY |
1027 | dma_free_coherent(&np->pci_dev->dev, |
1028 | sizeof(struct ring_desc) * | |
1029 | (np->rx_ring_size + | |
1030 | np->tx_ring_size), | |
1031 | np->rx_ring.orig, np->ring_addr); | |
eafa59f6 AA |
1032 | } else { |
1033 | if (np->rx_ring.ex) | |
e8992e40 ZY |
1034 | dma_free_coherent(&np->pci_dev->dev, |
1035 | sizeof(struct ring_desc_ex) * | |
1036 | (np->rx_ring_size + | |
1037 | np->tx_ring_size), | |
1038 | np->rx_ring.ex, np->ring_addr); | |
eafa59f6 | 1039 | } |
9b03b06b SJ |
1040 | kfree(np->rx_skb); |
1041 | kfree(np->tx_skb); | |
eafa59f6 AA |
1042 | } |
1043 | ||
84b3932b AA |
1044 | static int using_multi_irqs(struct net_device *dev) |
1045 | { | |
1046 | struct fe_priv *np = get_nvpriv(dev); | |
1047 | ||
1048 | if (!(np->msi_flags & NV_MSI_X_ENABLED) || | |
1049 | ((np->msi_flags & NV_MSI_X_ENABLED) && | |
1050 | ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1))) | |
1051 | return 0; | |
1052 | else | |
1053 | return 1; | |
1054 | } | |
1055 | ||
88d7d8b0 AA |
1056 | static void nv_txrx_gate(struct net_device *dev, bool gate) |
1057 | { | |
1058 | struct fe_priv *np = get_nvpriv(dev); | |
1059 | u8 __iomem *base = get_hwbase(dev); | |
1060 | u32 powerstate; | |
1061 | ||
1062 | if (!np->mac_in_use && | |
1063 | (np->driver_data & DEV_HAS_POWER_CNTRL)) { | |
1064 | powerstate = readl(base + NvRegPowerState2); | |
1065 | if (gate) | |
1066 | powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS; | |
1067 | else | |
1068 | powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS; | |
1069 | writel(powerstate, base + NvRegPowerState2); | |
1070 | } | |
1071 | } | |
1072 | ||
84b3932b AA |
1073 | static void nv_enable_irq(struct net_device *dev) |
1074 | { | |
1075 | struct fe_priv *np = get_nvpriv(dev); | |
1076 | ||
1077 | if (!using_multi_irqs(dev)) { | |
1078 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1079 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1080 | else | |
a7475906 | 1081 | enable_irq(np->pci_dev->irq); |
84b3932b AA |
1082 | } else { |
1083 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1084 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1085 | enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static void nv_disable_irq(struct net_device *dev) | |
1090 | { | |
1091 | struct fe_priv *np = get_nvpriv(dev); | |
1092 | ||
1093 | if (!using_multi_irqs(dev)) { | |
1094 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
1095 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector); | |
1096 | else | |
a7475906 | 1097 | disable_irq(np->pci_dev->irq); |
84b3932b AA |
1098 | } else { |
1099 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector); | |
1100 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector); | |
1101 | disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector); | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | /* In MSIX mode, a write to irqmask behaves as XOR */ | |
1106 | static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask) | |
1107 | { | |
1108 | u8 __iomem *base = get_hwbase(dev); | |
1109 | ||
1110 | writel(mask, base + NvRegIrqMask); | |
1111 | } | |
1112 | ||
1113 | static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask) | |
1114 | { | |
1115 | struct fe_priv *np = get_nvpriv(dev); | |
1116 | u8 __iomem *base = get_hwbase(dev); | |
1117 | ||
1118 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
1119 | writel(mask, base + NvRegIrqMask); | |
1120 | } else { | |
1121 | if (np->msi_flags & NV_MSI_ENABLED) | |
1122 | writel(0, base + NvRegMSIIrqMask); | |
1123 | writel(0, base + NvRegIrqMask); | |
1124 | } | |
1125 | } | |
1126 | ||
08d93575 AA |
1127 | static void nv_napi_enable(struct net_device *dev) |
1128 | { | |
08d93575 AA |
1129 | struct fe_priv *np = get_nvpriv(dev); |
1130 | ||
1131 | napi_enable(&np->napi); | |
08d93575 AA |
1132 | } |
1133 | ||
1134 | static void nv_napi_disable(struct net_device *dev) | |
1135 | { | |
08d93575 AA |
1136 | struct fe_priv *np = get_nvpriv(dev); |
1137 | ||
1138 | napi_disable(&np->napi); | |
08d93575 AA |
1139 | } |
1140 | ||
1da177e4 LT |
1141 | #define MII_READ (-1) |
1142 | /* mii_rw: read/write a register on the PHY. | |
1143 | * | |
1144 | * Caller must guarantee serialization | |
1145 | */ | |
1146 | static int mii_rw(struct net_device *dev, int addr, int miireg, int value) | |
1147 | { | |
1148 | u8 __iomem *base = get_hwbase(dev); | |
1149 | u32 reg; | |
1150 | int retval; | |
1151 | ||
eb798428 | 1152 | writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); |
1da177e4 LT |
1153 | |
1154 | reg = readl(base + NvRegMIIControl); | |
1155 | if (reg & NVREG_MIICTL_INUSE) { | |
1156 | writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); | |
1157 | udelay(NV_MIIBUSY_DELAY); | |
1158 | } | |
1159 | ||
1160 | reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; | |
1161 | if (value != MII_READ) { | |
1162 | writel(value, base + NvRegMIIData); | |
1163 | reg |= NVREG_MIICTL_WRITE; | |
1164 | } | |
1165 | writel(reg, base + NvRegMIIControl); | |
1166 | ||
1167 | if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, | |
344d0dce | 1168 | NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) { |
1da177e4 LT |
1169 | retval = -1; |
1170 | } else if (value != MII_READ) { | |
1171 | /* it was a write operation - fewer failures are detectable */ | |
1da177e4 LT |
1172 | retval = 0; |
1173 | } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { | |
1da177e4 LT |
1174 | retval = -1; |
1175 | } else { | |
1176 | retval = readl(base + NvRegMIIData); | |
1da177e4 LT |
1177 | } |
1178 | ||
1179 | return retval; | |
1180 | } | |
1181 | ||
edf7e5ec | 1182 | static int phy_reset(struct net_device *dev, u32 bmcr_setup) |
1da177e4 | 1183 | { |
ac9c1897 | 1184 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1185 | u32 miicontrol; |
1186 | unsigned int tries = 0; | |
1187 | ||
edf7e5ec | 1188 | miicontrol = BMCR_RESET | bmcr_setup; |
78aea4fc | 1189 | if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) |
1da177e4 | 1190 | return -1; |
1da177e4 LT |
1191 | |
1192 | /* wait for 500ms */ | |
1193 | msleep(500); | |
1194 | ||
1195 | /* must wait till reset is deasserted */ | |
1196 | while (miicontrol & BMCR_RESET) { | |
de855b99 | 1197 | usleep_range(10000, 20000); |
1da177e4 LT |
1198 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1199 | /* FIXME: 100 tries seem excessive */ | |
1200 | if (tries++ > 100) | |
1201 | return -1; | |
1202 | } | |
1203 | return 0; | |
1204 | } | |
1205 | ||
c41d41e1 JP |
1206 | static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np) |
1207 | { | |
1208 | static const struct { | |
1209 | int reg; | |
1210 | int init; | |
1211 | } ri[] = { | |
1212 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | |
1213 | { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 }, | |
1214 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 }, | |
1215 | { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 }, | |
1216 | { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 }, | |
1217 | { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 }, | |
1218 | { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 }, | |
1219 | }; | |
1220 | int i; | |
1221 | ||
1222 | for (i = 0; i < ARRAY_SIZE(ri); i++) { | |
cd66328b JP |
1223 | if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) |
1224 | return PHY_ERROR; | |
1225 | } | |
1226 | ||
1227 | return 0; | |
1228 | } | |
1229 | ||
1230 | static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np) | |
1231 | { | |
1232 | u32 reg; | |
1233 | u8 __iomem *base = get_hwbase(dev); | |
1234 | u32 powerstate = readl(base + NvRegPowerState2); | |
1235 | ||
1236 | /* need to perform hw phy reset */ | |
1237 | powerstate |= NVREG_POWERSTATE2_PHY_RESET; | |
1238 | writel(powerstate, base + NvRegPowerState2); | |
1239 | msleep(25); | |
1240 | ||
1241 | powerstate &= ~NVREG_POWERSTATE2_PHY_RESET; | |
1242 | writel(powerstate, base + NvRegPowerState2); | |
1243 | msleep(25); | |
1244 | ||
1245 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); | |
1246 | reg |= PHY_REALTEK_INIT9; | |
1247 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) | |
1248 | return PHY_ERROR; | |
1249 | if (mii_rw(dev, np->phyaddr, | |
1250 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) | |
1251 | return PHY_ERROR; | |
1252 | reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); | |
1253 | if (!(reg & PHY_REALTEK_INIT11)) { | |
1254 | reg |= PHY_REALTEK_INIT11; | |
1255 | if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) | |
1256 | return PHY_ERROR; | |
1257 | } | |
1258 | if (mii_rw(dev, np->phyaddr, | |
1259 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) | |
1260 | return PHY_ERROR; | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | static int init_realtek_8201(struct net_device *dev, struct fe_priv *np) | |
1266 | { | |
1267 | u32 phy_reserved; | |
1268 | ||
1269 | if (np->driver_data & DEV_NEED_PHY_INIT_FIX) { | |
1270 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1271 | PHY_REALTEK_INIT_REG6, MII_READ); | |
1272 | phy_reserved |= PHY_REALTEK_INIT7; | |
1273 | if (mii_rw(dev, np->phyaddr, | |
1274 | PHY_REALTEK_INIT_REG6, phy_reserved)) | |
1275 | return PHY_ERROR; | |
1276 | } | |
1277 | ||
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np) | |
1282 | { | |
1283 | u32 phy_reserved; | |
1284 | ||
1285 | if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
1286 | if (mii_rw(dev, np->phyaddr, | |
1287 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) | |
1288 | return PHY_ERROR; | |
1289 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1290 | PHY_REALTEK_INIT_REG2, MII_READ); | |
1291 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
1292 | phy_reserved |= PHY_REALTEK_INIT3; | |
1293 | if (mii_rw(dev, np->phyaddr, | |
1294 | PHY_REALTEK_INIT_REG2, phy_reserved)) | |
1295 | return PHY_ERROR; | |
1296 | if (mii_rw(dev, np->phyaddr, | |
1297 | PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) | |
c41d41e1 | 1298 | return PHY_ERROR; |
c41d41e1 JP |
1299 | } |
1300 | ||
1301 | return 0; | |
1302 | } | |
1303 | ||
cd66328b JP |
1304 | static int init_cicada(struct net_device *dev, struct fe_priv *np, |
1305 | u32 phyinterface) | |
1306 | { | |
1307 | u32 phy_reserved; | |
1308 | ||
1309 | if (phyinterface & PHY_RGMII) { | |
1310 | phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); | |
1311 | phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2); | |
1312 | phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4); | |
1313 | if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) | |
1314 | return PHY_ERROR; | |
1315 | phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1316 | phy_reserved |= PHY_CICADA_INIT5; | |
1317 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) | |
1318 | return PHY_ERROR; | |
1319 | } | |
1320 | phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); | |
1321 | phy_reserved |= PHY_CICADA_INIT6; | |
1322 | if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) | |
1323 | return PHY_ERROR; | |
1324 | ||
1325 | return 0; | |
1326 | } | |
1327 | ||
1328 | static int init_vitesse(struct net_device *dev, struct fe_priv *np) | |
1329 | { | |
1330 | u32 phy_reserved; | |
1331 | ||
1332 | if (mii_rw(dev, np->phyaddr, | |
1333 | PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) | |
1334 | return PHY_ERROR; | |
1335 | if (mii_rw(dev, np->phyaddr, | |
1336 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) | |
1337 | return PHY_ERROR; | |
1338 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1339 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1340 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1341 | return PHY_ERROR; | |
1342 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1343 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1344 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1345 | phy_reserved |= PHY_VITESSE_INIT3; | |
1346 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1347 | return PHY_ERROR; | |
1348 | if (mii_rw(dev, np->phyaddr, | |
1349 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) | |
1350 | return PHY_ERROR; | |
1351 | if (mii_rw(dev, np->phyaddr, | |
1352 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) | |
1353 | return PHY_ERROR; | |
1354 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1355 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1356 | phy_reserved &= ~PHY_VITESSE_INIT_MSK1; | |
1357 | phy_reserved |= PHY_VITESSE_INIT3; | |
1358 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1359 | return PHY_ERROR; | |
1360 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1361 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1362 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1363 | return PHY_ERROR; | |
1364 | if (mii_rw(dev, np->phyaddr, | |
1365 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) | |
1366 | return PHY_ERROR; | |
1367 | if (mii_rw(dev, np->phyaddr, | |
1368 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) | |
1369 | return PHY_ERROR; | |
1370 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1371 | PHY_VITESSE_INIT_REG4, MII_READ); | |
1372 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) | |
1373 | return PHY_ERROR; | |
1374 | phy_reserved = mii_rw(dev, np->phyaddr, | |
1375 | PHY_VITESSE_INIT_REG3, MII_READ); | |
1376 | phy_reserved &= ~PHY_VITESSE_INIT_MSK2; | |
1377 | phy_reserved |= PHY_VITESSE_INIT8; | |
1378 | if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) | |
1379 | return PHY_ERROR; | |
1380 | if (mii_rw(dev, np->phyaddr, | |
1381 | PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) | |
1382 | return PHY_ERROR; | |
1383 | if (mii_rw(dev, np->phyaddr, | |
1384 | PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) | |
1385 | return PHY_ERROR; | |
1386 | ||
1387 | return 0; | |
1388 | } | |
1389 | ||
1da177e4 LT |
1390 | static int phy_init(struct net_device *dev) |
1391 | { | |
1392 | struct fe_priv *np = get_nvpriv(dev); | |
1393 | u8 __iomem *base = get_hwbase(dev); | |
cd66328b JP |
1394 | u32 phyinterface; |
1395 | u32 mii_status, mii_control, mii_control_1000, reg; | |
1da177e4 | 1396 | |
edf7e5ec AA |
1397 | /* phy errata for E3016 phy */ |
1398 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { | |
1399 | reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); | |
1400 | reg &= ~PHY_MARVELL_E3016_INITMASK; | |
1401 | if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { | |
1d397f36 JP |
1402 | netdev_info(dev, "%s: phy write to errata reg failed\n", |
1403 | pci_name(np->pci_dev)); | |
edf7e5ec AA |
1404 | return PHY_ERROR; |
1405 | } | |
1406 | } | |
c5e3ae88 | 1407 | if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1408 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1409 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
cd66328b | 1410 | if (init_realtek_8211b(dev, np)) { |
1d397f36 JP |
1411 | netdev_info(dev, "%s: phy init failed\n", |
1412 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1413 | return PHY_ERROR; |
1414 | } | |
cd66328b JP |
1415 | } else if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1416 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1417 | if (init_realtek_8211c(dev, np)) { | |
1d397f36 JP |
1418 | netdev_info(dev, "%s: phy init failed\n", |
1419 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1420 | return PHY_ERROR; |
1421 | } | |
cd66328b JP |
1422 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1423 | if (init_realtek_8201(dev, np)) { | |
1d397f36 JP |
1424 | netdev_info(dev, "%s: phy init failed\n", |
1425 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1426 | return PHY_ERROR; |
1427 | } | |
1428 | } | |
c5e3ae88 | 1429 | } |
edf7e5ec | 1430 | |
1da177e4 LT |
1431 | /* set advertise register */ |
1432 | reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
cd66328b JP |
1433 | reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
1434 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
1435 | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); | |
1da177e4 | 1436 | if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { |
1d397f36 JP |
1437 | netdev_info(dev, "%s: phy write to advertise failed\n", |
1438 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1439 | return PHY_ERROR; |
1440 | } | |
1441 | ||
1442 | /* get phy interface type */ | |
1443 | phyinterface = readl(base + NvRegPhyInterface); | |
1444 | ||
1445 | /* see if gigabit phy */ | |
1446 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
1447 | if (mii_status & PHY_GIGABIT) { | |
1448 | np->gigabit = PHY_GIGABIT; | |
cd66328b JP |
1449 | mii_control_1000 = mii_rw(dev, np->phyaddr, |
1450 | MII_CTRL1000, MII_READ); | |
1da177e4 LT |
1451 | mii_control_1000 &= ~ADVERTISE_1000HALF; |
1452 | if (phyinterface & PHY_RGMII) | |
1453 | mii_control_1000 |= ADVERTISE_1000FULL; | |
1454 | else | |
1455 | mii_control_1000 &= ~ADVERTISE_1000FULL; | |
1456 | ||
eb91f61b | 1457 | if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { |
1d397f36 JP |
1458 | netdev_info(dev, "%s: phy init failed\n", |
1459 | pci_name(np->pci_dev)); | |
1da177e4 LT |
1460 | return PHY_ERROR; |
1461 | } | |
78aea4fc | 1462 | } else |
1da177e4 LT |
1463 | np->gigabit = 0; |
1464 | ||
edf7e5ec AA |
1465 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
1466 | mii_control |= BMCR_ANENABLE; | |
1467 | ||
22ae03a1 AA |
1468 | if (np->phy_oui == PHY_OUI_REALTEK && |
1469 | np->phy_model == PHY_MODEL_REALTEK_8211 && | |
1470 | np->phy_rev == PHY_REV_REALTEK_8211C) { | |
1471 | /* start autoneg since we already performed hw reset above */ | |
1472 | mii_control |= BMCR_ANRESTART; | |
1473 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { | |
1d397f36 JP |
1474 | netdev_info(dev, "%s: phy init failed\n", |
1475 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1476 | return PHY_ERROR; |
1477 | } | |
1478 | } else { | |
1479 | /* reset the phy | |
1480 | * (certain phys need bmcr to be setup with reset) | |
1481 | */ | |
1482 | if (phy_reset(dev, mii_control)) { | |
1d397f36 JP |
1483 | netdev_info(dev, "%s: phy reset failed\n", |
1484 | pci_name(np->pci_dev)); | |
22ae03a1 AA |
1485 | return PHY_ERROR; |
1486 | } | |
1da177e4 LT |
1487 | } |
1488 | ||
1489 | /* phy vendor specific configuration */ | |
d46781bc | 1490 | if (np->phy_oui == PHY_OUI_CICADA) { |
cd66328b | 1491 | if (init_cicada(dev, np, phyinterface)) { |
1d397f36 JP |
1492 | netdev_info(dev, "%s: phy init failed\n", |
1493 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1494 | return PHY_ERROR; |
1495 | } | |
cd66328b JP |
1496 | } else if (np->phy_oui == PHY_OUI_VITESSE) { |
1497 | if (init_vitesse(dev, np)) { | |
1d397f36 JP |
1498 | netdev_info(dev, "%s: phy init failed\n", |
1499 | pci_name(np->pci_dev)); | |
d215d8a2 AA |
1500 | return PHY_ERROR; |
1501 | } | |
cd66328b | 1502 | } else if (np->phy_oui == PHY_OUI_REALTEK) { |
9f3f7910 AA |
1503 | if (np->phy_model == PHY_MODEL_REALTEK_8211 && |
1504 | np->phy_rev == PHY_REV_REALTEK_8211B) { | |
1505 | /* reset could have cleared these out, set them back */ | |
cd66328b JP |
1506 | if (init_realtek_8211b(dev, np)) { |
1507 | netdev_info(dev, "%s: phy init failed\n", | |
1508 | pci_name(np->pci_dev)); | |
9f3f7910 | 1509 | return PHY_ERROR; |
9f3f7910 | 1510 | } |
cd66328b JP |
1511 | } else if (np->phy_model == PHY_MODEL_REALTEK_8201) { |
1512 | if (init_realtek_8201(dev, np) || | |
1513 | init_realtek_8201_cross(dev, np)) { | |
1514 | netdev_info(dev, "%s: phy init failed\n", | |
1515 | pci_name(np->pci_dev)); | |
1516 | return PHY_ERROR; | |
9f3f7910 | 1517 | } |
c5e3ae88 AA |
1518 | } |
1519 | } | |
1520 | ||
25985edc | 1521 | /* some phys clear out pause advertisement on reset, set it back */ |
eb91f61b | 1522 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); |
1da177e4 | 1523 | |
cb52deba | 1524 | /* restart auto negotiation, power down phy */ |
1da177e4 | 1525 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
5a9a8e32 | 1526 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); |
78aea4fc | 1527 | if (phy_power_down) |
5a9a8e32 | 1528 | mii_control |= BMCR_PDOWN; |
78aea4fc | 1529 | if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) |
1da177e4 | 1530 | return PHY_ERROR; |
1da177e4 LT |
1531 | |
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | static void nv_start_rx(struct net_device *dev) | |
1536 | { | |
ac9c1897 | 1537 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1538 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1539 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 | 1540 | |
1da177e4 | 1541 | /* Already running? Stop it. */ |
f35723ec AA |
1542 | if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { |
1543 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1544 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1545 | pci_push(base); |
1546 | } | |
1547 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
1548 | pci_push(base); | |
78aea4fc SJ |
1549 | rx_ctrl |= NVREG_RCVCTL_START; |
1550 | if (np->mac_in_use) | |
f35723ec AA |
1551 | rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; |
1552 | writel(rx_ctrl, base + NvRegReceiverControl); | |
1da177e4 LT |
1553 | pci_push(base); |
1554 | } | |
1555 | ||
1556 | static void nv_stop_rx(struct net_device *dev) | |
1557 | { | |
f35723ec | 1558 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1559 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1560 | u32 rx_ctrl = readl(base + NvRegReceiverControl); |
1da177e4 | 1561 | |
f35723ec AA |
1562 | if (!np->mac_in_use) |
1563 | rx_ctrl &= ~NVREG_RCVCTL_START; | |
1564 | else | |
1565 | rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; | |
1566 | writel(rx_ctrl, base + NvRegReceiverControl); | |
344d0dce JP |
1567 | if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, |
1568 | NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX)) | |
1d397f36 JP |
1569 | netdev_info(dev, "%s: ReceiverStatus remained busy\n", |
1570 | __func__); | |
1da177e4 LT |
1571 | |
1572 | udelay(NV_RXSTOP_DELAY2); | |
f35723ec AA |
1573 | if (!np->mac_in_use) |
1574 | writel(0, base + NvRegLinkSpeed); | |
1da177e4 LT |
1575 | } |
1576 | ||
1577 | static void nv_start_tx(struct net_device *dev) | |
1578 | { | |
f35723ec | 1579 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1580 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1581 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 | 1582 | |
f35723ec AA |
1583 | tx_ctrl |= NVREG_XMITCTL_START; |
1584 | if (np->mac_in_use) | |
1585 | tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; | |
1586 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
1da177e4 LT |
1587 | pci_push(base); |
1588 | } | |
1589 | ||
1590 | static void nv_stop_tx(struct net_device *dev) | |
1591 | { | |
f35723ec | 1592 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1593 | u8 __iomem *base = get_hwbase(dev); |
f35723ec | 1594 | u32 tx_ctrl = readl(base + NvRegTransmitterControl); |
1da177e4 | 1595 | |
f35723ec AA |
1596 | if (!np->mac_in_use) |
1597 | tx_ctrl &= ~NVREG_XMITCTL_START; | |
1598 | else | |
1599 | tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; | |
1600 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
344d0dce JP |
1601 | if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, |
1602 | NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX)) | |
1d397f36 JP |
1603 | netdev_info(dev, "%s: TransmitterStatus remained busy\n", |
1604 | __func__); | |
1da177e4 LT |
1605 | |
1606 | udelay(NV_TXSTOP_DELAY2); | |
f35723ec AA |
1607 | if (!np->mac_in_use) |
1608 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, | |
1609 | base + NvRegTransmitPoll); | |
1da177e4 LT |
1610 | } |
1611 | ||
36b30ea9 JG |
1612 | static void nv_start_rxtx(struct net_device *dev) |
1613 | { | |
1614 | nv_start_rx(dev); | |
1615 | nv_start_tx(dev); | |
1616 | } | |
1617 | ||
1618 | static void nv_stop_rxtx(struct net_device *dev) | |
1619 | { | |
1620 | nv_stop_rx(dev); | |
1621 | nv_stop_tx(dev); | |
1622 | } | |
1623 | ||
1da177e4 LT |
1624 | static void nv_txrx_reset(struct net_device *dev) |
1625 | { | |
ac9c1897 | 1626 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
1627 | u8 __iomem *base = get_hwbase(dev); |
1628 | ||
8a4ae7f2 | 1629 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1630 | pci_push(base); |
1631 | udelay(NV_TXRX_RESET_DELAY); | |
8a4ae7f2 | 1632 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1da177e4 LT |
1633 | pci_push(base); |
1634 | } | |
1635 | ||
86a0f043 AA |
1636 | static void nv_mac_reset(struct net_device *dev) |
1637 | { | |
1638 | struct fe_priv *np = netdev_priv(dev); | |
1639 | u8 __iomem *base = get_hwbase(dev); | |
4e84f9b1 | 1640 | u32 temp1, temp2, temp3; |
86a0f043 | 1641 | |
86a0f043 AA |
1642 | writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); |
1643 | pci_push(base); | |
4e84f9b1 AA |
1644 | |
1645 | /* save registers since they will be cleared on reset */ | |
1646 | temp1 = readl(base + NvRegMacAddrA); | |
1647 | temp2 = readl(base + NvRegMacAddrB); | |
1648 | temp3 = readl(base + NvRegTransmitPoll); | |
1649 | ||
86a0f043 AA |
1650 | writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); |
1651 | pci_push(base); | |
1652 | udelay(NV_MAC_RESET_DELAY); | |
1653 | writel(0, base + NvRegMacReset); | |
1654 | pci_push(base); | |
1655 | udelay(NV_MAC_RESET_DELAY); | |
4e84f9b1 AA |
1656 | |
1657 | /* restore saved registers */ | |
1658 | writel(temp1, base + NvRegMacAddrA); | |
1659 | writel(temp2, base + NvRegMacAddrB); | |
1660 | writel(temp3, base + NvRegTransmitPoll); | |
1661 | ||
86a0f043 AA |
1662 | writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); |
1663 | pci_push(base); | |
1664 | } | |
1665 | ||
f5d827ae | 1666 | /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */ |
1667 | static void nv_update_stats(struct net_device *dev) | |
57fff698 AA |
1668 | { |
1669 | struct fe_priv *np = netdev_priv(dev); | |
1670 | u8 __iomem *base = get_hwbase(dev); | |
1671 | ||
f5d827ae | 1672 | /* If it happens that this is run in top-half context, then |
1673 | * replace the spin_lock of hwstats_lock with | |
1674 | * spin_lock_irqsave() in calling functions. */ | |
1675 | WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half"); | |
1676 | assert_spin_locked(&np->hwstats_lock); | |
1677 | ||
1678 | /* query hardware */ | |
57fff698 AA |
1679 | np->estats.tx_bytes += readl(base + NvRegTxCnt); |
1680 | np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt); | |
1681 | np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt); | |
1682 | np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt); | |
1683 | np->estats.tx_late_collision += readl(base + NvRegTxLateCol); | |
1684 | np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow); | |
1685 | np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier); | |
1686 | np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef); | |
1687 | np->estats.tx_retry_error += readl(base + NvRegTxRetryErr); | |
1688 | np->estats.rx_frame_error += readl(base + NvRegRxFrameErr); | |
1689 | np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte); | |
1690 | np->estats.rx_late_collision += readl(base + NvRegRxLateCol); | |
1691 | np->estats.rx_runt += readl(base + NvRegRxRunt); | |
1692 | np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong); | |
1693 | np->estats.rx_over_errors += readl(base + NvRegRxOverflow); | |
1694 | np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr); | |
1695 | np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr); | |
1696 | np->estats.rx_length_error += readl(base + NvRegRxLenErr); | |
1697 | np->estats.rx_unicast += readl(base + NvRegRxUnicast); | |
1698 | np->estats.rx_multicast += readl(base + NvRegRxMulticast); | |
1699 | np->estats.rx_broadcast += readl(base + NvRegRxBroadcast); | |
1700 | np->estats.rx_packets = | |
1701 | np->estats.rx_unicast + | |
1702 | np->estats.rx_multicast + | |
1703 | np->estats.rx_broadcast; | |
1704 | np->estats.rx_errors_total = | |
1705 | np->estats.rx_crc_errors + | |
1706 | np->estats.rx_over_errors + | |
1707 | np->estats.rx_frame_error + | |
1708 | (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) + | |
1709 | np->estats.rx_late_collision + | |
1710 | np->estats.rx_runt + | |
1711 | np->estats.rx_frame_too_long; | |
1712 | np->estats.tx_errors_total = | |
1713 | np->estats.tx_late_collision + | |
1714 | np->estats.tx_fifo_errors + | |
1715 | np->estats.tx_carrier_errors + | |
1716 | np->estats.tx_excess_deferral + | |
1717 | np->estats.tx_retry_error; | |
1718 | ||
1719 | if (np->driver_data & DEV_HAS_STATISTICS_V2) { | |
1720 | np->estats.tx_deferral += readl(base + NvRegTxDef); | |
1721 | np->estats.tx_packets += readl(base + NvRegTxFrame); | |
1722 | np->estats.rx_bytes += readl(base + NvRegRxCnt); | |
1723 | np->estats.tx_pause += readl(base + NvRegTxPause); | |
1724 | np->estats.rx_pause += readl(base + NvRegRxPause); | |
1725 | np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame); | |
0bdfea8b | 1726 | np->estats.rx_errors_total += np->estats.rx_drop_frame; |
57fff698 | 1727 | } |
9c662435 AA |
1728 | |
1729 | if (np->driver_data & DEV_HAS_STATISTICS_V3) { | |
1730 | np->estats.tx_unicast += readl(base + NvRegTxUnicast); | |
1731 | np->estats.tx_multicast += readl(base + NvRegTxMulticast); | |
1732 | np->estats.tx_broadcast += readl(base + NvRegTxBroadcast); | |
1733 | } | |
57fff698 AA |
1734 | } |
1735 | ||
1da177e4 | 1736 | /* |
f5d827ae | 1737 | * nv_get_stats64: dev->ndo_get_stats64 function |
1da177e4 LT |
1738 | * Get latest stats value from the nic. |
1739 | * Called with read_lock(&dev_base_lock) held for read - | |
1740 | * only synchronized against unregister_netdevice. | |
1741 | */ | |
bc1f4470 | 1742 | static void |
f5d827ae | 1743 | nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage) |
1744 | __acquires(&netdev_priv(dev)->hwstats_lock) | |
1745 | __releases(&netdev_priv(dev)->hwstats_lock) | |
1da177e4 | 1746 | { |
ac9c1897 | 1747 | struct fe_priv *np = netdev_priv(dev); |
f5d827ae | 1748 | unsigned int syncp_start; |
1749 | ||
1750 | /* | |
1751 | * Note: because HW stats are not always available and for | |
1752 | * consistency reasons, the following ifconfig stats are | |
1753 | * managed by software: rx_bytes, tx_bytes, rx_packets and | |
1754 | * tx_packets. The related hardware stats reported by ethtool | |
1755 | * should be equivalent to these ifconfig stats, with 4 | |
1756 | * additional bytes per packet (Ethernet FCS CRC), except for | |
1757 | * tx_packets when TSO kicks in. | |
1758 | */ | |
1759 | ||
1760 | /* software stats */ | |
1761 | do { | |
57a7744e | 1762 | syncp_start = u64_stats_fetch_begin_irq(&np->swstats_rx_syncp); |
f5d827ae | 1763 | storage->rx_packets = np->stat_rx_packets; |
1764 | storage->rx_bytes = np->stat_rx_bytes; | |
0a1f222d | 1765 | storage->rx_dropped = np->stat_rx_dropped; |
f5d827ae | 1766 | storage->rx_missed_errors = np->stat_rx_missed_errors; |
57a7744e | 1767 | } while (u64_stats_fetch_retry_irq(&np->swstats_rx_syncp, syncp_start)); |
f5d827ae | 1768 | |
1769 | do { | |
57a7744e | 1770 | syncp_start = u64_stats_fetch_begin_irq(&np->swstats_tx_syncp); |
f5d827ae | 1771 | storage->tx_packets = np->stat_tx_packets; |
1772 | storage->tx_bytes = np->stat_tx_bytes; | |
1773 | storage->tx_dropped = np->stat_tx_dropped; | |
57a7744e | 1774 | } while (u64_stats_fetch_retry_irq(&np->swstats_tx_syncp, syncp_start)); |
1da177e4 | 1775 | |
21828163 | 1776 | /* If the nic supports hw counters then retrieve latest values */ |
f5d827ae | 1777 | if (np->driver_data & DEV_HAS_STATISTICS_V123) { |
1778 | spin_lock_bh(&np->hwstats_lock); | |
21828163 | 1779 | |
f5d827ae | 1780 | nv_update_stats(dev); |
1781 | ||
1782 | /* generic stats */ | |
1783 | storage->rx_errors = np->estats.rx_errors_total; | |
1784 | storage->tx_errors = np->estats.tx_errors_total; | |
1785 | ||
1786 | /* meaningful only when NIC supports stats v3 */ | |
1787 | storage->multicast = np->estats.rx_multicast; | |
1788 | ||
1789 | /* detailed rx_errors */ | |
1790 | storage->rx_length_errors = np->estats.rx_length_error; | |
1791 | storage->rx_over_errors = np->estats.rx_over_errors; | |
1792 | storage->rx_crc_errors = np->estats.rx_crc_errors; | |
1793 | storage->rx_frame_errors = np->estats.rx_frame_align_error; | |
1794 | storage->rx_fifo_errors = np->estats.rx_drop_frame; | |
674aee3b | 1795 | |
f5d827ae | 1796 | /* detailed tx_errors */ |
1797 | storage->tx_carrier_errors = np->estats.tx_carrier_errors; | |
1798 | storage->tx_fifo_errors = np->estats.tx_fifo_errors; | |
1799 | ||
1800 | spin_unlock_bh(&np->hwstats_lock); | |
21828163 | 1801 | } |
1da177e4 LT |
1802 | } |
1803 | ||
1804 | /* | |
1805 | * nv_alloc_rx: fill rx ring entries. | |
1806 | * Return 1 if the allocations for the skbs failed and the | |
1807 | * rx engine is without Available descriptors | |
1808 | */ | |
1809 | static int nv_alloc_rx(struct net_device *dev) | |
1810 | { | |
ac9c1897 | 1811 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 1812 | struct ring_desc *less_rx; |
1da177e4 | 1813 | |
86b22b0d | 1814 | less_rx = np->get_rx.orig; |
64f26abb | 1815 | if (less_rx-- == np->rx_ring.orig) |
86b22b0d | 1816 | less_rx = np->last_rx.orig; |
761fcd9e | 1817 | |
86b22b0d | 1818 | while (np->put_rx.orig != less_rx) { |
dae2e9f4 | 1819 | struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD); |
ac0b715e | 1820 | if (likely(skb)) { |
86b22b0d | 1821 | np->put_rx_ctx->skb = skb; |
7598b349 | 1822 | np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev, |
4305b541 | 1823 | skb->data, |
8b5be268 | 1824 | skb_tailroom(skb), |
7598b349 | 1825 | DMA_FROM_DEVICE); |
39e50d96 ZY |
1826 | if (unlikely(dma_mapping_error(&np->pci_dev->dev, |
1827 | np->put_rx_ctx->dma))) { | |
612a7c4e LF |
1828 | kfree_skb(skb); |
1829 | goto packet_dropped; | |
1830 | } | |
8b5be268 | 1831 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
86b22b0d AA |
1832 | np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma); |
1833 | wmb(); | |
1834 | np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL); | |
b01867cb | 1835 | if (unlikely(np->put_rx.orig++ == np->last_rx.orig)) |
64f26abb | 1836 | np->put_rx.orig = np->rx_ring.orig; |
b01867cb | 1837 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
a9124ec4 | 1838 | np->put_rx_ctx = np->rx_skb; |
0a1f222d | 1839 | } else { |
612a7c4e | 1840 | packet_dropped: |
0a1f222d | 1841 | u64_stats_update_begin(&np->swstats_rx_syncp); |
1842 | np->stat_rx_dropped++; | |
1843 | u64_stats_update_end(&np->swstats_rx_syncp); | |
86b22b0d | 1844 | return 1; |
0a1f222d | 1845 | } |
86b22b0d AA |
1846 | } |
1847 | return 0; | |
1848 | } | |
1849 | ||
1850 | static int nv_alloc_rx_optimized(struct net_device *dev) | |
1851 | { | |
1852 | struct fe_priv *np = netdev_priv(dev); | |
78aea4fc | 1853 | struct ring_desc_ex *less_rx; |
86b22b0d AA |
1854 | |
1855 | less_rx = np->get_rx.ex; | |
64f26abb | 1856 | if (less_rx-- == np->rx_ring.ex) |
86b22b0d | 1857 | less_rx = np->last_rx.ex; |
761fcd9e | 1858 | |
86b22b0d | 1859 | while (np->put_rx.ex != less_rx) { |
dae2e9f4 | 1860 | struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD); |
ac0b715e | 1861 | if (likely(skb)) { |
761fcd9e | 1862 | np->put_rx_ctx->skb = skb; |
7598b349 | 1863 | np->put_rx_ctx->dma = dma_map_single(&np->pci_dev->dev, |
4305b541 | 1864 | skb->data, |
8b5be268 | 1865 | skb_tailroom(skb), |
7598b349 | 1866 | DMA_FROM_DEVICE); |
39e50d96 ZY |
1867 | if (unlikely(dma_mapping_error(&np->pci_dev->dev, |
1868 | np->put_rx_ctx->dma))) { | |
612a7c4e LF |
1869 | kfree_skb(skb); |
1870 | goto packet_dropped; | |
1871 | } | |
8b5be268 | 1872 | np->put_rx_ctx->dma_len = skb_tailroom(skb); |
5bb7ea26 AV |
1873 | np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma)); |
1874 | np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma)); | |
86b22b0d AA |
1875 | wmb(); |
1876 | np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL); | |
b01867cb | 1877 | if (unlikely(np->put_rx.ex++ == np->last_rx.ex)) |
64f26abb | 1878 | np->put_rx.ex = np->rx_ring.ex; |
b01867cb | 1879 | if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx)) |
a9124ec4 | 1880 | np->put_rx_ctx = np->rx_skb; |
0a1f222d | 1881 | } else { |
612a7c4e | 1882 | packet_dropped: |
0a1f222d | 1883 | u64_stats_update_begin(&np->swstats_rx_syncp); |
1884 | np->stat_rx_dropped++; | |
1885 | u64_stats_update_end(&np->swstats_rx_syncp); | |
0d63fb32 | 1886 | return 1; |
0a1f222d | 1887 | } |
1da177e4 | 1888 | } |
1da177e4 LT |
1889 | return 0; |
1890 | } | |
1891 | ||
e27cdba5 | 1892 | /* If rx bufs are exhausted called after 50ms to attempt to refresh */ |
d9935679 | 1893 | static void nv_do_rx_refill(struct timer_list *t) |
e27cdba5 | 1894 | { |
d9935679 | 1895 | struct fe_priv *np = from_timer(np, t, oom_kick); |
e27cdba5 SH |
1896 | |
1897 | /* Just reschedule NAPI rx processing */ | |
288379f0 | 1898 | napi_schedule(&np->napi); |
e27cdba5 | 1899 | } |
1da177e4 | 1900 | |
f3b197ac | 1901 | static void nv_init_rx(struct net_device *dev) |
1da177e4 | 1902 | { |
ac9c1897 | 1903 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 1904 | int i; |
36b30ea9 | 1905 | |
64f26abb ZY |
1906 | np->get_rx = np->rx_ring; |
1907 | np->put_rx = np->rx_ring; | |
36b30ea9 JG |
1908 | |
1909 | if (!nv_optimized(np)) | |
761fcd9e AA |
1910 | np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1]; |
1911 | else | |
1912 | np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1]; | |
a9124ec4 ZY |
1913 | np->get_rx_ctx = np->rx_skb; |
1914 | np->put_rx_ctx = np->rx_skb; | |
761fcd9e | 1915 | np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1]; |
1da177e4 | 1916 | |
761fcd9e | 1917 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 1918 | if (!nv_optimized(np)) { |
f82a9352 | 1919 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1920 | np->rx_ring.orig[i].buf = 0; |
1921 | } else { | |
f82a9352 | 1922 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1923 | np->rx_ring.ex[i].txvlan = 0; |
1924 | np->rx_ring.ex[i].bufhigh = 0; | |
1925 | np->rx_ring.ex[i].buflow = 0; | |
1926 | } | |
1927 | np->rx_skb[i].skb = NULL; | |
1928 | np->rx_skb[i].dma = 0; | |
1929 | } | |
d81c0983 MS |
1930 | } |
1931 | ||
1932 | static void nv_init_tx(struct net_device *dev) | |
1933 | { | |
ac9c1897 | 1934 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 | 1935 | int i; |
36b30ea9 | 1936 | |
c360f2b5 ZY |
1937 | np->get_tx = np->tx_ring; |
1938 | np->put_tx = np->tx_ring; | |
36b30ea9 JG |
1939 | |
1940 | if (!nv_optimized(np)) | |
761fcd9e AA |
1941 | np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1]; |
1942 | else | |
1943 | np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; | |
41b0cd36 ZY |
1944 | np->get_tx_ctx = np->tx_skb; |
1945 | np->put_tx_ctx = np->tx_skb; | |
761fcd9e | 1946 | np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1]; |
b8bfca94 | 1947 | netdev_reset_queue(np->dev); |
3b446c3e AA |
1948 | np->tx_pkts_in_progress = 0; |
1949 | np->tx_change_owner = NULL; | |
1950 | np->tx_end_flip = NULL; | |
8f955d7f | 1951 | np->tx_stop = 0; |
d81c0983 | 1952 | |
eafa59f6 | 1953 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 1954 | if (!nv_optimized(np)) { |
f82a9352 | 1955 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
1956 | np->tx_ring.orig[i].buf = 0; |
1957 | } else { | |
f82a9352 | 1958 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
1959 | np->tx_ring.ex[i].txvlan = 0; |
1960 | np->tx_ring.ex[i].bufhigh = 0; | |
1961 | np->tx_ring.ex[i].buflow = 0; | |
1962 | } | |
1963 | np->tx_skb[i].skb = NULL; | |
1964 | np->tx_skb[i].dma = 0; | |
3b446c3e | 1965 | np->tx_skb[i].dma_len = 0; |
73a37079 | 1966 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
1967 | np->tx_skb[i].first_tx_desc = NULL; |
1968 | np->tx_skb[i].next_tx_ctx = NULL; | |
ac9c1897 | 1969 | } |
d81c0983 MS |
1970 | } |
1971 | ||
1972 | static int nv_init_ring(struct net_device *dev) | |
1973 | { | |
86b22b0d AA |
1974 | struct fe_priv *np = netdev_priv(dev); |
1975 | ||
d81c0983 MS |
1976 | nv_init_tx(dev); |
1977 | nv_init_rx(dev); | |
36b30ea9 JG |
1978 | |
1979 | if (!nv_optimized(np)) | |
86b22b0d AA |
1980 | return nv_alloc_rx(dev); |
1981 | else | |
1982 | return nv_alloc_rx_optimized(dev); | |
1da177e4 LT |
1983 | } |
1984 | ||
73a37079 | 1985 | static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) |
ac9c1897 | 1986 | { |
761fcd9e | 1987 | if (tx_skb->dma) { |
73a37079 | 1988 | if (tx_skb->dma_single) |
7598b349 | 1989 | dma_unmap_single(&np->pci_dev->dev, tx_skb->dma, |
73a37079 | 1990 | tx_skb->dma_len, |
7598b349 | 1991 | DMA_TO_DEVICE); |
73a37079 | 1992 | else |
ca43a0c7 | 1993 | dma_unmap_page(&np->pci_dev->dev, tx_skb->dma, |
73a37079 | 1994 | tx_skb->dma_len, |
ca43a0c7 | 1995 | DMA_TO_DEVICE); |
761fcd9e | 1996 | tx_skb->dma = 0; |
fa45459e | 1997 | } |
73a37079 ED |
1998 | } |
1999 | ||
2000 | static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb) | |
2001 | { | |
2002 | nv_unmap_txskb(np, tx_skb); | |
761fcd9e AA |
2003 | if (tx_skb->skb) { |
2004 | dev_kfree_skb_any(tx_skb->skb); | |
2005 | tx_skb->skb = NULL; | |
fa45459e | 2006 | return 1; |
ac9c1897 | 2007 | } |
73a37079 | 2008 | return 0; |
ac9c1897 AA |
2009 | } |
2010 | ||
1da177e4 LT |
2011 | static void nv_drain_tx(struct net_device *dev) |
2012 | { | |
ac9c1897 AA |
2013 | struct fe_priv *np = netdev_priv(dev); |
2014 | unsigned int i; | |
f3b197ac | 2015 | |
eafa59f6 | 2016 | for (i = 0; i < np->tx_ring_size; i++) { |
36b30ea9 | 2017 | if (!nv_optimized(np)) { |
f82a9352 | 2018 | np->tx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
2019 | np->tx_ring.orig[i].buf = 0; |
2020 | } else { | |
f82a9352 | 2021 | np->tx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
2022 | np->tx_ring.ex[i].txvlan = 0; |
2023 | np->tx_ring.ex[i].bufhigh = 0; | |
2024 | np->tx_ring.ex[i].buflow = 0; | |
2025 | } | |
f5d827ae | 2026 | if (nv_release_txskb(np, &np->tx_skb[i])) { |
2027 | u64_stats_update_begin(&np->swstats_tx_syncp); | |
2028 | np->stat_tx_dropped++; | |
2029 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2030 | } | |
3b446c3e AA |
2031 | np->tx_skb[i].dma = 0; |
2032 | np->tx_skb[i].dma_len = 0; | |
73a37079 | 2033 | np->tx_skb[i].dma_single = 0; |
3b446c3e AA |
2034 | np->tx_skb[i].first_tx_desc = NULL; |
2035 | np->tx_skb[i].next_tx_ctx = NULL; | |
1da177e4 | 2036 | } |
3b446c3e AA |
2037 | np->tx_pkts_in_progress = 0; |
2038 | np->tx_change_owner = NULL; | |
2039 | np->tx_end_flip = NULL; | |
1da177e4 LT |
2040 | } |
2041 | ||
2042 | static void nv_drain_rx(struct net_device *dev) | |
2043 | { | |
ac9c1897 | 2044 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2045 | int i; |
761fcd9e | 2046 | |
eafa59f6 | 2047 | for (i = 0; i < np->rx_ring_size; i++) { |
36b30ea9 | 2048 | if (!nv_optimized(np)) { |
f82a9352 | 2049 | np->rx_ring.orig[i].flaglen = 0; |
761fcd9e AA |
2050 | np->rx_ring.orig[i].buf = 0; |
2051 | } else { | |
f82a9352 | 2052 | np->rx_ring.ex[i].flaglen = 0; |
761fcd9e AA |
2053 | np->rx_ring.ex[i].txvlan = 0; |
2054 | np->rx_ring.ex[i].bufhigh = 0; | |
2055 | np->rx_ring.ex[i].buflow = 0; | |
2056 | } | |
1da177e4 | 2057 | wmb(); |
761fcd9e | 2058 | if (np->rx_skb[i].skb) { |
7598b349 | 2059 | dma_unmap_single(&np->pci_dev->dev, np->rx_skb[i].dma, |
4305b541 | 2060 | (skb_end_pointer(np->rx_skb[i].skb) - |
7598b349 ZY |
2061 | np->rx_skb[i].skb->data), |
2062 | DMA_FROM_DEVICE); | |
761fcd9e AA |
2063 | dev_kfree_skb(np->rx_skb[i].skb); |
2064 | np->rx_skb[i].skb = NULL; | |
1da177e4 LT |
2065 | } |
2066 | } | |
2067 | } | |
2068 | ||
36b30ea9 | 2069 | static void nv_drain_rxtx(struct net_device *dev) |
1da177e4 LT |
2070 | { |
2071 | nv_drain_tx(dev); | |
2072 | nv_drain_rx(dev); | |
2073 | } | |
2074 | ||
761fcd9e AA |
2075 | static inline u32 nv_get_empty_tx_slots(struct fe_priv *np) |
2076 | { | |
2077 | return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size)); | |
2078 | } | |
2079 | ||
a433686c AA |
2080 | static void nv_legacybackoff_reseed(struct net_device *dev) |
2081 | { | |
2082 | u8 __iomem *base = get_hwbase(dev); | |
2083 | u32 reg; | |
2084 | u32 low; | |
2085 | int tx_status = 0; | |
2086 | ||
2087 | reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK; | |
2088 | get_random_bytes(&low, sizeof(low)); | |
2089 | reg |= low & NVREG_SLOTTIME_MASK; | |
2090 | ||
2091 | /* Need to stop tx before change takes effect. | |
2092 | * Caller has already gained np->lock. | |
2093 | */ | |
2094 | tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START; | |
2095 | if (tx_status) | |
2096 | nv_stop_tx(dev); | |
2097 | nv_stop_rx(dev); | |
2098 | writel(reg, base + NvRegSlotTime); | |
2099 | if (tx_status) | |
2100 | nv_start_tx(dev); | |
2101 | nv_start_rx(dev); | |
2102 | } | |
2103 | ||
2104 | /* Gear Backoff Seeds */ | |
2105 | #define BACKOFF_SEEDSET_ROWS 8 | |
2106 | #define BACKOFF_SEEDSET_LFSRS 15 | |
2107 | ||
2108 | /* Known Good seed sets */ | |
2109 | static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2110 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, |
2111 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974}, | |
2112 | {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874}, | |
2113 | {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974}, | |
2114 | {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984}, | |
2115 | {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984}, | |
2116 | {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84}, | |
2117 | {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} }; | |
a433686c AA |
2118 | |
2119 | static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = { | |
78aea4fc SJ |
2120 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, |
2121 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2122 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397}, | |
2123 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2124 | {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295}, | |
2125 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2126 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}, | |
2127 | {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} }; | |
a433686c AA |
2128 | |
2129 | static void nv_gear_backoff_reseed(struct net_device *dev) | |
2130 | { | |
2131 | u8 __iomem *base = get_hwbase(dev); | |
2132 | u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed; | |
2133 | u32 temp, seedset, combinedSeed; | |
2134 | int i; | |
2135 | ||
2136 | /* Setup seed for free running LFSR */ | |
2137 | /* We are going to read the time stamp counter 3 times | |
2138 | and swizzle bits around to increase randomness */ | |
2139 | get_random_bytes(&miniseed1, sizeof(miniseed1)); | |
2140 | miniseed1 &= 0x0fff; | |
2141 | if (miniseed1 == 0) | |
2142 | miniseed1 = 0xabc; | |
2143 | ||
2144 | get_random_bytes(&miniseed2, sizeof(miniseed2)); | |
2145 | miniseed2 &= 0x0fff; | |
2146 | if (miniseed2 == 0) | |
2147 | miniseed2 = 0xabc; | |
2148 | miniseed2_reversed = | |
2149 | ((miniseed2 & 0xF00) >> 8) | | |
2150 | (miniseed2 & 0x0F0) | | |
2151 | ((miniseed2 & 0x00F) << 8); | |
2152 | ||
2153 | get_random_bytes(&miniseed3, sizeof(miniseed3)); | |
2154 | miniseed3 &= 0x0fff; | |
2155 | if (miniseed3 == 0) | |
2156 | miniseed3 = 0xabc; | |
2157 | miniseed3_reversed = | |
2158 | ((miniseed3 & 0xF00) >> 8) | | |
2159 | (miniseed3 & 0x0F0) | | |
2160 | ((miniseed3 & 0x00F) << 8); | |
2161 | ||
2162 | combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) | | |
2163 | (miniseed2 ^ miniseed3_reversed); | |
2164 | ||
2165 | /* Seeds can not be zero */ | |
2166 | if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0) | |
2167 | combinedSeed |= 0x08; | |
2168 | if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0) | |
2169 | combinedSeed |= 0x8000; | |
2170 | ||
2171 | /* No need to disable tx here */ | |
2172 | temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT); | |
2173 | temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK; | |
2174 | temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR; | |
78aea4fc | 2175 | writel(temp, base + NvRegBackOffControl); |
a433686c | 2176 | |
78aea4fc | 2177 | /* Setup seeds for all gear LFSRs. */ |
a433686c AA |
2178 | get_random_bytes(&seedset, sizeof(seedset)); |
2179 | seedset = seedset % BACKOFF_SEEDSET_ROWS; | |
78aea4fc | 2180 | for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) { |
a433686c AA |
2181 | temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT); |
2182 | temp |= main_seedset[seedset][i-1] & 0x3ff; | |
2183 | temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR); | |
2184 | writel(temp, base + NvRegBackOffControl); | |
2185 | } | |
2186 | } | |
2187 | ||
1da177e4 LT |
2188 | /* |
2189 | * nv_start_xmit: dev->hard_start_xmit function | |
932ff279 | 2190 | * Called with netif_tx_lock held. |
1da177e4 | 2191 | */ |
61357325 | 2192 | static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 2193 | { |
ac9c1897 | 2194 | struct fe_priv *np = netdev_priv(dev); |
fa45459e | 2195 | u32 tx_flags = 0; |
ac9c1897 AA |
2196 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); |
2197 | unsigned int fragments = skb_shinfo(skb)->nr_frags; | |
ac9c1897 | 2198 | unsigned int i; |
fa45459e AA |
2199 | u32 offset = 0; |
2200 | u32 bcnt; | |
e743d313 | 2201 | u32 size = skb_headlen(skb); |
fa45459e | 2202 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
761fcd9e | 2203 | u32 empty_slots; |
78aea4fc SJ |
2204 | struct ring_desc *put_tx; |
2205 | struct ring_desc *start_tx; | |
2206 | struct ring_desc *prev_tx; | |
2207 | struct nv_skb_map *prev_tx_ctx; | |
f7f22874 | 2208 | struct nv_skb_map *tmp_tx_ctx = NULL, *start_tx_ctx = NULL; |
bd6ca637 | 2209 | unsigned long flags; |
fa45459e AA |
2210 | |
2211 | /* add fragments to entries count */ | |
2212 | for (i = 0; i < fragments; i++) { | |
e45a6187 | 2213 | u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]); |
9e903e08 | 2214 | |
e45a6187 | 2215 | entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) + |
2216 | ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
fa45459e | 2217 | } |
ac9c1897 | 2218 | |
001eb84b | 2219 | spin_lock_irqsave(&np->lock, flags); |
761fcd9e | 2220 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2221 | if (unlikely(empty_slots <= entries)) { |
ac9c1897 | 2222 | netif_stop_queue(dev); |
aaa37d2d | 2223 | np->tx_stop = 1; |
bd6ca637 | 2224 | spin_unlock_irqrestore(&np->lock, flags); |
ac9c1897 AA |
2225 | return NETDEV_TX_BUSY; |
2226 | } | |
001eb84b | 2227 | spin_unlock_irqrestore(&np->lock, flags); |
1da177e4 | 2228 | |
86b22b0d | 2229 | start_tx = put_tx = np->put_tx.orig; |
761fcd9e | 2230 | |
fa45459e AA |
2231 | /* setup the header buffer */ |
2232 | do { | |
2233 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; | |
7598b349 ZY |
2234 | np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev, |
2235 | skb->data + offset, bcnt, | |
2236 | DMA_TO_DEVICE); | |
39e50d96 ZY |
2237 | if (unlikely(dma_mapping_error(&np->pci_dev->dev, |
2238 | np->put_tx_ctx->dma))) { | |
612a7c4e | 2239 | /* on DMA mapping error - drop the packet */ |
1616566c | 2240 | dev_kfree_skb_any(skb); |
612a7c4e LF |
2241 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2242 | np->stat_tx_dropped++; | |
2243 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2244 | return NETDEV_TX_OK; | |
2245 | } | |
761fcd9e | 2246 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2247 | np->put_tx_ctx->dma_single = 1; |
86b22b0d AA |
2248 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2249 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2250 | |
fa45459e AA |
2251 | tx_flags = np->tx_flags; |
2252 | offset += bcnt; | |
2253 | size -= bcnt; | |
445583b8 | 2254 | if (unlikely(put_tx++ == np->last_tx.orig)) |
c360f2b5 | 2255 | put_tx = np->tx_ring.orig; |
445583b8 | 2256 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
41b0cd36 | 2257 | np->put_tx_ctx = np->tx_skb; |
f82a9352 | 2258 | } while (size); |
fa45459e AA |
2259 | |
2260 | /* setup the fragments */ | |
2261 | for (i = 0; i < fragments; i++) { | |
9e903e08 | 2262 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
e45a6187 | 2263 | u32 frag_size = skb_frag_size(frag); |
fa45459e AA |
2264 | offset = 0; |
2265 | ||
2266 | do { | |
f7f22874 NH |
2267 | if (!start_tx_ctx) |
2268 | start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx; | |
2269 | ||
e45a6187 | 2270 | bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size; |
671173c3 IC |
2271 | np->put_tx_ctx->dma = skb_frag_dma_map( |
2272 | &np->pci_dev->dev, | |
2273 | frag, offset, | |
2274 | bcnt, | |
5d6bcdfe | 2275 | DMA_TO_DEVICE); |
39e50d96 ZY |
2276 | if (unlikely(dma_mapping_error(&np->pci_dev->dev, |
2277 | np->put_tx_ctx->dma))) { | |
f7f22874 NH |
2278 | |
2279 | /* Unwind the mapped fragments */ | |
2280 | do { | |
2281 | nv_unmap_txskb(np, start_tx_ctx); | |
2282 | if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx)) | |
41b0cd36 | 2283 | tmp_tx_ctx = np->tx_skb; |
f7f22874 | 2284 | } while (tmp_tx_ctx != np->put_tx_ctx); |
1616566c | 2285 | dev_kfree_skb_any(skb); |
f7f22874 NH |
2286 | np->put_tx_ctx = start_tx_ctx; |
2287 | u64_stats_update_begin(&np->swstats_tx_syncp); | |
2288 | np->stat_tx_dropped++; | |
2289 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2290 | return NETDEV_TX_OK; | |
2291 | } | |
2292 | ||
761fcd9e | 2293 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2294 | np->put_tx_ctx->dma_single = 0; |
86b22b0d AA |
2295 | put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma); |
2296 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); | |
445583b8 | 2297 | |
fa45459e | 2298 | offset += bcnt; |
e45a6187 | 2299 | frag_size -= bcnt; |
445583b8 | 2300 | if (unlikely(put_tx++ == np->last_tx.orig)) |
c360f2b5 | 2301 | put_tx = np->tx_ring.orig; |
445583b8 | 2302 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
41b0cd36 | 2303 | np->put_tx_ctx = np->tx_skb; |
e45a6187 | 2304 | } while (frag_size); |
fa45459e | 2305 | } |
ac9c1897 | 2306 | |
c360f2b5 | 2307 | if (unlikely(put_tx == np->tx_ring.orig)) |
0d728b84 ZY |
2308 | prev_tx = np->last_tx.orig; |
2309 | else | |
2310 | prev_tx = put_tx - 1; | |
2311 | ||
41b0cd36 | 2312 | if (unlikely(np->put_tx_ctx == np->tx_skb)) |
0d728b84 ZY |
2313 | prev_tx_ctx = np->last_tx_ctx; |
2314 | else | |
2315 | prev_tx_ctx = np->put_tx_ctx - 1; | |
2316 | ||
fa45459e | 2317 | /* set last fragment flag */ |
86b22b0d | 2318 | prev_tx->flaglen |= cpu_to_le32(tx_flags_extra); |
ac9c1897 | 2319 | |
761fcd9e AA |
2320 | /* save skb in this slot's context area */ |
2321 | prev_tx_ctx->skb = skb; | |
fa45459e | 2322 | |
89114afd | 2323 | if (skb_is_gso(skb)) |
7967168c | 2324 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); |
ac9c1897 | 2325 | else |
1d39ed56 | 2326 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? |
84fa7933 | 2327 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; |
ac9c1897 | 2328 | |
bd6ca637 | 2329 | spin_lock_irqsave(&np->lock, flags); |
164a86e4 | 2330 | |
fa45459e | 2331 | /* set tx flags */ |
86b22b0d | 2332 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
b8bfca94 TH |
2333 | |
2334 | netdev_sent_queue(np->dev, skb->len); | |
2335 | ||
49cbb1c1 WB |
2336 | skb_tx_timestamp(skb); |
2337 | ||
86b22b0d | 2338 | np->put_tx.orig = put_tx; |
1da177e4 | 2339 | |
bd6ca637 | 2340 | spin_unlock_irqrestore(&np->lock, flags); |
761fcd9e | 2341 | |
8a4ae7f2 | 2342 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
ac9c1897 | 2343 | return NETDEV_TX_OK; |
1da177e4 LT |
2344 | } |
2345 | ||
61357325 SH |
2346 | static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb, |
2347 | struct net_device *dev) | |
86b22b0d AA |
2348 | { |
2349 | struct fe_priv *np = netdev_priv(dev); | |
2350 | u32 tx_flags = 0; | |
445583b8 | 2351 | u32 tx_flags_extra; |
86b22b0d AA |
2352 | unsigned int fragments = skb_shinfo(skb)->nr_frags; |
2353 | unsigned int i; | |
2354 | u32 offset = 0; | |
2355 | u32 bcnt; | |
e743d313 | 2356 | u32 size = skb_headlen(skb); |
86b22b0d AA |
2357 | u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); |
2358 | u32 empty_slots; | |
78aea4fc SJ |
2359 | struct ring_desc_ex *put_tx; |
2360 | struct ring_desc_ex *start_tx; | |
2361 | struct ring_desc_ex *prev_tx; | |
2362 | struct nv_skb_map *prev_tx_ctx; | |
f7f22874 NH |
2363 | struct nv_skb_map *start_tx_ctx = NULL; |
2364 | struct nv_skb_map *tmp_tx_ctx = NULL; | |
bd6ca637 | 2365 | unsigned long flags; |
86b22b0d AA |
2366 | |
2367 | /* add fragments to entries count */ | |
2368 | for (i = 0; i < fragments; i++) { | |
e45a6187 | 2369 | u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]); |
9e903e08 | 2370 | |
e45a6187 | 2371 | entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) + |
2372 | ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0); | |
86b22b0d AA |
2373 | } |
2374 | ||
001eb84b | 2375 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2376 | empty_slots = nv_get_empty_tx_slots(np); |
445583b8 | 2377 | if (unlikely(empty_slots <= entries)) { |
86b22b0d | 2378 | netif_stop_queue(dev); |
aaa37d2d | 2379 | np->tx_stop = 1; |
bd6ca637 | 2380 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2381 | return NETDEV_TX_BUSY; |
2382 | } | |
001eb84b | 2383 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d AA |
2384 | |
2385 | start_tx = put_tx = np->put_tx.ex; | |
3b446c3e | 2386 | start_tx_ctx = np->put_tx_ctx; |
86b22b0d AA |
2387 | |
2388 | /* setup the header buffer */ | |
2389 | do { | |
86b22b0d | 2390 | bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size; |
7598b349 ZY |
2391 | np->put_tx_ctx->dma = dma_map_single(&np->pci_dev->dev, |
2392 | skb->data + offset, bcnt, | |
2393 | DMA_TO_DEVICE); | |
39e50d96 ZY |
2394 | if (unlikely(dma_mapping_error(&np->pci_dev->dev, |
2395 | np->put_tx_ctx->dma))) { | |
612a7c4e | 2396 | /* on DMA mapping error - drop the packet */ |
1616566c | 2397 | dev_kfree_skb_any(skb); |
612a7c4e LF |
2398 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2399 | np->stat_tx_dropped++; | |
2400 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2401 | return NETDEV_TX_OK; | |
2402 | } | |
86b22b0d | 2403 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2404 | np->put_tx_ctx->dma_single = 1; |
5bb7ea26 AV |
2405 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2406 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2407 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 AA |
2408 | |
2409 | tx_flags = NV_TX2_VALID; | |
86b22b0d AA |
2410 | offset += bcnt; |
2411 | size -= bcnt; | |
445583b8 | 2412 | if (unlikely(put_tx++ == np->last_tx.ex)) |
c360f2b5 | 2413 | put_tx = np->tx_ring.ex; |
445583b8 | 2414 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
41b0cd36 | 2415 | np->put_tx_ctx = np->tx_skb; |
86b22b0d AA |
2416 | } while (size); |
2417 | ||
2418 | /* setup the fragments */ | |
2419 | for (i = 0; i < fragments; i++) { | |
2420 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
e45a6187 | 2421 | u32 frag_size = skb_frag_size(frag); |
86b22b0d AA |
2422 | offset = 0; |
2423 | ||
2424 | do { | |
e45a6187 | 2425 | bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size; |
f7f22874 NH |
2426 | if (!start_tx_ctx) |
2427 | start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx; | |
671173c3 IC |
2428 | np->put_tx_ctx->dma = skb_frag_dma_map( |
2429 | &np->pci_dev->dev, | |
2430 | frag, offset, | |
2431 | bcnt, | |
5d6bcdfe | 2432 | DMA_TO_DEVICE); |
f7f22874 | 2433 | |
39e50d96 ZY |
2434 | if (unlikely(dma_mapping_error(&np->pci_dev->dev, |
2435 | np->put_tx_ctx->dma))) { | |
f7f22874 NH |
2436 | |
2437 | /* Unwind the mapped fragments */ | |
2438 | do { | |
2439 | nv_unmap_txskb(np, start_tx_ctx); | |
2440 | if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx)) | |
41b0cd36 | 2441 | tmp_tx_ctx = np->tx_skb; |
f7f22874 | 2442 | } while (tmp_tx_ctx != np->put_tx_ctx); |
1616566c | 2443 | dev_kfree_skb_any(skb); |
f7f22874 NH |
2444 | np->put_tx_ctx = start_tx_ctx; |
2445 | u64_stats_update_begin(&np->swstats_tx_syncp); | |
2446 | np->stat_tx_dropped++; | |
2447 | u64_stats_update_end(&np->swstats_tx_syncp); | |
2448 | return NETDEV_TX_OK; | |
2449 | } | |
86b22b0d | 2450 | np->put_tx_ctx->dma_len = bcnt; |
73a37079 | 2451 | np->put_tx_ctx->dma_single = 0; |
5bb7ea26 AV |
2452 | put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma)); |
2453 | put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma)); | |
86b22b0d | 2454 | put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags); |
445583b8 | 2455 | |
86b22b0d | 2456 | offset += bcnt; |
e45a6187 | 2457 | frag_size -= bcnt; |
445583b8 | 2458 | if (unlikely(put_tx++ == np->last_tx.ex)) |
c360f2b5 | 2459 | put_tx = np->tx_ring.ex; |
445583b8 | 2460 | if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx)) |
41b0cd36 | 2461 | np->put_tx_ctx = np->tx_skb; |
e45a6187 | 2462 | } while (frag_size); |
86b22b0d AA |
2463 | } |
2464 | ||
c360f2b5 | 2465 | if (unlikely(put_tx == np->tx_ring.ex)) |
0d728b84 ZY |
2466 | prev_tx = np->last_tx.ex; |
2467 | else | |
2468 | prev_tx = put_tx - 1; | |
2469 | ||
41b0cd36 | 2470 | if (unlikely(np->put_tx_ctx == np->tx_skb)) |
0d728b84 ZY |
2471 | prev_tx_ctx = np->last_tx_ctx; |
2472 | else | |
2473 | prev_tx_ctx = np->put_tx_ctx - 1; | |
2474 | ||
86b22b0d | 2475 | /* set last fragment flag */ |
445583b8 | 2476 | prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET); |
86b22b0d AA |
2477 | |
2478 | /* save skb in this slot's context area */ | |
2479 | prev_tx_ctx->skb = skb; | |
2480 | ||
2481 | if (skb_is_gso(skb)) | |
2482 | tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT); | |
2483 | else | |
2484 | tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ? | |
2485 | NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0; | |
2486 | ||
2487 | /* vlan tag */ | |
df8a39de | 2488 | if (skb_vlan_tag_present(skb)) |
eab6d18d | 2489 | start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | |
df8a39de | 2490 | skb_vlan_tag_get(skb)); |
eab6d18d | 2491 | else |
445583b8 | 2492 | start_tx->txvlan = 0; |
86b22b0d | 2493 | |
bd6ca637 | 2494 | spin_lock_irqsave(&np->lock, flags); |
86b22b0d | 2495 | |
3b446c3e AA |
2496 | if (np->tx_limit) { |
2497 | /* Limit the number of outstanding tx. Setup all fragments, but | |
2498 | * do not set the VALID bit on the first descriptor. Save a pointer | |
2499 | * to that descriptor and also for next skb_map element. | |
2500 | */ | |
2501 | ||
2502 | if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) { | |
2503 | if (!np->tx_change_owner) | |
2504 | np->tx_change_owner = start_tx_ctx; | |
2505 | ||
2506 | /* remove VALID bit */ | |
2507 | tx_flags &= ~NV_TX2_VALID; | |
2508 | start_tx_ctx->first_tx_desc = start_tx; | |
2509 | start_tx_ctx->next_tx_ctx = np->put_tx_ctx; | |
2510 | np->tx_end_flip = np->put_tx_ctx; | |
2511 | } else { | |
2512 | np->tx_pkts_in_progress++; | |
2513 | } | |
2514 | } | |
2515 | ||
86b22b0d | 2516 | /* set tx flags */ |
86b22b0d | 2517 | start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra); |
b8bfca94 TH |
2518 | |
2519 | netdev_sent_queue(np->dev, skb->len); | |
2520 | ||
49cbb1c1 WB |
2521 | skb_tx_timestamp(skb); |
2522 | ||
86b22b0d AA |
2523 | np->put_tx.ex = put_tx; |
2524 | ||
bd6ca637 | 2525 | spin_unlock_irqrestore(&np->lock, flags); |
86b22b0d | 2526 | |
86b22b0d | 2527 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
86b22b0d AA |
2528 | return NETDEV_TX_OK; |
2529 | } | |
2530 | ||
3b446c3e AA |
2531 | static inline void nv_tx_flip_ownership(struct net_device *dev) |
2532 | { | |
2533 | struct fe_priv *np = netdev_priv(dev); | |
2534 | ||
2535 | np->tx_pkts_in_progress--; | |
2536 | if (np->tx_change_owner) { | |
30ecce90 AV |
2537 | np->tx_change_owner->first_tx_desc->flaglen |= |
2538 | cpu_to_le32(NV_TX2_VALID); | |
3b446c3e AA |
2539 | np->tx_pkts_in_progress++; |
2540 | ||
2541 | np->tx_change_owner = np->tx_change_owner->next_tx_ctx; | |
2542 | if (np->tx_change_owner == np->tx_end_flip) | |
2543 | np->tx_change_owner = NULL; | |
2544 | ||
2545 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
2546 | } | |
2547 | } | |
2548 | ||
1da177e4 LT |
2549 | /* |
2550 | * nv_tx_done: check for completed packets, release the skbs. | |
2551 | * | |
2552 | * Caller must own np->lock. | |
2553 | */ | |
33912e72 | 2554 | static int nv_tx_done(struct net_device *dev, int limit) |
1da177e4 | 2555 | { |
ac9c1897 | 2556 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2557 | u32 flags; |
33912e72 | 2558 | int tx_work = 0; |
78aea4fc | 2559 | struct ring_desc *orig_get_tx = np->get_tx.orig; |
b8bfca94 | 2560 | unsigned int bytes_compl = 0; |
1da177e4 | 2561 | |
445583b8 | 2562 | while ((np->get_tx.orig != np->put_tx.orig) && |
33912e72 AA |
2563 | !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) && |
2564 | (tx_work < limit)) { | |
1da177e4 | 2565 | |
73a37079 | 2566 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2567 | |
1da177e4 | 2568 | if (np->desc_ver == DESC_VER_1) { |
f82a9352 | 2569 | if (flags & NV_TX_LASTPACKET) { |
b78a6aa3 | 2570 | if (unlikely(flags & NV_TX_ERROR)) { |
f5d827ae | 2571 | if ((flags & NV_TX_RETRYERROR) |
2572 | && !(flags & NV_TX_RETRYCOUNT_MASK)) | |
a433686c | 2573 | nv_legacybackoff_reseed(dev); |
674aee3b | 2574 | } else { |
f5d827ae | 2575 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2576 | np->stat_tx_packets++; | |
2577 | np->stat_tx_bytes += np->get_tx_ctx->skb->len; | |
2578 | u64_stats_update_end(&np->swstats_tx_syncp); | |
ac9c1897 | 2579 | } |
b8bfca94 | 2580 | bytes_compl += np->get_tx_ctx->skb->len; |
445583b8 AA |
2581 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2582 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2583 | tx_work++; |
1da177e4 LT |
2584 | } |
2585 | } else { | |
f82a9352 | 2586 | if (flags & NV_TX2_LASTPACKET) { |
b78a6aa3 | 2587 | if (unlikely(flags & NV_TX2_ERROR)) { |
f5d827ae | 2588 | if ((flags & NV_TX2_RETRYERROR) |
2589 | && !(flags & NV_TX2_RETRYCOUNT_MASK)) | |
a433686c | 2590 | nv_legacybackoff_reseed(dev); |
674aee3b | 2591 | } else { |
f5d827ae | 2592 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2593 | np->stat_tx_packets++; | |
2594 | np->stat_tx_bytes += np->get_tx_ctx->skb->len; | |
2595 | u64_stats_update_end(&np->swstats_tx_syncp); | |
f3b197ac | 2596 | } |
b8bfca94 | 2597 | bytes_compl += np->get_tx_ctx->skb->len; |
445583b8 AA |
2598 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2599 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2600 | tx_work++; |
1da177e4 LT |
2601 | } |
2602 | } | |
445583b8 | 2603 | if (unlikely(np->get_tx.orig++ == np->last_tx.orig)) |
c360f2b5 | 2604 | np->get_tx.orig = np->tx_ring.orig; |
445583b8 | 2605 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
41b0cd36 | 2606 | np->get_tx_ctx = np->tx_skb; |
86b22b0d | 2607 | } |
b8bfca94 TH |
2608 | |
2609 | netdev_completed_queue(np->dev, tx_work, bytes_compl); | |
2610 | ||
445583b8 | 2611 | if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) { |
aaa37d2d | 2612 | np->tx_stop = 0; |
86b22b0d | 2613 | netif_wake_queue(dev); |
aaa37d2d | 2614 | } |
33912e72 | 2615 | return tx_work; |
86b22b0d AA |
2616 | } |
2617 | ||
33912e72 | 2618 | static int nv_tx_done_optimized(struct net_device *dev, int limit) |
86b22b0d AA |
2619 | { |
2620 | struct fe_priv *np = netdev_priv(dev); | |
2621 | u32 flags; | |
33912e72 | 2622 | int tx_work = 0; |
78aea4fc | 2623 | struct ring_desc_ex *orig_get_tx = np->get_tx.ex; |
b8bfca94 | 2624 | unsigned long bytes_cleaned = 0; |
86b22b0d | 2625 | |
445583b8 | 2626 | while ((np->get_tx.ex != np->put_tx.ex) && |
217d32dc | 2627 | !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) && |
33912e72 | 2628 | (tx_work < limit)) { |
86b22b0d | 2629 | |
73a37079 | 2630 | nv_unmap_txskb(np, np->get_tx_ctx); |
445583b8 | 2631 | |
86b22b0d | 2632 | if (flags & NV_TX2_LASTPACKET) { |
b78a6aa3 | 2633 | if (unlikely(flags & NV_TX2_ERROR)) { |
f5d827ae | 2634 | if ((flags & NV_TX2_RETRYERROR) |
2635 | && !(flags & NV_TX2_RETRYCOUNT_MASK)) { | |
a433686c AA |
2636 | if (np->driver_data & DEV_HAS_GEAR_MODE) |
2637 | nv_gear_backoff_reseed(dev); | |
2638 | else | |
2639 | nv_legacybackoff_reseed(dev); | |
2640 | } | |
674aee3b | 2641 | } else { |
efd0bf97 DM |
2642 | u64_stats_update_begin(&np->swstats_tx_syncp); |
2643 | np->stat_tx_packets++; | |
2644 | np->stat_tx_bytes += np->get_tx_ctx->skb->len; | |
2645 | u64_stats_update_end(&np->swstats_tx_syncp); | |
a433686c AA |
2646 | } |
2647 | ||
b8bfca94 | 2648 | bytes_cleaned += np->get_tx_ctx->skb->len; |
445583b8 AA |
2649 | dev_kfree_skb_any(np->get_tx_ctx->skb); |
2650 | np->get_tx_ctx->skb = NULL; | |
33912e72 | 2651 | tx_work++; |
3b446c3e | 2652 | |
78aea4fc | 2653 | if (np->tx_limit) |
3b446c3e | 2654 | nv_tx_flip_ownership(dev); |
761fcd9e | 2655 | } |
b8bfca94 | 2656 | |
445583b8 | 2657 | if (unlikely(np->get_tx.ex++ == np->last_tx.ex)) |
c360f2b5 | 2658 | np->get_tx.ex = np->tx_ring.ex; |
445583b8 | 2659 | if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx)) |
41b0cd36 | 2660 | np->get_tx_ctx = np->tx_skb; |
1da177e4 | 2661 | } |
7505afe2 IM |
2662 | |
2663 | netdev_completed_queue(np->dev, tx_work, bytes_cleaned); | |
2664 | ||
445583b8 | 2665 | if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) { |
aaa37d2d | 2666 | np->tx_stop = 0; |
1da177e4 | 2667 | netif_wake_queue(dev); |
aaa37d2d | 2668 | } |
33912e72 | 2669 | return tx_work; |
1da177e4 LT |
2670 | } |
2671 | ||
2672 | /* | |
2673 | * nv_tx_timeout: dev->tx_timeout function | |
932ff279 | 2674 | * Called with netif_tx_lock held. |
1da177e4 LT |
2675 | */ |
2676 | static void nv_tx_timeout(struct net_device *dev) | |
2677 | { | |
ac9c1897 | 2678 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 2679 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 2680 | u32 status; |
8f955d7f AA |
2681 | union ring_type put_tx; |
2682 | int saved_tx_limit; | |
d33a73c8 AA |
2683 | |
2684 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
2685 | status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2686 | else | |
2687 | status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
1da177e4 | 2688 | |
1ec4f2d3 | 2689 | netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status); |
1da177e4 | 2690 | |
1ec4f2d3 SN |
2691 | if (unlikely(debug_tx_timeout)) { |
2692 | int i; | |
2693 | ||
2694 | netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr); | |
2695 | netdev_info(dev, "Dumping tx registers\n"); | |
2696 | for (i = 0; i <= np->register_size; i += 32) { | |
1d397f36 | 2697 | netdev_info(dev, |
1ec4f2d3 SN |
2698 | "%3x: %08x %08x %08x %08x " |
2699 | "%08x %08x %08x %08x\n", | |
1d397f36 | 2700 | i, |
1ec4f2d3 SN |
2701 | readl(base + i + 0), readl(base + i + 4), |
2702 | readl(base + i + 8), readl(base + i + 12), | |
2703 | readl(base + i + 16), readl(base + i + 20), | |
2704 | readl(base + i + 24), readl(base + i + 28)); | |
2705 | } | |
2706 | netdev_info(dev, "Dumping tx ring\n"); | |
2707 | for (i = 0; i < np->tx_ring_size; i += 4) { | |
2708 | if (!nv_optimized(np)) { | |
2709 | netdev_info(dev, | |
2710 | "%03x: %08x %08x // %08x %08x " | |
2711 | "// %08x %08x // %08x %08x\n", | |
2712 | i, | |
2713 | le32_to_cpu(np->tx_ring.orig[i].buf), | |
2714 | le32_to_cpu(np->tx_ring.orig[i].flaglen), | |
2715 | le32_to_cpu(np->tx_ring.orig[i+1].buf), | |
2716 | le32_to_cpu(np->tx_ring.orig[i+1].flaglen), | |
2717 | le32_to_cpu(np->tx_ring.orig[i+2].buf), | |
2718 | le32_to_cpu(np->tx_ring.orig[i+2].flaglen), | |
2719 | le32_to_cpu(np->tx_ring.orig[i+3].buf), | |
2720 | le32_to_cpu(np->tx_ring.orig[i+3].flaglen)); | |
2721 | } else { | |
2722 | netdev_info(dev, | |
2723 | "%03x: %08x %08x %08x " | |
2724 | "// %08x %08x %08x " | |
2725 | "// %08x %08x %08x " | |
2726 | "// %08x %08x %08x\n", | |
2727 | i, | |
2728 | le32_to_cpu(np->tx_ring.ex[i].bufhigh), | |
2729 | le32_to_cpu(np->tx_ring.ex[i].buflow), | |
2730 | le32_to_cpu(np->tx_ring.ex[i].flaglen), | |
2731 | le32_to_cpu(np->tx_ring.ex[i+1].bufhigh), | |
2732 | le32_to_cpu(np->tx_ring.ex[i+1].buflow), | |
2733 | le32_to_cpu(np->tx_ring.ex[i+1].flaglen), | |
2734 | le32_to_cpu(np->tx_ring.ex[i+2].bufhigh), | |
2735 | le32_to_cpu(np->tx_ring.ex[i+2].buflow), | |
2736 | le32_to_cpu(np->tx_ring.ex[i+2].flaglen), | |
2737 | le32_to_cpu(np->tx_ring.ex[i+3].bufhigh), | |
2738 | le32_to_cpu(np->tx_ring.ex[i+3].buflow), | |
2739 | le32_to_cpu(np->tx_ring.ex[i+3].flaglen)); | |
2740 | } | |
c2dba06d MS |
2741 | } |
2742 | } | |
2743 | ||
1da177e4 LT |
2744 | spin_lock_irq(&np->lock); |
2745 | ||
2746 | /* 1) stop tx engine */ | |
2747 | nv_stop_tx(dev); | |
2748 | ||
8f955d7f AA |
2749 | /* 2) complete any outstanding tx and do not give HW any limited tx pkts */ |
2750 | saved_tx_limit = np->tx_limit; | |
2751 | np->tx_limit = 0; /* prevent giving HW any limited pkts */ | |
2752 | np->tx_stop = 0; /* prevent waking tx queue */ | |
36b30ea9 | 2753 | if (!nv_optimized(np)) |
33912e72 | 2754 | nv_tx_done(dev, np->tx_ring_size); |
86b22b0d | 2755 | else |
4e16ed1b | 2756 | nv_tx_done_optimized(dev, np->tx_ring_size); |
1da177e4 | 2757 | |
25985edc | 2758 | /* save current HW position */ |
8f955d7f AA |
2759 | if (np->tx_change_owner) |
2760 | put_tx.ex = np->tx_change_owner->first_tx_desc; | |
2761 | else | |
2762 | put_tx = np->put_tx; | |
1da177e4 | 2763 | |
8f955d7f AA |
2764 | /* 3) clear all tx state */ |
2765 | nv_drain_tx(dev); | |
2766 | nv_init_tx(dev); | |
2767 | ||
2768 | /* 4) restore state to current HW position */ | |
2769 | np->get_tx = np->put_tx = put_tx; | |
2770 | np->tx_limit = saved_tx_limit; | |
3ba4d093 | 2771 | |
8f955d7f | 2772 | /* 5) restart tx engine */ |
1da177e4 | 2773 | nv_start_tx(dev); |
8f955d7f | 2774 | netif_wake_queue(dev); |
1da177e4 LT |
2775 | spin_unlock_irq(&np->lock); |
2776 | } | |
2777 | ||
22c6d143 MS |
2778 | /* |
2779 | * Called when the nic notices a mismatch between the actual data len on the | |
2780 | * wire and the len indicated in the 802 header | |
2781 | */ | |
2782 | static int nv_getlen(struct net_device *dev, void *packet, int datalen) | |
2783 | { | |
2784 | int hdrlen; /* length of the 802 header */ | |
2785 | int protolen; /* length as stored in the proto field */ | |
2786 | ||
2787 | /* 1) calculate len according to header */ | |
78aea4fc SJ |
2788 | if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) { |
2789 | protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto); | |
22c6d143 MS |
2790 | hdrlen = VLAN_HLEN; |
2791 | } else { | |
78aea4fc | 2792 | protolen = ntohs(((struct ethhdr *)packet)->h_proto); |
22c6d143 MS |
2793 | hdrlen = ETH_HLEN; |
2794 | } | |
22c6d143 MS |
2795 | if (protolen > ETH_DATA_LEN) |
2796 | return datalen; /* Value in proto field not a len, no checks possible */ | |
2797 | ||
2798 | protolen += hdrlen; | |
2799 | /* consistency checks: */ | |
2800 | if (datalen > ETH_ZLEN) { | |
2801 | if (datalen >= protolen) { | |
2802 | /* more data on wire than in 802 header, trim of | |
2803 | * additional data. | |
2804 | */ | |
22c6d143 MS |
2805 | return protolen; |
2806 | } else { | |
2807 | /* less data on wire than mentioned in header. | |
2808 | * Discard the packet. | |
2809 | */ | |
22c6d143 MS |
2810 | return -1; |
2811 | } | |
2812 | } else { | |
2813 | /* short packet. Accept only if 802 values are also short */ | |
2814 | if (protolen > ETH_ZLEN) { | |
22c6d143 MS |
2815 | return -1; |
2816 | } | |
22c6d143 MS |
2817 | return datalen; |
2818 | } | |
2819 | } | |
2820 | ||
e27cdba5 | 2821 | static int nv_rx_process(struct net_device *dev, int limit) |
1da177e4 | 2822 | { |
ac9c1897 | 2823 | struct fe_priv *np = netdev_priv(dev); |
f82a9352 | 2824 | u32 flags; |
bcb5febb | 2825 | int rx_work = 0; |
b01867cb AA |
2826 | struct sk_buff *skb; |
2827 | int len; | |
1da177e4 | 2828 | |
78aea4fc | 2829 | while ((np->get_rx.orig != np->put_rx.orig) && |
b01867cb | 2830 | !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) && |
bcb5febb | 2831 | (rx_work < limit)) { |
1da177e4 | 2832 | |
1da177e4 LT |
2833 | /* |
2834 | * the packet is for us - immediately tear down the pci mapping. | |
2835 | * TODO: check if a prefetch of the first cacheline improves | |
2836 | * the performance. | |
2837 | */ | |
7598b349 ZY |
2838 | dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma, |
2839 | np->get_rx_ctx->dma_len, | |
2840 | DMA_FROM_DEVICE); | |
0d63fb32 AA |
2841 | skb = np->get_rx_ctx->skb; |
2842 | np->get_rx_ctx->skb = NULL; | |
1da177e4 | 2843 | |
1da177e4 LT |
2844 | /* look at what we actually got: */ |
2845 | if (np->desc_ver == DESC_VER_1) { | |
b01867cb AA |
2846 | if (likely(flags & NV_RX_DESCRIPTORVALID)) { |
2847 | len = flags & LEN_MASK_V1; | |
2848 | if (unlikely(flags & NV_RX_ERROR)) { | |
1ef6841b | 2849 | if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) { |
b01867cb AA |
2850 | len = nv_getlen(dev, skb->data, len); |
2851 | if (len < 0) { | |
b01867cb AA |
2852 | dev_kfree_skb(skb); |
2853 | goto next_pkt; | |
2854 | } | |
2855 | } | |
2856 | /* framing errors are soft errors */ | |
1ef6841b | 2857 | else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) { |
cef33c81 | 2858 | if (flags & NV_RX_SUBTRACT1) |
b01867cb | 2859 | len--; |
b01867cb AA |
2860 | } |
2861 | /* the rest are hard errors */ | |
2862 | else { | |
f5d827ae | 2863 | if (flags & NV_RX_MISSEDFRAME) { |
2864 | u64_stats_update_begin(&np->swstats_rx_syncp); | |
2865 | np->stat_rx_missed_errors++; | |
2866 | u64_stats_update_end(&np->swstats_rx_syncp); | |
2867 | } | |
0d63fb32 | 2868 | dev_kfree_skb(skb); |
a971c324 AA |
2869 | goto next_pkt; |
2870 | } | |
2871 | } | |
b01867cb | 2872 | } else { |
0d63fb32 | 2873 | dev_kfree_skb(skb); |
1da177e4 | 2874 | goto next_pkt; |
0d63fb32 | 2875 | } |
b01867cb AA |
2876 | } else { |
2877 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { | |
2878 | len = flags & LEN_MASK_V2; | |
2879 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2880 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2881 | len = nv_getlen(dev, skb->data, len); |
2882 | if (len < 0) { | |
b01867cb AA |
2883 | dev_kfree_skb(skb); |
2884 | goto next_pkt; | |
2885 | } | |
2886 | } | |
2887 | /* framing errors are soft errors */ | |
1ef6841b | 2888 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
cef33c81 | 2889 | if (flags & NV_RX2_SUBTRACT1) |
b01867cb | 2890 | len--; |
b01867cb AA |
2891 | } |
2892 | /* the rest are hard errors */ | |
2893 | else { | |
0d63fb32 | 2894 | dev_kfree_skb(skb); |
a971c324 AA |
2895 | goto next_pkt; |
2896 | } | |
2897 | } | |
bfaffe8f AA |
2898 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2899 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
0d63fb32 | 2900 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2901 | } else { |
2902 | dev_kfree_skb(skb); | |
2903 | goto next_pkt; | |
1da177e4 LT |
2904 | } |
2905 | } | |
2906 | /* got a valid packet - forward it to the network core */ | |
1da177e4 LT |
2907 | skb_put(skb, len); |
2908 | skb->protocol = eth_type_trans(skb, dev); | |
53f224cc | 2909 | napi_gro_receive(&np->napi, skb); |
f5d827ae | 2910 | u64_stats_update_begin(&np->swstats_rx_syncp); |
2911 | np->stat_rx_packets++; | |
2912 | np->stat_rx_bytes += len; | |
2913 | u64_stats_update_end(&np->swstats_rx_syncp); | |
1da177e4 | 2914 | next_pkt: |
b01867cb | 2915 | if (unlikely(np->get_rx.orig++ == np->last_rx.orig)) |
64f26abb | 2916 | np->get_rx.orig = np->rx_ring.orig; |
b01867cb | 2917 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
a9124ec4 | 2918 | np->get_rx_ctx = np->rx_skb; |
bcb5febb IM |
2919 | |
2920 | rx_work++; | |
86b22b0d AA |
2921 | } |
2922 | ||
bcb5febb | 2923 | return rx_work; |
86b22b0d AA |
2924 | } |
2925 | ||
2926 | static int nv_rx_process_optimized(struct net_device *dev, int limit) | |
2927 | { | |
2928 | struct fe_priv *np = netdev_priv(dev); | |
2929 | u32 flags; | |
2930 | u32 vlanflags = 0; | |
c1b7151a | 2931 | int rx_work = 0; |
b01867cb AA |
2932 | struct sk_buff *skb; |
2933 | int len; | |
86b22b0d | 2934 | |
78aea4fc | 2935 | while ((np->get_rx.ex != np->put_rx.ex) && |
b01867cb | 2936 | !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) && |
c1b7151a | 2937 | (rx_work < limit)) { |
86b22b0d | 2938 | |
86b22b0d AA |
2939 | /* |
2940 | * the packet is for us - immediately tear down the pci mapping. | |
2941 | * TODO: check if a prefetch of the first cacheline improves | |
2942 | * the performance. | |
2943 | */ | |
7598b349 ZY |
2944 | dma_unmap_single(&np->pci_dev->dev, np->get_rx_ctx->dma, |
2945 | np->get_rx_ctx->dma_len, | |
2946 | DMA_FROM_DEVICE); | |
86b22b0d AA |
2947 | skb = np->get_rx_ctx->skb; |
2948 | np->get_rx_ctx->skb = NULL; | |
2949 | ||
86b22b0d | 2950 | /* look at what we actually got: */ |
b01867cb AA |
2951 | if (likely(flags & NV_RX2_DESCRIPTORVALID)) { |
2952 | len = flags & LEN_MASK_V2; | |
2953 | if (unlikely(flags & NV_RX2_ERROR)) { | |
1ef6841b | 2954 | if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) { |
b01867cb AA |
2955 | len = nv_getlen(dev, skb->data, len); |
2956 | if (len < 0) { | |
b01867cb AA |
2957 | dev_kfree_skb(skb); |
2958 | goto next_pkt; | |
2959 | } | |
2960 | } | |
2961 | /* framing errors are soft errors */ | |
1ef6841b | 2962 | else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) { |
cef33c81 | 2963 | if (flags & NV_RX2_SUBTRACT1) |
b01867cb | 2964 | len--; |
b01867cb AA |
2965 | } |
2966 | /* the rest are hard errors */ | |
2967 | else { | |
86b22b0d AA |
2968 | dev_kfree_skb(skb); |
2969 | goto next_pkt; | |
2970 | } | |
2971 | } | |
b01867cb | 2972 | |
bfaffe8f AA |
2973 | if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */ |
2974 | ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */ | |
86b22b0d | 2975 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
b01867cb AA |
2976 | |
2977 | /* got a valid packet - forward it to the network core */ | |
2978 | skb_put(skb, len); | |
2979 | skb->protocol = eth_type_trans(skb, dev); | |
2980 | prefetch(skb->data); | |
2981 | ||
3326c784 | 2982 | vlanflags = le32_to_cpu(np->get_rx.ex->buflow); |
0891b0e0 JP |
2983 | |
2984 | /* | |
f646968f PM |
2985 | * There's need to check for NETIF_F_HW_VLAN_CTAG_RX |
2986 | * here. Even if vlan rx accel is disabled, | |
0891b0e0 JP |
2987 | * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set. |
2988 | */ | |
f646968f | 2989 | if (dev->features & NETIF_F_HW_VLAN_CTAG_RX && |
0891b0e0 | 2990 | vlanflags & NV_RX3_VLAN_TAG_PRESENT) { |
3326c784 JP |
2991 | u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK; |
2992 | ||
86a9bad3 | 2993 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); |
b01867cb | 2994 | } |
3326c784 | 2995 | napi_gro_receive(&np->napi, skb); |
f5d827ae | 2996 | u64_stats_update_begin(&np->swstats_rx_syncp); |
2997 | np->stat_rx_packets++; | |
2998 | np->stat_rx_bytes += len; | |
2999 | u64_stats_update_end(&np->swstats_rx_syncp); | |
b01867cb AA |
3000 | } else { |
3001 | dev_kfree_skb(skb); | |
3002 | } | |
86b22b0d | 3003 | next_pkt: |
b01867cb | 3004 | if (unlikely(np->get_rx.ex++ == np->last_rx.ex)) |
64f26abb | 3005 | np->get_rx.ex = np->rx_ring.ex; |
b01867cb | 3006 | if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx)) |
a9124ec4 | 3007 | np->get_rx_ctx = np->rx_skb; |
c1b7151a IM |
3008 | |
3009 | rx_work++; | |
1da177e4 | 3010 | } |
e27cdba5 | 3011 | |
c1b7151a | 3012 | return rx_work; |
1da177e4 LT |
3013 | } |
3014 | ||
d81c0983 MS |
3015 | static void set_bufsize(struct net_device *dev) |
3016 | { | |
3017 | struct fe_priv *np = netdev_priv(dev); | |
3018 | ||
3019 | if (dev->mtu <= ETH_DATA_LEN) | |
3020 | np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS; | |
3021 | else | |
3022 | np->rx_buf_sz = dev->mtu + NV_RX_HEADERS; | |
3023 | } | |
3024 | ||
1da177e4 LT |
3025 | /* |
3026 | * nv_change_mtu: dev->change_mtu function | |
3027 | * Called with dev_base_lock held for read. | |
3028 | */ | |
3029 | static int nv_change_mtu(struct net_device *dev, int new_mtu) | |
3030 | { | |
ac9c1897 | 3031 | struct fe_priv *np = netdev_priv(dev); |
d81c0983 MS |
3032 | int old_mtu; |
3033 | ||
d81c0983 | 3034 | old_mtu = dev->mtu; |
1da177e4 | 3035 | dev->mtu = new_mtu; |
d81c0983 MS |
3036 | |
3037 | /* return early if the buffer sizes will not change */ | |
3038 | if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN) | |
3039 | return 0; | |
d81c0983 MS |
3040 | |
3041 | /* synchronized against open : rtnl_lock() held by caller */ | |
3042 | if (netif_running(dev)) { | |
25097d4b | 3043 | u8 __iomem *base = get_hwbase(dev); |
d81c0983 MS |
3044 | /* |
3045 | * It seems that the nic preloads valid ring entries into an | |
3046 | * internal buffer. The procedure for flushing everything is | |
3047 | * guessed, there is probably a simpler approach. | |
3048 | * Changing the MTU is a rare event, it shouldn't matter. | |
3049 | */ | |
84b3932b | 3050 | nv_disable_irq(dev); |
08d93575 | 3051 | nv_napi_disable(dev); |
932ff279 | 3052 | netif_tx_lock_bh(dev); |
e308a5d8 | 3053 | netif_addr_lock(dev); |
d81c0983 MS |
3054 | spin_lock(&np->lock); |
3055 | /* stop engines */ | |
36b30ea9 | 3056 | nv_stop_rxtx(dev); |
d81c0983 MS |
3057 | nv_txrx_reset(dev); |
3058 | /* drain rx queue */ | |
36b30ea9 | 3059 | nv_drain_rxtx(dev); |
d81c0983 | 3060 | /* reinit driver view of the rx queue */ |
d81c0983 | 3061 | set_bufsize(dev); |
eafa59f6 | 3062 | if (nv_init_ring(dev)) { |
d81c0983 MS |
3063 | if (!np->in_shutdown) |
3064 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3065 | } | |
3066 | /* reinit nic view of the rx queue */ | |
3067 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
0832b25a | 3068 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 3069 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
d81c0983 MS |
3070 | base + NvRegRingSizes); |
3071 | pci_push(base); | |
8a4ae7f2 | 3072 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); |
d81c0983 MS |
3073 | pci_push(base); |
3074 | ||
3075 | /* restart rx engine */ | |
36b30ea9 | 3076 | nv_start_rxtx(dev); |
d81c0983 | 3077 | spin_unlock(&np->lock); |
e308a5d8 | 3078 | netif_addr_unlock(dev); |
932ff279 | 3079 | netif_tx_unlock_bh(dev); |
08d93575 | 3080 | nv_napi_enable(dev); |
84b3932b | 3081 | nv_enable_irq(dev); |
d81c0983 | 3082 | } |
1da177e4 LT |
3083 | return 0; |
3084 | } | |
3085 | ||
72b31782 MS |
3086 | static void nv_copy_mac_to_hw(struct net_device *dev) |
3087 | { | |
25097d4b | 3088 | u8 __iomem *base = get_hwbase(dev); |
72b31782 MS |
3089 | u32 mac[2]; |
3090 | ||
3091 | mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) + | |
3092 | (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24); | |
3093 | mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8); | |
3094 | ||
3095 | writel(mac[0], base + NvRegMacAddrA); | |
3096 | writel(mac[1], base + NvRegMacAddrB); | |
3097 | } | |
3098 | ||
3099 | /* | |
3100 | * nv_set_mac_address: dev->set_mac_address function | |
3101 | * Called with rtnl_lock() held. | |
3102 | */ | |
3103 | static int nv_set_mac_address(struct net_device *dev, void *addr) | |
3104 | { | |
ac9c1897 | 3105 | struct fe_priv *np = netdev_priv(dev); |
78aea4fc | 3106 | struct sockaddr *macaddr = (struct sockaddr *)addr; |
72b31782 | 3107 | |
f82a9352 | 3108 | if (!is_valid_ether_addr(macaddr->sa_data)) |
72b31782 MS |
3109 | return -EADDRNOTAVAIL; |
3110 | ||
3111 | /* synchronized against open : rtnl_lock() held by caller */ | |
3112 | memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN); | |
3113 | ||
3114 | if (netif_running(dev)) { | |
932ff279 | 3115 | netif_tx_lock_bh(dev); |
e308a5d8 | 3116 | netif_addr_lock(dev); |
72b31782 MS |
3117 | spin_lock_irq(&np->lock); |
3118 | ||
3119 | /* stop rx engine */ | |
3120 | nv_stop_rx(dev); | |
3121 | ||
3122 | /* set mac address */ | |
3123 | nv_copy_mac_to_hw(dev); | |
3124 | ||
3125 | /* restart rx engine */ | |
3126 | nv_start_rx(dev); | |
3127 | spin_unlock_irq(&np->lock); | |
e308a5d8 | 3128 | netif_addr_unlock(dev); |
932ff279 | 3129 | netif_tx_unlock_bh(dev); |
72b31782 MS |
3130 | } else { |
3131 | nv_copy_mac_to_hw(dev); | |
3132 | } | |
3133 | return 0; | |
3134 | } | |
3135 | ||
1da177e4 LT |
3136 | /* |
3137 | * nv_set_multicast: dev->set_multicast function | |
932ff279 | 3138 | * Called with netif_tx_lock held. |
1da177e4 LT |
3139 | */ |
3140 | static void nv_set_multicast(struct net_device *dev) | |
3141 | { | |
ac9c1897 | 3142 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
3143 | u8 __iomem *base = get_hwbase(dev); |
3144 | u32 addr[2]; | |
3145 | u32 mask[2]; | |
b6d0773f | 3146 | u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; |
1da177e4 LT |
3147 | |
3148 | memset(addr, 0, sizeof(addr)); | |
3149 | memset(mask, 0, sizeof(mask)); | |
3150 | ||
3151 | if (dev->flags & IFF_PROMISC) { | |
b6d0773f | 3152 | pff |= NVREG_PFF_PROMISC; |
1da177e4 | 3153 | } else { |
b6d0773f | 3154 | pff |= NVREG_PFF_MYADDR; |
1da177e4 | 3155 | |
48e2f183 | 3156 | if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) { |
1da177e4 LT |
3157 | u32 alwaysOff[2]; |
3158 | u32 alwaysOn[2]; | |
3159 | ||
3160 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff; | |
3161 | if (dev->flags & IFF_ALLMULTI) { | |
3162 | alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0; | |
3163 | } else { | |
22bedad3 | 3164 | struct netdev_hw_addr *ha; |
1da177e4 | 3165 | |
22bedad3 | 3166 | netdev_for_each_mc_addr(ha, dev) { |
e45a6187 | 3167 | unsigned char *hw_addr = ha->addr; |
1da177e4 | 3168 | u32 a, b; |
22bedad3 | 3169 | |
e45a6187 | 3170 | a = le32_to_cpu(*(__le32 *) hw_addr); |
3171 | b = le16_to_cpu(*(__le16 *) (&hw_addr[4])); | |
1da177e4 LT |
3172 | alwaysOn[0] &= a; |
3173 | alwaysOff[0] &= ~a; | |
3174 | alwaysOn[1] &= b; | |
3175 | alwaysOff[1] &= ~b; | |
1da177e4 LT |
3176 | } |
3177 | } | |
3178 | addr[0] = alwaysOn[0]; | |
3179 | addr[1] = alwaysOn[1]; | |
3180 | mask[0] = alwaysOn[0] | alwaysOff[0]; | |
3181 | mask[1] = alwaysOn[1] | alwaysOff[1]; | |
bb9a4fd1 AA |
3182 | } else { |
3183 | mask[0] = NVREG_MCASTMASKA_NONE; | |
3184 | mask[1] = NVREG_MCASTMASKB_NONE; | |
1da177e4 LT |
3185 | } |
3186 | } | |
3187 | addr[0] |= NVREG_MCASTADDRA_FORCE; | |
3188 | pff |= NVREG_PFF_ALWAYS; | |
3189 | spin_lock_irq(&np->lock); | |
3190 | nv_stop_rx(dev); | |
3191 | writel(addr[0], base + NvRegMulticastAddrA); | |
3192 | writel(addr[1], base + NvRegMulticastAddrB); | |
3193 | writel(mask[0], base + NvRegMulticastMaskA); | |
3194 | writel(mask[1], base + NvRegMulticastMaskB); | |
3195 | writel(pff, base + NvRegPacketFilterFlags); | |
1da177e4 LT |
3196 | nv_start_rx(dev); |
3197 | spin_unlock_irq(&np->lock); | |
3198 | } | |
3199 | ||
c7985051 | 3200 | static void nv_update_pause(struct net_device *dev, u32 pause_flags) |
b6d0773f AA |
3201 | { |
3202 | struct fe_priv *np = netdev_priv(dev); | |
3203 | u8 __iomem *base = get_hwbase(dev); | |
3204 | ||
3205 | np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE); | |
3206 | ||
3207 | if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) { | |
3208 | u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; | |
3209 | if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) { | |
3210 | writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); | |
3211 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3212 | } else { | |
3213 | writel(pff, base + NvRegPacketFilterFlags); | |
3214 | } | |
3215 | } | |
3216 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) { | |
3217 | u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; | |
3218 | if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) { | |
5289b4c4 AA |
3219 | u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; |
3220 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) | |
3221 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; | |
9a33e883 | 3222 | if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) { |
5289b4c4 | 3223 | pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; |
9a33e883 AA |
3224 | /* limit the number of tx pause frames to a default of 8 */ |
3225 | writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit); | |
3226 | } | |
5289b4c4 | 3227 | writel(pause_enable, base + NvRegTxPauseFrame); |
b6d0773f AA |
3228 | writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); |
3229 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3230 | } else { | |
3231 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
3232 | writel(regmisc, base + NvRegMisc1); | |
3233 | } | |
3234 | } | |
3235 | } | |
3236 | ||
e19df76a SH |
3237 | static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex) |
3238 | { | |
3239 | struct fe_priv *np = netdev_priv(dev); | |
3240 | u8 __iomem *base = get_hwbase(dev); | |
3241 | u32 phyreg, txreg; | |
3242 | int mii_status; | |
3243 | ||
3244 | np->linkspeed = NVREG_LINKSPEED_FORCE|speed; | |
3245 | np->duplex = duplex; | |
3246 | ||
3247 | /* see if gigabit phy */ | |
3248 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3249 | if (mii_status & PHY_GIGABIT) { | |
3250 | np->gigabit = PHY_GIGABIT; | |
3251 | phyreg = readl(base + NvRegSlotTime); | |
3252 | phyreg &= ~(0x3FF00); | |
3253 | if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) | |
3254 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
3255 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) | |
3256 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
3257 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) | |
3258 | phyreg |= NVREG_SLOTTIME_1000_FULL; | |
3259 | writel(phyreg, base + NvRegSlotTime); | |
3260 | } | |
3261 | ||
3262 | phyreg = readl(base + NvRegPhyInterface); | |
3263 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3264 | if (np->duplex == 0) | |
3265 | phyreg |= PHY_HALF; | |
3266 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3267 | phyreg |= PHY_100; | |
3268 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == | |
3269 | NVREG_LINKSPEED_1000) | |
3270 | phyreg |= PHY_1000; | |
3271 | writel(phyreg, base + NvRegPhyInterface); | |
3272 | ||
3273 | if (phyreg & PHY_RGMII) { | |
3274 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == | |
3275 | NVREG_LINKSPEED_1000) | |
3276 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; | |
3277 | else | |
3278 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3279 | } else { | |
3280 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
3281 | } | |
3282 | writel(txreg, base + NvRegTxDeferral); | |
3283 | ||
3284 | if (np->desc_ver == DESC_VER_1) { | |
3285 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3286 | } else { | |
3287 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == | |
3288 | NVREG_LINKSPEED_1000) | |
3289 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3290 | else | |
3291 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3292 | } | |
3293 | writel(txreg, base + NvRegTxWatermark); | |
3294 | ||
3295 | writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), | |
3296 | base + NvRegMisc1); | |
3297 | pci_push(base); | |
3298 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3299 | pci_push(base); | |
e19df76a SH |
3300 | } |
3301 | ||
4ea7f299 | 3302 | /** |
49ce9c2c | 3303 | * nv_update_linkspeed - Setup the MAC according to the link partner |
4ea7f299 AA |
3304 | * @dev: Network device to be configured |
3305 | * | |
3306 | * The function queries the PHY and checks if there is a link partner. | |
3307 | * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is | |
3308 | * set to 10 MBit HD. | |
3309 | * | |
3310 | * The function returns 0 if there is no link partner and 1 if there is | |
3311 | * a good link partner. | |
3312 | */ | |
1da177e4 LT |
3313 | static int nv_update_linkspeed(struct net_device *dev) |
3314 | { | |
ac9c1897 | 3315 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3316 | u8 __iomem *base = get_hwbase(dev); |
eb91f61b AA |
3317 | int adv = 0; |
3318 | int lpa = 0; | |
3319 | int adv_lpa, adv_pause, lpa_pause; | |
1da177e4 LT |
3320 | int newls = np->linkspeed; |
3321 | int newdup = np->duplex; | |
3322 | int mii_status; | |
e19df76a | 3323 | u32 bmcr; |
1da177e4 | 3324 | int retval = 0; |
9744e218 | 3325 | u32 control_1000, status_1000, phyreg, pause_flags, txreg; |
b2976d23 | 3326 | u32 txrxFlags = 0; |
fd9b558c | 3327 | u32 phy_exp; |
1da177e4 | 3328 | |
e19df76a SH |
3329 | /* If device loopback is enabled, set carrier on and enable max link |
3330 | * speed. | |
3331 | */ | |
3332 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
3333 | if (bmcr & BMCR_LOOPBACK) { | |
3334 | if (netif_running(dev)) { | |
3335 | nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1); | |
3336 | if (!netif_carrier_ok(dev)) | |
3337 | netif_carrier_on(dev); | |
3338 | } | |
3339 | return 1; | |
3340 | } | |
3341 | ||
1da177e4 LT |
3342 | /* BMSR_LSTATUS is latched, read it twice: |
3343 | * we want the current value. | |
3344 | */ | |
3345 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3346 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
3347 | ||
3348 | if (!(mii_status & BMSR_LSTATUS)) { | |
1da177e4 LT |
3349 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3350 | newdup = 0; | |
3351 | retval = 0; | |
3352 | goto set_speed; | |
3353 | } | |
3354 | ||
3355 | if (np->autoneg == 0) { | |
1da177e4 LT |
3356 | if (np->fixed_mode & LPA_100FULL) { |
3357 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3358 | newdup = 1; | |
3359 | } else if (np->fixed_mode & LPA_100HALF) { | |
3360 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; | |
3361 | newdup = 0; | |
3362 | } else if (np->fixed_mode & LPA_10FULL) { | |
3363 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3364 | newdup = 1; | |
3365 | } else { | |
3366 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3367 | newdup = 0; | |
3368 | } | |
3369 | retval = 1; | |
3370 | goto set_speed; | |
3371 | } | |
3372 | /* check auto negotiation is complete */ | |
3373 | if (!(mii_status & BMSR_ANEGCOMPLETE)) { | |
3374 | /* still in autonegotiation - configure nic for 10 MBit HD and wait. */ | |
3375 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
3376 | newdup = 0; | |
3377 | retval = 0; | |
1da177e4 LT |
3378 | goto set_speed; |
3379 | } | |
3380 | ||
b6d0773f AA |
3381 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
3382 | lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); | |
b6d0773f | 3383 | |
1da177e4 LT |
3384 | retval = 1; |
3385 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b AA |
3386 | control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
3387 | status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); | |
1da177e4 LT |
3388 | |
3389 | if ((control_1000 & ADVERTISE_1000FULL) && | |
3390 | (status_1000 & LPA_1000FULL)) { | |
1da177e4 LT |
3391 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; |
3392 | newdup = 1; | |
3393 | goto set_speed; | |
3394 | } | |
3395 | } | |
3396 | ||
1da177e4 | 3397 | /* FIXME: handle parallel detection properly */ |
eb91f61b AA |
3398 | adv_lpa = lpa & adv; |
3399 | if (adv_lpa & LPA_100FULL) { | |
1da177e4 LT |
3400 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3401 | newdup = 1; | |
eb91f61b | 3402 | } else if (adv_lpa & LPA_100HALF) { |
1da177e4 LT |
3403 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; |
3404 | newdup = 0; | |
eb91f61b | 3405 | } else if (adv_lpa & LPA_10FULL) { |
1da177e4 LT |
3406 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3407 | newdup = 1; | |
eb91f61b | 3408 | } else if (adv_lpa & LPA_10HALF) { |
1da177e4 LT |
3409 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3410 | newdup = 0; | |
3411 | } else { | |
1da177e4 LT |
3412 | newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; |
3413 | newdup = 0; | |
3414 | } | |
3415 | ||
3416 | set_speed: | |
3417 | if (np->duplex == newdup && np->linkspeed == newls) | |
3418 | return retval; | |
3419 | ||
1da177e4 LT |
3420 | np->duplex = newdup; |
3421 | np->linkspeed = newls; | |
3422 | ||
b2976d23 AA |
3423 | /* The transmitter and receiver must be restarted for safe update */ |
3424 | if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { | |
3425 | txrxFlags |= NV_RESTART_TX; | |
3426 | nv_stop_tx(dev); | |
3427 | } | |
3428 | if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { | |
3429 | txrxFlags |= NV_RESTART_RX; | |
3430 | nv_stop_rx(dev); | |
3431 | } | |
3432 | ||
1da177e4 | 3433 | if (np->gigabit == PHY_GIGABIT) { |
a433686c | 3434 | phyreg = readl(base + NvRegSlotTime); |
1da177e4 | 3435 | phyreg &= ~(0x3FF00); |
a433686c AA |
3436 | if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) || |
3437 | ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)) | |
3438 | phyreg |= NVREG_SLOTTIME_10_100_FULL; | |
1da177e4 | 3439 | else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) |
a433686c AA |
3440 | phyreg |= NVREG_SLOTTIME_1000_FULL; |
3441 | writel(phyreg, base + NvRegSlotTime); | |
1da177e4 LT |
3442 | } |
3443 | ||
3444 | phyreg = readl(base + NvRegPhyInterface); | |
3445 | phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); | |
3446 | if (np->duplex == 0) | |
3447 | phyreg |= PHY_HALF; | |
3448 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) | |
3449 | phyreg |= PHY_100; | |
3450 | else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3451 | phyreg |= PHY_1000; | |
3452 | writel(phyreg, base + NvRegPhyInterface); | |
3453 | ||
fd9b558c | 3454 | phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ |
9744e218 | 3455 | if (phyreg & PHY_RGMII) { |
fd9b558c | 3456 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { |
9744e218 | 3457 | txreg = NVREG_TX_DEFERRAL_RGMII_1000; |
fd9b558c AA |
3458 | } else { |
3459 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) { | |
3460 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) | |
3461 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10; | |
3462 | else | |
3463 | txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100; | |
3464 | } else { | |
3465 | txreg = NVREG_TX_DEFERRAL_RGMII_10_100; | |
3466 | } | |
3467 | } | |
9744e218 | 3468 | } else { |
fd9b558c AA |
3469 | if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) |
3470 | txreg = NVREG_TX_DEFERRAL_MII_STRETCH; | |
3471 | else | |
3472 | txreg = NVREG_TX_DEFERRAL_DEFAULT; | |
9744e218 AA |
3473 | } |
3474 | writel(txreg, base + NvRegTxDeferral); | |
3475 | ||
95d161cb AA |
3476 | if (np->desc_ver == DESC_VER_1) { |
3477 | txreg = NVREG_TX_WM_DESC1_DEFAULT; | |
3478 | } else { | |
3479 | if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) | |
3480 | txreg = NVREG_TX_WM_DESC2_3_1000; | |
3481 | else | |
3482 | txreg = NVREG_TX_WM_DESC2_3_DEFAULT; | |
3483 | } | |
3484 | writel(txreg, base + NvRegTxWatermark); | |
3485 | ||
78aea4fc | 3486 | writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD), |
1da177e4 LT |
3487 | base + NvRegMisc1); |
3488 | pci_push(base); | |
3489 | writel(np->linkspeed, base + NvRegLinkSpeed); | |
3490 | pci_push(base); | |
3491 | ||
b6d0773f AA |
3492 | pause_flags = 0; |
3493 | /* setup pause frame */ | |
1ff39eb6 | 3494 | if (netif_running(dev) && (np->duplex != 0)) { |
b6d0773f | 3495 | if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) { |
78aea4fc SJ |
3496 | adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
3497 | lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM); | |
b6d0773f AA |
3498 | |
3499 | switch (adv_pause) { | |
f82a9352 | 3500 | case ADVERTISE_PAUSE_CAP: |
b6d0773f AA |
3501 | if (lpa_pause & LPA_PAUSE_CAP) { |
3502 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
3503 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3504 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3505 | } | |
3506 | break; | |
f82a9352 | 3507 | case ADVERTISE_PAUSE_ASYM: |
78aea4fc | 3508 | if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM)) |
b6d0773f | 3509 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; |
b6d0773f | 3510 | break; |
78aea4fc SJ |
3511 | case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM: |
3512 | if (lpa_pause & LPA_PAUSE_CAP) { | |
b6d0773f AA |
3513 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
3514 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
3515 | pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
3516 | } | |
3517 | if (lpa_pause == LPA_PAUSE_ASYM) | |
b6d0773f | 3518 | pause_flags |= NV_PAUSEFRAME_RX_ENABLE; |
b6d0773f | 3519 | break; |
f3b197ac | 3520 | } |
eb91f61b | 3521 | } else { |
b6d0773f | 3522 | pause_flags = np->pause_flags; |
eb91f61b AA |
3523 | } |
3524 | } | |
b6d0773f | 3525 | nv_update_pause(dev, pause_flags); |
eb91f61b | 3526 | |
b2976d23 AA |
3527 | if (txrxFlags & NV_RESTART_TX) |
3528 | nv_start_tx(dev); | |
3529 | if (txrxFlags & NV_RESTART_RX) | |
3530 | nv_start_rx(dev); | |
3531 | ||
1da177e4 LT |
3532 | return retval; |
3533 | } | |
3534 | ||
3535 | static void nv_linkchange(struct net_device *dev) | |
3536 | { | |
3537 | if (nv_update_linkspeed(dev)) { | |
4ea7f299 | 3538 | if (!netif_carrier_ok(dev)) { |
1da177e4 | 3539 | netif_carrier_on(dev); |
1d397f36 | 3540 | netdev_info(dev, "link up\n"); |
88d7d8b0 | 3541 | nv_txrx_gate(dev, false); |
4ea7f299 | 3542 | nv_start_rx(dev); |
1da177e4 | 3543 | } |
1da177e4 LT |
3544 | } else { |
3545 | if (netif_carrier_ok(dev)) { | |
3546 | netif_carrier_off(dev); | |
1d397f36 | 3547 | netdev_info(dev, "link down\n"); |
88d7d8b0 | 3548 | nv_txrx_gate(dev, true); |
1da177e4 LT |
3549 | nv_stop_rx(dev); |
3550 | } | |
3551 | } | |
3552 | } | |
3553 | ||
3554 | static void nv_link_irq(struct net_device *dev) | |
3555 | { | |
3556 | u8 __iomem *base = get_hwbase(dev); | |
3557 | u32 miistat; | |
3558 | ||
3559 | miistat = readl(base + NvRegMIIStatus); | |
eb798428 | 3560 | writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); |
1da177e4 LT |
3561 | |
3562 | if (miistat & (NVREG_MIISTAT_LINKCHANGE)) | |
3563 | nv_linkchange(dev); | |
1da177e4 LT |
3564 | } |
3565 | ||
4db0ee17 AA |
3566 | static void nv_msi_workaround(struct fe_priv *np) |
3567 | { | |
3568 | ||
3569 | /* Need to toggle the msi irq mask within the ethernet device, | |
3570 | * otherwise, future interrupts will not be detected. | |
3571 | */ | |
3572 | if (np->msi_flags & NV_MSI_ENABLED) { | |
3573 | u8 __iomem *base = np->base; | |
3574 | ||
3575 | writel(0, base + NvRegMSIIrqMask); | |
3576 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
3577 | } | |
3578 | } | |
3579 | ||
4145ade2 AA |
3580 | static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work) |
3581 | { | |
3582 | struct fe_priv *np = netdev_priv(dev); | |
3583 | ||
3584 | if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) { | |
3585 | if (total_work > NV_DYNAMIC_THRESHOLD) { | |
3586 | /* transition to poll based interrupts */ | |
3587 | np->quiet_count = 0; | |
3588 | if (np->irqmask != NVREG_IRQMASK_CPU) { | |
3589 | np->irqmask = NVREG_IRQMASK_CPU; | |
3590 | return 1; | |
3591 | } | |
3592 | } else { | |
3593 | if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) { | |
3594 | np->quiet_count++; | |
3595 | } else { | |
3596 | /* reached a period of low activity, switch | |
3597 | to per tx/rx packet interrupts */ | |
3598 | if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { | |
3599 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
3600 | return 1; | |
3601 | } | |
3602 | } | |
3603 | } | |
3604 | } | |
3605 | return 0; | |
3606 | } | |
3607 | ||
7d12e780 | 3608 | static irqreturn_t nv_nic_irq(int foo, void *data) |
1da177e4 LT |
3609 | { |
3610 | struct net_device *dev = (struct net_device *) data; | |
ac9c1897 | 3611 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 3612 | u8 __iomem *base = get_hwbase(dev); |
1da177e4 | 3613 | |
b67874ac AA |
3614 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3615 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3616 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3617 | } else { |
3618 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3619 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac | 3620 | } |
b67874ac AA |
3621 | if (!(np->events & np->irqmask)) |
3622 | return IRQ_NONE; | |
1da177e4 | 3623 | |
b67874ac | 3624 | nv_msi_workaround(np); |
4db0ee17 | 3625 | |
78c29bd9 ED |
3626 | if (napi_schedule_prep(&np->napi)) { |
3627 | /* | |
3628 | * Disable further irq's (msix not enabled with napi) | |
3629 | */ | |
3630 | writel(0, base + NvRegIrqMask); | |
3631 | __napi_schedule(&np->napi); | |
3632 | } | |
f0734ab6 | 3633 | |
b67874ac | 3634 | return IRQ_HANDLED; |
1da177e4 LT |
3635 | } |
3636 | ||
1aa8b471 | 3637 | /* All _optimized functions are used to help increase performance |
f0734ab6 AA |
3638 | * (reduce CPU and increase throughput). They use descripter version 3, |
3639 | * compiler directives, and reduce memory accesses. | |
3640 | */ | |
86b22b0d AA |
3641 | static irqreturn_t nv_nic_irq_optimized(int foo, void *data) |
3642 | { | |
3643 | struct net_device *dev = (struct net_device *) data; | |
3644 | struct fe_priv *np = netdev_priv(dev); | |
3645 | u8 __iomem *base = get_hwbase(dev); | |
86b22b0d | 3646 | |
b67874ac AA |
3647 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3648 | np->events = readl(base + NvRegIrqStatus); | |
1b2bb76f | 3649 | writel(np->events, base + NvRegIrqStatus); |
b67874ac AA |
3650 | } else { |
3651 | np->events = readl(base + NvRegMSIXIrqStatus); | |
1b2bb76f | 3652 | writel(np->events, base + NvRegMSIXIrqStatus); |
b67874ac | 3653 | } |
b67874ac AA |
3654 | if (!(np->events & np->irqmask)) |
3655 | return IRQ_NONE; | |
86b22b0d | 3656 | |
b67874ac | 3657 | nv_msi_workaround(np); |
4db0ee17 | 3658 | |
78c29bd9 ED |
3659 | if (napi_schedule_prep(&np->napi)) { |
3660 | /* | |
3661 | * Disable further irq's (msix not enabled with napi) | |
3662 | */ | |
3663 | writel(0, base + NvRegIrqMask); | |
3664 | __napi_schedule(&np->napi); | |
3665 | } | |
86b22b0d | 3666 | |
b67874ac | 3667 | return IRQ_HANDLED; |
86b22b0d AA |
3668 | } |
3669 | ||
7d12e780 | 3670 | static irqreturn_t nv_nic_irq_tx(int foo, void *data) |
d33a73c8 AA |
3671 | { |
3672 | struct net_device *dev = (struct net_device *) data; | |
3673 | struct fe_priv *np = netdev_priv(dev); | |
3674 | u8 __iomem *base = get_hwbase(dev); | |
3675 | u32 events; | |
3676 | int i; | |
0a07bc64 | 3677 | unsigned long flags; |
d33a73c8 | 3678 | |
78aea4fc | 3679 | for (i = 0;; i++) { |
d33a73c8 | 3680 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; |
2a4e7a08 MD |
3681 | writel(events, base + NvRegMSIXIrqStatus); |
3682 | netdev_dbg(dev, "tx irq events: %08x\n", events); | |
d33a73c8 AA |
3683 | if (!(events & np->irqmask)) |
3684 | break; | |
3685 | ||
0a07bc64 | 3686 | spin_lock_irqsave(&np->lock, flags); |
4e16ed1b | 3687 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); |
0a07bc64 | 3688 | spin_unlock_irqrestore(&np->lock, flags); |
f3b197ac | 3689 | |
f0734ab6 | 3690 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3691 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3692 | /* disable interrupts on the nic */ |
3693 | writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); | |
3694 | pci_push(base); | |
3695 | ||
3696 | if (!np->in_shutdown) { | |
3697 | np->nic_poll_irq |= NVREG_IRQ_TX_ALL; | |
3698 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3699 | } | |
0a07bc64 | 3700 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3701 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3702 | __func__, i); | |
d33a73c8 AA |
3703 | break; |
3704 | } | |
3705 | ||
3706 | } | |
d33a73c8 AA |
3707 | |
3708 | return IRQ_RETVAL(i); | |
3709 | } | |
3710 | ||
bea3348e | 3711 | static int nv_napi_poll(struct napi_struct *napi, int budget) |
e27cdba5 | 3712 | { |
bea3348e SH |
3713 | struct fe_priv *np = container_of(napi, struct fe_priv, napi); |
3714 | struct net_device *dev = np->dev; | |
e27cdba5 | 3715 | u8 __iomem *base = get_hwbase(dev); |
d15e9c4d | 3716 | unsigned long flags; |
4145ade2 | 3717 | int retcode; |
78aea4fc | 3718 | int rx_count, tx_work = 0, rx_work = 0; |
e27cdba5 | 3719 | |
81a2e36d | 3720 | do { |
3721 | if (!nv_optimized(np)) { | |
3722 | spin_lock_irqsave(&np->lock, flags); | |
3723 | tx_work += nv_tx_done(dev, np->tx_ring_size); | |
3724 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3725 | |
d951f725 | 3726 | rx_count = nv_rx_process(dev, budget - rx_work); |
81a2e36d | 3727 | retcode = nv_alloc_rx(dev); |
3728 | } else { | |
3729 | spin_lock_irqsave(&np->lock, flags); | |
3730 | tx_work += nv_tx_done_optimized(dev, np->tx_ring_size); | |
3731 | spin_unlock_irqrestore(&np->lock, flags); | |
f27e6f39 | 3732 | |
d951f725 TH |
3733 | rx_count = nv_rx_process_optimized(dev, |
3734 | budget - rx_work); | |
81a2e36d | 3735 | retcode = nv_alloc_rx_optimized(dev); |
3736 | } | |
3737 | } while (retcode == 0 && | |
3738 | rx_count > 0 && (rx_work += rx_count) < budget); | |
e27cdba5 | 3739 | |
e0379a14 | 3740 | if (retcode) { |
d15e9c4d | 3741 | spin_lock_irqsave(&np->lock, flags); |
e27cdba5 SH |
3742 | if (!np->in_shutdown) |
3743 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
d15e9c4d | 3744 | spin_unlock_irqrestore(&np->lock, flags); |
e27cdba5 SH |
3745 | } |
3746 | ||
4145ade2 AA |
3747 | nv_change_interrupt_mode(dev, tx_work + rx_work); |
3748 | ||
f27e6f39 AA |
3749 | if (unlikely(np->events & NVREG_IRQ_LINK)) { |
3750 | spin_lock_irqsave(&np->lock, flags); | |
3751 | nv_link_irq(dev); | |
3752 | spin_unlock_irqrestore(&np->lock, flags); | |
3753 | } | |
3754 | if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) { | |
3755 | spin_lock_irqsave(&np->lock, flags); | |
3756 | nv_linkchange(dev); | |
3757 | spin_unlock_irqrestore(&np->lock, flags); | |
3758 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
3759 | } | |
3760 | if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) { | |
3761 | spin_lock_irqsave(&np->lock, flags); | |
3762 | if (!np->in_shutdown) { | |
3763 | np->nic_poll_irq = np->irqmask; | |
3764 | np->recover_error = 1; | |
3765 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3766 | } | |
3767 | spin_unlock_irqrestore(&np->lock, flags); | |
6c2da9c2 | 3768 | napi_complete(napi); |
4145ade2 | 3769 | return rx_work; |
f27e6f39 AA |
3770 | } |
3771 | ||
4145ade2 | 3772 | if (rx_work < budget) { |
f27e6f39 AA |
3773 | /* re-enable interrupts |
3774 | (msix not enabled in napi) */ | |
6ad20165 | 3775 | napi_complete_done(napi, rx_work); |
bea3348e | 3776 | |
f27e6f39 | 3777 | writel(np->irqmask, base + NvRegIrqMask); |
e27cdba5 | 3778 | } |
4145ade2 | 3779 | return rx_work; |
e27cdba5 | 3780 | } |
e27cdba5 | 3781 | |
7d12e780 | 3782 | static irqreturn_t nv_nic_irq_rx(int foo, void *data) |
d33a73c8 AA |
3783 | { |
3784 | struct net_device *dev = (struct net_device *) data; | |
3785 | struct fe_priv *np = netdev_priv(dev); | |
3786 | u8 __iomem *base = get_hwbase(dev); | |
3787 | u32 events; | |
3788 | int i; | |
0a07bc64 | 3789 | unsigned long flags; |
d33a73c8 | 3790 | |
78aea4fc | 3791 | for (i = 0;; i++) { |
d33a73c8 | 3792 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; |
2a4e7a08 MD |
3793 | writel(events, base + NvRegMSIXIrqStatus); |
3794 | netdev_dbg(dev, "rx irq events: %08x\n", events); | |
d33a73c8 AA |
3795 | if (!(events & np->irqmask)) |
3796 | break; | |
f3b197ac | 3797 | |
bea3348e | 3798 | if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) { |
f0734ab6 AA |
3799 | if (unlikely(nv_alloc_rx_optimized(dev))) { |
3800 | spin_lock_irqsave(&np->lock, flags); | |
3801 | if (!np->in_shutdown) | |
3802 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
3803 | spin_unlock_irqrestore(&np->lock, flags); | |
3804 | } | |
d33a73c8 | 3805 | } |
f3b197ac | 3806 | |
f0734ab6 | 3807 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3808 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3809 | /* disable interrupts on the nic */ |
3810 | writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); | |
3811 | pci_push(base); | |
3812 | ||
3813 | if (!np->in_shutdown) { | |
3814 | np->nic_poll_irq |= NVREG_IRQ_RX_ALL; | |
3815 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3816 | } | |
0a07bc64 | 3817 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3818 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3819 | __func__, i); | |
d33a73c8 AA |
3820 | break; |
3821 | } | |
d33a73c8 | 3822 | } |
d33a73c8 AA |
3823 | |
3824 | return IRQ_RETVAL(i); | |
3825 | } | |
3826 | ||
7d12e780 | 3827 | static irqreturn_t nv_nic_irq_other(int foo, void *data) |
d33a73c8 AA |
3828 | { |
3829 | struct net_device *dev = (struct net_device *) data; | |
3830 | struct fe_priv *np = netdev_priv(dev); | |
3831 | u8 __iomem *base = get_hwbase(dev); | |
3832 | u32 events; | |
3833 | int i; | |
0a07bc64 | 3834 | unsigned long flags; |
d33a73c8 | 3835 | |
78aea4fc | 3836 | for (i = 0;; i++) { |
d33a73c8 | 3837 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; |
2a4e7a08 MD |
3838 | writel(events, base + NvRegMSIXIrqStatus); |
3839 | netdev_dbg(dev, "irq events: %08x\n", events); | |
d33a73c8 AA |
3840 | if (!(events & np->irqmask)) |
3841 | break; | |
f3b197ac | 3842 | |
4e16ed1b AA |
3843 | /* check tx in case we reached max loop limit in tx isr */ |
3844 | spin_lock_irqsave(&np->lock, flags); | |
3845 | nv_tx_done_optimized(dev, TX_WORK_PER_LOOP); | |
3846 | spin_unlock_irqrestore(&np->lock, flags); | |
3847 | ||
d33a73c8 | 3848 | if (events & NVREG_IRQ_LINK) { |
0a07bc64 | 3849 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3850 | nv_link_irq(dev); |
0a07bc64 | 3851 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3852 | } |
3853 | if (np->need_linktimer && time_after(jiffies, np->link_timeout)) { | |
0a07bc64 | 3854 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 | 3855 | nv_linkchange(dev); |
0a07bc64 | 3856 | spin_unlock_irqrestore(&np->lock, flags); |
d33a73c8 AA |
3857 | np->link_timeout = jiffies + LINK_TIMEOUT; |
3858 | } | |
c5cf9101 | 3859 | if (events & NVREG_IRQ_RECOVER_ERROR) { |
186e8687 | 3860 | spin_lock_irqsave(&np->lock, flags); |
c5cf9101 AA |
3861 | /* disable interrupts on the nic */ |
3862 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3863 | pci_push(base); | |
3864 | ||
3865 | if (!np->in_shutdown) { | |
3866 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3867 | np->recover_error = 1; | |
3868 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3869 | } | |
186e8687 | 3870 | spin_unlock_irqrestore(&np->lock, flags); |
c5cf9101 AA |
3871 | break; |
3872 | } | |
f0734ab6 | 3873 | if (unlikely(i > max_interrupt_work)) { |
0a07bc64 | 3874 | spin_lock_irqsave(&np->lock, flags); |
d33a73c8 AA |
3875 | /* disable interrupts on the nic */ |
3876 | writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); | |
3877 | pci_push(base); | |
3878 | ||
3879 | if (!np->in_shutdown) { | |
3880 | np->nic_poll_irq |= NVREG_IRQ_OTHER; | |
3881 | mod_timer(&np->nic_poll, jiffies + POLL_WAIT); | |
3882 | } | |
0a07bc64 | 3883 | spin_unlock_irqrestore(&np->lock, flags); |
c20ec761 JP |
3884 | netdev_dbg(dev, "%s: too many iterations (%d)\n", |
3885 | __func__, i); | |
d33a73c8 AA |
3886 | break; |
3887 | } | |
3888 | ||
3889 | } | |
d33a73c8 AA |
3890 | |
3891 | return IRQ_RETVAL(i); | |
3892 | } | |
3893 | ||
7d12e780 | 3894 | static irqreturn_t nv_nic_irq_test(int foo, void *data) |
9589c77a AA |
3895 | { |
3896 | struct net_device *dev = (struct net_device *) data; | |
3897 | struct fe_priv *np = netdev_priv(dev); | |
3898 | u8 __iomem *base = get_hwbase(dev); | |
3899 | u32 events; | |
3900 | ||
9589c77a AA |
3901 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) { |
3902 | events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; | |
2a4e7a08 | 3903 | writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus); |
9589c77a AA |
3904 | } else { |
3905 | events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; | |
2a4e7a08 | 3906 | writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); |
9589c77a AA |
3907 | } |
3908 | pci_push(base); | |
9589c77a AA |
3909 | if (!(events & NVREG_IRQ_TIMER)) |
3910 | return IRQ_RETVAL(0); | |
3911 | ||
4db0ee17 AA |
3912 | nv_msi_workaround(np); |
3913 | ||
9589c77a AA |
3914 | spin_lock(&np->lock); |
3915 | np->intr_test = 1; | |
3916 | spin_unlock(&np->lock); | |
3917 | ||
9589c77a AA |
3918 | return IRQ_RETVAL(1); |
3919 | } | |
3920 | ||
7a1854b7 AA |
3921 | static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) |
3922 | { | |
3923 | u8 __iomem *base = get_hwbase(dev); | |
3924 | int i; | |
3925 | u32 msixmap = 0; | |
3926 | ||
3927 | /* Each interrupt bit can be mapped to a MSIX vector (4 bits). | |
3928 | * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents | |
3929 | * the remaining 8 interrupts. | |
3930 | */ | |
3931 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3932 | if ((irqmask >> i) & 0x1) |
7a1854b7 | 3933 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3934 | } |
3935 | writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0); | |
3936 | ||
3937 | msixmap = 0; | |
3938 | for (i = 0; i < 8; i++) { | |
78aea4fc | 3939 | if ((irqmask >> (i + 8)) & 0x1) |
7a1854b7 | 3940 | msixmap |= vector << (i << 2); |
7a1854b7 AA |
3941 | } |
3942 | writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1); | |
3943 | } | |
3944 | ||
9589c77a | 3945 | static int nv_request_irq(struct net_device *dev, int intr_test) |
7a1854b7 AA |
3946 | { |
3947 | struct fe_priv *np = get_nvpriv(dev); | |
3948 | u8 __iomem *base = get_hwbase(dev); | |
d9bd00a1 | 3949 | int ret; |
7a1854b7 | 3950 | int i; |
86b22b0d AA |
3951 | irqreturn_t (*handler)(int foo, void *data); |
3952 | ||
3953 | if (intr_test) { | |
3954 | handler = nv_nic_irq_test; | |
3955 | } else { | |
36b30ea9 | 3956 | if (nv_optimized(np)) |
86b22b0d AA |
3957 | handler = nv_nic_irq_optimized; |
3958 | else | |
3959 | handler = nv_nic_irq; | |
3960 | } | |
7a1854b7 AA |
3961 | |
3962 | if (np->msi_flags & NV_MSI_X_CAPABLE) { | |
78aea4fc | 3963 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 3964 | np->msi_x_entry[i].entry = i; |
04698ef3 AG |
3965 | ret = pci_enable_msix_range(np->pci_dev, |
3966 | np->msi_x_entry, | |
3967 | np->msi_flags & NV_MSI_X_VECTORS_MASK, | |
3968 | np->msi_flags & NV_MSI_X_VECTORS_MASK); | |
3969 | if (ret > 0) { | |
7a1854b7 | 3970 | np->msi_flags |= NV_MSI_X_ENABLED; |
9589c77a | 3971 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) { |
7a1854b7 | 3972 | /* Request irq for rx handling */ |
ddb213f0 | 3973 | sprintf(np->name_rx, "%s-rx", dev->name); |
61c9471e AG |
3974 | ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, |
3975 | nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev); | |
3976 | if (ret) { | |
1d397f36 JP |
3977 | netdev_info(dev, |
3978 | "request_irq failed for rx %d\n", | |
3979 | ret); | |
7a1854b7 AA |
3980 | pci_disable_msix(np->pci_dev); |
3981 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3982 | goto out_err; | |
3983 | } | |
3984 | /* Request irq for tx handling */ | |
ddb213f0 | 3985 | sprintf(np->name_tx, "%s-tx", dev->name); |
61c9471e AG |
3986 | ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, |
3987 | nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev); | |
3988 | if (ret) { | |
1d397f36 JP |
3989 | netdev_info(dev, |
3990 | "request_irq failed for tx %d\n", | |
3991 | ret); | |
7a1854b7 AA |
3992 | pci_disable_msix(np->pci_dev); |
3993 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
3994 | goto out_free_rx; | |
3995 | } | |
3996 | /* Request irq for link and timer handling */ | |
ddb213f0 | 3997 | sprintf(np->name_other, "%s-other", dev->name); |
61c9471e AG |
3998 | ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, |
3999 | nv_nic_irq_other, IRQF_SHARED, np->name_other, dev); | |
4000 | if (ret) { | |
1d397f36 JP |
4001 | netdev_info(dev, |
4002 | "request_irq failed for link %d\n", | |
4003 | ret); | |
7a1854b7 AA |
4004 | pci_disable_msix(np->pci_dev); |
4005 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
4006 | goto out_free_tx; | |
4007 | } | |
4008 | /* map interrupts to their respective vector */ | |
4009 | writel(0, base + NvRegMSIXMap0); | |
4010 | writel(0, base + NvRegMSIXMap1); | |
4011 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); | |
4012 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); | |
4013 | set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); | |
4014 | } else { | |
4015 | /* Request irq for all interrupts */ | |
61c9471e AG |
4016 | ret = request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, |
4017 | handler, IRQF_SHARED, dev->name, dev); | |
4018 | if (ret) { | |
1d397f36 JP |
4019 | netdev_info(dev, |
4020 | "request_irq failed %d\n", | |
4021 | ret); | |
7a1854b7 AA |
4022 | pci_disable_msix(np->pci_dev); |
4023 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
4024 | goto out_err; | |
4025 | } | |
4026 | ||
4027 | /* map interrupts to vector 0 */ | |
4028 | writel(0, base + NvRegMSIXMap0); | |
4029 | writel(0, base + NvRegMSIXMap1); | |
4030 | } | |
89328783 | 4031 | netdev_info(dev, "MSI-X enabled\n"); |
d9bd00a1 | 4032 | return 0; |
7a1854b7 AA |
4033 | } |
4034 | } | |
d9bd00a1 | 4035 | if (np->msi_flags & NV_MSI_CAPABLE) { |
34cf97eb SJ |
4036 | ret = pci_enable_msi(np->pci_dev); |
4037 | if (ret == 0) { | |
7a1854b7 | 4038 | np->msi_flags |= NV_MSI_ENABLED; |
61c9471e AG |
4039 | ret = request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev); |
4040 | if (ret) { | |
1d397f36 JP |
4041 | netdev_info(dev, "request_irq failed %d\n", |
4042 | ret); | |
7a1854b7 AA |
4043 | pci_disable_msi(np->pci_dev); |
4044 | np->msi_flags &= ~NV_MSI_ENABLED; | |
4045 | goto out_err; | |
4046 | } | |
4047 | ||
4048 | /* map interrupts to vector 0 */ | |
4049 | writel(0, base + NvRegMSIMap0); | |
4050 | writel(0, base + NvRegMSIMap1); | |
4051 | /* enable msi vector 0 */ | |
4052 | writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); | |
89328783 | 4053 | netdev_info(dev, "MSI enabled\n"); |
d9bd00a1 | 4054 | return 0; |
7a1854b7 AA |
4055 | } |
4056 | } | |
9589c77a | 4057 | |
d9bd00a1 AG |
4058 | if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) |
4059 | goto out_err; | |
7a1854b7 AA |
4060 | |
4061 | return 0; | |
4062 | out_free_tx: | |
4063 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev); | |
4064 | out_free_rx: | |
4065 | free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev); | |
4066 | out_err: | |
4067 | return 1; | |
4068 | } | |
4069 | ||
4070 | static void nv_free_irq(struct net_device *dev) | |
4071 | { | |
4072 | struct fe_priv *np = get_nvpriv(dev); | |
4073 | int i; | |
4074 | ||
4075 | if (np->msi_flags & NV_MSI_X_ENABLED) { | |
78aea4fc | 4076 | for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) |
7a1854b7 | 4077 | free_irq(np->msi_x_entry[i].vector, dev); |
7a1854b7 AA |
4078 | pci_disable_msix(np->pci_dev); |
4079 | np->msi_flags &= ~NV_MSI_X_ENABLED; | |
4080 | } else { | |
4081 | free_irq(np->pci_dev->irq, dev); | |
4082 | if (np->msi_flags & NV_MSI_ENABLED) { | |
4083 | pci_disable_msi(np->pci_dev); | |
4084 | np->msi_flags &= ~NV_MSI_ENABLED; | |
4085 | } | |
4086 | } | |
4087 | } | |
4088 | ||
d9935679 | 4089 | static void nv_do_nic_poll(struct timer_list *t) |
1da177e4 | 4090 | { |
d9935679 KC |
4091 | struct fe_priv *np = from_timer(np, t, nic_poll); |
4092 | struct net_device *dev = np->dev; | |
1da177e4 | 4093 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 | 4094 | u32 mask = 0; |
0b7c8743 NH |
4095 | unsigned long flags; |
4096 | unsigned int irq = 0; | |
1da177e4 | 4097 | |
1da177e4 | 4098 | /* |
d33a73c8 | 4099 | * First disable irq(s) and then |
1da177e4 LT |
4100 | * reenable interrupts on the nic, we have to do this before calling |
4101 | * nv_nic_irq because that may decide to do otherwise | |
4102 | */ | |
d33a73c8 | 4103 | |
84b3932b AA |
4104 | if (!using_multi_irqs(dev)) { |
4105 | if (np->msi_flags & NV_MSI_X_ENABLED) | |
0b7c8743 | 4106 | irq = np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector; |
84b3932b | 4107 | else |
0b7c8743 | 4108 | irq = np->pci_dev->irq; |
d33a73c8 AA |
4109 | mask = np->irqmask; |
4110 | } else { | |
4111 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
0b7c8743 | 4112 | irq = np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector; |
d33a73c8 AA |
4113 | mask |= NVREG_IRQ_RX_ALL; |
4114 | } | |
4115 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
0b7c8743 | 4116 | irq = np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector; |
d33a73c8 AA |
4117 | mask |= NVREG_IRQ_TX_ALL; |
4118 | } | |
4119 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
0b7c8743 | 4120 | irq = np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector; |
d33a73c8 AA |
4121 | mask |= NVREG_IRQ_OTHER; |
4122 | } | |
4123 | } | |
0b7c8743 NH |
4124 | |
4125 | disable_irq_nosync_lockdep_irqsave(irq, &flags); | |
4126 | synchronize_irq(irq); | |
a7475906 | 4127 | |
c5cf9101 AA |
4128 | if (np->recover_error) { |
4129 | np->recover_error = 0; | |
1d397f36 | 4130 | netdev_info(dev, "MAC in recoverable error state\n"); |
c5cf9101 AA |
4131 | if (netif_running(dev)) { |
4132 | netif_tx_lock_bh(dev); | |
e308a5d8 | 4133 | netif_addr_lock(dev); |
c5cf9101 AA |
4134 | spin_lock(&np->lock); |
4135 | /* stop engines */ | |
36b30ea9 | 4136 | nv_stop_rxtx(dev); |
daa91a9d AA |
4137 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
4138 | nv_mac_reset(dev); | |
c5cf9101 AA |
4139 | nv_txrx_reset(dev); |
4140 | /* drain rx queue */ | |
36b30ea9 | 4141 | nv_drain_rxtx(dev); |
c5cf9101 AA |
4142 | /* reinit driver view of the rx queue */ |
4143 | set_bufsize(dev); | |
4144 | if (nv_init_ring(dev)) { | |
4145 | if (!np->in_shutdown) | |
4146 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4147 | } | |
4148 | /* reinit nic view of the rx queue */ | |
4149 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4150 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4151 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
c5cf9101 AA |
4152 | base + NvRegRingSizes); |
4153 | pci_push(base); | |
4154 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4155 | pci_push(base); | |
daa91a9d AA |
4156 | /* clear interrupts */ |
4157 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
4158 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
4159 | else | |
4160 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
c5cf9101 AA |
4161 | |
4162 | /* restart rx engine */ | |
36b30ea9 | 4163 | nv_start_rxtx(dev); |
c5cf9101 | 4164 | spin_unlock(&np->lock); |
e308a5d8 | 4165 | netif_addr_unlock(dev); |
c5cf9101 AA |
4166 | netif_tx_unlock_bh(dev); |
4167 | } | |
4168 | } | |
4169 | ||
d33a73c8 | 4170 | writel(mask, base + NvRegIrqMask); |
1da177e4 | 4171 | pci_push(base); |
d33a73c8 | 4172 | |
84b3932b | 4173 | if (!using_multi_irqs(dev)) { |
79d30a58 | 4174 | np->nic_poll_irq = 0; |
36b30ea9 | 4175 | if (nv_optimized(np)) |
fcc5f266 AA |
4176 | nv_nic_irq_optimized(0, dev); |
4177 | else | |
4178 | nv_nic_irq(0, dev); | |
d33a73c8 AA |
4179 | } else { |
4180 | if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { | |
79d30a58 | 4181 | np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL; |
7d12e780 | 4182 | nv_nic_irq_rx(0, dev); |
d33a73c8 AA |
4183 | } |
4184 | if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { | |
79d30a58 | 4185 | np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL; |
7d12e780 | 4186 | nv_nic_irq_tx(0, dev); |
d33a73c8 AA |
4187 | } |
4188 | if (np->nic_poll_irq & NVREG_IRQ_OTHER) { | |
79d30a58 | 4189 | np->nic_poll_irq &= ~NVREG_IRQ_OTHER; |
7d12e780 | 4190 | nv_nic_irq_other(0, dev); |
d33a73c8 AA |
4191 | } |
4192 | } | |
79d30a58 | 4193 | |
0b7c8743 | 4194 | enable_irq_lockdep_irqrestore(irq, &flags); |
1da177e4 LT |
4195 | } |
4196 | ||
2918c35d MS |
4197 | #ifdef CONFIG_NET_POLL_CONTROLLER |
4198 | static void nv_poll_controller(struct net_device *dev) | |
4199 | { | |
d9935679 KC |
4200 | struct fe_priv *np = netdev_priv(dev); |
4201 | ||
4202 | nv_do_nic_poll(&np->nic_poll); | |
2918c35d MS |
4203 | } |
4204 | #endif | |
4205 | ||
d9935679 | 4206 | static void nv_do_stats_poll(struct timer_list *t) |
f5d827ae | 4207 | __acquires(&netdev_priv(dev)->hwstats_lock) |
4208 | __releases(&netdev_priv(dev)->hwstats_lock) | |
52da3578 | 4209 | { |
d9935679 KC |
4210 | struct fe_priv *np = from_timer(np, t, stats_poll); |
4211 | struct net_device *dev = np->dev; | |
52da3578 | 4212 | |
f5d827ae | 4213 | /* If lock is currently taken, the stats are being refreshed |
4214 | * and hence fresh enough */ | |
4215 | if (spin_trylock(&np->hwstats_lock)) { | |
4216 | nv_update_stats(dev); | |
4217 | spin_unlock(&np->hwstats_lock); | |
4218 | } | |
52da3578 AA |
4219 | |
4220 | if (!np->in_shutdown) | |
bfebbb88 DD |
4221 | mod_timer(&np->stats_poll, |
4222 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 AA |
4223 | } |
4224 | ||
1da177e4 LT |
4225 | static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
4226 | { | |
ac9c1897 | 4227 | struct fe_priv *np = netdev_priv(dev); |
68aad78c RJ |
4228 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
4229 | strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version)); | |
4230 | strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); | |
1da177e4 LT |
4231 | } |
4232 | ||
4233 | static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4234 | { | |
ac9c1897 | 4235 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
4236 | wolinfo->supported = WAKE_MAGIC; |
4237 | ||
4238 | spin_lock_irq(&np->lock); | |
4239 | if (np->wolenabled) | |
4240 | wolinfo->wolopts = WAKE_MAGIC; | |
4241 | spin_unlock_irq(&np->lock); | |
4242 | } | |
4243 | ||
4244 | static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo) | |
4245 | { | |
ac9c1897 | 4246 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 4247 | u8 __iomem *base = get_hwbase(dev); |
c42d9df9 | 4248 | u32 flags = 0; |
1da177e4 | 4249 | |
1da177e4 | 4250 | if (wolinfo->wolopts == 0) { |
1da177e4 | 4251 | np->wolenabled = 0; |
c42d9df9 | 4252 | } else if (wolinfo->wolopts & WAKE_MAGIC) { |
1da177e4 | 4253 | np->wolenabled = 1; |
c42d9df9 AA |
4254 | flags = NVREG_WAKEUPFLAGS_ENABLE; |
4255 | } | |
4256 | if (netif_running(dev)) { | |
4257 | spin_lock_irq(&np->lock); | |
4258 | writel(flags, base + NvRegWakeUpFlags); | |
4259 | spin_unlock_irq(&np->lock); | |
1da177e4 | 4260 | } |
dba5a68a | 4261 | device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled); |
1da177e4 LT |
4262 | return 0; |
4263 | } | |
4264 | ||
0fa9e289 PR |
4265 | static int nv_get_link_ksettings(struct net_device *dev, |
4266 | struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
4267 | { |
4268 | struct fe_priv *np = netdev_priv(dev); | |
0fa9e289 | 4269 | u32 speed, supported, advertising; |
1da177e4 LT |
4270 | int adv; |
4271 | ||
4272 | spin_lock_irq(&np->lock); | |
0fa9e289 | 4273 | cmd->base.port = PORT_MII; |
1da177e4 LT |
4274 | if (!netif_running(dev)) { |
4275 | /* We do not track link speed / duplex setting if the | |
4276 | * interface is disabled. Force a link check */ | |
f9430a01 | 4277 | if (nv_update_linkspeed(dev)) { |
5d826b7b | 4278 | netif_carrier_on(dev); |
f9430a01 | 4279 | } else { |
5d826b7b | 4280 | netif_carrier_off(dev); |
f9430a01 | 4281 | } |
1da177e4 | 4282 | } |
f9430a01 AA |
4283 | |
4284 | if (netif_carrier_ok(dev)) { | |
78aea4fc | 4285 | switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) { |
1da177e4 | 4286 | case NVREG_LINKSPEED_10: |
70739497 | 4287 | speed = SPEED_10; |
1da177e4 LT |
4288 | break; |
4289 | case NVREG_LINKSPEED_100: | |
70739497 | 4290 | speed = SPEED_100; |
1da177e4 LT |
4291 | break; |
4292 | case NVREG_LINKSPEED_1000: | |
70739497 DD |
4293 | speed = SPEED_1000; |
4294 | break; | |
4295 | default: | |
4296 | speed = -1; | |
1da177e4 | 4297 | break; |
f9430a01 | 4298 | } |
0fa9e289 | 4299 | cmd->base.duplex = DUPLEX_HALF; |
f9430a01 | 4300 | if (np->duplex) |
0fa9e289 | 4301 | cmd->base.duplex = DUPLEX_FULL; |
f9430a01 | 4302 | } else { |
537fae01 | 4303 | speed = SPEED_UNKNOWN; |
0fa9e289 | 4304 | cmd->base.duplex = DUPLEX_UNKNOWN; |
1da177e4 | 4305 | } |
0fa9e289 PR |
4306 | cmd->base.speed = speed; |
4307 | cmd->base.autoneg = np->autoneg; | |
1da177e4 | 4308 | |
0fa9e289 | 4309 | advertising = ADVERTISED_MII; |
1da177e4 | 4310 | if (np->autoneg) { |
0fa9e289 | 4311 | advertising |= ADVERTISED_Autoneg; |
1da177e4 | 4312 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); |
f9430a01 | 4313 | if (adv & ADVERTISE_10HALF) |
0fa9e289 | 4314 | advertising |= ADVERTISED_10baseT_Half; |
f9430a01 | 4315 | if (adv & ADVERTISE_10FULL) |
0fa9e289 | 4316 | advertising |= ADVERTISED_10baseT_Full; |
f9430a01 | 4317 | if (adv & ADVERTISE_100HALF) |
0fa9e289 | 4318 | advertising |= ADVERTISED_100baseT_Half; |
f9430a01 | 4319 | if (adv & ADVERTISE_100FULL) |
0fa9e289 | 4320 | advertising |= ADVERTISED_100baseT_Full; |
f9430a01 AA |
4321 | if (np->gigabit == PHY_GIGABIT) { |
4322 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); | |
4323 | if (adv & ADVERTISE_1000FULL) | |
0fa9e289 | 4324 | advertising |= ADVERTISED_1000baseT_Full; |
f9430a01 | 4325 | } |
1da177e4 | 4326 | } |
0fa9e289 | 4327 | supported = (SUPPORTED_Autoneg | |
1da177e4 LT |
4328 | SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | |
4329 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | | |
4330 | SUPPORTED_MII); | |
4331 | if (np->gigabit == PHY_GIGABIT) | |
0fa9e289 | 4332 | supported |= SUPPORTED_1000baseT_Full; |
1da177e4 | 4333 | |
0fa9e289 PR |
4334 | cmd->base.phy_address = np->phyaddr; |
4335 | ||
4336 | ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, | |
4337 | supported); | |
4338 | ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, | |
4339 | advertising); | |
1da177e4 LT |
4340 | |
4341 | /* ignore maxtxpkt, maxrxpkt for now */ | |
4342 | spin_unlock_irq(&np->lock); | |
4343 | return 0; | |
4344 | } | |
4345 | ||
0fa9e289 PR |
4346 | static int nv_set_link_ksettings(struct net_device *dev, |
4347 | const struct ethtool_link_ksettings *cmd) | |
1da177e4 LT |
4348 | { |
4349 | struct fe_priv *np = netdev_priv(dev); | |
0fa9e289 PR |
4350 | u32 speed = cmd->base.speed; |
4351 | u32 advertising; | |
1da177e4 | 4352 | |
0fa9e289 PR |
4353 | ethtool_convert_link_mode_to_legacy_u32(&advertising, |
4354 | cmd->link_modes.advertising); | |
4355 | ||
4356 | if (cmd->base.port != PORT_MII) | |
1da177e4 | 4357 | return -EINVAL; |
0fa9e289 | 4358 | if (cmd->base.phy_address != np->phyaddr) { |
1da177e4 LT |
4359 | /* TODO: support switching between multiple phys. Should be |
4360 | * trivial, but not enabled due to lack of test hardware. */ | |
4361 | return -EINVAL; | |
4362 | } | |
0fa9e289 | 4363 | if (cmd->base.autoneg == AUTONEG_ENABLE) { |
1da177e4 LT |
4364 | u32 mask; |
4365 | ||
4366 | mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
4367 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full; | |
4368 | if (np->gigabit == PHY_GIGABIT) | |
4369 | mask |= ADVERTISED_1000baseT_Full; | |
4370 | ||
0fa9e289 | 4371 | if ((advertising & mask) == 0) |
1da177e4 LT |
4372 | return -EINVAL; |
4373 | ||
0fa9e289 | 4374 | } else if (cmd->base.autoneg == AUTONEG_DISABLE) { |
1da177e4 | 4375 | /* Note: autonegotiation disable, speed 1000 intentionally |
25985edc | 4376 | * forbidden - no one should need that. */ |
1da177e4 | 4377 | |
25db0338 | 4378 | if (speed != SPEED_10 && speed != SPEED_100) |
1da177e4 | 4379 | return -EINVAL; |
0fa9e289 PR |
4380 | if (cmd->base.duplex != DUPLEX_HALF && |
4381 | cmd->base.duplex != DUPLEX_FULL) | |
1da177e4 LT |
4382 | return -EINVAL; |
4383 | } else { | |
4384 | return -EINVAL; | |
4385 | } | |
4386 | ||
f9430a01 AA |
4387 | netif_carrier_off(dev); |
4388 | if (netif_running(dev)) { | |
97bff095 TD |
4389 | unsigned long flags; |
4390 | ||
f9430a01 | 4391 | nv_disable_irq(dev); |
58dfd9c1 | 4392 | netif_tx_lock_bh(dev); |
e308a5d8 | 4393 | netif_addr_lock(dev); |
97bff095 TD |
4394 | /* with plain spinlock lockdep complains */ |
4395 | spin_lock_irqsave(&np->lock, flags); | |
f9430a01 | 4396 | /* stop engines */ |
97bff095 TD |
4397 | /* FIXME: |
4398 | * this can take some time, and interrupts are disabled | |
4399 | * due to spin_lock_irqsave, but let's hope no daemon | |
4400 | * is going to change the settings very often... | |
4401 | * Worst case: | |
4402 | * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX | |
4403 | * + some minor delays, which is up to a second approximately | |
4404 | */ | |
36b30ea9 | 4405 | nv_stop_rxtx(dev); |
97bff095 | 4406 | spin_unlock_irqrestore(&np->lock, flags); |
e308a5d8 | 4407 | netif_addr_unlock(dev); |
58dfd9c1 | 4408 | netif_tx_unlock_bh(dev); |
f9430a01 AA |
4409 | } |
4410 | ||
0fa9e289 | 4411 | if (cmd->base.autoneg == AUTONEG_ENABLE) { |
1da177e4 LT |
4412 | int adv, bmcr; |
4413 | ||
4414 | np->autoneg = 1; | |
4415 | ||
4416 | /* advertise only what has been requested */ | |
4417 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4418 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
0fa9e289 | 4419 | if (advertising & ADVERTISED_10baseT_Half) |
1da177e4 | 4420 | adv |= ADVERTISE_10HALF; |
0fa9e289 | 4421 | if (advertising & ADVERTISED_10baseT_Full) |
b6d0773f | 4422 | adv |= ADVERTISE_10FULL; |
0fa9e289 | 4423 | if (advertising & ADVERTISED_100baseT_Half) |
1da177e4 | 4424 | adv |= ADVERTISE_100HALF; |
0fa9e289 | 4425 | if (advertising & ADVERTISED_100baseT_Full) |
b6d0773f | 4426 | adv |= ADVERTISE_100FULL; |
25985edc | 4427 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4428 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4429 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4430 | adv |= ADVERTISE_PAUSE_ASYM; | |
1da177e4 LT |
4431 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4432 | ||
4433 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4434 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4435 | adv &= ~ADVERTISE_1000FULL; |
0fa9e289 | 4436 | if (advertising & ADVERTISED_1000baseT_Full) |
1da177e4 | 4437 | adv |= ADVERTISE_1000FULL; |
eb91f61b | 4438 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4439 | } |
4440 | ||
f9430a01 | 4441 | if (netif_running(dev)) |
1d397f36 | 4442 | netdev_info(dev, "link down\n"); |
1da177e4 | 4443 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4444 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4445 | bmcr |= BMCR_ANENABLE; | |
4446 | /* reset the phy in order for settings to stick, | |
4447 | * and cause autoneg to start */ | |
4448 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4449 | netdev_info(dev, "phy reset failed\n"); |
edf7e5ec AA |
4450 | return -EINVAL; |
4451 | } | |
4452 | } else { | |
4453 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4454 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4455 | } | |
1da177e4 LT |
4456 | } else { |
4457 | int adv, bmcr; | |
4458 | ||
4459 | np->autoneg = 0; | |
4460 | ||
4461 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
eb91f61b | 4462 | adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); |
0fa9e289 | 4463 | if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF) |
1da177e4 | 4464 | adv |= ADVERTISE_10HALF; |
0fa9e289 | 4465 | if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL) |
b6d0773f | 4466 | adv |= ADVERTISE_10FULL; |
0fa9e289 | 4467 | if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF) |
1da177e4 | 4468 | adv |= ADVERTISE_100HALF; |
0fa9e289 | 4469 | if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL) |
b6d0773f AA |
4470 | adv |= ADVERTISE_100FULL; |
4471 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
25985edc | 4472 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4473 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4474 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4475 | } | |
4476 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) { | |
4477 | adv |= ADVERTISE_PAUSE_ASYM; | |
4478 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4479 | } | |
1da177e4 LT |
4480 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); |
4481 | np->fixed_mode = adv; | |
4482 | ||
4483 | if (np->gigabit == PHY_GIGABIT) { | |
eb91f61b | 4484 | adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); |
1da177e4 | 4485 | adv &= ~ADVERTISE_1000FULL; |
eb91f61b | 4486 | mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); |
1da177e4 LT |
4487 | } |
4488 | ||
4489 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
f9430a01 AA |
4490 | bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX); |
4491 | if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL)) | |
1da177e4 | 4492 | bmcr |= BMCR_FULLDPLX; |
f9430a01 | 4493 | if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL)) |
1da177e4 | 4494 | bmcr |= BMCR_SPEED100; |
f9430a01 | 4495 | if (np->phy_oui == PHY_OUI_MARVELL) { |
edf7e5ec AA |
4496 | /* reset the phy in order for forced mode settings to stick */ |
4497 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4498 | netdev_info(dev, "phy reset failed\n"); |
f9430a01 AA |
4499 | return -EINVAL; |
4500 | } | |
edf7e5ec AA |
4501 | } else { |
4502 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4503 | if (netif_running(dev)) { | |
4504 | /* Wait a bit and then reconfigure the nic. */ | |
4505 | udelay(10); | |
4506 | nv_linkchange(dev); | |
4507 | } | |
1da177e4 LT |
4508 | } |
4509 | } | |
f9430a01 AA |
4510 | |
4511 | if (netif_running(dev)) { | |
36b30ea9 | 4512 | nv_start_rxtx(dev); |
f9430a01 AA |
4513 | nv_enable_irq(dev); |
4514 | } | |
1da177e4 LT |
4515 | |
4516 | return 0; | |
4517 | } | |
4518 | ||
dc8216c1 | 4519 | #define FORCEDETH_REGS_VER 1 |
dc8216c1 MS |
4520 | |
4521 | static int nv_get_regs_len(struct net_device *dev) | |
4522 | { | |
86a0f043 AA |
4523 | struct fe_priv *np = netdev_priv(dev); |
4524 | return np->register_size; | |
dc8216c1 MS |
4525 | } |
4526 | ||
4527 | static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) | |
4528 | { | |
ac9c1897 | 4529 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4530 | u8 __iomem *base = get_hwbase(dev); |
4531 | u32 *rbuf = buf; | |
4532 | int i; | |
4533 | ||
4534 | regs->version = FORCEDETH_REGS_VER; | |
4535 | spin_lock_irq(&np->lock); | |
ba9aa134 | 4536 | for (i = 0; i < np->register_size/sizeof(u32); i++) |
dc8216c1 MS |
4537 | rbuf[i] = readl(base + i*sizeof(u32)); |
4538 | spin_unlock_irq(&np->lock); | |
4539 | } | |
4540 | ||
4541 | static int nv_nway_reset(struct net_device *dev) | |
4542 | { | |
ac9c1897 | 4543 | struct fe_priv *np = netdev_priv(dev); |
dc8216c1 MS |
4544 | int ret; |
4545 | ||
dc8216c1 MS |
4546 | if (np->autoneg) { |
4547 | int bmcr; | |
4548 | ||
f9430a01 AA |
4549 | netif_carrier_off(dev); |
4550 | if (netif_running(dev)) { | |
4551 | nv_disable_irq(dev); | |
58dfd9c1 | 4552 | netif_tx_lock_bh(dev); |
e308a5d8 | 4553 | netif_addr_lock(dev); |
f9430a01 AA |
4554 | spin_lock(&np->lock); |
4555 | /* stop engines */ | |
36b30ea9 | 4556 | nv_stop_rxtx(dev); |
f9430a01 | 4557 | spin_unlock(&np->lock); |
e308a5d8 | 4558 | netif_addr_unlock(dev); |
58dfd9c1 | 4559 | netif_tx_unlock_bh(dev); |
1d397f36 | 4560 | netdev_info(dev, "link down\n"); |
f9430a01 AA |
4561 | } |
4562 | ||
dc8216c1 | 4563 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
edf7e5ec AA |
4564 | if (np->phy_model == PHY_MODEL_MARVELL_E3016) { |
4565 | bmcr |= BMCR_ANENABLE; | |
4566 | /* reset the phy in order for settings to stick*/ | |
4567 | if (phy_reset(dev, bmcr)) { | |
1d397f36 | 4568 | netdev_info(dev, "phy reset failed\n"); |
edf7e5ec AA |
4569 | return -EINVAL; |
4570 | } | |
4571 | } else { | |
4572 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4573 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4574 | } | |
dc8216c1 | 4575 | |
f9430a01 | 4576 | if (netif_running(dev)) { |
36b30ea9 | 4577 | nv_start_rxtx(dev); |
f9430a01 AA |
4578 | nv_enable_irq(dev); |
4579 | } | |
dc8216c1 MS |
4580 | ret = 0; |
4581 | } else { | |
4582 | ret = -EINVAL; | |
4583 | } | |
dc8216c1 MS |
4584 | |
4585 | return ret; | |
4586 | } | |
4587 | ||
eafa59f6 AA |
4588 | static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) |
4589 | { | |
4590 | struct fe_priv *np = netdev_priv(dev); | |
4591 | ||
4592 | ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; | |
eafa59f6 AA |
4593 | ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3; |
4594 | ||
4595 | ring->rx_pending = np->rx_ring_size; | |
eafa59f6 AA |
4596 | ring->tx_pending = np->tx_ring_size; |
4597 | } | |
4598 | ||
4599 | static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring) | |
4600 | { | |
4601 | struct fe_priv *np = netdev_priv(dev); | |
4602 | u8 __iomem *base = get_hwbase(dev); | |
761fcd9e | 4603 | u8 *rxtx_ring, *rx_skbuff, *tx_skbuff; |
eafa59f6 AA |
4604 | dma_addr_t ring_addr; |
4605 | ||
4606 | if (ring->rx_pending < RX_RING_MIN || | |
4607 | ring->tx_pending < TX_RING_MIN || | |
4608 | ring->rx_mini_pending != 0 || | |
4609 | ring->rx_jumbo_pending != 0 || | |
4610 | (np->desc_ver == DESC_VER_1 && | |
4611 | (ring->rx_pending > RING_MAX_DESC_VER_1 || | |
4612 | ring->tx_pending > RING_MAX_DESC_VER_1)) || | |
4613 | (np->desc_ver != DESC_VER_1 && | |
4614 | (ring->rx_pending > RING_MAX_DESC_VER_2_3 || | |
4615 | ring->tx_pending > RING_MAX_DESC_VER_2_3))) { | |
4616 | return -EINVAL; | |
4617 | } | |
4618 | ||
4619 | /* allocate new rings */ | |
36b30ea9 | 4620 | if (!nv_optimized(np)) { |
e8992e40 ZY |
4621 | rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev, |
4622 | sizeof(struct ring_desc) * | |
4623 | (ring->rx_pending + | |
4624 | ring->tx_pending), | |
4625 | &ring_addr, GFP_ATOMIC); | |
eafa59f6 | 4626 | } else { |
e8992e40 ZY |
4627 | rxtx_ring = dma_alloc_coherent(&np->pci_dev->dev, |
4628 | sizeof(struct ring_desc_ex) * | |
4629 | (ring->rx_pending + | |
4630 | ring->tx_pending), | |
4631 | &ring_addr, GFP_ATOMIC); | |
eafa59f6 | 4632 | } |
6da2ec56 KC |
4633 | rx_skbuff = kmalloc_array(ring->rx_pending, sizeof(struct nv_skb_map), |
4634 | GFP_KERNEL); | |
4635 | tx_skbuff = kmalloc_array(ring->tx_pending, sizeof(struct nv_skb_map), | |
4636 | GFP_KERNEL); | |
761fcd9e | 4637 | if (!rxtx_ring || !rx_skbuff || !tx_skbuff) { |
eafa59f6 | 4638 | /* fall back to old rings */ |
36b30ea9 | 4639 | if (!nv_optimized(np)) { |
f82a9352 | 4640 | if (rxtx_ring) |
e8992e40 ZY |
4641 | dma_free_coherent(&np->pci_dev->dev, |
4642 | sizeof(struct ring_desc) * | |
4643 | (ring->rx_pending + | |
4644 | ring->tx_pending), | |
4645 | rxtx_ring, ring_addr); | |
eafa59f6 AA |
4646 | } else { |
4647 | if (rxtx_ring) | |
e8992e40 ZY |
4648 | dma_free_coherent(&np->pci_dev->dev, |
4649 | sizeof(struct ring_desc_ex) * | |
4650 | (ring->rx_pending + | |
4651 | ring->tx_pending), | |
4652 | rxtx_ring, ring_addr); | |
eafa59f6 | 4653 | } |
9b03b06b SJ |
4654 | |
4655 | kfree(rx_skbuff); | |
4656 | kfree(tx_skbuff); | |
eafa59f6 AA |
4657 | goto exit; |
4658 | } | |
4659 | ||
4660 | if (netif_running(dev)) { | |
4661 | nv_disable_irq(dev); | |
08d93575 | 4662 | nv_napi_disable(dev); |
58dfd9c1 | 4663 | netif_tx_lock_bh(dev); |
e308a5d8 | 4664 | netif_addr_lock(dev); |
eafa59f6 AA |
4665 | spin_lock(&np->lock); |
4666 | /* stop engines */ | |
36b30ea9 | 4667 | nv_stop_rxtx(dev); |
eafa59f6 AA |
4668 | nv_txrx_reset(dev); |
4669 | /* drain queues */ | |
36b30ea9 | 4670 | nv_drain_rxtx(dev); |
eafa59f6 AA |
4671 | /* delete queues */ |
4672 | free_rings(dev); | |
4673 | } | |
4674 | ||
4675 | /* set new values */ | |
4676 | np->rx_ring_size = ring->rx_pending; | |
4677 | np->tx_ring_size = ring->tx_pending; | |
36b30ea9 JG |
4678 | |
4679 | if (!nv_optimized(np)) { | |
78aea4fc | 4680 | np->rx_ring.orig = (struct ring_desc *)rxtx_ring; |
eafa59f6 AA |
4681 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
4682 | } else { | |
78aea4fc | 4683 | np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring; |
eafa59f6 AA |
4684 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
4685 | } | |
78aea4fc SJ |
4686 | np->rx_skb = (struct nv_skb_map *)rx_skbuff; |
4687 | np->tx_skb = (struct nv_skb_map *)tx_skbuff; | |
eafa59f6 AA |
4688 | np->ring_addr = ring_addr; |
4689 | ||
761fcd9e AA |
4690 | memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size); |
4691 | memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size); | |
eafa59f6 AA |
4692 | |
4693 | if (netif_running(dev)) { | |
4694 | /* reinit driver view of the queues */ | |
4695 | set_bufsize(dev); | |
4696 | if (nv_init_ring(dev)) { | |
4697 | if (!np->in_shutdown) | |
4698 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
4699 | } | |
4700 | ||
4701 | /* reinit nic view of the queues */ | |
4702 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
4703 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 4704 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
eafa59f6 AA |
4705 | base + NvRegRingSizes); |
4706 | pci_push(base); | |
4707 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4708 | pci_push(base); | |
4709 | ||
4710 | /* restart engines */ | |
36b30ea9 | 4711 | nv_start_rxtx(dev); |
eafa59f6 | 4712 | spin_unlock(&np->lock); |
e308a5d8 | 4713 | netif_addr_unlock(dev); |
58dfd9c1 | 4714 | netif_tx_unlock_bh(dev); |
08d93575 | 4715 | nv_napi_enable(dev); |
eafa59f6 AA |
4716 | nv_enable_irq(dev); |
4717 | } | |
4718 | return 0; | |
4719 | exit: | |
4720 | return -ENOMEM; | |
4721 | } | |
4722 | ||
b6d0773f AA |
4723 | static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) |
4724 | { | |
4725 | struct fe_priv *np = netdev_priv(dev); | |
4726 | ||
4727 | pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0; | |
4728 | pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0; | |
4729 | pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0; | |
4730 | } | |
4731 | ||
4732 | static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause) | |
4733 | { | |
4734 | struct fe_priv *np = netdev_priv(dev); | |
4735 | int adv, bmcr; | |
4736 | ||
4737 | if ((!np->autoneg && np->duplex == 0) || | |
4738 | (np->autoneg && !pause->autoneg && np->duplex == 0)) { | |
1d397f36 | 4739 | netdev_info(dev, "can not set pause settings when forced link is in half duplex\n"); |
b6d0773f AA |
4740 | return -EINVAL; |
4741 | } | |
4742 | if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) { | |
1d397f36 | 4743 | netdev_info(dev, "hardware does not support tx pause frames\n"); |
b6d0773f AA |
4744 | return -EINVAL; |
4745 | } | |
4746 | ||
4747 | netif_carrier_off(dev); | |
4748 | if (netif_running(dev)) { | |
4749 | nv_disable_irq(dev); | |
58dfd9c1 | 4750 | netif_tx_lock_bh(dev); |
e308a5d8 | 4751 | netif_addr_lock(dev); |
b6d0773f AA |
4752 | spin_lock(&np->lock); |
4753 | /* stop engines */ | |
36b30ea9 | 4754 | nv_stop_rxtx(dev); |
b6d0773f | 4755 | spin_unlock(&np->lock); |
e308a5d8 | 4756 | netif_addr_unlock(dev); |
58dfd9c1 | 4757 | netif_tx_unlock_bh(dev); |
b6d0773f AA |
4758 | } |
4759 | ||
4760 | np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ); | |
4761 | if (pause->rx_pause) | |
4762 | np->pause_flags |= NV_PAUSEFRAME_RX_REQ; | |
4763 | if (pause->tx_pause) | |
4764 | np->pause_flags |= NV_PAUSEFRAME_TX_REQ; | |
4765 | ||
4766 | if (np->autoneg && pause->autoneg) { | |
4767 | np->pause_flags |= NV_PAUSEFRAME_AUTONEG; | |
4768 | ||
4769 | adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); | |
4770 | adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
25985edc | 4771 | if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */ |
b6d0773f AA |
4772 | adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
4773 | if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) | |
4774 | adv |= ADVERTISE_PAUSE_ASYM; | |
4775 | mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); | |
4776 | ||
4777 | if (netif_running(dev)) | |
1d397f36 | 4778 | netdev_info(dev, "link down\n"); |
b6d0773f AA |
4779 | bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); |
4780 | bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); | |
4781 | mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); | |
4782 | } else { | |
4783 | np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE); | |
4784 | if (pause->rx_pause) | |
4785 | np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE; | |
4786 | if (pause->tx_pause) | |
4787 | np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE; | |
4788 | ||
4789 | if (!netif_running(dev)) | |
4790 | nv_update_linkspeed(dev); | |
4791 | else | |
4792 | nv_update_pause(dev, np->pause_flags); | |
4793 | } | |
4794 | ||
4795 | if (netif_running(dev)) { | |
36b30ea9 | 4796 | nv_start_rxtx(dev); |
b6d0773f AA |
4797 | nv_enable_irq(dev); |
4798 | } | |
4799 | return 0; | |
4800 | } | |
4801 | ||
c8f44aff | 4802 | static int nv_set_loopback(struct net_device *dev, netdev_features_t features) |
e19df76a SH |
4803 | { |
4804 | struct fe_priv *np = netdev_priv(dev); | |
4805 | unsigned long flags; | |
4806 | u32 miicontrol; | |
4807 | int err, retval = 0; | |
4808 | ||
4809 | spin_lock_irqsave(&np->lock, flags); | |
4810 | miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
4811 | if (features & NETIF_F_LOOPBACK) { | |
4812 | if (miicontrol & BMCR_LOOPBACK) { | |
4813 | spin_unlock_irqrestore(&np->lock, flags); | |
4814 | netdev_info(dev, "Loopback already enabled\n"); | |
4815 | return 0; | |
4816 | } | |
4817 | nv_disable_irq(dev); | |
4818 | /* Turn on loopback mode */ | |
4819 | miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
4820 | err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); | |
4821 | if (err) { | |
4822 | retval = PHY_ERROR; | |
4823 | spin_unlock_irqrestore(&np->lock, flags); | |
4824 | phy_init(dev); | |
4825 | } else { | |
4826 | if (netif_running(dev)) { | |
4827 | /* Force 1000 Mbps full-duplex */ | |
4828 | nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, | |
4829 | 1); | |
4830 | /* Force link up */ | |
4831 | netif_carrier_on(dev); | |
4832 | } | |
4833 | spin_unlock_irqrestore(&np->lock, flags); | |
4834 | netdev_info(dev, | |
4835 | "Internal PHY loopback mode enabled.\n"); | |
4836 | } | |
4837 | } else { | |
4838 | if (!(miicontrol & BMCR_LOOPBACK)) { | |
4839 | spin_unlock_irqrestore(&np->lock, flags); | |
4840 | netdev_info(dev, "Loopback already disabled\n"); | |
4841 | return 0; | |
4842 | } | |
4843 | nv_disable_irq(dev); | |
4844 | /* Turn off loopback */ | |
4845 | spin_unlock_irqrestore(&np->lock, flags); | |
4846 | netdev_info(dev, "Internal PHY loopback mode disabled.\n"); | |
4847 | phy_init(dev); | |
4848 | } | |
4849 | msleep(500); | |
4850 | spin_lock_irqsave(&np->lock, flags); | |
4851 | nv_enable_irq(dev); | |
4852 | spin_unlock_irqrestore(&np->lock, flags); | |
4853 | ||
4854 | return retval; | |
4855 | } | |
4856 | ||
c8f44aff MM |
4857 | static netdev_features_t nv_fix_features(struct net_device *dev, |
4858 | netdev_features_t features) | |
5ed2616f | 4859 | { |
569e1463 | 4860 | /* vlan is dependent on rx checksum offload */ |
f646968f | 4861 | if (features & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX)) |
569e1463 MM |
4862 | features |= NETIF_F_RXCSUM; |
4863 | ||
4864 | return features; | |
5ed2616f AA |
4865 | } |
4866 | ||
c8f44aff | 4867 | static void nv_vlan_mode(struct net_device *dev, netdev_features_t features) |
3326c784 JP |
4868 | { |
4869 | struct fe_priv *np = get_nvpriv(dev); | |
4870 | ||
4871 | spin_lock_irq(&np->lock); | |
4872 | ||
f646968f | 4873 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
3326c784 JP |
4874 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP; |
4875 | else | |
4876 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; | |
4877 | ||
f646968f | 4878 | if (features & NETIF_F_HW_VLAN_CTAG_TX) |
3326c784 JP |
4879 | np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS; |
4880 | else | |
4881 | np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; | |
4882 | ||
4883 | writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
4884 | ||
4885 | spin_unlock_irq(&np->lock); | |
4886 | } | |
4887 | ||
c8f44aff | 4888 | static int nv_set_features(struct net_device *dev, netdev_features_t features) |
5ed2616f AA |
4889 | { |
4890 | struct fe_priv *np = netdev_priv(dev); | |
4891 | u8 __iomem *base = get_hwbase(dev); | |
c8f44aff | 4892 | netdev_features_t changed = dev->features ^ features; |
e19df76a SH |
4893 | int retval; |
4894 | ||
4895 | if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) { | |
4896 | retval = nv_set_loopback(dev, features); | |
4897 | if (retval != 0) | |
4898 | return retval; | |
4899 | } | |
5ed2616f | 4900 | |
569e1463 MM |
4901 | if (changed & NETIF_F_RXCSUM) { |
4902 | spin_lock_irq(&np->lock); | |
5ed2616f | 4903 | |
569e1463 MM |
4904 | if (features & NETIF_F_RXCSUM) |
4905 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; | |
4906 | else | |
4907 | np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; | |
5ed2616f | 4908 | |
569e1463 MM |
4909 | if (netif_running(dev)) |
4910 | writel(np->txrxctl_bits, base + NvRegTxRxControl); | |
5ed2616f | 4911 | |
569e1463 MM |
4912 | spin_unlock_irq(&np->lock); |
4913 | } | |
5ed2616f | 4914 | |
f646968f | 4915 | if (changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX)) |
3326c784 JP |
4916 | nv_vlan_mode(dev, features); |
4917 | ||
569e1463 | 4918 | return 0; |
5ed2616f AA |
4919 | } |
4920 | ||
b9f2c044 | 4921 | static int nv_get_sset_count(struct net_device *dev, int sset) |
52da3578 AA |
4922 | { |
4923 | struct fe_priv *np = netdev_priv(dev); | |
4924 | ||
b9f2c044 JG |
4925 | switch (sset) { |
4926 | case ETH_SS_TEST: | |
4927 | if (np->driver_data & DEV_HAS_TEST_EXTENDED) | |
4928 | return NV_TEST_COUNT_EXTENDED; | |
4929 | else | |
4930 | return NV_TEST_COUNT_BASE; | |
4931 | case ETH_SS_STATS: | |
8ed1454a AA |
4932 | if (np->driver_data & DEV_HAS_STATISTICS_V3) |
4933 | return NV_DEV_STATISTICS_V3_COUNT; | |
b9f2c044 JG |
4934 | else if (np->driver_data & DEV_HAS_STATISTICS_V2) |
4935 | return NV_DEV_STATISTICS_V2_COUNT; | |
8ed1454a AA |
4936 | else if (np->driver_data & DEV_HAS_STATISTICS_V1) |
4937 | return NV_DEV_STATISTICS_V1_COUNT; | |
b9f2c044 JG |
4938 | else |
4939 | return 0; | |
4940 | default: | |
4941 | return -EOPNOTSUPP; | |
4942 | } | |
52da3578 AA |
4943 | } |
4944 | ||
f5d827ae | 4945 | static void nv_get_ethtool_stats(struct net_device *dev, |
4946 | struct ethtool_stats *estats, u64 *buffer) | |
4947 | __acquires(&netdev_priv(dev)->hwstats_lock) | |
4948 | __releases(&netdev_priv(dev)->hwstats_lock) | |
52da3578 AA |
4949 | { |
4950 | struct fe_priv *np = netdev_priv(dev); | |
4951 | ||
f5d827ae | 4952 | spin_lock_bh(&np->hwstats_lock); |
4953 | nv_update_stats(dev); | |
4954 | memcpy(buffer, &np->estats, | |
4955 | nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64)); | |
4956 | spin_unlock_bh(&np->hwstats_lock); | |
9589c77a AA |
4957 | } |
4958 | ||
4959 | static int nv_link_test(struct net_device *dev) | |
4960 | { | |
4961 | struct fe_priv *np = netdev_priv(dev); | |
4962 | int mii_status; | |
4963 | ||
4964 | mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4965 | mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
4966 | ||
4967 | /* check phy link status */ | |
4968 | if (!(mii_status & BMSR_LSTATUS)) | |
4969 | return 0; | |
4970 | else | |
4971 | return 1; | |
4972 | } | |
4973 | ||
4974 | static int nv_register_test(struct net_device *dev) | |
4975 | { | |
4976 | u8 __iomem *base = get_hwbase(dev); | |
4977 | int i = 0; | |
4978 | u32 orig_read, new_read; | |
4979 | ||
4980 | do { | |
4981 | orig_read = readl(base + nv_registers_test[i].reg); | |
4982 | ||
4983 | /* xor with mask to toggle bits */ | |
4984 | orig_read ^= nv_registers_test[i].mask; | |
4985 | ||
4986 | writel(orig_read, base + nv_registers_test[i].reg); | |
4987 | ||
4988 | new_read = readl(base + nv_registers_test[i].reg); | |
4989 | ||
4990 | if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask)) | |
4991 | return 0; | |
4992 | ||
4993 | /* restore original value */ | |
4994 | orig_read ^= nv_registers_test[i].mask; | |
4995 | writel(orig_read, base + nv_registers_test[i].reg); | |
4996 | ||
4997 | } while (nv_registers_test[++i].reg != 0); | |
4998 | ||
4999 | return 1; | |
5000 | } | |
5001 | ||
5002 | static int nv_interrupt_test(struct net_device *dev) | |
5003 | { | |
5004 | struct fe_priv *np = netdev_priv(dev); | |
5005 | u8 __iomem *base = get_hwbase(dev); | |
5006 | int ret = 1; | |
5007 | int testcnt; | |
5008 | u32 save_msi_flags, save_poll_interval = 0; | |
5009 | ||
5010 | if (netif_running(dev)) { | |
5011 | /* free current irq */ | |
5012 | nv_free_irq(dev); | |
5013 | save_poll_interval = readl(base+NvRegPollingInterval); | |
5014 | } | |
5015 | ||
5016 | /* flag to test interrupt handler */ | |
5017 | np->intr_test = 0; | |
5018 | ||
5019 | /* setup test irq */ | |
5020 | save_msi_flags = np->msi_flags; | |
5021 | np->msi_flags &= ~NV_MSI_X_VECTORS_MASK; | |
5022 | np->msi_flags |= 0x001; /* setup 1 vector */ | |
5023 | if (nv_request_irq(dev, 1)) | |
5024 | return 0; | |
5025 | ||
5026 | /* setup timer interrupt */ | |
5027 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
5028 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
5029 | ||
5030 | nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
5031 | ||
5032 | /* wait for at least one interrupt */ | |
5033 | msleep(100); | |
5034 | ||
5035 | spin_lock_irq(&np->lock); | |
5036 | ||
5037 | /* flag should be set within ISR */ | |
5038 | testcnt = np->intr_test; | |
5039 | if (!testcnt) | |
5040 | ret = 2; | |
5041 | ||
5042 | nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); | |
5043 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) | |
5044 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); | |
5045 | else | |
5046 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); | |
5047 | ||
5048 | spin_unlock_irq(&np->lock); | |
5049 | ||
5050 | nv_free_irq(dev); | |
5051 | ||
5052 | np->msi_flags = save_msi_flags; | |
5053 | ||
5054 | if (netif_running(dev)) { | |
5055 | writel(save_poll_interval, base + NvRegPollingInterval); | |
5056 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); | |
5057 | /* restore original irq */ | |
5058 | if (nv_request_irq(dev, 0)) | |
5059 | return 0; | |
5060 | } | |
5061 | ||
5062 | return ret; | |
5063 | } | |
5064 | ||
5065 | static int nv_loopback_test(struct net_device *dev) | |
5066 | { | |
5067 | struct fe_priv *np = netdev_priv(dev); | |
5068 | u8 __iomem *base = get_hwbase(dev); | |
5069 | struct sk_buff *tx_skb, *rx_skb; | |
5070 | dma_addr_t test_dma_addr; | |
5071 | u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET); | |
f82a9352 | 5072 | u32 flags; |
9589c77a AA |
5073 | int len, i, pkt_len; |
5074 | u8 *pkt_data; | |
5075 | u32 filter_flags = 0; | |
5076 | u32 misc1_flags = 0; | |
5077 | int ret = 1; | |
5078 | ||
5079 | if (netif_running(dev)) { | |
5080 | nv_disable_irq(dev); | |
5081 | filter_flags = readl(base + NvRegPacketFilterFlags); | |
5082 | misc1_flags = readl(base + NvRegMisc1); | |
5083 | } else { | |
5084 | nv_txrx_reset(dev); | |
5085 | } | |
5086 | ||
5087 | /* reinit driver view of the rx queue */ | |
5088 | set_bufsize(dev); | |
5089 | nv_init_ring(dev); | |
5090 | ||
5091 | /* setup hardware for loopback */ | |
5092 | writel(NVREG_MISC1_FORCE, base + NvRegMisc1); | |
5093 | writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); | |
5094 | ||
5095 | /* reinit nic view of the rx queue */ | |
5096 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
5097 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 5098 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
5099 | base + NvRegRingSizes); |
5100 | pci_push(base); | |
5101 | ||
5102 | /* restart rx engine */ | |
36b30ea9 | 5103 | nv_start_rxtx(dev); |
9589c77a AA |
5104 | |
5105 | /* setup packet for tx */ | |
5106 | pkt_len = ETH_DATA_LEN; | |
dae2e9f4 | 5107 | tx_skb = netdev_alloc_skb(dev, pkt_len); |
46798c89 | 5108 | if (!tx_skb) { |
46798c89 JJ |
5109 | ret = 0; |
5110 | goto out; | |
5111 | } | |
7598b349 | 5112 | test_dma_addr = dma_map_single(&np->pci_dev->dev, tx_skb->data, |
8b5be268 | 5113 | skb_tailroom(tx_skb), |
7598b349 | 5114 | DMA_FROM_DEVICE); |
39e50d96 ZY |
5115 | if (unlikely(dma_mapping_error(&np->pci_dev->dev, |
5116 | test_dma_addr))) { | |
612a7c4e LF |
5117 | dev_kfree_skb_any(tx_skb); |
5118 | goto out; | |
5119 | } | |
9589c77a AA |
5120 | pkt_data = skb_put(tx_skb, pkt_len); |
5121 | for (i = 0; i < pkt_len; i++) | |
5122 | pkt_data[i] = (u8)(i & 0xff); | |
9589c77a | 5123 | |
36b30ea9 | 5124 | if (!nv_optimized(np)) { |
f82a9352 SH |
5125 | np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr); |
5126 | np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); | |
9589c77a | 5127 | } else { |
5bb7ea26 AV |
5128 | np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr)); |
5129 | np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr)); | |
f82a9352 | 5130 | np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra); |
9589c77a AA |
5131 | } |
5132 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
5133 | pci_push(get_hwbase(dev)); | |
5134 | ||
5135 | msleep(500); | |
5136 | ||
5137 | /* check for rx of the packet */ | |
36b30ea9 | 5138 | if (!nv_optimized(np)) { |
f82a9352 | 5139 | flags = le32_to_cpu(np->rx_ring.orig[0].flaglen); |
9589c77a AA |
5140 | len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver); |
5141 | ||
5142 | } else { | |
f82a9352 | 5143 | flags = le32_to_cpu(np->rx_ring.ex[0].flaglen); |
9589c77a AA |
5144 | len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver); |
5145 | } | |
5146 | ||
f82a9352 | 5147 | if (flags & NV_RX_AVAIL) { |
9589c77a AA |
5148 | ret = 0; |
5149 | } else if (np->desc_ver == DESC_VER_1) { | |
f82a9352 | 5150 | if (flags & NV_RX_ERROR) |
9589c77a AA |
5151 | ret = 0; |
5152 | } else { | |
78aea4fc | 5153 | if (flags & NV_RX2_ERROR) |
9589c77a | 5154 | ret = 0; |
9589c77a AA |
5155 | } |
5156 | ||
5157 | if (ret) { | |
5158 | if (len != pkt_len) { | |
5159 | ret = 0; | |
9589c77a | 5160 | } else { |
761fcd9e | 5161 | rx_skb = np->rx_skb[0].skb; |
9589c77a AA |
5162 | for (i = 0; i < pkt_len; i++) { |
5163 | if (rx_skb->data[i] != (u8)(i & 0xff)) { | |
5164 | ret = 0; | |
9589c77a AA |
5165 | break; |
5166 | } | |
5167 | } | |
5168 | } | |
9589c77a AA |
5169 | } |
5170 | ||
7598b349 ZY |
5171 | dma_unmap_single(&np->pci_dev->dev, test_dma_addr, |
5172 | (skb_end_pointer(tx_skb) - tx_skb->data), | |
5173 | DMA_TO_DEVICE); | |
9589c77a | 5174 | dev_kfree_skb_any(tx_skb); |
46798c89 | 5175 | out: |
9589c77a | 5176 | /* stop engines */ |
36b30ea9 | 5177 | nv_stop_rxtx(dev); |
9589c77a AA |
5178 | nv_txrx_reset(dev); |
5179 | /* drain rx queue */ | |
36b30ea9 | 5180 | nv_drain_rxtx(dev); |
9589c77a AA |
5181 | |
5182 | if (netif_running(dev)) { | |
5183 | writel(misc1_flags, base + NvRegMisc1); | |
5184 | writel(filter_flags, base + NvRegPacketFilterFlags); | |
5185 | nv_enable_irq(dev); | |
5186 | } | |
5187 | ||
5188 | return ret; | |
5189 | } | |
5190 | ||
5191 | static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer) | |
5192 | { | |
5193 | struct fe_priv *np = netdev_priv(dev); | |
5194 | u8 __iomem *base = get_hwbase(dev); | |
86d9be26 IV |
5195 | int result, count; |
5196 | ||
5197 | count = nv_get_sset_count(dev, ETH_SS_TEST); | |
5198 | memset(buffer, 0, count * sizeof(u64)); | |
9589c77a AA |
5199 | |
5200 | if (!nv_link_test(dev)) { | |
5201 | test->flags |= ETH_TEST_FL_FAILED; | |
5202 | buffer[0] = 1; | |
5203 | } | |
5204 | ||
5205 | if (test->flags & ETH_TEST_FL_OFFLINE) { | |
5206 | if (netif_running(dev)) { | |
5207 | netif_stop_queue(dev); | |
08d93575 | 5208 | nv_napi_disable(dev); |
58dfd9c1 | 5209 | netif_tx_lock_bh(dev); |
e308a5d8 | 5210 | netif_addr_lock(dev); |
9589c77a AA |
5211 | spin_lock_irq(&np->lock); |
5212 | nv_disable_hw_interrupts(dev, np->irqmask); | |
78aea4fc | 5213 | if (!(np->msi_flags & NV_MSI_X_ENABLED)) |
9589c77a | 5214 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
78aea4fc | 5215 | else |
9589c77a | 5216 | writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); |
9589c77a | 5217 | /* stop engines */ |
36b30ea9 | 5218 | nv_stop_rxtx(dev); |
9589c77a AA |
5219 | nv_txrx_reset(dev); |
5220 | /* drain rx queue */ | |
36b30ea9 | 5221 | nv_drain_rxtx(dev); |
9589c77a | 5222 | spin_unlock_irq(&np->lock); |
e308a5d8 | 5223 | netif_addr_unlock(dev); |
58dfd9c1 | 5224 | netif_tx_unlock_bh(dev); |
9589c77a AA |
5225 | } |
5226 | ||
5227 | if (!nv_register_test(dev)) { | |
5228 | test->flags |= ETH_TEST_FL_FAILED; | |
5229 | buffer[1] = 1; | |
5230 | } | |
5231 | ||
5232 | result = nv_interrupt_test(dev); | |
5233 | if (result != 1) { | |
5234 | test->flags |= ETH_TEST_FL_FAILED; | |
5235 | buffer[2] = 1; | |
5236 | } | |
5237 | if (result == 0) { | |
5238 | /* bail out */ | |
5239 | return; | |
5240 | } | |
5241 | ||
86d9be26 | 5242 | if (count > NV_TEST_COUNT_BASE && !nv_loopback_test(dev)) { |
9589c77a AA |
5243 | test->flags |= ETH_TEST_FL_FAILED; |
5244 | buffer[3] = 1; | |
5245 | } | |
5246 | ||
5247 | if (netif_running(dev)) { | |
5248 | /* reinit driver view of the rx queue */ | |
5249 | set_bufsize(dev); | |
5250 | if (nv_init_ring(dev)) { | |
5251 | if (!np->in_shutdown) | |
5252 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
5253 | } | |
5254 | /* reinit nic view of the rx queue */ | |
5255 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); | |
5256 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); | |
78aea4fc | 5257 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
9589c77a AA |
5258 | base + NvRegRingSizes); |
5259 | pci_push(base); | |
5260 | writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); | |
5261 | pci_push(base); | |
5262 | /* restart rx engine */ | |
36b30ea9 | 5263 | nv_start_rxtx(dev); |
9589c77a | 5264 | netif_start_queue(dev); |
08d93575 | 5265 | nv_napi_enable(dev); |
9589c77a AA |
5266 | nv_enable_hw_interrupts(dev, np->irqmask); |
5267 | } | |
5268 | } | |
5269 | } | |
5270 | ||
52da3578 AA |
5271 | static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer) |
5272 | { | |
5273 | switch (stringset) { | |
5274 | case ETH_SS_STATS: | |
b9f2c044 | 5275 | memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str)); |
52da3578 | 5276 | break; |
9589c77a | 5277 | case ETH_SS_TEST: |
b9f2c044 | 5278 | memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str)); |
9589c77a | 5279 | break; |
52da3578 AA |
5280 | } |
5281 | } | |
5282 | ||
7282d491 | 5283 | static const struct ethtool_ops ops = { |
1da177e4 LT |
5284 | .get_drvinfo = nv_get_drvinfo, |
5285 | .get_link = ethtool_op_get_link, | |
5286 | .get_wol = nv_get_wol, | |
5287 | .set_wol = nv_set_wol, | |
dc8216c1 MS |
5288 | .get_regs_len = nv_get_regs_len, |
5289 | .get_regs = nv_get_regs, | |
5290 | .nway_reset = nv_nway_reset, | |
eafa59f6 AA |
5291 | .get_ringparam = nv_get_ringparam, |
5292 | .set_ringparam = nv_set_ringparam, | |
b6d0773f AA |
5293 | .get_pauseparam = nv_get_pauseparam, |
5294 | .set_pauseparam = nv_set_pauseparam, | |
52da3578 | 5295 | .get_strings = nv_get_strings, |
52da3578 | 5296 | .get_ethtool_stats = nv_get_ethtool_stats, |
b9f2c044 | 5297 | .get_sset_count = nv_get_sset_count, |
9589c77a | 5298 | .self_test = nv_self_test, |
7491302d | 5299 | .get_ts_info = ethtool_op_get_ts_info, |
0fa9e289 PR |
5300 | .get_link_ksettings = nv_get_link_ksettings, |
5301 | .set_link_ksettings = nv_set_link_ksettings, | |
1da177e4 LT |
5302 | }; |
5303 | ||
7e680c22 AA |
5304 | /* The mgmt unit and driver use a semaphore to access the phy during init */ |
5305 | static int nv_mgmt_acquire_sema(struct net_device *dev) | |
5306 | { | |
cac1c52c | 5307 | struct fe_priv *np = netdev_priv(dev); |
7e680c22 AA |
5308 | u8 __iomem *base = get_hwbase(dev); |
5309 | int i; | |
5310 | u32 tx_ctrl, mgmt_sema; | |
5311 | ||
5312 | for (i = 0; i < 10; i++) { | |
5313 | mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; | |
5314 | if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5315 | break; | |
5316 | msleep(500); | |
5317 | } | |
5318 | ||
5319 | if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) | |
5320 | return 0; | |
5321 | ||
5322 | for (i = 0; i < 2; i++) { | |
5323 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5324 | tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5325 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5326 | ||
5327 | /* verify that semaphore was acquired */ | |
5328 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5329 | if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && | |
cac1c52c AA |
5330 | ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) { |
5331 | np->mgmt_sema = 1; | |
7e680c22 | 5332 | return 1; |
78aea4fc | 5333 | } else |
7e680c22 AA |
5334 | udelay(50); |
5335 | } | |
5336 | ||
5337 | return 0; | |
5338 | } | |
5339 | ||
cac1c52c AA |
5340 | static void nv_mgmt_release_sema(struct net_device *dev) |
5341 | { | |
5342 | struct fe_priv *np = netdev_priv(dev); | |
5343 | u8 __iomem *base = get_hwbase(dev); | |
5344 | u32 tx_ctrl; | |
5345 | ||
5346 | if (np->driver_data & DEV_HAS_MGMT_UNIT) { | |
5347 | if (np->mgmt_sema) { | |
5348 | tx_ctrl = readl(base + NvRegTransmitterControl); | |
5349 | tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ; | |
5350 | writel(tx_ctrl, base + NvRegTransmitterControl); | |
5351 | } | |
5352 | } | |
5353 | } | |
5354 | ||
5355 | ||
5356 | static int nv_mgmt_get_version(struct net_device *dev) | |
5357 | { | |
5358 | struct fe_priv *np = netdev_priv(dev); | |
5359 | u8 __iomem *base = get_hwbase(dev); | |
5360 | u32 data_ready = readl(base + NvRegTransmitterControl); | |
5361 | u32 data_ready2 = 0; | |
5362 | unsigned long start; | |
5363 | int ready = 0; | |
5364 | ||
5365 | writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion); | |
5366 | writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl); | |
5367 | start = jiffies; | |
5368 | while (time_before(jiffies, start + 5*HZ)) { | |
5369 | data_ready2 = readl(base + NvRegTransmitterControl); | |
5370 | if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) { | |
5371 | ready = 1; | |
5372 | break; | |
5373 | } | |
5374 | schedule_timeout_uninterruptible(1); | |
5375 | } | |
5376 | ||
5377 | if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR)) | |
5378 | return 0; | |
5379 | ||
5380 | np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION; | |
5381 | ||
5382 | return 1; | |
5383 | } | |
5384 | ||
1da177e4 LT |
5385 | static int nv_open(struct net_device *dev) |
5386 | { | |
ac9c1897 | 5387 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 | 5388 | u8 __iomem *base = get_hwbase(dev); |
d33a73c8 AA |
5389 | int ret = 1; |
5390 | int oom, i; | |
a433686c | 5391 | u32 low; |
1da177e4 | 5392 | |
cb52deba ES |
5393 | /* power up phy */ |
5394 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5395 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); | |
5396 | ||
88d7d8b0 | 5397 | nv_txrx_gate(dev, false); |
f1489653 | 5398 | /* erase previous misconfiguration */ |
86a0f043 AA |
5399 | if (np->driver_data & DEV_HAS_POWER_CNTRL) |
5400 | nv_mac_reset(dev); | |
1da177e4 LT |
5401 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); |
5402 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5403 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5404 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5405 | writel(0, base + NvRegPacketFilterFlags); |
5406 | ||
5407 | writel(0, base + NvRegTransmitterControl); | |
5408 | writel(0, base + NvRegReceiverControl); | |
5409 | ||
5410 | writel(0, base + NvRegAdapterControl); | |
5411 | ||
eb91f61b AA |
5412 | if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) |
5413 | writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); | |
5414 | ||
f1489653 | 5415 | /* initialize descriptor rings */ |
d81c0983 | 5416 | set_bufsize(dev); |
1da177e4 LT |
5417 | oom = nv_init_ring(dev); |
5418 | ||
5419 | writel(0, base + NvRegLinkSpeed); | |
5070d340 | 5420 | writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
1da177e4 LT |
5421 | nv_txrx_reset(dev); |
5422 | writel(0, base + NvRegUnknownSetupReg6); | |
5423 | ||
5424 | np->in_shutdown = 0; | |
5425 | ||
f1489653 | 5426 | /* give hw rings */ |
0832b25a | 5427 | setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING); |
78aea4fc | 5428 | writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), |
1da177e4 LT |
5429 | base + NvRegRingSizes); |
5430 | ||
1da177e4 | 5431 | writel(np->linkspeed, base + NvRegLinkSpeed); |
95d161cb AA |
5432 | if (np->desc_ver == DESC_VER_1) |
5433 | writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); | |
5434 | else | |
5435 | writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); | |
8a4ae7f2 | 5436 | writel(np->txrxctl_bits, base + NvRegTxRxControl); |
ee407b02 | 5437 | writel(np->vlanctl_bits, base + NvRegVlanControl); |
1da177e4 | 5438 | pci_push(base); |
8a4ae7f2 | 5439 | writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); |
344d0dce JP |
5440 | if (reg_delay(dev, NvRegUnknownSetupReg5, |
5441 | NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, | |
5442 | NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX)) | |
1d397f36 JP |
5443 | netdev_info(dev, |
5444 | "%s: SetupReg5, Bit 31 remained off\n", __func__); | |
1da177e4 | 5445 | |
7e680c22 | 5446 | writel(0, base + NvRegMIIMask); |
1da177e4 | 5447 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
eb798428 | 5448 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 | 5449 | |
1da177e4 LT |
5450 | writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); |
5451 | writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus); | |
5452 | writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); | |
d81c0983 | 5453 | writel(np->rx_buf_sz, base + NvRegOffloadConfig); |
1da177e4 LT |
5454 | |
5455 | writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); | |
a433686c AA |
5456 | |
5457 | get_random_bytes(&low, sizeof(low)); | |
5458 | low &= NVREG_SLOTTIME_MASK; | |
5459 | if (np->desc_ver == DESC_VER_1) { | |
5460 | writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime); | |
5461 | } else { | |
5462 | if (!(np->driver_data & DEV_HAS_GEAR_MODE)) { | |
5463 | /* setup legacy backoff */ | |
5464 | writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime); | |
5465 | } else { | |
5466 | writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime); | |
5467 | nv_gear_backoff_reseed(dev); | |
5468 | } | |
5469 | } | |
9744e218 AA |
5470 | writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); |
5471 | writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); | |
a971c324 AA |
5472 | if (poll_interval == -1) { |
5473 | if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) | |
5474 | writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); | |
5475 | else | |
5476 | writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); | |
78aea4fc | 5477 | } else |
a971c324 | 5478 | writel(poll_interval & 0xFFFF, base + NvRegPollingInterval); |
1da177e4 LT |
5479 | writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); |
5480 | writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, | |
5481 | base + NvRegAdapterControl); | |
5482 | writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); | |
7e680c22 | 5483 | writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); |
c42d9df9 AA |
5484 | if (np->wolenabled) |
5485 | writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); | |
1da177e4 LT |
5486 | |
5487 | i = readl(base + NvRegPowerState); | |
78aea4fc | 5488 | if ((i & NVREG_POWERSTATE_POWEREDUP) == 0) |
1da177e4 LT |
5489 | writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); |
5490 | ||
5491 | pci_push(base); | |
5492 | udelay(10); | |
5493 | writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); | |
5494 | ||
84b3932b | 5495 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5496 | pci_push(base); |
eb798428 | 5497 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
1da177e4 LT |
5498 | writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); |
5499 | pci_push(base); | |
5500 | ||
78aea4fc | 5501 | if (nv_request_irq(dev, 0)) |
84b3932b | 5502 | goto out_drain; |
1da177e4 LT |
5503 | |
5504 | /* ask for interrupts */ | |
84b3932b | 5505 | nv_enable_hw_interrupts(dev, np->irqmask); |
1da177e4 LT |
5506 | |
5507 | spin_lock_irq(&np->lock); | |
5508 | writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); | |
5509 | writel(0, base + NvRegMulticastAddrB); | |
bb9a4fd1 AA |
5510 | writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); |
5511 | writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); | |
1da177e4 LT |
5512 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
5513 | /* One manual link speed update: Interrupts are enabled, future link | |
5514 | * speed changes cause interrupts and are handled by nv_link_irq(). | |
5515 | */ | |
1da847b9 ZY |
5516 | readl(base + NvRegMIIStatus); |
5517 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); | |
5518 | ||
1b1b3c9b MS |
5519 | /* set linkspeed to invalid value, thus force nv_update_linkspeed |
5520 | * to init hw */ | |
5521 | np->linkspeed = 0; | |
1da177e4 | 5522 | ret = nv_update_linkspeed(dev); |
36b30ea9 | 5523 | nv_start_rxtx(dev); |
1da177e4 | 5524 | netif_start_queue(dev); |
08d93575 | 5525 | nv_napi_enable(dev); |
e27cdba5 | 5526 | |
1da177e4 LT |
5527 | if (ret) { |
5528 | netif_carrier_on(dev); | |
5529 | } else { | |
1d397f36 | 5530 | netdev_info(dev, "no link during initialization\n"); |
1da177e4 LT |
5531 | netif_carrier_off(dev); |
5532 | } | |
5533 | if (oom) | |
5534 | mod_timer(&np->oom_kick, jiffies + OOM_REFILL); | |
52da3578 AA |
5535 | |
5536 | /* start statistics timer */ | |
9c662435 | 5537 | if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
bfebbb88 DD |
5538 | mod_timer(&np->stats_poll, |
5539 | round_jiffies(jiffies + STATS_INTERVAL)); | |
52da3578 | 5540 | |
1da177e4 LT |
5541 | spin_unlock_irq(&np->lock); |
5542 | ||
e19df76a SH |
5543 | /* If the loopback feature was set while the device was down, make sure |
5544 | * that it's set correctly now. | |
5545 | */ | |
5546 | if (dev->features & NETIF_F_LOOPBACK) | |
5547 | nv_set_loopback(dev, dev->features); | |
5548 | ||
1da177e4 LT |
5549 | return 0; |
5550 | out_drain: | |
36b30ea9 | 5551 | nv_drain_rxtx(dev); |
1da177e4 LT |
5552 | return ret; |
5553 | } | |
5554 | ||
5555 | static int nv_close(struct net_device *dev) | |
5556 | { | |
ac9c1897 | 5557 | struct fe_priv *np = netdev_priv(dev); |
1da177e4 LT |
5558 | u8 __iomem *base; |
5559 | ||
5560 | spin_lock_irq(&np->lock); | |
5561 | np->in_shutdown = 1; | |
5562 | spin_unlock_irq(&np->lock); | |
08d93575 | 5563 | nv_napi_disable(dev); |
a7475906 | 5564 | synchronize_irq(np->pci_dev->irq); |
1da177e4 LT |
5565 | |
5566 | del_timer_sync(&np->oom_kick); | |
5567 | del_timer_sync(&np->nic_poll); | |
52da3578 | 5568 | del_timer_sync(&np->stats_poll); |
1da177e4 LT |
5569 | |
5570 | netif_stop_queue(dev); | |
5571 | spin_lock_irq(&np->lock); | |
1ff39eb6 | 5572 | nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */ |
36b30ea9 | 5573 | nv_stop_rxtx(dev); |
1da177e4 LT |
5574 | nv_txrx_reset(dev); |
5575 | ||
5576 | /* disable interrupts on the nic or we will lock up */ | |
5577 | base = get_hwbase(dev); | |
84b3932b | 5578 | nv_disable_hw_interrupts(dev, np->irqmask); |
1da177e4 | 5579 | pci_push(base); |
1da177e4 LT |
5580 | |
5581 | spin_unlock_irq(&np->lock); | |
5582 | ||
84b3932b | 5583 | nv_free_irq(dev); |
1da177e4 | 5584 | |
36b30ea9 | 5585 | nv_drain_rxtx(dev); |
1da177e4 | 5586 | |
5a9a8e32 | 5587 | if (np->wolenabled || !phy_power_down) { |
88d7d8b0 | 5588 | nv_txrx_gate(dev, false); |
2cc49a5c | 5589 | writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); |
1da177e4 | 5590 | nv_start_rx(dev); |
cb52deba ES |
5591 | } else { |
5592 | /* power down phy */ | |
5593 | mii_rw(dev, np->phyaddr, MII_BMCR, | |
5594 | mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); | |
88d7d8b0 | 5595 | nv_txrx_gate(dev, true); |
2cc49a5c | 5596 | } |
1da177e4 LT |
5597 | |
5598 | /* FIXME: power down nic */ | |
5599 | ||
5600 | return 0; | |
5601 | } | |
5602 | ||
b94426bd SH |
5603 | static const struct net_device_ops nv_netdev_ops = { |
5604 | .ndo_open = nv_open, | |
5605 | .ndo_stop = nv_close, | |
f5d827ae | 5606 | .ndo_get_stats64 = nv_get_stats64, |
00829823 SH |
5607 | .ndo_start_xmit = nv_start_xmit, |
5608 | .ndo_tx_timeout = nv_tx_timeout, | |
5609 | .ndo_change_mtu = nv_change_mtu, | |
569e1463 MM |
5610 | .ndo_fix_features = nv_fix_features, |
5611 | .ndo_set_features = nv_set_features, | |
00829823 SH |
5612 | .ndo_validate_addr = eth_validate_addr, |
5613 | .ndo_set_mac_address = nv_set_mac_address, | |
afc4b13d | 5614 | .ndo_set_rx_mode = nv_set_multicast, |
00829823 SH |
5615 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5616 | .ndo_poll_controller = nv_poll_controller, | |
5617 | #endif | |
5618 | }; | |
5619 | ||
5620 | static const struct net_device_ops nv_netdev_ops_optimized = { | |
5621 | .ndo_open = nv_open, | |
5622 | .ndo_stop = nv_close, | |
f5d827ae | 5623 | .ndo_get_stats64 = nv_get_stats64, |
00829823 | 5624 | .ndo_start_xmit = nv_start_xmit_optimized, |
b94426bd SH |
5625 | .ndo_tx_timeout = nv_tx_timeout, |
5626 | .ndo_change_mtu = nv_change_mtu, | |
569e1463 MM |
5627 | .ndo_fix_features = nv_fix_features, |
5628 | .ndo_set_features = nv_set_features, | |
b94426bd SH |
5629 | .ndo_validate_addr = eth_validate_addr, |
5630 | .ndo_set_mac_address = nv_set_mac_address, | |
afc4b13d | 5631 | .ndo_set_rx_mode = nv_set_multicast, |
b94426bd SH |
5632 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5633 | .ndo_poll_controller = nv_poll_controller, | |
5634 | #endif | |
5635 | }; | |
5636 | ||
d05919a1 | 5637 | static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) |
1da177e4 LT |
5638 | { |
5639 | struct net_device *dev; | |
5640 | struct fe_priv *np; | |
5641 | unsigned long addr; | |
5642 | u8 __iomem *base; | |
5643 | int err, i; | |
5070d340 | 5644 | u32 powerstate, txreg; |
7e680c22 AA |
5645 | u32 phystate_orig = 0, phystate; |
5646 | int phyinitialized = 0; | |
3f88ce49 JG |
5647 | static int printed_version; |
5648 | ||
5649 | if (!printed_version++) | |
294a554e JP |
5650 | pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n", |
5651 | FORCEDETH_VERSION); | |
1da177e4 LT |
5652 | |
5653 | dev = alloc_etherdev(sizeof(struct fe_priv)); | |
5654 | err = -ENOMEM; | |
5655 | if (!dev) | |
5656 | goto out; | |
5657 | ||
ac9c1897 | 5658 | np = netdev_priv(dev); |
bea3348e | 5659 | np->dev = dev; |
1da177e4 LT |
5660 | np->pci_dev = pci_dev; |
5661 | spin_lock_init(&np->lock); | |
f5d827ae | 5662 | spin_lock_init(&np->hwstats_lock); |
1da177e4 | 5663 | SET_NETDEV_DEV(dev, &pci_dev->dev); |
827da44c JS |
5664 | u64_stats_init(&np->swstats_rx_syncp); |
5665 | u64_stats_init(&np->swstats_tx_syncp); | |
1da177e4 | 5666 | |
d9935679 KC |
5667 | timer_setup(&np->oom_kick, nv_do_rx_refill, 0); |
5668 | timer_setup(&np->nic_poll, nv_do_nic_poll, 0); | |
5669 | timer_setup(&np->stats_poll, nv_do_stats_poll, TIMER_DEFERRABLE); | |
1da177e4 LT |
5670 | |
5671 | err = pci_enable_device(pci_dev); | |
3f88ce49 | 5672 | if (err) |
1da177e4 | 5673 | goto out_free; |
1da177e4 LT |
5674 | |
5675 | pci_set_master(pci_dev); | |
5676 | ||
5677 | err = pci_request_regions(pci_dev, DRV_NAME); | |
5678 | if (err < 0) | |
5679 | goto out_disable; | |
5680 | ||
9c662435 | 5681 | if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) |
57fff698 AA |
5682 | np->register_size = NV_PCI_REGSZ_VER3; |
5683 | else if (id->driver_data & DEV_HAS_STATISTICS_V1) | |
86a0f043 AA |
5684 | np->register_size = NV_PCI_REGSZ_VER2; |
5685 | else | |
5686 | np->register_size = NV_PCI_REGSZ_VER1; | |
5687 | ||
1da177e4 LT |
5688 | err = -EINVAL; |
5689 | addr = 0; | |
5690 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1da177e4 | 5691 | if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM && |
86a0f043 | 5692 | pci_resource_len(pci_dev, i) >= np->register_size) { |
1da177e4 LT |
5693 | addr = pci_resource_start(pci_dev, i); |
5694 | break; | |
5695 | } | |
5696 | } | |
5697 | if (i == DEVICE_COUNT_RESOURCE) { | |
b2ba08e6 | 5698 | dev_info(&pci_dev->dev, "Couldn't find register window\n"); |
1da177e4 LT |
5699 | goto out_relreg; |
5700 | } | |
5701 | ||
86a0f043 AA |
5702 | /* copy of driver data */ |
5703 | np->driver_data = id->driver_data; | |
9f3f7910 AA |
5704 | /* copy of device id */ |
5705 | np->device_id = id->device; | |
86a0f043 | 5706 | |
1da177e4 | 5707 | /* handle different descriptor versions */ |
ee73362c MS |
5708 | if (id->driver_data & DEV_HAS_HIGH_DMA) { |
5709 | /* packet format 3: supports 40-bit addressing */ | |
5710 | np->desc_ver = DESC_VER_3; | |
84b3932b | 5711 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; |
69fe3fd7 | 5712 | if (dma_64bit) { |
6afd142f | 5713 | if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39))) |
b2ba08e6 JP |
5714 | dev_info(&pci_dev->dev, |
5715 | "64-bit DMA failed, using 32-bit addressing\n"); | |
3f88ce49 | 5716 | else |
69fe3fd7 | 5717 | dev->features |= NETIF_F_HIGHDMA; |
6afd142f | 5718 | if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) { |
b2ba08e6 JP |
5719 | dev_info(&pci_dev->dev, |
5720 | "64-bit DMA (consistent) failed, using 32-bit ring buffers\n"); | |
69fe3fd7 | 5721 | } |
ee73362c MS |
5722 | } |
5723 | } else if (id->driver_data & DEV_HAS_LARGEDESC) { | |
5724 | /* packet format 2: supports jumbo frames */ | |
1da177e4 | 5725 | np->desc_ver = DESC_VER_2; |
8a4ae7f2 | 5726 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; |
ee73362c MS |
5727 | } else { |
5728 | /* original packet format */ | |
5729 | np->desc_ver = DESC_VER_1; | |
8a4ae7f2 | 5730 | np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; |
d81c0983 | 5731 | } |
ee73362c MS |
5732 | |
5733 | np->pkt_limit = NV_PKTLIMIT_1; | |
5734 | if (id->driver_data & DEV_HAS_LARGEDESC) | |
5735 | np->pkt_limit = NV_PKTLIMIT_2; | |
5736 | ||
8a4ae7f2 MS |
5737 | if (id->driver_data & DEV_HAS_CHECKSUM) { |
5738 | np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; | |
569e1463 MM |
5739 | dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | |
5740 | NETIF_F_TSO | NETIF_F_RXCSUM; | |
21828163 | 5741 | } |
8a4ae7f2 | 5742 | |
ee407b02 AA |
5743 | np->vlanctl_bits = 0; |
5744 | if (id->driver_data & DEV_HAS_VLAN) { | |
5745 | np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; | |
f646968f PM |
5746 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | |
5747 | NETIF_F_HW_VLAN_CTAG_TX; | |
ee407b02 AA |
5748 | } |
5749 | ||
0891b0e0 JP |
5750 | dev->features |= dev->hw_features; |
5751 | ||
e19df76a SH |
5752 | /* Add loopback capability to the device. */ |
5753 | dev->hw_features |= NETIF_F_LOOPBACK; | |
5754 | ||
44770e11 JW |
5755 | /* MTU range: 64 - 1500 or 9100 */ |
5756 | dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN; | |
5757 | dev->max_mtu = np->pkt_limit; | |
5758 | ||
b6d0773f | 5759 | np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG; |
5289b4c4 AA |
5760 | if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) || |
5761 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) || | |
5762 | (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) { | |
b6d0773f | 5763 | np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ; |
eb91f61b | 5764 | } |
f3b197ac | 5765 | |
1da177e4 | 5766 | err = -ENOMEM; |
86a0f043 | 5767 | np->base = ioremap(addr, np->register_size); |
1da177e4 LT |
5768 | if (!np->base) |
5769 | goto out_relreg; | |
ee73362c | 5770 | |
eafa59f6 AA |
5771 | np->rx_ring_size = RX_RING_DEFAULT; |
5772 | np->tx_ring_size = TX_RING_DEFAULT; | |
eafa59f6 | 5773 | |
36b30ea9 | 5774 | if (!nv_optimized(np)) { |
e8992e40 ZY |
5775 | np->rx_ring.orig = dma_alloc_coherent(&pci_dev->dev, |
5776 | sizeof(struct ring_desc) * | |
5777 | (np->rx_ring_size + | |
5778 | np->tx_ring_size), | |
5779 | &np->ring_addr, | |
5780 | GFP_ATOMIC); | |
ee73362c MS |
5781 | if (!np->rx_ring.orig) |
5782 | goto out_unmap; | |
eafa59f6 | 5783 | np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size]; |
ee73362c | 5784 | } else { |
e8992e40 ZY |
5785 | np->rx_ring.ex = dma_alloc_coherent(&pci_dev->dev, |
5786 | sizeof(struct ring_desc_ex) * | |
5787 | (np->rx_ring_size + | |
5788 | np->tx_ring_size), | |
5789 | &np->ring_addr, GFP_ATOMIC); | |
ee73362c MS |
5790 | if (!np->rx_ring.ex) |
5791 | goto out_unmap; | |
eafa59f6 AA |
5792 | np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size]; |
5793 | } | |
dd00cc48 YP |
5794 | np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); |
5795 | np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL); | |
761fcd9e | 5796 | if (!np->rx_skb || !np->tx_skb) |
eafa59f6 | 5797 | goto out_freering; |
1da177e4 | 5798 | |
36b30ea9 | 5799 | if (!nv_optimized(np)) |
00829823 | 5800 | dev->netdev_ops = &nv_netdev_ops; |
86b22b0d | 5801 | else |
00829823 | 5802 | dev->netdev_ops = &nv_netdev_ops_optimized; |
b94426bd | 5803 | |
bea3348e | 5804 | netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP); |
7ad24ea4 | 5805 | dev->ethtool_ops = &ops; |
1da177e4 LT |
5806 | dev->watchdog_timeo = NV_WATCHDOG_TIMEO; |
5807 | ||
5808 | pci_set_drvdata(pci_dev, dev); | |
5809 | ||
5810 | /* read the mac address */ | |
5811 | base = get_hwbase(dev); | |
5812 | np->orig_mac[0] = readl(base + NvRegMacAddrA); | |
5813 | np->orig_mac[1] = readl(base + NvRegMacAddrB); | |
5814 | ||
5070d340 AA |
5815 | /* check the workaround bit for correct mac address order */ |
5816 | txreg = readl(base + NvRegTransmitPoll); | |
a376e79c | 5817 | if (id->driver_data & DEV_HAS_CORRECT_MACADDR) { |
5070d340 AA |
5818 | /* mac address is already in correct order */ |
5819 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5820 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5821 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5822 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5823 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5824 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
a376e79c AA |
5825 | } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { |
5826 | /* mac address is already in correct order */ | |
5827 | dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff; | |
5828 | dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff; | |
5829 | dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff; | |
5830 | dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff; | |
5831 | dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff; | |
5832 | dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff; | |
5833 | /* | |
5834 | * Set orig mac address back to the reversed version. | |
5835 | * This flag will be cleared during low power transition. | |
5836 | * Therefore, we should always put back the reversed address. | |
5837 | */ | |
5838 | np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) + | |
5839 | (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24); | |
5840 | np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8); | |
5070d340 AA |
5841 | } else { |
5842 | /* need to reverse mac address to correct order */ | |
5843 | dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff; | |
5844 | dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff; | |
5845 | dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff; | |
5846 | dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff; | |
5847 | dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff; | |
5848 | dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff; | |
5070d340 | 5849 | writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); |
c20ec761 JP |
5850 | dev_dbg(&pci_dev->dev, |
5851 | "%s: set workaround bit for reversed mac addr\n", | |
5852 | __func__); | |
5070d340 | 5853 | } |
1da177e4 | 5854 | |
aaeb6cdf | 5855 | if (!is_valid_ether_addr(dev->dev_addr)) { |
1da177e4 LT |
5856 | /* |
5857 | * Bad mac address. At least one bios sets the mac address | |
5858 | * to 01:23:45:67:89:ab | |
5859 | */ | |
b2ba08e6 | 5860 | dev_err(&pci_dev->dev, |
c20ec761 | 5861 | "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n", |
78aea4fc | 5862 | dev->dev_addr); |
7ce5d222 | 5863 | eth_hw_addr_random(dev); |
c20ec761 JP |
5864 | dev_err(&pci_dev->dev, |
5865 | "Using random MAC address: %pM\n", dev->dev_addr); | |
1da177e4 LT |
5866 | } |
5867 | ||
f1489653 AA |
5868 | /* set mac address */ |
5869 | nv_copy_mac_to_hw(dev); | |
5870 | ||
1da177e4 LT |
5871 | /* disable WOL */ |
5872 | writel(0, base + NvRegWakeUpFlags); | |
5873 | np->wolenabled = 0; | |
dba5a68a | 5874 | device_set_wakeup_enable(&pci_dev->dev, false); |
1da177e4 | 5875 | |
86a0f043 | 5876 | if (id->driver_data & DEV_HAS_POWER_CNTRL) { |
86a0f043 AA |
5877 | |
5878 | /* take phy and nic out of low power mode */ | |
5879 | powerstate = readl(base + NvRegPowerState2); | |
5880 | powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; | |
3c2e1c11 | 5881 | if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) && |
44c10138 | 5882 | pci_dev->revision >= 0xA3) |
86a0f043 AA |
5883 | powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; |
5884 | writel(powerstate, base + NvRegPowerState2); | |
5885 | } | |
5886 | ||
78aea4fc | 5887 | if (np->desc_ver == DESC_VER_1) |
ac9c1897 | 5888 | np->tx_flags = NV_TX_VALID; |
78aea4fc | 5889 | else |
ac9c1897 | 5890 | np->tx_flags = NV_TX2_VALID; |
9e184767 AA |
5891 | |
5892 | np->msi_flags = 0; | |
78aea4fc | 5893 | if ((id->driver_data & DEV_HAS_MSI) && msi) |
9e184767 | 5894 | np->msi_flags |= NV_MSI_CAPABLE; |
78aea4fc | 5895 | |
9e184767 AA |
5896 | if ((id->driver_data & DEV_HAS_MSI_X) && msix) { |
5897 | /* msix has had reported issues when modifying irqmask | |
5898 | as in the case of napi, therefore, disable for now | |
5899 | */ | |
0a12761b | 5900 | #if 0 |
9e184767 AA |
5901 | np->msi_flags |= NV_MSI_X_CAPABLE; |
5902 | #endif | |
5903 | } | |
5904 | ||
5905 | if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) { | |
a971c324 | 5906 | np->irqmask = NVREG_IRQMASK_CPU; |
d33a73c8 AA |
5907 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ |
5908 | np->msi_flags |= 0x0001; | |
9e184767 AA |
5909 | } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC && |
5910 | !(id->driver_data & DEV_NEED_TIMERIRQ)) { | |
5911 | /* start off in throughput mode */ | |
5912 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5913 | /* remove support for msix mode */ | |
5914 | np->msi_flags &= ~NV_MSI_X_CAPABLE; | |
5915 | } else { | |
5916 | optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT; | |
5917 | np->irqmask = NVREG_IRQMASK_THROUGHPUT; | |
5918 | if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */ | |
5919 | np->msi_flags |= 0x0003; | |
d33a73c8 | 5920 | } |
a971c324 | 5921 | |
1da177e4 LT |
5922 | if (id->driver_data & DEV_NEED_TIMERIRQ) |
5923 | np->irqmask |= NVREG_IRQ_TIMER; | |
5924 | if (id->driver_data & DEV_NEED_LINKTIMER) { | |
1da177e4 LT |
5925 | np->need_linktimer = 1; |
5926 | np->link_timeout = jiffies + LINK_TIMEOUT; | |
5927 | } else { | |
1da177e4 LT |
5928 | np->need_linktimer = 0; |
5929 | } | |
5930 | ||
3b446c3e AA |
5931 | /* Limit the number of tx's outstanding for hw bug */ |
5932 | if (id->driver_data & DEV_NEED_TX_LIMIT) { | |
5933 | np->tx_limit = 1; | |
5c659322 | 5934 | if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) && |
3b446c3e AA |
5935 | pci_dev->revision >= 0xA2) |
5936 | np->tx_limit = 0; | |
5937 | } | |
5938 | ||
7e680c22 AA |
5939 | /* clear phy state and temporarily halt phy interrupts */ |
5940 | writel(0, base + NvRegMIIMask); | |
5941 | phystate = readl(base + NvRegAdapterControl); | |
5942 | if (phystate & NVREG_ADAPTCTL_RUNNING) { | |
5943 | phystate_orig = 1; | |
5944 | phystate &= ~NVREG_ADAPTCTL_RUNNING; | |
5945 | writel(phystate, base + NvRegAdapterControl); | |
5946 | } | |
eb798428 | 5947 | writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); |
7e680c22 AA |
5948 | |
5949 | if (id->driver_data & DEV_HAS_MGMT_UNIT) { | |
7e680c22 | 5950 | /* management unit running on the mac? */ |
cac1c52c AA |
5951 | if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) && |
5952 | (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) && | |
5953 | nv_mgmt_acquire_sema(dev) && | |
5954 | nv_mgmt_get_version(dev)) { | |
5955 | np->mac_in_use = 1; | |
78aea4fc | 5956 | if (np->mgmt_version > 0) |
cac1c52c | 5957 | np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE; |
cac1c52c AA |
5958 | /* management unit setup the phy already? */ |
5959 | if (np->mac_in_use && | |
5960 | ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == | |
5961 | NVREG_XMITCTL_SYNC_PHY_INIT)) { | |
5962 | /* phy is inited by mgmt unit */ | |
5963 | phyinitialized = 1; | |
cac1c52c AA |
5964 | } else { |
5965 | /* we need to init the phy */ | |
7e680c22 AA |
5966 | } |
5967 | } | |
5968 | } | |
5969 | ||
1da177e4 | 5970 | /* find a suitable phy */ |
7a33e45a | 5971 | for (i = 1; i <= 32; i++) { |
1da177e4 | 5972 | int id1, id2; |
7a33e45a | 5973 | int phyaddr = i & 0x1F; |
1da177e4 LT |
5974 | |
5975 | spin_lock_irq(&np->lock); | |
7a33e45a | 5976 | id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); |
1da177e4 LT |
5977 | spin_unlock_irq(&np->lock); |
5978 | if (id1 < 0 || id1 == 0xffff) | |
5979 | continue; | |
5980 | spin_lock_irq(&np->lock); | |
7a33e45a | 5981 | id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); |
1da177e4 LT |
5982 | spin_unlock_irq(&np->lock); |
5983 | if (id2 < 0 || id2 == 0xffff) | |
5984 | continue; | |
5985 | ||
edf7e5ec | 5986 | np->phy_model = id2 & PHYID2_MODEL_MASK; |
1da177e4 LT |
5987 | id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT; |
5988 | id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT; | |
7a33e45a | 5989 | np->phyaddr = phyaddr; |
1da177e4 | 5990 | np->phy_oui = id1 | id2; |
9f3f7910 AA |
5991 | |
5992 | /* Realtek hardcoded phy id1 to all zero's on certain phys */ | |
5993 | if (np->phy_oui == PHY_OUI_REALTEK2) | |
5994 | np->phy_oui = PHY_OUI_REALTEK; | |
5995 | /* Setup phy revision for Realtek */ | |
5996 | if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211) | |
5997 | np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; | |
5998 | ||
1da177e4 LT |
5999 | break; |
6000 | } | |
7a33e45a | 6001 | if (i == 33) { |
b2ba08e6 | 6002 | dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n"); |
eafa59f6 | 6003 | goto out_error; |
1da177e4 | 6004 | } |
f3b197ac | 6005 | |
7e680c22 AA |
6006 | if (!phyinitialized) { |
6007 | /* reset it */ | |
6008 | phy_init(dev); | |
f35723ec AA |
6009 | } else { |
6010 | /* see if it is a gigabit phy */ | |
6011 | u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); | |
78aea4fc | 6012 | if (mii_status & PHY_GIGABIT) |
f35723ec | 6013 | np->gigabit = PHY_GIGABIT; |
7e680c22 | 6014 | } |
1da177e4 LT |
6015 | |
6016 | /* set default link speed settings */ | |
6017 | np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; | |
6018 | np->duplex = 0; | |
6019 | np->autoneg = 1; | |
6020 | ||
6021 | err = register_netdev(dev); | |
6022 | if (err) { | |
b2ba08e6 | 6023 | dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err); |
eafa59f6 | 6024 | goto out_error; |
1da177e4 | 6025 | } |
3f88ce49 | 6026 | |
3f0a1b58 | 6027 | netif_carrier_off(dev); |
6028 | ||
6029 | /* Some NICs freeze when TX pause is enabled while NIC is | |
6030 | * down, and this stays across warm reboots. The sequence | |
6031 | * below should be enough to recover from that state. | |
6032 | */ | |
6033 | nv_update_pause(dev, 0); | |
6034 | nv_start_tx(dev); | |
6035 | nv_stop_tx(dev); | |
6036 | ||
9331db4f JP |
6037 | if (id->driver_data & DEV_HAS_VLAN) |
6038 | nv_vlan_mode(dev, dev->features); | |
0891b0e0 | 6039 | |
b2ba08e6 JP |
6040 | dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n", |
6041 | dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); | |
6042 | ||
e19df76a | 6043 | dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n", |
b2ba08e6 JP |
6044 | dev->features & NETIF_F_HIGHDMA ? "highdma " : "", |
6045 | dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ? | |
78aea4fc | 6046 | "csum " : "", |
f646968f PM |
6047 | dev->features & (NETIF_F_HW_VLAN_CTAG_RX | |
6048 | NETIF_F_HW_VLAN_CTAG_TX) ? | |
78aea4fc | 6049 | "vlan " : "", |
e19df76a SH |
6050 | dev->features & (NETIF_F_LOOPBACK) ? |
6051 | "loopback " : "", | |
b2ba08e6 JP |
6052 | id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "", |
6053 | id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "", | |
6054 | id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "", | |
6055 | np->gigabit == PHY_GIGABIT ? "gbit " : "", | |
6056 | np->need_linktimer ? "lnktim " : "", | |
6057 | np->msi_flags & NV_MSI_CAPABLE ? "msi " : "", | |
6058 | np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "", | |
6059 | np->desc_ver); | |
1da177e4 LT |
6060 | |
6061 | return 0; | |
6062 | ||
eafa59f6 | 6063 | out_error: |
7e680c22 AA |
6064 | if (phystate_orig) |
6065 | writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); | |
eafa59f6 AA |
6066 | out_freering: |
6067 | free_rings(dev); | |
1da177e4 LT |
6068 | out_unmap: |
6069 | iounmap(get_hwbase(dev)); | |
6070 | out_relreg: | |
6071 | pci_release_regions(pci_dev); | |
6072 | out_disable: | |
6073 | pci_disable_device(pci_dev); | |
6074 | out_free: | |
6075 | free_netdev(dev); | |
6076 | out: | |
6077 | return err; | |
6078 | } | |
6079 | ||
9f3f7910 AA |
6080 | static void nv_restore_phy(struct net_device *dev) |
6081 | { | |
6082 | struct fe_priv *np = netdev_priv(dev); | |
6083 | u16 phy_reserved, mii_control; | |
6084 | ||
6085 | if (np->phy_oui == PHY_OUI_REALTEK && | |
6086 | np->phy_model == PHY_MODEL_REALTEK_8201 && | |
6087 | phy_cross == NV_CROSSOVER_DETECTION_DISABLED) { | |
6088 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); | |
6089 | phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); | |
6090 | phy_reserved &= ~PHY_REALTEK_INIT_MSK1; | |
6091 | phy_reserved |= PHY_REALTEK_INIT8; | |
6092 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); | |
6093 | mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); | |
6094 | ||
6095 | /* restart auto negotiation */ | |
6096 | mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); | |
6097 | mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE); | |
6098 | mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); | |
6099 | } | |
6100 | } | |
6101 | ||
f55c21fd | 6102 | static void nv_restore_mac_addr(struct pci_dev *pci_dev) |
1da177e4 LT |
6103 | { |
6104 | struct net_device *dev = pci_get_drvdata(pci_dev); | |
f1489653 AA |
6105 | struct fe_priv *np = netdev_priv(dev); |
6106 | u8 __iomem *base = get_hwbase(dev); | |
1da177e4 | 6107 | |
f1489653 AA |
6108 | /* special op: write back the misordered MAC address - otherwise |
6109 | * the next nv_probe would see a wrong address. | |
6110 | */ | |
6111 | writel(np->orig_mac[0], base + NvRegMacAddrA); | |
6112 | writel(np->orig_mac[1], base + NvRegMacAddrB); | |