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[linux-block.git] / drivers / net / ethernet / neterion / vxge / vxge-config.c
CommitLineData
40a3a915
RV		 1/******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
9 *
926bd900 10 * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
40a3a915 11 * Virtualized Server Adapter.
926bd900 12 * Copyright(c) 2002-2010 Exar Corp.
40a3a915
RV		 13 ******************************************************************************/
14#include <linux/vmalloc.h>
15#include <linux/etherdevice.h>
16#include <linux/pci.h>
17#include <linux/pci_hotplug.h>
5a0e3ad6 18#include <linux/slab.h>
40a3a915
RV		 19
20#include "vxge-traffic.h"
21#include "vxge-config.h"
8424e00d 22#include "vxge-main.h"
40a3a915 23
528f7272
JM		 24#define VXGE_HW_VPATH_STATS_PIO_READ(offset) { \
25 status = __vxge_hw_vpath_stats_access(vpath, \
26 VXGE_HW_STATS_OP_READ, \
27 offset, \
28 &val64); \
29 if (status != VXGE_HW_OK) \
30 return status; \
42821a5b 31}
32
4d2a5b40
JM		 33static void
34vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
35{
36 u64 val64;
37
38 val64 = readq(&vp_reg->rxmac_vcfg0);
39 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
40 writeq(val64, &vp_reg->rxmac_vcfg0);
41 val64 = readq(&vp_reg->rxmac_vcfg0);
4d2a5b40
JM		 42}
43
44/*
45 * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
46 */
47int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
48{
49 struct vxge_hw_vpath_reg __iomem *vp_reg;
50 struct __vxge_hw_virtualpath *vpath;
51 u64 val64, rxd_count, rxd_spat;
52 int count = 0, total_count = 0;
53
54 vpath = &hldev->virtual_paths[vp_id];
55 vp_reg = vpath->vp_reg;
56
57 vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
58
59 /* Check that the ring controller for this vpath has enough free RxDs
60 * to send frames to the host. This is done by reading the
61 * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
62 * RXD_SPAT value for the vpath.
63 */
64 val64 = readq(&vp_reg->prc_cfg6);
65 rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
66 /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
67 * leg room.
68 */
69 rxd_spat *= 2;
70
71 do {
72 mdelay(1);
73
74 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
75
76 /* Check that the ring controller for this vpath does
77 * not have any frame in its pipeline.
78 */
79 val64 = readq(&vp_reg->frm_in_progress_cnt);
80 if ((rxd_count <= rxd_spat) || (val64 > 0))
81 count = 0;
82 else
83 count++;
84 total_count++;
85 } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
86 (total_count < VXGE_HW_MAX_POLLING_COUNT));
87
88 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
89 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
90 __func__);
91
92 return total_count;
93}
94
95/* vxge_hw_device_wait_receive_idle - This function waits until all frames
96 * stored in the frame buffer for each vpath assigned to the given
97 * function (hldev) have been sent to the host.
98 */
99void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
100{
101 int i, total_count = 0;
102
103 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
104 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
105 continue;
106
107 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
108 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
109 break;
110 }
111}
112
528f7272
JM		 113/*
114 * __vxge_hw_device_register_poll
115 * Will poll certain register for specified amount of time.
116 * Will poll until masked bit is not cleared.
117 */
118static enum vxge_hw_status
119__vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
120{
121 u64 val64;
122 u32 i = 0;
528f7272
JM		 123
124 udelay(10);
125
126 do {
127 val64 = readq(reg);
128 if (!(val64 & mask))
129 return VXGE_HW_OK;
130 udelay(100);
131 } while (++i <= 9);
132
133 i = 0;
134 do {
135 val64 = readq(reg);
136 if (!(val64 & mask))
137 return VXGE_HW_OK;
138 mdelay(1);
139 } while (++i <= max_millis);
140
f6d9b514 141 return VXGE_HW_FAIL;
528f7272
JM		 142}
143
144static inline enum vxge_hw_status
145__vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
146 u64 mask, u32 max_millis)
147{
148 __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
149 wmb();
150 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
151 wmb();
152
153 return __vxge_hw_device_register_poll(addr, mask, max_millis);
154}
155
8424e00d
JM		 156static enum vxge_hw_status
157vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
158 u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
159 u64 *steer_ctrl)
160{
9f9b1645 161 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
8424e00d
JM		 162 enum vxge_hw_status status;
163 u64 val64;
9f9b1645 164 u32 retry = 0, max_retry = 3;
8424e00d 165
9f9b1645
JM		 166 spin_lock(&vpath->lock);
167 if (!vpath->vp_open) {
168 spin_unlock(&vpath->lock);
169 max_retry = 100;
8424e00d
JM		 170 }
171
172 writeq(*data0, &vp_reg->rts_access_steer_data0);
173 writeq(*data1, &vp_reg->rts_access_steer_data1);
174 wmb();
175
176 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
177 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
178 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
179 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
180 *steer_ctrl;
181
182 status = __vxge_hw_pio_mem_write64(val64,
183 &vp_reg->rts_access_steer_ctrl,
184 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
185 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
186
187 /* The __vxge_hw_device_register_poll can udelay for a significant
25985edc 188 * amount of time, blocking other process from the CPU. If it delays
8424e00d
JM		 189 * for ~5secs, a NMI error can occur. A way around this is to give up
190 * the processor via msleep, but this is not allowed is under lock.
191 * So, only allow it to sleep for ~4secs if open. Otherwise, delay for
192 * 1sec and sleep for 10ms until the firmware operation has completed
193 * or timed-out.
194 */
195 while ((status != VXGE_HW_OK) && retry++ < max_retry) {
196 if (!vpath->vp_open)
197 msleep(20);
198 status = __vxge_hw_device_register_poll(
199 &vp_reg->rts_access_steer_ctrl,
200 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
201 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
202 }
203
204 if (status != VXGE_HW_OK)
205 goto out;
206
207 val64 = readq(&vp_reg->rts_access_steer_ctrl);
208 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
209 *data0 = readq(&vp_reg->rts_access_steer_data0);
210 *data1 = readq(&vp_reg->rts_access_steer_data1);
211 *steer_ctrl = val64;
212 } else
213 status = VXGE_HW_FAIL;
214
215out:
216 if (vpath->vp_open)
217 spin_unlock(&vpath->lock);
218 return status;
219}
220
e8ac1756
JM		 221enum vxge_hw_status
222vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
223 u32 *minor, u32 *build)
224{
225 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
226 struct __vxge_hw_virtualpath *vpath;
227 enum vxge_hw_status status;
228
229 vpath = &hldev->virtual_paths[hldev->first_vp_id];
230
231 status = vxge_hw_vpath_fw_api(vpath,
232 VXGE_HW_FW_UPGRADE_ACTION,
233 VXGE_HW_FW_UPGRADE_MEMO,
234 VXGE_HW_FW_UPGRADE_OFFSET_READ,
235 &data0, &data1, &steer_ctrl);
236 if (status != VXGE_HW_OK)
237 return status;
238
239 *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
240 *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
241 *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
242
243 return status;
244}
245
246enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
247{
248 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
249 struct __vxge_hw_virtualpath *vpath;
250 enum vxge_hw_status status;
251 u32 ret;
252
253 vpath = &hldev->virtual_paths[hldev->first_vp_id];
254
255 status = vxge_hw_vpath_fw_api(vpath,
256 VXGE_HW_FW_UPGRADE_ACTION,
257 VXGE_HW_FW_UPGRADE_MEMO,
258 VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
259 &data0, &data1, &steer_ctrl);
260 if (status != VXGE_HW_OK) {
261 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
262 goto exit;
263 }
264
265 ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
266 if (ret != 1) {
267 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
268 __func__, ret);
269 status = VXGE_HW_FAIL;
270 }
271
272exit:
273 return status;
274}
275
276enum vxge_hw_status
277vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
278{
279 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
280 struct __vxge_hw_virtualpath *vpath;
281 enum vxge_hw_status status;
282 int ret_code, sec_code;
283
284 vpath = &hldev->virtual_paths[hldev->first_vp_id];
285
286 /* send upgrade start command */
287 status = vxge_hw_vpath_fw_api(vpath,
288 VXGE_HW_FW_UPGRADE_ACTION,
289 VXGE_HW_FW_UPGRADE_MEMO,
290 VXGE_HW_FW_UPGRADE_OFFSET_START,
291 &data0, &data1, &steer_ctrl);
292 if (status != VXGE_HW_OK) {
293 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
294 __func__);
295 return status;
296 }
297
298 /* Transfer fw image to adapter 16 bytes at a time */
299 for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
300 steer_ctrl = 0;
301
302 /* The next 128bits of fwdata to be loaded onto the adapter */
303 data0 = *((u64 *)fwdata);
304 data1 = *((u64 *)fwdata + 1);
305
306 status = vxge_hw_vpath_fw_api(vpath,
307 VXGE_HW_FW_UPGRADE_ACTION,
308 VXGE_HW_FW_UPGRADE_MEMO,
309 VXGE_HW_FW_UPGRADE_OFFSET_SEND,
310 &data0, &data1, &steer_ctrl);
311 if (status != VXGE_HW_OK) {
312 vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
313 __func__);
314 goto out;
315 }
316
317 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
318 switch (ret_code) {
319 case VXGE_HW_FW_UPGRADE_OK:
320 /* All OK, send next 16 bytes. */
321 break;
322 case VXGE_FW_UPGRADE_BYTES2SKIP:
323 /* skip bytes in the stream */
324 fwdata += (data0 >> 8) & 0xFFFFFFFF;
325 break;
326 case VXGE_HW_FW_UPGRADE_DONE:
327 goto out;
328 case VXGE_HW_FW_UPGRADE_ERR:
329 sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
330 switch (sec_code) {
331 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
332 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
333 printk(KERN_ERR
334 "corrupted data from .ncf file\n");
335 break;
336 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
337 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
338 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
339 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
340 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
341 printk(KERN_ERR "invalid .ncf file\n");
342 break;
343 case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
344 printk(KERN_ERR "buffer overflow\n");
345 break;
346 case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
347 printk(KERN_ERR "failed to flash the image\n");
348 break;
349 case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
350 printk(KERN_ERR
351 "generic error. Unknown error type\n");
352 break;
353 default:
354 printk(KERN_ERR "Unknown error of type %d\n",
355 sec_code);
356 break;
357 }
358 status = VXGE_HW_FAIL;
359 goto out;
360 default:
361 printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
362 status = VXGE_HW_FAIL;
363 goto out;
364 }
365 /* point to next 16 bytes */
366 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
367 }
368out:
369 return status;
370}
371
372enum vxge_hw_status
373vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
374 struct eprom_image *img)
375{
376 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
377 struct __vxge_hw_virtualpath *vpath;
378 enum vxge_hw_status status;
379 int i;
380
381 vpath = &hldev->virtual_paths[hldev->first_vp_id];
382
383 for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
384 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
385 data1 = steer_ctrl = 0;
386
387 status = vxge_hw_vpath_fw_api(vpath,
e8ac1756 388 VXGE_HW_FW_API_GET_EPROM_REV,
1d15f81c 389 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
e8ac1756
JM		 390 0, &data0, &data1, &steer_ctrl);
391 if (status != VXGE_HW_OK)
392 break;
393
394 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
395 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
396 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
397 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
398 }
399
400 return status;
401}
402
40a3a915
RV		 403/*
404 * __vxge_hw_channel_free - Free memory allocated for channel
405 * This function deallocates memory from the channel and various arrays
406 * in the channel
407 */
2c91308f 408static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
40a3a915
RV		 409{
410 kfree(channel->work_arr);
411 kfree(channel->free_arr);
412 kfree(channel->reserve_arr);
413 kfree(channel->orig_arr);
414 kfree(channel);
415}
416
417/*
418 * __vxge_hw_channel_initialize - Initialize a channel
419 * This function initializes a channel by properly setting the
420 * various references
421 */
2c91308f 422static enum vxge_hw_status
40a3a915
RV		 423__vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
424{
425 u32 i;
426 struct __vxge_hw_virtualpath *vpath;
427
428 vpath = channel->vph->vpath;
429
430 if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
431 for (i = 0; i < channel->length; i++)
432 channel->orig_arr[i] = channel->reserve_arr[i];
433 }
434
435 switch (channel->type) {
436 case VXGE_HW_CHANNEL_TYPE_FIFO:
437 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
438 channel->stats = &((struct __vxge_hw_fifo *)
439 channel)->stats->common_stats;
440 break;
441 case VXGE_HW_CHANNEL_TYPE_RING:
442 vpath->ringh = (struct __vxge_hw_ring *)channel;
443 channel->stats = &((struct __vxge_hw_ring *)
444 channel)->stats->common_stats;
445 break;
446 default:
447 break;
448 }
449
450 return VXGE_HW_OK;
451}
452
453/*
454 * __vxge_hw_channel_reset - Resets a channel
455 * This function resets a channel by properly setting the various references
456 */
2c91308f 457static enum vxge_hw_status
40a3a915
RV		 458__vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
459{
460 u32 i;
461
462 for (i = 0; i < channel->length; i++) {
463 if (channel->reserve_arr != NULL)
464 channel->reserve_arr[i] = channel->orig_arr[i];
465 if (channel->free_arr != NULL)
466 channel->free_arr[i] = NULL;
467 if (channel->work_arr != NULL)
468 channel->work_arr[i] = NULL;
469 }
470 channel->free_ptr = channel->length;
471 channel->reserve_ptr = channel->length;
472 channel->reserve_top = 0;
473 channel->post_index = 0;
474 channel->compl_index = 0;
475
476 return VXGE_HW_OK;
477}
478
479/*
480 * __vxge_hw_device_pci_e_init
481 * Initialize certain PCI/PCI-X configuration registers
482 * with recommended values. Save config space for future hw resets.
483 */
2c91308f 484static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
40a3a915
RV		 485{
486 u16 cmd = 0;
487
488 /* Set the PErr Repconse bit and SERR in PCI command register. */
489 pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
490 cmd |= 0x140;
491 pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
492
493 pci_save_state(hldev->pdev);
40a3a915
RV		 494}
495
4d2a5b40 496/* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
40a3a915
RV		 497 * in progress
498 * This routine checks the vpath reset in progress register is turned zero
499 */
42821a5b 500static enum vxge_hw_status
40a3a915
RV		 501__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
502{
503 enum vxge_hw_status status;
504 status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
505 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
506 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
507 return status;
508}
509
528f7272
JM		 510/*
511 * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
512 * Set the swapper bits appropriately for the lagacy section.
513 */
514static enum vxge_hw_status
515__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
516{
517 u64 val64;
518 enum vxge_hw_status status = VXGE_HW_OK;
519
520 val64 = readq(&legacy_reg->toc_swapper_fb);
521
522 wmb();
523
524 switch (val64) {
525 case VXGE_HW_SWAPPER_INITIAL_VALUE:
526 return status;
527
528 case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
529 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
530 &legacy_reg->pifm_rd_swap_en);
531 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
532 &legacy_reg->pifm_rd_flip_en);
533 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
534 &legacy_reg->pifm_wr_swap_en);
535 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
536 &legacy_reg->pifm_wr_flip_en);
537 break;
538
539 case VXGE_HW_SWAPPER_BYTE_SWAPPED:
540 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
541 &legacy_reg->pifm_rd_swap_en);
542 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
543 &legacy_reg->pifm_wr_swap_en);
544 break;
545
546 case VXGE_HW_SWAPPER_BIT_FLIPPED:
547 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
548 &legacy_reg->pifm_rd_flip_en);
549 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
550 &legacy_reg->pifm_wr_flip_en);
551 break;
552 }
553
554 wmb();
555
556 val64 = readq(&legacy_reg->toc_swapper_fb);
557
558 if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
559 status = VXGE_HW_ERR_SWAPPER_CTRL;
560
561 return status;
562}
563
40a3a915
RV		 564/*
565 * __vxge_hw_device_toc_get
566 * This routine sets the swapper and reads the toc pointer and returns the
567 * memory mapped address of the toc
568 */
42821a5b 569static struct vxge_hw_toc_reg __iomem *
40a3a915
RV		 570__vxge_hw_device_toc_get(void __iomem *bar0)
571{
572 u64 val64;
573 struct vxge_hw_toc_reg __iomem *toc = NULL;
574 enum vxge_hw_status status;
575
576 struct vxge_hw_legacy_reg __iomem *legacy_reg =
577 (struct vxge_hw_legacy_reg __iomem *)bar0;
578
579 status = __vxge_hw_legacy_swapper_set(legacy_reg);
580 if (status != VXGE_HW_OK)
581 goto exit;
582
583 val64 = readq(&legacy_reg->toc_first_pointer);
43d620c8 584 toc = bar0 + val64;
40a3a915
RV		 585exit:
586 return toc;
587}
588
589/*
590 * __vxge_hw_device_reg_addr_get
591 * This routine sets the swapper and reads the toc pointer and initializes the
592 * register location pointers in the device object. It waits until the ric is
593 * completed initializing registers.
594 */
2c91308f 595static enum vxge_hw_status
40a3a915
RV		 596__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
597{
598 u64 val64;
599 u32 i;
600 enum vxge_hw_status status = VXGE_HW_OK;
601
43d620c8 602 hldev->legacy_reg = hldev->bar0;
40a3a915
RV		 603
604 hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
605 if (hldev->toc_reg == NULL) {
606 status = VXGE_HW_FAIL;
607 goto exit;
608 }
609
610 val64 = readq(&hldev->toc_reg->toc_common_pointer);
43d620c8 611 hldev->common_reg = hldev->bar0 + val64;
40a3a915
RV		 612
613 val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
43d620c8 614 hldev->mrpcim_reg = hldev->bar0 + val64;
40a3a915
RV		 615
616 for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
617 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
43d620c8 618 hldev->srpcim_reg[i] = hldev->bar0 + val64;
40a3a915
RV		 619 }
620
621 for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
622 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
43d620c8 623 hldev->vpmgmt_reg[i] = hldev->bar0 + val64;
40a3a915
RV		 624 }
625
626 for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
627 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
43d620c8 628 hldev->vpath_reg[i] = hldev->bar0 + val64;
40a3a915
RV		 629 }
630
631 val64 = readq(&hldev->toc_reg->toc_kdfc);
632
633 switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
634 case 0:
43d620c8 635 hldev->kdfc = hldev->bar0 + VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64) ;
40a3a915 636 break;
40a3a915
RV		 637 default:
638 break;
639 }
640
641 status = __vxge_hw_device_vpath_reset_in_prog_check(
642 (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
643exit:
644 return status;
645}
646
40a3a915
RV		 647/*
648 * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
649 * This routine returns the Access Rights of the driver
650 */
651static u32
652__vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
653{
654 u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
655
656 switch (host_type) {
657 case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
1dc47a9b
SH		 658 if (func_id == 0) {
659 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
660 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
661 }
40a3a915
RV		 662 break;
663 case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
664 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
665 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
666 break;
667 case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
668 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
669 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
670 break;
671 case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
672 case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
673 case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
674 break;
675 case VXGE_HW_SR_VH_FUNCTION0:
676 case VXGE_HW_VH_NORMAL_FUNCTION:
677 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
678 break;
679 }
680
681 return access_rights;
682}
92cdd7c3
SH		 683/*
684 * __vxge_hw_device_is_privilaged
685 * This routine checks if the device function is privilaged or not
686 */
687
688enum vxge_hw_status
689__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
690{
691 if (__vxge_hw_device_access_rights_get(host_type,
692 func_id) &
693 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
694 return VXGE_HW_OK;
695 else
7c6f9747 696 return VXGE_HW_ERR_PRIVILEGED_OPERATION;
92cdd7c3
SH		 697}
698
8424e00d
JM		 699/*
700 * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
701 * Returns the function number of the vpath.
702 */
703static u32
704__vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
705{
706 u64 val64;
707
708 val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
709
710 return
711 (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
712}
713
40a3a915
RV		 714/*
715 * __vxge_hw_device_host_info_get
716 * This routine returns the host type assignments
717 */
8424e00d 718static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
40a3a915
RV		 719{
720 u64 val64;
721 u32 i;
722
723 val64 = readq(&hldev->common_reg->host_type_assignments);
724
725 hldev->host_type =
726 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
727
728 hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
729
730 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 731 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
732 continue;
733
734 hldev->func_id =
8424e00d 735 __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
40a3a915
RV		 736
737 hldev->access_rights = __vxge_hw_device_access_rights_get(
738 hldev->host_type, hldev->func_id);
739
8424e00d
JM		 740 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
741 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
742
40a3a915
RV		 743 hldev->first_vp_id = i;
744 break;
745 }
40a3a915
RV		 746}
747
748/*
749 * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
750 * link width and signalling rate.
751 */
752static enum vxge_hw_status
753__vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
754{
95cab738 755 struct pci_dev *dev = hldev->pdev;
40a3a915
RV		 756 u16 lnk;
757
758 /* Get the negotiated link width and speed from PCI config space */
d892aa00 759 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
40a3a915
RV		 760
761 if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
762 return VXGE_HW_ERR_INVALID_PCI_INFO;
763
764 switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
765 case PCIE_LNK_WIDTH_RESRV:
766 case PCIE_LNK_X1:
767 case PCIE_LNK_X2:
768 case PCIE_LNK_X4:
769 case PCIE_LNK_X8:
770 break;
771 default:
772 return VXGE_HW_ERR_INVALID_PCI_INFO;
773 }
774
775 return VXGE_HW_OK;
776}
777
40a3a915
RV		 778/*
779 * __vxge_hw_device_initialize
780 * Initialize Titan-V hardware.
781 */
2c91308f
JM		 782static enum vxge_hw_status
783__vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
40a3a915
RV		 784{
785 enum vxge_hw_status status = VXGE_HW_OK;
786
92cdd7c3
SH		 787 if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
788 hldev->func_id)) {
5dbc9011
SS		 789 /* Validate the pci-e link width and speed */
790 status = __vxge_hw_verify_pci_e_info(hldev);
791 if (status != VXGE_HW_OK)
792 goto exit;
793 }
40a3a915 794
40a3a915
RV		 795exit:
796 return status;
797}
798
8424e00d
JM		 799/*
800 * __vxge_hw_vpath_fw_ver_get - Get the fw version
801 * Returns FW Version
802 */
803static enum vxge_hw_status
804__vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
805 struct vxge_hw_device_hw_info *hw_info)
806{
807 struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
808 struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
809 struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
810 struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
811 u64 data0, data1 = 0, steer_ctrl = 0;
812 enum vxge_hw_status status;
813
814 status = vxge_hw_vpath_fw_api(vpath,
815 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
816 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
817 0, &data0, &data1, &steer_ctrl);
818 if (status != VXGE_HW_OK)
819 goto exit;
820
821 fw_date->day =
822 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
823 fw_date->month =
824 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
825 fw_date->year =
826 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
827
828 snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
829 fw_date->month, fw_date->day, fw_date->year);
830
831 fw_version->major =
832 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
833 fw_version->minor =
834 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
835 fw_version->build =
836 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
837
838 snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
839 fw_version->major, fw_version->minor, fw_version->build);
840
841 flash_date->day =
842 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
843 flash_date->month =
844 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
845 flash_date->year =
846 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
847
848 snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
849 flash_date->month, flash_date->day, flash_date->year);
850
851 flash_version->major =
852 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
853 flash_version->minor =
854 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
855 flash_version->build =
856 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
857
858 snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
859 flash_version->major, flash_version->minor,
860 flash_version->build);
861
862exit:
863 return status;
864}
865
866/*
867 * __vxge_hw_vpath_card_info_get - Get the serial numbers,
868 * part number and product description.
869 */
870static enum vxge_hw_status
871__vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
872 struct vxge_hw_device_hw_info *hw_info)
873{
874 enum vxge_hw_status status;
875 u64 data0, data1 = 0, steer_ctrl = 0;
876 u8 *serial_number = hw_info->serial_number;
877 u8 *part_number = hw_info->part_number;
878 u8 *product_desc = hw_info->product_desc;
879 u32 i, j = 0;
880
881 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
882
883 status = vxge_hw_vpath_fw_api(vpath,
884 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
885 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
886 0, &data0, &data1, &steer_ctrl);
887 if (status != VXGE_HW_OK)
888 return status;
889
890 ((u64 *)serial_number)[0] = be64_to_cpu(data0);
891 ((u64 *)serial_number)[1] = be64_to_cpu(data1);
892
893 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
894 data1 = steer_ctrl = 0;
895
896 status = vxge_hw_vpath_fw_api(vpath,
897 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
898 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
899 0, &data0, &data1, &steer_ctrl);
900 if (status != VXGE_HW_OK)
901 return status;
902
903 ((u64 *)part_number)[0] = be64_to_cpu(data0);
904 ((u64 *)part_number)[1] = be64_to_cpu(data1);
905
906 for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
907 i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
908 data0 = i;
909 data1 = steer_ctrl = 0;
910
911 status = vxge_hw_vpath_fw_api(vpath,
912 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
913 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
914 0, &data0, &data1, &steer_ctrl);
915 if (status != VXGE_HW_OK)
916 return status;
917
918 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
919 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
920 }
921
922 return status;
923}
924
925/*
926 * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
927 * Returns pci function mode
928 */
c3150eac
JM		 929static enum vxge_hw_status
930__vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
931 struct vxge_hw_device_hw_info *hw_info)
8424e00d
JM		 932{
933 u64 data0, data1 = 0, steer_ctrl = 0;
934 enum vxge_hw_status status;
935
ca3e3b8f 936 data0 = 0;
8424e00d
JM		 937
938 status = vxge_hw_vpath_fw_api(vpath,
ca3e3b8f 939 VXGE_HW_FW_API_GET_FUNC_MODE,
8424e00d
JM		 940 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
941 0, &data0, &data1, &steer_ctrl);
c3150eac
JM		 942 if (status != VXGE_HW_OK)
943 return status;
8424e00d 944
ca3e3b8f 945 hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
c3150eac 946 return status;
8424e00d
JM		 947}
948
949/*
950 * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
951 * from MAC address table.
952 */
953static enum vxge_hw_status
954__vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
955 u8 *macaddr, u8 *macaddr_mask)
956{
957 u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
958 data0 = 0, data1 = 0, steer_ctrl = 0;
959 enum vxge_hw_status status;
960 int i;
961
962 do {
963 status = vxge_hw_vpath_fw_api(vpath, action,
964 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
965 0, &data0, &data1, &steer_ctrl);
966 if (status != VXGE_HW_OK)
967 goto exit;
968
969 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
970 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
971 data1);
972
973 for (i = ETH_ALEN; i > 0; i--) {
974 macaddr[i - 1] = (u8) (data0 & 0xFF);
975 data0 >>= 8;
976
977 macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
978 data1 >>= 8;
979 }
980
981 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
982 data0 = 0, data1 = 0, steer_ctrl = 0;
983
984 } while (!is_valid_ether_addr(macaddr));
985exit:
986 return status;
987}
988
40a3a915
RV		 989/**
990 * vxge_hw_device_hw_info_get - Get the hw information
991 * Returns the vpath mask that has the bits set for each vpath allocated
9f9b1645 992 * for the driver, FW version information, and the first mac address for
40a3a915
RV		 993 * each vpath
994 */
3a036ce5 995enum vxge_hw_status
40a3a915
RV		 996vxge_hw_device_hw_info_get(void __iomem *bar0,
997 struct vxge_hw_device_hw_info *hw_info)
998{
999 u32 i;
1000 u64 val64;
1001 struct vxge_hw_toc_reg __iomem *toc;
1002 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1003 struct vxge_hw_common_reg __iomem *common_reg;
40a3a915
RV		 1004 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1005 enum vxge_hw_status status;
8424e00d 1006 struct __vxge_hw_virtualpath vpath;
40a3a915
RV		 1007
1008 memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1009
1010 toc = __vxge_hw_device_toc_get(bar0);
1011 if (toc == NULL) {
1012 status = VXGE_HW_ERR_CRITICAL;
1013 goto exit;
1014 }
1015
1016 val64 = readq(&toc->toc_common_pointer);
43d620c8 1017 common_reg = bar0 + val64;
40a3a915
RV		 1018
1019 status = __vxge_hw_device_vpath_reset_in_prog_check(
1020 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1021 if (status != VXGE_HW_OK)
1022 goto exit;
1023
1024 hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1025
1026 val64 = readq(&common_reg->host_type_assignments);
1027
1028 hw_info->host_type =
1029 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1030
1031 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 1032 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1033 continue;
1034
1035 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1036
43d620c8 1037 vpmgmt_reg = bar0 + val64;
40a3a915 1038
8424e00d 1039 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
40a3a915
RV		 1040 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1041 hw_info->func_id) &
1042 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1043
1044 val64 = readq(&toc->toc_mrpcim_pointer);
1045
43d620c8 1046 mrpcim_reg = bar0 + val64;
40a3a915
RV		 1047
1048 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1049 wmb();
1050 }
1051
1052 val64 = readq(&toc->toc_vpath_pointer[i]);
1053
9f9b1645 1054 spin_lock_init(&vpath.lock);
43d620c8 1055 vpath.vp_reg = bar0 + val64;
9f9b1645 1056 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
40a3a915 1057
c3150eac
JM		 1058 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1059 if (status != VXGE_HW_OK)
1060 goto exit;
40a3a915 1061
8424e00d 1062 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
40a3a915
RV		 1063 if (status != VXGE_HW_OK)
1064 goto exit;
1065
8424e00d 1066 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
40a3a915
RV		 1067 if (status != VXGE_HW_OK)
1068 goto exit;
1069
1070 break;
1071 }
1072
1073 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 1074 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1075 continue;
1076
1077 val64 = readq(&toc->toc_vpath_pointer[i]);
43d620c8 1078 vpath.vp_reg = bar0 + val64;
9f9b1645 1079 vpath.vp_open = VXGE_HW_VP_NOT_OPEN;
40a3a915 1080
8424e00d 1081 status = __vxge_hw_vpath_addr_get(&vpath,
40a3a915
RV		 1082 hw_info->mac_addrs[i],
1083 hw_info->mac_addr_masks[i]);
1084 if (status != VXGE_HW_OK)
1085 goto exit;
1086 }
1087exit:
1088 return status;
1089}
1090
1091/*
528f7272
JM		 1092 * __vxge_hw_blockpool_destroy - Deallocates the block pool
1093 */
1094static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
1095{
1096 struct __vxge_hw_device *hldev;
1097 struct list_head *p, *n;
1098 u16 ret;
1099
1100 if (blockpool == NULL) {
1101 ret = 1;
1102 goto exit;
1103 }
1104
1105 hldev = blockpool->hldev;
1106
1107 list_for_each_safe(p, n, &blockpool->free_block_list) {
1108 pci_unmap_single(hldev->pdev,
1109 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
1110 ((struct __vxge_hw_blockpool_entry *)p)->length,
1111 PCI_DMA_BIDIRECTIONAL);
1112
1113 vxge_os_dma_free(hldev->pdev,
1114 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
1115 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
1116
1117 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1118 kfree(p);
1119 blockpool->pool_size--;
1120 }
1121
1122 list_for_each_safe(p, n, &blockpool->free_entry_list) {
1123 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
1124 kfree((void *)p);
1125 }
1126 ret = 0;
1127exit:
1128 return;
1129}
1130
1131/*
1132 * __vxge_hw_blockpool_create - Create block pool
1133 */
1134static enum vxge_hw_status
1135__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
1136 struct __vxge_hw_blockpool *blockpool,
1137 u32 pool_size,
1138 u32 pool_max)
1139{
1140 u32 i;
1141 struct __vxge_hw_blockpool_entry *entry = NULL;
1142 void *memblock;
1143 dma_addr_t dma_addr;
1144 struct pci_dev *dma_handle;
1145 struct pci_dev *acc_handle;
1146 enum vxge_hw_status status = VXGE_HW_OK;
1147
1148 if (blockpool == NULL) {
1149 status = VXGE_HW_FAIL;
1150 goto blockpool_create_exit;
1151 }
1152
1153 blockpool->hldev = hldev;
1154 blockpool->block_size = VXGE_HW_BLOCK_SIZE;
1155 blockpool->pool_size = 0;
1156 blockpool->pool_max = pool_max;
1157 blockpool->req_out = 0;
1158
1159 INIT_LIST_HEAD(&blockpool->free_block_list);
1160 INIT_LIST_HEAD(&blockpool->free_entry_list);
1161
1162 for (i = 0; i < pool_size + pool_max; i++) {
1163 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1164 GFP_KERNEL);
1165 if (entry == NULL) {
1166 __vxge_hw_blockpool_destroy(blockpool);
1167 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1168 goto blockpool_create_exit;
1169 }
1170 list_add(&entry->item, &blockpool->free_entry_list);
1171 }
1172
1173 for (i = 0; i < pool_size; i++) {
1174 memblock = vxge_os_dma_malloc(
1175 hldev->pdev,
1176 VXGE_HW_BLOCK_SIZE,
1177 &dma_handle,
1178 &acc_handle);
1179 if (memblock == NULL) {
1180 __vxge_hw_blockpool_destroy(blockpool);
1181 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1182 goto blockpool_create_exit;
1183 }
1184
1185 dma_addr = pci_map_single(hldev->pdev, memblock,
1186 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
1187 if (unlikely(pci_dma_mapping_error(hldev->pdev,
1188 dma_addr))) {
1189 vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
1190 __vxge_hw_blockpool_destroy(blockpool);
1191 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1192 goto blockpool_create_exit;
1193 }
1194
1195 if (!list_empty(&blockpool->free_entry_list))
1196 entry = (struct __vxge_hw_blockpool_entry *)
1197 list_first_entry(&blockpool->free_entry_list,
1198 struct __vxge_hw_blockpool_entry,
1199 item);
1200
1201 if (entry == NULL)
1202 entry =
1203 kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
1204 GFP_KERNEL);
1205 if (entry != NULL) {
1206 list_del(&entry->item);
1207 entry->length = VXGE_HW_BLOCK_SIZE;
1208 entry->memblock = memblock;
1209 entry->dma_addr = dma_addr;
1210 entry->acc_handle = acc_handle;
1211 entry->dma_handle = dma_handle;
1212 list_add(&entry->item,
1213 &blockpool->free_block_list);
1214 blockpool->pool_size++;
1215 } else {
1216 __vxge_hw_blockpool_destroy(blockpool);
1217 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1218 goto blockpool_create_exit;
1219 }
1220 }
1221
1222blockpool_create_exit:
1223 return status;
1224}
1225
1226/*
1227 * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1228 * Check the fifo configuration
1229 */
1230static enum vxge_hw_status
1231__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1232{
1233 if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1234 (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1235 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1236
1237 return VXGE_HW_OK;
1238}
1239
1240/*
1241 * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1242 * Check the vpath configuration
1243 */
1244static enum vxge_hw_status
1245__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1246{
1247 enum vxge_hw_status status;
1248
1249 if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1250 (vp_config->min_bandwidth > VXGE_HW_VPATH_BANDWIDTH_MAX))
1251 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1252
1253 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1254 if (status != VXGE_HW_OK)
1255 return status;
1256
1257 if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1258 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1259 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1260 return VXGE_HW_BADCFG_VPATH_MTU;
1261
1262 if ((vp_config->rpa_strip_vlan_tag !=
1263 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1264 (vp_config->rpa_strip_vlan_tag !=
1265 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1266 (vp_config->rpa_strip_vlan_tag !=
1267 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1268 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1269
1270 return VXGE_HW_OK;
1271}
1272
1273/*
1274 * __vxge_hw_device_config_check - Check device configuration.
1275 * Check the device configuration
1276 */
1277static enum vxge_hw_status
1278__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1279{
1280 u32 i;
1281 enum vxge_hw_status status;
1282
1283 if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1284 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1285 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1286 (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1287 return VXGE_HW_BADCFG_INTR_MODE;
1288
1289 if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1290 (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1291 return VXGE_HW_BADCFG_RTS_MAC_EN;
1292
1293 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1294 status = __vxge_hw_device_vpath_config_check(
1295 &new_config->vp_config[i]);
1296 if (status != VXGE_HW_OK)
1297 return status;
1298 }
1299
1300 return VXGE_HW_OK;
1301}
1302
1303/*
1304 * vxge_hw_device_initialize - Initialize Titan device.
1305 * Initialize Titan device. Note that all the arguments of this public API
1306 * are 'IN', including @hldev. Driver cooperates with
40a3a915
RV		 1307 * OS to find new Titan device, locate its PCI and memory spaces.
1308 *
1309 * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1310 * to enable the latter to perform Titan hardware initialization.
1311 */
3a036ce5 1312enum vxge_hw_status
40a3a915
RV		 1313vxge_hw_device_initialize(
1314 struct __vxge_hw_device **devh,
1315 struct vxge_hw_device_attr *attr,
1316 struct vxge_hw_device_config *device_config)
1317{
1318 u32 i;
1319 u32 nblocks = 0;
1320 struct __vxge_hw_device *hldev = NULL;
1321 enum vxge_hw_status status = VXGE_HW_OK;
1322
1323 status = __vxge_hw_device_config_check(device_config);
1324 if (status != VXGE_HW_OK)
1325 goto exit;
1326
e80be0b0 1327 hldev = vzalloc(sizeof(struct __vxge_hw_device));
40a3a915
RV		 1328 if (hldev == NULL) {
1329 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1330 goto exit;
1331 }
1332
40a3a915
RV		 1333 hldev->magic = VXGE_HW_DEVICE_MAGIC;
1334
1335 vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1336
1337 /* apply config */
1338 memcpy(&hldev->config, device_config,
1339 sizeof(struct vxge_hw_device_config));
1340
1341 hldev->bar0 = attr->bar0;
40a3a915
RV		 1342 hldev->pdev = attr->pdev;
1343
956a2066 1344 hldev->uld_callbacks = attr->uld_callbacks;
40a3a915
RV		 1345
1346 __vxge_hw_device_pci_e_init(hldev);
1347
1348 status = __vxge_hw_device_reg_addr_get(hldev);
aaffbd9f
SH		 1349 if (status != VXGE_HW_OK) {
1350 vfree(hldev);
40a3a915 1351 goto exit;
aaffbd9f 1352 }
40a3a915
RV		 1353
1354 __vxge_hw_device_host_info_get(hldev);
1355
1356 /* Incrementing for stats blocks */
1357 nblocks++;
1358
1359 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 1360 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1361 continue;
1362
1363 if (device_config->vp_config[i].ring.enable ==
1364 VXGE_HW_RING_ENABLE)
1365 nblocks += device_config->vp_config[i].ring.ring_blocks;
1366
1367 if (device_config->vp_config[i].fifo.enable ==
1368 VXGE_HW_FIFO_ENABLE)
1369 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1370 nblocks++;
1371 }
1372
1373 if (__vxge_hw_blockpool_create(hldev,
1374 &hldev->block_pool,
1375 device_config->dma_blockpool_initial + nblocks,
1376 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1377
1378 vxge_hw_device_terminate(hldev);
1379 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1380 goto exit;
1381 }
1382
1383 status = __vxge_hw_device_initialize(hldev);
40a3a915
RV		 1384 if (status != VXGE_HW_OK) {
1385 vxge_hw_device_terminate(hldev);
1386 goto exit;
1387 }
1388
1389 *devh = hldev;
1390exit:
1391 return status;
1392}
1393
1394/*
1395 * vxge_hw_device_terminate - Terminate Titan device.
1396 * Terminate HW device.
1397 */
1398void
1399vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1400{
1401 vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1402
1403 hldev->magic = VXGE_HW_DEVICE_DEAD;
1404 __vxge_hw_blockpool_destroy(&hldev->block_pool);
1405 vfree(hldev);
1406}
1407
1408/*
528f7272
JM		 1409 * __vxge_hw_vpath_stats_access - Get the statistics from the given location
1410 * and offset and perform an operation
40a3a915 1411 */
528f7272
JM		 1412static enum vxge_hw_status
1413__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
1414 u32 operation, u32 offset, u64 *stat)
40a3a915 1415{
528f7272 1416 u64 val64;
40a3a915 1417 enum vxge_hw_status status = VXGE_HW_OK;
528f7272 1418 struct vxge_hw_vpath_reg __iomem *vp_reg;
40a3a915 1419
528f7272
JM		 1420 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1421 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1422 goto vpath_stats_access_exit;
1423 }
40a3a915 1424
528f7272 1425 vp_reg = vpath->vp_reg;
40a3a915 1426
528f7272
JM		 1427 val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
1428 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
1429 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
40a3a915 1430
528f7272
JM		 1431 status = __vxge_hw_pio_mem_write64(val64,
1432 &vp_reg->xmac_stats_access_cmd,
1433 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
1434 vpath->hldev->config.device_poll_millis);
1435 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1436 *stat = readq(&vp_reg->xmac_stats_access_data);
1437 else
1438 *stat = 0;
40a3a915 1439
528f7272 1440vpath_stats_access_exit:
40a3a915
RV		 1441 return status;
1442}
1443
1444/*
528f7272
JM		 1445 * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
1446 */
1447static enum vxge_hw_status
1448__vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
1449 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
1450{
1451 u64 *val64;
1452 int i;
1453 u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
1454 enum vxge_hw_status status = VXGE_HW_OK;
1455
1456 val64 = (u64 *)vpath_tx_stats;
1457
1458 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1459 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1460 goto exit;
1461 }
1462
1463 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
1464 status = __vxge_hw_vpath_stats_access(vpath,
1465 VXGE_HW_STATS_OP_READ,
1466 offset, val64);
1467 if (status != VXGE_HW_OK)
1468 goto exit;
1469 offset++;
1470 val64++;
1471 }
1472exit:
1473 return status;
1474}
1475
1476/*
1477 * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
1478 */
1479static enum vxge_hw_status
1480__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
1481 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
1482{
1483 u64 *val64;
1484 enum vxge_hw_status status = VXGE_HW_OK;
1485 int i;
1486 u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
1487 val64 = (u64 *) vpath_rx_stats;
1488
1489 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1490 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1491 goto exit;
1492 }
1493 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
1494 status = __vxge_hw_vpath_stats_access(vpath,
1495 VXGE_HW_STATS_OP_READ,
1496 offset >> 3, val64);
1497 if (status != VXGE_HW_OK)
1498 goto exit;
1499
1500 offset += 8;
1501 val64++;
1502 }
1503exit:
1504 return status;
1505}
1506
1507/*
1508 * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
1509 */
1510static enum vxge_hw_status
1511__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
1512 struct vxge_hw_vpath_stats_hw_info *hw_stats)
1513{
1514 u64 val64;
1515 enum vxge_hw_status status = VXGE_HW_OK;
1516 struct vxge_hw_vpath_reg __iomem *vp_reg;
1517
1518 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
1519 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
1520 goto exit;
1521 }
1522 vp_reg = vpath->vp_reg;
1523
1524 val64 = readq(&vp_reg->vpath_debug_stats0);
1525 hw_stats->ini_num_mwr_sent =
1526 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
1527
1528 val64 = readq(&vp_reg->vpath_debug_stats1);
1529 hw_stats->ini_num_mrd_sent =
1530 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
1531
1532 val64 = readq(&vp_reg->vpath_debug_stats2);
1533 hw_stats->ini_num_cpl_rcvd =
1534 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
1535
1536 val64 = readq(&vp_reg->vpath_debug_stats3);
1537 hw_stats->ini_num_mwr_byte_sent =
1538 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
1539
1540 val64 = readq(&vp_reg->vpath_debug_stats4);
1541 hw_stats->ini_num_cpl_byte_rcvd =
1542 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
1543
1544 val64 = readq(&vp_reg->vpath_debug_stats5);
1545 hw_stats->wrcrdtarb_xoff =
1546 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
1547
1548 val64 = readq(&vp_reg->vpath_debug_stats6);
1549 hw_stats->rdcrdtarb_xoff =
1550 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
1551
1552 val64 = readq(&vp_reg->vpath_genstats_count01);
1553 hw_stats->vpath_genstats_count0 =
1554 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
1555 val64);
1556
1557 val64 = readq(&vp_reg->vpath_genstats_count01);
1558 hw_stats->vpath_genstats_count1 =
1559 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
1560 val64);
1561
1562 val64 = readq(&vp_reg->vpath_genstats_count23);
1563 hw_stats->vpath_genstats_count2 =
1564 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
1565 val64);
1566
1567 val64 = readq(&vp_reg->vpath_genstats_count01);
1568 hw_stats->vpath_genstats_count3 =
1569 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
1570 val64);
1571
1572 val64 = readq(&vp_reg->vpath_genstats_count4);
1573 hw_stats->vpath_genstats_count4 =
1574 (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
1575 val64);
1576
1577 val64 = readq(&vp_reg->vpath_genstats_count5);
1578 hw_stats->vpath_genstats_count5 =
1579 (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
1580 val64);
1581
1582 status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
1583 if (status != VXGE_HW_OK)
1584 goto exit;
1585
1586 status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
1587 if (status != VXGE_HW_OK)
1588 goto exit;
1589
1590 VXGE_HW_VPATH_STATS_PIO_READ(
1591 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
1592
1593 hw_stats->prog_event_vnum0 =
1594 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
1595
1596 hw_stats->prog_event_vnum1 =
1597 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
1598
1599 VXGE_HW_VPATH_STATS_PIO_READ(
1600 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
1601
1602 hw_stats->prog_event_vnum2 =
1603 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
1604
1605 hw_stats->prog_event_vnum3 =
1606 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
1607
1608 val64 = readq(&vp_reg->rx_multi_cast_stats);
1609 hw_stats->rx_multi_cast_frame_discard =
1610 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
1611
1612 val64 = readq(&vp_reg->rx_frm_transferred);
1613 hw_stats->rx_frm_transferred =
1614 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
1615
1616 val64 = readq(&vp_reg->rxd_returned);
1617 hw_stats->rxd_returned =
1618 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
1619
1620 val64 = readq(&vp_reg->dbg_stats_rx_mpa);
1621 hw_stats->rx_mpa_len_fail_frms =
1622 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
1623 hw_stats->rx_mpa_mrk_fail_frms =
1624 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
1625 hw_stats->rx_mpa_crc_fail_frms =
1626 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
1627
1628 val64 = readq(&vp_reg->dbg_stats_rx_fau);
1629 hw_stats->rx_permitted_frms =
1630 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
1631 hw_stats->rx_vp_reset_discarded_frms =
1632 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
1633 hw_stats->rx_wol_frms =
1634 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
1635
1636 val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
1637 hw_stats->tx_vp_reset_discarded_frms =
1638 (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
1639 val64);
1640exit:
1641 return status;
1642}
1643
1644/*
1645 * vxge_hw_device_stats_get - Get the device hw statistics.
1646 * Returns the vpath h/w stats for the device.
1647 */
1648enum vxge_hw_status
1649vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1650 struct vxge_hw_device_stats_hw_info *hw_stats)
1651{
1652 u32 i;
1653 enum vxge_hw_status status = VXGE_HW_OK;
1654
1655 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1656 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1657 (hldev->virtual_paths[i].vp_open ==
1658 VXGE_HW_VP_NOT_OPEN))
1659 continue;
1660
1661 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1662 hldev->virtual_paths[i].hw_stats,
1663 sizeof(struct vxge_hw_vpath_stats_hw_info));
1664
1665 status = __vxge_hw_vpath_stats_get(
1666 &hldev->virtual_paths[i],
1667 hldev->virtual_paths[i].hw_stats);
1668 }
1669
1670 memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1671 sizeof(struct vxge_hw_device_stats_hw_info));
1672
1673 return status;
1674}
1675
1676/*
1677 * vxge_hw_driver_stats_get - Get the device sw statistics.
1678 * Returns the vpath s/w stats for the device.
40a3a915
RV		 1679 */
1680enum vxge_hw_status vxge_hw_driver_stats_get(
1681 struct __vxge_hw_device *hldev,
1682 struct vxge_hw_device_stats_sw_info *sw_stats)
1683{
40a3a915
RV		 1684 memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1685 sizeof(struct vxge_hw_device_stats_sw_info));
1686
f6d9b514 1687 return VXGE_HW_OK;
40a3a915
RV		 1688}
1689
1690/*
1691 * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1692 * and offset and perform an operation
1693 * Get the statistics from the given location and offset.
1694 */
1695enum vxge_hw_status
1696vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1697 u32 operation, u32 location, u32 offset, u64 *stat)
1698{
1699 u64 val64;
1700 enum vxge_hw_status status = VXGE_HW_OK;
1701
92cdd7c3
SH		 1702 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1703 hldev->func_id);
40a3a915
RV		 1704 if (status != VXGE_HW_OK)
1705 goto exit;
1706
1707 val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1708 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1709 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1710 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1711
1712 status = __vxge_hw_pio_mem_write64(val64,
1713 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1714 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1715 hldev->config.device_poll_millis);
1716
1717 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1718 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1719 else
1720 *stat = 0;
1721exit:
1722 return status;
1723}
1724
1725/*
1726 * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1727 * Get the Statistics on aggregate port
1728 */
42821a5b 1729static enum vxge_hw_status
40a3a915
RV		 1730vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1731 struct vxge_hw_xmac_aggr_stats *aggr_stats)
1732{
1733 u64 *val64;
1734 int i;
1735 u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1736 enum vxge_hw_status status = VXGE_HW_OK;
1737
1738 val64 = (u64 *)aggr_stats;
1739
92cdd7c3
SH		 1740 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1741 hldev->func_id);
40a3a915
RV		 1742 if (status != VXGE_HW_OK)
1743 goto exit;
1744
1745 for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1746 status = vxge_hw_mrpcim_stats_access(hldev,
1747 VXGE_HW_STATS_OP_READ,
1748 VXGE_HW_STATS_LOC_AGGR,
1749 ((offset + (104 * port)) >> 3), val64);
1750 if (status != VXGE_HW_OK)
1751 goto exit;
1752
1753 offset += 8;
1754 val64++;
1755 }
1756exit:
1757 return status;
1758}
1759
1760/*
1761 * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1762 * Get the Statistics on port
1763 */
42821a5b 1764static enum vxge_hw_status
40a3a915
RV		 1765vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1766 struct vxge_hw_xmac_port_stats *port_stats)
1767{
1768 u64 *val64;
1769 enum vxge_hw_status status = VXGE_HW_OK;
1770 int i;
1771 u32 offset = 0x0;
1772 val64 = (u64 *) port_stats;
1773
92cdd7c3
SH		 1774 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1775 hldev->func_id);
40a3a915
RV		 1776 if (status != VXGE_HW_OK)
1777 goto exit;
1778
1779 for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1780 status = vxge_hw_mrpcim_stats_access(hldev,
1781 VXGE_HW_STATS_OP_READ,
1782 VXGE_HW_STATS_LOC_AGGR,
1783 ((offset + (608 * port)) >> 3), val64);
1784 if (status != VXGE_HW_OK)
1785 goto exit;
1786
1787 offset += 8;
1788 val64++;
1789 }
1790
1791exit:
1792 return status;
1793}
1794
1795/*
1796 * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1797 * Get the XMAC Statistics
1798 */
1799enum vxge_hw_status
1800vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1801 struct vxge_hw_xmac_stats *xmac_stats)
1802{
1803 enum vxge_hw_status status = VXGE_HW_OK;
1804 u32 i;
1805
1806 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1807 0, &xmac_stats->aggr_stats[0]);
40a3a915
RV		 1808 if (status != VXGE_HW_OK)
1809 goto exit;
1810
1811 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1812 1, &xmac_stats->aggr_stats[1]);
1813 if (status != VXGE_HW_OK)
1814 goto exit;
1815
1816 for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1817
1818 status = vxge_hw_device_xmac_port_stats_get(hldev,
1819 i, &xmac_stats->port_stats[i]);
1820 if (status != VXGE_HW_OK)
1821 goto exit;
1822 }
1823
1824 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1825
1826 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1827 continue;
1828
1829 status = __vxge_hw_vpath_xmac_tx_stats_get(
1830 &hldev->virtual_paths[i],
1831 &xmac_stats->vpath_tx_stats[i]);
1832 if (status != VXGE_HW_OK)
1833 goto exit;
1834
1835 status = __vxge_hw_vpath_xmac_rx_stats_get(
1836 &hldev->virtual_paths[i],
1837 &xmac_stats->vpath_rx_stats[i]);
1838 if (status != VXGE_HW_OK)
1839 goto exit;
1840 }
1841exit:
1842 return status;
1843}
1844
1845/*
1846 * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1847 * This routine is used to dynamically change the debug output
1848 */
1849void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1850 enum vxge_debug_level level, u32 mask)
1851{
1852 if (hldev == NULL)
1853 return;
1854
1855#if defined(VXGE_DEBUG_TRACE_MASK) || \
1856 defined(VXGE_DEBUG_ERR_MASK)
1857 hldev->debug_module_mask = mask;
1858 hldev->debug_level = level;
1859#endif
1860
1861#if defined(VXGE_DEBUG_ERR_MASK)
1862 hldev->level_err = level & VXGE_ERR;
1863#endif
1864
1865#if defined(VXGE_DEBUG_TRACE_MASK)
1866 hldev->level_trace = level & VXGE_TRACE;
1867#endif
1868}
1869
1870/*
1871 * vxge_hw_device_error_level_get - Get the error level
1872 * This routine returns the current error level set
1873 */
1874u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1875{
1876#if defined(VXGE_DEBUG_ERR_MASK)
1877 if (hldev == NULL)
1878 return VXGE_ERR;
1879 else
1880 return hldev->level_err;
1881#else
1882 return 0;
1883#endif
1884}
1885
1886/*
1887 * vxge_hw_device_trace_level_get - Get the trace level
1888 * This routine returns the current trace level set
1889 */
1890u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1891{
1892#if defined(VXGE_DEBUG_TRACE_MASK)
1893 if (hldev == NULL)
1894 return VXGE_TRACE;
1895 else
1896 return hldev->level_trace;
1897#else
1898 return 0;
1899#endif
1900}
40a3a915
RV		 1901
1902/*
1903 * vxge_hw_getpause_data -Pause frame frame generation and reception.
1904 * Returns the Pause frame generation and reception capability of the NIC.
1905 */
1906enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1907 u32 port, u32 *tx, u32 *rx)
1908{
1909 u64 val64;
1910 enum vxge_hw_status status = VXGE_HW_OK;
1911
1912 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1913 status = VXGE_HW_ERR_INVALID_DEVICE;
1914 goto exit;
1915 }
1916
1917 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1918 status = VXGE_HW_ERR_INVALID_PORT;
1919 goto exit;
1920 }
1921
1922 if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
7c6f9747 1923 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
40a3a915
RV		 1924 goto exit;
1925 }
1926
1927 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1928 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1929 *tx = 1;
1930 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1931 *rx = 1;
1932exit:
1933 return status;
1934}
1935
1936/*
1937 * vxge_hw_device_setpause_data - set/reset pause frame generation.
1938 * It can be used to set or reset Pause frame generation or reception
1939 * support of the NIC.
1940 */
40a3a915
RV		 1941enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1942 u32 port, u32 tx, u32 rx)
1943{
1944 u64 val64;
1945 enum vxge_hw_status status = VXGE_HW_OK;
1946
1947 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1948 status = VXGE_HW_ERR_INVALID_DEVICE;
1949 goto exit;
1950 }
1951
1952 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1953 status = VXGE_HW_ERR_INVALID_PORT;
1954 goto exit;
1955 }
1956
92cdd7c3
SH		 1957 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1958 hldev->func_id);
40a3a915
RV		 1959 if (status != VXGE_HW_OK)
1960 goto exit;
1961
1962 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1963 if (tx)
1964 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1965 else
1966 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1967 if (rx)
1968 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1969 else
1970 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1971
1972 writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1973exit:
1974 return status;
1975}
1976
1977u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1978{
95cab738 1979 struct pci_dev *dev = hldev->pdev;
40a3a915
RV		 1980 u16 lnk;
1981
d892aa00 1982 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnk);
95cab738 1983 return (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
40a3a915
RV		 1984}
1985
1986/*
1987 * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1988 * This function returns the index of memory block
1989 */
1990static inline u32
1991__vxge_hw_ring_block_memblock_idx(u8 *block)
1992{
1993 return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1994}
1995
1996/*
1997 * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1998 * This function sets index to a memory block
1999 */
2000static inline void
2001__vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
2002{
2003 *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
2004}
2005
2006/*
2007 * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
2008 * in RxD block
2009 * Sets the next block pointer in RxD block
2010 */
2011static inline void
2012__vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
2013{
2014 *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
2015}
2016
2017/*
2018 * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
2019 * first block
2020 * Returns the dma address of the first RxD block
2021 */
42821a5b 2022static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
40a3a915
RV		 2023{
2024 struct vxge_hw_mempool_dma *dma_object;
2025
2026 dma_object = ring->mempool->memblocks_dma_arr;
2027 vxge_assert(dma_object != NULL);
2028
2029 return dma_object->addr;
2030}
2031
2032/*
2033 * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
2034 * This function returns the dma address of a given item
2035 */
2036static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
2037 void *item)
2038{
2039 u32 memblock_idx;
2040 void *memblock;
2041 struct vxge_hw_mempool_dma *memblock_dma_object;
2042 ptrdiff_t dma_item_offset;
2043
2044 /* get owner memblock index */
2045 memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
2046
2047 /* get owner memblock by memblock index */
2048 memblock = mempoolh->memblocks_arr[memblock_idx];
2049
2050 /* get memblock DMA object by memblock index */
2051 memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
2052
2053 /* calculate offset in the memblock of this item */
2054 dma_item_offset = (u8 *)item - (u8 *)memblock;
2055
2056 return memblock_dma_object->addr + dma_item_offset;
2057}
2058
2059/*
2060 * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
2061 * This function returns the dma address of a given item
2062 */
2063static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
2064 struct __vxge_hw_ring *ring, u32 from,
2065 u32 to)
2066{
2067 u8 *to_item , *from_item;
2068 dma_addr_t to_dma;
2069
2070 /* get "from" RxD block */
2071 from_item = mempoolh->items_arr[from];
2072 vxge_assert(from_item);
2073
2074 /* get "to" RxD block */
2075 to_item = mempoolh->items_arr[to];
2076 vxge_assert(to_item);
2077
2078 /* return address of the beginning of previous RxD block */
2079 to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
2080
2081 /* set next pointer for this RxD block to point on
2082 * previous item's DMA start address */
2083 __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
2084}
2085
2086/*
2087 * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
2088 * block callback
2089 * This function is callback passed to __vxge_hw_mempool_create to create memory
2090 * pool for RxD block
2091 */
2092static void
2093__vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
2094 u32 memblock_index,
2095 struct vxge_hw_mempool_dma *dma_object,
2096 u32 index, u32 is_last)
2097{
2098 u32 i;
2099 void *item = mempoolh->items_arr[index];
2100 struct __vxge_hw_ring *ring =
2101 (struct __vxge_hw_ring *)mempoolh->userdata;
2102
2103 /* format rxds array */
2104 for (i = 0; i < ring->rxds_per_block; i++) {
2105 void *rxdblock_priv;
2106 void *uld_priv;
2107 struct vxge_hw_ring_rxd_1 *rxdp;
2108
2109 u32 reserve_index = ring->channel.reserve_ptr -
2110 (index * ring->rxds_per_block + i + 1);
2111 u32 memblock_item_idx;
2112
2113 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
2114 i * ring->rxd_size;
2115
2116 /* Note: memblock_item_idx is index of the item within
2117 * the memblock. For instance, in case of three RxD-blocks
2118 * per memblock this value can be 0, 1 or 2. */
2119 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
2120 memblock_index, item,
2121 &memblock_item_idx);
2122
43d620c8 2123 rxdp = ring->channel.reserve_arr[reserve_index];
40a3a915
RV		 2124
2125 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
2126
2127 /* pre-format Host_Control */
2128 rxdp->host_control = (u64)(size_t)uld_priv;
2129 }
2130
2131 __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
2132
2133 if (is_last) {
2134 /* link last one with first one */
2135 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
2136 }
2137
2138 if (index > 0) {
2139 /* link this RxD block with previous one */
2140 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
2141 }
40a3a915
RV		 2142}
2143
2144/*
3363276f 2145 * __vxge_hw_ring_replenish - Initial replenish of RxDs
40a3a915
RV		 2146 * This function replenishes the RxDs from reserve array to work array
2147 */
e40c10fc 2148static enum vxge_hw_status
3363276f 2149vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
40a3a915
RV		 2150{
2151 void *rxd;
40a3a915
RV		 2152 struct __vxge_hw_channel *channel;
2153 enum vxge_hw_status status = VXGE_HW_OK;
2154
2155 channel = &ring->channel;
2156
2157 while (vxge_hw_channel_dtr_count(channel) > 0) {
2158
2159 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
2160
2161 vxge_assert(status == VXGE_HW_OK);
2162
2163 if (ring->rxd_init) {
2164 status = ring->rxd_init(rxd, channel->userdata);
2165 if (status != VXGE_HW_OK) {
2166 vxge_hw_ring_rxd_free(ring, rxd);
2167 goto exit;
2168 }
2169 }
2170
2171 vxge_hw_ring_rxd_post(ring, rxd);
40a3a915
RV		 2172 }
2173 status = VXGE_HW_OK;
2174exit:
2175 return status;
2176}
2177
2178/*
528f7272
JM		 2179 * __vxge_hw_channel_allocate - Allocate memory for channel
2180 * This function allocates required memory for the channel and various arrays
2181 * in the channel
40a3a915 2182 */
528f7272
JM		 2183static struct __vxge_hw_channel *
2184__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
2185 enum __vxge_hw_channel_type type,
2186 u32 length, u32 per_dtr_space,
2187 void *userdata)
40a3a915 2188{
528f7272 2189 struct __vxge_hw_channel *channel;
40a3a915 2190 struct __vxge_hw_device *hldev;
528f7272 2191 int size = 0;
40a3a915 2192 u32 vp_id;
40a3a915 2193
528f7272
JM		 2194 hldev = vph->vpath->hldev;
2195 vp_id = vph->vpath->vp_id;
40a3a915 2196
528f7272
JM		 2197 switch (type) {
2198 case VXGE_HW_CHANNEL_TYPE_FIFO:
2199 size = sizeof(struct __vxge_hw_fifo);
2200 break;
2201 case VXGE_HW_CHANNEL_TYPE_RING:
2202 size = sizeof(struct __vxge_hw_ring);
2203 break;
2204 default:
2205 break;
40a3a915
RV		 2206 }
2207
528f7272
JM		 2208 channel = kzalloc(size, GFP_KERNEL);
2209 if (channel == NULL)
2210 goto exit0;
2211 INIT_LIST_HEAD(&channel->item);
40a3a915 2212
528f7272
JM		 2213 channel->common_reg = hldev->common_reg;
2214 channel->first_vp_id = hldev->first_vp_id;
2215 channel->type = type;
2216 channel->devh = hldev;
2217 channel->vph = vph;
2218 channel->userdata = userdata;
2219 channel->per_dtr_space = per_dtr_space;
2220 channel->length = length;
2221 channel->vp_id = vp_id;
40a3a915 2222
6396bb22 2223 channel->work_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
528f7272
JM		 2224 if (channel->work_arr == NULL)
2225 goto exit1;
40a3a915 2226
6396bb22 2227 channel->free_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
528f7272
JM		 2228 if (channel->free_arr == NULL)
2229 goto exit1;
2230 channel->free_ptr = length;
40a3a915 2231
6396bb22 2232 channel->reserve_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
528f7272
JM		 2233 if (channel->reserve_arr == NULL)
2234 goto exit1;
2235 channel->reserve_ptr = length;
2236 channel->reserve_top = 0;
40a3a915 2237
6396bb22 2238 channel->orig_arr = kcalloc(length, sizeof(void *), GFP_KERNEL);
528f7272
JM		 2239 if (channel->orig_arr == NULL)
2240 goto exit1;
40a3a915 2241
528f7272
JM		 2242 return channel;
2243exit1:
2244 __vxge_hw_channel_free(channel);
40a3a915 2245
528f7272
JM		 2246exit0:
2247 return NULL;
40a3a915
RV		 2248}
2249
2250/*
528f7272
JM		 2251 * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
2252 * Adds a block to block pool
40a3a915 2253 */
528f7272
JM		 2254static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
2255 void *block_addr,
2256 u32 length,
2257 struct pci_dev *dma_h,
2258 struct pci_dev *acc_handle)
40a3a915 2259{
528f7272
JM		 2260 struct __vxge_hw_blockpool *blockpool;
2261 struct __vxge_hw_blockpool_entry *entry = NULL;
2262 dma_addr_t dma_addr;
2263 enum vxge_hw_status status = VXGE_HW_OK;
2264 u32 req_out;
40a3a915 2265
528f7272 2266 blockpool = &devh->block_pool;
40a3a915 2267
528f7272
JM		 2268 if (block_addr == NULL) {
2269 blockpool->req_out--;
2270 status = VXGE_HW_FAIL;
2271 goto exit;
2272 }
40a3a915 2273
528f7272
JM		 2274 dma_addr = pci_map_single(devh->pdev, block_addr, length,
2275 PCI_DMA_BIDIRECTIONAL);
40a3a915 2276
528f7272
JM		 2277 if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
2278 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
2279 blockpool->req_out--;
2280 status = VXGE_HW_FAIL;
2281 goto exit;
2282 }
40a3a915 2283
528f7272
JM		 2284 if (!list_empty(&blockpool->free_entry_list))
2285 entry = (struct __vxge_hw_blockpool_entry *)
2286 list_first_entry(&blockpool->free_entry_list,
2287 struct __vxge_hw_blockpool_entry,
2288 item);
40a3a915 2289
528f7272
JM		 2290 if (entry == NULL)
2291 entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
2292 else
2293 list_del(&entry->item);
40a3a915 2294
528f7272
JM		 2295 if (entry != NULL) {
2296 entry->length = length;
2297 entry->memblock = block_addr;
2298 entry->dma_addr = dma_addr;
2299 entry->acc_handle = acc_handle;
2300 entry->dma_handle = dma_h;
2301 list_add(&entry->item, &blockpool->free_block_list);
2302 blockpool->pool_size++;
2303 status = VXGE_HW_OK;
2304 } else
2305 status = VXGE_HW_ERR_OUT_OF_MEMORY;
40a3a915 2306
528f7272 2307 blockpool->req_out--;
40a3a915 2308
528f7272
JM		 2309 req_out = blockpool->req_out;
2310exit:
2311 return;
2312}
40a3a915 2313
528f7272
JM		 2314static inline void
2315vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, unsigned long size)
2316{
2317 gfp_t flags;
2318 void *vaddr;
40a3a915 2319
528f7272
JM		 2320 if (in_interrupt())
2321 flags = GFP_ATOMIC | GFP_DMA;
2322 else
2323 flags = GFP_KERNEL | GFP_DMA;
40a3a915 2324
528f7272 2325 vaddr = kmalloc((size), flags);
40a3a915 2326
528f7272 2327 vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
40a3a915
RV		 2328}
2329
2330/*
528f7272 2331 * __vxge_hw_blockpool_blocks_add - Request additional blocks
40a3a915 2332 */
528f7272
JM		 2333static
2334void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
40a3a915 2335{
528f7272 2336 u32 nreq = 0, i;
40a3a915 2337
528f7272
JM		 2338 if ((blockpool->pool_size + blockpool->req_out) <
2339 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
2340 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
2341 blockpool->req_out += nreq;
2342 }
40a3a915 2343
528f7272
JM		 2344 for (i = 0; i < nreq; i++)
2345 vxge_os_dma_malloc_async(
64699336 2346 (blockpool->hldev)->pdev,
528f7272 2347 blockpool->hldev, VXGE_HW_BLOCK_SIZE);
40a3a915
RV		 2348}
2349
2350/*
528f7272
JM		 2351 * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
2352 * Allocates a block of memory of given size, either from block pool
2353 * or by calling vxge_os_dma_malloc()
40a3a915 2354 */
528f7272
JM		 2355static void *__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
2356 struct vxge_hw_mempool_dma *dma_object)
40a3a915 2357{
528f7272
JM		 2358 struct __vxge_hw_blockpool_entry *entry = NULL;
2359 struct __vxge_hw_blockpool *blockpool;
2360 void *memblock = NULL;
40a3a915
RV		 2361 enum vxge_hw_status status = VXGE_HW_OK;
2362
528f7272
JM		 2363 blockpool = &devh->block_pool;
2364
2365 if (size != blockpool->block_size) {
2366
2367 memblock = vxge_os_dma_malloc(devh->pdev, size,
2368 &dma_object->handle,
2369 &dma_object->acc_handle);
2370
2371 if (memblock == NULL) {
2372 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2373 goto exit;
2374 }
2375
2376 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
2377 PCI_DMA_BIDIRECTIONAL);
2378
2379 if (unlikely(pci_dma_mapping_error(devh->pdev,
2380 dma_object->addr))) {
2381 vxge_os_dma_free(devh->pdev, memblock,
2382 &dma_object->acc_handle);
2383 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2384 goto exit;
2385 }
2386
2387 } else {
2388
2389 if (!list_empty(&blockpool->free_block_list))
2390 entry = (struct __vxge_hw_blockpool_entry *)
2391 list_first_entry(&blockpool->free_block_list,
2392 struct __vxge_hw_blockpool_entry,
2393 item);
2394
2395 if (entry != NULL) {
2396 list_del(&entry->item);
2397 dma_object->addr = entry->dma_addr;
2398 dma_object->handle = entry->dma_handle;
2399 dma_object->acc_handle = entry->acc_handle;
2400 memblock = entry->memblock;
2401
2402 list_add(&entry->item,
2403 &blockpool->free_entry_list);
2404 blockpool->pool_size--;
2405 }
2406
2407 if (memblock != NULL)
2408 __vxge_hw_blockpool_blocks_add(blockpool);
2409 }
2410exit:
2411 return memblock;
2412}
2413
2414/*
2415 * __vxge_hw_blockpool_blocks_remove - Free additional blocks
2416 */
2417static void
2418__vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
2419{
2420 struct list_head *p, *n;
2421
2422 list_for_each_safe(p, n, &blockpool->free_block_list) {
2423
2424 if (blockpool->pool_size < blockpool->pool_max)
2425 break;
2426
2427 pci_unmap_single(
64699336 2428 (blockpool->hldev)->pdev,
528f7272
JM		 2429 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
2430 ((struct __vxge_hw_blockpool_entry *)p)->length,
2431 PCI_DMA_BIDIRECTIONAL);
2432
2433 vxge_os_dma_free(
64699336 2434 (blockpool->hldev)->pdev,
528f7272
JM		 2435 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
2436 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
2437
2438 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
2439
2440 list_add(p, &blockpool->free_entry_list);
2441
2442 blockpool->pool_size--;
2443
2444 }
2445}
2446
2447/*
2448 * __vxge_hw_blockpool_free - Frees the memory allcoated with
2449 * __vxge_hw_blockpool_malloc
2450 */
2451static void __vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
2452 void *memblock, u32 size,
2453 struct vxge_hw_mempool_dma *dma_object)
2454{
2455 struct __vxge_hw_blockpool_entry *entry = NULL;
2456 struct __vxge_hw_blockpool *blockpool;
2457 enum vxge_hw_status status = VXGE_HW_OK;
2458
2459 blockpool = &devh->block_pool;
2460
2461 if (size != blockpool->block_size) {
2462 pci_unmap_single(devh->pdev, dma_object->addr, size,
2463 PCI_DMA_BIDIRECTIONAL);
2464 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
2465 } else {
2466
2467 if (!list_empty(&blockpool->free_entry_list))
2468 entry = (struct __vxge_hw_blockpool_entry *)
2469 list_first_entry(&blockpool->free_entry_list,
2470 struct __vxge_hw_blockpool_entry,
2471 item);
2472
2473 if (entry == NULL)
2474 entry = vmalloc(sizeof(
2475 struct __vxge_hw_blockpool_entry));
2476 else
2477 list_del(&entry->item);
2478
2479 if (entry != NULL) {
2480 entry->length = size;
2481 entry->memblock = memblock;
2482 entry->dma_addr = dma_object->addr;
2483 entry->acc_handle = dma_object->acc_handle;
2484 entry->dma_handle = dma_object->handle;
2485 list_add(&entry->item,
2486 &blockpool->free_block_list);
2487 blockpool->pool_size++;
2488 status = VXGE_HW_OK;
2489 } else
2490 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2491
2492 if (status == VXGE_HW_OK)
2493 __vxge_hw_blockpool_blocks_remove(blockpool);
2494 }
2495}
2496
2497/*
2498 * vxge_hw_mempool_destroy
2499 */
2500static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
2501{
2502 u32 i, j;
2503 struct __vxge_hw_device *devh = mempool->devh;
2504
2505 for (i = 0; i < mempool->memblocks_allocated; i++) {
2506 struct vxge_hw_mempool_dma *dma_object;
2507
2508 vxge_assert(mempool->memblocks_arr[i]);
2509 vxge_assert(mempool->memblocks_dma_arr + i);
2510
2511 dma_object = mempool->memblocks_dma_arr + i;
2512
2513 for (j = 0; j < mempool->items_per_memblock; j++) {
2514 u32 index = i * mempool->items_per_memblock + j;
2515
2516 /* to skip last partially filled(if any) memblock */
2517 if (index >= mempool->items_current)
2518 break;
2519 }
2520
2521 vfree(mempool->memblocks_priv_arr[i]);
2522
2523 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2524 mempool->memblock_size, dma_object);
2525 }
2526
2527 vfree(mempool->items_arr);
2528 vfree(mempool->memblocks_dma_arr);
2529 vfree(mempool->memblocks_priv_arr);
2530 vfree(mempool->memblocks_arr);
2531 vfree(mempool);
2532}
2533
2534/*
2535 * __vxge_hw_mempool_grow
2536 * Will resize mempool up to %num_allocate value.
2537 */
2538static enum vxge_hw_status
2539__vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2540 u32 *num_allocated)
2541{
2542 u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2543 u32 n_items = mempool->items_per_memblock;
2544 u32 start_block_idx = mempool->memblocks_allocated;
2545 u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2546 enum vxge_hw_status status = VXGE_HW_OK;
2547
2548 *num_allocated = 0;
40a3a915
RV		 2549
2550 if (end_block_idx > mempool->memblocks_max) {
2551 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2552 goto exit;
2553 }
2554
2555 for (i = start_block_idx; i < end_block_idx; i++) {
2556 u32 j;
2557 u32 is_last = ((end_block_idx - 1) == i);
2558 struct vxge_hw_mempool_dma *dma_object =
2559 mempool->memblocks_dma_arr + i;
2560 void *the_memblock;
2561
2562 /* allocate memblock's private part. Each DMA memblock
2563 * has a space allocated for item's private usage upon
2564 * mempool's user request. Each time mempool grows, it will
2565 * allocate new memblock and its private part at once.
2566 * This helps to minimize memory usage a lot. */
2567 mempool->memblocks_priv_arr[i] =
fad953ce 2568 vzalloc(array_size(mempool->items_priv_size, n_items));
40a3a915
RV		 2569 if (mempool->memblocks_priv_arr[i] == NULL) {
2570 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2571 goto exit;
2572 }
2573
40a3a915
RV		 2574 /* allocate DMA-capable memblock */
2575 mempool->memblocks_arr[i] =
2576 __vxge_hw_blockpool_malloc(mempool->devh,
2577 mempool->memblock_size, dma_object);
2578 if (mempool->memblocks_arr[i] == NULL) {
2579 vfree(mempool->memblocks_priv_arr[i]);
2580 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2581 goto exit;
2582 }
2583
2584 (*num_allocated)++;
2585 mempool->memblocks_allocated++;
2586
2587 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2588
2589 the_memblock = mempool->memblocks_arr[i];
2590
2591 /* fill the items hash array */
2592 for (j = 0; j < n_items; j++) {
2593 u32 index = i * n_items + j;
2594
2595 if (first_time && index >= mempool->items_initial)
2596 break;
2597
2598 mempool->items_arr[index] =
2599 ((char *)the_memblock + j*mempool->item_size);
2600
2601 /* let caller to do more job on each item */
2602 if (mempool->item_func_alloc != NULL)
2603 mempool->item_func_alloc(mempool, i,
2604 dma_object, index, is_last);
2605
2606 mempool->items_current = index + 1;
2607 }
2608
2609 if (first_time && mempool->items_current ==
2610 mempool->items_initial)
2611 break;
2612 }
2613exit:
2614 return status;
2615}
2616
2617/*
2618 * vxge_hw_mempool_create
2619 * This function will create memory pool object. Pool may grow but will
2620 * never shrink. Pool consists of number of dynamically allocated blocks
2621 * with size enough to hold %items_initial number of items. Memory is
2622 * DMA-able but client must map/unmap before interoperating with the device.
2623 */
528f7272
JM		 2624static struct vxge_hw_mempool *
2625__vxge_hw_mempool_create(struct __vxge_hw_device *devh,
2626 u32 memblock_size,
2627 u32 item_size,
2628 u32 items_priv_size,
2629 u32 items_initial,
2630 u32 items_max,
956a2066 2631 const struct vxge_hw_mempool_cbs *mp_callback,
528f7272 2632 void *userdata)
40a3a915
RV		 2633{
2634 enum vxge_hw_status status = VXGE_HW_OK;
2635 u32 memblocks_to_allocate;
2636 struct vxge_hw_mempool *mempool = NULL;
2637 u32 allocated;
2638
2639 if (memblock_size < item_size) {
2640 status = VXGE_HW_FAIL;
2641 goto exit;
2642 }
2643
e80be0b0 2644 mempool = vzalloc(sizeof(struct vxge_hw_mempool));
40a3a915
RV		 2645 if (mempool == NULL) {
2646 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2647 goto exit;
2648 }
40a3a915
RV		 2649
2650 mempool->devh = devh;
2651 mempool->memblock_size = memblock_size;
2652 mempool->items_max = items_max;
2653 mempool->items_initial = items_initial;
2654 mempool->item_size = item_size;
2655 mempool->items_priv_size = items_priv_size;
2656 mempool->item_func_alloc = mp_callback->item_func_alloc;
2657 mempool->userdata = userdata;
2658
2659 mempool->memblocks_allocated = 0;
2660
2661 mempool->items_per_memblock = memblock_size / item_size;
2662
2663 mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2664 mempool->items_per_memblock;
2665
2666 /* allocate array of memblocks */
2667 mempool->memblocks_arr =
fad953ce 2668 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
40a3a915
RV		 2669 if (mempool->memblocks_arr == NULL) {
2670 __vxge_hw_mempool_destroy(mempool);
2671 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2672 mempool = NULL;
2673 goto exit;
2674 }
40a3a915
RV		 2675
2676 /* allocate array of private parts of items per memblocks */
2677 mempool->memblocks_priv_arr =
fad953ce 2678 vzalloc(array_size(sizeof(void *), mempool->memblocks_max));
40a3a915
RV		 2679 if (mempool->memblocks_priv_arr == NULL) {
2680 __vxge_hw_mempool_destroy(mempool);
2681 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2682 mempool = NULL;
2683 goto exit;
2684 }
40a3a915
RV		 2685
2686 /* allocate array of memblocks DMA objects */
e80be0b0 2687 mempool->memblocks_dma_arr =
fad953ce
KC		 2688 vzalloc(array_size(sizeof(struct vxge_hw_mempool_dma),
2689 mempool->memblocks_max));
40a3a915
RV		 2690 if (mempool->memblocks_dma_arr == NULL) {
2691 __vxge_hw_mempool_destroy(mempool);
2692 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2693 mempool = NULL;
2694 goto exit;
2695 }
40a3a915
RV		 2696
2697 /* allocate hash array of items */
fad953ce
KC		 2698 mempool->items_arr = vzalloc(array_size(sizeof(void *),
2699 mempool->items_max));
40a3a915
RV		 2700 if (mempool->items_arr == NULL) {
2701 __vxge_hw_mempool_destroy(mempool);
2702 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2703 mempool = NULL;
2704 goto exit;
2705 }
40a3a915
RV		 2706
2707 /* calculate initial number of memblocks */
2708 memblocks_to_allocate = (mempool->items_initial +
2709 mempool->items_per_memblock - 1) /
2710 mempool->items_per_memblock;
2711
2712 /* pre-allocate the mempool */
2713 status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2714 &allocated);
2715 if (status != VXGE_HW_OK) {
2716 __vxge_hw_mempool_destroy(mempool);
2717 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2718 mempool = NULL;
2719 goto exit;
2720 }
2721
2722exit:
2723 return mempool;
2724}
2725
2726/*
528f7272
JM		 2727 * __vxge_hw_ring_abort - Returns the RxD
2728 * This function terminates the RxDs of ring
40a3a915 2729 */
528f7272 2730static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
40a3a915 2731{
528f7272
JM		 2732 void *rxdh;
2733 struct __vxge_hw_channel *channel;
40a3a915 2734
528f7272 2735 channel = &ring->channel;
40a3a915 2736
528f7272
JM		 2737 for (;;) {
2738 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
40a3a915 2739
528f7272
JM		 2740 if (rxdh == NULL)
2741 break;
40a3a915 2742
528f7272 2743 vxge_hw_channel_dtr_complete(channel);
40a3a915 2744
528f7272
JM		 2745 if (ring->rxd_term)
2746 ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
2747 channel->userdata);
40a3a915 2748
528f7272 2749 vxge_hw_channel_dtr_free(channel, rxdh);
40a3a915
RV		 2750 }
2751
528f7272
JM		 2752 return VXGE_HW_OK;
2753}
40a3a915 2754
528f7272
JM		 2755/*
2756 * __vxge_hw_ring_reset - Resets the ring
2757 * This function resets the ring during vpath reset operation
2758 */
2759static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
2760{
2761 enum vxge_hw_status status = VXGE_HW_OK;
2762 struct __vxge_hw_channel *channel;
40a3a915 2763
528f7272 2764 channel = &ring->channel;
40a3a915 2765
528f7272 2766 __vxge_hw_ring_abort(ring);
40a3a915 2767
528f7272
JM		 2768 status = __vxge_hw_channel_reset(channel);
2769
2770 if (status != VXGE_HW_OK)
2771 goto exit;
2772
2773 if (ring->rxd_init) {
2774 status = vxge_hw_ring_replenish(ring);
2775 if (status != VXGE_HW_OK)
2776 goto exit;
2777 }
2778exit:
2779 return status;
40a3a915
RV		 2780}
2781
2782/*
528f7272
JM		 2783 * __vxge_hw_ring_delete - Removes the ring
2784 * This function freeup the memory pool and removes the ring
40a3a915 2785 */
2c91308f 2786static enum vxge_hw_status
528f7272 2787__vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
40a3a915 2788{
528f7272 2789 struct __vxge_hw_ring *ring = vp->vpath->ringh;
40a3a915 2790
528f7272 2791 __vxge_hw_ring_abort(ring);
40a3a915 2792
528f7272
JM		 2793 if (ring->mempool)
2794 __vxge_hw_mempool_destroy(ring->mempool);
40a3a915 2795
528f7272
JM		 2796 vp->vpath->ringh = NULL;
2797 __vxge_hw_channel_free(&ring->channel);
40a3a915
RV		 2798
2799 return VXGE_HW_OK;
2800}
2801
2802/*
528f7272
JM		 2803 * __vxge_hw_ring_create - Create a Ring
2804 * This function creates Ring and initializes it.
40a3a915 2805 */
2c91308f 2806static enum vxge_hw_status
528f7272
JM		 2807__vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
2808 struct vxge_hw_ring_attr *attr)
40a3a915 2809{
528f7272
JM		 2810 enum vxge_hw_status status = VXGE_HW_OK;
2811 struct __vxge_hw_ring *ring;
2812 u32 ring_length;
2813 struct vxge_hw_ring_config *config;
2814 struct __vxge_hw_device *hldev;
2815 u32 vp_id;
956a2066 2816 static const struct vxge_hw_mempool_cbs ring_mp_callback = {
2817 .item_func_alloc = __vxge_hw_ring_mempool_item_alloc,
2818 };
40a3a915 2819
528f7272
JM		 2820 if ((vp == NULL) || (attr == NULL)) {
2821 status = VXGE_HW_FAIL;
2822 goto exit;
2823 }
40a3a915 2824
528f7272
JM		 2825 hldev = vp->vpath->hldev;
2826 vp_id = vp->vpath->vp_id;
40a3a915 2827
528f7272
JM		 2828 config = &hldev->config.vp_config[vp_id].ring;
2829
2830 ring_length = config->ring_blocks *
2831 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2832
2833 ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
2834 VXGE_HW_CHANNEL_TYPE_RING,
2835 ring_length,
2836 attr->per_rxd_space,
2837 attr->userdata);
2838 if (ring == NULL) {
2839 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2840 goto exit;
40a3a915
RV		 2841 }
2842
528f7272
JM		 2843 vp->vpath->ringh = ring;
2844 ring->vp_id = vp_id;
2845 ring->vp_reg = vp->vpath->vp_reg;
2846 ring->common_reg = hldev->common_reg;
2847 ring->stats = &vp->vpath->sw_stats->ring_stats;
2848 ring->config = config;
2849 ring->callback = attr->callback;
2850 ring->rxd_init = attr->rxd_init;
2851 ring->rxd_term = attr->rxd_term;
2852 ring->buffer_mode = config->buffer_mode;
16fded7d
JM		 2853 ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
2854 ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
528f7272
JM		 2855 ring->rxds_limit = config->rxds_limit;
2856
2857 ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
2858 ring->rxd_priv_size =
2859 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
2860 ring->per_rxd_space = attr->per_rxd_space;
2861
2862 ring->rxd_priv_size =
2863 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2864 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2865
2866 /* how many RxDs can fit into one block. Depends on configured
2867 * buffer_mode. */
2868 ring->rxds_per_block =
2869 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
2870
2871 /* calculate actual RxD block private size */
2872 ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
528f7272
JM		 2873 ring->mempool = __vxge_hw_mempool_create(hldev,
2874 VXGE_HW_BLOCK_SIZE,
2875 VXGE_HW_BLOCK_SIZE,
2876 ring->rxdblock_priv_size,
2877 ring->config->ring_blocks,
2878 ring->config->ring_blocks,
2879 &ring_mp_callback,
2880 ring);
2881 if (ring->mempool == NULL) {
2882 __vxge_hw_ring_delete(vp);
2883 return VXGE_HW_ERR_OUT_OF_MEMORY;
2884 }
2885
2886 status = __vxge_hw_channel_initialize(&ring->channel);
2887 if (status != VXGE_HW_OK) {
2888 __vxge_hw_ring_delete(vp);
2889 goto exit;
2890 }
2891
2892 /* Note:
2893 * Specifying rxd_init callback means two things:
2894 * 1) rxds need to be initialized by driver at channel-open time;
2895 * 2) rxds need to be posted at channel-open time
2896 * (that's what the initial_replenish() below does)
2897 * Currently we don't have a case when the 1) is done without the 2).
2898 */
2899 if (ring->rxd_init) {
2900 status = vxge_hw_ring_replenish(ring);
2901 if (status != VXGE_HW_OK) {
2902 __vxge_hw_ring_delete(vp);
2903 goto exit;
2904 }
2905 }
2906
2907 /* initial replenish will increment the counter in its post() routine,
2908 * we have to reset it */
2909 ring->stats->common_stats.usage_cnt = 0;
2910exit:
2911 return status;
40a3a915
RV		 2912}
2913
2914/*
2915 * vxge_hw_device_config_default_get - Initialize device config with defaults.
2916 * Initialize Titan device config with default values.
2917 */
3a036ce5 2918enum vxge_hw_status
40a3a915
RV		 2919vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2920{
2921 u32 i;
2922
2923 device_config->dma_blockpool_initial =
2924 VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2925 device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2926 device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2927 device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2928 device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2929 device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2930 device_config->rts_mac_en = VXGE_HW_RTS_MAC_DEFAULT;
2931
2932 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 2933 device_config->vp_config[i].vp_id = i;
2934
2935 device_config->vp_config[i].min_bandwidth =
2936 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2937
2938 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2939
2940 device_config->vp_config[i].ring.ring_blocks =
2941 VXGE_HW_DEF_RING_BLOCKS;
2942
2943 device_config->vp_config[i].ring.buffer_mode =
2944 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2945
2946 device_config->vp_config[i].ring.scatter_mode =
2947 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2948
2949 device_config->vp_config[i].ring.rxds_limit =
2950 VXGE_HW_DEF_RING_RXDS_LIMIT;
2951
2952 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2953
2954 device_config->vp_config[i].fifo.fifo_blocks =
2955 VXGE_HW_MIN_FIFO_BLOCKS;
2956
2957 device_config->vp_config[i].fifo.max_frags =
2958 VXGE_HW_MAX_FIFO_FRAGS;
2959
2960 device_config->vp_config[i].fifo.memblock_size =
2961 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2962
2963 device_config->vp_config[i].fifo.alignment_size =
2964 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2965
2966 device_config->vp_config[i].fifo.intr =
2967 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2968
2969 device_config->vp_config[i].fifo.no_snoop_bits =
2970 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2971 device_config->vp_config[i].tti.intr_enable =
2972 VXGE_HW_TIM_INTR_DEFAULT;
2973
2974 device_config->vp_config[i].tti.btimer_val =
2975 VXGE_HW_USE_FLASH_DEFAULT;
2976
2977 device_config->vp_config[i].tti.timer_ac_en =
2978 VXGE_HW_USE_FLASH_DEFAULT;
2979
2980 device_config->vp_config[i].tti.timer_ci_en =
2981 VXGE_HW_USE_FLASH_DEFAULT;
2982
2983 device_config->vp_config[i].tti.timer_ri_en =
2984 VXGE_HW_USE_FLASH_DEFAULT;
2985
2986 device_config->vp_config[i].tti.rtimer_val =
2987 VXGE_HW_USE_FLASH_DEFAULT;
2988
2989 device_config->vp_config[i].tti.util_sel =
2990 VXGE_HW_USE_FLASH_DEFAULT;
2991
2992 device_config->vp_config[i].tti.ltimer_val =
2993 VXGE_HW_USE_FLASH_DEFAULT;
2994
2995 device_config->vp_config[i].tti.urange_a =
2996 VXGE_HW_USE_FLASH_DEFAULT;
2997
2998 device_config->vp_config[i].tti.uec_a =
2999 VXGE_HW_USE_FLASH_DEFAULT;
3000
3001 device_config->vp_config[i].tti.urange_b =
3002 VXGE_HW_USE_FLASH_DEFAULT;
3003
3004 device_config->vp_config[i].tti.uec_b =
3005 VXGE_HW_USE_FLASH_DEFAULT;
3006
3007 device_config->vp_config[i].tti.urange_c =
3008 VXGE_HW_USE_FLASH_DEFAULT;
3009
3010 device_config->vp_config[i].tti.uec_c =
3011 VXGE_HW_USE_FLASH_DEFAULT;
3012
3013 device_config->vp_config[i].tti.uec_d =
3014 VXGE_HW_USE_FLASH_DEFAULT;
3015
3016 device_config->vp_config[i].rti.intr_enable =
3017 VXGE_HW_TIM_INTR_DEFAULT;
3018
3019 device_config->vp_config[i].rti.btimer_val =
3020 VXGE_HW_USE_FLASH_DEFAULT;
3021
3022 device_config->vp_config[i].rti.timer_ac_en =
3023 VXGE_HW_USE_FLASH_DEFAULT;
3024
3025 device_config->vp_config[i].rti.timer_ci_en =
3026 VXGE_HW_USE_FLASH_DEFAULT;
3027
3028 device_config->vp_config[i].rti.timer_ri_en =
3029 VXGE_HW_USE_FLASH_DEFAULT;
3030
3031 device_config->vp_config[i].rti.rtimer_val =
3032 VXGE_HW_USE_FLASH_DEFAULT;
3033
3034 device_config->vp_config[i].rti.util_sel =
3035 VXGE_HW_USE_FLASH_DEFAULT;
3036
3037 device_config->vp_config[i].rti.ltimer_val =
3038 VXGE_HW_USE_FLASH_DEFAULT;
3039
3040 device_config->vp_config[i].rti.urange_a =
3041 VXGE_HW_USE_FLASH_DEFAULT;
3042
3043 device_config->vp_config[i].rti.uec_a =
3044 VXGE_HW_USE_FLASH_DEFAULT;
3045
3046 device_config->vp_config[i].rti.urange_b =
3047 VXGE_HW_USE_FLASH_DEFAULT;
3048
3049 device_config->vp_config[i].rti.uec_b =
3050 VXGE_HW_USE_FLASH_DEFAULT;
3051
3052 device_config->vp_config[i].rti.urange_c =
3053 VXGE_HW_USE_FLASH_DEFAULT;
3054
3055 device_config->vp_config[i].rti.uec_c =
3056 VXGE_HW_USE_FLASH_DEFAULT;
3057
3058 device_config->vp_config[i].rti.uec_d =
3059 VXGE_HW_USE_FLASH_DEFAULT;
3060
3061 device_config->vp_config[i].mtu =
3062 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
3063
3064 device_config->vp_config[i].rpa_strip_vlan_tag =
3065 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
3066 }
3067
3068 return VXGE_HW_OK;
3069}
3070
40a3a915
RV		 3071/*
3072 * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
3073 * Set the swapper bits appropriately for the vpath.
3074 */
42821a5b 3075static enum vxge_hw_status
40a3a915
RV		 3076__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
3077{
3078#ifndef __BIG_ENDIAN
3079 u64 val64;
3080
3081 val64 = readq(&vpath_reg->vpath_general_cfg1);
3082 wmb();
3083 val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
3084 writeq(val64, &vpath_reg->vpath_general_cfg1);
3085 wmb();
3086#endif
3087 return VXGE_HW_OK;
3088}
3089
3090/*
3091 * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
3092 * Set the swapper bits appropriately for the vpath.
3093 */
42821a5b 3094static enum vxge_hw_status
528f7272
JM		 3095__vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
3096 struct vxge_hw_vpath_reg __iomem *vpath_reg)
40a3a915
RV		 3097{
3098 u64 val64;
3099
3100 val64 = readq(&legacy_reg->pifm_wr_swap_en);
3101
3102 if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
3103 val64 = readq(&vpath_reg->kdfcctl_cfg0);
3104 wmb();
3105
3106 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
3107 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
3108 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
3109
3110 writeq(val64, &vpath_reg->kdfcctl_cfg0);
3111 wmb();
3112 }
3113
3114 return VXGE_HW_OK;
3115}
3116
40a3a915
RV		 3117/*
3118 * vxge_hw_mgmt_reg_read - Read Titan register.
3119 */
3120enum vxge_hw_status
3121vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
3122 enum vxge_hw_mgmt_reg_type type,
3123 u32 index, u32 offset, u64 *value)
3124{
3125 enum vxge_hw_status status = VXGE_HW_OK;
3126
3127 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3128 status = VXGE_HW_ERR_INVALID_DEVICE;
3129 goto exit;
3130 }
3131
3132 switch (type) {
3133 case vxge_hw_mgmt_reg_type_legacy:
3134 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3135 status = VXGE_HW_ERR_INVALID_OFFSET;
3136 break;
3137 }
3138 *value = readq((void __iomem *)hldev->legacy_reg + offset);
3139 break;
3140 case vxge_hw_mgmt_reg_type_toc:
3141 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3142 status = VXGE_HW_ERR_INVALID_OFFSET;
3143 break;
3144 }
3145 *value = readq((void __iomem *)hldev->toc_reg + offset);
3146 break;
3147 case vxge_hw_mgmt_reg_type_common:
3148 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3149 status = VXGE_HW_ERR_INVALID_OFFSET;
3150 break;
3151 }
3152 *value = readq((void __iomem *)hldev->common_reg + offset);
3153 break;
3154 case vxge_hw_mgmt_reg_type_mrpcim:
3155 if (!(hldev->access_rights &
3156 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
7c6f9747 3157 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
40a3a915
RV		 3158 break;
3159 }
3160 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3161 status = VXGE_HW_ERR_INVALID_OFFSET;
3162 break;
3163 }
3164 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
3165 break;
3166 case vxge_hw_mgmt_reg_type_srpcim:
3167 if (!(hldev->access_rights &
3168 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
7c6f9747 3169 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
40a3a915
RV		 3170 break;
3171 }
3172 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3173 status = VXGE_HW_ERR_INVALID_INDEX;
3174 break;
3175 }
3176 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3177 status = VXGE_HW_ERR_INVALID_OFFSET;
3178 break;
3179 }
3180 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
3181 offset);
3182 break;
3183 case vxge_hw_mgmt_reg_type_vpmgmt:
3184 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3185 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3186 status = VXGE_HW_ERR_INVALID_INDEX;
3187 break;
3188 }
3189 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3190 status = VXGE_HW_ERR_INVALID_OFFSET;
3191 break;
3192 }
3193 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
3194 offset);
3195 break;
3196 case vxge_hw_mgmt_reg_type_vpath:
3197 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
3198 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3199 status = VXGE_HW_ERR_INVALID_INDEX;
3200 break;
3201 }
3202 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
3203 status = VXGE_HW_ERR_INVALID_INDEX;
3204 break;
3205 }
3206 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3207 status = VXGE_HW_ERR_INVALID_OFFSET;
3208 break;
3209 }
3210 *value = readq((void __iomem *)hldev->vpath_reg[index] +
3211 offset);
3212 break;
3213 default:
3214 status = VXGE_HW_ERR_INVALID_TYPE;
3215 break;
3216 }
3217
3218exit:
3219 return status;
3220}
3221
fa41fd10
SH		 3222/*
3223 * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
3224 */
3225enum vxge_hw_status
3226vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
3227{
3228 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
fa41fd10
SH		 3229 int i = 0, j = 0;
3230
3231 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3232 if (!((vpath_mask) & vxge_mBIT(i)))
3233 continue;
3234 vpmgmt_reg = hldev->vpmgmt_reg[i];
3235 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
3236 if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
3237 & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
3238 return VXGE_HW_FAIL;
3239 }
3240 }
f6d9b514 3241 return VXGE_HW_OK;
fa41fd10 3242}
40a3a915
RV		 3243/*
3244 * vxge_hw_mgmt_reg_Write - Write Titan register.
3245 */
3246enum vxge_hw_status
3247vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
3248 enum vxge_hw_mgmt_reg_type type,
3249 u32 index, u32 offset, u64 value)
3250{
3251 enum vxge_hw_status status = VXGE_HW_OK;
3252
3253 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
3254 status = VXGE_HW_ERR_INVALID_DEVICE;
3255 goto exit;
3256 }
3257
3258 switch (type) {
3259 case vxge_hw_mgmt_reg_type_legacy:
3260 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
3261 status = VXGE_HW_ERR_INVALID_OFFSET;
3262 break;
3263 }
3264 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
3265 break;
3266 case vxge_hw_mgmt_reg_type_toc:
3267 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
3268 status = VXGE_HW_ERR_INVALID_OFFSET;
3269 break;
3270 }
3271 writeq(value, (void __iomem *)hldev->toc_reg + offset);
3272 break;
3273 case vxge_hw_mgmt_reg_type_common:
3274 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
3275 status = VXGE_HW_ERR_INVALID_OFFSET;
3276 break;
3277 }
3278 writeq(value, (void __iomem *)hldev->common_reg + offset);
3279 break;
3280 case vxge_hw_mgmt_reg_type_mrpcim:
3281 if (!(hldev->access_rights &
3282 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
7c6f9747 3283 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
40a3a915
RV		 3284 break;
3285 }
3286 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
3287 status = VXGE_HW_ERR_INVALID_OFFSET;
3288 break;
3289 }
3290 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
3291 break;
3292 case vxge_hw_mgmt_reg_type_srpcim:
3293 if (!(hldev->access_rights &
3294 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
7c6f9747 3295 status = VXGE_HW_ERR_PRIVILEGED_OPERATION;
40a3a915
RV		 3296 break;
3297 }
3298 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
3299 status = VXGE_HW_ERR_INVALID_INDEX;
3300 break;
3301 }
3302 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
3303 status = VXGE_HW_ERR_INVALID_OFFSET;
3304 break;
3305 }
3306 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
3307 offset);
3308
3309 break;
3310 case vxge_hw_mgmt_reg_type_vpmgmt:
3311 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
3312 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3313 status = VXGE_HW_ERR_INVALID_INDEX;
3314 break;
3315 }
3316 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
3317 status = VXGE_HW_ERR_INVALID_OFFSET;
3318 break;
3319 }
3320 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
3321 offset);
3322 break;
3323 case vxge_hw_mgmt_reg_type_vpath:
3324 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
3325 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
3326 status = VXGE_HW_ERR_INVALID_INDEX;
3327 break;
3328 }
3329 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
3330 status = VXGE_HW_ERR_INVALID_OFFSET;
3331 break;
3332 }
3333 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
3334 offset);
3335 break;
3336 default:
3337 status = VXGE_HW_ERR_INVALID_TYPE;
3338 break;
3339 }
3340exit:
3341 return status;
3342}
3343
3344/*
528f7272
JM		 3345 * __vxge_hw_fifo_abort - Returns the TxD
3346 * This function terminates the TxDs of fifo
40a3a915 3347 */
528f7272 3348static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
40a3a915 3349{
528f7272 3350 void *txdlh;
40a3a915 3351
528f7272
JM		 3352 for (;;) {
3353 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
40a3a915 3354
528f7272
JM		 3355 if (txdlh == NULL)
3356 break;
40a3a915 3357
528f7272 3358 vxge_hw_channel_dtr_complete(&fifo->channel);
40a3a915 3359
528f7272
JM		 3360 if (fifo->txdl_term) {
3361 fifo->txdl_term(txdlh,
3362 VXGE_HW_TXDL_STATE_POSTED,
3363 fifo->channel.userdata);
3364 }
40a3a915 3365
528f7272
JM		 3366 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3367 }
40a3a915 3368
528f7272 3369 return VXGE_HW_OK;
40a3a915
RV		 3370}
3371
3372/*
528f7272
JM		 3373 * __vxge_hw_fifo_reset - Resets the fifo
3374 * This function resets the fifo during vpath reset operation
40a3a915 3375 */
528f7272 3376static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
40a3a915
RV		 3377{
3378 enum vxge_hw_status status = VXGE_HW_OK;
528f7272
JM		 3379
3380 __vxge_hw_fifo_abort(fifo);
3381 status = __vxge_hw_channel_reset(&fifo->channel);
3382
3383 return status;
3384}
3385
3386/*
3387 * __vxge_hw_fifo_delete - Removes the FIFO
3388 * This function freeup the memory pool and removes the FIFO
3389 */
3390static enum vxge_hw_status
3391__vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
3392{
3393 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3394
3395 __vxge_hw_fifo_abort(fifo);
3396
3397 if (fifo->mempool)
3398 __vxge_hw_mempool_destroy(fifo->mempool);
3399
3400 vp->vpath->fifoh = NULL;
3401
3402 __vxge_hw_channel_free(&fifo->channel);
3403
3404 return VXGE_HW_OK;
3405}
3406
3407/*
3408 * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
3409 * list callback
3410 * This function is callback passed to __vxge_hw_mempool_create to create memory
3411 * pool for TxD list
3412 */
3413static void
3414__vxge_hw_fifo_mempool_item_alloc(
3415 struct vxge_hw_mempool *mempoolh,
3416 u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
3417 u32 index, u32 is_last)
3418{
3419 u32 memblock_item_idx;
3420 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
3421 struct vxge_hw_fifo_txd *txdp =
3422 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
3423 struct __vxge_hw_fifo *fifo =
3424 (struct __vxge_hw_fifo *)mempoolh->userdata;
3425 void *memblock = mempoolh->memblocks_arr[memblock_index];
3426
3427 vxge_assert(txdp);
3428
3429 txdp->host_control = (u64) (size_t)
3430 __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
3431 &memblock_item_idx);
3432
3433 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3434
3435 vxge_assert(txdl_priv);
3436
3437 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3438
3439 /* pre-format HW's TxDL's private */
3440 txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
3441 txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
3442 txdl_priv->dma_handle = dma_object->handle;
3443 txdl_priv->memblock = memblock;
3444 txdl_priv->first_txdp = txdp;
3445 txdl_priv->next_txdl_priv = NULL;
3446 txdl_priv->alloc_frags = 0;
3447}
3448
3449/*
3450 * __vxge_hw_fifo_create - Create a FIFO
3451 * This function creates FIFO and initializes it.
3452 */
3453static enum vxge_hw_status
3454__vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
3455 struct vxge_hw_fifo_attr *attr)
3456{
3457 enum vxge_hw_status status = VXGE_HW_OK;
3458 struct __vxge_hw_fifo *fifo;
40a3a915
RV		 3459 struct vxge_hw_fifo_config *config;
3460 u32 txdl_size, txdl_per_memblock;
3461 struct vxge_hw_mempool_cbs fifo_mp_callback;
3462 struct __vxge_hw_virtualpath *vpath;
3463
3464 if ((vp == NULL) || (attr == NULL)) {
3465 status = VXGE_HW_ERR_INVALID_HANDLE;
3466 goto exit;
3467 }
3468 vpath = vp->vpath;
3469 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3470
3471 txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
3472
3473 txdl_per_memblock = config->memblock_size / txdl_size;
3474
3475 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3476 VXGE_HW_CHANNEL_TYPE_FIFO,
3477 config->fifo_blocks * txdl_per_memblock,
3478 attr->per_txdl_space, attr->userdata);
3479
3480 if (fifo == NULL) {
3481 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3482 goto exit;
3483 }
3484
3485 vpath->fifoh = fifo;
3486 fifo->nofl_db = vpath->nofl_db;
3487
3488 fifo->vp_id = vpath->vp_id;
3489 fifo->vp_reg = vpath->vp_reg;
3490 fifo->stats = &vpath->sw_stats->fifo_stats;
3491
3492 fifo->config = config;
3493
3494 /* apply "interrupts per txdl" attribute */
3495 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
16fded7d
JM		 3496 fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3497 fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
40a3a915
RV		 3498
3499 if (fifo->config->intr)
3500 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3501
3502 fifo->no_snoop_bits = config->no_snoop_bits;
3503
3504 /*
3505 * FIFO memory management strategy:
3506 *
3507 * TxDL split into three independent parts:
3508 * - set of TxD's
3509 * - TxD HW private part
3510 * - driver private part
3511 *
3512 * Adaptative memory allocation used. i.e. Memory allocated on
3513 * demand with the size which will fit into one memory block.
3514 * One memory block may contain more than one TxDL.
3515 *
3516 * During "reserve" operations more memory can be allocated on demand
3517 * for example due to FIFO full condition.
3518 *
3519 * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
3520 * routine which will essentially stop the channel and free resources.
3521 */
3522
3523 /* TxDL common private size == TxDL private + driver private */
3524 fifo->priv_size =
3525 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
3526 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
3527 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
3528
3529 fifo->per_txdl_space = attr->per_txdl_space;
3530
3531 /* recompute txdl size to be cacheline aligned */
3532 fifo->txdl_size = txdl_size;
3533 fifo->txdl_per_memblock = txdl_per_memblock;
3534
3535 fifo->txdl_term = attr->txdl_term;
3536 fifo->callback = attr->callback;
3537
3538 if (fifo->txdl_per_memblock == 0) {
3539 __vxge_hw_fifo_delete(vp);
3540 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
3541 goto exit;
3542 }
3543
3544 fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
3545
3546 fifo->mempool =
3547 __vxge_hw_mempool_create(vpath->hldev,
3548 fifo->config->memblock_size,
3549 fifo->txdl_size,
3550 fifo->priv_size,
3551 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3552 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3553 &fifo_mp_callback,
3554 fifo);
3555
3556 if (fifo->mempool == NULL) {
3557 __vxge_hw_fifo_delete(vp);
3558 status = VXGE_HW_ERR_OUT_OF_MEMORY;
3559 goto exit;
3560 }
3561
3562 status = __vxge_hw_channel_initialize(&fifo->channel);
3563 if (status != VXGE_HW_OK) {
3564 __vxge_hw_fifo_delete(vp);
3565 goto exit;
3566 }
3567
3568 vxge_assert(fifo->channel.reserve_ptr);
3569exit:
3570 return status;
3571}
3572
40a3a915
RV		 3573/*
3574 * __vxge_hw_vpath_pci_read - Read the content of given address
3575 * in pci config space.
3576 * Read from the vpath pci config space.
3577 */
42821a5b 3578static enum vxge_hw_status
40a3a915
RV		 3579__vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3580 u32 phy_func_0, u32 offset, u32 *val)
3581{
3582 u64 val64;
3583 enum vxge_hw_status status = VXGE_HW_OK;
3584 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3585
3586 val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3587
3588 if (phy_func_0)
3589 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3590
3591 writeq(val64, &vp_reg->pci_config_access_cfg1);
3592 wmb();
3593 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3594 &vp_reg->pci_config_access_cfg2);
3595 wmb();
3596
3597 status = __vxge_hw_device_register_poll(
3598 &vp_reg->pci_config_access_cfg2,
3599 VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3600
3601 if (status != VXGE_HW_OK)
3602 goto exit;
3603
3604 val64 = readq(&vp_reg->pci_config_access_status);
3605
3606 if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3607 status = VXGE_HW_FAIL;
3608 *val = 0;
3609 } else
3610 *val = (u32)vxge_bVALn(val64, 32, 32);
3611exit:
3612 return status;
3613}
3614
40a3a915
RV		 3615/**
3616 * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3617 * @hldev: HW device.
3618 * @on_off: TRUE if flickering to be on, FALSE to be off
3619 *
3620 * Flicker the link LED.
3621 */
3622enum vxge_hw_status
8424e00d 3623vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
40a3a915 3624{
8424e00d
JM		 3625 struct __vxge_hw_virtualpath *vpath;
3626 u64 data0, data1 = 0, steer_ctrl = 0;
3627 enum vxge_hw_status status;
40a3a915
RV		 3628
3629 if (hldev == NULL) {
3630 status = VXGE_HW_ERR_INVALID_DEVICE;
3631 goto exit;
3632 }
3633
8424e00d 3634 vpath = &hldev->virtual_paths[hldev->first_vp_id];
40a3a915 3635
8424e00d
JM		 3636 data0 = on_off;
3637 status = vxge_hw_vpath_fw_api(vpath,
3638 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3639 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3640 0, &data0, &data1, &steer_ctrl);
40a3a915
RV		 3641exit:
3642 return status;
3643}
3644
3645/*
3646 * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3647 */
3648enum vxge_hw_status
8424e00d
JM		 3649__vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3650 u32 action, u32 rts_table, u32 offset,
3651 u64 *data0, u64 *data1)
40a3a915 3652{
8424e00d
JM		 3653 enum vxge_hw_status status;
3654 u64 steer_ctrl = 0;
40a3a915
RV		 3655
3656 if (vp == NULL) {
3657 status = VXGE_HW_ERR_INVALID_HANDLE;
3658 goto exit;
3659 }
3660
40a3a915 3661 if ((rts_table ==
8424e00d 3662 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
40a3a915 3663 (rts_table ==
8424e00d 3664 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
40a3a915 3665 (rts_table ==
8424e00d 3666 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
40a3a915 3667 (rts_table ==
8424e00d
JM		 3668 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3669 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
40a3a915
RV		 3670 }
3671
8424e00d
JM		 3672 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3673 data0, data1, &steer_ctrl);
40a3a915
RV		 3674 if (status != VXGE_HW_OK)
3675 goto exit;
3676
48bc9a2c 3677 if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) &&
8424e00d
JM		 3678 (rts_table !=
3679 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3680 *data1 = 0;
40a3a915
RV		 3681exit:
3682 return status;
3683}
3684
3685/*
3686 * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3687 */
3688enum vxge_hw_status
8424e00d
JM		 3689__vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3690 u32 rts_table, u32 offset, u64 steer_data0,
3691 u64 steer_data1)
40a3a915 3692{
8424e00d
JM		 3693 u64 data0, data1 = 0, steer_ctrl = 0;
3694 enum vxge_hw_status status;
40a3a915
RV		 3695
3696 if (vp == NULL) {
3697 status = VXGE_HW_ERR_INVALID_HANDLE;
3698 goto exit;
3699 }
3700
8424e00d 3701 data0 = steer_data0;
40a3a915
RV		 3702
3703 if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3704 (rts_table ==
8424e00d
JM		 3705 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3706 data1 = steer_data1;
40a3a915 3707
8424e00d
JM		 3708 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3709 &data0, &data1, &steer_ctrl);
40a3a915
RV		 3710exit:
3711 return status;
3712}
3713
3714/*
3715 * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3716 */
3717enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3718 struct __vxge_hw_vpath_handle *vp,
3719 enum vxge_hw_rth_algoritms algorithm,
3720 struct vxge_hw_rth_hash_types *hash_type,
3721 u16 bucket_size)
3722{
3723 u64 data0, data1;
3724 enum vxge_hw_status status = VXGE_HW_OK;
3725
3726 if (vp == NULL) {
3727 status = VXGE_HW_ERR_INVALID_HANDLE;
3728 goto exit;
3729 }
3730
3731 status = __vxge_hw_vpath_rts_table_get(vp,
3732 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3733 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3734 0, &data0, &data1);
47f01db4
JM		 3735 if (status != VXGE_HW_OK)
3736 goto exit;
40a3a915
RV		 3737
3738 data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3739 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3740
3741 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3742 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3743 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3744
3745 if (hash_type->hash_type_tcpipv4_en)
3746 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3747
3748 if (hash_type->hash_type_ipv4_en)
3749 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3750
3751 if (hash_type->hash_type_tcpipv6_en)
3752 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3753
3754 if (hash_type->hash_type_ipv6_en)
3755 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3756
3757 if (hash_type->hash_type_tcpipv6ex_en)
3758 data0 |=
3759 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3760
3761 if (hash_type->hash_type_ipv6ex_en)
3762 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3763
3764 if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3765 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3766 else
3767 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3768
3769 status = __vxge_hw_vpath_rts_table_set(vp,
3770 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3771 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3772 0, data0, 0);
3773exit:
3774 return status;
3775}
3776
3777static void
3778vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3779 u16 flag, u8 *itable)
3780{
3781 switch (flag) {
3782 case 1:
3783 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3784 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3785 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3786 itable[j]);
3787 case 2:
3788 *data0 |=
3789 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3790 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3791 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3792 itable[j]);
3793 case 3:
3794 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3795 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3796 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3797 itable[j]);
3798 case 4:
3799 *data1 |=
3800 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3801 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3802 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3803 itable[j]);
3804 default:
3805 return;
3806 }
3807}
3808/*
3809 * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3810 */
3811enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3812 struct __vxge_hw_vpath_handle **vpath_handles,
3813 u32 vpath_count,
3814 u8 *mtable,
3815 u8 *itable,
3816 u32 itable_size)
3817{
3818 u32 i, j, action, rts_table;
3819 u64 data0;
3820 u64 data1;
3821 u32 max_entries;
3822 enum vxge_hw_status status = VXGE_HW_OK;
3823 struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3824
3825 if (vp == NULL) {
3826 status = VXGE_HW_ERR_INVALID_HANDLE;
3827 goto exit;
3828 }
3829
3830 max_entries = (((u32)1) << itable_size);
3831
3832 if (vp->vpath->hldev->config.rth_it_type
3833 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3834 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3835 rts_table =
3836 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3837
3838 for (j = 0; j < max_entries; j++) {
3839
3840 data1 = 0;
3841
3842 data0 =
3843 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3844 itable[j]);
3845
3846 status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3847 action, rts_table, j, data0, data1);
3848
3849 if (status != VXGE_HW_OK)
3850 goto exit;
3851 }
3852
3853 for (j = 0; j < max_entries; j++) {
3854
3855 data1 = 0;
3856
3857 data0 =
3858 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3859 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3860 itable[j]);
3861
3862 status = __vxge_hw_vpath_rts_table_set(
3863 vpath_handles[mtable[itable[j]]], action,
3864 rts_table, j, data0, data1);
3865
3866 if (status != VXGE_HW_OK)
3867 goto exit;
3868 }
3869 } else {
3870 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3871 rts_table =
3872 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3873 for (i = 0; i < vpath_count; i++) {
3874
3875 for (j = 0; j < max_entries;) {
3876
3877 data0 = 0;
3878 data1 = 0;
3879
3880 while (j < max_entries) {
3881 if (mtable[itable[j]] != i) {
3882 j++;
3883 continue;
3884 }
3885 vxge_hw_rts_rth_data0_data1_get(j,
3886 &data0, &data1, 1, itable);
3887 j++;
3888 break;
3889 }
3890
3891 while (j < max_entries) {
3892 if (mtable[itable[j]] != i) {
3893 j++;
3894 continue;
3895 }
3896 vxge_hw_rts_rth_data0_data1_get(j,
3897 &data0, &data1, 2, itable);
3898 j++;
3899 break;
3900 }
3901
3902 while (j < max_entries) {
3903 if (mtable[itable[j]] != i) {
3904 j++;
3905 continue;
3906 }
3907 vxge_hw_rts_rth_data0_data1_get(j,
3908 &data0, &data1, 3, itable);
3909 j++;
3910 break;
3911 }
3912
3913 while (j < max_entries) {
3914 if (mtable[itable[j]] != i) {
3915 j++;
3916 continue;
3917 }
3918 vxge_hw_rts_rth_data0_data1_get(j,
3919 &data0, &data1, 4, itable);
3920 j++;
3921 break;
3922 }
3923
3924 if (data0 != 0) {
3925 status = __vxge_hw_vpath_rts_table_set(
3926 vpath_handles[i],
3927 action, rts_table,
3928 0, data0, data1);
3929
3930 if (status != VXGE_HW_OK)
3931 goto exit;
3932 }
3933 }
3934 }
3935 }
3936exit:
3937 return status;
3938}
3939
3940/**
3941 * vxge_hw_vpath_check_leak - Check for memory leak
3942 * @ringh: Handle to the ring object used for receive
3943 *
3944 * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3945 * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3946 * Returns: VXGE_HW_FAIL, if leak has occurred.
3947 *
3948 */
3949enum vxge_hw_status
3950vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3951{
3952 enum vxge_hw_status status = VXGE_HW_OK;
3953 u64 rxd_new_count, rxd_spat;
3954
3955 if (ring == NULL)
3956 return status;
3957
3958 rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3959 rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3960 rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3961
3962 if (rxd_new_count >= rxd_spat)
3963 status = VXGE_HW_FAIL;
3964
3965 return status;
3966}
3967
3968/*
3969 * __vxge_hw_vpath_mgmt_read
3970 * This routine reads the vpath_mgmt registers
3971 */
3972static enum vxge_hw_status
3973__vxge_hw_vpath_mgmt_read(
3974 struct __vxge_hw_device *hldev,
3975 struct __vxge_hw_virtualpath *vpath)
3976{
3977 u32 i, mtu = 0, max_pyld = 0;
3978 u64 val64;
40a3a915
RV		 3979
3980 for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3981
3982 val64 = readq(&vpath->vpmgmt_reg->
3983 rxmac_cfg0_port_vpmgmt_clone[i]);
3984 max_pyld =
3985 (u32)
3986 VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3987 (val64);
3988 if (mtu < max_pyld)
3989 mtu = max_pyld;
3990 }
3991
3992 vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3993
3994 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3995
3996 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3997 if (val64 & vxge_mBIT(i))
3998 vpath->vsport_number = i;
3999 }
4000
4001 val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
4002
4003 if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
4004 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
4005 else
4006 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
4007
f6d9b514 4008 return VXGE_HW_OK;
40a3a915
RV		 4009}
4010
4011/*
4012 * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
4013 * This routine checks the vpath_rst_in_prog register to see if
4014 * adapter completed the reset process for the vpath
4015 */
42821a5b 4016static enum vxge_hw_status
40a3a915
RV		 4017__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
4018{
4019 enum vxge_hw_status status;
4020
4021 status = __vxge_hw_device_register_poll(
4022 &vpath->hldev->common_reg->vpath_rst_in_prog,
4023 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
4024 1 << (16 - vpath->vp_id)),
4025 vpath->hldev->config.device_poll_millis);
4026
4027 return status;
4028}
4029
4030/*
4031 * __vxge_hw_vpath_reset
4032 * This routine resets the vpath on the device
4033 */
42821a5b 4034static enum vxge_hw_status
40a3a915
RV		 4035__vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4036{
4037 u64 val64;
40a3a915
RV		 4038
4039 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
4040
4041 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4042 &hldev->common_reg->cmn_rsthdlr_cfg0);
4043
f6d9b514 4044 return VXGE_HW_OK;
40a3a915
RV		 4045}
4046
4047/*
4048 * __vxge_hw_vpath_sw_reset
4049 * This routine resets the vpath structures
4050 */
42821a5b 4051static enum vxge_hw_status
40a3a915
RV		 4052__vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
4053{
4054 enum vxge_hw_status status = VXGE_HW_OK;
4055 struct __vxge_hw_virtualpath *vpath;
4056
64699336 4057 vpath = &hldev->virtual_paths[vp_id];
40a3a915
RV		 4058
4059 if (vpath->ringh) {
4060 status = __vxge_hw_ring_reset(vpath->ringh);
4061 if (status != VXGE_HW_OK)
4062 goto exit;
4063 }
4064
4065 if (vpath->fifoh)
4066 status = __vxge_hw_fifo_reset(vpath->fifoh);
4067exit:
4068 return status;
4069}
4070
4071/*
4072 * __vxge_hw_vpath_prc_configure
4073 * This routine configures the prc registers of virtual path using the config
4074 * passed
4075 */
42821a5b 4076static void
40a3a915
RV		 4077__vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4078{
4079 u64 val64;
4080 struct __vxge_hw_virtualpath *vpath;
4081 struct vxge_hw_vp_config *vp_config;
4082 struct vxge_hw_vpath_reg __iomem *vp_reg;
4083
4084 vpath = &hldev->virtual_paths[vp_id];
4085 vp_reg = vpath->vp_reg;
4086 vp_config = vpath->vp_config;
4087
4088 if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
4089 return;
4090
4091 val64 = readq(&vp_reg->prc_cfg1);
4092 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
4093 writeq(val64, &vp_reg->prc_cfg1);
4094
4095 val64 = readq(&vpath->vp_reg->prc_cfg6);
4096 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
4097 writeq(val64, &vpath->vp_reg->prc_cfg6);
4098
4099 val64 = readq(&vp_reg->prc_cfg7);
4100
4101 if (vpath->vp_config->ring.scatter_mode !=
4102 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
4103
4104 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
4105
4106 switch (vpath->vp_config->ring.scatter_mode) {
4107 case VXGE_HW_RING_SCATTER_MODE_A:
4108 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4109 VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
4110 break;
4111 case VXGE_HW_RING_SCATTER_MODE_B:
4112 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4113 VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
4114 break;
4115 case VXGE_HW_RING_SCATTER_MODE_C:
4116 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
4117 VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
4118 break;
4119 }
4120 }
4121
4122 writeq(val64, &vp_reg->prc_cfg7);
4123
4124 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
4125 __vxge_hw_ring_first_block_address_get(
4126 vpath->ringh) >> 3), &vp_reg->prc_cfg5);
4127
4128 val64 = readq(&vp_reg->prc_cfg4);
4129 val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
4130 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
4131
4132 val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
4133 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
4134
4135 if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
4136 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
4137 else
4138 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
4139
4140 writeq(val64, &vp_reg->prc_cfg4);
40a3a915
RV		 4141}
4142
4143/*
4144 * __vxge_hw_vpath_kdfc_configure
4145 * This routine configures the kdfc registers of virtual path using the
4146 * config passed
4147 */
42821a5b 4148static enum vxge_hw_status
40a3a915
RV		 4149__vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4150{
4151 u64 val64;
4152 u64 vpath_stride;
4153 enum vxge_hw_status status = VXGE_HW_OK;
4154 struct __vxge_hw_virtualpath *vpath;
4155 struct vxge_hw_vpath_reg __iomem *vp_reg;
4156
4157 vpath = &hldev->virtual_paths[vp_id];
4158 vp_reg = vpath->vp_reg;
4159 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
4160
4161 if (status != VXGE_HW_OK)
4162 goto exit;
4163
4164 val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
4165
4166 vpath->max_kdfc_db =
4167 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
4168 val64+1)/2;
4169
4170 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4171
4172 vpath->max_nofl_db = vpath->max_kdfc_db;
4173
4174 if (vpath->max_nofl_db <
4175 ((vpath->vp_config->fifo.memblock_size /
4176 (vpath->vp_config->fifo.max_frags *
4177 sizeof(struct vxge_hw_fifo_txd))) *
4178 vpath->vp_config->fifo.fifo_blocks)) {
4179
4180 return VXGE_HW_BADCFG_FIFO_BLOCKS;
4181 }
4182 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
4183 (vpath->max_nofl_db*2)-1);
4184 }
4185
4186 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
4187
4188 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
4189 &vp_reg->kdfc_fifo_trpl_ctrl);
4190
4191 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
4192
4193 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
4194 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
4195
4196 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
4197 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
4198#ifndef __BIG_ENDIAN
4199 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
4200#endif
4201 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
4202
4203 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
4204 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
4205 wmb();
4206 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
4207
4208 vpath->nofl_db =
4209 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
4210 (hldev->kdfc + (vp_id *
4211 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
4212 vpath_stride)));
4213exit:
4214 return status;
4215}
4216
4217/*
4218 * __vxge_hw_vpath_mac_configure
4219 * This routine configures the mac of virtual path using the config passed
4220 */
42821a5b 4221static enum vxge_hw_status
40a3a915
RV		 4222__vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4223{
4224 u64 val64;
40a3a915
RV		 4225 struct __vxge_hw_virtualpath *vpath;
4226 struct vxge_hw_vp_config *vp_config;
4227 struct vxge_hw_vpath_reg __iomem *vp_reg;
4228
4229 vpath = &hldev->virtual_paths[vp_id];
4230 vp_reg = vpath->vp_reg;
4231 vp_config = vpath->vp_config;
4232
4233 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
4234 vpath->vsport_number), &vp_reg->xmac_vsport_choice);
4235
4236 if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4237
4238 val64 = readq(&vp_reg->xmac_rpa_vcfg);
4239
4240 if (vp_config->rpa_strip_vlan_tag !=
4241 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
4242 if (vp_config->rpa_strip_vlan_tag)
4243 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4244 else
4245 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
4246 }
4247
4248 writeq(val64, &vp_reg->xmac_rpa_vcfg);
4249 val64 = readq(&vp_reg->rxmac_vcfg0);
4250
4251 if (vp_config->mtu !=
4252 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
4253 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4254 if ((vp_config->mtu +
4255 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
4256 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4257 vp_config->mtu +
4258 VXGE_HW_MAC_HEADER_MAX_SIZE);
4259 else
4260 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
4261 vpath->max_mtu);
4262 }
4263
4264 writeq(val64, &vp_reg->rxmac_vcfg0);
4265
4266 val64 = readq(&vp_reg->rxmac_vcfg1);
4267
4268 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
4269 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
4270
4271 if (hldev->config.rth_it_type ==
4272 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
4273 val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
4274 0x2) |
4275 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
4276 }
4277
4278 writeq(val64, &vp_reg->rxmac_vcfg1);
4279 }
f6d9b514 4280 return VXGE_HW_OK;
40a3a915
RV		 4281}
4282
4283/*
4284 * __vxge_hw_vpath_tim_configure
4285 * This routine configures the tim registers of virtual path using the config
4286 * passed
4287 */
42821a5b 4288static enum vxge_hw_status
40a3a915
RV		 4289__vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
4290{
4291 u64 val64;
40a3a915
RV		 4292 struct __vxge_hw_virtualpath *vpath;
4293 struct vxge_hw_vpath_reg __iomem *vp_reg;
4294 struct vxge_hw_vp_config *config;
4295
4296 vpath = &hldev->virtual_paths[vp_id];
4297 vp_reg = vpath->vp_reg;
4298 config = vpath->vp_config;
4299
528f7272
JM		 4300 writeq(0, &vp_reg->tim_dest_addr);
4301 writeq(0, &vp_reg->tim_vpath_map);
4302 writeq(0, &vp_reg->tim_bitmap);
4303 writeq(0, &vp_reg->tim_remap);
40a3a915
RV		 4304
4305 if (config->ring.enable == VXGE_HW_RING_ENABLE)
4306 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
4307 (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4308 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
4309
4310 val64 = readq(&vp_reg->tim_pci_cfg);
4311 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
4312 writeq(val64, &vp_reg->tim_pci_cfg);
4313
4314 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4315
4316 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4317
4318 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4319 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4320 0x3ffffff);
4321 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4322 config->tti.btimer_val);
4323 }
4324
4325 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
4326
4327 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4328 if (config->tti.timer_ac_en)
4329 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4330 else
4331 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4332 }
4333
4334 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4335 if (config->tti.timer_ci_en)
4336 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4337 else
4338 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4339 }
4340
4341 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4342 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4343 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4344 config->tti.urange_a);
4345 }
4346
4347 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4348 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4349 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4350 config->tti.urange_b);
4351 }
4352
4353 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4354 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4355 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4356 config->tti.urange_c);
4357 }
4358
4359 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
16fded7d
JM		 4360 vpath->tim_tti_cfg1_saved = val64;
4361
40a3a915
RV		 4362 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4363
4364 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4365 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4366 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4367 config->tti.uec_a);
4368 }
4369
4370 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4371 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4372 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4373 config->tti.uec_b);
4374 }
4375
4376 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4377 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4378 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4379 config->tti.uec_c);
4380 }
4381
4382 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4383 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4384 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4385 config->tti.uec_d);
4386 }
4387
4388 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
4389 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
4390
4391 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4392 if (config->tti.timer_ri_en)
4393 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4394 else
4395 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4396 }
4397
4398 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4399 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4400 0x3ffffff);
4401 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4402 config->tti.rtimer_val);
4403 }
4404
4405 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4406 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
b55e7b15 4407 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
40a3a915
RV		 4408 }
4409
4410 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4411 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4412 0x3ffffff);
4413 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4414 config->tti.ltimer_val);
4415 }
4416
528f7272 4417 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
16fded7d 4418 vpath->tim_tti_cfg3_saved = val64;
528f7272 4419 }
40a3a915 4420
528f7272 4421 if (config->ring.enable == VXGE_HW_RING_ENABLE) {
40a3a915 4422
528f7272 4423 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
40a3a915 4424
528f7272
JM		 4425 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4426 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4427 0x3ffffff);
4428 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
4429 config->rti.btimer_val);
4430 }
40a3a915 4431
528f7272 4432 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
40a3a915 4433
528f7272
JM		 4434 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
4435 if (config->rti.timer_ac_en)
4436 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4437 else
4438 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
4439 }
40a3a915 4440
528f7272
JM		 4441 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
4442 if (config->rti.timer_ci_en)
4443 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4444 else
4445 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4446 }
40a3a915 4447
528f7272
JM		 4448 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
4449 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
4450 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
4451 config->rti.urange_a);
4452 }
40a3a915 4453
528f7272
JM		 4454 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
4455 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
4456 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
4457 config->rti.urange_b);
4458 }
40a3a915 4459
528f7272
JM		 4460 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
4461 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
4462 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
4463 config->rti.urange_c);
4464 }
40a3a915 4465
528f7272 4466 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
16fded7d
JM		 4467 vpath->tim_rti_cfg1_saved = val64;
4468
528f7272 4469 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
40a3a915 4470
528f7272
JM		 4471 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
4472 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
4473 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
4474 config->rti.uec_a);
4475 }
40a3a915 4476
528f7272
JM		 4477 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
4478 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
4479 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
4480 config->rti.uec_b);
4481 }
40a3a915 4482
528f7272
JM		 4483 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
4484 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
4485 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
4486 config->rti.uec_c);
4487 }
40a3a915 4488
528f7272
JM		 4489 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
4490 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
4491 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
4492 config->rti.uec_d);
4493 }
40a3a915 4494
528f7272
JM		 4495 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
4496 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
40a3a915 4497
528f7272
JM		 4498 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4499 if (config->rti.timer_ri_en)
4500 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4501 else
4502 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4503 }
40a3a915 4504
528f7272
JM		 4505 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4506 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4507 0x3ffffff);
4508 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4509 config->rti.rtimer_val);
4510 }
40a3a915 4511
528f7272
JM		 4512 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4513 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
b55e7b15 4514 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
528f7272 4515 }
40a3a915 4516
528f7272
JM		 4517 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4518 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4519 0x3ffffff);
4520 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4521 config->rti.ltimer_val);
4522 }
40a3a915 4523
528f7272 4524 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
16fded7d 4525 vpath->tim_rti_cfg3_saved = val64;
40a3a915
RV		 4526 }
4527
528f7272
JM		 4528 val64 = 0;
4529 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4530 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4531 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4532 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4533 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4534 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4535
b55e7b15
JM		 4536 val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
4537 val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
4538 val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
4539 writeq(val64, &vp_reg->tim_wrkld_clc);
4540
f6d9b514 4541 return VXGE_HW_OK;
40a3a915
RV		 4542}
4543
40a3a915 4544/*
528f7272
JM		 4545 * __vxge_hw_vpath_initialize
4546 * This routine is the final phase of init which initializes the
4547 * registers of the vpath using the configuration passed.
40a3a915 4548 */
42821a5b 4549static enum vxge_hw_status
528f7272 4550__vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
40a3a915
RV		 4551{
4552 u64 val64;
528f7272 4553 u32 val32;
40a3a915 4554 enum vxge_hw_status status = VXGE_HW_OK;
528f7272 4555 struct __vxge_hw_virtualpath *vpath;
40a3a915
RV		 4556 struct vxge_hw_vpath_reg __iomem *vp_reg;
4557
528f7272
JM		 4558 vpath = &hldev->virtual_paths[vp_id];
4559
4560 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4561 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
40a3a915
RV		 4562 goto exit;
4563 }
4564 vp_reg = vpath->vp_reg;
4565
528f7272
JM		 4566 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4567 if (status != VXGE_HW_OK)
4568 goto exit;
40a3a915 4569
528f7272
JM		 4570 status = __vxge_hw_vpath_mac_configure(hldev, vp_id);
4571 if (status != VXGE_HW_OK)
4572 goto exit;
40a3a915 4573
528f7272
JM		 4574 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4575 if (status != VXGE_HW_OK)
4576 goto exit;
40a3a915 4577
528f7272
JM		 4578 status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4579 if (status != VXGE_HW_OK)
4580 goto exit;
40a3a915 4581
528f7272 4582 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
40a3a915 4583
528f7272
JM		 4584 /* Get MRRS value from device control */
4585 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4586 if (status == VXGE_HW_OK) {
4587 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4588 val64 &=
4589 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4590 val64 |=
4591 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
40a3a915 4592
528f7272
JM		 4593 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4594 }
40a3a915 4595
528f7272
JM		 4596 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4597 val64 |=
4598 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4599 VXGE_HW_MAX_PAYLOAD_SIZE_512);
40a3a915 4600
528f7272
JM		 4601 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4602 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
40a3a915 4603
528f7272
JM		 4604exit:
4605 return status;
4606}
40a3a915 4607
528f7272
JM		 4608/*
4609 * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4610 * This routine closes all channels it opened and freeup memory
4611 */
4612static void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4613{
4614 struct __vxge_hw_virtualpath *vpath;
40a3a915 4615
528f7272 4616 vpath = &hldev->virtual_paths[vp_id];
40a3a915 4617
528f7272 4618 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
40a3a915
RV		 4619 goto exit;
4620
528f7272
JM		 4621 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4622 vpath->hldev->tim_int_mask1, vpath->vp_id);
4623 hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
40a3a915 4624
9f9b1645
JM		 4625 /* If the whole struct __vxge_hw_virtualpath is zeroed, nothing will
4626 * work after the interface is brought down.
4627 */
4628 spin_lock(&vpath->lock);
4629 vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4630 spin_unlock(&vpath->lock);
4631
4632 vpath->vpmgmt_reg = NULL;
4633 vpath->nofl_db = NULL;
4634 vpath->max_mtu = 0;
4635 vpath->vsport_number = 0;
4636 vpath->max_kdfc_db = 0;
4637 vpath->max_nofl_db = 0;
4638 vpath->ringh = NULL;
4639 vpath->fifoh = NULL;
4640 memset(&vpath->vpath_handles, 0, sizeof(struct list_head));
2ca292d9 4641 vpath->stats_block = NULL;
9f9b1645
JM		 4642 vpath->hw_stats = NULL;
4643 vpath->hw_stats_sav = NULL;
4644 vpath->sw_stats = NULL;
4645
528f7272
JM		 4646exit:
4647 return;
4648}
40a3a915 4649
528f7272
JM		 4650/*
4651 * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4652 * This routine is the initial phase of init which resets the vpath and
4653 * initializes the software support structures.
4654 */
4655static enum vxge_hw_status
4656__vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4657 struct vxge_hw_vp_config *config)
4658{
4659 struct __vxge_hw_virtualpath *vpath;
4660 enum vxge_hw_status status = VXGE_HW_OK;
40a3a915 4661
528f7272
JM		 4662 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4663 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4664 goto exit;
4665 }
40a3a915 4666
528f7272 4667 vpath = &hldev->virtual_paths[vp_id];
40a3a915 4668
9f9b1645 4669 spin_lock_init(&vpath->lock);
528f7272
JM		 4670 vpath->vp_id = vp_id;
4671 vpath->vp_open = VXGE_HW_VP_OPEN;
4672 vpath->hldev = hldev;
4673 vpath->vp_config = config;
4674 vpath->vp_reg = hldev->vpath_reg[vp_id];
4675 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
40a3a915 4676
528f7272 4677 __vxge_hw_vpath_reset(hldev, vp_id);
40a3a915 4678
528f7272
JM		 4679 status = __vxge_hw_vpath_reset_check(vpath);
4680 if (status != VXGE_HW_OK) {
4681 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4682 goto exit;
4683 }
40a3a915 4684
528f7272
JM		 4685 status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4686 if (status != VXGE_HW_OK) {
4687 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4688 goto exit;
4689 }
40a3a915 4690
528f7272 4691 INIT_LIST_HEAD(&vpath->vpath_handles);
40a3a915 4692
528f7272 4693 vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
40a3a915 4694
528f7272
JM		 4695 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4696 hldev->tim_int_mask1, vp_id);
40a3a915 4697
528f7272
JM		 4698 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4699 if (status != VXGE_HW_OK)
4700 __vxge_hw_vp_terminate(hldev, vp_id);
40a3a915
RV		 4701exit:
4702 return status;
4703}
4704
528f7272
JM		 4705/*
4706 * vxge_hw_vpath_mtu_set - Set MTU.
4707 * Set new MTU value. Example, to use jumbo frames:
4708 * vxge_hw_vpath_mtu_set(my_device, 9600);
4709 */
4710enum vxge_hw_status
4711vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
42821a5b 4712{
528f7272
JM		 4713 u64 val64;
4714 enum vxge_hw_status status = VXGE_HW_OK;
4715 struct __vxge_hw_virtualpath *vpath;
42821a5b 4716
528f7272
JM		 4717 if (vp == NULL) {
4718 status = VXGE_HW_ERR_INVALID_HANDLE;
4719 goto exit;
4720 }
4721 vpath = vp->vpath;
42821a5b 4722
528f7272 4723 new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
42821a5b 4724
528f7272
JM		 4725 if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4726 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
42821a5b 4727
528f7272
JM		 4728 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4729
4730 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4731 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4732
4733 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4734
4735 vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4736
4737exit:
4738 return status;
42821a5b 4739}
4740
40a3a915 4741/*
528f7272
JM		 4742 * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4743 * Enable the DMA vpath statistics. The function is to be called to re-enable
4744 * the adapter to update stats into the host memory
40a3a915 4745 */
2c91308f 4746static enum vxge_hw_status
528f7272 4747vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
40a3a915 4748{
40a3a915 4749 enum vxge_hw_status status = VXGE_HW_OK;
528f7272 4750 struct __vxge_hw_virtualpath *vpath;
40a3a915 4751
528f7272 4752 vpath = vp->vpath;
40a3a915 4753
528f7272
JM		 4754 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4755 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4756 goto exit;
40a3a915
RV		 4757 }
4758
528f7272
JM		 4759 memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4760 sizeof(struct vxge_hw_vpath_stats_hw_info));
40a3a915 4761
528f7272
JM		 4762 status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4763exit:
4764 return status;
4765}
40a3a915 4766
528f7272
JM		 4767/*
4768 * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
4769 * This function allocates a block from block pool or from the system
4770 */
4771static struct __vxge_hw_blockpool_entry *
4772__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
4773{
4774 struct __vxge_hw_blockpool_entry *entry = NULL;
4775 struct __vxge_hw_blockpool *blockpool;
40a3a915 4776
528f7272 4777 blockpool = &devh->block_pool;
40a3a915 4778
528f7272 4779 if (size == blockpool->block_size) {
40a3a915 4780
528f7272 4781 if (!list_empty(&blockpool->free_block_list))
40a3a915 4782 entry = (struct __vxge_hw_blockpool_entry *)
528f7272 4783 list_first_entry(&blockpool->free_block_list,
40a3a915
RV		 4784 struct __vxge_hw_blockpool_entry,
4785 item);
4786
40a3a915
RV		 4787 if (entry != NULL) {
4788 list_del(&entry->item);
528f7272 4789 blockpool->pool_size--;
40a3a915
RV		 4790 }
4791 }
4792
528f7272
JM		 4793 if (entry != NULL)
4794 __vxge_hw_blockpool_blocks_add(blockpool);
4795
4796 return entry;
40a3a915
RV		 4797}
4798
4799/*
528f7272
JM		 4800 * vxge_hw_vpath_open - Open a virtual path on a given adapter
4801 * This function is used to open access to virtual path of an
4802 * adapter for offload, GRO operations. This function returns
4803 * synchronously.
40a3a915 4804 */
528f7272
JM		 4805enum vxge_hw_status
4806vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4807 struct vxge_hw_vpath_attr *attr,
4808 struct __vxge_hw_vpath_handle **vpath_handle)
40a3a915 4809{
528f7272
JM		 4810 struct __vxge_hw_virtualpath *vpath;
4811 struct __vxge_hw_vpath_handle *vp;
4812 enum vxge_hw_status status;
40a3a915 4813
528f7272 4814 vpath = &hldev->virtual_paths[attr->vp_id];
40a3a915 4815
528f7272
JM		 4816 if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4817 status = VXGE_HW_ERR_INVALID_STATE;
4818 goto vpath_open_exit1;
40a3a915
RV		 4819 }
4820
528f7272
JM		 4821 status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4822 &hldev->config.vp_config[attr->vp_id]);
4823 if (status != VXGE_HW_OK)
4824 goto vpath_open_exit1;
40a3a915 4825
528f7272
JM		 4826 vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
4827 if (vp == NULL) {
4828 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4829 goto vpath_open_exit2;
4830 }
40a3a915 4831
528f7272 4832 vp->vpath = vpath;
40a3a915 4833
528f7272
JM		 4834 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4835 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4836 if (status != VXGE_HW_OK)
4837 goto vpath_open_exit6;
40a3a915
RV		 4838 }
4839
528f7272
JM		 4840 if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4841 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4842 if (status != VXGE_HW_OK)
4843 goto vpath_open_exit7;
4844
4845 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
40a3a915 4846 }
40a3a915 4847
528f7272
JM		 4848 vpath->fifoh->tx_intr_num =
4849 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4850 VXGE_HW_VPATH_INTR_TX;
40a3a915 4851
528f7272
JM		 4852 vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4853 VXGE_HW_BLOCK_SIZE);
4854 if (vpath->stats_block == NULL) {
4855 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4856 goto vpath_open_exit8;
40a3a915
RV		 4857 }
4858
43d620c8 4859 vpath->hw_stats = vpath->stats_block->memblock;
528f7272
JM		 4860 memset(vpath->hw_stats, 0,
4861 sizeof(struct vxge_hw_vpath_stats_hw_info));
40a3a915 4862
528f7272
JM		 4863 hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4864 vpath->hw_stats;
40a3a915 4865
528f7272
JM		 4866 vpath->hw_stats_sav =
4867 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4868 memset(vpath->hw_stats_sav, 0,
4869 sizeof(struct vxge_hw_vpath_stats_hw_info));
40a3a915 4870
528f7272 4871 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
40a3a915 4872
528f7272
JM		 4873 status = vxge_hw_vpath_stats_enable(vp);
4874 if (status != VXGE_HW_OK)
4875 goto vpath_open_exit8;
40a3a915 4876
528f7272 4877 list_add(&vp->item, &vpath->vpath_handles);
40a3a915 4878
528f7272 4879 hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
40a3a915 4880
528f7272 4881 *vpath_handle = vp;
40a3a915 4882
528f7272
JM		 4883 attr->fifo_attr.userdata = vpath->fifoh;
4884 attr->ring_attr.userdata = vpath->ringh;
40a3a915 4885
528f7272
JM		 4886 return VXGE_HW_OK;
4887
4888vpath_open_exit8:
4889 if (vpath->ringh != NULL)
4890 __vxge_hw_ring_delete(vp);
4891vpath_open_exit7:
4892 if (vpath->fifoh != NULL)
4893 __vxge_hw_fifo_delete(vp);
4894vpath_open_exit6:
4895 vfree(vp);
4896vpath_open_exit2:
4897 __vxge_hw_vp_terminate(hldev, attr->vp_id);
4898vpath_open_exit1:
4899
4900 return status;
40a3a915
RV		 4901}
4902
528f7272
JM		 4903/**
4904 * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4905 * (vpath) open
4906 * @vp: Handle got from previous vpath open
4907 *
4908 * This function is used to close access to virtual path opened
4909 * earlier.
40a3a915 4910 */
528f7272 4911void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
40a3a915 4912{
528f7272
JM		 4913 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4914 struct __vxge_hw_ring *ring = vpath->ringh;
4915 struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
4916 u64 new_count, val64, val164;
40a3a915 4917
528f7272
JM		 4918 if (vdev->titan1) {
4919 new_count = readq(&vpath->vp_reg->rxdmem_size);
4920 new_count &= 0x1fff;
4921 } else
4922 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
40a3a915 4923
528f7272 4924 val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
40a3a915 4925
528f7272
JM		 4926 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4927 &vpath->vp_reg->prc_rxd_doorbell);
4928 readl(&vpath->vp_reg->prc_rxd_doorbell);
40a3a915 4929
528f7272
JM		 4930 val164 /= 2;
4931 val64 = readq(&vpath->vp_reg->prc_cfg6);
4932 val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4933 val64 &= 0x1ff;
40a3a915 4934
528f7272
JM		 4935 /*
4936 * Each RxD is of 4 qwords
4937 */
4938 new_count -= (val64 + 1);
4939 val64 = min(val164, new_count) / 4;
40a3a915 4940
528f7272
JM		 4941 ring->rxds_limit = min(ring->rxds_limit, val64);
4942 if (ring->rxds_limit < 4)
4943 ring->rxds_limit = 4;
4944}
40a3a915 4945
528f7272
JM		 4946/*
4947 * __vxge_hw_blockpool_block_free - Frees a block from block pool
4948 * @devh: Hal device
4949 * @entry: Entry of block to be freed
4950 *
4951 * This function frees a block from block pool
4952 */
4953static void
4954__vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
4955 struct __vxge_hw_blockpool_entry *entry)
4956{
4957 struct __vxge_hw_blockpool *blockpool;
40a3a915 4958
528f7272 4959 blockpool = &devh->block_pool;
40a3a915 4960
528f7272 4961 if (entry->length == blockpool->block_size) {
40a3a915
RV		 4962 list_add(&entry->item, &blockpool->free_block_list);
4963 blockpool->pool_size++;
528f7272 4964 }
40a3a915 4965
528f7272 4966 __vxge_hw_blockpool_blocks_remove(blockpool);
40a3a915
RV		 4967}
4968
4969/*
528f7272
JM		 4970 * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4971 * This function is used to close access to virtual path opened
4972 * earlier.
40a3a915 4973 */
528f7272 4974enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
40a3a915 4975{
528f7272
JM		 4976 struct __vxge_hw_virtualpath *vpath = NULL;
4977 struct __vxge_hw_device *devh = NULL;
4978 u32 vp_id = vp->vpath->vp_id;
4979 u32 is_empty = TRUE;
40a3a915
RV		 4980 enum vxge_hw_status status = VXGE_HW_OK;
4981
528f7272
JM		 4982 vpath = vp->vpath;
4983 devh = vpath->hldev;
40a3a915 4984
528f7272
JM		 4985 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4986 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4987 goto vpath_close_exit;
4988 }
40a3a915 4989
528f7272 4990 list_del(&vp->item);
40a3a915 4991
528f7272
JM		 4992 if (!list_empty(&vpath->vpath_handles)) {
4993 list_add(&vp->item, &vpath->vpath_handles);
4994 is_empty = FALSE;
4995 }
40a3a915 4996
528f7272
JM		 4997 if (!is_empty) {
4998 status = VXGE_HW_FAIL;
4999 goto vpath_close_exit;
5000 }
40a3a915 5001
528f7272 5002 devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
40a3a915 5003
528f7272
JM		 5004 if (vpath->ringh != NULL)
5005 __vxge_hw_ring_delete(vp);
40a3a915 5006
528f7272
JM		 5007 if (vpath->fifoh != NULL)
5008 __vxge_hw_fifo_delete(vp);
40a3a915 5009
528f7272
JM		 5010 if (vpath->stats_block != NULL)
5011 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
40a3a915 5012
528f7272 5013 vfree(vp);
40a3a915 5014
528f7272
JM		 5015 __vxge_hw_vp_terminate(devh, vp_id);
5016
528f7272
JM		 5017vpath_close_exit:
5018 return status;
40a3a915
RV		 5019}
5020
5021/*
528f7272
JM		 5022 * vxge_hw_vpath_reset - Resets vpath
5023 * This function is used to request a reset of vpath
40a3a915 5024 */
528f7272 5025enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
40a3a915 5026{
528f7272
JM		 5027 enum vxge_hw_status status;
5028 u32 vp_id;
5029 struct __vxge_hw_virtualpath *vpath = vp->vpath;
40a3a915 5030
528f7272 5031 vp_id = vpath->vp_id;
40a3a915 5032
528f7272
JM		 5033 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5034 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5035 goto exit;
40a3a915 5036 }
528f7272
JM		 5037
5038 status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
5039 if (status == VXGE_HW_OK)
5040 vpath->sw_stats->soft_reset_cnt++;
5041exit:
5042 return status;
40a3a915
RV		 5043}
5044
5045/*
528f7272
JM		 5046 * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
5047 * This function poll's for the vpath reset completion and re initializes
5048 * the vpath.
40a3a915 5049 */
528f7272
JM		 5050enum vxge_hw_status
5051vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
40a3a915 5052{
528f7272
JM		 5053 struct __vxge_hw_virtualpath *vpath = NULL;
5054 enum vxge_hw_status status;
5055 struct __vxge_hw_device *hldev;
5056 u32 vp_id;
40a3a915 5057
528f7272
JM		 5058 vp_id = vp->vpath->vp_id;
5059 vpath = vp->vpath;
5060 hldev = vpath->hldev;
40a3a915 5061
528f7272
JM		 5062 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
5063 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
5064 goto exit;
5065 }
40a3a915 5066
528f7272
JM		 5067 status = __vxge_hw_vpath_reset_check(vpath);
5068 if (status != VXGE_HW_OK)
5069 goto exit;
40a3a915 5070
528f7272
JM		 5071 status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
5072 if (status != VXGE_HW_OK)
5073 goto exit;
40a3a915 5074
528f7272
JM		 5075 status = __vxge_hw_vpath_initialize(hldev, vp_id);
5076 if (status != VXGE_HW_OK)
5077 goto exit;
40a3a915 5078
528f7272
JM		 5079 if (vpath->ringh != NULL)
5080 __vxge_hw_vpath_prc_configure(hldev, vp_id);
5081
5082 memset(vpath->hw_stats, 0,
5083 sizeof(struct vxge_hw_vpath_stats_hw_info));
5084
5085 memset(vpath->hw_stats_sav, 0,
5086 sizeof(struct vxge_hw_vpath_stats_hw_info));
5087
5088 writeq(vpath->stats_block->dma_addr,
5089 &vpath->vp_reg->stats_cfg);
5090
5091 status = vxge_hw_vpath_stats_enable(vp);
5092
5093exit:
5094 return status;
40a3a915
RV		 5095}
5096
5097/*
528f7272
JM		 5098 * vxge_hw_vpath_enable - Enable vpath.
5099 * This routine clears the vpath reset thereby enabling a vpath
5100 * to start forwarding frames and generating interrupts.
40a3a915 5101 */
528f7272
JM		 5102void
5103vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
40a3a915 5104{
528f7272
JM		 5105 struct __vxge_hw_device *hldev;
5106 u64 val64;
40a3a915 5107
528f7272 5108 hldev = vp->vpath->hldev;
40a3a915 5109
528f7272
JM		 5110 val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
5111 1 << (16 - vp->vpath->vp_id));
40a3a915 5112
528f7272
JM		 5113 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
5114 &hldev->common_reg->cmn_rsthdlr_cfg1);
40a3a915 5115}
Linux 6.x block layer and io_uring tree(s)