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1da177e4 | 1 | /************************************************************************ |
776bd20f | 2 | * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC |
926bd900 | 3 | * Copyright(c) 2002-2010 Exar Corp. |
d44570e4 | 4 | * |
1da177e4 LT |
5 | * This software may be used and distributed according to the terms of |
6 | * the GNU General Public License (GPL), incorporated herein by reference. | |
7 | * Drivers based on or derived from this code fall under the GPL and must | |
8 | * retain the authorship, copyright and license notice. This file is not | |
9 | * a complete program and may only be used when the entire operating | |
10 | * system is licensed under the GPL. | |
11 | * See the file COPYING in this distribution for more information. | |
12 | * | |
13 | * Credits: | |
20346722 | 14 | * Jeff Garzik : For pointing out the improper error condition |
15 | * check in the s2io_xmit routine and also some | |
16 | * issues in the Tx watch dog function. Also for | |
17 | * patiently answering all those innumerable | |
1da177e4 LT |
18 | * questions regaring the 2.6 porting issues. |
19 | * Stephen Hemminger : Providing proper 2.6 porting mechanism for some | |
20 | * macros available only in 2.6 Kernel. | |
20346722 | 21 | * Francois Romieu : For pointing out all code part that were |
1da177e4 | 22 | * deprecated and also styling related comments. |
20346722 | 23 | * Grant Grundler : For helping me get rid of some Architecture |
1da177e4 LT |
24 | * dependent code. |
25 | * Christopher Hellwig : Some more 2.6 specific issues in the driver. | |
20346722 | 26 | * |
1da177e4 | 27 | * The module loadable parameters that are supported by the driver and a brief |
a2a20aef | 28 | * explanation of all the variables. |
9dc737a7 | 29 | * |
20346722 | 30 | * rx_ring_num : This can be used to program the number of receive rings used |
31 | * in the driver. | |
9dc737a7 AR |
32 | * rx_ring_sz: This defines the number of receive blocks each ring can have. |
33 | * This is also an array of size 8. | |
da6971d8 | 34 | * rx_ring_mode: This defines the operation mode of all 8 rings. The valid |
6d517a27 | 35 | * values are 1, 2. |
1da177e4 | 36 | * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver. |
20346722 | 37 | * tx_fifo_len: This too is an array of 8. Each element defines the number of |
1da177e4 | 38 | * Tx descriptors that can be associated with each corresponding FIFO. |
9dc737a7 | 39 | * intr_type: This defines the type of interrupt. The values can be 0(INTA), |
8abc4d5b | 40 | * 2(MSI_X). Default value is '2(MSI_X)' |
9dc737a7 AR |
41 | * lro_max_pkts: This parameter defines maximum number of packets can be |
42 | * aggregated as a single large packet | |
926930b2 SS |
43 | * napi: This parameter used to enable/disable NAPI (polling Rx) |
44 | * Possible values '1' for enable and '0' for disable. Default is '1' | |
45 | * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO) | |
46 | * Possible values '1' for enable and '0' for disable. Default is '0' | |
47 | * vlan_tag_strip: This can be used to enable or disable vlan stripping. | |
48 | * Possible values '1' for enable , '0' for disable. | |
49 | * Default is '2' - which means disable in promisc mode | |
50 | * and enable in non-promiscuous mode. | |
3a3d5756 SH |
51 | * multiq: This parameter used to enable/disable MULTIQUEUE support. |
52 | * Possible values '1' for enable and '0' for disable. Default is '0' | |
1da177e4 LT |
53 | ************************************************************************/ |
54 | ||
6cef2b8e JP |
55 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
56 | ||
1da177e4 LT |
57 | #include <linux/module.h> |
58 | #include <linux/types.h> | |
59 | #include <linux/errno.h> | |
60 | #include <linux/ioport.h> | |
61 | #include <linux/pci.h> | |
1e7f0bd8 | 62 | #include <linux/dma-mapping.h> |
1da177e4 LT |
63 | #include <linux/kernel.h> |
64 | #include <linux/netdevice.h> | |
65 | #include <linux/etherdevice.h> | |
40239396 | 66 | #include <linux/mdio.h> |
1da177e4 LT |
67 | #include <linux/skbuff.h> |
68 | #include <linux/init.h> | |
69 | #include <linux/delay.h> | |
70 | #include <linux/stddef.h> | |
71 | #include <linux/ioctl.h> | |
72 | #include <linux/timex.h> | |
1da177e4 | 73 | #include <linux/ethtool.h> |
1da177e4 | 74 | #include <linux/workqueue.h> |
be3a6b02 | 75 | #include <linux/if_vlan.h> |
7d3d0439 RA |
76 | #include <linux/ip.h> |
77 | #include <linux/tcp.h> | |
d44570e4 JP |
78 | #include <linux/uaccess.h> |
79 | #include <linux/io.h> | |
5a0e3ad6 | 80 | #include <linux/slab.h> |
70c71606 | 81 | #include <linux/prefetch.h> |
7d3d0439 | 82 | #include <net/tcp.h> |
1da177e4 | 83 | |
1da177e4 | 84 | #include <asm/system.h> |
fe931395 | 85 | #include <asm/div64.h> |
330ce0de | 86 | #include <asm/irq.h> |
1da177e4 LT |
87 | |
88 | /* local include */ | |
89 | #include "s2io.h" | |
90 | #include "s2io-regs.h" | |
91 | ||
11410b62 | 92 | #define DRV_VERSION "2.0.26.28" |
6c1792f4 | 93 | |
1da177e4 | 94 | /* S2io Driver name & version. */ |
c0dbf37e JM |
95 | static const char s2io_driver_name[] = "Neterion"; |
96 | static const char s2io_driver_version[] = DRV_VERSION; | |
1da177e4 | 97 | |
c0dbf37e JM |
98 | static const int rxd_size[2] = {32, 48}; |
99 | static const int rxd_count[2] = {127, 85}; | |
da6971d8 | 100 | |
1ee6dd77 | 101 | static inline int RXD_IS_UP2DT(struct RxD_t *rxdp) |
5e25b9dd | 102 | { |
103 | int ret; | |
104 | ||
105 | ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) && | |
d44570e4 | 106 | (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK)); |
5e25b9dd | 107 | |
108 | return ret; | |
109 | } | |
110 | ||
20346722 | 111 | /* |
1da177e4 LT |
112 | * Cards with following subsystem_id have a link state indication |
113 | * problem, 600B, 600C, 600D, 640B, 640C and 640D. | |
114 | * macro below identifies these cards given the subsystem_id. | |
115 | */ | |
d44570e4 JP |
116 | #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \ |
117 | (dev_type == XFRAME_I_DEVICE) ? \ | |
118 | ((((subid >= 0x600B) && (subid <= 0x600D)) || \ | |
119 | ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0 | |
1da177e4 LT |
120 | |
121 | #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \ | |
122 | ADAPTER_STATUS_RMAC_LOCAL_FAULT))) | |
1da177e4 | 123 | |
d44570e4 | 124 | static inline int is_s2io_card_up(const struct s2io_nic *sp) |
92b84437 SS |
125 | { |
126 | return test_bit(__S2IO_STATE_CARD_UP, &sp->state); | |
127 | } | |
128 | ||
1da177e4 | 129 | /* Ethtool related variables and Macros. */ |
6fce365d | 130 | static const char s2io_gstrings[][ETH_GSTRING_LEN] = { |
1da177e4 LT |
131 | "Register test\t(offline)", |
132 | "Eeprom test\t(offline)", | |
133 | "Link test\t(online)", | |
134 | "RLDRAM test\t(offline)", | |
135 | "BIST Test\t(offline)" | |
136 | }; | |
137 | ||
6fce365d | 138 | static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = { |
1da177e4 LT |
139 | {"tmac_frms"}, |
140 | {"tmac_data_octets"}, | |
141 | {"tmac_drop_frms"}, | |
142 | {"tmac_mcst_frms"}, | |
143 | {"tmac_bcst_frms"}, | |
144 | {"tmac_pause_ctrl_frms"}, | |
bd1034f0 AR |
145 | {"tmac_ttl_octets"}, |
146 | {"tmac_ucst_frms"}, | |
147 | {"tmac_nucst_frms"}, | |
1da177e4 | 148 | {"tmac_any_err_frms"}, |
bd1034f0 | 149 | {"tmac_ttl_less_fb_octets"}, |
1da177e4 LT |
150 | {"tmac_vld_ip_octets"}, |
151 | {"tmac_vld_ip"}, | |
152 | {"tmac_drop_ip"}, | |
153 | {"tmac_icmp"}, | |
154 | {"tmac_rst_tcp"}, | |
155 | {"tmac_tcp"}, | |
156 | {"tmac_udp"}, | |
157 | {"rmac_vld_frms"}, | |
158 | {"rmac_data_octets"}, | |
159 | {"rmac_fcs_err_frms"}, | |
160 | {"rmac_drop_frms"}, | |
161 | {"rmac_vld_mcst_frms"}, | |
162 | {"rmac_vld_bcst_frms"}, | |
163 | {"rmac_in_rng_len_err_frms"}, | |
bd1034f0 | 164 | {"rmac_out_rng_len_err_frms"}, |
1da177e4 LT |
165 | {"rmac_long_frms"}, |
166 | {"rmac_pause_ctrl_frms"}, | |
bd1034f0 AR |
167 | {"rmac_unsup_ctrl_frms"}, |
168 | {"rmac_ttl_octets"}, | |
169 | {"rmac_accepted_ucst_frms"}, | |
170 | {"rmac_accepted_nucst_frms"}, | |
1da177e4 | 171 | {"rmac_discarded_frms"}, |
bd1034f0 AR |
172 | {"rmac_drop_events"}, |
173 | {"rmac_ttl_less_fb_octets"}, | |
174 | {"rmac_ttl_frms"}, | |
1da177e4 LT |
175 | {"rmac_usized_frms"}, |
176 | {"rmac_osized_frms"}, | |
177 | {"rmac_frag_frms"}, | |
178 | {"rmac_jabber_frms"}, | |
bd1034f0 AR |
179 | {"rmac_ttl_64_frms"}, |
180 | {"rmac_ttl_65_127_frms"}, | |
181 | {"rmac_ttl_128_255_frms"}, | |
182 | {"rmac_ttl_256_511_frms"}, | |
183 | {"rmac_ttl_512_1023_frms"}, | |
184 | {"rmac_ttl_1024_1518_frms"}, | |
1da177e4 LT |
185 | {"rmac_ip"}, |
186 | {"rmac_ip_octets"}, | |
187 | {"rmac_hdr_err_ip"}, | |
188 | {"rmac_drop_ip"}, | |
189 | {"rmac_icmp"}, | |
190 | {"rmac_tcp"}, | |
191 | {"rmac_udp"}, | |
192 | {"rmac_err_drp_udp"}, | |
bd1034f0 AR |
193 | {"rmac_xgmii_err_sym"}, |
194 | {"rmac_frms_q0"}, | |
195 | {"rmac_frms_q1"}, | |
196 | {"rmac_frms_q2"}, | |
197 | {"rmac_frms_q3"}, | |
198 | {"rmac_frms_q4"}, | |
199 | {"rmac_frms_q5"}, | |
200 | {"rmac_frms_q6"}, | |
201 | {"rmac_frms_q7"}, | |
202 | {"rmac_full_q0"}, | |
203 | {"rmac_full_q1"}, | |
204 | {"rmac_full_q2"}, | |
205 | {"rmac_full_q3"}, | |
206 | {"rmac_full_q4"}, | |
207 | {"rmac_full_q5"}, | |
208 | {"rmac_full_q6"}, | |
209 | {"rmac_full_q7"}, | |
1da177e4 | 210 | {"rmac_pause_cnt"}, |
bd1034f0 AR |
211 | {"rmac_xgmii_data_err_cnt"}, |
212 | {"rmac_xgmii_ctrl_err_cnt"}, | |
1da177e4 LT |
213 | {"rmac_accepted_ip"}, |
214 | {"rmac_err_tcp"}, | |
bd1034f0 AR |
215 | {"rd_req_cnt"}, |
216 | {"new_rd_req_cnt"}, | |
217 | {"new_rd_req_rtry_cnt"}, | |
218 | {"rd_rtry_cnt"}, | |
219 | {"wr_rtry_rd_ack_cnt"}, | |
220 | {"wr_req_cnt"}, | |
221 | {"new_wr_req_cnt"}, | |
222 | {"new_wr_req_rtry_cnt"}, | |
223 | {"wr_rtry_cnt"}, | |
224 | {"wr_disc_cnt"}, | |
225 | {"rd_rtry_wr_ack_cnt"}, | |
226 | {"txp_wr_cnt"}, | |
227 | {"txd_rd_cnt"}, | |
228 | {"txd_wr_cnt"}, | |
229 | {"rxd_rd_cnt"}, | |
230 | {"rxd_wr_cnt"}, | |
231 | {"txf_rd_cnt"}, | |
fa1f0cb3 SS |
232 | {"rxf_wr_cnt"} |
233 | }; | |
234 | ||
6fce365d | 235 | static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = { |
bd1034f0 AR |
236 | {"rmac_ttl_1519_4095_frms"}, |
237 | {"rmac_ttl_4096_8191_frms"}, | |
238 | {"rmac_ttl_8192_max_frms"}, | |
239 | {"rmac_ttl_gt_max_frms"}, | |
240 | {"rmac_osized_alt_frms"}, | |
241 | {"rmac_jabber_alt_frms"}, | |
242 | {"rmac_gt_max_alt_frms"}, | |
243 | {"rmac_vlan_frms"}, | |
244 | {"rmac_len_discard"}, | |
245 | {"rmac_fcs_discard"}, | |
246 | {"rmac_pf_discard"}, | |
247 | {"rmac_da_discard"}, | |
248 | {"rmac_red_discard"}, | |
249 | {"rmac_rts_discard"}, | |
250 | {"rmac_ingm_full_discard"}, | |
fa1f0cb3 SS |
251 | {"link_fault_cnt"} |
252 | }; | |
253 | ||
6fce365d | 254 | static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = { |
7ba013ac | 255 | {"\n DRIVER STATISTICS"}, |
256 | {"single_bit_ecc_errs"}, | |
257 | {"double_bit_ecc_errs"}, | |
bd1034f0 AR |
258 | {"parity_err_cnt"}, |
259 | {"serious_err_cnt"}, | |
260 | {"soft_reset_cnt"}, | |
261 | {"fifo_full_cnt"}, | |
8116f3cf SS |
262 | {"ring_0_full_cnt"}, |
263 | {"ring_1_full_cnt"}, | |
264 | {"ring_2_full_cnt"}, | |
265 | {"ring_3_full_cnt"}, | |
266 | {"ring_4_full_cnt"}, | |
267 | {"ring_5_full_cnt"}, | |
268 | {"ring_6_full_cnt"}, | |
269 | {"ring_7_full_cnt"}, | |
43b7c451 SH |
270 | {"alarm_transceiver_temp_high"}, |
271 | {"alarm_transceiver_temp_low"}, | |
272 | {"alarm_laser_bias_current_high"}, | |
273 | {"alarm_laser_bias_current_low"}, | |
274 | {"alarm_laser_output_power_high"}, | |
275 | {"alarm_laser_output_power_low"}, | |
276 | {"warn_transceiver_temp_high"}, | |
277 | {"warn_transceiver_temp_low"}, | |
278 | {"warn_laser_bias_current_high"}, | |
279 | {"warn_laser_bias_current_low"}, | |
280 | {"warn_laser_output_power_high"}, | |
281 | {"warn_laser_output_power_low"}, | |
282 | {"lro_aggregated_pkts"}, | |
283 | {"lro_flush_both_count"}, | |
284 | {"lro_out_of_sequence_pkts"}, | |
285 | {"lro_flush_due_to_max_pkts"}, | |
286 | {"lro_avg_aggr_pkts"}, | |
287 | {"mem_alloc_fail_cnt"}, | |
288 | {"pci_map_fail_cnt"}, | |
289 | {"watchdog_timer_cnt"}, | |
290 | {"mem_allocated"}, | |
291 | {"mem_freed"}, | |
292 | {"link_up_cnt"}, | |
293 | {"link_down_cnt"}, | |
294 | {"link_up_time"}, | |
295 | {"link_down_time"}, | |
296 | {"tx_tcode_buf_abort_cnt"}, | |
297 | {"tx_tcode_desc_abort_cnt"}, | |
298 | {"tx_tcode_parity_err_cnt"}, | |
299 | {"tx_tcode_link_loss_cnt"}, | |
300 | {"tx_tcode_list_proc_err_cnt"}, | |
301 | {"rx_tcode_parity_err_cnt"}, | |
302 | {"rx_tcode_abort_cnt"}, | |
303 | {"rx_tcode_parity_abort_cnt"}, | |
304 | {"rx_tcode_rda_fail_cnt"}, | |
305 | {"rx_tcode_unkn_prot_cnt"}, | |
306 | {"rx_tcode_fcs_err_cnt"}, | |
307 | {"rx_tcode_buf_size_err_cnt"}, | |
308 | {"rx_tcode_rxd_corrupt_cnt"}, | |
309 | {"rx_tcode_unkn_err_cnt"}, | |
8116f3cf SS |
310 | {"tda_err_cnt"}, |
311 | {"pfc_err_cnt"}, | |
312 | {"pcc_err_cnt"}, | |
313 | {"tti_err_cnt"}, | |
314 | {"tpa_err_cnt"}, | |
315 | {"sm_err_cnt"}, | |
316 | {"lso_err_cnt"}, | |
317 | {"mac_tmac_err_cnt"}, | |
318 | {"mac_rmac_err_cnt"}, | |
319 | {"xgxs_txgxs_err_cnt"}, | |
320 | {"xgxs_rxgxs_err_cnt"}, | |
321 | {"rc_err_cnt"}, | |
322 | {"prc_pcix_err_cnt"}, | |
323 | {"rpa_err_cnt"}, | |
324 | {"rda_err_cnt"}, | |
325 | {"rti_err_cnt"}, | |
326 | {"mc_err_cnt"} | |
1da177e4 LT |
327 | }; |
328 | ||
4c3616cd AMR |
329 | #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys) |
330 | #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys) | |
331 | #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys) | |
fa1f0cb3 | 332 | |
d44570e4 JP |
333 | #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN) |
334 | #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN) | |
fa1f0cb3 | 335 | |
d44570e4 JP |
336 | #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN) |
337 | #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN) | |
1da177e4 | 338 | |
4c3616cd | 339 | #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings) |
d44570e4 | 340 | #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN) |
1da177e4 | 341 | |
d44570e4 JP |
342 | #define S2IO_TIMER_CONF(timer, handle, arg, exp) \ |
343 | init_timer(&timer); \ | |
344 | timer.function = handle; \ | |
345 | timer.data = (unsigned long)arg; \ | |
346 | mod_timer(&timer, (jiffies + exp)) \ | |
25fff88e | 347 | |
2fd37688 SS |
348 | /* copy mac addr to def_mac_addr array */ |
349 | static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr) | |
350 | { | |
351 | sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr); | |
352 | sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8); | |
353 | sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16); | |
354 | sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24); | |
355 | sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32); | |
356 | sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40); | |
357 | } | |
04025095 | 358 | |
20346722 | 359 | /* |
1da177e4 LT |
360 | * Constants to be programmed into the Xena's registers, to configure |
361 | * the XAUI. | |
362 | */ | |
363 | ||
1da177e4 | 364 | #define END_SIGN 0x0 |
f71e1309 | 365 | static const u64 herc_act_dtx_cfg[] = { |
541ae68f | 366 | /* Set address */ |
e960fc5c | 367 | 0x8000051536750000ULL, 0x80000515367500E0ULL, |
541ae68f | 368 | /* Write data */ |
e960fc5c | 369 | 0x8000051536750004ULL, 0x80000515367500E4ULL, |
541ae68f | 370 | /* Set address */ |
371 | 0x80010515003F0000ULL, 0x80010515003F00E0ULL, | |
372 | /* Write data */ | |
373 | 0x80010515003F0004ULL, 0x80010515003F00E4ULL, | |
374 | /* Set address */ | |
e960fc5c | 375 | 0x801205150D440000ULL, 0x801205150D4400E0ULL, |
376 | /* Write data */ | |
377 | 0x801205150D440004ULL, 0x801205150D4400E4ULL, | |
378 | /* Set address */ | |
541ae68f | 379 | 0x80020515F2100000ULL, 0x80020515F21000E0ULL, |
380 | /* Write data */ | |
381 | 0x80020515F2100004ULL, 0x80020515F21000E4ULL, | |
382 | /* Done */ | |
383 | END_SIGN | |
384 | }; | |
385 | ||
f71e1309 | 386 | static const u64 xena_dtx_cfg[] = { |
c92ca04b | 387 | /* Set address */ |
1da177e4 | 388 | 0x8000051500000000ULL, 0x80000515000000E0ULL, |
c92ca04b AR |
389 | /* Write data */ |
390 | 0x80000515D9350004ULL, 0x80000515D93500E4ULL, | |
391 | /* Set address */ | |
392 | 0x8001051500000000ULL, 0x80010515000000E0ULL, | |
393 | /* Write data */ | |
394 | 0x80010515001E0004ULL, 0x80010515001E00E4ULL, | |
395 | /* Set address */ | |
1da177e4 | 396 | 0x8002051500000000ULL, 0x80020515000000E0ULL, |
c92ca04b AR |
397 | /* Write data */ |
398 | 0x80020515F2100004ULL, 0x80020515F21000E4ULL, | |
1da177e4 LT |
399 | END_SIGN |
400 | }; | |
401 | ||
20346722 | 402 | /* |
1da177e4 LT |
403 | * Constants for Fixing the MacAddress problem seen mostly on |
404 | * Alpha machines. | |
405 | */ | |
f71e1309 | 406 | static const u64 fix_mac[] = { |
1da177e4 LT |
407 | 0x0060000000000000ULL, 0x0060600000000000ULL, |
408 | 0x0040600000000000ULL, 0x0000600000000000ULL, | |
409 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
410 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
411 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
412 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
413 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
414 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
415 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
416 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
417 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
418 | 0x0020600000000000ULL, 0x0060600000000000ULL, | |
419 | 0x0020600000000000ULL, 0x0000600000000000ULL, | |
420 | 0x0040600000000000ULL, 0x0060600000000000ULL, | |
421 | END_SIGN | |
422 | }; | |
423 | ||
b41477f3 AR |
424 | MODULE_LICENSE("GPL"); |
425 | MODULE_VERSION(DRV_VERSION); | |
426 | ||
427 | ||
1da177e4 | 428 | /* Module Loadable parameters. */ |
6cfc482b | 429 | S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM); |
b41477f3 | 430 | S2IO_PARM_INT(rx_ring_num, 1); |
3a3d5756 | 431 | S2IO_PARM_INT(multiq, 0); |
b41477f3 AR |
432 | S2IO_PARM_INT(rx_ring_mode, 1); |
433 | S2IO_PARM_INT(use_continuous_tx_intrs, 1); | |
434 | S2IO_PARM_INT(rmac_pause_time, 0x100); | |
435 | S2IO_PARM_INT(mc_pause_threshold_q0q3, 187); | |
436 | S2IO_PARM_INT(mc_pause_threshold_q4q7, 187); | |
437 | S2IO_PARM_INT(shared_splits, 0); | |
438 | S2IO_PARM_INT(tmac_util_period, 5); | |
439 | S2IO_PARM_INT(rmac_util_period, 5); | |
b41477f3 | 440 | S2IO_PARM_INT(l3l4hdr_size, 128); |
6cfc482b SH |
441 | /* 0 is no steering, 1 is Priority steering, 2 is Default steering */ |
442 | S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING); | |
303bcb4b | 443 | /* Frequency of Rx desc syncs expressed as power of 2 */ |
b41477f3 | 444 | S2IO_PARM_INT(rxsync_frequency, 3); |
eccb8628 | 445 | /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */ |
8abc4d5b | 446 | S2IO_PARM_INT(intr_type, 2); |
7d3d0439 | 447 | /* Large receive offload feature */ |
43b7c451 | 448 | |
7d3d0439 RA |
449 | /* Max pkts to be aggregated by LRO at one time. If not specified, |
450 | * aggregation happens until we hit max IP pkt size(64K) | |
451 | */ | |
b41477f3 | 452 | S2IO_PARM_INT(lro_max_pkts, 0xFFFF); |
b41477f3 | 453 | S2IO_PARM_INT(indicate_max_pkts, 0); |
db874e65 SS |
454 | |
455 | S2IO_PARM_INT(napi, 1); | |
456 | S2IO_PARM_INT(ufo, 0); | |
926930b2 | 457 | S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC); |
b41477f3 AR |
458 | |
459 | static unsigned int tx_fifo_len[MAX_TX_FIFOS] = | |
d44570e4 | 460 | {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN}; |
b41477f3 | 461 | static unsigned int rx_ring_sz[MAX_RX_RINGS] = |
d44570e4 | 462 | {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT}; |
b41477f3 | 463 | static unsigned int rts_frm_len[MAX_RX_RINGS] = |
d44570e4 | 464 | {[0 ...(MAX_RX_RINGS - 1)] = 0 }; |
b41477f3 AR |
465 | |
466 | module_param_array(tx_fifo_len, uint, NULL, 0); | |
467 | module_param_array(rx_ring_sz, uint, NULL, 0); | |
468 | module_param_array(rts_frm_len, uint, NULL, 0); | |
1da177e4 | 469 | |
20346722 | 470 | /* |
1da177e4 | 471 | * S2IO device table. |
20346722 | 472 | * This table lists all the devices that this driver supports. |
1da177e4 | 473 | */ |
a3aa1884 | 474 | static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = { |
1da177e4 LT |
475 | {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN, |
476 | PCI_ANY_ID, PCI_ANY_ID}, | |
477 | {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI, | |
478 | PCI_ANY_ID, PCI_ANY_ID}, | |
479 | {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN, | |
d44570e4 JP |
480 | PCI_ANY_ID, PCI_ANY_ID}, |
481 | {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI, | |
482 | PCI_ANY_ID, PCI_ANY_ID}, | |
1da177e4 LT |
483 | {0,} |
484 | }; | |
485 | ||
486 | MODULE_DEVICE_TABLE(pci, s2io_tbl); | |
487 | ||
d796fdb7 LV |
488 | static struct pci_error_handlers s2io_err_handler = { |
489 | .error_detected = s2io_io_error_detected, | |
490 | .slot_reset = s2io_io_slot_reset, | |
491 | .resume = s2io_io_resume, | |
492 | }; | |
493 | ||
1da177e4 | 494 | static struct pci_driver s2io_driver = { |
d44570e4 JP |
495 | .name = "S2IO", |
496 | .id_table = s2io_tbl, | |
497 | .probe = s2io_init_nic, | |
498 | .remove = __devexit_p(s2io_rem_nic), | |
499 | .err_handler = &s2io_err_handler, | |
1da177e4 LT |
500 | }; |
501 | ||
502 | /* A simplifier macro used both by init and free shared_mem Fns(). */ | |
503 | #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each) | |
504 | ||
3a3d5756 SH |
505 | /* netqueue manipulation helper functions */ |
506 | static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp) | |
507 | { | |
fd2ea0a7 DM |
508 | if (!sp->config.multiq) { |
509 | int i; | |
510 | ||
3a3d5756 SH |
511 | for (i = 0; i < sp->config.tx_fifo_num; i++) |
512 | sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP; | |
3a3d5756 | 513 | } |
fd2ea0a7 | 514 | netif_tx_stop_all_queues(sp->dev); |
3a3d5756 SH |
515 | } |
516 | ||
517 | static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no) | |
518 | { | |
fd2ea0a7 | 519 | if (!sp->config.multiq) |
3a3d5756 SH |
520 | sp->mac_control.fifos[fifo_no].queue_state = |
521 | FIFO_QUEUE_STOP; | |
fd2ea0a7 DM |
522 | |
523 | netif_tx_stop_all_queues(sp->dev); | |
3a3d5756 SH |
524 | } |
525 | ||
526 | static inline void s2io_start_all_tx_queue(struct s2io_nic *sp) | |
527 | { | |
fd2ea0a7 DM |
528 | if (!sp->config.multiq) { |
529 | int i; | |
530 | ||
3a3d5756 SH |
531 | for (i = 0; i < sp->config.tx_fifo_num; i++) |
532 | sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; | |
3a3d5756 | 533 | } |
fd2ea0a7 | 534 | netif_tx_start_all_queues(sp->dev); |
3a3d5756 SH |
535 | } |
536 | ||
537 | static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no) | |
538 | { | |
fd2ea0a7 | 539 | if (!sp->config.multiq) |
3a3d5756 SH |
540 | sp->mac_control.fifos[fifo_no].queue_state = |
541 | FIFO_QUEUE_START; | |
fd2ea0a7 DM |
542 | |
543 | netif_tx_start_all_queues(sp->dev); | |
3a3d5756 SH |
544 | } |
545 | ||
546 | static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp) | |
547 | { | |
fd2ea0a7 DM |
548 | if (!sp->config.multiq) { |
549 | int i; | |
550 | ||
3a3d5756 SH |
551 | for (i = 0; i < sp->config.tx_fifo_num; i++) |
552 | sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START; | |
3a3d5756 | 553 | } |
fd2ea0a7 | 554 | netif_tx_wake_all_queues(sp->dev); |
3a3d5756 SH |
555 | } |
556 | ||
557 | static inline void s2io_wake_tx_queue( | |
558 | struct fifo_info *fifo, int cnt, u8 multiq) | |
559 | { | |
560 | ||
3a3d5756 SH |
561 | if (multiq) { |
562 | if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no)) | |
563 | netif_wake_subqueue(fifo->dev, fifo->fifo_no); | |
b19fa1fa | 564 | } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) { |
3a3d5756 SH |
565 | if (netif_queue_stopped(fifo->dev)) { |
566 | fifo->queue_state = FIFO_QUEUE_START; | |
567 | netif_wake_queue(fifo->dev); | |
568 | } | |
569 | } | |
570 | } | |
571 | ||
1da177e4 LT |
572 | /** |
573 | * init_shared_mem - Allocation and Initialization of Memory | |
574 | * @nic: Device private variable. | |
20346722 | 575 | * Description: The function allocates all the memory areas shared |
576 | * between the NIC and the driver. This includes Tx descriptors, | |
1da177e4 LT |
577 | * Rx descriptors and the statistics block. |
578 | */ | |
579 | ||
580 | static int init_shared_mem(struct s2io_nic *nic) | |
581 | { | |
582 | u32 size; | |
583 | void *tmp_v_addr, *tmp_v_addr_next; | |
584 | dma_addr_t tmp_p_addr, tmp_p_addr_next; | |
1ee6dd77 | 585 | struct RxD_block *pre_rxd_blk = NULL; |
372cc597 | 586 | int i, j, blk_cnt; |
1da177e4 LT |
587 | int lst_size, lst_per_page; |
588 | struct net_device *dev = nic->dev; | |
8ae418cf | 589 | unsigned long tmp; |
1ee6dd77 | 590 | struct buffAdd *ba; |
ffb5df6c JP |
591 | struct config_param *config = &nic->config; |
592 | struct mac_info *mac_control = &nic->mac_control; | |
491976b2 | 593 | unsigned long long mem_allocated = 0; |
1da177e4 | 594 | |
13d866a9 | 595 | /* Allocation and initialization of TXDLs in FIFOs */ |
1da177e4 LT |
596 | size = 0; |
597 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
598 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
599 | ||
600 | size += tx_cfg->fifo_len; | |
1da177e4 LT |
601 | } |
602 | if (size > MAX_AVAILABLE_TXDS) { | |
9e39f7c5 JP |
603 | DBG_PRINT(ERR_DBG, |
604 | "Too many TxDs requested: %d, max supported: %d\n", | |
605 | size, MAX_AVAILABLE_TXDS); | |
b41477f3 | 606 | return -EINVAL; |
1da177e4 LT |
607 | } |
608 | ||
2fda096d SR |
609 | size = 0; |
610 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
611 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
612 | ||
613 | size = tx_cfg->fifo_len; | |
2fda096d SR |
614 | /* |
615 | * Legal values are from 2 to 8192 | |
616 | */ | |
617 | if (size < 2) { | |
9e39f7c5 JP |
618 | DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - " |
619 | "Valid lengths are 2 through 8192\n", | |
620 | i, size); | |
2fda096d SR |
621 | return -EINVAL; |
622 | } | |
623 | } | |
624 | ||
1ee6dd77 | 625 | lst_size = (sizeof(struct TxD) * config->max_txds); |
1da177e4 LT |
626 | lst_per_page = PAGE_SIZE / lst_size; |
627 | ||
628 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
629 | struct fifo_info *fifo = &mac_control->fifos[i]; |
630 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
631 | int fifo_len = tx_cfg->fifo_len; | |
1ee6dd77 | 632 | int list_holder_size = fifo_len * sizeof(struct list_info_hold); |
13d866a9 JP |
633 | |
634 | fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL); | |
635 | if (!fifo->list_info) { | |
d44570e4 | 636 | DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n"); |
1da177e4 LT |
637 | return -ENOMEM; |
638 | } | |
491976b2 | 639 | mem_allocated += list_holder_size; |
1da177e4 LT |
640 | } |
641 | for (i = 0; i < config->tx_fifo_num; i++) { | |
642 | int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len, | |
643 | lst_per_page); | |
13d866a9 JP |
644 | struct fifo_info *fifo = &mac_control->fifos[i]; |
645 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
646 | ||
647 | fifo->tx_curr_put_info.offset = 0; | |
648 | fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1; | |
649 | fifo->tx_curr_get_info.offset = 0; | |
650 | fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1; | |
651 | fifo->fifo_no = i; | |
652 | fifo->nic = nic; | |
653 | fifo->max_txds = MAX_SKB_FRAGS + 2; | |
654 | fifo->dev = dev; | |
20346722 | 655 | |
1da177e4 LT |
656 | for (j = 0; j < page_num; j++) { |
657 | int k = 0; | |
658 | dma_addr_t tmp_p; | |
659 | void *tmp_v; | |
660 | tmp_v = pci_alloc_consistent(nic->pdev, | |
661 | PAGE_SIZE, &tmp_p); | |
662 | if (!tmp_v) { | |
9e39f7c5 JP |
663 | DBG_PRINT(INFO_DBG, |
664 | "pci_alloc_consistent failed for TxDL\n"); | |
1da177e4 LT |
665 | return -ENOMEM; |
666 | } | |
776bd20f | 667 | /* If we got a zero DMA address(can happen on |
668 | * certain platforms like PPC), reallocate. | |
669 | * Store virtual address of page we don't want, | |
670 | * to be freed later. | |
671 | */ | |
672 | if (!tmp_p) { | |
673 | mac_control->zerodma_virt_addr = tmp_v; | |
6aa20a22 | 674 | DBG_PRINT(INIT_DBG, |
9e39f7c5 JP |
675 | "%s: Zero DMA address for TxDL. " |
676 | "Virtual address %p\n", | |
677 | dev->name, tmp_v); | |
776bd20f | 678 | tmp_v = pci_alloc_consistent(nic->pdev, |
d44570e4 | 679 | PAGE_SIZE, &tmp_p); |
776bd20f | 680 | if (!tmp_v) { |
0c61ed5f | 681 | DBG_PRINT(INFO_DBG, |
9e39f7c5 | 682 | "pci_alloc_consistent failed for TxDL\n"); |
776bd20f | 683 | return -ENOMEM; |
684 | } | |
491976b2 | 685 | mem_allocated += PAGE_SIZE; |
776bd20f | 686 | } |
1da177e4 LT |
687 | while (k < lst_per_page) { |
688 | int l = (j * lst_per_page) + k; | |
13d866a9 | 689 | if (l == tx_cfg->fifo_len) |
20346722 | 690 | break; |
13d866a9 | 691 | fifo->list_info[l].list_virt_addr = |
d44570e4 | 692 | tmp_v + (k * lst_size); |
13d866a9 | 693 | fifo->list_info[l].list_phy_addr = |
d44570e4 | 694 | tmp_p + (k * lst_size); |
1da177e4 LT |
695 | k++; |
696 | } | |
697 | } | |
698 | } | |
1da177e4 | 699 | |
2fda096d | 700 | for (i = 0; i < config->tx_fifo_num; i++) { |
13d866a9 JP |
701 | struct fifo_info *fifo = &mac_control->fifos[i]; |
702 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
703 | ||
704 | size = tx_cfg->fifo_len; | |
705 | fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL); | |
706 | if (!fifo->ufo_in_band_v) | |
2fda096d SR |
707 | return -ENOMEM; |
708 | mem_allocated += (size * sizeof(u64)); | |
709 | } | |
fed5eccd | 710 | |
1da177e4 LT |
711 | /* Allocation and initialization of RXDs in Rings */ |
712 | size = 0; | |
713 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
714 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
715 | struct ring_info *ring = &mac_control->rings[i]; | |
716 | ||
717 | if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) { | |
9e39f7c5 JP |
718 | DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a " |
719 | "multiple of RxDs per Block\n", | |
720 | dev->name, i); | |
1da177e4 LT |
721 | return FAILURE; |
722 | } | |
13d866a9 JP |
723 | size += rx_cfg->num_rxd; |
724 | ring->block_count = rx_cfg->num_rxd / | |
d44570e4 | 725 | (rxd_count[nic->rxd_mode] + 1); |
13d866a9 | 726 | ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count; |
1da177e4 | 727 | } |
da6971d8 | 728 | if (nic->rxd_mode == RXD_MODE_1) |
1ee6dd77 | 729 | size = (size * (sizeof(struct RxD1))); |
da6971d8 | 730 | else |
1ee6dd77 | 731 | size = (size * (sizeof(struct RxD3))); |
1da177e4 LT |
732 | |
733 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
734 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
735 | struct ring_info *ring = &mac_control->rings[i]; | |
736 | ||
737 | ring->rx_curr_get_info.block_index = 0; | |
738 | ring->rx_curr_get_info.offset = 0; | |
739 | ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1; | |
740 | ring->rx_curr_put_info.block_index = 0; | |
741 | ring->rx_curr_put_info.offset = 0; | |
742 | ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1; | |
743 | ring->nic = nic; | |
744 | ring->ring_no = i; | |
13d866a9 JP |
745 | |
746 | blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1); | |
1da177e4 LT |
747 | /* Allocating all the Rx blocks */ |
748 | for (j = 0; j < blk_cnt; j++) { | |
1ee6dd77 | 749 | struct rx_block_info *rx_blocks; |
da6971d8 AR |
750 | int l; |
751 | ||
13d866a9 | 752 | rx_blocks = &ring->rx_blocks[j]; |
d44570e4 | 753 | size = SIZE_OF_BLOCK; /* size is always page size */ |
1da177e4 LT |
754 | tmp_v_addr = pci_alloc_consistent(nic->pdev, size, |
755 | &tmp_p_addr); | |
756 | if (tmp_v_addr == NULL) { | |
757 | /* | |
20346722 | 758 | * In case of failure, free_shared_mem() |
759 | * is called, which should free any | |
760 | * memory that was alloced till the | |
1da177e4 LT |
761 | * failure happened. |
762 | */ | |
da6971d8 | 763 | rx_blocks->block_virt_addr = tmp_v_addr; |
1da177e4 LT |
764 | return -ENOMEM; |
765 | } | |
491976b2 | 766 | mem_allocated += size; |
1da177e4 | 767 | memset(tmp_v_addr, 0, size); |
4f870320 JP |
768 | |
769 | size = sizeof(struct rxd_info) * | |
770 | rxd_count[nic->rxd_mode]; | |
da6971d8 AR |
771 | rx_blocks->block_virt_addr = tmp_v_addr; |
772 | rx_blocks->block_dma_addr = tmp_p_addr; | |
4f870320 | 773 | rx_blocks->rxds = kmalloc(size, GFP_KERNEL); |
372cc597 SS |
774 | if (!rx_blocks->rxds) |
775 | return -ENOMEM; | |
4f870320 | 776 | mem_allocated += size; |
d44570e4 | 777 | for (l = 0; l < rxd_count[nic->rxd_mode]; l++) { |
da6971d8 AR |
778 | rx_blocks->rxds[l].virt_addr = |
779 | rx_blocks->block_virt_addr + | |
780 | (rxd_size[nic->rxd_mode] * l); | |
781 | rx_blocks->rxds[l].dma_addr = | |
782 | rx_blocks->block_dma_addr + | |
783 | (rxd_size[nic->rxd_mode] * l); | |
784 | } | |
1da177e4 LT |
785 | } |
786 | /* Interlinking all Rx Blocks */ | |
787 | for (j = 0; j < blk_cnt; j++) { | |
13d866a9 JP |
788 | int next = (j + 1) % blk_cnt; |
789 | tmp_v_addr = ring->rx_blocks[j].block_virt_addr; | |
790 | tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr; | |
791 | tmp_p_addr = ring->rx_blocks[j].block_dma_addr; | |
792 | tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr; | |
1da177e4 | 793 | |
43d620c8 | 794 | pre_rxd_blk = tmp_v_addr; |
1da177e4 | 795 | pre_rxd_blk->reserved_2_pNext_RxD_block = |
d44570e4 | 796 | (unsigned long)tmp_v_addr_next; |
1da177e4 | 797 | pre_rxd_blk->pNext_RxD_Blk_physical = |
d44570e4 | 798 | (u64)tmp_p_addr_next; |
1da177e4 LT |
799 | } |
800 | } | |
6d517a27 | 801 | if (nic->rxd_mode == RXD_MODE_3B) { |
da6971d8 AR |
802 | /* |
803 | * Allocation of Storages for buffer addresses in 2BUFF mode | |
804 | * and the buffers as well. | |
805 | */ | |
806 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
807 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
808 | struct ring_info *ring = &mac_control->rings[i]; | |
809 | ||
810 | blk_cnt = rx_cfg->num_rxd / | |
d44570e4 | 811 | (rxd_count[nic->rxd_mode] + 1); |
4f870320 JP |
812 | size = sizeof(struct buffAdd *) * blk_cnt; |
813 | ring->ba = kmalloc(size, GFP_KERNEL); | |
13d866a9 | 814 | if (!ring->ba) |
1da177e4 | 815 | return -ENOMEM; |
4f870320 | 816 | mem_allocated += size; |
da6971d8 AR |
817 | for (j = 0; j < blk_cnt; j++) { |
818 | int k = 0; | |
4f870320 JP |
819 | |
820 | size = sizeof(struct buffAdd) * | |
821 | (rxd_count[nic->rxd_mode] + 1); | |
822 | ring->ba[j] = kmalloc(size, GFP_KERNEL); | |
13d866a9 | 823 | if (!ring->ba[j]) |
1da177e4 | 824 | return -ENOMEM; |
4f870320 | 825 | mem_allocated += size; |
da6971d8 | 826 | while (k != rxd_count[nic->rxd_mode]) { |
13d866a9 | 827 | ba = &ring->ba[j][k]; |
4f870320 JP |
828 | size = BUF0_LEN + ALIGN_SIZE; |
829 | ba->ba_0_org = kmalloc(size, GFP_KERNEL); | |
da6971d8 AR |
830 | if (!ba->ba_0_org) |
831 | return -ENOMEM; | |
4f870320 | 832 | mem_allocated += size; |
da6971d8 AR |
833 | tmp = (unsigned long)ba->ba_0_org; |
834 | tmp += ALIGN_SIZE; | |
d44570e4 JP |
835 | tmp &= ~((unsigned long)ALIGN_SIZE); |
836 | ba->ba_0 = (void *)tmp; | |
da6971d8 | 837 | |
4f870320 JP |
838 | size = BUF1_LEN + ALIGN_SIZE; |
839 | ba->ba_1_org = kmalloc(size, GFP_KERNEL); | |
da6971d8 AR |
840 | if (!ba->ba_1_org) |
841 | return -ENOMEM; | |
4f870320 | 842 | mem_allocated += size; |
d44570e4 | 843 | tmp = (unsigned long)ba->ba_1_org; |
da6971d8 | 844 | tmp += ALIGN_SIZE; |
d44570e4 JP |
845 | tmp &= ~((unsigned long)ALIGN_SIZE); |
846 | ba->ba_1 = (void *)tmp; | |
da6971d8 AR |
847 | k++; |
848 | } | |
1da177e4 LT |
849 | } |
850 | } | |
851 | } | |
1da177e4 LT |
852 | |
853 | /* Allocation and initialization of Statistics block */ | |
1ee6dd77 | 854 | size = sizeof(struct stat_block); |
d44570e4 JP |
855 | mac_control->stats_mem = |
856 | pci_alloc_consistent(nic->pdev, size, | |
857 | &mac_control->stats_mem_phy); | |
1da177e4 LT |
858 | |
859 | if (!mac_control->stats_mem) { | |
20346722 | 860 | /* |
861 | * In case of failure, free_shared_mem() is called, which | |
862 | * should free any memory that was alloced till the | |
1da177e4 LT |
863 | * failure happened. |
864 | */ | |
865 | return -ENOMEM; | |
866 | } | |
491976b2 | 867 | mem_allocated += size; |
1da177e4 LT |
868 | mac_control->stats_mem_sz = size; |
869 | ||
870 | tmp_v_addr = mac_control->stats_mem; | |
43d620c8 | 871 | mac_control->stats_info = tmp_v_addr; |
1da177e4 | 872 | memset(tmp_v_addr, 0, size); |
3a22813a BL |
873 | DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n", |
874 | dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr); | |
491976b2 | 875 | mac_control->stats_info->sw_stat.mem_allocated += mem_allocated; |
1da177e4 LT |
876 | return SUCCESS; |
877 | } | |
878 | ||
20346722 | 879 | /** |
880 | * free_shared_mem - Free the allocated Memory | |
1da177e4 LT |
881 | * @nic: Device private variable. |
882 | * Description: This function is to free all memory locations allocated by | |
883 | * the init_shared_mem() function and return it to the kernel. | |
884 | */ | |
885 | ||
886 | static void free_shared_mem(struct s2io_nic *nic) | |
887 | { | |
888 | int i, j, blk_cnt, size; | |
889 | void *tmp_v_addr; | |
890 | dma_addr_t tmp_p_addr; | |
1da177e4 | 891 | int lst_size, lst_per_page; |
8910b49f | 892 | struct net_device *dev; |
491976b2 | 893 | int page_num = 0; |
ffb5df6c JP |
894 | struct config_param *config; |
895 | struct mac_info *mac_control; | |
896 | struct stat_block *stats; | |
897 | struct swStat *swstats; | |
1da177e4 LT |
898 | |
899 | if (!nic) | |
900 | return; | |
901 | ||
8910b49f MG |
902 | dev = nic->dev; |
903 | ||
1da177e4 | 904 | config = &nic->config; |
ffb5df6c JP |
905 | mac_control = &nic->mac_control; |
906 | stats = mac_control->stats_info; | |
907 | swstats = &stats->sw_stat; | |
1da177e4 | 908 | |
d44570e4 | 909 | lst_size = sizeof(struct TxD) * config->max_txds; |
1da177e4 LT |
910 | lst_per_page = PAGE_SIZE / lst_size; |
911 | ||
912 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
913 | struct fifo_info *fifo = &mac_control->fifos[i]; |
914 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
915 | ||
916 | page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page); | |
1da177e4 LT |
917 | for (j = 0; j < page_num; j++) { |
918 | int mem_blks = (j * lst_per_page); | |
13d866a9 JP |
919 | struct list_info_hold *fli; |
920 | ||
921 | if (!fifo->list_info) | |
6aa20a22 | 922 | return; |
13d866a9 JP |
923 | |
924 | fli = &fifo->list_info[mem_blks]; | |
925 | if (!fli->list_virt_addr) | |
1da177e4 LT |
926 | break; |
927 | pci_free_consistent(nic->pdev, PAGE_SIZE, | |
13d866a9 JP |
928 | fli->list_virt_addr, |
929 | fli->list_phy_addr); | |
ffb5df6c | 930 | swstats->mem_freed += PAGE_SIZE; |
1da177e4 | 931 | } |
776bd20f | 932 | /* If we got a zero DMA address during allocation, |
933 | * free the page now | |
934 | */ | |
935 | if (mac_control->zerodma_virt_addr) { | |
936 | pci_free_consistent(nic->pdev, PAGE_SIZE, | |
937 | mac_control->zerodma_virt_addr, | |
938 | (dma_addr_t)0); | |
6aa20a22 | 939 | DBG_PRINT(INIT_DBG, |
9e39f7c5 JP |
940 | "%s: Freeing TxDL with zero DMA address. " |
941 | "Virtual address %p\n", | |
942 | dev->name, mac_control->zerodma_virt_addr); | |
ffb5df6c | 943 | swstats->mem_freed += PAGE_SIZE; |
776bd20f | 944 | } |
13d866a9 | 945 | kfree(fifo->list_info); |
82c2d023 | 946 | swstats->mem_freed += tx_cfg->fifo_len * |
d44570e4 | 947 | sizeof(struct list_info_hold); |
1da177e4 LT |
948 | } |
949 | ||
1da177e4 | 950 | size = SIZE_OF_BLOCK; |
1da177e4 | 951 | for (i = 0; i < config->rx_ring_num; i++) { |
13d866a9 JP |
952 | struct ring_info *ring = &mac_control->rings[i]; |
953 | ||
954 | blk_cnt = ring->block_count; | |
1da177e4 | 955 | for (j = 0; j < blk_cnt; j++) { |
13d866a9 JP |
956 | tmp_v_addr = ring->rx_blocks[j].block_virt_addr; |
957 | tmp_p_addr = ring->rx_blocks[j].block_dma_addr; | |
1da177e4 LT |
958 | if (tmp_v_addr == NULL) |
959 | break; | |
960 | pci_free_consistent(nic->pdev, size, | |
961 | tmp_v_addr, tmp_p_addr); | |
ffb5df6c | 962 | swstats->mem_freed += size; |
13d866a9 | 963 | kfree(ring->rx_blocks[j].rxds); |
ffb5df6c JP |
964 | swstats->mem_freed += sizeof(struct rxd_info) * |
965 | rxd_count[nic->rxd_mode]; | |
1da177e4 LT |
966 | } |
967 | } | |
968 | ||
6d517a27 | 969 | if (nic->rxd_mode == RXD_MODE_3B) { |
da6971d8 AR |
970 | /* Freeing buffer storage addresses in 2BUFF mode. */ |
971 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
972 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
973 | struct ring_info *ring = &mac_control->rings[i]; | |
974 | ||
975 | blk_cnt = rx_cfg->num_rxd / | |
976 | (rxd_count[nic->rxd_mode] + 1); | |
da6971d8 AR |
977 | for (j = 0; j < blk_cnt; j++) { |
978 | int k = 0; | |
13d866a9 | 979 | if (!ring->ba[j]) |
da6971d8 AR |
980 | continue; |
981 | while (k != rxd_count[nic->rxd_mode]) { | |
13d866a9 | 982 | struct buffAdd *ba = &ring->ba[j][k]; |
da6971d8 | 983 | kfree(ba->ba_0_org); |
ffb5df6c JP |
984 | swstats->mem_freed += |
985 | BUF0_LEN + ALIGN_SIZE; | |
da6971d8 | 986 | kfree(ba->ba_1_org); |
ffb5df6c JP |
987 | swstats->mem_freed += |
988 | BUF1_LEN + ALIGN_SIZE; | |
da6971d8 AR |
989 | k++; |
990 | } | |
13d866a9 | 991 | kfree(ring->ba[j]); |
ffb5df6c JP |
992 | swstats->mem_freed += sizeof(struct buffAdd) * |
993 | (rxd_count[nic->rxd_mode] + 1); | |
1da177e4 | 994 | } |
13d866a9 | 995 | kfree(ring->ba); |
ffb5df6c JP |
996 | swstats->mem_freed += sizeof(struct buffAdd *) * |
997 | blk_cnt; | |
1da177e4 | 998 | } |
1da177e4 | 999 | } |
1da177e4 | 1000 | |
2fda096d | 1001 | for (i = 0; i < nic->config.tx_fifo_num; i++) { |
13d866a9 JP |
1002 | struct fifo_info *fifo = &mac_control->fifos[i]; |
1003 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; | |
1004 | ||
1005 | if (fifo->ufo_in_band_v) { | |
ffb5df6c JP |
1006 | swstats->mem_freed += tx_cfg->fifo_len * |
1007 | sizeof(u64); | |
13d866a9 | 1008 | kfree(fifo->ufo_in_band_v); |
2fda096d SR |
1009 | } |
1010 | } | |
1011 | ||
1da177e4 | 1012 | if (mac_control->stats_mem) { |
ffb5df6c | 1013 | swstats->mem_freed += mac_control->stats_mem_sz; |
1da177e4 LT |
1014 | pci_free_consistent(nic->pdev, |
1015 | mac_control->stats_mem_sz, | |
1016 | mac_control->stats_mem, | |
1017 | mac_control->stats_mem_phy); | |
491976b2 | 1018 | } |
1da177e4 LT |
1019 | } |
1020 | ||
541ae68f | 1021 | /** |
1022 | * s2io_verify_pci_mode - | |
1023 | */ | |
1024 | ||
1ee6dd77 | 1025 | static int s2io_verify_pci_mode(struct s2io_nic *nic) |
541ae68f | 1026 | { |
1ee6dd77 | 1027 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
541ae68f | 1028 | register u64 val64 = 0; |
1029 | int mode; | |
1030 | ||
1031 | val64 = readq(&bar0->pci_mode); | |
1032 | mode = (u8)GET_PCI_MODE(val64); | |
1033 | ||
d44570e4 | 1034 | if (val64 & PCI_MODE_UNKNOWN_MODE) |
541ae68f | 1035 | return -1; /* Unknown PCI mode */ |
1036 | return mode; | |
1037 | } | |
1038 | ||
c92ca04b AR |
1039 | #define NEC_VENID 0x1033 |
1040 | #define NEC_DEVID 0x0125 | |
1041 | static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev) | |
1042 | { | |
1043 | struct pci_dev *tdev = NULL; | |
26d36b64 AC |
1044 | while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) { |
1045 | if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) { | |
7ad62dbc | 1046 | if (tdev->bus == s2io_pdev->bus->parent) { |
26d36b64 | 1047 | pci_dev_put(tdev); |
c92ca04b | 1048 | return 1; |
7ad62dbc | 1049 | } |
c92ca04b AR |
1050 | } |
1051 | } | |
1052 | return 0; | |
1053 | } | |
541ae68f | 1054 | |
7b32a312 | 1055 | static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266}; |
541ae68f | 1056 | /** |
1057 | * s2io_print_pci_mode - | |
1058 | */ | |
1ee6dd77 | 1059 | static int s2io_print_pci_mode(struct s2io_nic *nic) |
541ae68f | 1060 | { |
1ee6dd77 | 1061 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
541ae68f | 1062 | register u64 val64 = 0; |
1063 | int mode; | |
1064 | struct config_param *config = &nic->config; | |
9e39f7c5 | 1065 | const char *pcimode; |
541ae68f | 1066 | |
1067 | val64 = readq(&bar0->pci_mode); | |
1068 | mode = (u8)GET_PCI_MODE(val64); | |
1069 | ||
d44570e4 | 1070 | if (val64 & PCI_MODE_UNKNOWN_MODE) |
541ae68f | 1071 | return -1; /* Unknown PCI mode */ |
1072 | ||
c92ca04b AR |
1073 | config->bus_speed = bus_speed[mode]; |
1074 | ||
1075 | if (s2io_on_nec_bridge(nic->pdev)) { | |
1076 | DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n", | |
d44570e4 | 1077 | nic->dev->name); |
c92ca04b AR |
1078 | return mode; |
1079 | } | |
1080 | ||
d44570e4 JP |
1081 | switch (mode) { |
1082 | case PCI_MODE_PCI_33: | |
9e39f7c5 | 1083 | pcimode = "33MHz PCI bus"; |
d44570e4 JP |
1084 | break; |
1085 | case PCI_MODE_PCI_66: | |
9e39f7c5 | 1086 | pcimode = "66MHz PCI bus"; |
d44570e4 JP |
1087 | break; |
1088 | case PCI_MODE_PCIX_M1_66: | |
9e39f7c5 | 1089 | pcimode = "66MHz PCIX(M1) bus"; |
d44570e4 JP |
1090 | break; |
1091 | case PCI_MODE_PCIX_M1_100: | |
9e39f7c5 | 1092 | pcimode = "100MHz PCIX(M1) bus"; |
d44570e4 JP |
1093 | break; |
1094 | case PCI_MODE_PCIX_M1_133: | |
9e39f7c5 | 1095 | pcimode = "133MHz PCIX(M1) bus"; |
d44570e4 JP |
1096 | break; |
1097 | case PCI_MODE_PCIX_M2_66: | |
9e39f7c5 | 1098 | pcimode = "133MHz PCIX(M2) bus"; |
d44570e4 JP |
1099 | break; |
1100 | case PCI_MODE_PCIX_M2_100: | |
9e39f7c5 | 1101 | pcimode = "200MHz PCIX(M2) bus"; |
d44570e4 JP |
1102 | break; |
1103 | case PCI_MODE_PCIX_M2_133: | |
9e39f7c5 | 1104 | pcimode = "266MHz PCIX(M2) bus"; |
d44570e4 JP |
1105 | break; |
1106 | default: | |
9e39f7c5 JP |
1107 | pcimode = "unsupported bus!"; |
1108 | mode = -1; | |
541ae68f | 1109 | } |
1110 | ||
9e39f7c5 JP |
1111 | DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n", |
1112 | nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode); | |
1113 | ||
541ae68f | 1114 | return mode; |
1115 | } | |
1116 | ||
b7c5678f RV |
1117 | /** |
1118 | * init_tti - Initialization transmit traffic interrupt scheme | |
1119 | * @nic: device private variable | |
1120 | * @link: link status (UP/DOWN) used to enable/disable continuous | |
1121 | * transmit interrupts | |
1122 | * Description: The function configures transmit traffic interrupts | |
1123 | * Return Value: SUCCESS on success and | |
1124 | * '-1' on failure | |
1125 | */ | |
1126 | ||
0d66afe7 | 1127 | static int init_tti(struct s2io_nic *nic, int link) |
b7c5678f RV |
1128 | { |
1129 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | |
1130 | register u64 val64 = 0; | |
1131 | int i; | |
ffb5df6c | 1132 | struct config_param *config = &nic->config; |
b7c5678f RV |
1133 | |
1134 | for (i = 0; i < config->tx_fifo_num; i++) { | |
1135 | /* | |
1136 | * TTI Initialization. Default Tx timer gets us about | |
1137 | * 250 interrupts per sec. Continuous interrupts are enabled | |
1138 | * by default. | |
1139 | */ | |
1140 | if (nic->device_type == XFRAME_II_DEVICE) { | |
1141 | int count = (nic->config.bus_speed * 125)/2; | |
1142 | val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count); | |
1143 | } else | |
1144 | val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078); | |
1145 | ||
1146 | val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) | | |
d44570e4 JP |
1147 | TTI_DATA1_MEM_TX_URNG_B(0x10) | |
1148 | TTI_DATA1_MEM_TX_URNG_C(0x30) | | |
1149 | TTI_DATA1_MEM_TX_TIMER_AC_EN; | |
ac731ab6 SH |
1150 | if (i == 0) |
1151 | if (use_continuous_tx_intrs && (link == LINK_UP)) | |
1152 | val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN; | |
b7c5678f RV |
1153 | writeq(val64, &bar0->tti_data1_mem); |
1154 | ||
ac731ab6 SH |
1155 | if (nic->config.intr_type == MSI_X) { |
1156 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | | |
1157 | TTI_DATA2_MEM_TX_UFC_B(0x100) | | |
1158 | TTI_DATA2_MEM_TX_UFC_C(0x200) | | |
1159 | TTI_DATA2_MEM_TX_UFC_D(0x300); | |
1160 | } else { | |
1161 | if ((nic->config.tx_steering_type == | |
d44570e4 JP |
1162 | TX_DEFAULT_STEERING) && |
1163 | (config->tx_fifo_num > 1) && | |
1164 | (i >= nic->udp_fifo_idx) && | |
1165 | (i < (nic->udp_fifo_idx + | |
1166 | nic->total_udp_fifos))) | |
ac731ab6 SH |
1167 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) | |
1168 | TTI_DATA2_MEM_TX_UFC_B(0x80) | | |
1169 | TTI_DATA2_MEM_TX_UFC_C(0x100) | | |
1170 | TTI_DATA2_MEM_TX_UFC_D(0x120); | |
1171 | else | |
1172 | val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) | | |
1173 | TTI_DATA2_MEM_TX_UFC_B(0x20) | | |
1174 | TTI_DATA2_MEM_TX_UFC_C(0x40) | | |
1175 | TTI_DATA2_MEM_TX_UFC_D(0x80); | |
1176 | } | |
b7c5678f RV |
1177 | |
1178 | writeq(val64, &bar0->tti_data2_mem); | |
1179 | ||
d44570e4 JP |
1180 | val64 = TTI_CMD_MEM_WE | |
1181 | TTI_CMD_MEM_STROBE_NEW_CMD | | |
1182 | TTI_CMD_MEM_OFFSET(i); | |
b7c5678f RV |
1183 | writeq(val64, &bar0->tti_command_mem); |
1184 | ||
1185 | if (wait_for_cmd_complete(&bar0->tti_command_mem, | |
d44570e4 JP |
1186 | TTI_CMD_MEM_STROBE_NEW_CMD, |
1187 | S2IO_BIT_RESET) != SUCCESS) | |
b7c5678f RV |
1188 | return FAILURE; |
1189 | } | |
1190 | ||
1191 | return SUCCESS; | |
1192 | } | |
1193 | ||
20346722 | 1194 | /** |
1195 | * init_nic - Initialization of hardware | |
b7c5678f | 1196 | * @nic: device private variable |
20346722 | 1197 | * Description: The function sequentially configures every block |
1198 | * of the H/W from their reset values. | |
1199 | * Return Value: SUCCESS on success and | |
1da177e4 LT |
1200 | * '-1' on failure (endian settings incorrect). |
1201 | */ | |
1202 | ||
1203 | static int init_nic(struct s2io_nic *nic) | |
1204 | { | |
1ee6dd77 | 1205 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1da177e4 LT |
1206 | struct net_device *dev = nic->dev; |
1207 | register u64 val64 = 0; | |
1208 | void __iomem *add; | |
1209 | u32 time; | |
1210 | int i, j; | |
c92ca04b | 1211 | int dtx_cnt = 0; |
1da177e4 | 1212 | unsigned long long mem_share; |
20346722 | 1213 | int mem_size; |
ffb5df6c JP |
1214 | struct config_param *config = &nic->config; |
1215 | struct mac_info *mac_control = &nic->mac_control; | |
1da177e4 | 1216 | |
5e25b9dd | 1217 | /* to set the swapper controle on the card */ |
d44570e4 JP |
1218 | if (s2io_set_swapper(nic)) { |
1219 | DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n"); | |
9f74ffde | 1220 | return -EIO; |
1da177e4 LT |
1221 | } |
1222 | ||
541ae68f | 1223 | /* |
1224 | * Herc requires EOI to be removed from reset before XGXS, so.. | |
1225 | */ | |
1226 | if (nic->device_type & XFRAME_II_DEVICE) { | |
1227 | val64 = 0xA500000000ULL; | |
1228 | writeq(val64, &bar0->sw_reset); | |
1229 | msleep(500); | |
1230 | val64 = readq(&bar0->sw_reset); | |
1231 | } | |
1232 | ||
1da177e4 LT |
1233 | /* Remove XGXS from reset state */ |
1234 | val64 = 0; | |
1235 | writeq(val64, &bar0->sw_reset); | |
1da177e4 | 1236 | msleep(500); |
20346722 | 1237 | val64 = readq(&bar0->sw_reset); |
1da177e4 | 1238 | |
7962024e SH |
1239 | /* Ensure that it's safe to access registers by checking |
1240 | * RIC_RUNNING bit is reset. Check is valid only for XframeII. | |
1241 | */ | |
1242 | if (nic->device_type == XFRAME_II_DEVICE) { | |
1243 | for (i = 0; i < 50; i++) { | |
1244 | val64 = readq(&bar0->adapter_status); | |
1245 | if (!(val64 & ADAPTER_STATUS_RIC_RUNNING)) | |
1246 | break; | |
1247 | msleep(10); | |
1248 | } | |
1249 | if (i == 50) | |
1250 | return -ENODEV; | |
1251 | } | |
1252 | ||
1da177e4 LT |
1253 | /* Enable Receiving broadcasts */ |
1254 | add = &bar0->mac_cfg; | |
1255 | val64 = readq(&bar0->mac_cfg); | |
1256 | val64 |= MAC_RMAC_BCAST_ENABLE; | |
1257 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
d44570e4 | 1258 | writel((u32)val64, add); |
1da177e4 LT |
1259 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); |
1260 | writel((u32) (val64 >> 32), (add + 4)); | |
1261 | ||
1262 | /* Read registers in all blocks */ | |
1263 | val64 = readq(&bar0->mac_int_mask); | |
1264 | val64 = readq(&bar0->mc_int_mask); | |
1265 | val64 = readq(&bar0->xgxs_int_mask); | |
1266 | ||
1267 | /* Set MTU */ | |
1268 | val64 = dev->mtu; | |
1269 | writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); | |
1270 | ||
541ae68f | 1271 | if (nic->device_type & XFRAME_II_DEVICE) { |
1272 | while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) { | |
303bcb4b | 1273 | SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt], |
1da177e4 | 1274 | &bar0->dtx_control, UF); |
541ae68f | 1275 | if (dtx_cnt & 0x1) |
1276 | msleep(1); /* Necessary!! */ | |
1da177e4 LT |
1277 | dtx_cnt++; |
1278 | } | |
541ae68f | 1279 | } else { |
c92ca04b AR |
1280 | while (xena_dtx_cfg[dtx_cnt] != END_SIGN) { |
1281 | SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt], | |
1282 | &bar0->dtx_control, UF); | |
1283 | val64 = readq(&bar0->dtx_control); | |
1284 | dtx_cnt++; | |
1da177e4 LT |
1285 | } |
1286 | } | |
1287 | ||
1288 | /* Tx DMA Initialization */ | |
1289 | val64 = 0; | |
1290 | writeq(val64, &bar0->tx_fifo_partition_0); | |
1291 | writeq(val64, &bar0->tx_fifo_partition_1); | |
1292 | writeq(val64, &bar0->tx_fifo_partition_2); | |
1293 | writeq(val64, &bar0->tx_fifo_partition_3); | |
1294 | ||
1da177e4 | 1295 | for (i = 0, j = 0; i < config->tx_fifo_num; i++) { |
13d866a9 JP |
1296 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
1297 | ||
1298 | val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) | | |
1299 | vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3); | |
1da177e4 LT |
1300 | |
1301 | if (i == (config->tx_fifo_num - 1)) { | |
1302 | if (i % 2 == 0) | |
1303 | i++; | |
1304 | } | |
1305 | ||
1306 | switch (i) { | |
1307 | case 1: | |
1308 | writeq(val64, &bar0->tx_fifo_partition_0); | |
1309 | val64 = 0; | |
b7c5678f | 1310 | j = 0; |
1da177e4 LT |
1311 | break; |
1312 | case 3: | |
1313 | writeq(val64, &bar0->tx_fifo_partition_1); | |
1314 | val64 = 0; | |
b7c5678f | 1315 | j = 0; |
1da177e4 LT |
1316 | break; |
1317 | case 5: | |
1318 | writeq(val64, &bar0->tx_fifo_partition_2); | |
1319 | val64 = 0; | |
b7c5678f | 1320 | j = 0; |
1da177e4 LT |
1321 | break; |
1322 | case 7: | |
1323 | writeq(val64, &bar0->tx_fifo_partition_3); | |
b7c5678f RV |
1324 | val64 = 0; |
1325 | j = 0; | |
1326 | break; | |
1327 | default: | |
1328 | j++; | |
1da177e4 LT |
1329 | break; |
1330 | } | |
1331 | } | |
1332 | ||
5e25b9dd | 1333 | /* |
1334 | * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug | |
1335 | * SXE-008 TRANSMIT DMA ARBITRATION ISSUE. | |
1336 | */ | |
d44570e4 | 1337 | if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4)) |
5e25b9dd | 1338 | writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); |
1339 | ||
1da177e4 LT |
1340 | val64 = readq(&bar0->tx_fifo_partition_0); |
1341 | DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n", | |
d44570e4 | 1342 | &bar0->tx_fifo_partition_0, (unsigned long long)val64); |
1da177e4 | 1343 | |
20346722 | 1344 | /* |
1345 | * Initialization of Tx_PA_CONFIG register to ignore packet | |
1da177e4 LT |
1346 | * integrity checking. |
1347 | */ | |
1348 | val64 = readq(&bar0->tx_pa_cfg); | |
d44570e4 JP |
1349 | val64 |= TX_PA_CFG_IGNORE_FRM_ERR | |
1350 | TX_PA_CFG_IGNORE_SNAP_OUI | | |
1351 | TX_PA_CFG_IGNORE_LLC_CTRL | | |
1352 | TX_PA_CFG_IGNORE_L2_ERR; | |
1da177e4 LT |
1353 | writeq(val64, &bar0->tx_pa_cfg); |
1354 | ||
1355 | /* Rx DMA intialization. */ | |
1356 | val64 = 0; | |
1357 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
1358 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
1359 | ||
1360 | val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3); | |
1da177e4 LT |
1361 | } |
1362 | writeq(val64, &bar0->rx_queue_priority); | |
1363 | ||
20346722 | 1364 | /* |
1365 | * Allocating equal share of memory to all the | |
1da177e4 LT |
1366 | * configured Rings. |
1367 | */ | |
1368 | val64 = 0; | |
541ae68f | 1369 | if (nic->device_type & XFRAME_II_DEVICE) |
1370 | mem_size = 32; | |
1371 | else | |
1372 | mem_size = 64; | |
1373 | ||
1da177e4 LT |
1374 | for (i = 0; i < config->rx_ring_num; i++) { |
1375 | switch (i) { | |
1376 | case 0: | |
20346722 | 1377 | mem_share = (mem_size / config->rx_ring_num + |
1378 | mem_size % config->rx_ring_num); | |
1da177e4 LT |
1379 | val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share); |
1380 | continue; | |
1381 | case 1: | |
20346722 | 1382 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1383 | val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share); |
1384 | continue; | |
1385 | case 2: | |
20346722 | 1386 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1387 | val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share); |
1388 | continue; | |
1389 | case 3: | |
20346722 | 1390 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1391 | val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share); |
1392 | continue; | |
1393 | case 4: | |
20346722 | 1394 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1395 | val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share); |
1396 | continue; | |
1397 | case 5: | |
20346722 | 1398 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1399 | val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share); |
1400 | continue; | |
1401 | case 6: | |
20346722 | 1402 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1403 | val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share); |
1404 | continue; | |
1405 | case 7: | |
20346722 | 1406 | mem_share = (mem_size / config->rx_ring_num); |
1da177e4 LT |
1407 | val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share); |
1408 | continue; | |
1409 | } | |
1410 | } | |
1411 | writeq(val64, &bar0->rx_queue_cfg); | |
1412 | ||
20346722 | 1413 | /* |
5e25b9dd | 1414 | * Filling Tx round robin registers |
b7c5678f | 1415 | * as per the number of FIFOs for equal scheduling priority |
1da177e4 | 1416 | */ |
5e25b9dd | 1417 | switch (config->tx_fifo_num) { |
1418 | case 1: | |
b7c5678f | 1419 | val64 = 0x0; |
5e25b9dd | 1420 | writeq(val64, &bar0->tx_w_round_robin_0); |
1421 | writeq(val64, &bar0->tx_w_round_robin_1); | |
1422 | writeq(val64, &bar0->tx_w_round_robin_2); | |
1423 | writeq(val64, &bar0->tx_w_round_robin_3); | |
1424 | writeq(val64, &bar0->tx_w_round_robin_4); | |
1425 | break; | |
1426 | case 2: | |
b7c5678f | 1427 | val64 = 0x0001000100010001ULL; |
5e25b9dd | 1428 | writeq(val64, &bar0->tx_w_round_robin_0); |
5e25b9dd | 1429 | writeq(val64, &bar0->tx_w_round_robin_1); |
5e25b9dd | 1430 | writeq(val64, &bar0->tx_w_round_robin_2); |
5e25b9dd | 1431 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1432 | val64 = 0x0001000100000000ULL; |
5e25b9dd | 1433 | writeq(val64, &bar0->tx_w_round_robin_4); |
1434 | break; | |
1435 | case 3: | |
b7c5678f | 1436 | val64 = 0x0001020001020001ULL; |
5e25b9dd | 1437 | writeq(val64, &bar0->tx_w_round_robin_0); |
b7c5678f | 1438 | val64 = 0x0200010200010200ULL; |
5e25b9dd | 1439 | writeq(val64, &bar0->tx_w_round_robin_1); |
b7c5678f | 1440 | val64 = 0x0102000102000102ULL; |
5e25b9dd | 1441 | writeq(val64, &bar0->tx_w_round_robin_2); |
b7c5678f | 1442 | val64 = 0x0001020001020001ULL; |
5e25b9dd | 1443 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1444 | val64 = 0x0200010200000000ULL; |
5e25b9dd | 1445 | writeq(val64, &bar0->tx_w_round_robin_4); |
1446 | break; | |
1447 | case 4: | |
b7c5678f | 1448 | val64 = 0x0001020300010203ULL; |
5e25b9dd | 1449 | writeq(val64, &bar0->tx_w_round_robin_0); |
5e25b9dd | 1450 | writeq(val64, &bar0->tx_w_round_robin_1); |
5e25b9dd | 1451 | writeq(val64, &bar0->tx_w_round_robin_2); |
5e25b9dd | 1452 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1453 | val64 = 0x0001020300000000ULL; |
5e25b9dd | 1454 | writeq(val64, &bar0->tx_w_round_robin_4); |
1455 | break; | |
1456 | case 5: | |
b7c5678f | 1457 | val64 = 0x0001020304000102ULL; |
5e25b9dd | 1458 | writeq(val64, &bar0->tx_w_round_robin_0); |
b7c5678f | 1459 | val64 = 0x0304000102030400ULL; |
5e25b9dd | 1460 | writeq(val64, &bar0->tx_w_round_robin_1); |
b7c5678f | 1461 | val64 = 0x0102030400010203ULL; |
5e25b9dd | 1462 | writeq(val64, &bar0->tx_w_round_robin_2); |
b7c5678f | 1463 | val64 = 0x0400010203040001ULL; |
5e25b9dd | 1464 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1465 | val64 = 0x0203040000000000ULL; |
5e25b9dd | 1466 | writeq(val64, &bar0->tx_w_round_robin_4); |
1467 | break; | |
1468 | case 6: | |
b7c5678f | 1469 | val64 = 0x0001020304050001ULL; |
5e25b9dd | 1470 | writeq(val64, &bar0->tx_w_round_robin_0); |
b7c5678f | 1471 | val64 = 0x0203040500010203ULL; |
5e25b9dd | 1472 | writeq(val64, &bar0->tx_w_round_robin_1); |
b7c5678f | 1473 | val64 = 0x0405000102030405ULL; |
5e25b9dd | 1474 | writeq(val64, &bar0->tx_w_round_robin_2); |
b7c5678f | 1475 | val64 = 0x0001020304050001ULL; |
5e25b9dd | 1476 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1477 | val64 = 0x0203040500000000ULL; |
5e25b9dd | 1478 | writeq(val64, &bar0->tx_w_round_robin_4); |
1479 | break; | |
1480 | case 7: | |
b7c5678f | 1481 | val64 = 0x0001020304050600ULL; |
5e25b9dd | 1482 | writeq(val64, &bar0->tx_w_round_robin_0); |
b7c5678f | 1483 | val64 = 0x0102030405060001ULL; |
5e25b9dd | 1484 | writeq(val64, &bar0->tx_w_round_robin_1); |
b7c5678f | 1485 | val64 = 0x0203040506000102ULL; |
5e25b9dd | 1486 | writeq(val64, &bar0->tx_w_round_robin_2); |
b7c5678f | 1487 | val64 = 0x0304050600010203ULL; |
5e25b9dd | 1488 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1489 | val64 = 0x0405060000000000ULL; |
5e25b9dd | 1490 | writeq(val64, &bar0->tx_w_round_robin_4); |
1491 | break; | |
1492 | case 8: | |
b7c5678f | 1493 | val64 = 0x0001020304050607ULL; |
5e25b9dd | 1494 | writeq(val64, &bar0->tx_w_round_robin_0); |
5e25b9dd | 1495 | writeq(val64, &bar0->tx_w_round_robin_1); |
5e25b9dd | 1496 | writeq(val64, &bar0->tx_w_round_robin_2); |
5e25b9dd | 1497 | writeq(val64, &bar0->tx_w_round_robin_3); |
b7c5678f | 1498 | val64 = 0x0001020300000000ULL; |
5e25b9dd | 1499 | writeq(val64, &bar0->tx_w_round_robin_4); |
1500 | break; | |
1501 | } | |
1502 | ||
b41477f3 | 1503 | /* Enable all configured Tx FIFO partitions */ |
5d3213cc AR |
1504 | val64 = readq(&bar0->tx_fifo_partition_0); |
1505 | val64 |= (TX_FIFO_PARTITION_EN); | |
1506 | writeq(val64, &bar0->tx_fifo_partition_0); | |
1507 | ||
5e25b9dd | 1508 | /* Filling the Rx round robin registers as per the |
0425b46a SH |
1509 | * number of Rings and steering based on QoS with |
1510 | * equal priority. | |
1511 | */ | |
5e25b9dd | 1512 | switch (config->rx_ring_num) { |
1513 | case 1: | |
0425b46a SH |
1514 | val64 = 0x0; |
1515 | writeq(val64, &bar0->rx_w_round_robin_0); | |
1516 | writeq(val64, &bar0->rx_w_round_robin_1); | |
1517 | writeq(val64, &bar0->rx_w_round_robin_2); | |
1518 | writeq(val64, &bar0->rx_w_round_robin_3); | |
1519 | writeq(val64, &bar0->rx_w_round_robin_4); | |
1520 | ||
5e25b9dd | 1521 | val64 = 0x8080808080808080ULL; |
1522 | writeq(val64, &bar0->rts_qos_steering); | |
1523 | break; | |
1524 | case 2: | |
0425b46a | 1525 | val64 = 0x0001000100010001ULL; |
5e25b9dd | 1526 | writeq(val64, &bar0->rx_w_round_robin_0); |
5e25b9dd | 1527 | writeq(val64, &bar0->rx_w_round_robin_1); |
5e25b9dd | 1528 | writeq(val64, &bar0->rx_w_round_robin_2); |
5e25b9dd | 1529 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1530 | val64 = 0x0001000100000000ULL; |
5e25b9dd | 1531 | writeq(val64, &bar0->rx_w_round_robin_4); |
1532 | ||
1533 | val64 = 0x8080808040404040ULL; | |
1534 | writeq(val64, &bar0->rts_qos_steering); | |
1535 | break; | |
1536 | case 3: | |
0425b46a | 1537 | val64 = 0x0001020001020001ULL; |
5e25b9dd | 1538 | writeq(val64, &bar0->rx_w_round_robin_0); |
0425b46a | 1539 | val64 = 0x0200010200010200ULL; |
5e25b9dd | 1540 | writeq(val64, &bar0->rx_w_round_robin_1); |
0425b46a | 1541 | val64 = 0x0102000102000102ULL; |
5e25b9dd | 1542 | writeq(val64, &bar0->rx_w_round_robin_2); |
0425b46a | 1543 | val64 = 0x0001020001020001ULL; |
5e25b9dd | 1544 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1545 | val64 = 0x0200010200000000ULL; |
5e25b9dd | 1546 | writeq(val64, &bar0->rx_w_round_robin_4); |
1547 | ||
1548 | val64 = 0x8080804040402020ULL; | |
1549 | writeq(val64, &bar0->rts_qos_steering); | |
1550 | break; | |
1551 | case 4: | |
0425b46a | 1552 | val64 = 0x0001020300010203ULL; |
5e25b9dd | 1553 | writeq(val64, &bar0->rx_w_round_robin_0); |
5e25b9dd | 1554 | writeq(val64, &bar0->rx_w_round_robin_1); |
5e25b9dd | 1555 | writeq(val64, &bar0->rx_w_round_robin_2); |
5e25b9dd | 1556 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1557 | val64 = 0x0001020300000000ULL; |
5e25b9dd | 1558 | writeq(val64, &bar0->rx_w_round_robin_4); |
1559 | ||
1560 | val64 = 0x8080404020201010ULL; | |
1561 | writeq(val64, &bar0->rts_qos_steering); | |
1562 | break; | |
1563 | case 5: | |
0425b46a | 1564 | val64 = 0x0001020304000102ULL; |
5e25b9dd | 1565 | writeq(val64, &bar0->rx_w_round_robin_0); |
0425b46a | 1566 | val64 = 0x0304000102030400ULL; |
5e25b9dd | 1567 | writeq(val64, &bar0->rx_w_round_robin_1); |
0425b46a | 1568 | val64 = 0x0102030400010203ULL; |
5e25b9dd | 1569 | writeq(val64, &bar0->rx_w_round_robin_2); |
0425b46a | 1570 | val64 = 0x0400010203040001ULL; |
5e25b9dd | 1571 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1572 | val64 = 0x0203040000000000ULL; |
5e25b9dd | 1573 | writeq(val64, &bar0->rx_w_round_robin_4); |
1574 | ||
1575 | val64 = 0x8080404020201008ULL; | |
1576 | writeq(val64, &bar0->rts_qos_steering); | |
1577 | break; | |
1578 | case 6: | |
0425b46a | 1579 | val64 = 0x0001020304050001ULL; |
5e25b9dd | 1580 | writeq(val64, &bar0->rx_w_round_robin_0); |
0425b46a | 1581 | val64 = 0x0203040500010203ULL; |
5e25b9dd | 1582 | writeq(val64, &bar0->rx_w_round_robin_1); |
0425b46a | 1583 | val64 = 0x0405000102030405ULL; |
5e25b9dd | 1584 | writeq(val64, &bar0->rx_w_round_robin_2); |
0425b46a | 1585 | val64 = 0x0001020304050001ULL; |
5e25b9dd | 1586 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1587 | val64 = 0x0203040500000000ULL; |
5e25b9dd | 1588 | writeq(val64, &bar0->rx_w_round_robin_4); |
1589 | ||
1590 | val64 = 0x8080404020100804ULL; | |
1591 | writeq(val64, &bar0->rts_qos_steering); | |
1592 | break; | |
1593 | case 7: | |
0425b46a | 1594 | val64 = 0x0001020304050600ULL; |
5e25b9dd | 1595 | writeq(val64, &bar0->rx_w_round_robin_0); |
0425b46a | 1596 | val64 = 0x0102030405060001ULL; |
5e25b9dd | 1597 | writeq(val64, &bar0->rx_w_round_robin_1); |
0425b46a | 1598 | val64 = 0x0203040506000102ULL; |
5e25b9dd | 1599 | writeq(val64, &bar0->rx_w_round_robin_2); |
0425b46a | 1600 | val64 = 0x0304050600010203ULL; |
5e25b9dd | 1601 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1602 | val64 = 0x0405060000000000ULL; |
5e25b9dd | 1603 | writeq(val64, &bar0->rx_w_round_robin_4); |
1604 | ||
1605 | val64 = 0x8080402010080402ULL; | |
1606 | writeq(val64, &bar0->rts_qos_steering); | |
1607 | break; | |
1608 | case 8: | |
0425b46a | 1609 | val64 = 0x0001020304050607ULL; |
5e25b9dd | 1610 | writeq(val64, &bar0->rx_w_round_robin_0); |
5e25b9dd | 1611 | writeq(val64, &bar0->rx_w_round_robin_1); |
5e25b9dd | 1612 | writeq(val64, &bar0->rx_w_round_robin_2); |
5e25b9dd | 1613 | writeq(val64, &bar0->rx_w_round_robin_3); |
0425b46a | 1614 | val64 = 0x0001020300000000ULL; |
5e25b9dd | 1615 | writeq(val64, &bar0->rx_w_round_robin_4); |
1616 | ||
1617 | val64 = 0x8040201008040201ULL; | |
1618 | writeq(val64, &bar0->rts_qos_steering); | |
1619 | break; | |
1620 | } | |
1da177e4 LT |
1621 | |
1622 | /* UDP Fix */ | |
1623 | val64 = 0; | |
20346722 | 1624 | for (i = 0; i < 8; i++) |
1da177e4 LT |
1625 | writeq(val64, &bar0->rts_frm_len_n[i]); |
1626 | ||
5e25b9dd | 1627 | /* Set the default rts frame length for the rings configured */ |
1628 | val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22); | |
1629 | for (i = 0 ; i < config->rx_ring_num ; i++) | |
1630 | writeq(val64, &bar0->rts_frm_len_n[i]); | |
1631 | ||
1632 | /* Set the frame length for the configured rings | |
1633 | * desired by the user | |
1634 | */ | |
1635 | for (i = 0; i < config->rx_ring_num; i++) { | |
1636 | /* If rts_frm_len[i] == 0 then it is assumed that user not | |
1637 | * specified frame length steering. | |
1638 | * If the user provides the frame length then program | |
1639 | * the rts_frm_len register for those values or else | |
1640 | * leave it as it is. | |
1641 | */ | |
1642 | if (rts_frm_len[i] != 0) { | |
1643 | writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]), | |
d44570e4 | 1644 | &bar0->rts_frm_len_n[i]); |
5e25b9dd | 1645 | } |
1646 | } | |
8a4bdbaa | 1647 | |
9fc93a41 SS |
1648 | /* Disable differentiated services steering logic */ |
1649 | for (i = 0; i < 64; i++) { | |
1650 | if (rts_ds_steer(nic, i, 0) == FAILURE) { | |
9e39f7c5 JP |
1651 | DBG_PRINT(ERR_DBG, |
1652 | "%s: rts_ds_steer failed on codepoint %d\n", | |
1653 | dev->name, i); | |
9f74ffde | 1654 | return -ENODEV; |
9fc93a41 SS |
1655 | } |
1656 | } | |
1657 | ||
20346722 | 1658 | /* Program statistics memory */ |
1da177e4 | 1659 | writeq(mac_control->stats_mem_phy, &bar0->stat_addr); |
1da177e4 | 1660 | |
541ae68f | 1661 | if (nic->device_type == XFRAME_II_DEVICE) { |
1662 | val64 = STAT_BC(0x320); | |
1663 | writeq(val64, &bar0->stat_byte_cnt); | |
1664 | } | |
1665 | ||
20346722 | 1666 | /* |
1da177e4 LT |
1667 | * Initializing the sampling rate for the device to calculate the |
1668 | * bandwidth utilization. | |
1669 | */ | |
1670 | val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) | | |
d44570e4 | 1671 | MAC_RX_LINK_UTIL_VAL(rmac_util_period); |
1da177e4 LT |
1672 | writeq(val64, &bar0->mac_link_util); |
1673 | ||
20346722 | 1674 | /* |
1675 | * Initializing the Transmit and Receive Traffic Interrupt | |
1da177e4 LT |
1676 | * Scheme. |
1677 | */ | |
1da177e4 | 1678 | |
b7c5678f RV |
1679 | /* Initialize TTI */ |
1680 | if (SUCCESS != init_tti(nic, nic->last_link_state)) | |
1681 | return -ENODEV; | |
1da177e4 | 1682 | |
8a4bdbaa SS |
1683 | /* RTI Initialization */ |
1684 | if (nic->device_type == XFRAME_II_DEVICE) { | |
541ae68f | 1685 | /* |
8a4bdbaa SS |
1686 | * Programmed to generate Apprx 500 Intrs per |
1687 | * second | |
1688 | */ | |
1689 | int count = (nic->config.bus_speed * 125)/4; | |
1690 | val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count); | |
1691 | } else | |
1692 | val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF); | |
1693 | val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) | | |
d44570e4 JP |
1694 | RTI_DATA1_MEM_RX_URNG_B(0x10) | |
1695 | RTI_DATA1_MEM_RX_URNG_C(0x30) | | |
1696 | RTI_DATA1_MEM_RX_TIMER_AC_EN; | |
8a4bdbaa SS |
1697 | |
1698 | writeq(val64, &bar0->rti_data1_mem); | |
1699 | ||
1700 | val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) | | |
1701 | RTI_DATA2_MEM_RX_UFC_B(0x2) ; | |
1702 | if (nic->config.intr_type == MSI_X) | |
d44570e4 JP |
1703 | val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | |
1704 | RTI_DATA2_MEM_RX_UFC_D(0x40)); | |
8a4bdbaa | 1705 | else |
d44570e4 JP |
1706 | val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | |
1707 | RTI_DATA2_MEM_RX_UFC_D(0x80)); | |
8a4bdbaa | 1708 | writeq(val64, &bar0->rti_data2_mem); |
1da177e4 | 1709 | |
8a4bdbaa | 1710 | for (i = 0; i < config->rx_ring_num; i++) { |
d44570e4 JP |
1711 | val64 = RTI_CMD_MEM_WE | |
1712 | RTI_CMD_MEM_STROBE_NEW_CMD | | |
1713 | RTI_CMD_MEM_OFFSET(i); | |
8a4bdbaa | 1714 | writeq(val64, &bar0->rti_command_mem); |
1da177e4 | 1715 | |
8a4bdbaa SS |
1716 | /* |
1717 | * Once the operation completes, the Strobe bit of the | |
1718 | * command register will be reset. We poll for this | |
1719 | * particular condition. We wait for a maximum of 500ms | |
1720 | * for the operation to complete, if it's not complete | |
1721 | * by then we return error. | |
1722 | */ | |
1723 | time = 0; | |
f957bcf0 | 1724 | while (true) { |
8a4bdbaa SS |
1725 | val64 = readq(&bar0->rti_command_mem); |
1726 | if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) | |
1727 | break; | |
b6e3f982 | 1728 | |
8a4bdbaa | 1729 | if (time > 10) { |
9e39f7c5 | 1730 | DBG_PRINT(ERR_DBG, "%s: RTI init failed\n", |
8a4bdbaa | 1731 | dev->name); |
9f74ffde | 1732 | return -ENODEV; |
b6e3f982 | 1733 | } |
8a4bdbaa SS |
1734 | time++; |
1735 | msleep(50); | |
1da177e4 | 1736 | } |
1da177e4 LT |
1737 | } |
1738 | ||
20346722 | 1739 | /* |
1740 | * Initializing proper values as Pause threshold into all | |
1da177e4 LT |
1741 | * the 8 Queues on Rx side. |
1742 | */ | |
1743 | writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); | |
1744 | writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); | |
1745 | ||
1746 | /* Disable RMAC PAD STRIPPING */ | |
509a2671 | 1747 | add = &bar0->mac_cfg; |
1da177e4 LT |
1748 | val64 = readq(&bar0->mac_cfg); |
1749 | val64 &= ~(MAC_CFG_RMAC_STRIP_PAD); | |
1750 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
1751 | writel((u32) (val64), add); | |
1752 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
1753 | writel((u32) (val64 >> 32), (add + 4)); | |
1754 | val64 = readq(&bar0->mac_cfg); | |
1755 | ||
7d3d0439 RA |
1756 | /* Enable FCS stripping by adapter */ |
1757 | add = &bar0->mac_cfg; | |
1758 | val64 = readq(&bar0->mac_cfg); | |
1759 | val64 |= MAC_CFG_RMAC_STRIP_FCS; | |
1760 | if (nic->device_type == XFRAME_II_DEVICE) | |
1761 | writeq(val64, &bar0->mac_cfg); | |
1762 | else { | |
1763 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
1764 | writel((u32) (val64), add); | |
1765 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
1766 | writel((u32) (val64 >> 32), (add + 4)); | |
1767 | } | |
1768 | ||
20346722 | 1769 | /* |
1770 | * Set the time value to be inserted in the pause frame | |
1da177e4 LT |
1771 | * generated by xena. |
1772 | */ | |
1773 | val64 = readq(&bar0->rmac_pause_cfg); | |
1774 | val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff)); | |
1775 | val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time); | |
1776 | writeq(val64, &bar0->rmac_pause_cfg); | |
1777 | ||
20346722 | 1778 | /* |
1da177e4 LT |
1779 | * Set the Threshold Limit for Generating the pause frame |
1780 | * If the amount of data in any Queue exceeds ratio of | |
1781 | * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256 | |
1782 | * pause frame is generated | |
1783 | */ | |
1784 | val64 = 0; | |
1785 | for (i = 0; i < 4; i++) { | |
d44570e4 JP |
1786 | val64 |= (((u64)0xFF00 | |
1787 | nic->mac_control.mc_pause_threshold_q0q3) | |
1788 | << (i * 2 * 8)); | |
1da177e4 LT |
1789 | } |
1790 | writeq(val64, &bar0->mc_pause_thresh_q0q3); | |
1791 | ||
1792 | val64 = 0; | |
1793 | for (i = 0; i < 4; i++) { | |
d44570e4 JP |
1794 | val64 |= (((u64)0xFF00 | |
1795 | nic->mac_control.mc_pause_threshold_q4q7) | |
1796 | << (i * 2 * 8)); | |
1da177e4 LT |
1797 | } |
1798 | writeq(val64, &bar0->mc_pause_thresh_q4q7); | |
1799 | ||
20346722 | 1800 | /* |
1801 | * TxDMA will stop Read request if the number of read split has | |
1da177e4 LT |
1802 | * exceeded the limit pointed by shared_splits |
1803 | */ | |
1804 | val64 = readq(&bar0->pic_control); | |
1805 | val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits); | |
1806 | writeq(val64, &bar0->pic_control); | |
1807 | ||
863c11a9 AR |
1808 | if (nic->config.bus_speed == 266) { |
1809 | writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout); | |
1810 | writeq(0x0, &bar0->read_retry_delay); | |
1811 | writeq(0x0, &bar0->write_retry_delay); | |
1812 | } | |
1813 | ||
541ae68f | 1814 | /* |
1815 | * Programming the Herc to split every write transaction | |
1816 | * that does not start on an ADB to reduce disconnects. | |
1817 | */ | |
1818 | if (nic->device_type == XFRAME_II_DEVICE) { | |
19a60522 SS |
1819 | val64 = FAULT_BEHAVIOUR | EXT_REQ_EN | |
1820 | MISC_LINK_STABILITY_PRD(3); | |
863c11a9 AR |
1821 | writeq(val64, &bar0->misc_control); |
1822 | val64 = readq(&bar0->pic_control2); | |
b7b5a128 | 1823 | val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15)); |
863c11a9 | 1824 | writeq(val64, &bar0->pic_control2); |
541ae68f | 1825 | } |
c92ca04b AR |
1826 | if (strstr(nic->product_name, "CX4")) { |
1827 | val64 = TMAC_AVG_IPG(0x17); | |
1828 | writeq(val64, &bar0->tmac_avg_ipg); | |
a371a07d | 1829 | } |
1830 | ||
1da177e4 LT |
1831 | return SUCCESS; |
1832 | } | |
a371a07d | 1833 | #define LINK_UP_DOWN_INTERRUPT 1 |
1834 | #define MAC_RMAC_ERR_TIMER 2 | |
1835 | ||
1ee6dd77 | 1836 | static int s2io_link_fault_indication(struct s2io_nic *nic) |
a371a07d | 1837 | { |
1838 | if (nic->device_type == XFRAME_II_DEVICE) | |
1839 | return LINK_UP_DOWN_INTERRUPT; | |
1840 | else | |
1841 | return MAC_RMAC_ERR_TIMER; | |
1842 | } | |
8116f3cf | 1843 | |
9caab458 SS |
1844 | /** |
1845 | * do_s2io_write_bits - update alarm bits in alarm register | |
1846 | * @value: alarm bits | |
1847 | * @flag: interrupt status | |
1848 | * @addr: address value | |
1849 | * Description: update alarm bits in alarm register | |
1850 | * Return Value: | |
1851 | * NONE. | |
1852 | */ | |
1853 | static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr) | |
1854 | { | |
1855 | u64 temp64; | |
1856 | ||
1857 | temp64 = readq(addr); | |
1858 | ||
d44570e4 JP |
1859 | if (flag == ENABLE_INTRS) |
1860 | temp64 &= ~((u64)value); | |
9caab458 | 1861 | else |
d44570e4 | 1862 | temp64 |= ((u64)value); |
9caab458 SS |
1863 | writeq(temp64, addr); |
1864 | } | |
1da177e4 | 1865 | |
43b7c451 | 1866 | static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag) |
9caab458 SS |
1867 | { |
1868 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | |
1869 | register u64 gen_int_mask = 0; | |
01e16faa | 1870 | u64 interruptible; |
9caab458 | 1871 | |
01e16faa | 1872 | writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask); |
9caab458 | 1873 | if (mask & TX_DMA_INTR) { |
9caab458 SS |
1874 | gen_int_mask |= TXDMA_INT_M; |
1875 | ||
1876 | do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT | | |
d44570e4 JP |
1877 | TXDMA_PCC_INT | TXDMA_TTI_INT | |
1878 | TXDMA_LSO_INT | TXDMA_TPA_INT | | |
1879 | TXDMA_SM_INT, flag, &bar0->txdma_int_mask); | |
9caab458 SS |
1880 | |
1881 | do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM | | |
d44570e4 JP |
1882 | PFC_MISC_0_ERR | PFC_MISC_1_ERR | |
1883 | PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag, | |
1884 | &bar0->pfc_err_mask); | |
9caab458 SS |
1885 | |
1886 | do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM | | |
d44570e4 JP |
1887 | TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR | |
1888 | TDA_PCIX_ERR, flag, &bar0->tda_err_mask); | |
9caab458 SS |
1889 | |
1890 | do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR | | |
d44570e4 JP |
1891 | PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM | |
1892 | PCC_N_SERR | PCC_6_COF_OV_ERR | | |
1893 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR | | |
1894 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR | | |
1895 | PCC_TXB_ECC_SG_ERR, | |
1896 | flag, &bar0->pcc_err_mask); | |
9caab458 SS |
1897 | |
1898 | do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR | | |
d44570e4 | 1899 | TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask); |
9caab458 SS |
1900 | |
1901 | do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT | | |
d44570e4 JP |
1902 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM | |
1903 | LSO6_SEND_OFLOW | LSO7_SEND_OFLOW, | |
1904 | flag, &bar0->lso_err_mask); | |
9caab458 SS |
1905 | |
1906 | do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP, | |
d44570e4 | 1907 | flag, &bar0->tpa_err_mask); |
9caab458 SS |
1908 | |
1909 | do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask); | |
9caab458 SS |
1910 | } |
1911 | ||
1912 | if (mask & TX_MAC_INTR) { | |
1913 | gen_int_mask |= TXMAC_INT_M; | |
1914 | do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag, | |
d44570e4 | 1915 | &bar0->mac_int_mask); |
9caab458 | 1916 | do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR | |
d44570e4 JP |
1917 | TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR | |
1918 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR, | |
1919 | flag, &bar0->mac_tmac_err_mask); | |
9caab458 SS |
1920 | } |
1921 | ||
1922 | if (mask & TX_XGXS_INTR) { | |
1923 | gen_int_mask |= TXXGXS_INT_M; | |
1924 | do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag, | |
d44570e4 | 1925 | &bar0->xgxs_int_mask); |
9caab458 | 1926 | do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR | |
d44570e4 JP |
1927 | TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR, |
1928 | flag, &bar0->xgxs_txgxs_err_mask); | |
9caab458 SS |
1929 | } |
1930 | ||
1931 | if (mask & RX_DMA_INTR) { | |
1932 | gen_int_mask |= RXDMA_INT_M; | |
1933 | do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M | | |
d44570e4 JP |
1934 | RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M, |
1935 | flag, &bar0->rxdma_int_mask); | |
9caab458 | 1936 | do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR | |
d44570e4 JP |
1937 | RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM | |
1938 | RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR | | |
1939 | RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask); | |
9caab458 | 1940 | do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn | |
d44570e4 JP |
1941 | PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn | |
1942 | PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag, | |
1943 | &bar0->prc_pcix_err_mask); | |
9caab458 | 1944 | do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR | |
d44570e4 JP |
1945 | RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag, |
1946 | &bar0->rpa_err_mask); | |
9caab458 | 1947 | do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR | |
d44570e4 JP |
1948 | RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM | |
1949 | RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR | | |
1950 | RDA_FRM_ECC_SG_ERR | | |
1951 | RDA_MISC_ERR|RDA_PCIX_ERR, | |
1952 | flag, &bar0->rda_err_mask); | |
9caab458 | 1953 | do_s2io_write_bits(RTI_SM_ERR_ALARM | |
d44570e4 JP |
1954 | RTI_ECC_SG_ERR | RTI_ECC_DB_ERR, |
1955 | flag, &bar0->rti_err_mask); | |
9caab458 SS |
1956 | } |
1957 | ||
1958 | if (mask & RX_MAC_INTR) { | |
1959 | gen_int_mask |= RXMAC_INT_M; | |
1960 | do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag, | |
d44570e4 JP |
1961 | &bar0->mac_int_mask); |
1962 | interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR | | |
1963 | RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR | | |
1964 | RMAC_DOUBLE_ECC_ERR); | |
01e16faa SH |
1965 | if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) |
1966 | interruptible |= RMAC_LINK_STATE_CHANGE_INT; | |
1967 | do_s2io_write_bits(interruptible, | |
d44570e4 | 1968 | flag, &bar0->mac_rmac_err_mask); |
9caab458 SS |
1969 | } |
1970 | ||
d44570e4 | 1971 | if (mask & RX_XGXS_INTR) { |
9caab458 SS |
1972 | gen_int_mask |= RXXGXS_INT_M; |
1973 | do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag, | |
d44570e4 | 1974 | &bar0->xgxs_int_mask); |
9caab458 | 1975 | do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag, |
d44570e4 | 1976 | &bar0->xgxs_rxgxs_err_mask); |
9caab458 SS |
1977 | } |
1978 | ||
1979 | if (mask & MC_INTR) { | |
1980 | gen_int_mask |= MC_INT_M; | |
d44570e4 JP |
1981 | do_s2io_write_bits(MC_INT_MASK_MC_INT, |
1982 | flag, &bar0->mc_int_mask); | |
9caab458 | 1983 | do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG | |
d44570e4 JP |
1984 | MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag, |
1985 | &bar0->mc_err_mask); | |
9caab458 SS |
1986 | } |
1987 | nic->general_int_mask = gen_int_mask; | |
1988 | ||
1989 | /* Remove this line when alarm interrupts are enabled */ | |
1990 | nic->general_int_mask = 0; | |
1991 | } | |
d44570e4 | 1992 | |
20346722 | 1993 | /** |
1994 | * en_dis_able_nic_intrs - Enable or Disable the interrupts | |
1da177e4 LT |
1995 | * @nic: device private variable, |
1996 | * @mask: A mask indicating which Intr block must be modified and, | |
1997 | * @flag: A flag indicating whether to enable or disable the Intrs. | |
1998 | * Description: This function will either disable or enable the interrupts | |
20346722 | 1999 | * depending on the flag argument. The mask argument can be used to |
2000 | * enable/disable any Intr block. | |
1da177e4 LT |
2001 | * Return Value: NONE. |
2002 | */ | |
2003 | ||
2004 | static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag) | |
2005 | { | |
1ee6dd77 | 2006 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
9caab458 SS |
2007 | register u64 temp64 = 0, intr_mask = 0; |
2008 | ||
2009 | intr_mask = nic->general_int_mask; | |
1da177e4 LT |
2010 | |
2011 | /* Top level interrupt classification */ | |
2012 | /* PIC Interrupts */ | |
9caab458 | 2013 | if (mask & TX_PIC_INTR) { |
1da177e4 | 2014 | /* Enable PIC Intrs in the general intr mask register */ |
9caab458 | 2015 | intr_mask |= TXPIC_INT_M; |
1da177e4 | 2016 | if (flag == ENABLE_INTRS) { |
20346722 | 2017 | /* |
a371a07d | 2018 | * If Hercules adapter enable GPIO otherwise |
b41477f3 | 2019 | * disable all PCIX, Flash, MDIO, IIC and GPIO |
20346722 | 2020 | * interrupts for now. |
2021 | * TODO | |
1da177e4 | 2022 | */ |
a371a07d | 2023 | if (s2io_link_fault_indication(nic) == |
d44570e4 | 2024 | LINK_UP_DOWN_INTERRUPT) { |
9caab458 | 2025 | do_s2io_write_bits(PIC_INT_GPIO, flag, |
d44570e4 | 2026 | &bar0->pic_int_mask); |
9caab458 | 2027 | do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag, |
d44570e4 | 2028 | &bar0->gpio_int_mask); |
9caab458 | 2029 | } else |
a371a07d | 2030 | writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); |
1da177e4 | 2031 | } else if (flag == DISABLE_INTRS) { |
20346722 | 2032 | /* |
2033 | * Disable PIC Intrs in the general | |
2034 | * intr mask register | |
1da177e4 LT |
2035 | */ |
2036 | writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); | |
1da177e4 LT |
2037 | } |
2038 | } | |
2039 | ||
1da177e4 LT |
2040 | /* Tx traffic interrupts */ |
2041 | if (mask & TX_TRAFFIC_INTR) { | |
9caab458 | 2042 | intr_mask |= TXTRAFFIC_INT_M; |
1da177e4 | 2043 | if (flag == ENABLE_INTRS) { |
20346722 | 2044 | /* |
1da177e4 | 2045 | * Enable all the Tx side interrupts |
20346722 | 2046 | * writing 0 Enables all 64 TX interrupt levels |
1da177e4 LT |
2047 | */ |
2048 | writeq(0x0, &bar0->tx_traffic_mask); | |
2049 | } else if (flag == DISABLE_INTRS) { | |
20346722 | 2050 | /* |
2051 | * Disable Tx Traffic Intrs in the general intr mask | |
1da177e4 LT |
2052 | * register. |
2053 | */ | |
2054 | writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); | |
1da177e4 LT |
2055 | } |
2056 | } | |
2057 | ||
2058 | /* Rx traffic interrupts */ | |
2059 | if (mask & RX_TRAFFIC_INTR) { | |
9caab458 | 2060 | intr_mask |= RXTRAFFIC_INT_M; |
1da177e4 | 2061 | if (flag == ENABLE_INTRS) { |
1da177e4 LT |
2062 | /* writing 0 Enables all 8 RX interrupt levels */ |
2063 | writeq(0x0, &bar0->rx_traffic_mask); | |
2064 | } else if (flag == DISABLE_INTRS) { | |
20346722 | 2065 | /* |
2066 | * Disable Rx Traffic Intrs in the general intr mask | |
1da177e4 LT |
2067 | * register. |
2068 | */ | |
2069 | writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); | |
1da177e4 LT |
2070 | } |
2071 | } | |
9caab458 SS |
2072 | |
2073 | temp64 = readq(&bar0->general_int_mask); | |
2074 | if (flag == ENABLE_INTRS) | |
d44570e4 | 2075 | temp64 &= ~((u64)intr_mask); |
9caab458 SS |
2076 | else |
2077 | temp64 = DISABLE_ALL_INTRS; | |
2078 | writeq(temp64, &bar0->general_int_mask); | |
2079 | ||
2080 | nic->general_int_mask = readq(&bar0->general_int_mask); | |
1da177e4 LT |
2081 | } |
2082 | ||
19a60522 SS |
2083 | /** |
2084 | * verify_pcc_quiescent- Checks for PCC quiescent state | |
2085 | * Return: 1 If PCC is quiescence | |
2086 | * 0 If PCC is not quiescence | |
2087 | */ | |
1ee6dd77 | 2088 | static int verify_pcc_quiescent(struct s2io_nic *sp, int flag) |
20346722 | 2089 | { |
19a60522 | 2090 | int ret = 0, herc; |
1ee6dd77 | 2091 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
19a60522 | 2092 | u64 val64 = readq(&bar0->adapter_status); |
8a4bdbaa | 2093 | |
19a60522 | 2094 | herc = (sp->device_type == XFRAME_II_DEVICE); |
20346722 | 2095 | |
f957bcf0 | 2096 | if (flag == false) { |
44c10138 | 2097 | if ((!herc && (sp->pdev->revision >= 4)) || herc) { |
19a60522 | 2098 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE)) |
5e25b9dd | 2099 | ret = 1; |
19a60522 SS |
2100 | } else { |
2101 | if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) | |
5e25b9dd | 2102 | ret = 1; |
20346722 | 2103 | } |
2104 | } else { | |
44c10138 | 2105 | if ((!herc && (sp->pdev->revision >= 4)) || herc) { |
5e25b9dd | 2106 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) == |
19a60522 | 2107 | ADAPTER_STATUS_RMAC_PCC_IDLE)) |
5e25b9dd | 2108 | ret = 1; |
5e25b9dd | 2109 | } else { |
2110 | if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) == | |
19a60522 | 2111 | ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE)) |
5e25b9dd | 2112 | ret = 1; |
20346722 | 2113 | } |
2114 | } | |
2115 | ||
2116 | return ret; | |
2117 | } | |
2118 | /** | |
2119 | * verify_xena_quiescence - Checks whether the H/W is ready | |
1da177e4 | 2120 | * Description: Returns whether the H/W is ready to go or not. Depending |
20346722 | 2121 | * on whether adapter enable bit was written or not the comparison |
1da177e4 LT |
2122 | * differs and the calling function passes the input argument flag to |
2123 | * indicate this. | |
20346722 | 2124 | * Return: 1 If xena is quiescence |
1da177e4 LT |
2125 | * 0 If Xena is not quiescence |
2126 | */ | |
2127 | ||
1ee6dd77 | 2128 | static int verify_xena_quiescence(struct s2io_nic *sp) |
1da177e4 | 2129 | { |
19a60522 | 2130 | int mode; |
1ee6dd77 | 2131 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
19a60522 SS |
2132 | u64 val64 = readq(&bar0->adapter_status); |
2133 | mode = s2io_verify_pci_mode(sp); | |
1da177e4 | 2134 | |
19a60522 | 2135 | if (!(val64 & ADAPTER_STATUS_TDMA_READY)) { |
9e39f7c5 | 2136 | DBG_PRINT(ERR_DBG, "TDMA is not ready!\n"); |
19a60522 SS |
2137 | return 0; |
2138 | } | |
2139 | if (!(val64 & ADAPTER_STATUS_RDMA_READY)) { | |
9e39f7c5 | 2140 | DBG_PRINT(ERR_DBG, "RDMA is not ready!\n"); |
19a60522 SS |
2141 | return 0; |
2142 | } | |
2143 | if (!(val64 & ADAPTER_STATUS_PFC_READY)) { | |
9e39f7c5 | 2144 | DBG_PRINT(ERR_DBG, "PFC is not ready!\n"); |
19a60522 SS |
2145 | return 0; |
2146 | } | |
2147 | if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) { | |
9e39f7c5 | 2148 | DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n"); |
19a60522 SS |
2149 | return 0; |
2150 | } | |
2151 | if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) { | |
9e39f7c5 | 2152 | DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n"); |
19a60522 SS |
2153 | return 0; |
2154 | } | |
2155 | if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) { | |
9e39f7c5 | 2156 | DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n"); |
19a60522 SS |
2157 | return 0; |
2158 | } | |
2159 | if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) { | |
9e39f7c5 | 2160 | DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n"); |
19a60522 SS |
2161 | return 0; |
2162 | } | |
2163 | if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) { | |
9e39f7c5 | 2164 | DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n"); |
19a60522 | 2165 | return 0; |
1da177e4 LT |
2166 | } |
2167 | ||
19a60522 SS |
2168 | /* |
2169 | * In PCI 33 mode, the P_PLL is not used, and therefore, | |
2170 | * the the P_PLL_LOCK bit in the adapter_status register will | |
2171 | * not be asserted. | |
2172 | */ | |
2173 | if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) && | |
d44570e4 JP |
2174 | sp->device_type == XFRAME_II_DEVICE && |
2175 | mode != PCI_MODE_PCI_33) { | |
9e39f7c5 | 2176 | DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n"); |
19a60522 SS |
2177 | return 0; |
2178 | } | |
2179 | if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) == | |
d44570e4 | 2180 | ADAPTER_STATUS_RC_PRC_QUIESCENT)) { |
9e39f7c5 | 2181 | DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n"); |
19a60522 SS |
2182 | return 0; |
2183 | } | |
2184 | return 1; | |
1da177e4 LT |
2185 | } |
2186 | ||
2187 | /** | |
2188 | * fix_mac_address - Fix for Mac addr problem on Alpha platforms | |
2189 | * @sp: Pointer to device specifc structure | |
20346722 | 2190 | * Description : |
1da177e4 LT |
2191 | * New procedure to clear mac address reading problems on Alpha platforms |
2192 | * | |
2193 | */ | |
2194 | ||
d44570e4 | 2195 | static void fix_mac_address(struct s2io_nic *sp) |
1da177e4 | 2196 | { |
1ee6dd77 | 2197 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
2198 | int i = 0; |
2199 | ||
2200 | while (fix_mac[i] != END_SIGN) { | |
2201 | writeq(fix_mac[i++], &bar0->gpio_control); | |
20346722 | 2202 | udelay(10); |
d83d282b | 2203 | (void) readq(&bar0->gpio_control); |
1da177e4 LT |
2204 | } |
2205 | } | |
2206 | ||
2207 | /** | |
20346722 | 2208 | * start_nic - Turns the device on |
1da177e4 | 2209 | * @nic : device private variable. |
20346722 | 2210 | * Description: |
2211 | * This function actually turns the device on. Before this function is | |
2212 | * called,all Registers are configured from their reset states | |
2213 | * and shared memory is allocated but the NIC is still quiescent. On | |
1da177e4 LT |
2214 | * calling this function, the device interrupts are cleared and the NIC is |
2215 | * literally switched on by writing into the adapter control register. | |
20346722 | 2216 | * Return Value: |
1da177e4 LT |
2217 | * SUCCESS on success and -1 on failure. |
2218 | */ | |
2219 | ||
2220 | static int start_nic(struct s2io_nic *nic) | |
2221 | { | |
1ee6dd77 | 2222 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1da177e4 LT |
2223 | struct net_device *dev = nic->dev; |
2224 | register u64 val64 = 0; | |
20346722 | 2225 | u16 subid, i; |
ffb5df6c JP |
2226 | struct config_param *config = &nic->config; |
2227 | struct mac_info *mac_control = &nic->mac_control; | |
1da177e4 LT |
2228 | |
2229 | /* PRC Initialization and configuration */ | |
2230 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
2231 | struct ring_info *ring = &mac_control->rings[i]; |
2232 | ||
d44570e4 | 2233 | writeq((u64)ring->rx_blocks[0].block_dma_addr, |
1da177e4 LT |
2234 | &bar0->prc_rxd0_n[i]); |
2235 | ||
2236 | val64 = readq(&bar0->prc_ctrl_n[i]); | |
da6971d8 AR |
2237 | if (nic->rxd_mode == RXD_MODE_1) |
2238 | val64 |= PRC_CTRL_RC_ENABLED; | |
2239 | else | |
2240 | val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3; | |
863c11a9 AR |
2241 | if (nic->device_type == XFRAME_II_DEVICE) |
2242 | val64 |= PRC_CTRL_GROUP_READS; | |
2243 | val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF); | |
2244 | val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000); | |
1da177e4 LT |
2245 | writeq(val64, &bar0->prc_ctrl_n[i]); |
2246 | } | |
2247 | ||
da6971d8 AR |
2248 | if (nic->rxd_mode == RXD_MODE_3B) { |
2249 | /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */ | |
2250 | val64 = readq(&bar0->rx_pa_cfg); | |
2251 | val64 |= RX_PA_CFG_IGNORE_L2_ERR; | |
2252 | writeq(val64, &bar0->rx_pa_cfg); | |
2253 | } | |
1da177e4 | 2254 | |
926930b2 SS |
2255 | if (vlan_tag_strip == 0) { |
2256 | val64 = readq(&bar0->rx_pa_cfg); | |
2257 | val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; | |
2258 | writeq(val64, &bar0->rx_pa_cfg); | |
cd0fce03 | 2259 | nic->vlan_strip_flag = 0; |
926930b2 SS |
2260 | } |
2261 | ||
20346722 | 2262 | /* |
1da177e4 LT |
2263 | * Enabling MC-RLDRAM. After enabling the device, we timeout |
2264 | * for around 100ms, which is approximately the time required | |
2265 | * for the device to be ready for operation. | |
2266 | */ | |
2267 | val64 = readq(&bar0->mc_rldram_mrs); | |
2268 | val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE; | |
2269 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); | |
2270 | val64 = readq(&bar0->mc_rldram_mrs); | |
2271 | ||
20346722 | 2272 | msleep(100); /* Delay by around 100 ms. */ |
1da177e4 LT |
2273 | |
2274 | /* Enabling ECC Protection. */ | |
2275 | val64 = readq(&bar0->adapter_control); | |
2276 | val64 &= ~ADAPTER_ECC_EN; | |
2277 | writeq(val64, &bar0->adapter_control); | |
2278 | ||
20346722 | 2279 | /* |
2280 | * Verify if the device is ready to be enabled, if so enable | |
1da177e4 LT |
2281 | * it. |
2282 | */ | |
2283 | val64 = readq(&bar0->adapter_status); | |
19a60522 | 2284 | if (!verify_xena_quiescence(nic)) { |
9e39f7c5 JP |
2285 | DBG_PRINT(ERR_DBG, "%s: device is not ready, " |
2286 | "Adapter status reads: 0x%llx\n", | |
2287 | dev->name, (unsigned long long)val64); | |
1da177e4 LT |
2288 | return FAILURE; |
2289 | } | |
2290 | ||
20346722 | 2291 | /* |
1da177e4 | 2292 | * With some switches, link might be already up at this point. |
20346722 | 2293 | * Because of this weird behavior, when we enable laser, |
2294 | * we may not get link. We need to handle this. We cannot | |
2295 | * figure out which switch is misbehaving. So we are forced to | |
2296 | * make a global change. | |
1da177e4 LT |
2297 | */ |
2298 | ||
2299 | /* Enabling Laser. */ | |
2300 | val64 = readq(&bar0->adapter_control); | |
2301 | val64 |= ADAPTER_EOI_TX_ON; | |
2302 | writeq(val64, &bar0->adapter_control); | |
2303 | ||
c92ca04b AR |
2304 | if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) { |
2305 | /* | |
25985edc | 2306 | * Dont see link state interrupts initially on some switches, |
c92ca04b AR |
2307 | * so directly scheduling the link state task here. |
2308 | */ | |
2309 | schedule_work(&nic->set_link_task); | |
2310 | } | |
1da177e4 LT |
2311 | /* SXE-002: Initialize link and activity LED */ |
2312 | subid = nic->pdev->subsystem_device; | |
541ae68f | 2313 | if (((subid & 0xFF) >= 0x07) && |
2314 | (nic->device_type == XFRAME_I_DEVICE)) { | |
1da177e4 LT |
2315 | val64 = readq(&bar0->gpio_control); |
2316 | val64 |= 0x0000800000000000ULL; | |
2317 | writeq(val64, &bar0->gpio_control); | |
2318 | val64 = 0x0411040400000000ULL; | |
509a2671 | 2319 | writeq(val64, (void __iomem *)bar0 + 0x2700); |
1da177e4 LT |
2320 | } |
2321 | ||
1da177e4 LT |
2322 | return SUCCESS; |
2323 | } | |
fed5eccd AR |
2324 | /** |
2325 | * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb | |
2326 | */ | |
d44570e4 JP |
2327 | static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, |
2328 | struct TxD *txdlp, int get_off) | |
fed5eccd | 2329 | { |
1ee6dd77 | 2330 | struct s2io_nic *nic = fifo_data->nic; |
fed5eccd | 2331 | struct sk_buff *skb; |
1ee6dd77 | 2332 | struct TxD *txds; |
fed5eccd AR |
2333 | u16 j, frg_cnt; |
2334 | ||
2335 | txds = txdlp; | |
2fda096d | 2336 | if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) { |
d44570e4 JP |
2337 | pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer, |
2338 | sizeof(u64), PCI_DMA_TODEVICE); | |
fed5eccd AR |
2339 | txds++; |
2340 | } | |
2341 | ||
d44570e4 | 2342 | skb = (struct sk_buff *)((unsigned long)txds->Host_Control); |
fed5eccd | 2343 | if (!skb) { |
1ee6dd77 | 2344 | memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds)); |
fed5eccd AR |
2345 | return NULL; |
2346 | } | |
d44570e4 | 2347 | pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer, |
e743d313 | 2348 | skb_headlen(skb), PCI_DMA_TODEVICE); |
fed5eccd AR |
2349 | frg_cnt = skb_shinfo(skb)->nr_frags; |
2350 | if (frg_cnt) { | |
2351 | txds++; | |
2352 | for (j = 0; j < frg_cnt; j++, txds++) { | |
9e903e08 | 2353 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; |
fed5eccd AR |
2354 | if (!txds->Buffer_Pointer) |
2355 | break; | |
d44570e4 JP |
2356 | pci_unmap_page(nic->pdev, |
2357 | (dma_addr_t)txds->Buffer_Pointer, | |
9e903e08 | 2358 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
fed5eccd AR |
2359 | } |
2360 | } | |
d44570e4 JP |
2361 | memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds)); |
2362 | return skb; | |
fed5eccd | 2363 | } |
1da177e4 | 2364 | |
20346722 | 2365 | /** |
2366 | * free_tx_buffers - Free all queued Tx buffers | |
1da177e4 | 2367 | * @nic : device private variable. |
20346722 | 2368 | * Description: |
1da177e4 | 2369 | * Free all queued Tx buffers. |
20346722 | 2370 | * Return Value: void |
d44570e4 | 2371 | */ |
1da177e4 LT |
2372 | |
2373 | static void free_tx_buffers(struct s2io_nic *nic) | |
2374 | { | |
2375 | struct net_device *dev = nic->dev; | |
2376 | struct sk_buff *skb; | |
1ee6dd77 | 2377 | struct TxD *txdp; |
1da177e4 | 2378 | int i, j; |
fed5eccd | 2379 | int cnt = 0; |
ffb5df6c JP |
2380 | struct config_param *config = &nic->config; |
2381 | struct mac_info *mac_control = &nic->mac_control; | |
2382 | struct stat_block *stats = mac_control->stats_info; | |
2383 | struct swStat *swstats = &stats->sw_stat; | |
1da177e4 LT |
2384 | |
2385 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
2386 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
2387 | struct fifo_info *fifo = &mac_control->fifos[i]; | |
2fda096d | 2388 | unsigned long flags; |
13d866a9 JP |
2389 | |
2390 | spin_lock_irqsave(&fifo->tx_lock, flags); | |
2391 | for (j = 0; j < tx_cfg->fifo_len; j++) { | |
43d620c8 | 2392 | txdp = fifo->list_info[j].list_virt_addr; |
fed5eccd AR |
2393 | skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j); |
2394 | if (skb) { | |
ffb5df6c | 2395 | swstats->mem_freed += skb->truesize; |
fed5eccd AR |
2396 | dev_kfree_skb(skb); |
2397 | cnt++; | |
1da177e4 | 2398 | } |
1da177e4 LT |
2399 | } |
2400 | DBG_PRINT(INTR_DBG, | |
9e39f7c5 | 2401 | "%s: forcibly freeing %d skbs on FIFO%d\n", |
1da177e4 | 2402 | dev->name, cnt, i); |
13d866a9 JP |
2403 | fifo->tx_curr_get_info.offset = 0; |
2404 | fifo->tx_curr_put_info.offset = 0; | |
2405 | spin_unlock_irqrestore(&fifo->tx_lock, flags); | |
1da177e4 LT |
2406 | } |
2407 | } | |
2408 | ||
20346722 | 2409 | /** |
2410 | * stop_nic - To stop the nic | |
1da177e4 | 2411 | * @nic ; device private variable. |
20346722 | 2412 | * Description: |
2413 | * This function does exactly the opposite of what the start_nic() | |
1da177e4 LT |
2414 | * function does. This function is called to stop the device. |
2415 | * Return Value: | |
2416 | * void. | |
2417 | */ | |
2418 | ||
2419 | static void stop_nic(struct s2io_nic *nic) | |
2420 | { | |
1ee6dd77 | 2421 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1da177e4 | 2422 | register u64 val64 = 0; |
5d3213cc | 2423 | u16 interruptible; |
1da177e4 LT |
2424 | |
2425 | /* Disable all interrupts */ | |
9caab458 | 2426 | en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS); |
e960fc5c | 2427 | interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; |
9caab458 | 2428 | interruptible |= TX_PIC_INTR; |
1da177e4 LT |
2429 | en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS); |
2430 | ||
5d3213cc AR |
2431 | /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */ |
2432 | val64 = readq(&bar0->adapter_control); | |
2433 | val64 &= ~(ADAPTER_CNTL_EN); | |
2434 | writeq(val64, &bar0->adapter_control); | |
1da177e4 LT |
2435 | } |
2436 | ||
20346722 | 2437 | /** |
2438 | * fill_rx_buffers - Allocates the Rx side skbs | |
0425b46a | 2439 | * @ring_info: per ring structure |
3f78d885 SH |
2440 | * @from_card_up: If this is true, we will map the buffer to get |
2441 | * the dma address for buf0 and buf1 to give it to the card. | |
2442 | * Else we will sync the already mapped buffer to give it to the card. | |
20346722 | 2443 | * Description: |
1da177e4 LT |
2444 | * The function allocates Rx side skbs and puts the physical |
2445 | * address of these buffers into the RxD buffer pointers, so that the NIC | |
2446 | * can DMA the received frame into these locations. | |
2447 | * The NIC supports 3 receive modes, viz | |
2448 | * 1. single buffer, | |
2449 | * 2. three buffer and | |
2450 | * 3. Five buffer modes. | |
20346722 | 2451 | * Each mode defines how many fragments the received frame will be split |
2452 | * up into by the NIC. The frame is split into L3 header, L4 Header, | |
1da177e4 LT |
2453 | * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself |
2454 | * is split into 3 fragments. As of now only single buffer mode is | |
2455 | * supported. | |
2456 | * Return Value: | |
2457 | * SUCCESS on success or an appropriate -ve value on failure. | |
2458 | */ | |
8d8bb39b | 2459 | static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring, |
d44570e4 | 2460 | int from_card_up) |
1da177e4 | 2461 | { |
1da177e4 | 2462 | struct sk_buff *skb; |
1ee6dd77 | 2463 | struct RxD_t *rxdp; |
0425b46a | 2464 | int off, size, block_no, block_no1; |
1da177e4 | 2465 | u32 alloc_tab = 0; |
20346722 | 2466 | u32 alloc_cnt; |
20346722 | 2467 | u64 tmp; |
1ee6dd77 | 2468 | struct buffAdd *ba; |
1ee6dd77 | 2469 | struct RxD_t *first_rxdp = NULL; |
363dc367 | 2470 | u64 Buffer0_ptr = 0, Buffer1_ptr = 0; |
0425b46a | 2471 | int rxd_index = 0; |
6d517a27 VP |
2472 | struct RxD1 *rxdp1; |
2473 | struct RxD3 *rxdp3; | |
ffb5df6c | 2474 | struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat; |
1da177e4 | 2475 | |
0425b46a | 2476 | alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left; |
1da177e4 | 2477 | |
0425b46a | 2478 | block_no1 = ring->rx_curr_get_info.block_index; |
1da177e4 | 2479 | while (alloc_tab < alloc_cnt) { |
0425b46a | 2480 | block_no = ring->rx_curr_put_info.block_index; |
1da177e4 | 2481 | |
0425b46a SH |
2482 | off = ring->rx_curr_put_info.offset; |
2483 | ||
2484 | rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr; | |
2485 | ||
2486 | rxd_index = off + 1; | |
2487 | if (block_no) | |
2488 | rxd_index += (block_no * ring->rxd_count); | |
da6971d8 | 2489 | |
7d2e3cb7 | 2490 | if ((block_no == block_no1) && |
d44570e4 JP |
2491 | (off == ring->rx_curr_get_info.offset) && |
2492 | (rxdp->Host_Control)) { | |
9e39f7c5 JP |
2493 | DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n", |
2494 | ring->dev->name); | |
1da177e4 LT |
2495 | goto end; |
2496 | } | |
0425b46a SH |
2497 | if (off && (off == ring->rxd_count)) { |
2498 | ring->rx_curr_put_info.block_index++; | |
2499 | if (ring->rx_curr_put_info.block_index == | |
d44570e4 | 2500 | ring->block_count) |
0425b46a SH |
2501 | ring->rx_curr_put_info.block_index = 0; |
2502 | block_no = ring->rx_curr_put_info.block_index; | |
2503 | off = 0; | |
2504 | ring->rx_curr_put_info.offset = off; | |
2505 | rxdp = ring->rx_blocks[block_no].block_virt_addr; | |
1da177e4 | 2506 | DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n", |
0425b46a SH |
2507 | ring->dev->name, rxdp); |
2508 | ||
1da177e4 | 2509 | } |
c9fcbf47 | 2510 | |
da6971d8 | 2511 | if ((rxdp->Control_1 & RXD_OWN_XENA) && |
d44570e4 JP |
2512 | ((ring->rxd_mode == RXD_MODE_3B) && |
2513 | (rxdp->Control_2 & s2BIT(0)))) { | |
0425b46a | 2514 | ring->rx_curr_put_info.offset = off; |
1da177e4 LT |
2515 | goto end; |
2516 | } | |
da6971d8 | 2517 | /* calculate size of skb based on ring mode */ |
d44570e4 JP |
2518 | size = ring->mtu + |
2519 | HEADER_ETHERNET_II_802_3_SIZE + | |
2520 | HEADER_802_2_SIZE + HEADER_SNAP_SIZE; | |
0425b46a | 2521 | if (ring->rxd_mode == RXD_MODE_1) |
da6971d8 | 2522 | size += NET_IP_ALIGN; |
da6971d8 | 2523 | else |
0425b46a | 2524 | size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4; |
1da177e4 | 2525 | |
da6971d8 AR |
2526 | /* allocate skb */ |
2527 | skb = dev_alloc_skb(size); | |
d44570e4 | 2528 | if (!skb) { |
9e39f7c5 JP |
2529 | DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n", |
2530 | ring->dev->name); | |
303bcb4b | 2531 | if (first_rxdp) { |
2532 | wmb(); | |
2533 | first_rxdp->Control_1 |= RXD_OWN_XENA; | |
2534 | } | |
ffb5df6c | 2535 | swstats->mem_alloc_fail_cnt++; |
7d2e3cb7 | 2536 | |
da6971d8 AR |
2537 | return -ENOMEM ; |
2538 | } | |
ffb5df6c | 2539 | swstats->mem_allocated += skb->truesize; |
0425b46a SH |
2540 | |
2541 | if (ring->rxd_mode == RXD_MODE_1) { | |
da6971d8 | 2542 | /* 1 buffer mode - normal operation mode */ |
d44570e4 | 2543 | rxdp1 = (struct RxD1 *)rxdp; |
1ee6dd77 | 2544 | memset(rxdp, 0, sizeof(struct RxD1)); |
da6971d8 | 2545 | skb_reserve(skb, NET_IP_ALIGN); |
d44570e4 JP |
2546 | rxdp1->Buffer0_ptr = |
2547 | pci_map_single(ring->pdev, skb->data, | |
2548 | size - NET_IP_ALIGN, | |
2549 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 2550 | if (pci_dma_mapping_error(nic->pdev, |
d44570e4 | 2551 | rxdp1->Buffer0_ptr)) |
491abf25 VP |
2552 | goto pci_map_failed; |
2553 | ||
8a4bdbaa | 2554 | rxdp->Control_2 = |
491976b2 | 2555 | SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN); |
d44570e4 | 2556 | rxdp->Host_Control = (unsigned long)skb; |
0425b46a | 2557 | } else if (ring->rxd_mode == RXD_MODE_3B) { |
da6971d8 | 2558 | /* |
6d517a27 VP |
2559 | * 2 buffer mode - |
2560 | * 2 buffer mode provides 128 | |
da6971d8 | 2561 | * byte aligned receive buffers. |
da6971d8 AR |
2562 | */ |
2563 | ||
d44570e4 | 2564 | rxdp3 = (struct RxD3 *)rxdp; |
491976b2 | 2565 | /* save buffer pointers to avoid frequent dma mapping */ |
6d517a27 VP |
2566 | Buffer0_ptr = rxdp3->Buffer0_ptr; |
2567 | Buffer1_ptr = rxdp3->Buffer1_ptr; | |
1ee6dd77 | 2568 | memset(rxdp, 0, sizeof(struct RxD3)); |
363dc367 | 2569 | /* restore the buffer pointers for dma sync*/ |
6d517a27 VP |
2570 | rxdp3->Buffer0_ptr = Buffer0_ptr; |
2571 | rxdp3->Buffer1_ptr = Buffer1_ptr; | |
363dc367 | 2572 | |
0425b46a | 2573 | ba = &ring->ba[block_no][off]; |
da6971d8 | 2574 | skb_reserve(skb, BUF0_LEN); |
d44570e4 | 2575 | tmp = (u64)(unsigned long)skb->data; |
da6971d8 AR |
2576 | tmp += ALIGN_SIZE; |
2577 | tmp &= ~ALIGN_SIZE; | |
2578 | skb->data = (void *) (unsigned long)tmp; | |
27a884dc | 2579 | skb_reset_tail_pointer(skb); |
da6971d8 | 2580 | |
3f78d885 | 2581 | if (from_card_up) { |
6d517a27 | 2582 | rxdp3->Buffer0_ptr = |
d44570e4 JP |
2583 | pci_map_single(ring->pdev, ba->ba_0, |
2584 | BUF0_LEN, | |
2585 | PCI_DMA_FROMDEVICE); | |
2586 | if (pci_dma_mapping_error(nic->pdev, | |
2587 | rxdp3->Buffer0_ptr)) | |
3f78d885 SH |
2588 | goto pci_map_failed; |
2589 | } else | |
0425b46a | 2590 | pci_dma_sync_single_for_device(ring->pdev, |
d44570e4 JP |
2591 | (dma_addr_t)rxdp3->Buffer0_ptr, |
2592 | BUF0_LEN, | |
2593 | PCI_DMA_FROMDEVICE); | |
491abf25 | 2594 | |
da6971d8 | 2595 | rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); |
0425b46a | 2596 | if (ring->rxd_mode == RXD_MODE_3B) { |
da6971d8 AR |
2597 | /* Two buffer mode */ |
2598 | ||
2599 | /* | |
6aa20a22 | 2600 | * Buffer2 will have L3/L4 header plus |
da6971d8 AR |
2601 | * L4 payload |
2602 | */ | |
d44570e4 JP |
2603 | rxdp3->Buffer2_ptr = pci_map_single(ring->pdev, |
2604 | skb->data, | |
2605 | ring->mtu + 4, | |
2606 | PCI_DMA_FROMDEVICE); | |
da6971d8 | 2607 | |
8d8bb39b | 2608 | if (pci_dma_mapping_error(nic->pdev, |
d44570e4 | 2609 | rxdp3->Buffer2_ptr)) |
491abf25 VP |
2610 | goto pci_map_failed; |
2611 | ||
3f78d885 | 2612 | if (from_card_up) { |
0425b46a SH |
2613 | rxdp3->Buffer1_ptr = |
2614 | pci_map_single(ring->pdev, | |
d44570e4 JP |
2615 | ba->ba_1, |
2616 | BUF1_LEN, | |
2617 | PCI_DMA_FROMDEVICE); | |
0425b46a | 2618 | |
8d8bb39b | 2619 | if (pci_dma_mapping_error(nic->pdev, |
d44570e4 JP |
2620 | rxdp3->Buffer1_ptr)) { |
2621 | pci_unmap_single(ring->pdev, | |
2622 | (dma_addr_t)(unsigned long) | |
2623 | skb->data, | |
2624 | ring->mtu + 4, | |
2625 | PCI_DMA_FROMDEVICE); | |
3f78d885 SH |
2626 | goto pci_map_failed; |
2627 | } | |
75c30b13 | 2628 | } |
da6971d8 AR |
2629 | rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1); |
2630 | rxdp->Control_2 |= SET_BUFFER2_SIZE_3 | |
d44570e4 | 2631 | (ring->mtu + 4); |
da6971d8 | 2632 | } |
b7b5a128 | 2633 | rxdp->Control_2 |= s2BIT(0); |
0425b46a | 2634 | rxdp->Host_Control = (unsigned long) (skb); |
1da177e4 | 2635 | } |
303bcb4b | 2636 | if (alloc_tab & ((1 << rxsync_frequency) - 1)) |
2637 | rxdp->Control_1 |= RXD_OWN_XENA; | |
1da177e4 | 2638 | off++; |
0425b46a | 2639 | if (off == (ring->rxd_count + 1)) |
da6971d8 | 2640 | off = 0; |
0425b46a | 2641 | ring->rx_curr_put_info.offset = off; |
20346722 | 2642 | |
da6971d8 | 2643 | rxdp->Control_2 |= SET_RXD_MARKER; |
303bcb4b | 2644 | if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) { |
2645 | if (first_rxdp) { | |
2646 | wmb(); | |
2647 | first_rxdp->Control_1 |= RXD_OWN_XENA; | |
2648 | } | |
2649 | first_rxdp = rxdp; | |
2650 | } | |
0425b46a | 2651 | ring->rx_bufs_left += 1; |
1da177e4 LT |
2652 | alloc_tab++; |
2653 | } | |
2654 | ||
d44570e4 | 2655 | end: |
303bcb4b | 2656 | /* Transfer ownership of first descriptor to adapter just before |
2657 | * exiting. Before that, use memory barrier so that ownership | |
2658 | * and other fields are seen by adapter correctly. | |
2659 | */ | |
2660 | if (first_rxdp) { | |
2661 | wmb(); | |
2662 | first_rxdp->Control_1 |= RXD_OWN_XENA; | |
2663 | } | |
2664 | ||
1da177e4 | 2665 | return SUCCESS; |
d44570e4 | 2666 | |
491abf25 | 2667 | pci_map_failed: |
ffb5df6c JP |
2668 | swstats->pci_map_fail_cnt++; |
2669 | swstats->mem_freed += skb->truesize; | |
491abf25 VP |
2670 | dev_kfree_skb_irq(skb); |
2671 | return -ENOMEM; | |
1da177e4 LT |
2672 | } |
2673 | ||
da6971d8 AR |
2674 | static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk) |
2675 | { | |
2676 | struct net_device *dev = sp->dev; | |
2677 | int j; | |
2678 | struct sk_buff *skb; | |
1ee6dd77 | 2679 | struct RxD_t *rxdp; |
6d517a27 VP |
2680 | struct RxD1 *rxdp1; |
2681 | struct RxD3 *rxdp3; | |
ffb5df6c JP |
2682 | struct mac_info *mac_control = &sp->mac_control; |
2683 | struct stat_block *stats = mac_control->stats_info; | |
2684 | struct swStat *swstats = &stats->sw_stat; | |
da6971d8 | 2685 | |
da6971d8 AR |
2686 | for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) { |
2687 | rxdp = mac_control->rings[ring_no]. | |
d44570e4 JP |
2688 | rx_blocks[blk].rxds[j].virt_addr; |
2689 | skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control); | |
2690 | if (!skb) | |
da6971d8 | 2691 | continue; |
da6971d8 | 2692 | if (sp->rxd_mode == RXD_MODE_1) { |
d44570e4 JP |
2693 | rxdp1 = (struct RxD1 *)rxdp; |
2694 | pci_unmap_single(sp->pdev, | |
2695 | (dma_addr_t)rxdp1->Buffer0_ptr, | |
2696 | dev->mtu + | |
2697 | HEADER_ETHERNET_II_802_3_SIZE + | |
2698 | HEADER_802_2_SIZE + HEADER_SNAP_SIZE, | |
2699 | PCI_DMA_FROMDEVICE); | |
1ee6dd77 | 2700 | memset(rxdp, 0, sizeof(struct RxD1)); |
d44570e4 JP |
2701 | } else if (sp->rxd_mode == RXD_MODE_3B) { |
2702 | rxdp3 = (struct RxD3 *)rxdp; | |
d44570e4 JP |
2703 | pci_unmap_single(sp->pdev, |
2704 | (dma_addr_t)rxdp3->Buffer0_ptr, | |
2705 | BUF0_LEN, | |
2706 | PCI_DMA_FROMDEVICE); | |
2707 | pci_unmap_single(sp->pdev, | |
2708 | (dma_addr_t)rxdp3->Buffer1_ptr, | |
2709 | BUF1_LEN, | |
2710 | PCI_DMA_FROMDEVICE); | |
2711 | pci_unmap_single(sp->pdev, | |
2712 | (dma_addr_t)rxdp3->Buffer2_ptr, | |
2713 | dev->mtu + 4, | |
2714 | PCI_DMA_FROMDEVICE); | |
1ee6dd77 | 2715 | memset(rxdp, 0, sizeof(struct RxD3)); |
da6971d8 | 2716 | } |
ffb5df6c | 2717 | swstats->mem_freed += skb->truesize; |
da6971d8 | 2718 | dev_kfree_skb(skb); |
0425b46a | 2719 | mac_control->rings[ring_no].rx_bufs_left -= 1; |
da6971d8 AR |
2720 | } |
2721 | } | |
2722 | ||
1da177e4 | 2723 | /** |
20346722 | 2724 | * free_rx_buffers - Frees all Rx buffers |
1da177e4 | 2725 | * @sp: device private variable. |
20346722 | 2726 | * Description: |
1da177e4 LT |
2727 | * This function will free all Rx buffers allocated by host. |
2728 | * Return Value: | |
2729 | * NONE. | |
2730 | */ | |
2731 | ||
2732 | static void free_rx_buffers(struct s2io_nic *sp) | |
2733 | { | |
2734 | struct net_device *dev = sp->dev; | |
da6971d8 | 2735 | int i, blk = 0, buf_cnt = 0; |
ffb5df6c JP |
2736 | struct config_param *config = &sp->config; |
2737 | struct mac_info *mac_control = &sp->mac_control; | |
1da177e4 LT |
2738 | |
2739 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
2740 | struct ring_info *ring = &mac_control->rings[i]; |
2741 | ||
da6971d8 | 2742 | for (blk = 0; blk < rx_ring_sz[i]; blk++) |
d44570e4 | 2743 | free_rxd_blk(sp, i, blk); |
1da177e4 | 2744 | |
13d866a9 JP |
2745 | ring->rx_curr_put_info.block_index = 0; |
2746 | ring->rx_curr_get_info.block_index = 0; | |
2747 | ring->rx_curr_put_info.offset = 0; | |
2748 | ring->rx_curr_get_info.offset = 0; | |
2749 | ring->rx_bufs_left = 0; | |
9e39f7c5 | 2750 | DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n", |
1da177e4 LT |
2751 | dev->name, buf_cnt, i); |
2752 | } | |
2753 | } | |
2754 | ||
8d8bb39b | 2755 | static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring) |
f61e0a35 | 2756 | { |
8d8bb39b | 2757 | if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) { |
9e39f7c5 JP |
2758 | DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n", |
2759 | ring->dev->name); | |
f61e0a35 SH |
2760 | } |
2761 | return 0; | |
2762 | } | |
2763 | ||
1da177e4 LT |
2764 | /** |
2765 | * s2io_poll - Rx interrupt handler for NAPI support | |
bea3348e | 2766 | * @napi : pointer to the napi structure. |
20346722 | 2767 | * @budget : The number of packets that were budgeted to be processed |
1da177e4 LT |
2768 | * during one pass through the 'Poll" function. |
2769 | * Description: | |
2770 | * Comes into picture only if NAPI support has been incorporated. It does | |
2771 | * the same thing that rx_intr_handler does, but not in a interrupt context | |
2772 | * also It will process only a given number of packets. | |
2773 | * Return value: | |
2774 | * 0 on success and 1 if there are No Rx packets to be processed. | |
2775 | */ | |
2776 | ||
f61e0a35 | 2777 | static int s2io_poll_msix(struct napi_struct *napi, int budget) |
1da177e4 | 2778 | { |
f61e0a35 SH |
2779 | struct ring_info *ring = container_of(napi, struct ring_info, napi); |
2780 | struct net_device *dev = ring->dev; | |
f61e0a35 | 2781 | int pkts_processed = 0; |
1a79d1c3 AV |
2782 | u8 __iomem *addr = NULL; |
2783 | u8 val8 = 0; | |
4cf1653a | 2784 | struct s2io_nic *nic = netdev_priv(dev); |
1ee6dd77 | 2785 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
f61e0a35 | 2786 | int budget_org = budget; |
1da177e4 | 2787 | |
f61e0a35 SH |
2788 | if (unlikely(!is_s2io_card_up(nic))) |
2789 | return 0; | |
1da177e4 | 2790 | |
f61e0a35 | 2791 | pkts_processed = rx_intr_handler(ring, budget); |
8d8bb39b | 2792 | s2io_chk_rx_buffers(nic, ring); |
1da177e4 | 2793 | |
f61e0a35 | 2794 | if (pkts_processed < budget_org) { |
288379f0 | 2795 | napi_complete(napi); |
f61e0a35 | 2796 | /*Re Enable MSI-Rx Vector*/ |
1a79d1c3 | 2797 | addr = (u8 __iomem *)&bar0->xmsi_mask_reg; |
f61e0a35 SH |
2798 | addr += 7 - ring->ring_no; |
2799 | val8 = (ring->ring_no == 0) ? 0x3f : 0xbf; | |
2800 | writeb(val8, addr); | |
2801 | val8 = readb(addr); | |
1da177e4 | 2802 | } |
f61e0a35 SH |
2803 | return pkts_processed; |
2804 | } | |
d44570e4 | 2805 | |
f61e0a35 SH |
2806 | static int s2io_poll_inta(struct napi_struct *napi, int budget) |
2807 | { | |
2808 | struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi); | |
f61e0a35 SH |
2809 | int pkts_processed = 0; |
2810 | int ring_pkts_processed, i; | |
2811 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | |
2812 | int budget_org = budget; | |
ffb5df6c JP |
2813 | struct config_param *config = &nic->config; |
2814 | struct mac_info *mac_control = &nic->mac_control; | |
1da177e4 | 2815 | |
f61e0a35 SH |
2816 | if (unlikely(!is_s2io_card_up(nic))) |
2817 | return 0; | |
1da177e4 | 2818 | |
1da177e4 | 2819 | for (i = 0; i < config->rx_ring_num; i++) { |
13d866a9 | 2820 | struct ring_info *ring = &mac_control->rings[i]; |
f61e0a35 | 2821 | ring_pkts_processed = rx_intr_handler(ring, budget); |
8d8bb39b | 2822 | s2io_chk_rx_buffers(nic, ring); |
f61e0a35 SH |
2823 | pkts_processed += ring_pkts_processed; |
2824 | budget -= ring_pkts_processed; | |
2825 | if (budget <= 0) | |
1da177e4 | 2826 | break; |
1da177e4 | 2827 | } |
f61e0a35 | 2828 | if (pkts_processed < budget_org) { |
288379f0 | 2829 | napi_complete(napi); |
f61e0a35 SH |
2830 | /* Re enable the Rx interrupts for the ring */ |
2831 | writeq(0, &bar0->rx_traffic_mask); | |
2832 | readl(&bar0->rx_traffic_mask); | |
2833 | } | |
2834 | return pkts_processed; | |
1da177e4 | 2835 | } |
20346722 | 2836 | |
b41477f3 | 2837 | #ifdef CONFIG_NET_POLL_CONTROLLER |
612eff0e | 2838 | /** |
b41477f3 | 2839 | * s2io_netpoll - netpoll event handler entry point |
612eff0e BH |
2840 | * @dev : pointer to the device structure. |
2841 | * Description: | |
b41477f3 AR |
2842 | * This function will be called by upper layer to check for events on the |
2843 | * interface in situations where interrupts are disabled. It is used for | |
2844 | * specific in-kernel networking tasks, such as remote consoles and kernel | |
2845 | * debugging over the network (example netdump in RedHat). | |
612eff0e | 2846 | */ |
612eff0e BH |
2847 | static void s2io_netpoll(struct net_device *dev) |
2848 | { | |
4cf1653a | 2849 | struct s2io_nic *nic = netdev_priv(dev); |
1ee6dd77 | 2850 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
b41477f3 | 2851 | u64 val64 = 0xFFFFFFFFFFFFFFFFULL; |
612eff0e | 2852 | int i; |
ffb5df6c JP |
2853 | struct config_param *config = &nic->config; |
2854 | struct mac_info *mac_control = &nic->mac_control; | |
612eff0e | 2855 | |
d796fdb7 LV |
2856 | if (pci_channel_offline(nic->pdev)) |
2857 | return; | |
2858 | ||
612eff0e BH |
2859 | disable_irq(dev->irq); |
2860 | ||
612eff0e | 2861 | writeq(val64, &bar0->rx_traffic_int); |
b41477f3 AR |
2862 | writeq(val64, &bar0->tx_traffic_int); |
2863 | ||
6aa20a22 | 2864 | /* we need to free up the transmitted skbufs or else netpoll will |
b41477f3 AR |
2865 | * run out of skbs and will fail and eventually netpoll application such |
2866 | * as netdump will fail. | |
2867 | */ | |
2868 | for (i = 0; i < config->tx_fifo_num; i++) | |
2869 | tx_intr_handler(&mac_control->fifos[i]); | |
612eff0e | 2870 | |
b41477f3 | 2871 | /* check for received packet and indicate up to network */ |
13d866a9 JP |
2872 | for (i = 0; i < config->rx_ring_num; i++) { |
2873 | struct ring_info *ring = &mac_control->rings[i]; | |
2874 | ||
2875 | rx_intr_handler(ring, 0); | |
2876 | } | |
612eff0e BH |
2877 | |
2878 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
2879 | struct ring_info *ring = &mac_control->rings[i]; |
2880 | ||
2881 | if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) { | |
9e39f7c5 JP |
2882 | DBG_PRINT(INFO_DBG, |
2883 | "%s: Out of memory in Rx Netpoll!!\n", | |
2884 | dev->name); | |
612eff0e BH |
2885 | break; |
2886 | } | |
2887 | } | |
612eff0e | 2888 | enable_irq(dev->irq); |
612eff0e BH |
2889 | } |
2890 | #endif | |
2891 | ||
20346722 | 2892 | /** |
1da177e4 | 2893 | * rx_intr_handler - Rx interrupt handler |
f61e0a35 SH |
2894 | * @ring_info: per ring structure. |
2895 | * @budget: budget for napi processing. | |
20346722 | 2896 | * Description: |
2897 | * If the interrupt is because of a received frame or if the | |
1da177e4 | 2898 | * receive ring contains fresh as yet un-processed frames,this function is |
20346722 | 2899 | * called. It picks out the RxD at which place the last Rx processing had |
2900 | * stopped and sends the skb to the OSM's Rx handler and then increments | |
1da177e4 LT |
2901 | * the offset. |
2902 | * Return Value: | |
f61e0a35 | 2903 | * No. of napi packets processed. |
1da177e4 | 2904 | */ |
f61e0a35 | 2905 | static int rx_intr_handler(struct ring_info *ring_data, int budget) |
1da177e4 | 2906 | { |
c9fcbf47 | 2907 | int get_block, put_block; |
1ee6dd77 RB |
2908 | struct rx_curr_get_info get_info, put_info; |
2909 | struct RxD_t *rxdp; | |
1da177e4 | 2910 | struct sk_buff *skb; |
f61e0a35 | 2911 | int pkt_cnt = 0, napi_pkts = 0; |
7d3d0439 | 2912 | int i; |
d44570e4 JP |
2913 | struct RxD1 *rxdp1; |
2914 | struct RxD3 *rxdp3; | |
7d3d0439 | 2915 | |
20346722 | 2916 | get_info = ring_data->rx_curr_get_info; |
2917 | get_block = get_info.block_index; | |
1ee6dd77 | 2918 | memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info)); |
20346722 | 2919 | put_block = put_info.block_index; |
da6971d8 | 2920 | rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr; |
db874e65 | 2921 | |
da6971d8 | 2922 | while (RXD_IS_UP2DT(rxdp)) { |
db874e65 SS |
2923 | /* |
2924 | * If your are next to put index then it's | |
2925 | * FIFO full condition | |
2926 | */ | |
da6971d8 AR |
2927 | if ((get_block == put_block) && |
2928 | (get_info.offset + 1) == put_info.offset) { | |
0425b46a | 2929 | DBG_PRINT(INTR_DBG, "%s: Ring Full\n", |
d44570e4 | 2930 | ring_data->dev->name); |
da6971d8 AR |
2931 | break; |
2932 | } | |
d44570e4 | 2933 | skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control); |
20346722 | 2934 | if (skb == NULL) { |
9e39f7c5 | 2935 | DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n", |
0425b46a | 2936 | ring_data->dev->name); |
f61e0a35 | 2937 | return 0; |
1da177e4 | 2938 | } |
0425b46a | 2939 | if (ring_data->rxd_mode == RXD_MODE_1) { |
d44570e4 | 2940 | rxdp1 = (struct RxD1 *)rxdp; |
0425b46a | 2941 | pci_unmap_single(ring_data->pdev, (dma_addr_t) |
d44570e4 JP |
2942 | rxdp1->Buffer0_ptr, |
2943 | ring_data->mtu + | |
2944 | HEADER_ETHERNET_II_802_3_SIZE + | |
2945 | HEADER_802_2_SIZE + | |
2946 | HEADER_SNAP_SIZE, | |
2947 | PCI_DMA_FROMDEVICE); | |
0425b46a | 2948 | } else if (ring_data->rxd_mode == RXD_MODE_3B) { |
d44570e4 JP |
2949 | rxdp3 = (struct RxD3 *)rxdp; |
2950 | pci_dma_sync_single_for_cpu(ring_data->pdev, | |
2951 | (dma_addr_t)rxdp3->Buffer0_ptr, | |
2952 | BUF0_LEN, | |
2953 | PCI_DMA_FROMDEVICE); | |
2954 | pci_unmap_single(ring_data->pdev, | |
2955 | (dma_addr_t)rxdp3->Buffer2_ptr, | |
2956 | ring_data->mtu + 4, | |
2957 | PCI_DMA_FROMDEVICE); | |
da6971d8 | 2958 | } |
863c11a9 | 2959 | prefetch(skb->data); |
20346722 | 2960 | rx_osm_handler(ring_data, rxdp); |
2961 | get_info.offset++; | |
da6971d8 AR |
2962 | ring_data->rx_curr_get_info.offset = get_info.offset; |
2963 | rxdp = ring_data->rx_blocks[get_block]. | |
d44570e4 | 2964 | rxds[get_info.offset].virt_addr; |
0425b46a | 2965 | if (get_info.offset == rxd_count[ring_data->rxd_mode]) { |
20346722 | 2966 | get_info.offset = 0; |
da6971d8 | 2967 | ring_data->rx_curr_get_info.offset = get_info.offset; |
20346722 | 2968 | get_block++; |
da6971d8 AR |
2969 | if (get_block == ring_data->block_count) |
2970 | get_block = 0; | |
2971 | ring_data->rx_curr_get_info.block_index = get_block; | |
20346722 | 2972 | rxdp = ring_data->rx_blocks[get_block].block_virt_addr; |
2973 | } | |
1da177e4 | 2974 | |
f61e0a35 SH |
2975 | if (ring_data->nic->config.napi) { |
2976 | budget--; | |
2977 | napi_pkts++; | |
2978 | if (!budget) | |
0425b46a SH |
2979 | break; |
2980 | } | |
20346722 | 2981 | pkt_cnt++; |
1da177e4 LT |
2982 | if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts)) |
2983 | break; | |
2984 | } | |
0425b46a | 2985 | if (ring_data->lro) { |
7d3d0439 | 2986 | /* Clear all LRO sessions before exiting */ |
d44570e4 | 2987 | for (i = 0; i < MAX_LRO_SESSIONS; i++) { |
0425b46a | 2988 | struct lro *lro = &ring_data->lro0_n[i]; |
7d3d0439 | 2989 | if (lro->in_use) { |
0425b46a | 2990 | update_L3L4_header(ring_data->nic, lro); |
cdb5bf02 | 2991 | queue_rx_frame(lro->parent, lro->vlan_tag); |
7d3d0439 RA |
2992 | clear_lro_session(lro); |
2993 | } | |
2994 | } | |
2995 | } | |
d44570e4 | 2996 | return napi_pkts; |
1da177e4 | 2997 | } |
20346722 | 2998 | |
2999 | /** | |
1da177e4 LT |
3000 | * tx_intr_handler - Transmit interrupt handler |
3001 | * @nic : device private variable | |
20346722 | 3002 | * Description: |
3003 | * If an interrupt was raised to indicate DMA complete of the | |
3004 | * Tx packet, this function is called. It identifies the last TxD | |
3005 | * whose buffer was freed and frees all skbs whose data have already | |
1da177e4 LT |
3006 | * DMA'ed into the NICs internal memory. |
3007 | * Return Value: | |
3008 | * NONE | |
3009 | */ | |
3010 | ||
1ee6dd77 | 3011 | static void tx_intr_handler(struct fifo_info *fifo_data) |
1da177e4 | 3012 | { |
1ee6dd77 | 3013 | struct s2io_nic *nic = fifo_data->nic; |
1ee6dd77 | 3014 | struct tx_curr_get_info get_info, put_info; |
3a3d5756 | 3015 | struct sk_buff *skb = NULL; |
1ee6dd77 | 3016 | struct TxD *txdlp; |
3a3d5756 | 3017 | int pkt_cnt = 0; |
2fda096d | 3018 | unsigned long flags = 0; |
f9046eb3 | 3019 | u8 err_mask; |
ffb5df6c JP |
3020 | struct stat_block *stats = nic->mac_control.stats_info; |
3021 | struct swStat *swstats = &stats->sw_stat; | |
1da177e4 | 3022 | |
2fda096d | 3023 | if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags)) |
d44570e4 | 3024 | return; |
2fda096d | 3025 | |
20346722 | 3026 | get_info = fifo_data->tx_curr_get_info; |
1ee6dd77 | 3027 | memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info)); |
43d620c8 | 3028 | txdlp = fifo_data->list_info[get_info.offset].list_virt_addr; |
20346722 | 3029 | while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) && |
3030 | (get_info.offset != put_info.offset) && | |
3031 | (txdlp->Host_Control)) { | |
3032 | /* Check for TxD errors */ | |
3033 | if (txdlp->Control_1 & TXD_T_CODE) { | |
3034 | unsigned long long err; | |
3035 | err = txdlp->Control_1 & TXD_T_CODE; | |
bd1034f0 | 3036 | if (err & 0x1) { |
ffb5df6c | 3037 | swstats->parity_err_cnt++; |
bd1034f0 | 3038 | } |
491976b2 SH |
3039 | |
3040 | /* update t_code statistics */ | |
f9046eb3 | 3041 | err_mask = err >> 48; |
d44570e4 JP |
3042 | switch (err_mask) { |
3043 | case 2: | |
ffb5df6c | 3044 | swstats->tx_buf_abort_cnt++; |
491976b2 SH |
3045 | break; |
3046 | ||
d44570e4 | 3047 | case 3: |
ffb5df6c | 3048 | swstats->tx_desc_abort_cnt++; |
491976b2 SH |
3049 | break; |
3050 | ||
d44570e4 | 3051 | case 7: |
ffb5df6c | 3052 | swstats->tx_parity_err_cnt++; |
491976b2 SH |
3053 | break; |
3054 | ||
d44570e4 | 3055 | case 10: |
ffb5df6c | 3056 | swstats->tx_link_loss_cnt++; |
491976b2 SH |
3057 | break; |
3058 | ||
d44570e4 | 3059 | case 15: |
ffb5df6c | 3060 | swstats->tx_list_proc_err_cnt++; |
491976b2 | 3061 | break; |
d44570e4 | 3062 | } |
20346722 | 3063 | } |
1da177e4 | 3064 | |
fed5eccd | 3065 | skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset); |
20346722 | 3066 | if (skb == NULL) { |
2fda096d | 3067 | spin_unlock_irqrestore(&fifo_data->tx_lock, flags); |
9e39f7c5 JP |
3068 | DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n", |
3069 | __func__); | |
20346722 | 3070 | return; |
3071 | } | |
3a3d5756 | 3072 | pkt_cnt++; |
20346722 | 3073 | |
20346722 | 3074 | /* Updating the statistics block */ |
ffb5df6c | 3075 | swstats->mem_freed += skb->truesize; |
20346722 | 3076 | dev_kfree_skb_irq(skb); |
3077 | ||
3078 | get_info.offset++; | |
863c11a9 AR |
3079 | if (get_info.offset == get_info.fifo_len + 1) |
3080 | get_info.offset = 0; | |
43d620c8 | 3081 | txdlp = fifo_data->list_info[get_info.offset].list_virt_addr; |
d44570e4 | 3082 | fifo_data->tx_curr_get_info.offset = get_info.offset; |
1da177e4 LT |
3083 | } |
3084 | ||
3a3d5756 | 3085 | s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq); |
2fda096d SR |
3086 | |
3087 | spin_unlock_irqrestore(&fifo_data->tx_lock, flags); | |
1da177e4 LT |
3088 | } |
3089 | ||
bd1034f0 AR |
3090 | /** |
3091 | * s2io_mdio_write - Function to write in to MDIO registers | |
3092 | * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS) | |
3093 | * @addr : address value | |
3094 | * @value : data value | |
3095 | * @dev : pointer to net_device structure | |
3096 | * Description: | |
3097 | * This function is used to write values to the MDIO registers | |
3098 | * NONE | |
3099 | */ | |
d44570e4 JP |
3100 | static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, |
3101 | struct net_device *dev) | |
bd1034f0 | 3102 | { |
d44570e4 | 3103 | u64 val64; |
4cf1653a | 3104 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 3105 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
bd1034f0 | 3106 | |
d44570e4 JP |
3107 | /* address transaction */ |
3108 | val64 = MDIO_MMD_INDX_ADDR(addr) | | |
3109 | MDIO_MMD_DEV_ADDR(mmd_type) | | |
3110 | MDIO_MMS_PRT_ADDR(0x0); | |
bd1034f0 AR |
3111 | writeq(val64, &bar0->mdio_control); |
3112 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3113 | writeq(val64, &bar0->mdio_control); | |
3114 | udelay(100); | |
3115 | ||
d44570e4 JP |
3116 | /* Data transaction */ |
3117 | val64 = MDIO_MMD_INDX_ADDR(addr) | | |
3118 | MDIO_MMD_DEV_ADDR(mmd_type) | | |
3119 | MDIO_MMS_PRT_ADDR(0x0) | | |
3120 | MDIO_MDIO_DATA(value) | | |
3121 | MDIO_OP(MDIO_OP_WRITE_TRANS); | |
bd1034f0 AR |
3122 | writeq(val64, &bar0->mdio_control); |
3123 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3124 | writeq(val64, &bar0->mdio_control); | |
3125 | udelay(100); | |
3126 | ||
d44570e4 JP |
3127 | val64 = MDIO_MMD_INDX_ADDR(addr) | |
3128 | MDIO_MMD_DEV_ADDR(mmd_type) | | |
3129 | MDIO_MMS_PRT_ADDR(0x0) | | |
3130 | MDIO_OP(MDIO_OP_READ_TRANS); | |
bd1034f0 AR |
3131 | writeq(val64, &bar0->mdio_control); |
3132 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3133 | writeq(val64, &bar0->mdio_control); | |
3134 | udelay(100); | |
bd1034f0 AR |
3135 | } |
3136 | ||
3137 | /** | |
3138 | * s2io_mdio_read - Function to write in to MDIO registers | |
3139 | * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS) | |
3140 | * @addr : address value | |
3141 | * @dev : pointer to net_device structure | |
3142 | * Description: | |
3143 | * This function is used to read values to the MDIO registers | |
3144 | * NONE | |
3145 | */ | |
3146 | static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev) | |
3147 | { | |
3148 | u64 val64 = 0x0; | |
3149 | u64 rval64 = 0x0; | |
4cf1653a | 3150 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 3151 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
bd1034f0 AR |
3152 | |
3153 | /* address transaction */ | |
d44570e4 JP |
3154 | val64 = val64 | (MDIO_MMD_INDX_ADDR(addr) |
3155 | | MDIO_MMD_DEV_ADDR(mmd_type) | |
3156 | | MDIO_MMS_PRT_ADDR(0x0)); | |
bd1034f0 AR |
3157 | writeq(val64, &bar0->mdio_control); |
3158 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3159 | writeq(val64, &bar0->mdio_control); | |
3160 | udelay(100); | |
3161 | ||
3162 | /* Data transaction */ | |
d44570e4 JP |
3163 | val64 = MDIO_MMD_INDX_ADDR(addr) | |
3164 | MDIO_MMD_DEV_ADDR(mmd_type) | | |
3165 | MDIO_MMS_PRT_ADDR(0x0) | | |
3166 | MDIO_OP(MDIO_OP_READ_TRANS); | |
bd1034f0 AR |
3167 | writeq(val64, &bar0->mdio_control); |
3168 | val64 = val64 | MDIO_CTRL_START_TRANS(0xE); | |
3169 | writeq(val64, &bar0->mdio_control); | |
3170 | udelay(100); | |
3171 | ||
3172 | /* Read the value from regs */ | |
3173 | rval64 = readq(&bar0->mdio_control); | |
3174 | rval64 = rval64 & 0xFFFF0000; | |
3175 | rval64 = rval64 >> 16; | |
3176 | return rval64; | |
3177 | } | |
d44570e4 | 3178 | |
bd1034f0 AR |
3179 | /** |
3180 | * s2io_chk_xpak_counter - Function to check the status of the xpak counters | |
fbfecd37 | 3181 | * @counter : counter value to be updated |
bd1034f0 AR |
3182 | * @flag : flag to indicate the status |
3183 | * @type : counter type | |
3184 | * Description: | |
3185 | * This function is to check the status of the xpak counters value | |
3186 | * NONE | |
3187 | */ | |
3188 | ||
d44570e4 JP |
3189 | static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, |
3190 | u16 flag, u16 type) | |
bd1034f0 AR |
3191 | { |
3192 | u64 mask = 0x3; | |
3193 | u64 val64; | |
3194 | int i; | |
d44570e4 | 3195 | for (i = 0; i < index; i++) |
bd1034f0 AR |
3196 | mask = mask << 0x2; |
3197 | ||
d44570e4 | 3198 | if (flag > 0) { |
bd1034f0 AR |
3199 | *counter = *counter + 1; |
3200 | val64 = *regs_stat & mask; | |
3201 | val64 = val64 >> (index * 0x2); | |
3202 | val64 = val64 + 1; | |
d44570e4 JP |
3203 | if (val64 == 3) { |
3204 | switch (type) { | |
bd1034f0 | 3205 | case 1: |
9e39f7c5 JP |
3206 | DBG_PRINT(ERR_DBG, |
3207 | "Take Xframe NIC out of service.\n"); | |
3208 | DBG_PRINT(ERR_DBG, | |
3209 | "Excessive temperatures may result in premature transceiver failure.\n"); | |
d44570e4 | 3210 | break; |
bd1034f0 | 3211 | case 2: |
9e39f7c5 JP |
3212 | DBG_PRINT(ERR_DBG, |
3213 | "Take Xframe NIC out of service.\n"); | |
3214 | DBG_PRINT(ERR_DBG, | |
3215 | "Excessive bias currents may indicate imminent laser diode failure.\n"); | |
d44570e4 | 3216 | break; |
bd1034f0 | 3217 | case 3: |
9e39f7c5 JP |
3218 | DBG_PRINT(ERR_DBG, |
3219 | "Take Xframe NIC out of service.\n"); | |
3220 | DBG_PRINT(ERR_DBG, | |
3221 | "Excessive laser output power may saturate far-end receiver.\n"); | |
d44570e4 | 3222 | break; |
bd1034f0 | 3223 | default: |
d44570e4 JP |
3224 | DBG_PRINT(ERR_DBG, |
3225 | "Incorrect XPAK Alarm type\n"); | |
bd1034f0 AR |
3226 | } |
3227 | val64 = 0x0; | |
3228 | } | |
3229 | val64 = val64 << (index * 0x2); | |
3230 | *regs_stat = (*regs_stat & (~mask)) | (val64); | |
3231 | ||
3232 | } else { | |
3233 | *regs_stat = *regs_stat & (~mask); | |
3234 | } | |
3235 | } | |
3236 | ||
3237 | /** | |
3238 | * s2io_updt_xpak_counter - Function to update the xpak counters | |
3239 | * @dev : pointer to net_device struct | |
3240 | * Description: | |
3241 | * This function is to upate the status of the xpak counters value | |
3242 | * NONE | |
3243 | */ | |
3244 | static void s2io_updt_xpak_counter(struct net_device *dev) | |
3245 | { | |
3246 | u16 flag = 0x0; | |
3247 | u16 type = 0x0; | |
3248 | u16 val16 = 0x0; | |
3249 | u64 val64 = 0x0; | |
3250 | u64 addr = 0x0; | |
3251 | ||
4cf1653a | 3252 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c JP |
3253 | struct stat_block *stats = sp->mac_control.stats_info; |
3254 | struct xpakStat *xstats = &stats->xpak_stat; | |
bd1034f0 AR |
3255 | |
3256 | /* Check the communication with the MDIO slave */ | |
40239396 | 3257 | addr = MDIO_CTRL1; |
bd1034f0 | 3258 | val64 = 0x0; |
40239396 | 3259 | val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); |
d44570e4 | 3260 | if ((val64 == 0xFFFF) || (val64 == 0x0000)) { |
9e39f7c5 JP |
3261 | DBG_PRINT(ERR_DBG, |
3262 | "ERR: MDIO slave access failed - Returned %llx\n", | |
3263 | (unsigned long long)val64); | |
bd1034f0 AR |
3264 | return; |
3265 | } | |
3266 | ||
40239396 | 3267 | /* Check for the expected value of control reg 1 */ |
d44570e4 | 3268 | if (val64 != MDIO_CTRL1_SPEED10G) { |
9e39f7c5 JP |
3269 | DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - " |
3270 | "Returned: %llx- Expected: 0x%x\n", | |
40239396 | 3271 | (unsigned long long)val64, MDIO_CTRL1_SPEED10G); |
bd1034f0 AR |
3272 | return; |
3273 | } | |
3274 | ||
3275 | /* Loading the DOM register to MDIO register */ | |
3276 | addr = 0xA100; | |
40239396 BH |
3277 | s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev); |
3278 | val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); | |
bd1034f0 AR |
3279 | |
3280 | /* Reading the Alarm flags */ | |
3281 | addr = 0xA070; | |
3282 | val64 = 0x0; | |
40239396 | 3283 | val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); |
bd1034f0 AR |
3284 | |
3285 | flag = CHECKBIT(val64, 0x7); | |
3286 | type = 1; | |
ffb5df6c JP |
3287 | s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high, |
3288 | &xstats->xpak_regs_stat, | |
d44570e4 | 3289 | 0x0, flag, type); |
bd1034f0 | 3290 | |
d44570e4 | 3291 | if (CHECKBIT(val64, 0x6)) |
ffb5df6c | 3292 | xstats->alarm_transceiver_temp_low++; |
bd1034f0 AR |
3293 | |
3294 | flag = CHECKBIT(val64, 0x3); | |
3295 | type = 2; | |
ffb5df6c JP |
3296 | s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high, |
3297 | &xstats->xpak_regs_stat, | |
d44570e4 | 3298 | 0x2, flag, type); |
bd1034f0 | 3299 | |
d44570e4 | 3300 | if (CHECKBIT(val64, 0x2)) |
ffb5df6c | 3301 | xstats->alarm_laser_bias_current_low++; |
bd1034f0 AR |
3302 | |
3303 | flag = CHECKBIT(val64, 0x1); | |
3304 | type = 3; | |
ffb5df6c JP |
3305 | s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high, |
3306 | &xstats->xpak_regs_stat, | |
d44570e4 | 3307 | 0x4, flag, type); |
bd1034f0 | 3308 | |
d44570e4 | 3309 | if (CHECKBIT(val64, 0x0)) |
ffb5df6c | 3310 | xstats->alarm_laser_output_power_low++; |
bd1034f0 AR |
3311 | |
3312 | /* Reading the Warning flags */ | |
3313 | addr = 0xA074; | |
3314 | val64 = 0x0; | |
40239396 | 3315 | val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev); |
bd1034f0 | 3316 | |
d44570e4 | 3317 | if (CHECKBIT(val64, 0x7)) |
ffb5df6c | 3318 | xstats->warn_transceiver_temp_high++; |
bd1034f0 | 3319 | |
d44570e4 | 3320 | if (CHECKBIT(val64, 0x6)) |
ffb5df6c | 3321 | xstats->warn_transceiver_temp_low++; |
bd1034f0 | 3322 | |
d44570e4 | 3323 | if (CHECKBIT(val64, 0x3)) |
ffb5df6c | 3324 | xstats->warn_laser_bias_current_high++; |
bd1034f0 | 3325 | |
d44570e4 | 3326 | if (CHECKBIT(val64, 0x2)) |
ffb5df6c | 3327 | xstats->warn_laser_bias_current_low++; |
bd1034f0 | 3328 | |
d44570e4 | 3329 | if (CHECKBIT(val64, 0x1)) |
ffb5df6c | 3330 | xstats->warn_laser_output_power_high++; |
bd1034f0 | 3331 | |
d44570e4 | 3332 | if (CHECKBIT(val64, 0x0)) |
ffb5df6c | 3333 | xstats->warn_laser_output_power_low++; |
bd1034f0 AR |
3334 | } |
3335 | ||
20346722 | 3336 | /** |
1da177e4 | 3337 | * wait_for_cmd_complete - waits for a command to complete. |
20346722 | 3338 | * @sp : private member of the device structure, which is a pointer to the |
1da177e4 | 3339 | * s2io_nic structure. |
20346722 | 3340 | * Description: Function that waits for a command to Write into RMAC |
3341 | * ADDR DATA registers to be completed and returns either success or | |
3342 | * error depending on whether the command was complete or not. | |
1da177e4 LT |
3343 | * Return value: |
3344 | * SUCCESS on success and FAILURE on failure. | |
3345 | */ | |
3346 | ||
9fc93a41 | 3347 | static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, |
d44570e4 | 3348 | int bit_state) |
1da177e4 | 3349 | { |
9fc93a41 | 3350 | int ret = FAILURE, cnt = 0, delay = 1; |
1da177e4 LT |
3351 | u64 val64; |
3352 | ||
9fc93a41 SS |
3353 | if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET)) |
3354 | return FAILURE; | |
3355 | ||
3356 | do { | |
c92ca04b | 3357 | val64 = readq(addr); |
9fc93a41 SS |
3358 | if (bit_state == S2IO_BIT_RESET) { |
3359 | if (!(val64 & busy_bit)) { | |
3360 | ret = SUCCESS; | |
3361 | break; | |
3362 | } | |
3363 | } else { | |
2d146eb1 | 3364 | if (val64 & busy_bit) { |
9fc93a41 SS |
3365 | ret = SUCCESS; |
3366 | break; | |
3367 | } | |
1da177e4 | 3368 | } |
c92ca04b | 3369 | |
d44570e4 | 3370 | if (in_interrupt()) |
9fc93a41 | 3371 | mdelay(delay); |
c92ca04b | 3372 | else |
9fc93a41 | 3373 | msleep(delay); |
c92ca04b | 3374 | |
9fc93a41 SS |
3375 | if (++cnt >= 10) |
3376 | delay = 50; | |
3377 | } while (cnt < 20); | |
1da177e4 LT |
3378 | return ret; |
3379 | } | |
19a60522 SS |
3380 | /* |
3381 | * check_pci_device_id - Checks if the device id is supported | |
3382 | * @id : device id | |
3383 | * Description: Function to check if the pci device id is supported by driver. | |
3384 | * Return value: Actual device id if supported else PCI_ANY_ID | |
3385 | */ | |
3386 | static u16 check_pci_device_id(u16 id) | |
3387 | { | |
3388 | switch (id) { | |
3389 | case PCI_DEVICE_ID_HERC_WIN: | |
3390 | case PCI_DEVICE_ID_HERC_UNI: | |
3391 | return XFRAME_II_DEVICE; | |
3392 | case PCI_DEVICE_ID_S2IO_UNI: | |
3393 | case PCI_DEVICE_ID_S2IO_WIN: | |
3394 | return XFRAME_I_DEVICE; | |
3395 | default: | |
3396 | return PCI_ANY_ID; | |
3397 | } | |
3398 | } | |
1da177e4 | 3399 | |
20346722 | 3400 | /** |
3401 | * s2io_reset - Resets the card. | |
1da177e4 LT |
3402 | * @sp : private member of the device structure. |
3403 | * Description: Function to Reset the card. This function then also | |
20346722 | 3404 | * restores the previously saved PCI configuration space registers as |
1da177e4 LT |
3405 | * the card reset also resets the configuration space. |
3406 | * Return value: | |
3407 | * void. | |
3408 | */ | |
3409 | ||
d44570e4 | 3410 | static void s2io_reset(struct s2io_nic *sp) |
1da177e4 | 3411 | { |
1ee6dd77 | 3412 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 3413 | u64 val64; |
5e25b9dd | 3414 | u16 subid, pci_cmd; |
19a60522 SS |
3415 | int i; |
3416 | u16 val16; | |
491976b2 SH |
3417 | unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt; |
3418 | unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt; | |
ffb5df6c JP |
3419 | struct stat_block *stats; |
3420 | struct swStat *swstats; | |
491976b2 | 3421 | |
9e39f7c5 | 3422 | DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n", |
3a22813a | 3423 | __func__, pci_name(sp->pdev)); |
1da177e4 | 3424 | |
0b1f7ebe | 3425 | /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */ |
e960fc5c | 3426 | pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd)); |
0b1f7ebe | 3427 | |
1da177e4 LT |
3428 | val64 = SW_RESET_ALL; |
3429 | writeq(val64, &bar0->sw_reset); | |
d44570e4 | 3430 | if (strstr(sp->product_name, "CX4")) |
c92ca04b | 3431 | msleep(750); |
19a60522 SS |
3432 | msleep(250); |
3433 | for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) { | |
1da177e4 | 3434 | |
19a60522 SS |
3435 | /* Restore the PCI state saved during initialization. */ |
3436 | pci_restore_state(sp->pdev); | |
b8a623bf | 3437 | pci_save_state(sp->pdev); |
19a60522 SS |
3438 | pci_read_config_word(sp->pdev, 0x2, &val16); |
3439 | if (check_pci_device_id(val16) != (u16)PCI_ANY_ID) | |
3440 | break; | |
3441 | msleep(200); | |
3442 | } | |
1da177e4 | 3443 | |
d44570e4 JP |
3444 | if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) |
3445 | DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__); | |
19a60522 SS |
3446 | |
3447 | pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd); | |
3448 | ||
3449 | s2io_init_pci(sp); | |
1da177e4 | 3450 | |
20346722 | 3451 | /* Set swapper to enable I/O register access */ |
3452 | s2io_set_swapper(sp); | |
3453 | ||
faa4f796 SH |
3454 | /* restore mac_addr entries */ |
3455 | do_s2io_restore_unicast_mc(sp); | |
3456 | ||
cc6e7c44 RA |
3457 | /* Restore the MSIX table entries from local variables */ |
3458 | restore_xmsi_data(sp); | |
3459 | ||
5e25b9dd | 3460 | /* Clear certain PCI/PCI-X fields after reset */ |
303bcb4b | 3461 | if (sp->device_type == XFRAME_II_DEVICE) { |
b41477f3 | 3462 | /* Clear "detected parity error" bit */ |
303bcb4b | 3463 | pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000); |
5e25b9dd | 3464 | |
303bcb4b | 3465 | /* Clearing PCIX Ecc status register */ |
3466 | pci_write_config_dword(sp->pdev, 0x68, 0x7C); | |
5e25b9dd | 3467 | |
303bcb4b | 3468 | /* Clearing PCI_STATUS error reflected here */ |
b7b5a128 | 3469 | writeq(s2BIT(62), &bar0->txpic_int_reg); |
303bcb4b | 3470 | } |
5e25b9dd | 3471 | |
20346722 | 3472 | /* Reset device statistics maintained by OS */ |
d44570e4 | 3473 | memset(&sp->stats, 0, sizeof(struct net_device_stats)); |
8a4bdbaa | 3474 | |
ffb5df6c JP |
3475 | stats = sp->mac_control.stats_info; |
3476 | swstats = &stats->sw_stat; | |
3477 | ||
491976b2 | 3478 | /* save link up/down time/cnt, reset/memory/watchdog cnt */ |
ffb5df6c JP |
3479 | up_cnt = swstats->link_up_cnt; |
3480 | down_cnt = swstats->link_down_cnt; | |
3481 | up_time = swstats->link_up_time; | |
3482 | down_time = swstats->link_down_time; | |
3483 | reset_cnt = swstats->soft_reset_cnt; | |
3484 | mem_alloc_cnt = swstats->mem_allocated; | |
3485 | mem_free_cnt = swstats->mem_freed; | |
3486 | watchdog_cnt = swstats->watchdog_timer_cnt; | |
3487 | ||
3488 | memset(stats, 0, sizeof(struct stat_block)); | |
3489 | ||
491976b2 | 3490 | /* restore link up/down time/cnt, reset/memory/watchdog cnt */ |
ffb5df6c JP |
3491 | swstats->link_up_cnt = up_cnt; |
3492 | swstats->link_down_cnt = down_cnt; | |
3493 | swstats->link_up_time = up_time; | |
3494 | swstats->link_down_time = down_time; | |
3495 | swstats->soft_reset_cnt = reset_cnt; | |
3496 | swstats->mem_allocated = mem_alloc_cnt; | |
3497 | swstats->mem_freed = mem_free_cnt; | |
3498 | swstats->watchdog_timer_cnt = watchdog_cnt; | |
20346722 | 3499 | |
1da177e4 LT |
3500 | /* SXE-002: Configure link and activity LED to turn it off */ |
3501 | subid = sp->pdev->subsystem_device; | |
541ae68f | 3502 | if (((subid & 0xFF) >= 0x07) && |
3503 | (sp->device_type == XFRAME_I_DEVICE)) { | |
1da177e4 LT |
3504 | val64 = readq(&bar0->gpio_control); |
3505 | val64 |= 0x0000800000000000ULL; | |
3506 | writeq(val64, &bar0->gpio_control); | |
3507 | val64 = 0x0411040400000000ULL; | |
509a2671 | 3508 | writeq(val64, (void __iomem *)bar0 + 0x2700); |
1da177e4 LT |
3509 | } |
3510 | ||
541ae68f | 3511 | /* |
25985edc | 3512 | * Clear spurious ECC interrupts that would have occurred on |
541ae68f | 3513 | * XFRAME II cards after reset. |
3514 | */ | |
3515 | if (sp->device_type == XFRAME_II_DEVICE) { | |
3516 | val64 = readq(&bar0->pcc_err_reg); | |
3517 | writeq(val64, &bar0->pcc_err_reg); | |
3518 | } | |
3519 | ||
f957bcf0 | 3520 | sp->device_enabled_once = false; |
1da177e4 LT |
3521 | } |
3522 | ||
3523 | /** | |
20346722 | 3524 | * s2io_set_swapper - to set the swapper controle on the card |
3525 | * @sp : private member of the device structure, | |
1da177e4 | 3526 | * pointer to the s2io_nic structure. |
20346722 | 3527 | * Description: Function to set the swapper control on the card |
1da177e4 LT |
3528 | * correctly depending on the 'endianness' of the system. |
3529 | * Return value: | |
3530 | * SUCCESS on success and FAILURE on failure. | |
3531 | */ | |
3532 | ||
d44570e4 | 3533 | static int s2io_set_swapper(struct s2io_nic *sp) |
1da177e4 LT |
3534 | { |
3535 | struct net_device *dev = sp->dev; | |
1ee6dd77 | 3536 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
3537 | u64 val64, valt, valr; |
3538 | ||
20346722 | 3539 | /* |
1da177e4 LT |
3540 | * Set proper endian settings and verify the same by reading |
3541 | * the PIF Feed-back register. | |
3542 | */ | |
3543 | ||
3544 | val64 = readq(&bar0->pif_rd_swapper_fb); | |
3545 | if (val64 != 0x0123456789ABCDEFULL) { | |
3546 | int i = 0; | |
85a56498 JM |
3547 | static const u64 value[] = { |
3548 | 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */ | |
3549 | 0x8100008181000081ULL, /* FE=1, SE=0 */ | |
3550 | 0x4200004242000042ULL, /* FE=0, SE=1 */ | |
3551 | 0 /* FE=0, SE=0 */ | |
3552 | }; | |
1da177e4 | 3553 | |
d44570e4 | 3554 | while (i < 4) { |
1da177e4 LT |
3555 | writeq(value[i], &bar0->swapper_ctrl); |
3556 | val64 = readq(&bar0->pif_rd_swapper_fb); | |
3557 | if (val64 == 0x0123456789ABCDEFULL) | |
3558 | break; | |
3559 | i++; | |
3560 | } | |
3561 | if (i == 4) { | |
9e39f7c5 JP |
3562 | DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, " |
3563 | "feedback read %llx\n", | |
3564 | dev->name, (unsigned long long)val64); | |
1da177e4 LT |
3565 | return FAILURE; |
3566 | } | |
3567 | valr = value[i]; | |
3568 | } else { | |
3569 | valr = readq(&bar0->swapper_ctrl); | |
3570 | } | |
3571 | ||
3572 | valt = 0x0123456789ABCDEFULL; | |
3573 | writeq(valt, &bar0->xmsi_address); | |
3574 | val64 = readq(&bar0->xmsi_address); | |
3575 | ||
d44570e4 | 3576 | if (val64 != valt) { |
1da177e4 | 3577 | int i = 0; |
85a56498 JM |
3578 | static const u64 value[] = { |
3579 | 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */ | |
3580 | 0x0081810000818100ULL, /* FE=1, SE=0 */ | |
3581 | 0x0042420000424200ULL, /* FE=0, SE=1 */ | |
3582 | 0 /* FE=0, SE=0 */ | |
3583 | }; | |
1da177e4 | 3584 | |
d44570e4 | 3585 | while (i < 4) { |
1da177e4 LT |
3586 | writeq((value[i] | valr), &bar0->swapper_ctrl); |
3587 | writeq(valt, &bar0->xmsi_address); | |
3588 | val64 = readq(&bar0->xmsi_address); | |
d44570e4 | 3589 | if (val64 == valt) |
1da177e4 LT |
3590 | break; |
3591 | i++; | |
3592 | } | |
d44570e4 | 3593 | if (i == 4) { |
20346722 | 3594 | unsigned long long x = val64; |
9e39f7c5 JP |
3595 | DBG_PRINT(ERR_DBG, |
3596 | "Write failed, Xmsi_addr reads:0x%llx\n", x); | |
1da177e4 LT |
3597 | return FAILURE; |
3598 | } | |
3599 | } | |
3600 | val64 = readq(&bar0->swapper_ctrl); | |
3601 | val64 &= 0xFFFF000000000000ULL; | |
3602 | ||
d44570e4 | 3603 | #ifdef __BIG_ENDIAN |
20346722 | 3604 | /* |
3605 | * The device by default set to a big endian format, so a | |
1da177e4 LT |
3606 | * big endian driver need not set anything. |
3607 | */ | |
3608 | val64 |= (SWAPPER_CTRL_TXP_FE | | |
d44570e4 JP |
3609 | SWAPPER_CTRL_TXP_SE | |
3610 | SWAPPER_CTRL_TXD_R_FE | | |
3611 | SWAPPER_CTRL_TXD_W_FE | | |
3612 | SWAPPER_CTRL_TXF_R_FE | | |
3613 | SWAPPER_CTRL_RXD_R_FE | | |
3614 | SWAPPER_CTRL_RXD_W_FE | | |
3615 | SWAPPER_CTRL_RXF_W_FE | | |
3616 | SWAPPER_CTRL_XMSI_FE | | |
3617 | SWAPPER_CTRL_STATS_FE | | |
3618 | SWAPPER_CTRL_STATS_SE); | |
eaae7f72 | 3619 | if (sp->config.intr_type == INTA) |
cc6e7c44 | 3620 | val64 |= SWAPPER_CTRL_XMSI_SE; |
1da177e4 LT |
3621 | writeq(val64, &bar0->swapper_ctrl); |
3622 | #else | |
20346722 | 3623 | /* |
1da177e4 | 3624 | * Initially we enable all bits to make it accessible by the |
20346722 | 3625 | * driver, then we selectively enable only those bits that |
1da177e4 LT |
3626 | * we want to set. |
3627 | */ | |
3628 | val64 |= (SWAPPER_CTRL_TXP_FE | | |
d44570e4 JP |
3629 | SWAPPER_CTRL_TXP_SE | |
3630 | SWAPPER_CTRL_TXD_R_FE | | |
3631 | SWAPPER_CTRL_TXD_R_SE | | |
3632 | SWAPPER_CTRL_TXD_W_FE | | |
3633 | SWAPPER_CTRL_TXD_W_SE | | |
3634 | SWAPPER_CTRL_TXF_R_FE | | |
3635 | SWAPPER_CTRL_RXD_R_FE | | |
3636 | SWAPPER_CTRL_RXD_R_SE | | |
3637 | SWAPPER_CTRL_RXD_W_FE | | |
3638 | SWAPPER_CTRL_RXD_W_SE | | |
3639 | SWAPPER_CTRL_RXF_W_FE | | |
3640 | SWAPPER_CTRL_XMSI_FE | | |
3641 | SWAPPER_CTRL_STATS_FE | | |
3642 | SWAPPER_CTRL_STATS_SE); | |
eaae7f72 | 3643 | if (sp->config.intr_type == INTA) |
cc6e7c44 | 3644 | val64 |= SWAPPER_CTRL_XMSI_SE; |
1da177e4 LT |
3645 | writeq(val64, &bar0->swapper_ctrl); |
3646 | #endif | |
3647 | val64 = readq(&bar0->swapper_ctrl); | |
3648 | ||
20346722 | 3649 | /* |
3650 | * Verifying if endian settings are accurate by reading a | |
1da177e4 LT |
3651 | * feedback register. |
3652 | */ | |
3653 | val64 = readq(&bar0->pif_rd_swapper_fb); | |
3654 | if (val64 != 0x0123456789ABCDEFULL) { | |
3655 | /* Endian settings are incorrect, calls for another dekko. */ | |
9e39f7c5 JP |
3656 | DBG_PRINT(ERR_DBG, |
3657 | "%s: Endian settings are wrong, feedback read %llx\n", | |
3658 | dev->name, (unsigned long long)val64); | |
1da177e4 LT |
3659 | return FAILURE; |
3660 | } | |
3661 | ||
3662 | return SUCCESS; | |
3663 | } | |
3664 | ||
1ee6dd77 | 3665 | static int wait_for_msix_trans(struct s2io_nic *nic, int i) |
cc6e7c44 | 3666 | { |
1ee6dd77 | 3667 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
cc6e7c44 RA |
3668 | u64 val64; |
3669 | int ret = 0, cnt = 0; | |
3670 | ||
3671 | do { | |
3672 | val64 = readq(&bar0->xmsi_access); | |
b7b5a128 | 3673 | if (!(val64 & s2BIT(15))) |
cc6e7c44 RA |
3674 | break; |
3675 | mdelay(1); | |
3676 | cnt++; | |
d44570e4 | 3677 | } while (cnt < 5); |
cc6e7c44 RA |
3678 | if (cnt == 5) { |
3679 | DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i); | |
3680 | ret = 1; | |
3681 | } | |
3682 | ||
3683 | return ret; | |
3684 | } | |
3685 | ||
1ee6dd77 | 3686 | static void restore_xmsi_data(struct s2io_nic *nic) |
cc6e7c44 | 3687 | { |
1ee6dd77 | 3688 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
cc6e7c44 | 3689 | u64 val64; |
f61e0a35 SH |
3690 | int i, msix_index; |
3691 | ||
f61e0a35 SH |
3692 | if (nic->device_type == XFRAME_I_DEVICE) |
3693 | return; | |
cc6e7c44 | 3694 | |
d44570e4 JP |
3695 | for (i = 0; i < MAX_REQUESTED_MSI_X; i++) { |
3696 | msix_index = (i) ? ((i-1) * 8 + 1) : 0; | |
cc6e7c44 RA |
3697 | writeq(nic->msix_info[i].addr, &bar0->xmsi_address); |
3698 | writeq(nic->msix_info[i].data, &bar0->xmsi_data); | |
f61e0a35 | 3699 | val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6)); |
cc6e7c44 | 3700 | writeq(val64, &bar0->xmsi_access); |
f61e0a35 | 3701 | if (wait_for_msix_trans(nic, msix_index)) { |
9e39f7c5 JP |
3702 | DBG_PRINT(ERR_DBG, "%s: index: %d failed\n", |
3703 | __func__, msix_index); | |
cc6e7c44 RA |
3704 | continue; |
3705 | } | |
3706 | } | |
3707 | } | |
3708 | ||
1ee6dd77 | 3709 | static void store_xmsi_data(struct s2io_nic *nic) |
cc6e7c44 | 3710 | { |
1ee6dd77 | 3711 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
cc6e7c44 | 3712 | u64 val64, addr, data; |
f61e0a35 SH |
3713 | int i, msix_index; |
3714 | ||
3715 | if (nic->device_type == XFRAME_I_DEVICE) | |
3716 | return; | |
cc6e7c44 RA |
3717 | |
3718 | /* Store and display */ | |
d44570e4 JP |
3719 | for (i = 0; i < MAX_REQUESTED_MSI_X; i++) { |
3720 | msix_index = (i) ? ((i-1) * 8 + 1) : 0; | |
f61e0a35 | 3721 | val64 = (s2BIT(15) | vBIT(msix_index, 26, 6)); |
cc6e7c44 | 3722 | writeq(val64, &bar0->xmsi_access); |
f61e0a35 | 3723 | if (wait_for_msix_trans(nic, msix_index)) { |
9e39f7c5 JP |
3724 | DBG_PRINT(ERR_DBG, "%s: index: %d failed\n", |
3725 | __func__, msix_index); | |
cc6e7c44 RA |
3726 | continue; |
3727 | } | |
3728 | addr = readq(&bar0->xmsi_address); | |
3729 | data = readq(&bar0->xmsi_data); | |
3730 | if (addr && data) { | |
3731 | nic->msix_info[i].addr = addr; | |
3732 | nic->msix_info[i].data = data; | |
3733 | } | |
3734 | } | |
3735 | } | |
3736 | ||
1ee6dd77 | 3737 | static int s2io_enable_msi_x(struct s2io_nic *nic) |
cc6e7c44 | 3738 | { |
1ee6dd77 | 3739 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
ac731ab6 | 3740 | u64 rx_mat; |
cc6e7c44 RA |
3741 | u16 msi_control; /* Temp variable */ |
3742 | int ret, i, j, msix_indx = 1; | |
4f870320 | 3743 | int size; |
ffb5df6c JP |
3744 | struct stat_block *stats = nic->mac_control.stats_info; |
3745 | struct swStat *swstats = &stats->sw_stat; | |
cc6e7c44 | 3746 | |
4f870320 | 3747 | size = nic->num_entries * sizeof(struct msix_entry); |
44364a03 | 3748 | nic->entries = kzalloc(size, GFP_KERNEL); |
bd684e43 | 3749 | if (!nic->entries) { |
d44570e4 JP |
3750 | DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", |
3751 | __func__); | |
ffb5df6c | 3752 | swstats->mem_alloc_fail_cnt++; |
cc6e7c44 RA |
3753 | return -ENOMEM; |
3754 | } | |
ffb5df6c | 3755 | swstats->mem_allocated += size; |
f61e0a35 | 3756 | |
4f870320 | 3757 | size = nic->num_entries * sizeof(struct s2io_msix_entry); |
44364a03 | 3758 | nic->s2io_entries = kzalloc(size, GFP_KERNEL); |
bd684e43 | 3759 | if (!nic->s2io_entries) { |
8a4bdbaa | 3760 | DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", |
d44570e4 | 3761 | __func__); |
ffb5df6c | 3762 | swstats->mem_alloc_fail_cnt++; |
cc6e7c44 | 3763 | kfree(nic->entries); |
ffb5df6c | 3764 | swstats->mem_freed |
f61e0a35 | 3765 | += (nic->num_entries * sizeof(struct msix_entry)); |
cc6e7c44 RA |
3766 | return -ENOMEM; |
3767 | } | |
ffb5df6c | 3768 | swstats->mem_allocated += size; |
cc6e7c44 | 3769 | |
ac731ab6 SH |
3770 | nic->entries[0].entry = 0; |
3771 | nic->s2io_entries[0].entry = 0; | |
3772 | nic->s2io_entries[0].in_use = MSIX_FLG; | |
3773 | nic->s2io_entries[0].type = MSIX_ALARM_TYPE; | |
3774 | nic->s2io_entries[0].arg = &nic->mac_control.fifos; | |
3775 | ||
f61e0a35 SH |
3776 | for (i = 1; i < nic->num_entries; i++) { |
3777 | nic->entries[i].entry = ((i - 1) * 8) + 1; | |
3778 | nic->s2io_entries[i].entry = ((i - 1) * 8) + 1; | |
cc6e7c44 RA |
3779 | nic->s2io_entries[i].arg = NULL; |
3780 | nic->s2io_entries[i].in_use = 0; | |
3781 | } | |
3782 | ||
8a4bdbaa | 3783 | rx_mat = readq(&bar0->rx_mat); |
f61e0a35 | 3784 | for (j = 0; j < nic->config.rx_ring_num; j++) { |
8a4bdbaa | 3785 | rx_mat |= RX_MAT_SET(j, msix_indx); |
f61e0a35 SH |
3786 | nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j]; |
3787 | nic->s2io_entries[j+1].type = MSIX_RING_TYPE; | |
3788 | nic->s2io_entries[j+1].in_use = MSIX_FLG; | |
3789 | msix_indx += 8; | |
cc6e7c44 | 3790 | } |
8a4bdbaa | 3791 | writeq(rx_mat, &bar0->rx_mat); |
f61e0a35 | 3792 | readq(&bar0->rx_mat); |
cc6e7c44 | 3793 | |
f61e0a35 | 3794 | ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries); |
c92ca04b | 3795 | /* We fail init if error or we get less vectors than min required */ |
cc6e7c44 | 3796 | if (ret) { |
9e39f7c5 | 3797 | DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n"); |
cc6e7c44 | 3798 | kfree(nic->entries); |
ffb5df6c JP |
3799 | swstats->mem_freed += nic->num_entries * |
3800 | sizeof(struct msix_entry); | |
cc6e7c44 | 3801 | kfree(nic->s2io_entries); |
ffb5df6c JP |
3802 | swstats->mem_freed += nic->num_entries * |
3803 | sizeof(struct s2io_msix_entry); | |
cc6e7c44 RA |
3804 | nic->entries = NULL; |
3805 | nic->s2io_entries = NULL; | |
3806 | return -ENOMEM; | |
3807 | } | |
3808 | ||
3809 | /* | |
3810 | * To enable MSI-X, MSI also needs to be enabled, due to a bug | |
3811 | * in the herc NIC. (Temp change, needs to be removed later) | |
3812 | */ | |
3813 | pci_read_config_word(nic->pdev, 0x42, &msi_control); | |
3814 | msi_control |= 0x1; /* Enable MSI */ | |
3815 | pci_write_config_word(nic->pdev, 0x42, msi_control); | |
3816 | ||
3817 | return 0; | |
3818 | } | |
3819 | ||
8abc4d5b | 3820 | /* Handle software interrupt used during MSI(X) test */ |
33390a70 | 3821 | static irqreturn_t s2io_test_intr(int irq, void *dev_id) |
8abc4d5b SS |
3822 | { |
3823 | struct s2io_nic *sp = dev_id; | |
3824 | ||
3825 | sp->msi_detected = 1; | |
3826 | wake_up(&sp->msi_wait); | |
3827 | ||
3828 | return IRQ_HANDLED; | |
3829 | } | |
3830 | ||
3831 | /* Test interrupt path by forcing a a software IRQ */ | |
33390a70 | 3832 | static int s2io_test_msi(struct s2io_nic *sp) |
8abc4d5b SS |
3833 | { |
3834 | struct pci_dev *pdev = sp->pdev; | |
3835 | struct XENA_dev_config __iomem *bar0 = sp->bar0; | |
3836 | int err; | |
3837 | u64 val64, saved64; | |
3838 | ||
3839 | err = request_irq(sp->entries[1].vector, s2io_test_intr, 0, | |
d44570e4 | 3840 | sp->name, sp); |
8abc4d5b SS |
3841 | if (err) { |
3842 | DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n", | |
d44570e4 | 3843 | sp->dev->name, pci_name(pdev), pdev->irq); |
8abc4d5b SS |
3844 | return err; |
3845 | } | |
3846 | ||
d44570e4 | 3847 | init_waitqueue_head(&sp->msi_wait); |
8abc4d5b SS |
3848 | sp->msi_detected = 0; |
3849 | ||
3850 | saved64 = val64 = readq(&bar0->scheduled_int_ctrl); | |
3851 | val64 |= SCHED_INT_CTRL_ONE_SHOT; | |
3852 | val64 |= SCHED_INT_CTRL_TIMER_EN; | |
3853 | val64 |= SCHED_INT_CTRL_INT2MSI(1); | |
3854 | writeq(val64, &bar0->scheduled_int_ctrl); | |
3855 | ||
3856 | wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10); | |
3857 | ||
3858 | if (!sp->msi_detected) { | |
3859 | /* MSI(X) test failed, go back to INTx mode */ | |
2450022a | 3860 | DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated " |
9e39f7c5 JP |
3861 | "using MSI(X) during test\n", |
3862 | sp->dev->name, pci_name(pdev)); | |
8abc4d5b SS |
3863 | |
3864 | err = -EOPNOTSUPP; | |
3865 | } | |
3866 | ||
3867 | free_irq(sp->entries[1].vector, sp); | |
3868 | ||
3869 | writeq(saved64, &bar0->scheduled_int_ctrl); | |
3870 | ||
3871 | return err; | |
3872 | } | |
18b2b7bd SH |
3873 | |
3874 | static void remove_msix_isr(struct s2io_nic *sp) | |
3875 | { | |
3876 | int i; | |
3877 | u16 msi_control; | |
3878 | ||
f61e0a35 | 3879 | for (i = 0; i < sp->num_entries; i++) { |
d44570e4 | 3880 | if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) { |
18b2b7bd SH |
3881 | int vector = sp->entries[i].vector; |
3882 | void *arg = sp->s2io_entries[i].arg; | |
3883 | free_irq(vector, arg); | |
3884 | } | |
3885 | } | |
3886 | ||
3887 | kfree(sp->entries); | |
3888 | kfree(sp->s2io_entries); | |
3889 | sp->entries = NULL; | |
3890 | sp->s2io_entries = NULL; | |
3891 | ||
3892 | pci_read_config_word(sp->pdev, 0x42, &msi_control); | |
3893 | msi_control &= 0xFFFE; /* Disable MSI */ | |
3894 | pci_write_config_word(sp->pdev, 0x42, msi_control); | |
3895 | ||
3896 | pci_disable_msix(sp->pdev); | |
3897 | } | |
3898 | ||
3899 | static void remove_inta_isr(struct s2io_nic *sp) | |
3900 | { | |
3901 | struct net_device *dev = sp->dev; | |
3902 | ||
3903 | free_irq(sp->pdev->irq, dev); | |
3904 | } | |
3905 | ||
1da177e4 LT |
3906 | /* ********************************************************* * |
3907 | * Functions defined below concern the OS part of the driver * | |
3908 | * ********************************************************* */ | |
3909 | ||
20346722 | 3910 | /** |
1da177e4 LT |
3911 | * s2io_open - open entry point of the driver |
3912 | * @dev : pointer to the device structure. | |
3913 | * Description: | |
3914 | * This function is the open entry point of the driver. It mainly calls a | |
3915 | * function to allocate Rx buffers and inserts them into the buffer | |
20346722 | 3916 | * descriptors and then enables the Rx part of the NIC. |
1da177e4 LT |
3917 | * Return value: |
3918 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
3919 | * file on failure. | |
3920 | */ | |
3921 | ||
ac1f60db | 3922 | static int s2io_open(struct net_device *dev) |
1da177e4 | 3923 | { |
4cf1653a | 3924 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c | 3925 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
1da177e4 LT |
3926 | int err = 0; |
3927 | ||
20346722 | 3928 | /* |
3929 | * Make sure you have link off by default every time | |
1da177e4 LT |
3930 | * Nic is initialized |
3931 | */ | |
3932 | netif_carrier_off(dev); | |
0b1f7ebe | 3933 | sp->last_link_state = 0; |
1da177e4 LT |
3934 | |
3935 | /* Initialize H/W and enable interrupts */ | |
c92ca04b AR |
3936 | err = s2io_card_up(sp); |
3937 | if (err) { | |
1da177e4 LT |
3938 | DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", |
3939 | dev->name); | |
e6a8fee2 | 3940 | goto hw_init_failed; |
1da177e4 LT |
3941 | } |
3942 | ||
2fd37688 | 3943 | if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) { |
1da177e4 | 3944 | DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n"); |
e6a8fee2 | 3945 | s2io_card_down(sp); |
20346722 | 3946 | err = -ENODEV; |
e6a8fee2 | 3947 | goto hw_init_failed; |
1da177e4 | 3948 | } |
3a3d5756 | 3949 | s2io_start_all_tx_queue(sp); |
1da177e4 | 3950 | return 0; |
20346722 | 3951 | |
20346722 | 3952 | hw_init_failed: |
eaae7f72 | 3953 | if (sp->config.intr_type == MSI_X) { |
491976b2 | 3954 | if (sp->entries) { |
cc6e7c44 | 3955 | kfree(sp->entries); |
ffb5df6c JP |
3956 | swstats->mem_freed += sp->num_entries * |
3957 | sizeof(struct msix_entry); | |
491976b2 SH |
3958 | } |
3959 | if (sp->s2io_entries) { | |
cc6e7c44 | 3960 | kfree(sp->s2io_entries); |
ffb5df6c JP |
3961 | swstats->mem_freed += sp->num_entries * |
3962 | sizeof(struct s2io_msix_entry); | |
491976b2 | 3963 | } |
cc6e7c44 | 3964 | } |
20346722 | 3965 | return err; |
1da177e4 LT |
3966 | } |
3967 | ||
3968 | /** | |
3969 | * s2io_close -close entry point of the driver | |
3970 | * @dev : device pointer. | |
3971 | * Description: | |
3972 | * This is the stop entry point of the driver. It needs to undo exactly | |
3973 | * whatever was done by the open entry point,thus it's usually referred to | |
3974 | * as the close function.Among other things this function mainly stops the | |
3975 | * Rx side of the NIC and frees all the Rx buffers in the Rx rings. | |
3976 | * Return value: | |
3977 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
3978 | * file on failure. | |
3979 | */ | |
3980 | ||
ac1f60db | 3981 | static int s2io_close(struct net_device *dev) |
1da177e4 | 3982 | { |
4cf1653a | 3983 | struct s2io_nic *sp = netdev_priv(dev); |
faa4f796 SH |
3984 | struct config_param *config = &sp->config; |
3985 | u64 tmp64; | |
3986 | int offset; | |
cc6e7c44 | 3987 | |
9f74ffde | 3988 | /* Return if the device is already closed * |
d44570e4 JP |
3989 | * Can happen when s2io_card_up failed in change_mtu * |
3990 | */ | |
9f74ffde SH |
3991 | if (!is_s2io_card_up(sp)) |
3992 | return 0; | |
3993 | ||
3a3d5756 | 3994 | s2io_stop_all_tx_queue(sp); |
faa4f796 SH |
3995 | /* delete all populated mac entries */ |
3996 | for (offset = 1; offset < config->max_mc_addr; offset++) { | |
3997 | tmp64 = do_s2io_read_unicast_mc(sp, offset); | |
3998 | if (tmp64 != S2IO_DISABLE_MAC_ENTRY) | |
3999 | do_s2io_delete_unicast_mc(sp, tmp64); | |
4000 | } | |
4001 | ||
e6a8fee2 | 4002 | s2io_card_down(sp); |
cc6e7c44 | 4003 | |
1da177e4 LT |
4004 | return 0; |
4005 | } | |
4006 | ||
4007 | /** | |
4008 | * s2io_xmit - Tx entry point of te driver | |
4009 | * @skb : the socket buffer containing the Tx data. | |
4010 | * @dev : device pointer. | |
4011 | * Description : | |
4012 | * This function is the Tx entry point of the driver. S2IO NIC supports | |
4013 | * certain protocol assist features on Tx side, namely CSO, S/G, LSO. | |
25985edc | 4014 | * NOTE: when device can't queue the pkt,just the trans_start variable will |
1da177e4 LT |
4015 | * not be upadted. |
4016 | * Return value: | |
4017 | * 0 on success & 1 on failure. | |
4018 | */ | |
4019 | ||
61357325 | 4020 | static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 4021 | { |
4cf1653a | 4022 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
4023 | u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off; |
4024 | register u64 val64; | |
1ee6dd77 RB |
4025 | struct TxD *txdp; |
4026 | struct TxFIFO_element __iomem *tx_fifo; | |
2fda096d | 4027 | unsigned long flags = 0; |
be3a6b02 | 4028 | u16 vlan_tag = 0; |
2fda096d | 4029 | struct fifo_info *fifo = NULL; |
6cfc482b | 4030 | int do_spin_lock = 1; |
75c30b13 | 4031 | int offload_type; |
6cfc482b | 4032 | int enable_per_list_interrupt = 0; |
ffb5df6c JP |
4033 | struct config_param *config = &sp->config; |
4034 | struct mac_info *mac_control = &sp->mac_control; | |
4035 | struct stat_block *stats = mac_control->stats_info; | |
4036 | struct swStat *swstats = &stats->sw_stat; | |
1da177e4 | 4037 | |
20346722 | 4038 | DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name); |
491976b2 SH |
4039 | |
4040 | if (unlikely(skb->len <= 0)) { | |
9e39f7c5 | 4041 | DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name); |
491976b2 | 4042 | dev_kfree_skb_any(skb); |
6ed10654 | 4043 | return NETDEV_TX_OK; |
2fda096d | 4044 | } |
491976b2 | 4045 | |
92b84437 | 4046 | if (!is_s2io_card_up(sp)) { |
20346722 | 4047 | DBG_PRINT(TX_DBG, "%s: Card going down for reset\n", |
1da177e4 | 4048 | dev->name); |
20346722 | 4049 | dev_kfree_skb(skb); |
6ed10654 | 4050 | return NETDEV_TX_OK; |
1da177e4 LT |
4051 | } |
4052 | ||
4053 | queue = 0; | |
eab6d18d | 4054 | if (vlan_tx_tag_present(skb)) |
be3a6b02 | 4055 | vlan_tag = vlan_tx_tag_get(skb); |
6cfc482b SH |
4056 | if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) { |
4057 | if (skb->protocol == htons(ETH_P_IP)) { | |
4058 | struct iphdr *ip; | |
4059 | struct tcphdr *th; | |
4060 | ip = ip_hdr(skb); | |
4061 | ||
56f8a75c | 4062 | if (!ip_is_fragment(ip)) { |
6cfc482b | 4063 | th = (struct tcphdr *)(((unsigned char *)ip) + |
d44570e4 | 4064 | ip->ihl*4); |
6cfc482b SH |
4065 | |
4066 | if (ip->protocol == IPPROTO_TCP) { | |
4067 | queue_len = sp->total_tcp_fifos; | |
4068 | queue = (ntohs(th->source) + | |
d44570e4 JP |
4069 | ntohs(th->dest)) & |
4070 | sp->fifo_selector[queue_len - 1]; | |
6cfc482b SH |
4071 | if (queue >= queue_len) |
4072 | queue = queue_len - 1; | |
4073 | } else if (ip->protocol == IPPROTO_UDP) { | |
4074 | queue_len = sp->total_udp_fifos; | |
4075 | queue = (ntohs(th->source) + | |
d44570e4 JP |
4076 | ntohs(th->dest)) & |
4077 | sp->fifo_selector[queue_len - 1]; | |
6cfc482b SH |
4078 | if (queue >= queue_len) |
4079 | queue = queue_len - 1; | |
4080 | queue += sp->udp_fifo_idx; | |
4081 | if (skb->len > 1024) | |
4082 | enable_per_list_interrupt = 1; | |
4083 | do_spin_lock = 0; | |
4084 | } | |
4085 | } | |
4086 | } | |
4087 | } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING) | |
4088 | /* get fifo number based on skb->priority value */ | |
4089 | queue = config->fifo_mapping | |
d44570e4 | 4090 | [skb->priority & (MAX_TX_FIFOS - 1)]; |
6cfc482b | 4091 | fifo = &mac_control->fifos[queue]; |
3a3d5756 | 4092 | |
6cfc482b SH |
4093 | if (do_spin_lock) |
4094 | spin_lock_irqsave(&fifo->tx_lock, flags); | |
4095 | else { | |
4096 | if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags))) | |
4097 | return NETDEV_TX_LOCKED; | |
4098 | } | |
be3a6b02 | 4099 | |
3a3d5756 SH |
4100 | if (sp->config.multiq) { |
4101 | if (__netif_subqueue_stopped(dev, fifo->fifo_no)) { | |
4102 | spin_unlock_irqrestore(&fifo->tx_lock, flags); | |
4103 | return NETDEV_TX_BUSY; | |
4104 | } | |
b19fa1fa | 4105 | } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) { |
3a3d5756 SH |
4106 | if (netif_queue_stopped(dev)) { |
4107 | spin_unlock_irqrestore(&fifo->tx_lock, flags); | |
4108 | return NETDEV_TX_BUSY; | |
4109 | } | |
4110 | } | |
4111 | ||
d44570e4 JP |
4112 | put_off = (u16)fifo->tx_curr_put_info.offset; |
4113 | get_off = (u16)fifo->tx_curr_get_info.offset; | |
43d620c8 | 4114 | txdp = fifo->list_info[put_off].list_virt_addr; |
20346722 | 4115 | |
2fda096d | 4116 | queue_len = fifo->tx_curr_put_info.fifo_len + 1; |
1da177e4 | 4117 | /* Avoid "put" pointer going beyond "get" pointer */ |
863c11a9 | 4118 | if (txdp->Host_Control || |
d44570e4 | 4119 | ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) { |
776bd20f | 4120 | DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n"); |
3a3d5756 | 4121 | s2io_stop_tx_queue(sp, fifo->fifo_no); |
1da177e4 | 4122 | dev_kfree_skb(skb); |
2fda096d | 4123 | spin_unlock_irqrestore(&fifo->tx_lock, flags); |
6ed10654 | 4124 | return NETDEV_TX_OK; |
1da177e4 | 4125 | } |
0b1f7ebe | 4126 | |
75c30b13 | 4127 | offload_type = s2io_offload_type(skb); |
75c30b13 | 4128 | if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { |
1da177e4 | 4129 | txdp->Control_1 |= TXD_TCP_LSO_EN; |
75c30b13 | 4130 | txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb)); |
1da177e4 | 4131 | } |
84fa7933 | 4132 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
d44570e4 JP |
4133 | txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN | |
4134 | TXD_TX_CKO_TCP_EN | | |
4135 | TXD_TX_CKO_UDP_EN); | |
1da177e4 | 4136 | } |
fed5eccd AR |
4137 | txdp->Control_1 |= TXD_GATHER_CODE_FIRST; |
4138 | txdp->Control_1 |= TXD_LIST_OWN_XENA; | |
2fda096d | 4139 | txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no); |
6cfc482b SH |
4140 | if (enable_per_list_interrupt) |
4141 | if (put_off & (queue_len >> 5)) | |
4142 | txdp->Control_2 |= TXD_INT_TYPE_PER_LIST; | |
3a3d5756 | 4143 | if (vlan_tag) { |
be3a6b02 | 4144 | txdp->Control_2 |= TXD_VLAN_ENABLE; |
4145 | txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag); | |
4146 | } | |
4147 | ||
e743d313 | 4148 | frg_len = skb_headlen(skb); |
75c30b13 | 4149 | if (offload_type == SKB_GSO_UDP) { |
fed5eccd AR |
4150 | int ufo_size; |
4151 | ||
75c30b13 | 4152 | ufo_size = s2io_udp_mss(skb); |
fed5eccd AR |
4153 | ufo_size &= ~7; |
4154 | txdp->Control_1 |= TXD_UFO_EN; | |
4155 | txdp->Control_1 |= TXD_UFO_MSS(ufo_size); | |
4156 | txdp->Control_1 |= TXD_BUFFER0_SIZE(8); | |
4157 | #ifdef __BIG_ENDIAN | |
3459feb8 | 4158 | /* both variants do cpu_to_be64(be32_to_cpu(...)) */ |
2fda096d | 4159 | fifo->ufo_in_band_v[put_off] = |
d44570e4 | 4160 | (__force u64)skb_shinfo(skb)->ip6_frag_id; |
fed5eccd | 4161 | #else |
2fda096d | 4162 | fifo->ufo_in_band_v[put_off] = |
d44570e4 | 4163 | (__force u64)skb_shinfo(skb)->ip6_frag_id << 32; |
fed5eccd | 4164 | #endif |
2fda096d | 4165 | txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v; |
fed5eccd | 4166 | txdp->Buffer_Pointer = pci_map_single(sp->pdev, |
d44570e4 JP |
4167 | fifo->ufo_in_band_v, |
4168 | sizeof(u64), | |
4169 | PCI_DMA_TODEVICE); | |
8d8bb39b | 4170 | if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer)) |
491abf25 | 4171 | goto pci_map_failed; |
fed5eccd | 4172 | txdp++; |
fed5eccd | 4173 | } |
1da177e4 | 4174 | |
d44570e4 JP |
4175 | txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data, |
4176 | frg_len, PCI_DMA_TODEVICE); | |
8d8bb39b | 4177 | if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer)) |
491abf25 VP |
4178 | goto pci_map_failed; |
4179 | ||
d44570e4 | 4180 | txdp->Host_Control = (unsigned long)skb; |
fed5eccd | 4181 | txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len); |
75c30b13 | 4182 | if (offload_type == SKB_GSO_UDP) |
fed5eccd AR |
4183 | txdp->Control_1 |= TXD_UFO_EN; |
4184 | ||
4185 | frg_cnt = skb_shinfo(skb)->nr_frags; | |
1da177e4 LT |
4186 | /* For fragmented SKB. */ |
4187 | for (i = 0; i < frg_cnt; i++) { | |
9e903e08 | 4188 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
0b1f7ebe | 4189 | /* A '0' length fragment will be ignored */ |
9e903e08 | 4190 | if (!skb_frag_size(frag)) |
0b1f7ebe | 4191 | continue; |
1da177e4 | 4192 | txdp++; |
f0d06d82 IC |
4193 | txdp->Buffer_Pointer = (u64)skb_frag_dma_map(&sp->pdev->dev, |
4194 | frag, 0, | |
9e903e08 | 4195 | skb_frag_size(frag), |
5d6bcdfe | 4196 | DMA_TO_DEVICE); |
9e903e08 | 4197 | txdp->Control_1 = TXD_BUFFER0_SIZE(skb_frag_size(frag)); |
75c30b13 | 4198 | if (offload_type == SKB_GSO_UDP) |
fed5eccd | 4199 | txdp->Control_1 |= TXD_UFO_EN; |
1da177e4 LT |
4200 | } |
4201 | txdp->Control_1 |= TXD_GATHER_CODE_LAST; | |
4202 | ||
75c30b13 | 4203 | if (offload_type == SKB_GSO_UDP) |
fed5eccd AR |
4204 | frg_cnt++; /* as Txd0 was used for inband header */ |
4205 | ||
1da177e4 | 4206 | tx_fifo = mac_control->tx_FIFO_start[queue]; |
2fda096d | 4207 | val64 = fifo->list_info[put_off].list_phy_addr; |
1da177e4 LT |
4208 | writeq(val64, &tx_fifo->TxDL_Pointer); |
4209 | ||
4210 | val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST | | |
4211 | TX_FIFO_LAST_LIST); | |
75c30b13 | 4212 | if (offload_type) |
fed5eccd | 4213 | val64 |= TX_FIFO_SPECIAL_FUNC; |
75c30b13 | 4214 | |
1da177e4 LT |
4215 | writeq(val64, &tx_fifo->List_Control); |
4216 | ||
303bcb4b | 4217 | mmiowb(); |
4218 | ||
1da177e4 | 4219 | put_off++; |
2fda096d | 4220 | if (put_off == fifo->tx_curr_put_info.fifo_len + 1) |
863c11a9 | 4221 | put_off = 0; |
2fda096d | 4222 | fifo->tx_curr_put_info.offset = put_off; |
1da177e4 LT |
4223 | |
4224 | /* Avoid "put" pointer going beyond "get" pointer */ | |
863c11a9 | 4225 | if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) { |
ffb5df6c | 4226 | swstats->fifo_full_cnt++; |
1da177e4 LT |
4227 | DBG_PRINT(TX_DBG, |
4228 | "No free TxDs for xmit, Put: 0x%x Get:0x%x\n", | |
4229 | put_off, get_off); | |
3a3d5756 | 4230 | s2io_stop_tx_queue(sp, fifo->fifo_no); |
1da177e4 | 4231 | } |
ffb5df6c | 4232 | swstats->mem_allocated += skb->truesize; |
2fda096d | 4233 | spin_unlock_irqrestore(&fifo->tx_lock, flags); |
1da177e4 | 4234 | |
f6f4bfa3 SH |
4235 | if (sp->config.intr_type == MSI_X) |
4236 | tx_intr_handler(fifo); | |
4237 | ||
6ed10654 | 4238 | return NETDEV_TX_OK; |
ffb5df6c | 4239 | |
491abf25 | 4240 | pci_map_failed: |
ffb5df6c | 4241 | swstats->pci_map_fail_cnt++; |
3a3d5756 | 4242 | s2io_stop_tx_queue(sp, fifo->fifo_no); |
ffb5df6c | 4243 | swstats->mem_freed += skb->truesize; |
491abf25 | 4244 | dev_kfree_skb(skb); |
2fda096d | 4245 | spin_unlock_irqrestore(&fifo->tx_lock, flags); |
6ed10654 | 4246 | return NETDEV_TX_OK; |
1da177e4 LT |
4247 | } |
4248 | ||
25fff88e | 4249 | static void |
4250 | s2io_alarm_handle(unsigned long data) | |
4251 | { | |
1ee6dd77 | 4252 | struct s2io_nic *sp = (struct s2io_nic *)data; |
8116f3cf | 4253 | struct net_device *dev = sp->dev; |
25fff88e | 4254 | |
8116f3cf | 4255 | s2io_handle_errors(dev); |
25fff88e | 4256 | mod_timer(&sp->alarm_timer, jiffies + HZ / 2); |
4257 | } | |
4258 | ||
7d12e780 | 4259 | static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id) |
cc6e7c44 | 4260 | { |
1ee6dd77 RB |
4261 | struct ring_info *ring = (struct ring_info *)dev_id; |
4262 | struct s2io_nic *sp = ring->nic; | |
f61e0a35 | 4263 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
cc6e7c44 | 4264 | |
f61e0a35 | 4265 | if (unlikely(!is_s2io_card_up(sp))) |
92b84437 | 4266 | return IRQ_HANDLED; |
92b84437 | 4267 | |
f61e0a35 | 4268 | if (sp->config.napi) { |
1a79d1c3 AV |
4269 | u8 __iomem *addr = NULL; |
4270 | u8 val8 = 0; | |
f61e0a35 | 4271 | |
1a79d1c3 | 4272 | addr = (u8 __iomem *)&bar0->xmsi_mask_reg; |
f61e0a35 SH |
4273 | addr += (7 - ring->ring_no); |
4274 | val8 = (ring->ring_no == 0) ? 0x7f : 0xff; | |
4275 | writeb(val8, addr); | |
4276 | val8 = readb(addr); | |
288379f0 | 4277 | napi_schedule(&ring->napi); |
f61e0a35 SH |
4278 | } else { |
4279 | rx_intr_handler(ring, 0); | |
8d8bb39b | 4280 | s2io_chk_rx_buffers(sp, ring); |
f61e0a35 | 4281 | } |
7d3d0439 | 4282 | |
cc6e7c44 RA |
4283 | return IRQ_HANDLED; |
4284 | } | |
4285 | ||
7d12e780 | 4286 | static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id) |
cc6e7c44 | 4287 | { |
ac731ab6 SH |
4288 | int i; |
4289 | struct fifo_info *fifos = (struct fifo_info *)dev_id; | |
4290 | struct s2io_nic *sp = fifos->nic; | |
4291 | struct XENA_dev_config __iomem *bar0 = sp->bar0; | |
4292 | struct config_param *config = &sp->config; | |
4293 | u64 reason; | |
cc6e7c44 | 4294 | |
ac731ab6 SH |
4295 | if (unlikely(!is_s2io_card_up(sp))) |
4296 | return IRQ_NONE; | |
4297 | ||
4298 | reason = readq(&bar0->general_int_status); | |
4299 | if (unlikely(reason == S2IO_MINUS_ONE)) | |
4300 | /* Nothing much can be done. Get out */ | |
92b84437 | 4301 | return IRQ_HANDLED; |
92b84437 | 4302 | |
01e16faa SH |
4303 | if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) { |
4304 | writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); | |
ac731ab6 | 4305 | |
01e16faa SH |
4306 | if (reason & GEN_INTR_TXPIC) |
4307 | s2io_txpic_intr_handle(sp); | |
ac731ab6 | 4308 | |
01e16faa SH |
4309 | if (reason & GEN_INTR_TXTRAFFIC) |
4310 | writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); | |
ac731ab6 | 4311 | |
01e16faa SH |
4312 | for (i = 0; i < config->tx_fifo_num; i++) |
4313 | tx_intr_handler(&fifos[i]); | |
ac731ab6 | 4314 | |
01e16faa SH |
4315 | writeq(sp->general_int_mask, &bar0->general_int_mask); |
4316 | readl(&bar0->general_int_status); | |
4317 | return IRQ_HANDLED; | |
4318 | } | |
4319 | /* The interrupt was not raised by us */ | |
4320 | return IRQ_NONE; | |
cc6e7c44 | 4321 | } |
ac731ab6 | 4322 | |
1ee6dd77 | 4323 | static void s2io_txpic_intr_handle(struct s2io_nic *sp) |
a371a07d | 4324 | { |
1ee6dd77 | 4325 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
a371a07d | 4326 | u64 val64; |
4327 | ||
4328 | val64 = readq(&bar0->pic_int_status); | |
4329 | if (val64 & PIC_INT_GPIO) { | |
4330 | val64 = readq(&bar0->gpio_int_reg); | |
4331 | if ((val64 & GPIO_INT_REG_LINK_DOWN) && | |
4332 | (val64 & GPIO_INT_REG_LINK_UP)) { | |
c92ca04b AR |
4333 | /* |
4334 | * This is unstable state so clear both up/down | |
4335 | * interrupt and adapter to re-evaluate the link state. | |
4336 | */ | |
d44570e4 | 4337 | val64 |= GPIO_INT_REG_LINK_DOWN; |
a371a07d | 4338 | val64 |= GPIO_INT_REG_LINK_UP; |
4339 | writeq(val64, &bar0->gpio_int_reg); | |
a371a07d | 4340 | val64 = readq(&bar0->gpio_int_mask); |
c92ca04b AR |
4341 | val64 &= ~(GPIO_INT_MASK_LINK_UP | |
4342 | GPIO_INT_MASK_LINK_DOWN); | |
a371a07d | 4343 | writeq(val64, &bar0->gpio_int_mask); |
d44570e4 | 4344 | } else if (val64 & GPIO_INT_REG_LINK_UP) { |
c92ca04b | 4345 | val64 = readq(&bar0->adapter_status); |
d44570e4 | 4346 | /* Enable Adapter */ |
19a60522 SS |
4347 | val64 = readq(&bar0->adapter_control); |
4348 | val64 |= ADAPTER_CNTL_EN; | |
4349 | writeq(val64, &bar0->adapter_control); | |
4350 | val64 |= ADAPTER_LED_ON; | |
4351 | writeq(val64, &bar0->adapter_control); | |
4352 | if (!sp->device_enabled_once) | |
4353 | sp->device_enabled_once = 1; | |
c92ca04b | 4354 | |
19a60522 SS |
4355 | s2io_link(sp, LINK_UP); |
4356 | /* | |
4357 | * unmask link down interrupt and mask link-up | |
4358 | * intr | |
4359 | */ | |
4360 | val64 = readq(&bar0->gpio_int_mask); | |
4361 | val64 &= ~GPIO_INT_MASK_LINK_DOWN; | |
4362 | val64 |= GPIO_INT_MASK_LINK_UP; | |
4363 | writeq(val64, &bar0->gpio_int_mask); | |
c92ca04b | 4364 | |
d44570e4 | 4365 | } else if (val64 & GPIO_INT_REG_LINK_DOWN) { |
c92ca04b | 4366 | val64 = readq(&bar0->adapter_status); |
19a60522 SS |
4367 | s2io_link(sp, LINK_DOWN); |
4368 | /* Link is down so unmaks link up interrupt */ | |
4369 | val64 = readq(&bar0->gpio_int_mask); | |
4370 | val64 &= ~GPIO_INT_MASK_LINK_UP; | |
4371 | val64 |= GPIO_INT_MASK_LINK_DOWN; | |
4372 | writeq(val64, &bar0->gpio_int_mask); | |
ac1f90d6 SS |
4373 | |
4374 | /* turn off LED */ | |
4375 | val64 = readq(&bar0->adapter_control); | |
d44570e4 | 4376 | val64 = val64 & (~ADAPTER_LED_ON); |
ac1f90d6 | 4377 | writeq(val64, &bar0->adapter_control); |
a371a07d | 4378 | } |
4379 | } | |
c92ca04b | 4380 | val64 = readq(&bar0->gpio_int_mask); |
a371a07d | 4381 | } |
4382 | ||
8116f3cf SS |
4383 | /** |
4384 | * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter | |
4385 | * @value: alarm bits | |
4386 | * @addr: address value | |
4387 | * @cnt: counter variable | |
4388 | * Description: Check for alarm and increment the counter | |
4389 | * Return Value: | |
4390 | * 1 - if alarm bit set | |
4391 | * 0 - if alarm bit is not set | |
4392 | */ | |
d44570e4 JP |
4393 | static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr, |
4394 | unsigned long long *cnt) | |
8116f3cf SS |
4395 | { |
4396 | u64 val64; | |
4397 | val64 = readq(addr); | |
d44570e4 | 4398 | if (val64 & value) { |
8116f3cf SS |
4399 | writeq(val64, addr); |
4400 | (*cnt)++; | |
4401 | return 1; | |
4402 | } | |
4403 | return 0; | |
4404 | ||
4405 | } | |
4406 | ||
4407 | /** | |
4408 | * s2io_handle_errors - Xframe error indication handler | |
4409 | * @nic: device private variable | |
4410 | * Description: Handle alarms such as loss of link, single or | |
4411 | * double ECC errors, critical and serious errors. | |
4412 | * Return Value: | |
4413 | * NONE | |
4414 | */ | |
d44570e4 | 4415 | static void s2io_handle_errors(void *dev_id) |
8116f3cf | 4416 | { |
d44570e4 | 4417 | struct net_device *dev = (struct net_device *)dev_id; |
4cf1653a | 4418 | struct s2io_nic *sp = netdev_priv(dev); |
8116f3cf | 4419 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
d44570e4 | 4420 | u64 temp64 = 0, val64 = 0; |
8116f3cf SS |
4421 | int i = 0; |
4422 | ||
4423 | struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat; | |
4424 | struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat; | |
4425 | ||
92b84437 | 4426 | if (!is_s2io_card_up(sp)) |
8116f3cf SS |
4427 | return; |
4428 | ||
4429 | if (pci_channel_offline(sp->pdev)) | |
4430 | return; | |
4431 | ||
4432 | memset(&sw_stat->ring_full_cnt, 0, | |
d44570e4 | 4433 | sizeof(sw_stat->ring_full_cnt)); |
8116f3cf SS |
4434 | |
4435 | /* Handling the XPAK counters update */ | |
d44570e4 | 4436 | if (stats->xpak_timer_count < 72000) { |
8116f3cf SS |
4437 | /* waiting for an hour */ |
4438 | stats->xpak_timer_count++; | |
4439 | } else { | |
4440 | s2io_updt_xpak_counter(dev); | |
4441 | /* reset the count to zero */ | |
4442 | stats->xpak_timer_count = 0; | |
4443 | } | |
4444 | ||
4445 | /* Handling link status change error Intr */ | |
4446 | if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) { | |
4447 | val64 = readq(&bar0->mac_rmac_err_reg); | |
4448 | writeq(val64, &bar0->mac_rmac_err_reg); | |
4449 | if (val64 & RMAC_LINK_STATE_CHANGE_INT) | |
4450 | schedule_work(&sp->set_link_task); | |
4451 | } | |
4452 | ||
4453 | /* In case of a serious error, the device will be Reset. */ | |
4454 | if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source, | |
d44570e4 | 4455 | &sw_stat->serious_err_cnt)) |
8116f3cf SS |
4456 | goto reset; |
4457 | ||
4458 | /* Check for data parity error */ | |
4459 | if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg, | |
d44570e4 | 4460 | &sw_stat->parity_err_cnt)) |
8116f3cf SS |
4461 | goto reset; |
4462 | ||
4463 | /* Check for ring full counter */ | |
4464 | if (sp->device_type == XFRAME_II_DEVICE) { | |
4465 | val64 = readq(&bar0->ring_bump_counter1); | |
d44570e4 JP |
4466 | for (i = 0; i < 4; i++) { |
4467 | temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); | |
8116f3cf SS |
4468 | temp64 >>= 64 - ((i+1)*16); |
4469 | sw_stat->ring_full_cnt[i] += temp64; | |
4470 | } | |
4471 | ||
4472 | val64 = readq(&bar0->ring_bump_counter2); | |
d44570e4 JP |
4473 | for (i = 0; i < 4; i++) { |
4474 | temp64 = (val64 & vBIT(0xFFFF, (i*16), 16)); | |
8116f3cf | 4475 | temp64 >>= 64 - ((i+1)*16); |
d44570e4 | 4476 | sw_stat->ring_full_cnt[i+4] += temp64; |
8116f3cf SS |
4477 | } |
4478 | } | |
4479 | ||
4480 | val64 = readq(&bar0->txdma_int_status); | |
4481 | /*check for pfc_err*/ | |
4482 | if (val64 & TXDMA_PFC_INT) { | |
d44570e4 JP |
4483 | if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM | |
4484 | PFC_MISC_0_ERR | PFC_MISC_1_ERR | | |
4485 | PFC_PCIX_ERR, | |
4486 | &bar0->pfc_err_reg, | |
4487 | &sw_stat->pfc_err_cnt)) | |
8116f3cf | 4488 | goto reset; |
d44570e4 JP |
4489 | do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, |
4490 | &bar0->pfc_err_reg, | |
4491 | &sw_stat->pfc_err_cnt); | |
8116f3cf SS |
4492 | } |
4493 | ||
4494 | /*check for tda_err*/ | |
4495 | if (val64 & TXDMA_TDA_INT) { | |
d44570e4 JP |
4496 | if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | |
4497 | TDA_SM0_ERR_ALARM | | |
4498 | TDA_SM1_ERR_ALARM, | |
4499 | &bar0->tda_err_reg, | |
4500 | &sw_stat->tda_err_cnt)) | |
8116f3cf SS |
4501 | goto reset; |
4502 | do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR, | |
d44570e4 JP |
4503 | &bar0->tda_err_reg, |
4504 | &sw_stat->tda_err_cnt); | |
8116f3cf SS |
4505 | } |
4506 | /*check for pcc_err*/ | |
4507 | if (val64 & TXDMA_PCC_INT) { | |
d44570e4 JP |
4508 | if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM | |
4509 | PCC_N_SERR | PCC_6_COF_OV_ERR | | |
4510 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR | | |
4511 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR | | |
4512 | PCC_TXB_ECC_DB_ERR, | |
4513 | &bar0->pcc_err_reg, | |
4514 | &sw_stat->pcc_err_cnt)) | |
8116f3cf SS |
4515 | goto reset; |
4516 | do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR, | |
d44570e4 JP |
4517 | &bar0->pcc_err_reg, |
4518 | &sw_stat->pcc_err_cnt); | |
8116f3cf SS |
4519 | } |
4520 | ||
4521 | /*check for tti_err*/ | |
4522 | if (val64 & TXDMA_TTI_INT) { | |
d44570e4 JP |
4523 | if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, |
4524 | &bar0->tti_err_reg, | |
4525 | &sw_stat->tti_err_cnt)) | |
8116f3cf SS |
4526 | goto reset; |
4527 | do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR, | |
d44570e4 JP |
4528 | &bar0->tti_err_reg, |
4529 | &sw_stat->tti_err_cnt); | |
8116f3cf SS |
4530 | } |
4531 | ||
4532 | /*check for lso_err*/ | |
4533 | if (val64 & TXDMA_LSO_INT) { | |
d44570e4 JP |
4534 | if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT | |
4535 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM, | |
4536 | &bar0->lso_err_reg, | |
4537 | &sw_stat->lso_err_cnt)) | |
8116f3cf SS |
4538 | goto reset; |
4539 | do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW, | |
d44570e4 JP |
4540 | &bar0->lso_err_reg, |
4541 | &sw_stat->lso_err_cnt); | |
8116f3cf SS |
4542 | } |
4543 | ||
4544 | /*check for tpa_err*/ | |
4545 | if (val64 & TXDMA_TPA_INT) { | |
d44570e4 JP |
4546 | if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, |
4547 | &bar0->tpa_err_reg, | |
4548 | &sw_stat->tpa_err_cnt)) | |
8116f3cf | 4549 | goto reset; |
d44570e4 JP |
4550 | do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, |
4551 | &bar0->tpa_err_reg, | |
4552 | &sw_stat->tpa_err_cnt); | |
8116f3cf SS |
4553 | } |
4554 | ||
4555 | /*check for sm_err*/ | |
4556 | if (val64 & TXDMA_SM_INT) { | |
d44570e4 JP |
4557 | if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, |
4558 | &bar0->sm_err_reg, | |
4559 | &sw_stat->sm_err_cnt)) | |
8116f3cf SS |
4560 | goto reset; |
4561 | } | |
4562 | ||
4563 | val64 = readq(&bar0->mac_int_status); | |
4564 | if (val64 & MAC_INT_STATUS_TMAC_INT) { | |
4565 | if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR, | |
d44570e4 JP |
4566 | &bar0->mac_tmac_err_reg, |
4567 | &sw_stat->mac_tmac_err_cnt)) | |
8116f3cf | 4568 | goto reset; |
d44570e4 JP |
4569 | do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR | |
4570 | TMAC_DESC_ECC_SG_ERR | | |
4571 | TMAC_DESC_ECC_DB_ERR, | |
4572 | &bar0->mac_tmac_err_reg, | |
4573 | &sw_stat->mac_tmac_err_cnt); | |
8116f3cf SS |
4574 | } |
4575 | ||
4576 | val64 = readq(&bar0->xgxs_int_status); | |
4577 | if (val64 & XGXS_INT_STATUS_TXGXS) { | |
4578 | if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR, | |
d44570e4 JP |
4579 | &bar0->xgxs_txgxs_err_reg, |
4580 | &sw_stat->xgxs_txgxs_err_cnt)) | |
8116f3cf SS |
4581 | goto reset; |
4582 | do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR, | |
d44570e4 JP |
4583 | &bar0->xgxs_txgxs_err_reg, |
4584 | &sw_stat->xgxs_txgxs_err_cnt); | |
8116f3cf SS |
4585 | } |
4586 | ||
4587 | val64 = readq(&bar0->rxdma_int_status); | |
4588 | if (val64 & RXDMA_INT_RC_INT_M) { | |
d44570e4 JP |
4589 | if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | |
4590 | RC_FTC_ECC_DB_ERR | | |
4591 | RC_PRCn_SM_ERR_ALARM | | |
4592 | RC_FTC_SM_ERR_ALARM, | |
4593 | &bar0->rc_err_reg, | |
4594 | &sw_stat->rc_err_cnt)) | |
8116f3cf | 4595 | goto reset; |
d44570e4 JP |
4596 | do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | |
4597 | RC_FTC_ECC_SG_ERR | | |
4598 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg, | |
4599 | &sw_stat->rc_err_cnt); | |
4600 | if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | | |
4601 | PRC_PCI_AB_WR_Rn | | |
4602 | PRC_PCI_AB_F_WR_Rn, | |
4603 | &bar0->prc_pcix_err_reg, | |
4604 | &sw_stat->prc_pcix_err_cnt)) | |
8116f3cf | 4605 | goto reset; |
d44570e4 JP |
4606 | do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | |
4607 | PRC_PCI_DP_WR_Rn | | |
4608 | PRC_PCI_DP_F_WR_Rn, | |
4609 | &bar0->prc_pcix_err_reg, | |
4610 | &sw_stat->prc_pcix_err_cnt); | |
8116f3cf SS |
4611 | } |
4612 | ||
4613 | if (val64 & RXDMA_INT_RPA_INT_M) { | |
4614 | if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR, | |
d44570e4 JP |
4615 | &bar0->rpa_err_reg, |
4616 | &sw_stat->rpa_err_cnt)) | |
8116f3cf SS |
4617 | goto reset; |
4618 | do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, | |
d44570e4 JP |
4619 | &bar0->rpa_err_reg, |
4620 | &sw_stat->rpa_err_cnt); | |
8116f3cf SS |
4621 | } |
4622 | ||
4623 | if (val64 & RXDMA_INT_RDA_INT_M) { | |
d44570e4 JP |
4624 | if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR | |
4625 | RDA_FRM_ECC_DB_N_AERR | | |
4626 | RDA_SM1_ERR_ALARM | | |
4627 | RDA_SM0_ERR_ALARM | | |
4628 | RDA_RXD_ECC_DB_SERR, | |
4629 | &bar0->rda_err_reg, | |
4630 | &sw_stat->rda_err_cnt)) | |
8116f3cf | 4631 | goto reset; |
d44570e4 JP |
4632 | do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | |
4633 | RDA_FRM_ECC_SG_ERR | | |
4634 | RDA_MISC_ERR | | |
4635 | RDA_PCIX_ERR, | |
4636 | &bar0->rda_err_reg, | |
4637 | &sw_stat->rda_err_cnt); | |
8116f3cf SS |
4638 | } |
4639 | ||
4640 | if (val64 & RXDMA_INT_RTI_INT_M) { | |
d44570e4 JP |
4641 | if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, |
4642 | &bar0->rti_err_reg, | |
4643 | &sw_stat->rti_err_cnt)) | |
8116f3cf SS |
4644 | goto reset; |
4645 | do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR, | |
d44570e4 JP |
4646 | &bar0->rti_err_reg, |
4647 | &sw_stat->rti_err_cnt); | |
8116f3cf SS |
4648 | } |
4649 | ||
4650 | val64 = readq(&bar0->mac_int_status); | |
4651 | if (val64 & MAC_INT_STATUS_RMAC_INT) { | |
4652 | if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR, | |
d44570e4 JP |
4653 | &bar0->mac_rmac_err_reg, |
4654 | &sw_stat->mac_rmac_err_cnt)) | |
8116f3cf | 4655 | goto reset; |
d44570e4 JP |
4656 | do_s2io_chk_alarm_bit(RMAC_UNUSED_INT | |
4657 | RMAC_SINGLE_ECC_ERR | | |
4658 | RMAC_DOUBLE_ECC_ERR, | |
4659 | &bar0->mac_rmac_err_reg, | |
4660 | &sw_stat->mac_rmac_err_cnt); | |
8116f3cf SS |
4661 | } |
4662 | ||
4663 | val64 = readq(&bar0->xgxs_int_status); | |
4664 | if (val64 & XGXS_INT_STATUS_RXGXS) { | |
4665 | if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, | |
d44570e4 JP |
4666 | &bar0->xgxs_rxgxs_err_reg, |
4667 | &sw_stat->xgxs_rxgxs_err_cnt)) | |
8116f3cf SS |
4668 | goto reset; |
4669 | } | |
4670 | ||
4671 | val64 = readq(&bar0->mc_int_status); | |
d44570e4 JP |
4672 | if (val64 & MC_INT_STATUS_MC_INT) { |
4673 | if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, | |
4674 | &bar0->mc_err_reg, | |
4675 | &sw_stat->mc_err_cnt)) | |
8116f3cf SS |
4676 | goto reset; |
4677 | ||
4678 | /* Handling Ecc errors */ | |
4679 | if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) { | |
4680 | writeq(val64, &bar0->mc_err_reg); | |
4681 | if (val64 & MC_ERR_REG_ECC_ALL_DBL) { | |
4682 | sw_stat->double_ecc_errs++; | |
4683 | if (sp->device_type != XFRAME_II_DEVICE) { | |
4684 | /* | |
4685 | * Reset XframeI only if critical error | |
4686 | */ | |
4687 | if (val64 & | |
d44570e4 JP |
4688 | (MC_ERR_REG_MIRI_ECC_DB_ERR_0 | |
4689 | MC_ERR_REG_MIRI_ECC_DB_ERR_1)) | |
4690 | goto reset; | |
4691 | } | |
8116f3cf SS |
4692 | } else |
4693 | sw_stat->single_ecc_errs++; | |
4694 | } | |
4695 | } | |
4696 | return; | |
4697 | ||
4698 | reset: | |
3a3d5756 | 4699 | s2io_stop_all_tx_queue(sp); |
8116f3cf SS |
4700 | schedule_work(&sp->rst_timer_task); |
4701 | sw_stat->soft_reset_cnt++; | |
8116f3cf SS |
4702 | } |
4703 | ||
1da177e4 LT |
4704 | /** |
4705 | * s2io_isr - ISR handler of the device . | |
4706 | * @irq: the irq of the device. | |
4707 | * @dev_id: a void pointer to the dev structure of the NIC. | |
20346722 | 4708 | * Description: This function is the ISR handler of the device. It |
4709 | * identifies the reason for the interrupt and calls the relevant | |
4710 | * service routines. As a contongency measure, this ISR allocates the | |
1da177e4 LT |
4711 | * recv buffers, if their numbers are below the panic value which is |
4712 | * presently set to 25% of the original number of rcv buffers allocated. | |
4713 | * Return value: | |
20346722 | 4714 | * IRQ_HANDLED: will be returned if IRQ was handled by this routine |
1da177e4 LT |
4715 | * IRQ_NONE: will be returned if interrupt is not from our device |
4716 | */ | |
7d12e780 | 4717 | static irqreturn_t s2io_isr(int irq, void *dev_id) |
1da177e4 | 4718 | { |
d44570e4 | 4719 | struct net_device *dev = (struct net_device *)dev_id; |
4cf1653a | 4720 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 4721 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
20346722 | 4722 | int i; |
19a60522 | 4723 | u64 reason = 0; |
1ee6dd77 | 4724 | struct mac_info *mac_control; |
1da177e4 LT |
4725 | struct config_param *config; |
4726 | ||
d796fdb7 LV |
4727 | /* Pretend we handled any irq's from a disconnected card */ |
4728 | if (pci_channel_offline(sp->pdev)) | |
4729 | return IRQ_NONE; | |
4730 | ||
596c5c97 | 4731 | if (!is_s2io_card_up(sp)) |
92b84437 | 4732 | return IRQ_NONE; |
92b84437 | 4733 | |
1da177e4 | 4734 | config = &sp->config; |
ffb5df6c | 4735 | mac_control = &sp->mac_control; |
1da177e4 | 4736 | |
20346722 | 4737 | /* |
1da177e4 LT |
4738 | * Identify the cause for interrupt and call the appropriate |
4739 | * interrupt handler. Causes for the interrupt could be; | |
4740 | * 1. Rx of packet. | |
4741 | * 2. Tx complete. | |
4742 | * 3. Link down. | |
1da177e4 LT |
4743 | */ |
4744 | reason = readq(&bar0->general_int_status); | |
4745 | ||
d44570e4 JP |
4746 | if (unlikely(reason == S2IO_MINUS_ONE)) |
4747 | return IRQ_HANDLED; /* Nothing much can be done. Get out */ | |
5d3213cc | 4748 | |
d44570e4 JP |
4749 | if (reason & |
4750 | (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) { | |
596c5c97 SS |
4751 | writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); |
4752 | ||
4753 | if (config->napi) { | |
4754 | if (reason & GEN_INTR_RXTRAFFIC) { | |
288379f0 | 4755 | napi_schedule(&sp->napi); |
f61e0a35 SH |
4756 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask); |
4757 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); | |
4758 | readl(&bar0->rx_traffic_int); | |
db874e65 | 4759 | } |
596c5c97 SS |
4760 | } else { |
4761 | /* | |
4762 | * rx_traffic_int reg is an R1 register, writing all 1's | |
4763 | * will ensure that the actual interrupt causing bit | |
4764 | * get's cleared and hence a read can be avoided. | |
4765 | */ | |
4766 | if (reason & GEN_INTR_RXTRAFFIC) | |
19a60522 | 4767 | writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); |
596c5c97 | 4768 | |
13d866a9 JP |
4769 | for (i = 0; i < config->rx_ring_num; i++) { |
4770 | struct ring_info *ring = &mac_control->rings[i]; | |
4771 | ||
4772 | rx_intr_handler(ring, 0); | |
4773 | } | |
db874e65 | 4774 | } |
596c5c97 | 4775 | |
db874e65 | 4776 | /* |
596c5c97 | 4777 | * tx_traffic_int reg is an R1 register, writing all 1's |
db874e65 SS |
4778 | * will ensure that the actual interrupt causing bit get's |
4779 | * cleared and hence a read can be avoided. | |
4780 | */ | |
596c5c97 SS |
4781 | if (reason & GEN_INTR_TXTRAFFIC) |
4782 | writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); | |
19a60522 | 4783 | |
596c5c97 SS |
4784 | for (i = 0; i < config->tx_fifo_num; i++) |
4785 | tx_intr_handler(&mac_control->fifos[i]); | |
1da177e4 | 4786 | |
596c5c97 SS |
4787 | if (reason & GEN_INTR_TXPIC) |
4788 | s2io_txpic_intr_handle(sp); | |
fe113638 | 4789 | |
596c5c97 SS |
4790 | /* |
4791 | * Reallocate the buffers from the interrupt handler itself. | |
4792 | */ | |
4793 | if (!config->napi) { | |
13d866a9 JP |
4794 | for (i = 0; i < config->rx_ring_num; i++) { |
4795 | struct ring_info *ring = &mac_control->rings[i]; | |
4796 | ||
4797 | s2io_chk_rx_buffers(sp, ring); | |
4798 | } | |
596c5c97 SS |
4799 | } |
4800 | writeq(sp->general_int_mask, &bar0->general_int_mask); | |
4801 | readl(&bar0->general_int_status); | |
20346722 | 4802 | |
596c5c97 | 4803 | return IRQ_HANDLED; |
db874e65 | 4804 | |
d44570e4 | 4805 | } else if (!reason) { |
596c5c97 SS |
4806 | /* The interrupt was not raised by us */ |
4807 | return IRQ_NONE; | |
4808 | } | |
db874e65 | 4809 | |
1da177e4 LT |
4810 | return IRQ_HANDLED; |
4811 | } | |
4812 | ||
7ba013ac | 4813 | /** |
4814 | * s2io_updt_stats - | |
4815 | */ | |
1ee6dd77 | 4816 | static void s2io_updt_stats(struct s2io_nic *sp) |
7ba013ac | 4817 | { |
1ee6dd77 | 4818 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
7ba013ac | 4819 | u64 val64; |
4820 | int cnt = 0; | |
4821 | ||
92b84437 | 4822 | if (is_s2io_card_up(sp)) { |
7ba013ac | 4823 | /* Apprx 30us on a 133 MHz bus */ |
4824 | val64 = SET_UPDT_CLICKS(10) | | |
4825 | STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN; | |
4826 | writeq(val64, &bar0->stat_cfg); | |
4827 | do { | |
4828 | udelay(100); | |
4829 | val64 = readq(&bar0->stat_cfg); | |
b7b5a128 | 4830 | if (!(val64 & s2BIT(0))) |
7ba013ac | 4831 | break; |
4832 | cnt++; | |
4833 | if (cnt == 5) | |
4834 | break; /* Updt failed */ | |
d44570e4 | 4835 | } while (1); |
8a4bdbaa | 4836 | } |
7ba013ac | 4837 | } |
4838 | ||
1da177e4 | 4839 | /** |
20346722 | 4840 | * s2io_get_stats - Updates the device statistics structure. |
1da177e4 LT |
4841 | * @dev : pointer to the device structure. |
4842 | * Description: | |
20346722 | 4843 | * This function updates the device statistics structure in the s2io_nic |
1da177e4 LT |
4844 | * structure and returns a pointer to the same. |
4845 | * Return value: | |
4846 | * pointer to the updated net_device_stats structure. | |
4847 | */ | |
ac1f60db | 4848 | static struct net_device_stats *s2io_get_stats(struct net_device *dev) |
1da177e4 | 4849 | { |
4cf1653a | 4850 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c JP |
4851 | struct mac_info *mac_control = &sp->mac_control; |
4852 | struct stat_block *stats = mac_control->stats_info; | |
4a490432 | 4853 | u64 delta; |
1da177e4 | 4854 | |
7ba013ac | 4855 | /* Configure Stats for immediate updt */ |
4856 | s2io_updt_stats(sp); | |
4857 | ||
4a490432 JM |
4858 | /* A device reset will cause the on-adapter statistics to be zero'ed. |
4859 | * This can be done while running by changing the MTU. To prevent the | |
4860 | * system from having the stats zero'ed, the driver keeps a copy of the | |
4861 | * last update to the system (which is also zero'ed on reset). This | |
4862 | * enables the driver to accurately know the delta between the last | |
4863 | * update and the current update. | |
4864 | */ | |
4865 | delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 | | |
4866 | le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets; | |
4867 | sp->stats.rx_packets += delta; | |
4868 | dev->stats.rx_packets += delta; | |
4869 | ||
4870 | delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 | | |
4871 | le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets; | |
4872 | sp->stats.tx_packets += delta; | |
4873 | dev->stats.tx_packets += delta; | |
4874 | ||
4875 | delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 | | |
4876 | le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes; | |
4877 | sp->stats.rx_bytes += delta; | |
4878 | dev->stats.rx_bytes += delta; | |
4879 | ||
4880 | delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 | | |
4881 | le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes; | |
4882 | sp->stats.tx_bytes += delta; | |
4883 | dev->stats.tx_bytes += delta; | |
4884 | ||
4885 | delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors; | |
4886 | sp->stats.rx_errors += delta; | |
4887 | dev->stats.rx_errors += delta; | |
4888 | ||
4889 | delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 | | |
4890 | le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors; | |
4891 | sp->stats.tx_errors += delta; | |
4892 | dev->stats.tx_errors += delta; | |
4893 | ||
4894 | delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped; | |
4895 | sp->stats.rx_dropped += delta; | |
4896 | dev->stats.rx_dropped += delta; | |
4897 | ||
4898 | delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped; | |
4899 | sp->stats.tx_dropped += delta; | |
4900 | dev->stats.tx_dropped += delta; | |
4901 | ||
4902 | /* The adapter MAC interprets pause frames as multicast packets, but | |
4903 | * does not pass them up. This erroneously increases the multicast | |
4904 | * packet count and needs to be deducted when the multicast frame count | |
4905 | * is queried. | |
4906 | */ | |
4907 | delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 | | |
4908 | le32_to_cpu(stats->rmac_vld_mcst_frms); | |
4909 | delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms); | |
4910 | delta -= sp->stats.multicast; | |
4911 | sp->stats.multicast += delta; | |
4912 | dev->stats.multicast += delta; | |
1da177e4 | 4913 | |
4a490432 JM |
4914 | delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 | |
4915 | le32_to_cpu(stats->rmac_usized_frms)) + | |
4916 | le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors; | |
4917 | sp->stats.rx_length_errors += delta; | |
4918 | dev->stats.rx_length_errors += delta; | |
13d866a9 | 4919 | |
4a490432 JM |
4920 | delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors; |
4921 | sp->stats.rx_crc_errors += delta; | |
4922 | dev->stats.rx_crc_errors += delta; | |
0425b46a | 4923 | |
d44570e4 | 4924 | return &dev->stats; |
1da177e4 LT |
4925 | } |
4926 | ||
4927 | /** | |
4928 | * s2io_set_multicast - entry point for multicast address enable/disable. | |
4929 | * @dev : pointer to the device structure | |
4930 | * Description: | |
20346722 | 4931 | * This function is a driver entry point which gets called by the kernel |
4932 | * whenever multicast addresses must be enabled/disabled. This also gets | |
1da177e4 LT |
4933 | * called to set/reset promiscuous mode. Depending on the deivce flag, we |
4934 | * determine, if multicast address must be enabled or if promiscuous mode | |
4935 | * is to be disabled etc. | |
4936 | * Return value: | |
4937 | * void. | |
4938 | */ | |
4939 | ||
4940 | static void s2io_set_multicast(struct net_device *dev) | |
4941 | { | |
4942 | int i, j, prev_cnt; | |
22bedad3 | 4943 | struct netdev_hw_addr *ha; |
4cf1653a | 4944 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 4945 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 4946 | u64 val64 = 0, multi_mac = 0x010203040506ULL, mask = |
d44570e4 | 4947 | 0xfeffffffffffULL; |
faa4f796 | 4948 | u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0; |
1da177e4 | 4949 | void __iomem *add; |
faa4f796 | 4950 | struct config_param *config = &sp->config; |
1da177e4 LT |
4951 | |
4952 | if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) { | |
4953 | /* Enable all Multicast addresses */ | |
4954 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac), | |
4955 | &bar0->rmac_addr_data0_mem); | |
4956 | writeq(RMAC_ADDR_DATA1_MEM_MASK(mask), | |
4957 | &bar0->rmac_addr_data1_mem); | |
4958 | val64 = RMAC_ADDR_CMD_MEM_WE | | |
d44570e4 JP |
4959 | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
4960 | RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1); | |
1da177e4 LT |
4961 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
4962 | /* Wait till command completes */ | |
c92ca04b | 4963 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
4964 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
4965 | S2IO_BIT_RESET); | |
1da177e4 LT |
4966 | |
4967 | sp->m_cast_flg = 1; | |
faa4f796 | 4968 | sp->all_multi_pos = config->max_mc_addr - 1; |
1da177e4 LT |
4969 | } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) { |
4970 | /* Disable all Multicast addresses */ | |
4971 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), | |
4972 | &bar0->rmac_addr_data0_mem); | |
5e25b9dd | 4973 | writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0), |
4974 | &bar0->rmac_addr_data1_mem); | |
1da177e4 | 4975 | val64 = RMAC_ADDR_CMD_MEM_WE | |
d44570e4 JP |
4976 | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
4977 | RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos); | |
1da177e4 LT |
4978 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
4979 | /* Wait till command completes */ | |
c92ca04b | 4980 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
4981 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
4982 | S2IO_BIT_RESET); | |
1da177e4 LT |
4983 | |
4984 | sp->m_cast_flg = 0; | |
4985 | sp->all_multi_pos = 0; | |
4986 | } | |
4987 | ||
4988 | if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) { | |
4989 | /* Put the NIC into promiscuous mode */ | |
4990 | add = &bar0->mac_cfg; | |
4991 | val64 = readq(&bar0->mac_cfg); | |
4992 | val64 |= MAC_CFG_RMAC_PROM_ENABLE; | |
4993 | ||
4994 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
d44570e4 | 4995 | writel((u32)val64, add); |
1da177e4 LT |
4996 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); |
4997 | writel((u32) (val64 >> 32), (add + 4)); | |
4998 | ||
926930b2 SS |
4999 | if (vlan_tag_strip != 1) { |
5000 | val64 = readq(&bar0->rx_pa_cfg); | |
5001 | val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG; | |
5002 | writeq(val64, &bar0->rx_pa_cfg); | |
cd0fce03 | 5003 | sp->vlan_strip_flag = 0; |
926930b2 SS |
5004 | } |
5005 | ||
1da177e4 LT |
5006 | val64 = readq(&bar0->mac_cfg); |
5007 | sp->promisc_flg = 1; | |
776bd20f | 5008 | DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n", |
1da177e4 LT |
5009 | dev->name); |
5010 | } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) { | |
5011 | /* Remove the NIC from promiscuous mode */ | |
5012 | add = &bar0->mac_cfg; | |
5013 | val64 = readq(&bar0->mac_cfg); | |
5014 | val64 &= ~MAC_CFG_RMAC_PROM_ENABLE; | |
5015 | ||
5016 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); | |
d44570e4 | 5017 | writel((u32)val64, add); |
1da177e4 LT |
5018 | writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); |
5019 | writel((u32) (val64 >> 32), (add + 4)); | |
5020 | ||
926930b2 SS |
5021 | if (vlan_tag_strip != 0) { |
5022 | val64 = readq(&bar0->rx_pa_cfg); | |
5023 | val64 |= RX_PA_CFG_STRIP_VLAN_TAG; | |
5024 | writeq(val64, &bar0->rx_pa_cfg); | |
cd0fce03 | 5025 | sp->vlan_strip_flag = 1; |
926930b2 SS |
5026 | } |
5027 | ||
1da177e4 LT |
5028 | val64 = readq(&bar0->mac_cfg); |
5029 | sp->promisc_flg = 0; | |
9e39f7c5 | 5030 | DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name); |
1da177e4 LT |
5031 | } |
5032 | ||
5033 | /* Update individual M_CAST address list */ | |
4cd24eaf JP |
5034 | if ((!sp->m_cast_flg) && netdev_mc_count(dev)) { |
5035 | if (netdev_mc_count(dev) > | |
faa4f796 | 5036 | (config->max_mc_addr - config->max_mac_addr)) { |
9e39f7c5 JP |
5037 | DBG_PRINT(ERR_DBG, |
5038 | "%s: No more Rx filters can be added - " | |
5039 | "please enable ALL_MULTI instead\n", | |
1da177e4 | 5040 | dev->name); |
1da177e4 LT |
5041 | return; |
5042 | } | |
5043 | ||
5044 | prev_cnt = sp->mc_addr_count; | |
4cd24eaf | 5045 | sp->mc_addr_count = netdev_mc_count(dev); |
1da177e4 LT |
5046 | |
5047 | /* Clear out the previous list of Mc in the H/W. */ | |
5048 | for (i = 0; i < prev_cnt; i++) { | |
5049 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr), | |
5050 | &bar0->rmac_addr_data0_mem); | |
5051 | writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), | |
d44570e4 | 5052 | &bar0->rmac_addr_data1_mem); |
1da177e4 | 5053 | val64 = RMAC_ADDR_CMD_MEM_WE | |
d44570e4 JP |
5054 | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
5055 | RMAC_ADDR_CMD_MEM_OFFSET | |
5056 | (config->mc_start_offset + i); | |
1da177e4 LT |
5057 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
5058 | ||
5059 | /* Wait for command completes */ | |
c92ca04b | 5060 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
5061 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
5062 | S2IO_BIT_RESET)) { | |
9e39f7c5 JP |
5063 | DBG_PRINT(ERR_DBG, |
5064 | "%s: Adding Multicasts failed\n", | |
5065 | dev->name); | |
1da177e4 LT |
5066 | return; |
5067 | } | |
5068 | } | |
5069 | ||
5070 | /* Create the new Rx filter list and update the same in H/W. */ | |
5508590c | 5071 | i = 0; |
22bedad3 | 5072 | netdev_for_each_mc_addr(ha, dev) { |
a7a80d5a | 5073 | mac_addr = 0; |
1da177e4 | 5074 | for (j = 0; j < ETH_ALEN; j++) { |
22bedad3 | 5075 | mac_addr |= ha->addr[j]; |
1da177e4 LT |
5076 | mac_addr <<= 8; |
5077 | } | |
5078 | mac_addr >>= 8; | |
5079 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr), | |
5080 | &bar0->rmac_addr_data0_mem); | |
5081 | writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL), | |
d44570e4 | 5082 | &bar0->rmac_addr_data1_mem); |
1da177e4 | 5083 | val64 = RMAC_ADDR_CMD_MEM_WE | |
d44570e4 JP |
5084 | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
5085 | RMAC_ADDR_CMD_MEM_OFFSET | |
5086 | (i + config->mc_start_offset); | |
1da177e4 LT |
5087 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
5088 | ||
5089 | /* Wait for command completes */ | |
c92ca04b | 5090 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
5091 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
5092 | S2IO_BIT_RESET)) { | |
9e39f7c5 JP |
5093 | DBG_PRINT(ERR_DBG, |
5094 | "%s: Adding Multicasts failed\n", | |
5095 | dev->name); | |
1da177e4 LT |
5096 | return; |
5097 | } | |
5508590c | 5098 | i++; |
1da177e4 LT |
5099 | } |
5100 | } | |
5101 | } | |
5102 | ||
faa4f796 SH |
5103 | /* read from CAM unicast & multicast addresses and store it in |
5104 | * def_mac_addr structure | |
5105 | */ | |
dac499f9 | 5106 | static void do_s2io_store_unicast_mc(struct s2io_nic *sp) |
faa4f796 SH |
5107 | { |
5108 | int offset; | |
5109 | u64 mac_addr = 0x0; | |
5110 | struct config_param *config = &sp->config; | |
5111 | ||
5112 | /* store unicast & multicast mac addresses */ | |
5113 | for (offset = 0; offset < config->max_mc_addr; offset++) { | |
5114 | mac_addr = do_s2io_read_unicast_mc(sp, offset); | |
5115 | /* if read fails disable the entry */ | |
5116 | if (mac_addr == FAILURE) | |
5117 | mac_addr = S2IO_DISABLE_MAC_ENTRY; | |
5118 | do_s2io_copy_mac_addr(sp, offset, mac_addr); | |
5119 | } | |
5120 | } | |
5121 | ||
5122 | /* restore unicast & multicast MAC to CAM from def_mac_addr structure */ | |
5123 | static void do_s2io_restore_unicast_mc(struct s2io_nic *sp) | |
5124 | { | |
5125 | int offset; | |
5126 | struct config_param *config = &sp->config; | |
5127 | /* restore unicast mac address */ | |
5128 | for (offset = 0; offset < config->max_mac_addr; offset++) | |
5129 | do_s2io_prog_unicast(sp->dev, | |
d44570e4 | 5130 | sp->def_mac_addr[offset].mac_addr); |
faa4f796 SH |
5131 | |
5132 | /* restore multicast mac address */ | |
5133 | for (offset = config->mc_start_offset; | |
d44570e4 | 5134 | offset < config->max_mc_addr; offset++) |
faa4f796 SH |
5135 | do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr); |
5136 | } | |
5137 | ||
5138 | /* add a multicast MAC address to CAM */ | |
5139 | static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr) | |
5140 | { | |
5141 | int i; | |
5142 | u64 mac_addr = 0; | |
5143 | struct config_param *config = &sp->config; | |
5144 | ||
5145 | for (i = 0; i < ETH_ALEN; i++) { | |
5146 | mac_addr <<= 8; | |
5147 | mac_addr |= addr[i]; | |
5148 | } | |
5149 | if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY)) | |
5150 | return SUCCESS; | |
5151 | ||
5152 | /* check if the multicast mac already preset in CAM */ | |
5153 | for (i = config->mc_start_offset; i < config->max_mc_addr; i++) { | |
5154 | u64 tmp64; | |
5155 | tmp64 = do_s2io_read_unicast_mc(sp, i); | |
5156 | if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */ | |
5157 | break; | |
5158 | ||
5159 | if (tmp64 == mac_addr) | |
5160 | return SUCCESS; | |
5161 | } | |
5162 | if (i == config->max_mc_addr) { | |
5163 | DBG_PRINT(ERR_DBG, | |
d44570e4 | 5164 | "CAM full no space left for multicast MAC\n"); |
faa4f796 SH |
5165 | return FAILURE; |
5166 | } | |
5167 | /* Update the internal structure with this new mac address */ | |
5168 | do_s2io_copy_mac_addr(sp, i, mac_addr); | |
5169 | ||
d44570e4 | 5170 | return do_s2io_add_mac(sp, mac_addr, i); |
faa4f796 SH |
5171 | } |
5172 | ||
5173 | /* add MAC address to CAM */ | |
5174 | static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off) | |
2fd37688 SS |
5175 | { |
5176 | u64 val64; | |
5177 | struct XENA_dev_config __iomem *bar0 = sp->bar0; | |
5178 | ||
5179 | writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr), | |
d44570e4 | 5180 | &bar0->rmac_addr_data0_mem); |
2fd37688 | 5181 | |
d44570e4 | 5182 | val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
2fd37688 SS |
5183 | RMAC_ADDR_CMD_MEM_OFFSET(off); |
5184 | writeq(val64, &bar0->rmac_addr_cmd_mem); | |
5185 | ||
5186 | /* Wait till command completes */ | |
5187 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | |
d44570e4 JP |
5188 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
5189 | S2IO_BIT_RESET)) { | |
faa4f796 | 5190 | DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n"); |
2fd37688 SS |
5191 | return FAILURE; |
5192 | } | |
5193 | return SUCCESS; | |
5194 | } | |
faa4f796 SH |
5195 | /* deletes a specified unicast/multicast mac entry from CAM */ |
5196 | static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr) | |
5197 | { | |
5198 | int offset; | |
5199 | u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64; | |
5200 | struct config_param *config = &sp->config; | |
5201 | ||
5202 | for (offset = 1; | |
d44570e4 | 5203 | offset < config->max_mc_addr; offset++) { |
faa4f796 SH |
5204 | tmp64 = do_s2io_read_unicast_mc(sp, offset); |
5205 | if (tmp64 == addr) { | |
5206 | /* disable the entry by writing 0xffffffffffffULL */ | |
5207 | if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE) | |
5208 | return FAILURE; | |
5209 | /* store the new mac list from CAM */ | |
5210 | do_s2io_store_unicast_mc(sp); | |
5211 | return SUCCESS; | |
5212 | } | |
5213 | } | |
5214 | DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n", | |
d44570e4 | 5215 | (unsigned long long)addr); |
faa4f796 SH |
5216 | return FAILURE; |
5217 | } | |
5218 | ||
5219 | /* read mac entries from CAM */ | |
5220 | static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset) | |
5221 | { | |
5222 | u64 tmp64 = 0xffffffffffff0000ULL, val64; | |
5223 | struct XENA_dev_config __iomem *bar0 = sp->bar0; | |
5224 | ||
5225 | /* read mac addr */ | |
d44570e4 | 5226 | val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | |
faa4f796 SH |
5227 | RMAC_ADDR_CMD_MEM_OFFSET(offset); |
5228 | writeq(val64, &bar0->rmac_addr_cmd_mem); | |
5229 | ||
5230 | /* Wait till command completes */ | |
5231 | if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, | |
d44570e4 JP |
5232 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
5233 | S2IO_BIT_RESET)) { | |
faa4f796 SH |
5234 | DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n"); |
5235 | return FAILURE; | |
5236 | } | |
5237 | tmp64 = readq(&bar0->rmac_addr_data0_mem); | |
d44570e4 JP |
5238 | |
5239 | return tmp64 >> 16; | |
faa4f796 | 5240 | } |
2fd37688 SS |
5241 | |
5242 | /** | |
5243 | * s2io_set_mac_addr driver entry point | |
5244 | */ | |
faa4f796 | 5245 | |
2fd37688 SS |
5246 | static int s2io_set_mac_addr(struct net_device *dev, void *p) |
5247 | { | |
5248 | struct sockaddr *addr = p; | |
5249 | ||
5250 | if (!is_valid_ether_addr(addr->sa_data)) | |
5251 | return -EINVAL; | |
5252 | ||
5253 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
5254 | ||
5255 | /* store the MAC address in CAM */ | |
d44570e4 | 5256 | return do_s2io_prog_unicast(dev, dev->dev_addr); |
2fd37688 | 5257 | } |
1da177e4 | 5258 | /** |
2fd37688 | 5259 | * do_s2io_prog_unicast - Programs the Xframe mac address |
1da177e4 LT |
5260 | * @dev : pointer to the device structure. |
5261 | * @addr: a uchar pointer to the new mac address which is to be set. | |
20346722 | 5262 | * Description : This procedure will program the Xframe to receive |
1da177e4 | 5263 | * frames with new Mac Address |
20346722 | 5264 | * Return value: SUCCESS on success and an appropriate (-)ve integer |
1da177e4 LT |
5265 | * as defined in errno.h file on failure. |
5266 | */ | |
faa4f796 | 5267 | |
2fd37688 | 5268 | static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr) |
1da177e4 | 5269 | { |
4cf1653a | 5270 | struct s2io_nic *sp = netdev_priv(dev); |
2fd37688 | 5271 | register u64 mac_addr = 0, perm_addr = 0; |
1da177e4 | 5272 | int i; |
faa4f796 SH |
5273 | u64 tmp64; |
5274 | struct config_param *config = &sp->config; | |
1da177e4 | 5275 | |
20346722 | 5276 | /* |
d44570e4 JP |
5277 | * Set the new MAC address as the new unicast filter and reflect this |
5278 | * change on the device address registered with the OS. It will be | |
5279 | * at offset 0. | |
5280 | */ | |
1da177e4 LT |
5281 | for (i = 0; i < ETH_ALEN; i++) { |
5282 | mac_addr <<= 8; | |
5283 | mac_addr |= addr[i]; | |
2fd37688 SS |
5284 | perm_addr <<= 8; |
5285 | perm_addr |= sp->def_mac_addr[0].mac_addr[i]; | |
d8d70caf SS |
5286 | } |
5287 | ||
2fd37688 SS |
5288 | /* check if the dev_addr is different than perm_addr */ |
5289 | if (mac_addr == perm_addr) | |
d8d70caf SS |
5290 | return SUCCESS; |
5291 | ||
faa4f796 SH |
5292 | /* check if the mac already preset in CAM */ |
5293 | for (i = 1; i < config->max_mac_addr; i++) { | |
5294 | tmp64 = do_s2io_read_unicast_mc(sp, i); | |
5295 | if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */ | |
5296 | break; | |
5297 | ||
5298 | if (tmp64 == mac_addr) { | |
5299 | DBG_PRINT(INFO_DBG, | |
d44570e4 JP |
5300 | "MAC addr:0x%llx already present in CAM\n", |
5301 | (unsigned long long)mac_addr); | |
faa4f796 SH |
5302 | return SUCCESS; |
5303 | } | |
5304 | } | |
5305 | if (i == config->max_mac_addr) { | |
5306 | DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n"); | |
5307 | return FAILURE; | |
5308 | } | |
d8d70caf | 5309 | /* Update the internal structure with this new mac address */ |
faa4f796 | 5310 | do_s2io_copy_mac_addr(sp, i, mac_addr); |
d44570e4 JP |
5311 | |
5312 | return do_s2io_add_mac(sp, mac_addr, i); | |
1da177e4 LT |
5313 | } |
5314 | ||
5315 | /** | |
20346722 | 5316 | * s2io_ethtool_sset - Sets different link parameters. |
1da177e4 LT |
5317 | * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. |
5318 | * @info: pointer to the structure with parameters given by ethtool to set | |
5319 | * link information. | |
5320 | * Description: | |
20346722 | 5321 | * The function sets different link parameters provided by the user onto |
1da177e4 LT |
5322 | * the NIC. |
5323 | * Return value: | |
5324 | * 0 on success. | |
d44570e4 | 5325 | */ |
1da177e4 LT |
5326 | |
5327 | static int s2io_ethtool_sset(struct net_device *dev, | |
5328 | struct ethtool_cmd *info) | |
5329 | { | |
4cf1653a | 5330 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 | 5331 | if ((info->autoneg == AUTONEG_ENABLE) || |
25db0338 | 5332 | (ethtool_cmd_speed(info) != SPEED_10000) || |
d44570e4 | 5333 | (info->duplex != DUPLEX_FULL)) |
1da177e4 LT |
5334 | return -EINVAL; |
5335 | else { | |
5336 | s2io_close(sp->dev); | |
5337 | s2io_open(sp->dev); | |
5338 | } | |
5339 | ||
5340 | return 0; | |
5341 | } | |
5342 | ||
5343 | /** | |
20346722 | 5344 | * s2io_ethtol_gset - Return link specific information. |
1da177e4 LT |
5345 | * @sp : private member of the device structure, pointer to the |
5346 | * s2io_nic structure. | |
5347 | * @info : pointer to the structure with parameters given by ethtool | |
5348 | * to return link information. | |
5349 | * Description: | |
5350 | * Returns link specific information like speed, duplex etc.. to ethtool. | |
5351 | * Return value : | |
5352 | * return 0 on success. | |
5353 | */ | |
5354 | ||
5355 | static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info) | |
5356 | { | |
4cf1653a | 5357 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
5358 | info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); |
5359 | info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE); | |
5360 | info->port = PORT_FIBRE; | |
1a7eb72b SS |
5361 | |
5362 | /* info->transceiver */ | |
5363 | info->transceiver = XCVR_EXTERNAL; | |
1da177e4 LT |
5364 | |
5365 | if (netif_carrier_ok(sp->dev)) { | |
70739497 | 5366 | ethtool_cmd_speed_set(info, SPEED_10000); |
1da177e4 LT |
5367 | info->duplex = DUPLEX_FULL; |
5368 | } else { | |
70739497 | 5369 | ethtool_cmd_speed_set(info, -1); |
1da177e4 LT |
5370 | info->duplex = -1; |
5371 | } | |
5372 | ||
5373 | info->autoneg = AUTONEG_DISABLE; | |
5374 | return 0; | |
5375 | } | |
5376 | ||
5377 | /** | |
20346722 | 5378 | * s2io_ethtool_gdrvinfo - Returns driver specific information. |
5379 | * @sp : private member of the device structure, which is a pointer to the | |
1da177e4 LT |
5380 | * s2io_nic structure. |
5381 | * @info : pointer to the structure with parameters given by ethtool to | |
5382 | * return driver information. | |
5383 | * Description: | |
5384 | * Returns driver specefic information like name, version etc.. to ethtool. | |
5385 | * Return value: | |
5386 | * void | |
5387 | */ | |
5388 | ||
5389 | static void s2io_ethtool_gdrvinfo(struct net_device *dev, | |
5390 | struct ethtool_drvinfo *info) | |
5391 | { | |
4cf1653a | 5392 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 | 5393 | |
dbc2309d JL |
5394 | strncpy(info->driver, s2io_driver_name, sizeof(info->driver)); |
5395 | strncpy(info->version, s2io_driver_version, sizeof(info->version)); | |
5396 | strncpy(info->fw_version, "", sizeof(info->fw_version)); | |
5397 | strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info)); | |
1da177e4 LT |
5398 | info->regdump_len = XENA_REG_SPACE; |
5399 | info->eedump_len = XENA_EEPROM_SPACE; | |
1da177e4 LT |
5400 | } |
5401 | ||
5402 | /** | |
5403 | * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer. | |
20346722 | 5404 | * @sp: private member of the device structure, which is a pointer to the |
1da177e4 | 5405 | * s2io_nic structure. |
20346722 | 5406 | * @regs : pointer to the structure with parameters given by ethtool for |
1da177e4 LT |
5407 | * dumping the registers. |
5408 | * @reg_space: The input argumnet into which all the registers are dumped. | |
5409 | * Description: | |
5410 | * Dumps the entire register space of xFrame NIC into the user given | |
5411 | * buffer area. | |
5412 | * Return value : | |
5413 | * void . | |
d44570e4 | 5414 | */ |
1da177e4 LT |
5415 | |
5416 | static void s2io_ethtool_gregs(struct net_device *dev, | |
5417 | struct ethtool_regs *regs, void *space) | |
5418 | { | |
5419 | int i; | |
5420 | u64 reg; | |
d44570e4 | 5421 | u8 *reg_space = (u8 *)space; |
4cf1653a | 5422 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
5423 | |
5424 | regs->len = XENA_REG_SPACE; | |
5425 | regs->version = sp->pdev->subsystem_device; | |
5426 | ||
5427 | for (i = 0; i < regs->len; i += 8) { | |
5428 | reg = readq(sp->bar0 + i); | |
5429 | memcpy((reg_space + i), ®, 8); | |
5430 | } | |
5431 | } | |
5432 | ||
034e3450 | 5433 | /* |
5434 | * s2io_set_led - control NIC led | |
d44570e4 | 5435 | */ |
034e3450 | 5436 | static void s2io_set_led(struct s2io_nic *sp, bool on) |
1da177e4 | 5437 | { |
1ee6dd77 | 5438 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
034e3450 | 5439 | u16 subid = sp->pdev->subsystem_device; |
5440 | u64 val64; | |
1da177e4 | 5441 | |
541ae68f | 5442 | if ((sp->device_type == XFRAME_II_DEVICE) || |
d44570e4 | 5443 | ((subid & 0xFF) >= 0x07)) { |
1da177e4 | 5444 | val64 = readq(&bar0->gpio_control); |
034e3450 | 5445 | if (on) |
5446 | val64 |= GPIO_CTRL_GPIO_0; | |
5447 | else | |
5448 | val64 &= ~GPIO_CTRL_GPIO_0; | |
5449 | ||
1da177e4 LT |
5450 | writeq(val64, &bar0->gpio_control); |
5451 | } else { | |
5452 | val64 = readq(&bar0->adapter_control); | |
034e3450 | 5453 | if (on) |
5454 | val64 |= ADAPTER_LED_ON; | |
5455 | else | |
5456 | val64 &= ~ADAPTER_LED_ON; | |
5457 | ||
1da177e4 LT |
5458 | writeq(val64, &bar0->adapter_control); |
5459 | } | |
5460 | ||
1da177e4 LT |
5461 | } |
5462 | ||
5463 | /** | |
034e3450 | 5464 | * s2io_ethtool_set_led - To physically identify the nic on the system. |
5465 | * @dev : network device | |
5466 | * @state: led setting | |
5467 | * | |
1da177e4 | 5468 | * Description: Used to physically identify the NIC on the system. |
20346722 | 5469 | * The Link LED will blink for a time specified by the user for |
1da177e4 | 5470 | * identification. |
20346722 | 5471 | * NOTE: The Link has to be Up to be able to blink the LED. Hence |
1da177e4 | 5472 | * identification is possible only if it's link is up. |
1da177e4 LT |
5473 | */ |
5474 | ||
034e3450 | 5475 | static int s2io_ethtool_set_led(struct net_device *dev, |
5476 | enum ethtool_phys_id_state state) | |
1da177e4 | 5477 | { |
4cf1653a | 5478 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 5479 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
034e3450 | 5480 | u16 subid = sp->pdev->subsystem_device; |
1da177e4 | 5481 | |
d44570e4 | 5482 | if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) { |
034e3450 | 5483 | u64 val64 = readq(&bar0->adapter_control); |
1da177e4 | 5484 | if (!(val64 & ADAPTER_CNTL_EN)) { |
6cef2b8e | 5485 | pr_err("Adapter Link down, cannot blink LED\n"); |
034e3450 | 5486 | return -EAGAIN; |
1da177e4 LT |
5487 | } |
5488 | } | |
1da177e4 | 5489 | |
034e3450 | 5490 | switch (state) { |
5491 | case ETHTOOL_ID_ACTIVE: | |
5492 | sp->adapt_ctrl_org = readq(&bar0->gpio_control); | |
fce55922 | 5493 | return 1; /* cycle on/off once per second */ |
034e3450 | 5494 | |
5495 | case ETHTOOL_ID_ON: | |
5496 | s2io_set_led(sp, true); | |
5497 | break; | |
5498 | ||
5499 | case ETHTOOL_ID_OFF: | |
5500 | s2io_set_led(sp, false); | |
5501 | break; | |
5502 | ||
5503 | case ETHTOOL_ID_INACTIVE: | |
5504 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) | |
5505 | writeq(sp->adapt_ctrl_org, &bar0->gpio_control); | |
1da177e4 LT |
5506 | } |
5507 | ||
5508 | return 0; | |
5509 | } | |
5510 | ||
0cec35eb | 5511 | static void s2io_ethtool_gringparam(struct net_device *dev, |
d44570e4 | 5512 | struct ethtool_ringparam *ering) |
0cec35eb | 5513 | { |
4cf1653a | 5514 | struct s2io_nic *sp = netdev_priv(dev); |
d44570e4 | 5515 | int i, tx_desc_count = 0, rx_desc_count = 0; |
0cec35eb | 5516 | |
1853e2e1 | 5517 | if (sp->rxd_mode == RXD_MODE_1) { |
0cec35eb | 5518 | ering->rx_max_pending = MAX_RX_DESC_1; |
1853e2e1 JM |
5519 | ering->rx_jumbo_max_pending = MAX_RX_DESC_1; |
5520 | } else { | |
0cec35eb | 5521 | ering->rx_max_pending = MAX_RX_DESC_2; |
1853e2e1 JM |
5522 | ering->rx_jumbo_max_pending = MAX_RX_DESC_2; |
5523 | } | |
0cec35eb SH |
5524 | |
5525 | ering->tx_max_pending = MAX_TX_DESC; | |
8a4bdbaa | 5526 | |
1853e2e1 | 5527 | for (i = 0; i < sp->config.rx_ring_num; i++) |
0cec35eb | 5528 | rx_desc_count += sp->config.rx_cfg[i].num_rxd; |
0cec35eb | 5529 | ering->rx_pending = rx_desc_count; |
0cec35eb | 5530 | ering->rx_jumbo_pending = rx_desc_count; |
1853e2e1 JM |
5531 | |
5532 | for (i = 0; i < sp->config.tx_fifo_num; i++) | |
5533 | tx_desc_count += sp->config.tx_cfg[i].fifo_len; | |
5534 | ering->tx_pending = tx_desc_count; | |
5535 | DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds); | |
0cec35eb SH |
5536 | } |
5537 | ||
1da177e4 LT |
5538 | /** |
5539 | * s2io_ethtool_getpause_data -Pause frame frame generation and reception. | |
20346722 | 5540 | * @sp : private member of the device structure, which is a pointer to the |
5541 | * s2io_nic structure. | |
1da177e4 LT |
5542 | * @ep : pointer to the structure with pause parameters given by ethtool. |
5543 | * Description: | |
5544 | * Returns the Pause frame generation and reception capability of the NIC. | |
5545 | * Return value: | |
5546 | * void | |
5547 | */ | |
5548 | static void s2io_ethtool_getpause_data(struct net_device *dev, | |
5549 | struct ethtool_pauseparam *ep) | |
5550 | { | |
5551 | u64 val64; | |
4cf1653a | 5552 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 5553 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
5554 | |
5555 | val64 = readq(&bar0->rmac_pause_cfg); | |
5556 | if (val64 & RMAC_PAUSE_GEN_ENABLE) | |
f957bcf0 | 5557 | ep->tx_pause = true; |
1da177e4 | 5558 | if (val64 & RMAC_PAUSE_RX_ENABLE) |
f957bcf0 TK |
5559 | ep->rx_pause = true; |
5560 | ep->autoneg = false; | |
1da177e4 LT |
5561 | } |
5562 | ||
5563 | /** | |
5564 | * s2io_ethtool_setpause_data - set/reset pause frame generation. | |
20346722 | 5565 | * @sp : private member of the device structure, which is a pointer to the |
1da177e4 LT |
5566 | * s2io_nic structure. |
5567 | * @ep : pointer to the structure with pause parameters given by ethtool. | |
5568 | * Description: | |
5569 | * It can be used to set or reset Pause frame generation or reception | |
5570 | * support of the NIC. | |
5571 | * Return value: | |
5572 | * int, returns 0 on Success | |
5573 | */ | |
5574 | ||
5575 | static int s2io_ethtool_setpause_data(struct net_device *dev, | |
d44570e4 | 5576 | struct ethtool_pauseparam *ep) |
1da177e4 LT |
5577 | { |
5578 | u64 val64; | |
4cf1653a | 5579 | struct s2io_nic *sp = netdev_priv(dev); |
1ee6dd77 | 5580 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
5581 | |
5582 | val64 = readq(&bar0->rmac_pause_cfg); | |
5583 | if (ep->tx_pause) | |
5584 | val64 |= RMAC_PAUSE_GEN_ENABLE; | |
5585 | else | |
5586 | val64 &= ~RMAC_PAUSE_GEN_ENABLE; | |
5587 | if (ep->rx_pause) | |
5588 | val64 |= RMAC_PAUSE_RX_ENABLE; | |
5589 | else | |
5590 | val64 &= ~RMAC_PAUSE_RX_ENABLE; | |
5591 | writeq(val64, &bar0->rmac_pause_cfg); | |
5592 | return 0; | |
5593 | } | |
5594 | ||
5595 | /** | |
5596 | * read_eeprom - reads 4 bytes of data from user given offset. | |
20346722 | 5597 | * @sp : private member of the device structure, which is a pointer to the |
1da177e4 LT |
5598 | * s2io_nic structure. |
5599 | * @off : offset at which the data must be written | |
5600 | * @data : Its an output parameter where the data read at the given | |
20346722 | 5601 | * offset is stored. |
1da177e4 | 5602 | * Description: |
20346722 | 5603 | * Will read 4 bytes of data from the user given offset and return the |
1da177e4 LT |
5604 | * read data. |
5605 | * NOTE: Will allow to read only part of the EEPROM visible through the | |
5606 | * I2C bus. | |
5607 | * Return value: | |
5608 | * -1 on failure and 0 on success. | |
5609 | */ | |
5610 | ||
5611 | #define S2IO_DEV_ID 5 | |
d44570e4 | 5612 | static int read_eeprom(struct s2io_nic *sp, int off, u64 *data) |
1da177e4 LT |
5613 | { |
5614 | int ret = -1; | |
5615 | u32 exit_cnt = 0; | |
5616 | u64 val64; | |
1ee6dd77 | 5617 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 5618 | |
ad4ebed0 | 5619 | if (sp->device_type == XFRAME_I_DEVICE) { |
d44570e4 JP |
5620 | val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | |
5621 | I2C_CONTROL_ADDR(off) | | |
5622 | I2C_CONTROL_BYTE_CNT(0x3) | | |
5623 | I2C_CONTROL_READ | | |
5624 | I2C_CONTROL_CNTL_START; | |
ad4ebed0 | 5625 | SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); |
1da177e4 | 5626 | |
ad4ebed0 | 5627 | while (exit_cnt < 5) { |
5628 | val64 = readq(&bar0->i2c_control); | |
5629 | if (I2C_CONTROL_CNTL_END(val64)) { | |
5630 | *data = I2C_CONTROL_GET_DATA(val64); | |
5631 | ret = 0; | |
5632 | break; | |
5633 | } | |
5634 | msleep(50); | |
5635 | exit_cnt++; | |
1da177e4 | 5636 | } |
1da177e4 LT |
5637 | } |
5638 | ||
ad4ebed0 | 5639 | if (sp->device_type == XFRAME_II_DEVICE) { |
5640 | val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | | |
6aa20a22 | 5641 | SPI_CONTROL_BYTECNT(0x3) | |
ad4ebed0 | 5642 | SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off); |
5643 | SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); | |
5644 | val64 |= SPI_CONTROL_REQ; | |
5645 | SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); | |
5646 | while (exit_cnt < 5) { | |
5647 | val64 = readq(&bar0->spi_control); | |
5648 | if (val64 & SPI_CONTROL_NACK) { | |
5649 | ret = 1; | |
5650 | break; | |
5651 | } else if (val64 & SPI_CONTROL_DONE) { | |
5652 | *data = readq(&bar0->spi_data); | |
5653 | *data &= 0xffffff; | |
5654 | ret = 0; | |
5655 | break; | |
5656 | } | |
5657 | msleep(50); | |
5658 | exit_cnt++; | |
5659 | } | |
5660 | } | |
1da177e4 LT |
5661 | return ret; |
5662 | } | |
5663 | ||
5664 | /** | |
5665 | * write_eeprom - actually writes the relevant part of the data value. | |
5666 | * @sp : private member of the device structure, which is a pointer to the | |
5667 | * s2io_nic structure. | |
5668 | * @off : offset at which the data must be written | |
5669 | * @data : The data that is to be written | |
20346722 | 5670 | * @cnt : Number of bytes of the data that are actually to be written into |
1da177e4 LT |
5671 | * the Eeprom. (max of 3) |
5672 | * Description: | |
5673 | * Actually writes the relevant part of the data value into the Eeprom | |
5674 | * through the I2C bus. | |
5675 | * Return value: | |
5676 | * 0 on success, -1 on failure. | |
5677 | */ | |
5678 | ||
d44570e4 | 5679 | static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt) |
1da177e4 LT |
5680 | { |
5681 | int exit_cnt = 0, ret = -1; | |
5682 | u64 val64; | |
1ee6dd77 | 5683 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 5684 | |
ad4ebed0 | 5685 | if (sp->device_type == XFRAME_I_DEVICE) { |
d44570e4 JP |
5686 | val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | |
5687 | I2C_CONTROL_ADDR(off) | | |
5688 | I2C_CONTROL_BYTE_CNT(cnt) | | |
5689 | I2C_CONTROL_SET_DATA((u32)data) | | |
5690 | I2C_CONTROL_CNTL_START; | |
ad4ebed0 | 5691 | SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); |
5692 | ||
5693 | while (exit_cnt < 5) { | |
5694 | val64 = readq(&bar0->i2c_control); | |
5695 | if (I2C_CONTROL_CNTL_END(val64)) { | |
5696 | if (!(val64 & I2C_CONTROL_NACK)) | |
5697 | ret = 0; | |
5698 | break; | |
5699 | } | |
5700 | msleep(50); | |
5701 | exit_cnt++; | |
5702 | } | |
5703 | } | |
1da177e4 | 5704 | |
ad4ebed0 | 5705 | if (sp->device_type == XFRAME_II_DEVICE) { |
5706 | int write_cnt = (cnt == 8) ? 0 : cnt; | |
d44570e4 | 5707 | writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data); |
ad4ebed0 | 5708 | |
5709 | val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 | | |
6aa20a22 | 5710 | SPI_CONTROL_BYTECNT(write_cnt) | |
ad4ebed0 | 5711 | SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off); |
5712 | SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); | |
5713 | val64 |= SPI_CONTROL_REQ; | |
5714 | SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); | |
5715 | while (exit_cnt < 5) { | |
5716 | val64 = readq(&bar0->spi_control); | |
5717 | if (val64 & SPI_CONTROL_NACK) { | |
5718 | ret = 1; | |
5719 | break; | |
5720 | } else if (val64 & SPI_CONTROL_DONE) { | |
1da177e4 | 5721 | ret = 0; |
ad4ebed0 | 5722 | break; |
5723 | } | |
5724 | msleep(50); | |
5725 | exit_cnt++; | |
1da177e4 | 5726 | } |
1da177e4 | 5727 | } |
1da177e4 LT |
5728 | return ret; |
5729 | } | |
1ee6dd77 | 5730 | static void s2io_vpd_read(struct s2io_nic *nic) |
9dc737a7 | 5731 | { |
b41477f3 AR |
5732 | u8 *vpd_data; |
5733 | u8 data; | |
9c179780 | 5734 | int i = 0, cnt, len, fail = 0; |
9dc737a7 | 5735 | int vpd_addr = 0x80; |
ffb5df6c | 5736 | struct swStat *swstats = &nic->mac_control.stats_info->sw_stat; |
9dc737a7 AR |
5737 | |
5738 | if (nic->device_type == XFRAME_II_DEVICE) { | |
5739 | strcpy(nic->product_name, "Xframe II 10GbE network adapter"); | |
5740 | vpd_addr = 0x80; | |
d44570e4 | 5741 | } else { |
9dc737a7 AR |
5742 | strcpy(nic->product_name, "Xframe I 10GbE network adapter"); |
5743 | vpd_addr = 0x50; | |
5744 | } | |
19a60522 | 5745 | strcpy(nic->serial_num, "NOT AVAILABLE"); |
9dc737a7 | 5746 | |
b41477f3 | 5747 | vpd_data = kmalloc(256, GFP_KERNEL); |
c53d4945 | 5748 | if (!vpd_data) { |
ffb5df6c | 5749 | swstats->mem_alloc_fail_cnt++; |
b41477f3 | 5750 | return; |
c53d4945 | 5751 | } |
ffb5df6c | 5752 | swstats->mem_allocated += 256; |
b41477f3 | 5753 | |
d44570e4 | 5754 | for (i = 0; i < 256; i += 4) { |
9dc737a7 AR |
5755 | pci_write_config_byte(nic->pdev, (vpd_addr + 2), i); |
5756 | pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data); | |
5757 | pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0); | |
d44570e4 | 5758 | for (cnt = 0; cnt < 5; cnt++) { |
9dc737a7 AR |
5759 | msleep(2); |
5760 | pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data); | |
5761 | if (data == 0x80) | |
5762 | break; | |
5763 | } | |
5764 | if (cnt >= 5) { | |
5765 | DBG_PRINT(ERR_DBG, "Read of VPD data failed\n"); | |
5766 | fail = 1; | |
5767 | break; | |
5768 | } | |
5769 | pci_read_config_dword(nic->pdev, (vpd_addr + 4), | |
5770 | (u32 *)&vpd_data[i]); | |
5771 | } | |
19a60522 | 5772 | |
d44570e4 | 5773 | if (!fail) { |
19a60522 | 5774 | /* read serial number of adapter */ |
9c179780 | 5775 | for (cnt = 0; cnt < 252; cnt++) { |
d44570e4 | 5776 | if ((vpd_data[cnt] == 'S') && |
9c179780 KV |
5777 | (vpd_data[cnt+1] == 'N')) { |
5778 | len = vpd_data[cnt+2]; | |
5779 | if (len < min(VPD_STRING_LEN, 256-cnt-2)) { | |
5780 | memcpy(nic->serial_num, | |
5781 | &vpd_data[cnt + 3], | |
5782 | len); | |
5783 | memset(nic->serial_num+len, | |
5784 | 0, | |
5785 | VPD_STRING_LEN-len); | |
5786 | break; | |
5787 | } | |
19a60522 SS |
5788 | } |
5789 | } | |
5790 | } | |
5791 | ||
9c179780 KV |
5792 | if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) { |
5793 | len = vpd_data[1]; | |
5794 | memcpy(nic->product_name, &vpd_data[3], len); | |
5795 | nic->product_name[len] = 0; | |
5796 | } | |
b41477f3 | 5797 | kfree(vpd_data); |
ffb5df6c | 5798 | swstats->mem_freed += 256; |
9dc737a7 AR |
5799 | } |
5800 | ||
1da177e4 LT |
5801 | /** |
5802 | * s2io_ethtool_geeprom - reads the value stored in the Eeprom. | |
5803 | * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure. | |
20346722 | 5804 | * @eeprom : pointer to the user level structure provided by ethtool, |
1da177e4 LT |
5805 | * containing all relevant information. |
5806 | * @data_buf : user defined value to be written into Eeprom. | |
5807 | * Description: Reads the values stored in the Eeprom at given offset | |
5808 | * for a given length. Stores these values int the input argument data | |
5809 | * buffer 'data_buf' and returns these to the caller (ethtool.) | |
5810 | * Return value: | |
5811 | * int 0 on success | |
5812 | */ | |
5813 | ||
5814 | static int s2io_ethtool_geeprom(struct net_device *dev, | |
d44570e4 | 5815 | struct ethtool_eeprom *eeprom, u8 * data_buf) |
1da177e4 | 5816 | { |
ad4ebed0 | 5817 | u32 i, valid; |
5818 | u64 data; | |
4cf1653a | 5819 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
5820 | |
5821 | eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16); | |
5822 | ||
5823 | if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE)) | |
5824 | eeprom->len = XENA_EEPROM_SPACE - eeprom->offset; | |
5825 | ||
5826 | for (i = 0; i < eeprom->len; i += 4) { | |
5827 | if (read_eeprom(sp, (eeprom->offset + i), &data)) { | |
5828 | DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n"); | |
5829 | return -EFAULT; | |
5830 | } | |
5831 | valid = INV(data); | |
5832 | memcpy((data_buf + i), &valid, 4); | |
5833 | } | |
5834 | return 0; | |
5835 | } | |
5836 | ||
5837 | /** | |
5838 | * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom | |
5839 | * @sp : private member of the device structure, which is a pointer to the | |
5840 | * s2io_nic structure. | |
20346722 | 5841 | * @eeprom : pointer to the user level structure provided by ethtool, |
1da177e4 LT |
5842 | * containing all relevant information. |
5843 | * @data_buf ; user defined value to be written into Eeprom. | |
5844 | * Description: | |
5845 | * Tries to write the user provided value in the Eeprom, at the offset | |
5846 | * given by the user. | |
5847 | * Return value: | |
5848 | * 0 on success, -EFAULT on failure. | |
5849 | */ | |
5850 | ||
5851 | static int s2io_ethtool_seeprom(struct net_device *dev, | |
5852 | struct ethtool_eeprom *eeprom, | |
d44570e4 | 5853 | u8 *data_buf) |
1da177e4 LT |
5854 | { |
5855 | int len = eeprom->len, cnt = 0; | |
ad4ebed0 | 5856 | u64 valid = 0, data; |
4cf1653a | 5857 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
5858 | |
5859 | if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) { | |
5860 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 JP |
5861 | "ETHTOOL_WRITE_EEPROM Err: " |
5862 | "Magic value is wrong, it is 0x%x should be 0x%x\n", | |
5863 | (sp->pdev->vendor | (sp->pdev->device << 16)), | |
5864 | eeprom->magic); | |
1da177e4 LT |
5865 | return -EFAULT; |
5866 | } | |
5867 | ||
5868 | while (len) { | |
d44570e4 JP |
5869 | data = (u32)data_buf[cnt] & 0x000000FF; |
5870 | if (data) | |
5871 | valid = (u32)(data << 24); | |
5872 | else | |
1da177e4 LT |
5873 | valid = data; |
5874 | ||
5875 | if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) { | |
5876 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 JP |
5877 | "ETHTOOL_WRITE_EEPROM Err: " |
5878 | "Cannot write into the specified offset\n"); | |
1da177e4 LT |
5879 | return -EFAULT; |
5880 | } | |
5881 | cnt++; | |
5882 | len--; | |
5883 | } | |
5884 | ||
5885 | return 0; | |
5886 | } | |
5887 | ||
5888 | /** | |
20346722 | 5889 | * s2io_register_test - reads and writes into all clock domains. |
5890 | * @sp : private member of the device structure, which is a pointer to the | |
1da177e4 LT |
5891 | * s2io_nic structure. |
5892 | * @data : variable that returns the result of each of the test conducted b | |
5893 | * by the driver. | |
5894 | * Description: | |
5895 | * Read and write into all clock domains. The NIC has 3 clock domains, | |
5896 | * see that registers in all the three regions are accessible. | |
5897 | * Return value: | |
5898 | * 0 on success. | |
5899 | */ | |
5900 | ||
d44570e4 | 5901 | static int s2io_register_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 | 5902 | { |
1ee6dd77 | 5903 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
ad4ebed0 | 5904 | u64 val64 = 0, exp_val; |
1da177e4 LT |
5905 | int fail = 0; |
5906 | ||
20346722 | 5907 | val64 = readq(&bar0->pif_rd_swapper_fb); |
5908 | if (val64 != 0x123456789abcdefULL) { | |
1da177e4 | 5909 | fail = 1; |
9e39f7c5 | 5910 | DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1); |
1da177e4 LT |
5911 | } |
5912 | ||
5913 | val64 = readq(&bar0->rmac_pause_cfg); | |
5914 | if (val64 != 0xc000ffff00000000ULL) { | |
5915 | fail = 1; | |
9e39f7c5 | 5916 | DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2); |
1da177e4 LT |
5917 | } |
5918 | ||
5919 | val64 = readq(&bar0->rx_queue_cfg); | |
ad4ebed0 | 5920 | if (sp->device_type == XFRAME_II_DEVICE) |
5921 | exp_val = 0x0404040404040404ULL; | |
5922 | else | |
5923 | exp_val = 0x0808080808080808ULL; | |
5924 | if (val64 != exp_val) { | |
1da177e4 | 5925 | fail = 1; |
9e39f7c5 | 5926 | DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3); |
1da177e4 LT |
5927 | } |
5928 | ||
5929 | val64 = readq(&bar0->xgxs_efifo_cfg); | |
5930 | if (val64 != 0x000000001923141EULL) { | |
5931 | fail = 1; | |
9e39f7c5 | 5932 | DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4); |
1da177e4 LT |
5933 | } |
5934 | ||
5935 | val64 = 0x5A5A5A5A5A5A5A5AULL; | |
5936 | writeq(val64, &bar0->xmsi_data); | |
5937 | val64 = readq(&bar0->xmsi_data); | |
5938 | if (val64 != 0x5A5A5A5A5A5A5A5AULL) { | |
5939 | fail = 1; | |
9e39f7c5 | 5940 | DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1); |
1da177e4 LT |
5941 | } |
5942 | ||
5943 | val64 = 0xA5A5A5A5A5A5A5A5ULL; | |
5944 | writeq(val64, &bar0->xmsi_data); | |
5945 | val64 = readq(&bar0->xmsi_data); | |
5946 | if (val64 != 0xA5A5A5A5A5A5A5A5ULL) { | |
5947 | fail = 1; | |
9e39f7c5 | 5948 | DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2); |
1da177e4 LT |
5949 | } |
5950 | ||
5951 | *data = fail; | |
ad4ebed0 | 5952 | return fail; |
1da177e4 LT |
5953 | } |
5954 | ||
5955 | /** | |
20346722 | 5956 | * s2io_eeprom_test - to verify that EEprom in the xena can be programmed. |
1da177e4 LT |
5957 | * @sp : private member of the device structure, which is a pointer to the |
5958 | * s2io_nic structure. | |
5959 | * @data:variable that returns the result of each of the test conducted by | |
5960 | * the driver. | |
5961 | * Description: | |
20346722 | 5962 | * Verify that EEPROM in the xena can be programmed using I2C_CONTROL |
1da177e4 LT |
5963 | * register. |
5964 | * Return value: | |
5965 | * 0 on success. | |
5966 | */ | |
5967 | ||
d44570e4 | 5968 | static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 LT |
5969 | { |
5970 | int fail = 0; | |
ad4ebed0 | 5971 | u64 ret_data, org_4F0, org_7F0; |
5972 | u8 saved_4F0 = 0, saved_7F0 = 0; | |
5973 | struct net_device *dev = sp->dev; | |
1da177e4 LT |
5974 | |
5975 | /* Test Write Error at offset 0 */ | |
ad4ebed0 | 5976 | /* Note that SPI interface allows write access to all areas |
5977 | * of EEPROM. Hence doing all negative testing only for Xframe I. | |
5978 | */ | |
5979 | if (sp->device_type == XFRAME_I_DEVICE) | |
5980 | if (!write_eeprom(sp, 0, 0, 3)) | |
5981 | fail = 1; | |
5982 | ||
5983 | /* Save current values at offsets 0x4F0 and 0x7F0 */ | |
5984 | if (!read_eeprom(sp, 0x4F0, &org_4F0)) | |
5985 | saved_4F0 = 1; | |
5986 | if (!read_eeprom(sp, 0x7F0, &org_7F0)) | |
5987 | saved_7F0 = 1; | |
1da177e4 LT |
5988 | |
5989 | /* Test Write at offset 4f0 */ | |
ad4ebed0 | 5990 | if (write_eeprom(sp, 0x4F0, 0x012345, 3)) |
1da177e4 LT |
5991 | fail = 1; |
5992 | if (read_eeprom(sp, 0x4F0, &ret_data)) | |
5993 | fail = 1; | |
5994 | ||
ad4ebed0 | 5995 | if (ret_data != 0x012345) { |
26b7625c | 5996 | DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. " |
d44570e4 JP |
5997 | "Data written %llx Data read %llx\n", |
5998 | dev->name, (unsigned long long)0x12345, | |
5999 | (unsigned long long)ret_data); | |
1da177e4 | 6000 | fail = 1; |
ad4ebed0 | 6001 | } |
1da177e4 LT |
6002 | |
6003 | /* Reset the EEPROM data go FFFF */ | |
ad4ebed0 | 6004 | write_eeprom(sp, 0x4F0, 0xFFFFFF, 3); |
1da177e4 LT |
6005 | |
6006 | /* Test Write Request Error at offset 0x7c */ | |
ad4ebed0 | 6007 | if (sp->device_type == XFRAME_I_DEVICE) |
6008 | if (!write_eeprom(sp, 0x07C, 0, 3)) | |
6009 | fail = 1; | |
1da177e4 | 6010 | |
ad4ebed0 | 6011 | /* Test Write Request at offset 0x7f0 */ |
6012 | if (write_eeprom(sp, 0x7F0, 0x012345, 3)) | |
1da177e4 | 6013 | fail = 1; |
ad4ebed0 | 6014 | if (read_eeprom(sp, 0x7F0, &ret_data)) |
1da177e4 LT |
6015 | fail = 1; |
6016 | ||
ad4ebed0 | 6017 | if (ret_data != 0x012345) { |
26b7625c | 6018 | DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. " |
d44570e4 JP |
6019 | "Data written %llx Data read %llx\n", |
6020 | dev->name, (unsigned long long)0x12345, | |
6021 | (unsigned long long)ret_data); | |
1da177e4 | 6022 | fail = 1; |
ad4ebed0 | 6023 | } |
1da177e4 LT |
6024 | |
6025 | /* Reset the EEPROM data go FFFF */ | |
ad4ebed0 | 6026 | write_eeprom(sp, 0x7F0, 0xFFFFFF, 3); |
1da177e4 | 6027 | |
ad4ebed0 | 6028 | if (sp->device_type == XFRAME_I_DEVICE) { |
6029 | /* Test Write Error at offset 0x80 */ | |
6030 | if (!write_eeprom(sp, 0x080, 0, 3)) | |
6031 | fail = 1; | |
1da177e4 | 6032 | |
ad4ebed0 | 6033 | /* Test Write Error at offset 0xfc */ |
6034 | if (!write_eeprom(sp, 0x0FC, 0, 3)) | |
6035 | fail = 1; | |
1da177e4 | 6036 | |
ad4ebed0 | 6037 | /* Test Write Error at offset 0x100 */ |
6038 | if (!write_eeprom(sp, 0x100, 0, 3)) | |
6039 | fail = 1; | |
1da177e4 | 6040 | |
ad4ebed0 | 6041 | /* Test Write Error at offset 4ec */ |
6042 | if (!write_eeprom(sp, 0x4EC, 0, 3)) | |
6043 | fail = 1; | |
6044 | } | |
6045 | ||
6046 | /* Restore values at offsets 0x4F0 and 0x7F0 */ | |
6047 | if (saved_4F0) | |
6048 | write_eeprom(sp, 0x4F0, org_4F0, 3); | |
6049 | if (saved_7F0) | |
6050 | write_eeprom(sp, 0x7F0, org_7F0, 3); | |
1da177e4 LT |
6051 | |
6052 | *data = fail; | |
ad4ebed0 | 6053 | return fail; |
1da177e4 LT |
6054 | } |
6055 | ||
6056 | /** | |
6057 | * s2io_bist_test - invokes the MemBist test of the card . | |
20346722 | 6058 | * @sp : private member of the device structure, which is a pointer to the |
1da177e4 | 6059 | * s2io_nic structure. |
20346722 | 6060 | * @data:variable that returns the result of each of the test conducted by |
1da177e4 LT |
6061 | * the driver. |
6062 | * Description: | |
6063 | * This invokes the MemBist test of the card. We give around | |
6064 | * 2 secs time for the Test to complete. If it's still not complete | |
20346722 | 6065 | * within this peiod, we consider that the test failed. |
1da177e4 LT |
6066 | * Return value: |
6067 | * 0 on success and -1 on failure. | |
6068 | */ | |
6069 | ||
d44570e4 | 6070 | static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 LT |
6071 | { |
6072 | u8 bist = 0; | |
6073 | int cnt = 0, ret = -1; | |
6074 | ||
6075 | pci_read_config_byte(sp->pdev, PCI_BIST, &bist); | |
6076 | bist |= PCI_BIST_START; | |
6077 | pci_write_config_word(sp->pdev, PCI_BIST, bist); | |
6078 | ||
6079 | while (cnt < 20) { | |
6080 | pci_read_config_byte(sp->pdev, PCI_BIST, &bist); | |
6081 | if (!(bist & PCI_BIST_START)) { | |
6082 | *data = (bist & PCI_BIST_CODE_MASK); | |
6083 | ret = 0; | |
6084 | break; | |
6085 | } | |
6086 | msleep(100); | |
6087 | cnt++; | |
6088 | } | |
6089 | ||
6090 | return ret; | |
6091 | } | |
6092 | ||
6093 | /** | |
20346722 | 6094 | * s2io-link_test - verifies the link state of the nic |
6095 | * @sp ; private member of the device structure, which is a pointer to the | |
1da177e4 LT |
6096 | * s2io_nic structure. |
6097 | * @data: variable that returns the result of each of the test conducted by | |
6098 | * the driver. | |
6099 | * Description: | |
20346722 | 6100 | * The function verifies the link state of the NIC and updates the input |
1da177e4 LT |
6101 | * argument 'data' appropriately. |
6102 | * Return value: | |
6103 | * 0 on success. | |
6104 | */ | |
6105 | ||
d44570e4 | 6106 | static int s2io_link_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 | 6107 | { |
1ee6dd77 | 6108 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 LT |
6109 | u64 val64; |
6110 | ||
6111 | val64 = readq(&bar0->adapter_status); | |
d44570e4 | 6112 | if (!(LINK_IS_UP(val64))) |
1da177e4 | 6113 | *data = 1; |
c92ca04b AR |
6114 | else |
6115 | *data = 0; | |
1da177e4 | 6116 | |
b41477f3 | 6117 | return *data; |
1da177e4 LT |
6118 | } |
6119 | ||
6120 | /** | |
20346722 | 6121 | * s2io_rldram_test - offline test for access to the RldRam chip on the NIC |
6122 | * @sp - private member of the device structure, which is a pointer to the | |
1da177e4 | 6123 | * s2io_nic structure. |
20346722 | 6124 | * @data - variable that returns the result of each of the test |
1da177e4 LT |
6125 | * conducted by the driver. |
6126 | * Description: | |
20346722 | 6127 | * This is one of the offline test that tests the read and write |
1da177e4 LT |
6128 | * access to the RldRam chip on the NIC. |
6129 | * Return value: | |
6130 | * 0 on success. | |
6131 | */ | |
6132 | ||
d44570e4 | 6133 | static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data) |
1da177e4 | 6134 | { |
1ee6dd77 | 6135 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
1da177e4 | 6136 | u64 val64; |
ad4ebed0 | 6137 | int cnt, iteration = 0, test_fail = 0; |
1da177e4 LT |
6138 | |
6139 | val64 = readq(&bar0->adapter_control); | |
6140 | val64 &= ~ADAPTER_ECC_EN; | |
6141 | writeq(val64, &bar0->adapter_control); | |
6142 | ||
6143 | val64 = readq(&bar0->mc_rldram_test_ctrl); | |
6144 | val64 |= MC_RLDRAM_TEST_MODE; | |
ad4ebed0 | 6145 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); |
1da177e4 LT |
6146 | |
6147 | val64 = readq(&bar0->mc_rldram_mrs); | |
6148 | val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE; | |
6149 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); | |
6150 | ||
6151 | val64 |= MC_RLDRAM_MRS_ENABLE; | |
6152 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); | |
6153 | ||
6154 | while (iteration < 2) { | |
6155 | val64 = 0x55555555aaaa0000ULL; | |
d44570e4 | 6156 | if (iteration == 1) |
1da177e4 | 6157 | val64 ^= 0xFFFFFFFFFFFF0000ULL; |
1da177e4 LT |
6158 | writeq(val64, &bar0->mc_rldram_test_d0); |
6159 | ||
6160 | val64 = 0xaaaa5a5555550000ULL; | |
d44570e4 | 6161 | if (iteration == 1) |
1da177e4 | 6162 | val64 ^= 0xFFFFFFFFFFFF0000ULL; |
1da177e4 LT |
6163 | writeq(val64, &bar0->mc_rldram_test_d1); |
6164 | ||
6165 | val64 = 0x55aaaaaaaa5a0000ULL; | |
d44570e4 | 6166 | if (iteration == 1) |
1da177e4 | 6167 | val64 ^= 0xFFFFFFFFFFFF0000ULL; |
1da177e4 LT |
6168 | writeq(val64, &bar0->mc_rldram_test_d2); |
6169 | ||
ad4ebed0 | 6170 | val64 = (u64) (0x0000003ffffe0100ULL); |
1da177e4 LT |
6171 | writeq(val64, &bar0->mc_rldram_test_add); |
6172 | ||
d44570e4 JP |
6173 | val64 = MC_RLDRAM_TEST_MODE | |
6174 | MC_RLDRAM_TEST_WRITE | | |
6175 | MC_RLDRAM_TEST_GO; | |
ad4ebed0 | 6176 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); |
1da177e4 LT |
6177 | |
6178 | for (cnt = 0; cnt < 5; cnt++) { | |
6179 | val64 = readq(&bar0->mc_rldram_test_ctrl); | |
6180 | if (val64 & MC_RLDRAM_TEST_DONE) | |
6181 | break; | |
6182 | msleep(200); | |
6183 | } | |
6184 | ||
6185 | if (cnt == 5) | |
6186 | break; | |
6187 | ||
ad4ebed0 | 6188 | val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO; |
6189 | SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); | |
1da177e4 LT |
6190 | |
6191 | for (cnt = 0; cnt < 5; cnt++) { | |
6192 | val64 = readq(&bar0->mc_rldram_test_ctrl); | |
6193 | if (val64 & MC_RLDRAM_TEST_DONE) | |
6194 | break; | |
6195 | msleep(500); | |
6196 | } | |
6197 | ||
6198 | if (cnt == 5) | |
6199 | break; | |
6200 | ||
6201 | val64 = readq(&bar0->mc_rldram_test_ctrl); | |
ad4ebed0 | 6202 | if (!(val64 & MC_RLDRAM_TEST_PASS)) |
6203 | test_fail = 1; | |
1da177e4 LT |
6204 | |
6205 | iteration++; | |
6206 | } | |
6207 | ||
ad4ebed0 | 6208 | *data = test_fail; |
1da177e4 | 6209 | |
ad4ebed0 | 6210 | /* Bring the adapter out of test mode */ |
6211 | SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF); | |
6212 | ||
6213 | return test_fail; | |
1da177e4 LT |
6214 | } |
6215 | ||
6216 | /** | |
6217 | * s2io_ethtool_test - conducts 6 tsets to determine the health of card. | |
6218 | * @sp : private member of the device structure, which is a pointer to the | |
6219 | * s2io_nic structure. | |
6220 | * @ethtest : pointer to a ethtool command specific structure that will be | |
6221 | * returned to the user. | |
20346722 | 6222 | * @data : variable that returns the result of each of the test |
1da177e4 LT |
6223 | * conducted by the driver. |
6224 | * Description: | |
6225 | * This function conducts 6 tests ( 4 offline and 2 online) to determine | |
6226 | * the health of the card. | |
6227 | * Return value: | |
6228 | * void | |
6229 | */ | |
6230 | ||
6231 | static void s2io_ethtool_test(struct net_device *dev, | |
6232 | struct ethtool_test *ethtest, | |
d44570e4 | 6233 | uint64_t *data) |
1da177e4 | 6234 | { |
4cf1653a | 6235 | struct s2io_nic *sp = netdev_priv(dev); |
1da177e4 LT |
6236 | int orig_state = netif_running(sp->dev); |
6237 | ||
6238 | if (ethtest->flags == ETH_TEST_FL_OFFLINE) { | |
6239 | /* Offline Tests. */ | |
20346722 | 6240 | if (orig_state) |
1da177e4 | 6241 | s2io_close(sp->dev); |
1da177e4 LT |
6242 | |
6243 | if (s2io_register_test(sp, &data[0])) | |
6244 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6245 | ||
6246 | s2io_reset(sp); | |
1da177e4 LT |
6247 | |
6248 | if (s2io_rldram_test(sp, &data[3])) | |
6249 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6250 | ||
6251 | s2io_reset(sp); | |
1da177e4 LT |
6252 | |
6253 | if (s2io_eeprom_test(sp, &data[1])) | |
6254 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6255 | ||
6256 | if (s2io_bist_test(sp, &data[4])) | |
6257 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6258 | ||
6259 | if (orig_state) | |
6260 | s2io_open(sp->dev); | |
6261 | ||
6262 | data[2] = 0; | |
6263 | } else { | |
6264 | /* Online Tests. */ | |
6265 | if (!orig_state) { | |
d44570e4 | 6266 | DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n", |
1da177e4 LT |
6267 | dev->name); |
6268 | data[0] = -1; | |
6269 | data[1] = -1; | |
6270 | data[2] = -1; | |
6271 | data[3] = -1; | |
6272 | data[4] = -1; | |
6273 | } | |
6274 | ||
6275 | if (s2io_link_test(sp, &data[2])) | |
6276 | ethtest->flags |= ETH_TEST_FL_FAILED; | |
6277 | ||
6278 | data[0] = 0; | |
6279 | data[1] = 0; | |
6280 | data[3] = 0; | |
6281 | data[4] = 0; | |
6282 | } | |
6283 | } | |
6284 | ||
6285 | static void s2io_get_ethtool_stats(struct net_device *dev, | |
6286 | struct ethtool_stats *estats, | |
d44570e4 | 6287 | u64 *tmp_stats) |
1da177e4 | 6288 | { |
8116f3cf | 6289 | int i = 0, k; |
4cf1653a | 6290 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c JP |
6291 | struct stat_block *stats = sp->mac_control.stats_info; |
6292 | struct swStat *swstats = &stats->sw_stat; | |
6293 | struct xpakStat *xstats = &stats->xpak_stat; | |
1da177e4 | 6294 | |
7ba013ac | 6295 | s2io_updt_stats(sp); |
541ae68f | 6296 | tmp_stats[i++] = |
ffb5df6c JP |
6297 | (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 | |
6298 | le32_to_cpu(stats->tmac_frms); | |
541ae68f | 6299 | tmp_stats[i++] = |
ffb5df6c JP |
6300 | (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 | |
6301 | le32_to_cpu(stats->tmac_data_octets); | |
6302 | tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms); | |
541ae68f | 6303 | tmp_stats[i++] = |
ffb5df6c JP |
6304 | (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 | |
6305 | le32_to_cpu(stats->tmac_mcst_frms); | |
541ae68f | 6306 | tmp_stats[i++] = |
ffb5df6c JP |
6307 | (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 | |
6308 | le32_to_cpu(stats->tmac_bcst_frms); | |
6309 | tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms); | |
bd1034f0 | 6310 | tmp_stats[i++] = |
ffb5df6c JP |
6311 | (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 | |
6312 | le32_to_cpu(stats->tmac_ttl_octets); | |
bd1034f0 | 6313 | tmp_stats[i++] = |
ffb5df6c JP |
6314 | (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 | |
6315 | le32_to_cpu(stats->tmac_ucst_frms); | |
d44570e4 | 6316 | tmp_stats[i++] = |
ffb5df6c JP |
6317 | (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 | |
6318 | le32_to_cpu(stats->tmac_nucst_frms); | |
541ae68f | 6319 | tmp_stats[i++] = |
ffb5df6c JP |
6320 | (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 | |
6321 | le32_to_cpu(stats->tmac_any_err_frms); | |
6322 | tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets); | |
6323 | tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets); | |
541ae68f | 6324 | tmp_stats[i++] = |
ffb5df6c JP |
6325 | (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 | |
6326 | le32_to_cpu(stats->tmac_vld_ip); | |
541ae68f | 6327 | tmp_stats[i++] = |
ffb5df6c JP |
6328 | (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 | |
6329 | le32_to_cpu(stats->tmac_drop_ip); | |
541ae68f | 6330 | tmp_stats[i++] = |
ffb5df6c JP |
6331 | (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 | |
6332 | le32_to_cpu(stats->tmac_icmp); | |
541ae68f | 6333 | tmp_stats[i++] = |
ffb5df6c JP |
6334 | (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 | |
6335 | le32_to_cpu(stats->tmac_rst_tcp); | |
6336 | tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp); | |
6337 | tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 | | |
6338 | le32_to_cpu(stats->tmac_udp); | |
541ae68f | 6339 | tmp_stats[i++] = |
ffb5df6c JP |
6340 | (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 | |
6341 | le32_to_cpu(stats->rmac_vld_frms); | |
541ae68f | 6342 | tmp_stats[i++] = |
ffb5df6c JP |
6343 | (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 | |
6344 | le32_to_cpu(stats->rmac_data_octets); | |
6345 | tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms); | |
6346 | tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms); | |
541ae68f | 6347 | tmp_stats[i++] = |
ffb5df6c JP |
6348 | (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 | |
6349 | le32_to_cpu(stats->rmac_vld_mcst_frms); | |
541ae68f | 6350 | tmp_stats[i++] = |
ffb5df6c JP |
6351 | (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 | |
6352 | le32_to_cpu(stats->rmac_vld_bcst_frms); | |
6353 | tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms); | |
6354 | tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms); | |
6355 | tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms); | |
6356 | tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms); | |
6357 | tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms); | |
d44570e4 | 6358 | tmp_stats[i++] = |
ffb5df6c JP |
6359 | (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 | |
6360 | le32_to_cpu(stats->rmac_ttl_octets); | |
bd1034f0 | 6361 | tmp_stats[i++] = |
ffb5df6c JP |
6362 | (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32 |
6363 | | le32_to_cpu(stats->rmac_accepted_ucst_frms); | |
d44570e4 | 6364 | tmp_stats[i++] = |
ffb5df6c JP |
6365 | (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow) |
6366 | << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms); | |
541ae68f | 6367 | tmp_stats[i++] = |
ffb5df6c JP |
6368 | (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 | |
6369 | le32_to_cpu(stats->rmac_discarded_frms); | |
d44570e4 | 6370 | tmp_stats[i++] = |
ffb5df6c JP |
6371 | (u64)le32_to_cpu(stats->rmac_drop_events_oflow) |
6372 | << 32 | le32_to_cpu(stats->rmac_drop_events); | |
6373 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets); | |
6374 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms); | |
541ae68f | 6375 | tmp_stats[i++] = |
ffb5df6c JP |
6376 | (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 | |
6377 | le32_to_cpu(stats->rmac_usized_frms); | |
541ae68f | 6378 | tmp_stats[i++] = |
ffb5df6c JP |
6379 | (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 | |
6380 | le32_to_cpu(stats->rmac_osized_frms); | |
541ae68f | 6381 | tmp_stats[i++] = |
ffb5df6c JP |
6382 | (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 | |
6383 | le32_to_cpu(stats->rmac_frag_frms); | |
541ae68f | 6384 | tmp_stats[i++] = |
ffb5df6c JP |
6385 | (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 | |
6386 | le32_to_cpu(stats->rmac_jabber_frms); | |
6387 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms); | |
6388 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms); | |
6389 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms); | |
6390 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms); | |
6391 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms); | |
6392 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms); | |
bd1034f0 | 6393 | tmp_stats[i++] = |
ffb5df6c JP |
6394 | (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 | |
6395 | le32_to_cpu(stats->rmac_ip); | |
6396 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets); | |
6397 | tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip); | |
bd1034f0 | 6398 | tmp_stats[i++] = |
ffb5df6c JP |
6399 | (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 | |
6400 | le32_to_cpu(stats->rmac_drop_ip); | |
bd1034f0 | 6401 | tmp_stats[i++] = |
ffb5df6c JP |
6402 | (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 | |
6403 | le32_to_cpu(stats->rmac_icmp); | |
6404 | tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp); | |
bd1034f0 | 6405 | tmp_stats[i++] = |
ffb5df6c JP |
6406 | (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 | |
6407 | le32_to_cpu(stats->rmac_udp); | |
541ae68f | 6408 | tmp_stats[i++] = |
ffb5df6c JP |
6409 | (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 | |
6410 | le32_to_cpu(stats->rmac_err_drp_udp); | |
6411 | tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym); | |
6412 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0); | |
6413 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1); | |
6414 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2); | |
6415 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3); | |
6416 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4); | |
6417 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5); | |
6418 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6); | |
6419 | tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7); | |
6420 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0); | |
6421 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1); | |
6422 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2); | |
6423 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3); | |
6424 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4); | |
6425 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5); | |
6426 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6); | |
6427 | tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7); | |
541ae68f | 6428 | tmp_stats[i++] = |
ffb5df6c JP |
6429 | (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 | |
6430 | le32_to_cpu(stats->rmac_pause_cnt); | |
6431 | tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt); | |
6432 | tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt); | |
541ae68f | 6433 | tmp_stats[i++] = |
ffb5df6c JP |
6434 | (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 | |
6435 | le32_to_cpu(stats->rmac_accepted_ip); | |
6436 | tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp); | |
6437 | tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt); | |
6438 | tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt); | |
6439 | tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt); | |
6440 | tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt); | |
6441 | tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt); | |
6442 | tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt); | |
6443 | tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt); | |
6444 | tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt); | |
6445 | tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt); | |
6446 | tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt); | |
6447 | tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt); | |
6448 | tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt); | |
6449 | tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt); | |
6450 | tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt); | |
6451 | tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt); | |
6452 | tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt); | |
6453 | tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt); | |
6454 | tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt); | |
fa1f0cb3 SS |
6455 | |
6456 | /* Enhanced statistics exist only for Hercules */ | |
d44570e4 | 6457 | if (sp->device_type == XFRAME_II_DEVICE) { |
fa1f0cb3 | 6458 | tmp_stats[i++] = |
ffb5df6c | 6459 | le64_to_cpu(stats->rmac_ttl_1519_4095_frms); |
fa1f0cb3 | 6460 | tmp_stats[i++] = |
ffb5df6c | 6461 | le64_to_cpu(stats->rmac_ttl_4096_8191_frms); |
fa1f0cb3 | 6462 | tmp_stats[i++] = |
ffb5df6c JP |
6463 | le64_to_cpu(stats->rmac_ttl_8192_max_frms); |
6464 | tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms); | |
6465 | tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms); | |
6466 | tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms); | |
6467 | tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms); | |
6468 | tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms); | |
6469 | tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard); | |
6470 | tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard); | |
6471 | tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard); | |
6472 | tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard); | |
6473 | tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard); | |
6474 | tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard); | |
6475 | tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard); | |
6476 | tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt); | |
fa1f0cb3 SS |
6477 | } |
6478 | ||
7ba013ac | 6479 | tmp_stats[i++] = 0; |
ffb5df6c JP |
6480 | tmp_stats[i++] = swstats->single_ecc_errs; |
6481 | tmp_stats[i++] = swstats->double_ecc_errs; | |
6482 | tmp_stats[i++] = swstats->parity_err_cnt; | |
6483 | tmp_stats[i++] = swstats->serious_err_cnt; | |
6484 | tmp_stats[i++] = swstats->soft_reset_cnt; | |
6485 | tmp_stats[i++] = swstats->fifo_full_cnt; | |
8116f3cf | 6486 | for (k = 0; k < MAX_RX_RINGS; k++) |
ffb5df6c JP |
6487 | tmp_stats[i++] = swstats->ring_full_cnt[k]; |
6488 | tmp_stats[i++] = xstats->alarm_transceiver_temp_high; | |
6489 | tmp_stats[i++] = xstats->alarm_transceiver_temp_low; | |
6490 | tmp_stats[i++] = xstats->alarm_laser_bias_current_high; | |
6491 | tmp_stats[i++] = xstats->alarm_laser_bias_current_low; | |
6492 | tmp_stats[i++] = xstats->alarm_laser_output_power_high; | |
6493 | tmp_stats[i++] = xstats->alarm_laser_output_power_low; | |
6494 | tmp_stats[i++] = xstats->warn_transceiver_temp_high; | |
6495 | tmp_stats[i++] = xstats->warn_transceiver_temp_low; | |
6496 | tmp_stats[i++] = xstats->warn_laser_bias_current_high; | |
6497 | tmp_stats[i++] = xstats->warn_laser_bias_current_low; | |
6498 | tmp_stats[i++] = xstats->warn_laser_output_power_high; | |
6499 | tmp_stats[i++] = xstats->warn_laser_output_power_low; | |
6500 | tmp_stats[i++] = swstats->clubbed_frms_cnt; | |
6501 | tmp_stats[i++] = swstats->sending_both; | |
6502 | tmp_stats[i++] = swstats->outof_sequence_pkts; | |
6503 | tmp_stats[i++] = swstats->flush_max_pkts; | |
6504 | if (swstats->num_aggregations) { | |
6505 | u64 tmp = swstats->sum_avg_pkts_aggregated; | |
bd1034f0 | 6506 | int count = 0; |
6aa20a22 | 6507 | /* |
bd1034f0 AR |
6508 | * Since 64-bit divide does not work on all platforms, |
6509 | * do repeated subtraction. | |
6510 | */ | |
ffb5df6c JP |
6511 | while (tmp >= swstats->num_aggregations) { |
6512 | tmp -= swstats->num_aggregations; | |
bd1034f0 AR |
6513 | count++; |
6514 | } | |
6515 | tmp_stats[i++] = count; | |
d44570e4 | 6516 | } else |
bd1034f0 | 6517 | tmp_stats[i++] = 0; |
ffb5df6c JP |
6518 | tmp_stats[i++] = swstats->mem_alloc_fail_cnt; |
6519 | tmp_stats[i++] = swstats->pci_map_fail_cnt; | |
6520 | tmp_stats[i++] = swstats->watchdog_timer_cnt; | |
6521 | tmp_stats[i++] = swstats->mem_allocated; | |
6522 | tmp_stats[i++] = swstats->mem_freed; | |
6523 | tmp_stats[i++] = swstats->link_up_cnt; | |
6524 | tmp_stats[i++] = swstats->link_down_cnt; | |
6525 | tmp_stats[i++] = swstats->link_up_time; | |
6526 | tmp_stats[i++] = swstats->link_down_time; | |
6527 | ||
6528 | tmp_stats[i++] = swstats->tx_buf_abort_cnt; | |
6529 | tmp_stats[i++] = swstats->tx_desc_abort_cnt; | |
6530 | tmp_stats[i++] = swstats->tx_parity_err_cnt; | |
6531 | tmp_stats[i++] = swstats->tx_link_loss_cnt; | |
6532 | tmp_stats[i++] = swstats->tx_list_proc_err_cnt; | |
6533 | ||
6534 | tmp_stats[i++] = swstats->rx_parity_err_cnt; | |
6535 | tmp_stats[i++] = swstats->rx_abort_cnt; | |
6536 | tmp_stats[i++] = swstats->rx_parity_abort_cnt; | |
6537 | tmp_stats[i++] = swstats->rx_rda_fail_cnt; | |
6538 | tmp_stats[i++] = swstats->rx_unkn_prot_cnt; | |
6539 | tmp_stats[i++] = swstats->rx_fcs_err_cnt; | |
6540 | tmp_stats[i++] = swstats->rx_buf_size_err_cnt; | |
6541 | tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt; | |
6542 | tmp_stats[i++] = swstats->rx_unkn_err_cnt; | |
6543 | tmp_stats[i++] = swstats->tda_err_cnt; | |
6544 | tmp_stats[i++] = swstats->pfc_err_cnt; | |
6545 | tmp_stats[i++] = swstats->pcc_err_cnt; | |
6546 | tmp_stats[i++] = swstats->tti_err_cnt; | |
6547 | tmp_stats[i++] = swstats->tpa_err_cnt; | |
6548 | tmp_stats[i++] = swstats->sm_err_cnt; | |
6549 | tmp_stats[i++] = swstats->lso_err_cnt; | |
6550 | tmp_stats[i++] = swstats->mac_tmac_err_cnt; | |
6551 | tmp_stats[i++] = swstats->mac_rmac_err_cnt; | |
6552 | tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt; | |
6553 | tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt; | |
6554 | tmp_stats[i++] = swstats->rc_err_cnt; | |
6555 | tmp_stats[i++] = swstats->prc_pcix_err_cnt; | |
6556 | tmp_stats[i++] = swstats->rpa_err_cnt; | |
6557 | tmp_stats[i++] = swstats->rda_err_cnt; | |
6558 | tmp_stats[i++] = swstats->rti_err_cnt; | |
6559 | tmp_stats[i++] = swstats->mc_err_cnt; | |
1da177e4 LT |
6560 | } |
6561 | ||
ac1f60db | 6562 | static int s2io_ethtool_get_regs_len(struct net_device *dev) |
1da177e4 | 6563 | { |
d44570e4 | 6564 | return XENA_REG_SPACE; |
1da177e4 LT |
6565 | } |
6566 | ||
6567 | ||
ac1f60db | 6568 | static int s2io_get_eeprom_len(struct net_device *dev) |
1da177e4 | 6569 | { |
d44570e4 | 6570 | return XENA_EEPROM_SPACE; |
1da177e4 LT |
6571 | } |
6572 | ||
b9f2c044 | 6573 | static int s2io_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 6574 | { |
4cf1653a | 6575 | struct s2io_nic *sp = netdev_priv(dev); |
b9f2c044 JG |
6576 | |
6577 | switch (sset) { | |
6578 | case ETH_SS_TEST: | |
6579 | return S2IO_TEST_LEN; | |
6580 | case ETH_SS_STATS: | |
d44570e4 | 6581 | switch (sp->device_type) { |
b9f2c044 JG |
6582 | case XFRAME_I_DEVICE: |
6583 | return XFRAME_I_STAT_LEN; | |
6584 | case XFRAME_II_DEVICE: | |
6585 | return XFRAME_II_STAT_LEN; | |
6586 | default: | |
6587 | return 0; | |
6588 | } | |
6589 | default: | |
6590 | return -EOPNOTSUPP; | |
6591 | } | |
1da177e4 | 6592 | } |
ac1f60db AB |
6593 | |
6594 | static void s2io_ethtool_get_strings(struct net_device *dev, | |
d44570e4 | 6595 | u32 stringset, u8 *data) |
1da177e4 | 6596 | { |
fa1f0cb3 | 6597 | int stat_size = 0; |
4cf1653a | 6598 | struct s2io_nic *sp = netdev_priv(dev); |
fa1f0cb3 | 6599 | |
1da177e4 LT |
6600 | switch (stringset) { |
6601 | case ETH_SS_TEST: | |
6602 | memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN); | |
6603 | break; | |
6604 | case ETH_SS_STATS: | |
fa1f0cb3 | 6605 | stat_size = sizeof(ethtool_xena_stats_keys); |
d44570e4 JP |
6606 | memcpy(data, ðtool_xena_stats_keys, stat_size); |
6607 | if (sp->device_type == XFRAME_II_DEVICE) { | |
fa1f0cb3 | 6608 | memcpy(data + stat_size, |
d44570e4 JP |
6609 | ðtool_enhanced_stats_keys, |
6610 | sizeof(ethtool_enhanced_stats_keys)); | |
fa1f0cb3 SS |
6611 | stat_size += sizeof(ethtool_enhanced_stats_keys); |
6612 | } | |
6613 | ||
6614 | memcpy(data + stat_size, ðtool_driver_stats_keys, | |
d44570e4 | 6615 | sizeof(ethtool_driver_stats_keys)); |
1da177e4 LT |
6616 | } |
6617 | } | |
1da177e4 | 6618 | |
b437a8cc | 6619 | static int s2io_set_features(struct net_device *dev, u32 features) |
958de193 JM |
6620 | { |
6621 | struct s2io_nic *sp = netdev_priv(dev); | |
b437a8cc | 6622 | u32 changed = (features ^ dev->features) & NETIF_F_LRO; |
958de193 JM |
6623 | |
6624 | if (changed && netif_running(dev)) { | |
b437a8cc MM |
6625 | int rc; |
6626 | ||
958de193 JM |
6627 | s2io_stop_all_tx_queue(sp); |
6628 | s2io_card_down(sp); | |
b437a8cc | 6629 | dev->features = features; |
958de193 JM |
6630 | rc = s2io_card_up(sp); |
6631 | if (rc) | |
6632 | s2io_reset(sp); | |
6633 | else | |
6634 | s2io_start_all_tx_queue(sp); | |
b437a8cc MM |
6635 | |
6636 | return rc ? rc : 1; | |
958de193 JM |
6637 | } |
6638 | ||
b437a8cc | 6639 | return 0; |
958de193 JM |
6640 | } |
6641 | ||
7282d491 | 6642 | static const struct ethtool_ops netdev_ethtool_ops = { |
1da177e4 LT |
6643 | .get_settings = s2io_ethtool_gset, |
6644 | .set_settings = s2io_ethtool_sset, | |
6645 | .get_drvinfo = s2io_ethtool_gdrvinfo, | |
6646 | .get_regs_len = s2io_ethtool_get_regs_len, | |
6647 | .get_regs = s2io_ethtool_gregs, | |
6648 | .get_link = ethtool_op_get_link, | |
6649 | .get_eeprom_len = s2io_get_eeprom_len, | |
6650 | .get_eeprom = s2io_ethtool_geeprom, | |
6651 | .set_eeprom = s2io_ethtool_seeprom, | |
0cec35eb | 6652 | .get_ringparam = s2io_ethtool_gringparam, |
1da177e4 LT |
6653 | .get_pauseparam = s2io_ethtool_getpause_data, |
6654 | .set_pauseparam = s2io_ethtool_setpause_data, | |
1da177e4 LT |
6655 | .self_test = s2io_ethtool_test, |
6656 | .get_strings = s2io_ethtool_get_strings, | |
034e3450 | 6657 | .set_phys_id = s2io_ethtool_set_led, |
b9f2c044 JG |
6658 | .get_ethtool_stats = s2io_get_ethtool_stats, |
6659 | .get_sset_count = s2io_get_sset_count, | |
1da177e4 LT |
6660 | }; |
6661 | ||
6662 | /** | |
20346722 | 6663 | * s2io_ioctl - Entry point for the Ioctl |
1da177e4 LT |
6664 | * @dev : Device pointer. |
6665 | * @ifr : An IOCTL specefic structure, that can contain a pointer to | |
6666 | * a proprietary structure used to pass information to the driver. | |
6667 | * @cmd : This is used to distinguish between the different commands that | |
6668 | * can be passed to the IOCTL functions. | |
6669 | * Description: | |
20346722 | 6670 | * Currently there are no special functionality supported in IOCTL, hence |
6671 | * function always return EOPNOTSUPPORTED | |
1da177e4 LT |
6672 | */ |
6673 | ||
ac1f60db | 6674 | static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1da177e4 LT |
6675 | { |
6676 | return -EOPNOTSUPP; | |
6677 | } | |
6678 | ||
6679 | /** | |
6680 | * s2io_change_mtu - entry point to change MTU size for the device. | |
6681 | * @dev : device pointer. | |
6682 | * @new_mtu : the new MTU size for the device. | |
6683 | * Description: A driver entry point to change MTU size for the device. | |
6684 | * Before changing the MTU the device must be stopped. | |
6685 | * Return value: | |
6686 | * 0 on success and an appropriate (-)ve integer as defined in errno.h | |
6687 | * file on failure. | |
6688 | */ | |
6689 | ||
ac1f60db | 6690 | static int s2io_change_mtu(struct net_device *dev, int new_mtu) |
1da177e4 | 6691 | { |
4cf1653a | 6692 | struct s2io_nic *sp = netdev_priv(dev); |
9f74ffde | 6693 | int ret = 0; |
1da177e4 LT |
6694 | |
6695 | if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) { | |
d44570e4 | 6696 | DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name); |
1da177e4 LT |
6697 | return -EPERM; |
6698 | } | |
6699 | ||
1da177e4 | 6700 | dev->mtu = new_mtu; |
d8892c6e | 6701 | if (netif_running(dev)) { |
3a3d5756 | 6702 | s2io_stop_all_tx_queue(sp); |
e6a8fee2 | 6703 | s2io_card_down(sp); |
9f74ffde SH |
6704 | ret = s2io_card_up(sp); |
6705 | if (ret) { | |
d8892c6e | 6706 | DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", |
b39d66a8 | 6707 | __func__); |
9f74ffde | 6708 | return ret; |
d8892c6e | 6709 | } |
3a3d5756 | 6710 | s2io_wake_all_tx_queue(sp); |
d8892c6e | 6711 | } else { /* Device is down */ |
1ee6dd77 | 6712 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
d8892c6e | 6713 | u64 val64 = new_mtu; |
6714 | ||
6715 | writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); | |
6716 | } | |
1da177e4 | 6717 | |
9f74ffde | 6718 | return ret; |
1da177e4 LT |
6719 | } |
6720 | ||
1da177e4 LT |
6721 | /** |
6722 | * s2io_set_link - Set the LInk status | |
6723 | * @data: long pointer to device private structue | |
6724 | * Description: Sets the link status for the adapter | |
6725 | */ | |
6726 | ||
c4028958 | 6727 | static void s2io_set_link(struct work_struct *work) |
1da177e4 | 6728 | { |
d44570e4 JP |
6729 | struct s2io_nic *nic = container_of(work, struct s2io_nic, |
6730 | set_link_task); | |
1da177e4 | 6731 | struct net_device *dev = nic->dev; |
1ee6dd77 | 6732 | struct XENA_dev_config __iomem *bar0 = nic->bar0; |
1da177e4 LT |
6733 | register u64 val64; |
6734 | u16 subid; | |
6735 | ||
22747d6b FR |
6736 | rtnl_lock(); |
6737 | ||
6738 | if (!netif_running(dev)) | |
6739 | goto out_unlock; | |
6740 | ||
92b84437 | 6741 | if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) { |
1da177e4 | 6742 | /* The card is being reset, no point doing anything */ |
22747d6b | 6743 | goto out_unlock; |
1da177e4 LT |
6744 | } |
6745 | ||
6746 | subid = nic->pdev->subsystem_device; | |
a371a07d | 6747 | if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) { |
6748 | /* | |
6749 | * Allow a small delay for the NICs self initiated | |
6750 | * cleanup to complete. | |
6751 | */ | |
6752 | msleep(100); | |
6753 | } | |
1da177e4 LT |
6754 | |
6755 | val64 = readq(&bar0->adapter_status); | |
19a60522 SS |
6756 | if (LINK_IS_UP(val64)) { |
6757 | if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) { | |
6758 | if (verify_xena_quiescence(nic)) { | |
6759 | val64 = readq(&bar0->adapter_control); | |
6760 | val64 |= ADAPTER_CNTL_EN; | |
1da177e4 | 6761 | writeq(val64, &bar0->adapter_control); |
19a60522 | 6762 | if (CARDS_WITH_FAULTY_LINK_INDICATORS( |
d44570e4 | 6763 | nic->device_type, subid)) { |
19a60522 SS |
6764 | val64 = readq(&bar0->gpio_control); |
6765 | val64 |= GPIO_CTRL_GPIO_0; | |
6766 | writeq(val64, &bar0->gpio_control); | |
6767 | val64 = readq(&bar0->gpio_control); | |
6768 | } else { | |
6769 | val64 |= ADAPTER_LED_ON; | |
6770 | writeq(val64, &bar0->adapter_control); | |
a371a07d | 6771 | } |
f957bcf0 | 6772 | nic->device_enabled_once = true; |
19a60522 | 6773 | } else { |
9e39f7c5 JP |
6774 | DBG_PRINT(ERR_DBG, |
6775 | "%s: Error: device is not Quiescent\n", | |
6776 | dev->name); | |
3a3d5756 | 6777 | s2io_stop_all_tx_queue(nic); |
1da177e4 | 6778 | } |
19a60522 | 6779 | } |
92c48799 SS |
6780 | val64 = readq(&bar0->adapter_control); |
6781 | val64 |= ADAPTER_LED_ON; | |
6782 | writeq(val64, &bar0->adapter_control); | |
6783 | s2io_link(nic, LINK_UP); | |
19a60522 SS |
6784 | } else { |
6785 | if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type, | |
6786 | subid)) { | |
6787 | val64 = readq(&bar0->gpio_control); | |
6788 | val64 &= ~GPIO_CTRL_GPIO_0; | |
6789 | writeq(val64, &bar0->gpio_control); | |
6790 | val64 = readq(&bar0->gpio_control); | |
1da177e4 | 6791 | } |
92c48799 SS |
6792 | /* turn off LED */ |
6793 | val64 = readq(&bar0->adapter_control); | |
d44570e4 | 6794 | val64 = val64 & (~ADAPTER_LED_ON); |
92c48799 | 6795 | writeq(val64, &bar0->adapter_control); |
19a60522 | 6796 | s2io_link(nic, LINK_DOWN); |
1da177e4 | 6797 | } |
92b84437 | 6798 | clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state)); |
22747d6b FR |
6799 | |
6800 | out_unlock: | |
d8d70caf | 6801 | rtnl_unlock(); |
1da177e4 LT |
6802 | } |
6803 | ||
1ee6dd77 | 6804 | static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp, |
d44570e4 JP |
6805 | struct buffAdd *ba, |
6806 | struct sk_buff **skb, u64 *temp0, u64 *temp1, | |
6807 | u64 *temp2, int size) | |
5d3213cc AR |
6808 | { |
6809 | struct net_device *dev = sp->dev; | |
491abf25 | 6810 | struct swStat *stats = &sp->mac_control.stats_info->sw_stat; |
5d3213cc AR |
6811 | |
6812 | if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) { | |
6d517a27 | 6813 | struct RxD1 *rxdp1 = (struct RxD1 *)rxdp; |
5d3213cc AR |
6814 | /* allocate skb */ |
6815 | if (*skb) { | |
6816 | DBG_PRINT(INFO_DBG, "SKB is not NULL\n"); | |
6817 | /* | |
6818 | * As Rx frame are not going to be processed, | |
6819 | * using same mapped address for the Rxd | |
6820 | * buffer pointer | |
6821 | */ | |
6d517a27 | 6822 | rxdp1->Buffer0_ptr = *temp0; |
5d3213cc AR |
6823 | } else { |
6824 | *skb = dev_alloc_skb(size); | |
6825 | if (!(*skb)) { | |
9e39f7c5 JP |
6826 | DBG_PRINT(INFO_DBG, |
6827 | "%s: Out of memory to allocate %s\n", | |
6828 | dev->name, "1 buf mode SKBs"); | |
ffb5df6c | 6829 | stats->mem_alloc_fail_cnt++; |
5d3213cc AR |
6830 | return -ENOMEM ; |
6831 | } | |
ffb5df6c | 6832 | stats->mem_allocated += (*skb)->truesize; |
5d3213cc AR |
6833 | /* storing the mapped addr in a temp variable |
6834 | * such it will be used for next rxd whose | |
6835 | * Host Control is NULL | |
6836 | */ | |
6d517a27 | 6837 | rxdp1->Buffer0_ptr = *temp0 = |
d44570e4 JP |
6838 | pci_map_single(sp->pdev, (*skb)->data, |
6839 | size - NET_IP_ALIGN, | |
6840 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 6841 | if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr)) |
491abf25 | 6842 | goto memalloc_failed; |
5d3213cc AR |
6843 | rxdp->Host_Control = (unsigned long) (*skb); |
6844 | } | |
6845 | } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) { | |
6d517a27 | 6846 | struct RxD3 *rxdp3 = (struct RxD3 *)rxdp; |
5d3213cc AR |
6847 | /* Two buffer Mode */ |
6848 | if (*skb) { | |
6d517a27 VP |
6849 | rxdp3->Buffer2_ptr = *temp2; |
6850 | rxdp3->Buffer0_ptr = *temp0; | |
6851 | rxdp3->Buffer1_ptr = *temp1; | |
5d3213cc AR |
6852 | } else { |
6853 | *skb = dev_alloc_skb(size); | |
2ceaac75 | 6854 | if (!(*skb)) { |
9e39f7c5 JP |
6855 | DBG_PRINT(INFO_DBG, |
6856 | "%s: Out of memory to allocate %s\n", | |
6857 | dev->name, | |
6858 | "2 buf mode SKBs"); | |
ffb5df6c | 6859 | stats->mem_alloc_fail_cnt++; |
2ceaac75 DR |
6860 | return -ENOMEM; |
6861 | } | |
ffb5df6c | 6862 | stats->mem_allocated += (*skb)->truesize; |
6d517a27 | 6863 | rxdp3->Buffer2_ptr = *temp2 = |
5d3213cc AR |
6864 | pci_map_single(sp->pdev, (*skb)->data, |
6865 | dev->mtu + 4, | |
6866 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 6867 | if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr)) |
491abf25 | 6868 | goto memalloc_failed; |
6d517a27 | 6869 | rxdp3->Buffer0_ptr = *temp0 = |
d44570e4 JP |
6870 | pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN, |
6871 | PCI_DMA_FROMDEVICE); | |
8d8bb39b | 6872 | if (pci_dma_mapping_error(sp->pdev, |
d44570e4 JP |
6873 | rxdp3->Buffer0_ptr)) { |
6874 | pci_unmap_single(sp->pdev, | |
6875 | (dma_addr_t)rxdp3->Buffer2_ptr, | |
6876 | dev->mtu + 4, | |
6877 | PCI_DMA_FROMDEVICE); | |
491abf25 VP |
6878 | goto memalloc_failed; |
6879 | } | |
5d3213cc AR |
6880 | rxdp->Host_Control = (unsigned long) (*skb); |
6881 | ||
6882 | /* Buffer-1 will be dummy buffer not used */ | |
6d517a27 | 6883 | rxdp3->Buffer1_ptr = *temp1 = |
5d3213cc | 6884 | pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN, |
d44570e4 | 6885 | PCI_DMA_FROMDEVICE); |
8d8bb39b | 6886 | if (pci_dma_mapping_error(sp->pdev, |
d44570e4 JP |
6887 | rxdp3->Buffer1_ptr)) { |
6888 | pci_unmap_single(sp->pdev, | |
6889 | (dma_addr_t)rxdp3->Buffer0_ptr, | |
6890 | BUF0_LEN, PCI_DMA_FROMDEVICE); | |
6891 | pci_unmap_single(sp->pdev, | |
6892 | (dma_addr_t)rxdp3->Buffer2_ptr, | |
6893 | dev->mtu + 4, | |
6894 | PCI_DMA_FROMDEVICE); | |
491abf25 VP |
6895 | goto memalloc_failed; |
6896 | } | |
5d3213cc AR |
6897 | } |
6898 | } | |
6899 | return 0; | |
d44570e4 JP |
6900 | |
6901 | memalloc_failed: | |
6902 | stats->pci_map_fail_cnt++; | |
6903 | stats->mem_freed += (*skb)->truesize; | |
6904 | dev_kfree_skb(*skb); | |
6905 | return -ENOMEM; | |
5d3213cc | 6906 | } |
491abf25 | 6907 | |
1ee6dd77 RB |
6908 | static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp, |
6909 | int size) | |
5d3213cc AR |
6910 | { |
6911 | struct net_device *dev = sp->dev; | |
6912 | if (sp->rxd_mode == RXD_MODE_1) { | |
d44570e4 | 6913 | rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN); |
5d3213cc AR |
6914 | } else if (sp->rxd_mode == RXD_MODE_3B) { |
6915 | rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN); | |
6916 | rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1); | |
d44570e4 | 6917 | rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4); |
5d3213cc AR |
6918 | } |
6919 | } | |
6920 | ||
1ee6dd77 | 6921 | static int rxd_owner_bit_reset(struct s2io_nic *sp) |
5d3213cc AR |
6922 | { |
6923 | int i, j, k, blk_cnt = 0, size; | |
5d3213cc | 6924 | struct config_param *config = &sp->config; |
ffb5df6c | 6925 | struct mac_info *mac_control = &sp->mac_control; |
5d3213cc | 6926 | struct net_device *dev = sp->dev; |
1ee6dd77 | 6927 | struct RxD_t *rxdp = NULL; |
5d3213cc | 6928 | struct sk_buff *skb = NULL; |
1ee6dd77 | 6929 | struct buffAdd *ba = NULL; |
5d3213cc AR |
6930 | u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0; |
6931 | ||
6932 | /* Calculate the size based on ring mode */ | |
6933 | size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE + | |
6934 | HEADER_802_2_SIZE + HEADER_SNAP_SIZE; | |
6935 | if (sp->rxd_mode == RXD_MODE_1) | |
6936 | size += NET_IP_ALIGN; | |
6937 | else if (sp->rxd_mode == RXD_MODE_3B) | |
6938 | size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4; | |
5d3213cc AR |
6939 | |
6940 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
6941 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
6942 | struct ring_info *ring = &mac_control->rings[i]; | |
6943 | ||
d44570e4 | 6944 | blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1); |
5d3213cc AR |
6945 | |
6946 | for (j = 0; j < blk_cnt; j++) { | |
6947 | for (k = 0; k < rxd_count[sp->rxd_mode]; k++) { | |
d44570e4 JP |
6948 | rxdp = ring->rx_blocks[j].rxds[k].virt_addr; |
6949 | if (sp->rxd_mode == RXD_MODE_3B) | |
13d866a9 | 6950 | ba = &ring->ba[j][k]; |
d44570e4 JP |
6951 | if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb, |
6952 | (u64 *)&temp0_64, | |
6953 | (u64 *)&temp1_64, | |
6954 | (u64 *)&temp2_64, | |
6955 | size) == -ENOMEM) { | |
ac1f90d6 SS |
6956 | return 0; |
6957 | } | |
5d3213cc AR |
6958 | |
6959 | set_rxd_buffer_size(sp, rxdp, size); | |
6960 | wmb(); | |
6961 | /* flip the Ownership bit to Hardware */ | |
6962 | rxdp->Control_1 |= RXD_OWN_XENA; | |
6963 | } | |
6964 | } | |
6965 | } | |
6966 | return 0; | |
6967 | ||
6968 | } | |
6969 | ||
d44570e4 | 6970 | static int s2io_add_isr(struct s2io_nic *sp) |
1da177e4 | 6971 | { |
e6a8fee2 | 6972 | int ret = 0; |
c92ca04b | 6973 | struct net_device *dev = sp->dev; |
e6a8fee2 | 6974 | int err = 0; |
1da177e4 | 6975 | |
eaae7f72 | 6976 | if (sp->config.intr_type == MSI_X) |
e6a8fee2 AR |
6977 | ret = s2io_enable_msi_x(sp); |
6978 | if (ret) { | |
6979 | DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name); | |
eaae7f72 | 6980 | sp->config.intr_type = INTA; |
20346722 | 6981 | } |
1da177e4 | 6982 | |
d44570e4 JP |
6983 | /* |
6984 | * Store the values of the MSIX table in | |
6985 | * the struct s2io_nic structure | |
6986 | */ | |
e6a8fee2 | 6987 | store_xmsi_data(sp); |
c92ca04b | 6988 | |
e6a8fee2 | 6989 | /* After proper initialization of H/W, register ISR */ |
eaae7f72 | 6990 | if (sp->config.intr_type == MSI_X) { |
ac731ab6 SH |
6991 | int i, msix_rx_cnt = 0; |
6992 | ||
f61e0a35 SH |
6993 | for (i = 0; i < sp->num_entries; i++) { |
6994 | if (sp->s2io_entries[i].in_use == MSIX_FLG) { | |
6995 | if (sp->s2io_entries[i].type == | |
d44570e4 | 6996 | MSIX_RING_TYPE) { |
ac731ab6 SH |
6997 | sprintf(sp->desc[i], "%s:MSI-X-%d-RX", |
6998 | dev->name, i); | |
6999 | err = request_irq(sp->entries[i].vector, | |
d44570e4 JP |
7000 | s2io_msix_ring_handle, |
7001 | 0, | |
7002 | sp->desc[i], | |
7003 | sp->s2io_entries[i].arg); | |
ac731ab6 | 7004 | } else if (sp->s2io_entries[i].type == |
d44570e4 | 7005 | MSIX_ALARM_TYPE) { |
ac731ab6 | 7006 | sprintf(sp->desc[i], "%s:MSI-X-%d-TX", |
d44570e4 | 7007 | dev->name, i); |
ac731ab6 | 7008 | err = request_irq(sp->entries[i].vector, |
d44570e4 JP |
7009 | s2io_msix_fifo_handle, |
7010 | 0, | |
7011 | sp->desc[i], | |
7012 | sp->s2io_entries[i].arg); | |
ac731ab6 | 7013 | |
fb6a825b | 7014 | } |
ac731ab6 SH |
7015 | /* if either data or addr is zero print it. */ |
7016 | if (!(sp->msix_info[i].addr && | |
d44570e4 | 7017 | sp->msix_info[i].data)) { |
ac731ab6 | 7018 | DBG_PRINT(ERR_DBG, |
d44570e4 JP |
7019 | "%s @Addr:0x%llx Data:0x%llx\n", |
7020 | sp->desc[i], | |
7021 | (unsigned long long) | |
7022 | sp->msix_info[i].addr, | |
7023 | (unsigned long long) | |
7024 | ntohl(sp->msix_info[i].data)); | |
ac731ab6 | 7025 | } else |
fb6a825b | 7026 | msix_rx_cnt++; |
ac731ab6 SH |
7027 | if (err) { |
7028 | remove_msix_isr(sp); | |
7029 | ||
7030 | DBG_PRINT(ERR_DBG, | |
d44570e4 JP |
7031 | "%s:MSI-X-%d registration " |
7032 | "failed\n", dev->name, i); | |
ac731ab6 SH |
7033 | |
7034 | DBG_PRINT(ERR_DBG, | |
d44570e4 JP |
7035 | "%s: Defaulting to INTA\n", |
7036 | dev->name); | |
ac731ab6 SH |
7037 | sp->config.intr_type = INTA; |
7038 | break; | |
fb6a825b | 7039 | } |
ac731ab6 SH |
7040 | sp->s2io_entries[i].in_use = |
7041 | MSIX_REGISTERED_SUCCESS; | |
c92ca04b | 7042 | } |
e6a8fee2 | 7043 | } |
18b2b7bd | 7044 | if (!err) { |
6cef2b8e | 7045 | pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt); |
9e39f7c5 JP |
7046 | DBG_PRINT(INFO_DBG, |
7047 | "MSI-X-TX entries enabled through alarm vector\n"); | |
18b2b7bd | 7048 | } |
e6a8fee2 | 7049 | } |
eaae7f72 | 7050 | if (sp->config.intr_type == INTA) { |
d44570e4 JP |
7051 | err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED, |
7052 | sp->name, dev); | |
e6a8fee2 AR |
7053 | if (err) { |
7054 | DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n", | |
7055 | dev->name); | |
7056 | return -1; | |
7057 | } | |
7058 | } | |
7059 | return 0; | |
7060 | } | |
d44570e4 JP |
7061 | |
7062 | static void s2io_rem_isr(struct s2io_nic *sp) | |
e6a8fee2 | 7063 | { |
18b2b7bd SH |
7064 | if (sp->config.intr_type == MSI_X) |
7065 | remove_msix_isr(sp); | |
7066 | else | |
7067 | remove_inta_isr(sp); | |
e6a8fee2 AR |
7068 | } |
7069 | ||
d44570e4 | 7070 | static void do_s2io_card_down(struct s2io_nic *sp, int do_io) |
e6a8fee2 AR |
7071 | { |
7072 | int cnt = 0; | |
1ee6dd77 | 7073 | struct XENA_dev_config __iomem *bar0 = sp->bar0; |
e6a8fee2 | 7074 | register u64 val64 = 0; |
5f490c96 SH |
7075 | struct config_param *config; |
7076 | config = &sp->config; | |
e6a8fee2 | 7077 | |
9f74ffde SH |
7078 | if (!is_s2io_card_up(sp)) |
7079 | return; | |
7080 | ||
e6a8fee2 AR |
7081 | del_timer_sync(&sp->alarm_timer); |
7082 | /* If s2io_set_link task is executing, wait till it completes. */ | |
d44570e4 | 7083 | while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) |
e6a8fee2 | 7084 | msleep(50); |
92b84437 | 7085 | clear_bit(__S2IO_STATE_CARD_UP, &sp->state); |
e6a8fee2 | 7086 | |
5f490c96 | 7087 | /* Disable napi */ |
f61e0a35 SH |
7088 | if (sp->config.napi) { |
7089 | int off = 0; | |
7090 | if (config->intr_type == MSI_X) { | |
7091 | for (; off < sp->config.rx_ring_num; off++) | |
7092 | napi_disable(&sp->mac_control.rings[off].napi); | |
d44570e4 | 7093 | } |
f61e0a35 SH |
7094 | else |
7095 | napi_disable(&sp->napi); | |
7096 | } | |
5f490c96 | 7097 | |
e6a8fee2 | 7098 | /* disable Tx and Rx traffic on the NIC */ |
d796fdb7 LV |
7099 | if (do_io) |
7100 | stop_nic(sp); | |
e6a8fee2 AR |
7101 | |
7102 | s2io_rem_isr(sp); | |
1da177e4 | 7103 | |
01e16faa SH |
7104 | /* stop the tx queue, indicate link down */ |
7105 | s2io_link(sp, LINK_DOWN); | |
7106 | ||
1da177e4 | 7107 | /* Check if the device is Quiescent and then Reset the NIC */ |
d44570e4 | 7108 | while (do_io) { |
5d3213cc AR |
7109 | /* As per the HW requirement we need to replenish the |
7110 | * receive buffer to avoid the ring bump. Since there is | |
7111 | * no intention of processing the Rx frame at this pointwe are | |
70f23fd6 | 7112 | * just setting the ownership bit of rxd in Each Rx |
5d3213cc AR |
7113 | * ring to HW and set the appropriate buffer size |
7114 | * based on the ring mode | |
7115 | */ | |
7116 | rxd_owner_bit_reset(sp); | |
7117 | ||
1da177e4 | 7118 | val64 = readq(&bar0->adapter_status); |
19a60522 | 7119 | if (verify_xena_quiescence(sp)) { |
d44570e4 JP |
7120 | if (verify_pcc_quiescent(sp, sp->device_enabled_once)) |
7121 | break; | |
1da177e4 LT |
7122 | } |
7123 | ||
7124 | msleep(50); | |
7125 | cnt++; | |
7126 | if (cnt == 10) { | |
9e39f7c5 JP |
7127 | DBG_PRINT(ERR_DBG, "Device not Quiescent - " |
7128 | "adapter status reads 0x%llx\n", | |
d44570e4 | 7129 | (unsigned long long)val64); |
1da177e4 LT |
7130 | break; |
7131 | } | |
d796fdb7 LV |
7132 | } |
7133 | if (do_io) | |
7134 | s2io_reset(sp); | |
1da177e4 | 7135 | |
7ba013ac | 7136 | /* Free all Tx buffers */ |
1da177e4 | 7137 | free_tx_buffers(sp); |
7ba013ac | 7138 | |
7139 | /* Free all Rx buffers */ | |
1da177e4 LT |
7140 | free_rx_buffers(sp); |
7141 | ||
92b84437 | 7142 | clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state)); |
1da177e4 LT |
7143 | } |
7144 | ||
d44570e4 | 7145 | static void s2io_card_down(struct s2io_nic *sp) |
d796fdb7 LV |
7146 | { |
7147 | do_s2io_card_down(sp, 1); | |
7148 | } | |
7149 | ||
d44570e4 | 7150 | static int s2io_card_up(struct s2io_nic *sp) |
1da177e4 | 7151 | { |
cc6e7c44 | 7152 | int i, ret = 0; |
1da177e4 | 7153 | struct config_param *config; |
ffb5df6c | 7154 | struct mac_info *mac_control; |
d44570e4 | 7155 | struct net_device *dev = (struct net_device *)sp->dev; |
e6a8fee2 | 7156 | u16 interruptible; |
1da177e4 LT |
7157 | |
7158 | /* Initialize the H/W I/O registers */ | |
9f74ffde SH |
7159 | ret = init_nic(sp); |
7160 | if (ret != 0) { | |
1da177e4 LT |
7161 | DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n", |
7162 | dev->name); | |
9f74ffde SH |
7163 | if (ret != -EIO) |
7164 | s2io_reset(sp); | |
7165 | return ret; | |
1da177e4 LT |
7166 | } |
7167 | ||
20346722 | 7168 | /* |
7169 | * Initializing the Rx buffers. For now we are considering only 1 | |
1da177e4 LT |
7170 | * Rx ring and initializing buffers into 30 Rx blocks |
7171 | */ | |
1da177e4 | 7172 | config = &sp->config; |
ffb5df6c | 7173 | mac_control = &sp->mac_control; |
1da177e4 LT |
7174 | |
7175 | for (i = 0; i < config->rx_ring_num; i++) { | |
13d866a9 JP |
7176 | struct ring_info *ring = &mac_control->rings[i]; |
7177 | ||
7178 | ring->mtu = dev->mtu; | |
f0c54ace | 7179 | ring->lro = !!(dev->features & NETIF_F_LRO); |
13d866a9 | 7180 | ret = fill_rx_buffers(sp, ring, 1); |
0425b46a | 7181 | if (ret) { |
1da177e4 LT |
7182 | DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n", |
7183 | dev->name); | |
7184 | s2io_reset(sp); | |
7185 | free_rx_buffers(sp); | |
7186 | return -ENOMEM; | |
7187 | } | |
7188 | DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i, | |
13d866a9 | 7189 | ring->rx_bufs_left); |
1da177e4 | 7190 | } |
5f490c96 SH |
7191 | |
7192 | /* Initialise napi */ | |
f61e0a35 | 7193 | if (config->napi) { |
f61e0a35 SH |
7194 | if (config->intr_type == MSI_X) { |
7195 | for (i = 0; i < sp->config.rx_ring_num; i++) | |
7196 | napi_enable(&sp->mac_control.rings[i].napi); | |
7197 | } else { | |
7198 | napi_enable(&sp->napi); | |
7199 | } | |
7200 | } | |
5f490c96 | 7201 | |
19a60522 SS |
7202 | /* Maintain the state prior to the open */ |
7203 | if (sp->promisc_flg) | |
7204 | sp->promisc_flg = 0; | |
7205 | if (sp->m_cast_flg) { | |
7206 | sp->m_cast_flg = 0; | |
d44570e4 | 7207 | sp->all_multi_pos = 0; |
19a60522 | 7208 | } |
1da177e4 LT |
7209 | |
7210 | /* Setting its receive mode */ | |
7211 | s2io_set_multicast(dev); | |
7212 | ||
f0c54ace | 7213 | if (dev->features & NETIF_F_LRO) { |
b41477f3 | 7214 | /* Initialize max aggregatable pkts per session based on MTU */ |
7d3d0439 | 7215 | sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu; |
d44570e4 | 7216 | /* Check if we can use (if specified) user provided value */ |
7d3d0439 RA |
7217 | if (lro_max_pkts < sp->lro_max_aggr_per_sess) |
7218 | sp->lro_max_aggr_per_sess = lro_max_pkts; | |
7219 | } | |
7220 | ||
1da177e4 LT |
7221 | /* Enable Rx Traffic and interrupts on the NIC */ |
7222 | if (start_nic(sp)) { | |
7223 | DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name); | |
1da177e4 | 7224 | s2io_reset(sp); |
e6a8fee2 AR |
7225 | free_rx_buffers(sp); |
7226 | return -ENODEV; | |
7227 | } | |
7228 | ||
7229 | /* Add interrupt service routine */ | |
7230 | if (s2io_add_isr(sp) != 0) { | |
eaae7f72 | 7231 | if (sp->config.intr_type == MSI_X) |
e6a8fee2 AR |
7232 | s2io_rem_isr(sp); |
7233 | s2io_reset(sp); | |
1da177e4 LT |
7234 | free_rx_buffers(sp); |
7235 | return -ENODEV; | |
7236 | } | |
7237 | ||
25fff88e | 7238 | S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2)); |
7239 | ||
01e16faa SH |
7240 | set_bit(__S2IO_STATE_CARD_UP, &sp->state); |
7241 | ||
e6a8fee2 | 7242 | /* Enable select interrupts */ |
9caab458 | 7243 | en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS); |
01e16faa SH |
7244 | if (sp->config.intr_type != INTA) { |
7245 | interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR; | |
7246 | en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS); | |
7247 | } else { | |
e6a8fee2 | 7248 | interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR; |
9caab458 | 7249 | interruptible |= TX_PIC_INTR; |
e6a8fee2 AR |
7250 | en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS); |
7251 | } | |
7252 | ||
1da177e4 LT |
7253 | return 0; |
7254 | } | |
7255 | ||
20346722 | 7256 | /** |
1da177e4 LT |
7257 | * s2io_restart_nic - Resets the NIC. |
7258 | * @data : long pointer to the device private structure | |
7259 | * Description: | |
7260 | * This function is scheduled to be run by the s2io_tx_watchdog | |
20346722 | 7261 | * function after 0.5 secs to reset the NIC. The idea is to reduce |
1da177e4 LT |
7262 | * the run time of the watch dog routine which is run holding a |
7263 | * spin lock. | |
7264 | */ | |
7265 | ||
c4028958 | 7266 | static void s2io_restart_nic(struct work_struct *work) |
1da177e4 | 7267 | { |
1ee6dd77 | 7268 | struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task); |
c4028958 | 7269 | struct net_device *dev = sp->dev; |
1da177e4 | 7270 | |
22747d6b FR |
7271 | rtnl_lock(); |
7272 | ||
7273 | if (!netif_running(dev)) | |
7274 | goto out_unlock; | |
7275 | ||
e6a8fee2 | 7276 | s2io_card_down(sp); |
1da177e4 | 7277 | if (s2io_card_up(sp)) { |
d44570e4 | 7278 | DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name); |
1da177e4 | 7279 | } |
3a3d5756 | 7280 | s2io_wake_all_tx_queue(sp); |
d44570e4 | 7281 | DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name); |
22747d6b FR |
7282 | out_unlock: |
7283 | rtnl_unlock(); | |
1da177e4 LT |
7284 | } |
7285 | ||
20346722 | 7286 | /** |
7287 | * s2io_tx_watchdog - Watchdog for transmit side. | |
1da177e4 LT |
7288 | * @dev : Pointer to net device structure |
7289 | * Description: | |
7290 | * This function is triggered if the Tx Queue is stopped | |
7291 | * for a pre-defined amount of time when the Interface is still up. | |
7292 | * If the Interface is jammed in such a situation, the hardware is | |
7293 | * reset (by s2io_close) and restarted again (by s2io_open) to | |
7294 | * overcome any problem that might have been caused in the hardware. | |
7295 | * Return value: | |
7296 | * void | |
7297 | */ | |
7298 | ||
7299 | static void s2io_tx_watchdog(struct net_device *dev) | |
7300 | { | |
4cf1653a | 7301 | struct s2io_nic *sp = netdev_priv(dev); |
ffb5df6c | 7302 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
1da177e4 LT |
7303 | |
7304 | if (netif_carrier_ok(dev)) { | |
ffb5df6c | 7305 | swstats->watchdog_timer_cnt++; |
1da177e4 | 7306 | schedule_work(&sp->rst_timer_task); |
ffb5df6c | 7307 | swstats->soft_reset_cnt++; |
1da177e4 LT |
7308 | } |
7309 | } | |
7310 | ||
7311 | /** | |
7312 | * rx_osm_handler - To perform some OS related operations on SKB. | |
7313 | * @sp: private member of the device structure,pointer to s2io_nic structure. | |
7314 | * @skb : the socket buffer pointer. | |
7315 | * @len : length of the packet | |
7316 | * @cksum : FCS checksum of the frame. | |
7317 | * @ring_no : the ring from which this RxD was extracted. | |
20346722 | 7318 | * Description: |
b41477f3 | 7319 | * This function is called by the Rx interrupt serivce routine to perform |
1da177e4 LT |
7320 | * some OS related operations on the SKB before passing it to the upper |
7321 | * layers. It mainly checks if the checksum is OK, if so adds it to the | |
7322 | * SKBs cksum variable, increments the Rx packet count and passes the SKB | |
7323 | * to the upper layer. If the checksum is wrong, it increments the Rx | |
7324 | * packet error count, frees the SKB and returns error. | |
7325 | * Return value: | |
7326 | * SUCCESS on success and -1 on failure. | |
7327 | */ | |
1ee6dd77 | 7328 | static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp) |
1da177e4 | 7329 | { |
1ee6dd77 | 7330 | struct s2io_nic *sp = ring_data->nic; |
d44570e4 | 7331 | struct net_device *dev = (struct net_device *)ring_data->dev; |
20346722 | 7332 | struct sk_buff *skb = (struct sk_buff *) |
d44570e4 | 7333 | ((unsigned long)rxdp->Host_Control); |
20346722 | 7334 | int ring_no = ring_data->ring_no; |
1da177e4 | 7335 | u16 l3_csum, l4_csum; |
863c11a9 | 7336 | unsigned long long err = rxdp->Control_1 & RXD_T_CODE; |
2e6a684b | 7337 | struct lro *uninitialized_var(lro); |
f9046eb3 | 7338 | u8 err_mask; |
ffb5df6c | 7339 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
da6971d8 | 7340 | |
20346722 | 7341 | skb->dev = dev; |
c92ca04b | 7342 | |
863c11a9 | 7343 | if (err) { |
bd1034f0 | 7344 | /* Check for parity error */ |
d44570e4 | 7345 | if (err & 0x1) |
ffb5df6c | 7346 | swstats->parity_err_cnt++; |
d44570e4 | 7347 | |
f9046eb3 | 7348 | err_mask = err >> 48; |
d44570e4 JP |
7349 | switch (err_mask) { |
7350 | case 1: | |
ffb5df6c | 7351 | swstats->rx_parity_err_cnt++; |
491976b2 SH |
7352 | break; |
7353 | ||
d44570e4 | 7354 | case 2: |
ffb5df6c | 7355 | swstats->rx_abort_cnt++; |
491976b2 SH |
7356 | break; |
7357 | ||
d44570e4 | 7358 | case 3: |
ffb5df6c | 7359 | swstats->rx_parity_abort_cnt++; |
491976b2 SH |
7360 | break; |
7361 | ||
d44570e4 | 7362 | case 4: |
ffb5df6c | 7363 | swstats->rx_rda_fail_cnt++; |
491976b2 SH |
7364 | break; |
7365 | ||
d44570e4 | 7366 | case 5: |
ffb5df6c | 7367 | swstats->rx_unkn_prot_cnt++; |
491976b2 SH |
7368 | break; |
7369 | ||
d44570e4 | 7370 | case 6: |
ffb5df6c | 7371 | swstats->rx_fcs_err_cnt++; |
491976b2 | 7372 | break; |
bd1034f0 | 7373 | |
d44570e4 | 7374 | case 7: |
ffb5df6c | 7375 | swstats->rx_buf_size_err_cnt++; |
491976b2 SH |
7376 | break; |
7377 | ||
d44570e4 | 7378 | case 8: |
ffb5df6c | 7379 | swstats->rx_rxd_corrupt_cnt++; |
491976b2 SH |
7380 | break; |
7381 | ||
d44570e4 | 7382 | case 15: |
ffb5df6c | 7383 | swstats->rx_unkn_err_cnt++; |
491976b2 SH |
7384 | break; |
7385 | } | |
863c11a9 | 7386 | /* |
d44570e4 JP |
7387 | * Drop the packet if bad transfer code. Exception being |
7388 | * 0x5, which could be due to unsupported IPv6 extension header. | |
7389 | * In this case, we let stack handle the packet. | |
7390 | * Note that in this case, since checksum will be incorrect, | |
7391 | * stack will validate the same. | |
7392 | */ | |
f9046eb3 OH |
7393 | if (err_mask != 0x5) { |
7394 | DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n", | |
d44570e4 | 7395 | dev->name, err_mask); |
dc56e634 | 7396 | dev->stats.rx_crc_errors++; |
ffb5df6c | 7397 | swstats->mem_freed |
491976b2 | 7398 | += skb->truesize; |
863c11a9 | 7399 | dev_kfree_skb(skb); |
0425b46a | 7400 | ring_data->rx_bufs_left -= 1; |
863c11a9 AR |
7401 | rxdp->Host_Control = 0; |
7402 | return 0; | |
7403 | } | |
20346722 | 7404 | } |
1da177e4 | 7405 | |
20346722 | 7406 | rxdp->Host_Control = 0; |
da6971d8 AR |
7407 | if (sp->rxd_mode == RXD_MODE_1) { |
7408 | int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2); | |
20346722 | 7409 | |
da6971d8 | 7410 | skb_put(skb, len); |
6d517a27 | 7411 | } else if (sp->rxd_mode == RXD_MODE_3B) { |
da6971d8 AR |
7412 | int get_block = ring_data->rx_curr_get_info.block_index; |
7413 | int get_off = ring_data->rx_curr_get_info.offset; | |
7414 | int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2); | |
7415 | int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2); | |
7416 | unsigned char *buff = skb_push(skb, buf0_len); | |
7417 | ||
1ee6dd77 | 7418 | struct buffAdd *ba = &ring_data->ba[get_block][get_off]; |
da6971d8 | 7419 | memcpy(buff, ba->ba_0, buf0_len); |
6d517a27 | 7420 | skb_put(skb, buf2_len); |
da6971d8 | 7421 | } |
20346722 | 7422 | |
d44570e4 JP |
7423 | if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && |
7424 | ((!ring_data->lro) || | |
7425 | (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) && | |
b437a8cc | 7426 | (dev->features & NETIF_F_RXCSUM)) { |
20346722 | 7427 | l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1); |
1da177e4 LT |
7428 | l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1); |
7429 | if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) { | |
20346722 | 7430 | /* |
1da177e4 LT |
7431 | * NIC verifies if the Checksum of the received |
7432 | * frame is Ok or not and accordingly returns | |
7433 | * a flag in the RxD. | |
7434 | */ | |
7435 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
0425b46a | 7436 | if (ring_data->lro) { |
06f0c139 | 7437 | u32 tcp_len = 0; |
7d3d0439 RA |
7438 | u8 *tcp; |
7439 | int ret = 0; | |
7440 | ||
0425b46a | 7441 | ret = s2io_club_tcp_session(ring_data, |
d44570e4 JP |
7442 | skb->data, &tcp, |
7443 | &tcp_len, &lro, | |
7444 | rxdp, sp); | |
7d3d0439 | 7445 | switch (ret) { |
d44570e4 JP |
7446 | case 3: /* Begin anew */ |
7447 | lro->parent = skb; | |
7448 | goto aggregate; | |
7449 | case 1: /* Aggregate */ | |
7450 | lro_append_pkt(sp, lro, skb, tcp_len); | |
7451 | goto aggregate; | |
7452 | case 4: /* Flush session */ | |
7453 | lro_append_pkt(sp, lro, skb, tcp_len); | |
7454 | queue_rx_frame(lro->parent, | |
7455 | lro->vlan_tag); | |
7456 | clear_lro_session(lro); | |
ffb5df6c | 7457 | swstats->flush_max_pkts++; |
d44570e4 JP |
7458 | goto aggregate; |
7459 | case 2: /* Flush both */ | |
7460 | lro->parent->data_len = lro->frags_len; | |
ffb5df6c | 7461 | swstats->sending_both++; |
d44570e4 JP |
7462 | queue_rx_frame(lro->parent, |
7463 | lro->vlan_tag); | |
7464 | clear_lro_session(lro); | |
7465 | goto send_up; | |
7466 | case 0: /* sessions exceeded */ | |
7467 | case -1: /* non-TCP or not L2 aggregatable */ | |
7468 | case 5: /* | |
7469 | * First pkt in session not | |
7470 | * L3/L4 aggregatable | |
7471 | */ | |
7472 | break; | |
7473 | default: | |
7474 | DBG_PRINT(ERR_DBG, | |
7475 | "%s: Samadhana!!\n", | |
7476 | __func__); | |
7477 | BUG(); | |
7d3d0439 RA |
7478 | } |
7479 | } | |
1da177e4 | 7480 | } else { |
20346722 | 7481 | /* |
7482 | * Packet with erroneous checksum, let the | |
1da177e4 LT |
7483 | * upper layers deal with it. |
7484 | */ | |
bc8acf2c | 7485 | skb_checksum_none_assert(skb); |
1da177e4 | 7486 | } |
cdb5bf02 | 7487 | } else |
bc8acf2c | 7488 | skb_checksum_none_assert(skb); |
cdb5bf02 | 7489 | |
ffb5df6c | 7490 | swstats->mem_freed += skb->truesize; |
7d3d0439 | 7491 | send_up: |
0c8dfc83 | 7492 | skb_record_rx_queue(skb, ring_no); |
cdb5bf02 | 7493 | queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2)); |
7d3d0439 | 7494 | aggregate: |
0425b46a | 7495 | sp->mac_control.rings[ring_no].rx_bufs_left -= 1; |
1da177e4 LT |
7496 | return SUCCESS; |
7497 | } | |
7498 | ||
7499 | /** | |
7500 | * s2io_link - stops/starts the Tx queue. | |
7501 | * @sp : private member of the device structure, which is a pointer to the | |
7502 | * s2io_nic structure. | |
7503 | * @link : inidicates whether link is UP/DOWN. | |
7504 | * Description: | |
7505 | * This function stops/starts the Tx queue depending on whether the link | |
20346722 | 7506 | * status of the NIC is is down or up. This is called by the Alarm |
7507 | * interrupt handler whenever a link change interrupt comes up. | |
1da177e4 LT |
7508 | * Return value: |
7509 | * void. | |
7510 | */ | |
7511 | ||
d44570e4 | 7512 | static void s2io_link(struct s2io_nic *sp, int link) |
1da177e4 | 7513 | { |
d44570e4 | 7514 | struct net_device *dev = (struct net_device *)sp->dev; |
ffb5df6c | 7515 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
1da177e4 LT |
7516 | |
7517 | if (link != sp->last_link_state) { | |
b7c5678f | 7518 | init_tti(sp, link); |
1da177e4 LT |
7519 | if (link == LINK_DOWN) { |
7520 | DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name); | |
3a3d5756 | 7521 | s2io_stop_all_tx_queue(sp); |
1da177e4 | 7522 | netif_carrier_off(dev); |
ffb5df6c JP |
7523 | if (swstats->link_up_cnt) |
7524 | swstats->link_up_time = | |
7525 | jiffies - sp->start_time; | |
7526 | swstats->link_down_cnt++; | |
1da177e4 LT |
7527 | } else { |
7528 | DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name); | |
ffb5df6c JP |
7529 | if (swstats->link_down_cnt) |
7530 | swstats->link_down_time = | |
d44570e4 | 7531 | jiffies - sp->start_time; |
ffb5df6c | 7532 | swstats->link_up_cnt++; |
1da177e4 | 7533 | netif_carrier_on(dev); |
3a3d5756 | 7534 | s2io_wake_all_tx_queue(sp); |
1da177e4 LT |
7535 | } |
7536 | } | |
7537 | sp->last_link_state = link; | |
491976b2 | 7538 | sp->start_time = jiffies; |
1da177e4 LT |
7539 | } |
7540 | ||
20346722 | 7541 | /** |
7542 | * s2io_init_pci -Initialization of PCI and PCI-X configuration registers . | |
7543 | * @sp : private member of the device structure, which is a pointer to the | |
1da177e4 LT |
7544 | * s2io_nic structure. |
7545 | * Description: | |
7546 | * This function initializes a few of the PCI and PCI-X configuration registers | |
7547 | * with recommended values. | |
7548 | * Return value: | |
7549 | * void | |
7550 | */ | |
7551 | ||
d44570e4 | 7552 | static void s2io_init_pci(struct s2io_nic *sp) |
1da177e4 | 7553 | { |
20346722 | 7554 | u16 pci_cmd = 0, pcix_cmd = 0; |
1da177e4 LT |
7555 | |
7556 | /* Enable Data Parity Error Recovery in PCI-X command register. */ | |
7557 | pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, | |
20346722 | 7558 | &(pcix_cmd)); |
1da177e4 | 7559 | pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, |
20346722 | 7560 | (pcix_cmd | 1)); |
1da177e4 | 7561 | pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, |
20346722 | 7562 | &(pcix_cmd)); |
1da177e4 LT |
7563 | |
7564 | /* Set the PErr Response bit in PCI command register. */ | |
7565 | pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); | |
7566 | pci_write_config_word(sp->pdev, PCI_COMMAND, | |
7567 | (pci_cmd | PCI_COMMAND_PARITY)); | |
7568 | pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd); | |
1da177e4 LT |
7569 | } |
7570 | ||
3a3d5756 | 7571 | static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type, |
d44570e4 | 7572 | u8 *dev_multiq) |
9dc737a7 | 7573 | { |
1853e2e1 JM |
7574 | int i; |
7575 | ||
d44570e4 | 7576 | if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) { |
9e39f7c5 | 7577 | DBG_PRINT(ERR_DBG, "Requested number of tx fifos " |
d44570e4 | 7578 | "(%d) not supported\n", tx_fifo_num); |
6cfc482b SH |
7579 | |
7580 | if (tx_fifo_num < 1) | |
7581 | tx_fifo_num = 1; | |
7582 | else | |
7583 | tx_fifo_num = MAX_TX_FIFOS; | |
7584 | ||
9e39f7c5 | 7585 | DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num); |
9dc737a7 | 7586 | } |
2fda096d | 7587 | |
6cfc482b | 7588 | if (multiq) |
3a3d5756 | 7589 | *dev_multiq = multiq; |
6cfc482b SH |
7590 | |
7591 | if (tx_steering_type && (1 == tx_fifo_num)) { | |
7592 | if (tx_steering_type != TX_DEFAULT_STEERING) | |
7593 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 | 7594 | "Tx steering is not supported with " |
d44570e4 | 7595 | "one fifo. Disabling Tx steering.\n"); |
6cfc482b SH |
7596 | tx_steering_type = NO_STEERING; |
7597 | } | |
7598 | ||
7599 | if ((tx_steering_type < NO_STEERING) || | |
d44570e4 JP |
7600 | (tx_steering_type > TX_DEFAULT_STEERING)) { |
7601 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 JP |
7602 | "Requested transmit steering not supported\n"); |
7603 | DBG_PRINT(ERR_DBG, "Disabling transmit steering\n"); | |
6cfc482b | 7604 | tx_steering_type = NO_STEERING; |
3a3d5756 SH |
7605 | } |
7606 | ||
0425b46a | 7607 | if (rx_ring_num > MAX_RX_RINGS) { |
d44570e4 | 7608 | DBG_PRINT(ERR_DBG, |
9e39f7c5 JP |
7609 | "Requested number of rx rings not supported\n"); |
7610 | DBG_PRINT(ERR_DBG, "Default to %d rx rings\n", | |
d44570e4 | 7611 | MAX_RX_RINGS); |
0425b46a | 7612 | rx_ring_num = MAX_RX_RINGS; |
9dc737a7 | 7613 | } |
0425b46a | 7614 | |
eccb8628 | 7615 | if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) { |
9e39f7c5 | 7616 | DBG_PRINT(ERR_DBG, "Wrong intr_type requested. " |
9dc737a7 AR |
7617 | "Defaulting to INTA\n"); |
7618 | *dev_intr_type = INTA; | |
7619 | } | |
596c5c97 | 7620 | |
9dc737a7 | 7621 | if ((*dev_intr_type == MSI_X) && |
d44570e4 JP |
7622 | ((pdev->device != PCI_DEVICE_ID_HERC_WIN) && |
7623 | (pdev->device != PCI_DEVICE_ID_HERC_UNI))) { | |
9e39f7c5 | 7624 | DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. " |
d44570e4 | 7625 | "Defaulting to INTA\n"); |
9dc737a7 AR |
7626 | *dev_intr_type = INTA; |
7627 | } | |
fb6a825b | 7628 | |
6d517a27 | 7629 | if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) { |
9e39f7c5 JP |
7630 | DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n"); |
7631 | DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n"); | |
6d517a27 | 7632 | rx_ring_mode = 1; |
9dc737a7 | 7633 | } |
1853e2e1 JM |
7634 | |
7635 | for (i = 0; i < MAX_RX_RINGS; i++) | |
7636 | if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) { | |
7637 | DBG_PRINT(ERR_DBG, "Requested rx ring size not " | |
7638 | "supported\nDefaulting to %d\n", | |
7639 | MAX_RX_BLOCKS_PER_RING); | |
7640 | rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING; | |
7641 | } | |
7642 | ||
9dc737a7 AR |
7643 | return SUCCESS; |
7644 | } | |
7645 | ||
9fc93a41 SS |
7646 | /** |
7647 | * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS | |
7648 | * or Traffic class respectively. | |
b7c5678f | 7649 | * @nic: device private variable |
9fc93a41 SS |
7650 | * Description: The function configures the receive steering to |
7651 | * desired receive ring. | |
7652 | * Return Value: SUCCESS on success and | |
7653 | * '-1' on failure (endian settings incorrect). | |
7654 | */ | |
7655 | static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring) | |
7656 | { | |
7657 | struct XENA_dev_config __iomem *bar0 = nic->bar0; | |
7658 | register u64 val64 = 0; | |
7659 | ||
7660 | if (ds_codepoint > 63) | |
7661 | return FAILURE; | |
7662 | ||
7663 | val64 = RTS_DS_MEM_DATA(ring); | |
7664 | writeq(val64, &bar0->rts_ds_mem_data); | |
7665 | ||
7666 | val64 = RTS_DS_MEM_CTRL_WE | | |
7667 | RTS_DS_MEM_CTRL_STROBE_NEW_CMD | | |
7668 | RTS_DS_MEM_CTRL_OFFSET(ds_codepoint); | |
7669 | ||
7670 | writeq(val64, &bar0->rts_ds_mem_ctrl); | |
7671 | ||
7672 | return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, | |
d44570e4 JP |
7673 | RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED, |
7674 | S2IO_BIT_RESET); | |
9fc93a41 SS |
7675 | } |
7676 | ||
04025095 SH |
7677 | static const struct net_device_ops s2io_netdev_ops = { |
7678 | .ndo_open = s2io_open, | |
7679 | .ndo_stop = s2io_close, | |
7680 | .ndo_get_stats = s2io_get_stats, | |
7681 | .ndo_start_xmit = s2io_xmit, | |
7682 | .ndo_validate_addr = eth_validate_addr, | |
afc4b13d | 7683 | .ndo_set_rx_mode = s2io_set_multicast, |
04025095 SH |
7684 | .ndo_do_ioctl = s2io_ioctl, |
7685 | .ndo_set_mac_address = s2io_set_mac_addr, | |
7686 | .ndo_change_mtu = s2io_change_mtu, | |
b437a8cc | 7687 | .ndo_set_features = s2io_set_features, |
04025095 SH |
7688 | .ndo_tx_timeout = s2io_tx_watchdog, |
7689 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7690 | .ndo_poll_controller = s2io_netpoll, | |
7691 | #endif | |
7692 | }; | |
7693 | ||
1da177e4 | 7694 | /** |
20346722 | 7695 | * s2io_init_nic - Initialization of the adapter . |
1da177e4 LT |
7696 | * @pdev : structure containing the PCI related information of the device. |
7697 | * @pre: List of PCI devices supported by the driver listed in s2io_tbl. | |
7698 | * Description: | |
7699 | * The function initializes an adapter identified by the pci_dec structure. | |
20346722 | 7700 | * All OS related initialization including memory and device structure and |
7701 | * initlaization of the device private variable is done. Also the swapper | |
7702 | * control register is initialized to enable read and write into the I/O | |
1da177e4 LT |
7703 | * registers of the device. |
7704 | * Return value: | |
7705 | * returns 0 on success and negative on failure. | |
7706 | */ | |
7707 | ||
7708 | static int __devinit | |
7709 | s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre) | |
7710 | { | |
1ee6dd77 | 7711 | struct s2io_nic *sp; |
1da177e4 | 7712 | struct net_device *dev; |
1da177e4 | 7713 | int i, j, ret; |
f957bcf0 | 7714 | int dma_flag = false; |
1da177e4 LT |
7715 | u32 mac_up, mac_down; |
7716 | u64 val64 = 0, tmp64 = 0; | |
1ee6dd77 | 7717 | struct XENA_dev_config __iomem *bar0 = NULL; |
1da177e4 | 7718 | u16 subid; |
1da177e4 | 7719 | struct config_param *config; |
ffb5df6c | 7720 | struct mac_info *mac_control; |
541ae68f | 7721 | int mode; |
cc6e7c44 | 7722 | u8 dev_intr_type = intr_type; |
3a3d5756 | 7723 | u8 dev_multiq = 0; |
1da177e4 | 7724 | |
3a3d5756 SH |
7725 | ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq); |
7726 | if (ret) | |
9dc737a7 | 7727 | return ret; |
1da177e4 | 7728 | |
d44570e4 JP |
7729 | ret = pci_enable_device(pdev); |
7730 | if (ret) { | |
1da177e4 | 7731 | DBG_PRINT(ERR_DBG, |
9e39f7c5 | 7732 | "%s: pci_enable_device failed\n", __func__); |
1da177e4 LT |
7733 | return ret; |
7734 | } | |
7735 | ||
6a35528a | 7736 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { |
9e39f7c5 | 7737 | DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__); |
f957bcf0 | 7738 | dma_flag = true; |
d44570e4 | 7739 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { |
1da177e4 | 7740 | DBG_PRINT(ERR_DBG, |
d44570e4 JP |
7741 | "Unable to obtain 64bit DMA " |
7742 | "for consistent allocations\n"); | |
1da177e4 LT |
7743 | pci_disable_device(pdev); |
7744 | return -ENOMEM; | |
7745 | } | |
284901a9 | 7746 | } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { |
9e39f7c5 | 7747 | DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__); |
1da177e4 LT |
7748 | } else { |
7749 | pci_disable_device(pdev); | |
7750 | return -ENOMEM; | |
7751 | } | |
d44570e4 JP |
7752 | ret = pci_request_regions(pdev, s2io_driver_name); |
7753 | if (ret) { | |
9e39f7c5 | 7754 | DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n", |
d44570e4 | 7755 | __func__, ret); |
eccb8628 VP |
7756 | pci_disable_device(pdev); |
7757 | return -ENODEV; | |
1da177e4 | 7758 | } |
3a3d5756 | 7759 | if (dev_multiq) |
6cfc482b | 7760 | dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num); |
3a3d5756 | 7761 | else |
b19fa1fa | 7762 | dev = alloc_etherdev(sizeof(struct s2io_nic)); |
1da177e4 LT |
7763 | if (dev == NULL) { |
7764 | DBG_PRINT(ERR_DBG, "Device allocation failed\n"); | |
7765 | pci_disable_device(pdev); | |
7766 | pci_release_regions(pdev); | |
7767 | return -ENODEV; | |
7768 | } | |
7769 | ||
7770 | pci_set_master(pdev); | |
7771 | pci_set_drvdata(pdev, dev); | |
1da177e4 LT |
7772 | SET_NETDEV_DEV(dev, &pdev->dev); |
7773 | ||
7774 | /* Private member variable initialized to s2io NIC structure */ | |
4cf1653a | 7775 | sp = netdev_priv(dev); |
1da177e4 LT |
7776 | sp->dev = dev; |
7777 | sp->pdev = pdev; | |
1da177e4 | 7778 | sp->high_dma_flag = dma_flag; |
f957bcf0 | 7779 | sp->device_enabled_once = false; |
da6971d8 AR |
7780 | if (rx_ring_mode == 1) |
7781 | sp->rxd_mode = RXD_MODE_1; | |
7782 | if (rx_ring_mode == 2) | |
7783 | sp->rxd_mode = RXD_MODE_3B; | |
da6971d8 | 7784 | |
eaae7f72 | 7785 | sp->config.intr_type = dev_intr_type; |
1da177e4 | 7786 | |
541ae68f | 7787 | if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) || |
d44570e4 | 7788 | (pdev->device == PCI_DEVICE_ID_HERC_UNI)) |
541ae68f | 7789 | sp->device_type = XFRAME_II_DEVICE; |
7790 | else | |
7791 | sp->device_type = XFRAME_I_DEVICE; | |
7792 | ||
6aa20a22 | 7793 | |
1da177e4 LT |
7794 | /* Initialize some PCI/PCI-X fields of the NIC. */ |
7795 | s2io_init_pci(sp); | |
7796 | ||
20346722 | 7797 | /* |
1da177e4 | 7798 | * Setting the device configuration parameters. |
20346722 | 7799 | * Most of these parameters can be specified by the user during |
7800 | * module insertion as they are module loadable parameters. If | |
7801 | * these parameters are not not specified during load time, they | |
1da177e4 LT |
7802 | * are initialized with default values. |
7803 | */ | |
1da177e4 | 7804 | config = &sp->config; |
ffb5df6c | 7805 | mac_control = &sp->mac_control; |
1da177e4 | 7806 | |
596c5c97 | 7807 | config->napi = napi; |
6cfc482b | 7808 | config->tx_steering_type = tx_steering_type; |
596c5c97 | 7809 | |
1da177e4 | 7810 | /* Tx side parameters. */ |
6cfc482b SH |
7811 | if (config->tx_steering_type == TX_PRIORITY_STEERING) |
7812 | config->tx_fifo_num = MAX_TX_FIFOS; | |
7813 | else | |
7814 | config->tx_fifo_num = tx_fifo_num; | |
7815 | ||
7816 | /* Initialize the fifos used for tx steering */ | |
7817 | if (config->tx_fifo_num < 5) { | |
d44570e4 JP |
7818 | if (config->tx_fifo_num == 1) |
7819 | sp->total_tcp_fifos = 1; | |
7820 | else | |
7821 | sp->total_tcp_fifos = config->tx_fifo_num - 1; | |
7822 | sp->udp_fifo_idx = config->tx_fifo_num - 1; | |
7823 | sp->total_udp_fifos = 1; | |
7824 | sp->other_fifo_idx = sp->total_tcp_fifos - 1; | |
6cfc482b SH |
7825 | } else { |
7826 | sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM - | |
d44570e4 | 7827 | FIFO_OTHER_MAX_NUM); |
6cfc482b SH |
7828 | sp->udp_fifo_idx = sp->total_tcp_fifos; |
7829 | sp->total_udp_fifos = FIFO_UDP_MAX_NUM; | |
7830 | sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM; | |
7831 | } | |
7832 | ||
3a3d5756 | 7833 | config->multiq = dev_multiq; |
6cfc482b | 7834 | for (i = 0; i < config->tx_fifo_num; i++) { |
13d866a9 JP |
7835 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
7836 | ||
7837 | tx_cfg->fifo_len = tx_fifo_len[i]; | |
7838 | tx_cfg->fifo_priority = i; | |
1da177e4 LT |
7839 | } |
7840 | ||
20346722 | 7841 | /* mapping the QoS priority to the configured fifos */ |
7842 | for (i = 0; i < MAX_TX_FIFOS; i++) | |
3a3d5756 | 7843 | config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i]; |
20346722 | 7844 | |
6cfc482b SH |
7845 | /* map the hashing selector table to the configured fifos */ |
7846 | for (i = 0; i < config->tx_fifo_num; i++) | |
7847 | sp->fifo_selector[i] = fifo_selector[i]; | |
7848 | ||
7849 | ||
1da177e4 LT |
7850 | config->tx_intr_type = TXD_INT_TYPE_UTILZ; |
7851 | for (i = 0; i < config->tx_fifo_num; i++) { | |
13d866a9 JP |
7852 | struct tx_fifo_config *tx_cfg = &config->tx_cfg[i]; |
7853 | ||
7854 | tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER); | |
7855 | if (tx_cfg->fifo_len < 65) { | |
1da177e4 LT |
7856 | config->tx_intr_type = TXD_INT_TYPE_PER_LIST; |
7857 | break; | |
7858 | } | |
7859 | } | |
fed5eccd AR |
7860 | /* + 2 because one Txd for skb->data and one Txd for UFO */ |
7861 | config->max_txds = MAX_SKB_FRAGS + 2; | |
1da177e4 LT |
7862 | |
7863 | /* Rx side parameters. */ | |
1da177e4 | 7864 | config->rx_ring_num = rx_ring_num; |
0425b46a | 7865 | for (i = 0; i < config->rx_ring_num; i++) { |
13d866a9 JP |
7866 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
7867 | struct ring_info *ring = &mac_control->rings[i]; | |
7868 | ||
7869 | rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1); | |
7870 | rx_cfg->ring_priority = i; | |
7871 | ring->rx_bufs_left = 0; | |
7872 | ring->rxd_mode = sp->rxd_mode; | |
7873 | ring->rxd_count = rxd_count[sp->rxd_mode]; | |
7874 | ring->pdev = sp->pdev; | |
7875 | ring->dev = sp->dev; | |
1da177e4 LT |
7876 | } |
7877 | ||
7878 | for (i = 0; i < rx_ring_num; i++) { | |
13d866a9 JP |
7879 | struct rx_ring_config *rx_cfg = &config->rx_cfg[i]; |
7880 | ||
7881 | rx_cfg->ring_org = RING_ORG_BUFF1; | |
7882 | rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER); | |
1da177e4 LT |
7883 | } |
7884 | ||
7885 | /* Setting Mac Control parameters */ | |
7886 | mac_control->rmac_pause_time = rmac_pause_time; | |
7887 | mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3; | |
7888 | mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7; | |
7889 | ||
7890 | ||
1da177e4 LT |
7891 | /* initialize the shared memory used by the NIC and the host */ |
7892 | if (init_shared_mem(sp)) { | |
d44570e4 | 7893 | DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name); |
1da177e4 LT |
7894 | ret = -ENOMEM; |
7895 | goto mem_alloc_failed; | |
7896 | } | |
7897 | ||
275f165f | 7898 | sp->bar0 = pci_ioremap_bar(pdev, 0); |
1da177e4 | 7899 | if (!sp->bar0) { |
19a60522 | 7900 | DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n", |
1da177e4 LT |
7901 | dev->name); |
7902 | ret = -ENOMEM; | |
7903 | goto bar0_remap_failed; | |
7904 | } | |
7905 | ||
275f165f | 7906 | sp->bar1 = pci_ioremap_bar(pdev, 2); |
1da177e4 | 7907 | if (!sp->bar1) { |
19a60522 | 7908 | DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n", |
1da177e4 LT |
7909 | dev->name); |
7910 | ret = -ENOMEM; | |
7911 | goto bar1_remap_failed; | |
7912 | } | |
7913 | ||
7914 | dev->irq = pdev->irq; | |
d44570e4 | 7915 | dev->base_addr = (unsigned long)sp->bar0; |
1da177e4 LT |
7916 | |
7917 | /* Initializing the BAR1 address as the start of the FIFO pointer. */ | |
7918 | for (j = 0; j < MAX_TX_FIFOS; j++) { | |
43d620c8 | 7919 | mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000); |
1da177e4 LT |
7920 | } |
7921 | ||
7922 | /* Driver entry points */ | |
04025095 | 7923 | dev->netdev_ops = &s2io_netdev_ops; |
1da177e4 | 7924 | SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); |
b437a8cc MM |
7925 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | |
7926 | NETIF_F_TSO | NETIF_F_TSO6 | | |
7927 | NETIF_F_RXCSUM | NETIF_F_LRO; | |
7928 | dev->features |= dev->hw_features | | |
7929 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
7930 | if (sp->device_type & XFRAME_II_DEVICE) { | |
7931 | dev->hw_features |= NETIF_F_UFO; | |
7932 | if (ufo) | |
7933 | dev->features |= NETIF_F_UFO; | |
7934 | } | |
f957bcf0 | 7935 | if (sp->high_dma_flag == true) |
1da177e4 | 7936 | dev->features |= NETIF_F_HIGHDMA; |
1da177e4 | 7937 | dev->watchdog_timeo = WATCH_DOG_TIMEOUT; |
c4028958 DH |
7938 | INIT_WORK(&sp->rst_timer_task, s2io_restart_nic); |
7939 | INIT_WORK(&sp->set_link_task, s2io_set_link); | |
1da177e4 | 7940 | |
e960fc5c | 7941 | pci_save_state(sp->pdev); |
1da177e4 LT |
7942 | |
7943 | /* Setting swapper control on the NIC, for proper reset operation */ | |
7944 | if (s2io_set_swapper(sp)) { | |
9e39f7c5 | 7945 | DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n", |
1da177e4 LT |
7946 | dev->name); |
7947 | ret = -EAGAIN; | |
7948 | goto set_swap_failed; | |
7949 | } | |
7950 | ||
541ae68f | 7951 | /* Verify if the Herc works on the slot its placed into */ |
7952 | if (sp->device_type & XFRAME_II_DEVICE) { | |
7953 | mode = s2io_verify_pci_mode(sp); | |
7954 | if (mode < 0) { | |
9e39f7c5 JP |
7955 | DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n", |
7956 | __func__); | |
541ae68f | 7957 | ret = -EBADSLT; |
7958 | goto set_swap_failed; | |
7959 | } | |
7960 | } | |
7961 | ||
f61e0a35 SH |
7962 | if (sp->config.intr_type == MSI_X) { |
7963 | sp->num_entries = config->rx_ring_num + 1; | |
7964 | ret = s2io_enable_msi_x(sp); | |
7965 | ||
7966 | if (!ret) { | |
7967 | ret = s2io_test_msi(sp); | |
7968 | /* rollback MSI-X, will re-enable during add_isr() */ | |
7969 | remove_msix_isr(sp); | |
7970 | } | |
7971 | if (ret) { | |
7972 | ||
7973 | DBG_PRINT(ERR_DBG, | |
9e39f7c5 | 7974 | "MSI-X requested but failed to enable\n"); |
f61e0a35 SH |
7975 | sp->config.intr_type = INTA; |
7976 | } | |
7977 | } | |
7978 | ||
7979 | if (config->intr_type == MSI_X) { | |
13d866a9 JP |
7980 | for (i = 0; i < config->rx_ring_num ; i++) { |
7981 | struct ring_info *ring = &mac_control->rings[i]; | |
7982 | ||
7983 | netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64); | |
7984 | } | |
f61e0a35 SH |
7985 | } else { |
7986 | netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64); | |
7987 | } | |
7988 | ||
541ae68f | 7989 | /* Not needed for Herc */ |
7990 | if (sp->device_type & XFRAME_I_DEVICE) { | |
7991 | /* | |
7992 | * Fix for all "FFs" MAC address problems observed on | |
7993 | * Alpha platforms | |
7994 | */ | |
7995 | fix_mac_address(sp); | |
7996 | s2io_reset(sp); | |
7997 | } | |
1da177e4 LT |
7998 | |
7999 | /* | |
1da177e4 LT |
8000 | * MAC address initialization. |
8001 | * For now only one mac address will be read and used. | |
8002 | */ | |
8003 | bar0 = sp->bar0; | |
8004 | val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD | | |
d44570e4 | 8005 | RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET); |
1da177e4 | 8006 | writeq(val64, &bar0->rmac_addr_cmd_mem); |
c92ca04b | 8007 | wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, |
d44570e4 JP |
8008 | RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, |
8009 | S2IO_BIT_RESET); | |
1da177e4 | 8010 | tmp64 = readq(&bar0->rmac_addr_data0_mem); |
d44570e4 | 8011 | mac_down = (u32)tmp64; |
1da177e4 LT |
8012 | mac_up = (u32) (tmp64 >> 32); |
8013 | ||
1da177e4 LT |
8014 | sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up); |
8015 | sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8); | |
8016 | sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16); | |
8017 | sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24); | |
8018 | sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16); | |
8019 | sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24); | |
8020 | ||
1da177e4 LT |
8021 | /* Set the factory defined MAC address initially */ |
8022 | dev->addr_len = ETH_ALEN; | |
8023 | memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN); | |
2fd37688 | 8024 | memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN); |
1da177e4 | 8025 | |
faa4f796 SH |
8026 | /* initialize number of multicast & unicast MAC entries variables */ |
8027 | if (sp->device_type == XFRAME_I_DEVICE) { | |
8028 | config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES; | |
8029 | config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES; | |
8030 | config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET; | |
8031 | } else if (sp->device_type == XFRAME_II_DEVICE) { | |
8032 | config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES; | |
8033 | config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES; | |
8034 | config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET; | |
8035 | } | |
8036 | ||
8037 | /* store mac addresses from CAM to s2io_nic structure */ | |
8038 | do_s2io_store_unicast_mc(sp); | |
8039 | ||
f61e0a35 SH |
8040 | /* Configure MSIX vector for number of rings configured plus one */ |
8041 | if ((sp->device_type == XFRAME_II_DEVICE) && | |
d44570e4 | 8042 | (config->intr_type == MSI_X)) |
f61e0a35 SH |
8043 | sp->num_entries = config->rx_ring_num + 1; |
8044 | ||
d44570e4 | 8045 | /* Store the values of the MSIX table in the s2io_nic structure */ |
c77dd43e | 8046 | store_xmsi_data(sp); |
b41477f3 AR |
8047 | /* reset Nic and bring it to known state */ |
8048 | s2io_reset(sp); | |
8049 | ||
1da177e4 | 8050 | /* |
99993af6 | 8051 | * Initialize link state flags |
541ae68f | 8052 | * and the card state parameter |
1da177e4 | 8053 | */ |
92b84437 | 8054 | sp->state = 0; |
1da177e4 | 8055 | |
1da177e4 | 8056 | /* Initialize spinlocks */ |
13d866a9 JP |
8057 | for (i = 0; i < sp->config.tx_fifo_num; i++) { |
8058 | struct fifo_info *fifo = &mac_control->fifos[i]; | |
8059 | ||
8060 | spin_lock_init(&fifo->tx_lock); | |
8061 | } | |
db874e65 | 8062 | |
20346722 | 8063 | /* |
8064 | * SXE-002: Configure link and activity LED to init state | |
8065 | * on driver load. | |
1da177e4 LT |
8066 | */ |
8067 | subid = sp->pdev->subsystem_device; | |
8068 | if ((subid & 0xFF) >= 0x07) { | |
8069 | val64 = readq(&bar0->gpio_control); | |
8070 | val64 |= 0x0000800000000000ULL; | |
8071 | writeq(val64, &bar0->gpio_control); | |
8072 | val64 = 0x0411040400000000ULL; | |
d44570e4 | 8073 | writeq(val64, (void __iomem *)bar0 + 0x2700); |
1da177e4 LT |
8074 | val64 = readq(&bar0->gpio_control); |
8075 | } | |
8076 | ||
8077 | sp->rx_csum = 1; /* Rx chksum verify enabled by default */ | |
8078 | ||
8079 | if (register_netdev(dev)) { | |
8080 | DBG_PRINT(ERR_DBG, "Device registration failed\n"); | |
8081 | ret = -ENODEV; | |
8082 | goto register_failed; | |
8083 | } | |
9dc737a7 | 8084 | s2io_vpd_read(sp); |
926bd900 | 8085 | DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n"); |
d44570e4 | 8086 | DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name, |
44c10138 | 8087 | sp->product_name, pdev->revision); |
b41477f3 AR |
8088 | DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name, |
8089 | s2io_driver_version); | |
9e39f7c5 JP |
8090 | DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr); |
8091 | DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num); | |
9dc737a7 | 8092 | if (sp->device_type & XFRAME_II_DEVICE) { |
0b1f7ebe | 8093 | mode = s2io_print_pci_mode(sp); |
541ae68f | 8094 | if (mode < 0) { |
541ae68f | 8095 | ret = -EBADSLT; |
9dc737a7 | 8096 | unregister_netdev(dev); |
541ae68f | 8097 | goto set_swap_failed; |
8098 | } | |
541ae68f | 8099 | } |
d44570e4 JP |
8100 | switch (sp->rxd_mode) { |
8101 | case RXD_MODE_1: | |
8102 | DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n", | |
8103 | dev->name); | |
8104 | break; | |
8105 | case RXD_MODE_3B: | |
8106 | DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n", | |
8107 | dev->name); | |
8108 | break; | |
9dc737a7 | 8109 | } |
db874e65 | 8110 | |
f61e0a35 SH |
8111 | switch (sp->config.napi) { |
8112 | case 0: | |
8113 | DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name); | |
8114 | break; | |
8115 | case 1: | |
db874e65 | 8116 | DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name); |
f61e0a35 SH |
8117 | break; |
8118 | } | |
3a3d5756 SH |
8119 | |
8120 | DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name, | |
d44570e4 | 8121 | sp->config.tx_fifo_num); |
3a3d5756 | 8122 | |
0425b46a SH |
8123 | DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name, |
8124 | sp->config.rx_ring_num); | |
8125 | ||
d44570e4 JP |
8126 | switch (sp->config.intr_type) { |
8127 | case INTA: | |
8128 | DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name); | |
8129 | break; | |
8130 | case MSI_X: | |
8131 | DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name); | |
8132 | break; | |
9dc737a7 | 8133 | } |
3a3d5756 | 8134 | if (sp->config.multiq) { |
13d866a9 JP |
8135 | for (i = 0; i < sp->config.tx_fifo_num; i++) { |
8136 | struct fifo_info *fifo = &mac_control->fifos[i]; | |
8137 | ||
8138 | fifo->multiq = config->multiq; | |
8139 | } | |
3a3d5756 | 8140 | DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n", |
d44570e4 | 8141 | dev->name); |
3a3d5756 SH |
8142 | } else |
8143 | DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n", | |
d44570e4 | 8144 | dev->name); |
3a3d5756 | 8145 | |
6cfc482b SH |
8146 | switch (sp->config.tx_steering_type) { |
8147 | case NO_STEERING: | |
d44570e4 JP |
8148 | DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n", |
8149 | dev->name); | |
8150 | break; | |
6cfc482b | 8151 | case TX_PRIORITY_STEERING: |
d44570e4 JP |
8152 | DBG_PRINT(ERR_DBG, |
8153 | "%s: Priority steering enabled for transmit\n", | |
8154 | dev->name); | |
6cfc482b SH |
8155 | break; |
8156 | case TX_DEFAULT_STEERING: | |
d44570e4 JP |
8157 | DBG_PRINT(ERR_DBG, |
8158 | "%s: Default steering enabled for transmit\n", | |
8159 | dev->name); | |
6cfc482b SH |
8160 | } |
8161 | ||
f0c54ace AW |
8162 | DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n", |
8163 | dev->name); | |
db874e65 | 8164 | if (ufo) |
d44570e4 JP |
8165 | DBG_PRINT(ERR_DBG, |
8166 | "%s: UDP Fragmentation Offload(UFO) enabled\n", | |
8167 | dev->name); | |
7ba013ac | 8168 | /* Initialize device name */ |
9dc737a7 | 8169 | sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name); |
7ba013ac | 8170 | |
cd0fce03 BL |
8171 | if (vlan_tag_strip) |
8172 | sp->vlan_strip_flag = 1; | |
8173 | else | |
8174 | sp->vlan_strip_flag = 0; | |
8175 | ||
20346722 | 8176 | /* |
8177 | * Make Link state as off at this point, when the Link change | |
8178 | * interrupt comes the state will be automatically changed to | |
1da177e4 LT |
8179 | * the right state. |
8180 | */ | |
8181 | netif_carrier_off(dev); | |
1da177e4 LT |
8182 | |
8183 | return 0; | |
8184 | ||
d44570e4 JP |
8185 | register_failed: |
8186 | set_swap_failed: | |
1da177e4 | 8187 | iounmap(sp->bar1); |
d44570e4 | 8188 | bar1_remap_failed: |
1da177e4 | 8189 | iounmap(sp->bar0); |
d44570e4 JP |
8190 | bar0_remap_failed: |
8191 | mem_alloc_failed: | |
1da177e4 LT |
8192 | free_shared_mem(sp); |
8193 | pci_disable_device(pdev); | |
eccb8628 | 8194 | pci_release_regions(pdev); |
1da177e4 LT |
8195 | pci_set_drvdata(pdev, NULL); |
8196 | free_netdev(dev); | |
8197 | ||
8198 | return ret; | |
8199 | } | |
8200 | ||
8201 | /** | |
20346722 | 8202 | * s2io_rem_nic - Free the PCI device |
1da177e4 | 8203 | * @pdev: structure containing the PCI related information of the device. |
20346722 | 8204 | * Description: This function is called by the Pci subsystem to release a |
1da177e4 | 8205 | * PCI device and free up all resource held up by the device. This could |
20346722 | 8206 | * be in response to a Hot plug event or when the driver is to be removed |
1da177e4 LT |
8207 | * from memory. |
8208 | */ | |
8209 | ||
8210 | static void __devexit s2io_rem_nic(struct pci_dev *pdev) | |
8211 | { | |
a31ff388 | 8212 | struct net_device *dev = pci_get_drvdata(pdev); |
1ee6dd77 | 8213 | struct s2io_nic *sp; |
1da177e4 LT |
8214 | |
8215 | if (dev == NULL) { | |
8216 | DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n"); | |
8217 | return; | |
8218 | } | |
8219 | ||
4cf1653a | 8220 | sp = netdev_priv(dev); |
23f333a2 TH |
8221 | |
8222 | cancel_work_sync(&sp->rst_timer_task); | |
8223 | cancel_work_sync(&sp->set_link_task); | |
8224 | ||
1da177e4 LT |
8225 | unregister_netdev(dev); |
8226 | ||
8227 | free_shared_mem(sp); | |
8228 | iounmap(sp->bar0); | |
8229 | iounmap(sp->bar1); | |
eccb8628 | 8230 | pci_release_regions(pdev); |
1da177e4 | 8231 | pci_set_drvdata(pdev, NULL); |
1da177e4 | 8232 | free_netdev(dev); |
19a60522 | 8233 | pci_disable_device(pdev); |
1da177e4 LT |
8234 | } |
8235 | ||
8236 | /** | |
8237 | * s2io_starter - Entry point for the driver | |
8238 | * Description: This function is the entry point for the driver. It verifies | |
8239 | * the module loadable parameters and initializes PCI configuration space. | |
8240 | */ | |
8241 | ||
43b7c451 | 8242 | static int __init s2io_starter(void) |
1da177e4 | 8243 | { |
29917620 | 8244 | return pci_register_driver(&s2io_driver); |
1da177e4 LT |
8245 | } |
8246 | ||
8247 | /** | |
20346722 | 8248 | * s2io_closer - Cleanup routine for the driver |
1da177e4 LT |
8249 | * Description: This function is the cleanup routine for the driver. It unregist * ers the driver. |
8250 | */ | |
8251 | ||
372cc597 | 8252 | static __exit void s2io_closer(void) |
1da177e4 LT |
8253 | { |
8254 | pci_unregister_driver(&s2io_driver); | |
8255 | DBG_PRINT(INIT_DBG, "cleanup done\n"); | |
8256 | } | |
8257 | ||
8258 | module_init(s2io_starter); | |
8259 | module_exit(s2io_closer); | |
7d3d0439 | 8260 | |
6aa20a22 | 8261 | static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip, |
d44570e4 JP |
8262 | struct tcphdr **tcp, struct RxD_t *rxdp, |
8263 | struct s2io_nic *sp) | |
7d3d0439 RA |
8264 | { |
8265 | int ip_off; | |
8266 | u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len; | |
8267 | ||
8268 | if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) { | |
d44570e4 JP |
8269 | DBG_PRINT(INIT_DBG, |
8270 | "%s: Non-TCP frames not supported for LRO\n", | |
b39d66a8 | 8271 | __func__); |
7d3d0439 RA |
8272 | return -1; |
8273 | } | |
8274 | ||
cdb5bf02 | 8275 | /* Checking for DIX type or DIX type with VLAN */ |
d44570e4 | 8276 | if ((l2_type == 0) || (l2_type == 4)) { |
cdb5bf02 SH |
8277 | ip_off = HEADER_ETHERNET_II_802_3_SIZE; |
8278 | /* | |
8279 | * If vlan stripping is disabled and the frame is VLAN tagged, | |
8280 | * shift the offset by the VLAN header size bytes. | |
8281 | */ | |
cd0fce03 | 8282 | if ((!sp->vlan_strip_flag) && |
d44570e4 | 8283 | (rxdp->Control_1 & RXD_FRAME_VLAN_TAG)) |
cdb5bf02 SH |
8284 | ip_off += HEADER_VLAN_SIZE; |
8285 | } else { | |
7d3d0439 | 8286 | /* LLC, SNAP etc are considered non-mergeable */ |
cdb5bf02 | 8287 | return -1; |
7d3d0439 RA |
8288 | } |
8289 | ||
8290 | *ip = (struct iphdr *)((u8 *)buffer + ip_off); | |
8291 | ip_len = (u8)((*ip)->ihl); | |
8292 | ip_len <<= 2; | |
8293 | *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len); | |
8294 | ||
8295 | return 0; | |
8296 | } | |
8297 | ||
1ee6dd77 | 8298 | static int check_for_socket_match(struct lro *lro, struct iphdr *ip, |
7d3d0439 RA |
8299 | struct tcphdr *tcp) |
8300 | { | |
d44570e4 JP |
8301 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
8302 | if ((lro->iph->saddr != ip->saddr) || | |
8303 | (lro->iph->daddr != ip->daddr) || | |
8304 | (lro->tcph->source != tcp->source) || | |
8305 | (lro->tcph->dest != tcp->dest)) | |
7d3d0439 RA |
8306 | return -1; |
8307 | return 0; | |
8308 | } | |
8309 | ||
8310 | static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp) | |
8311 | { | |
d44570e4 | 8312 | return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2); |
7d3d0439 RA |
8313 | } |
8314 | ||
1ee6dd77 | 8315 | static void initiate_new_session(struct lro *lro, u8 *l2h, |
d44570e4 JP |
8316 | struct iphdr *ip, struct tcphdr *tcp, |
8317 | u32 tcp_pyld_len, u16 vlan_tag) | |
7d3d0439 | 8318 | { |
d44570e4 | 8319 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
7d3d0439 RA |
8320 | lro->l2h = l2h; |
8321 | lro->iph = ip; | |
8322 | lro->tcph = tcp; | |
8323 | lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq); | |
c8855953 | 8324 | lro->tcp_ack = tcp->ack_seq; |
7d3d0439 RA |
8325 | lro->sg_num = 1; |
8326 | lro->total_len = ntohs(ip->tot_len); | |
8327 | lro->frags_len = 0; | |
cdb5bf02 | 8328 | lro->vlan_tag = vlan_tag; |
6aa20a22 | 8329 | /* |
d44570e4 JP |
8330 | * Check if we saw TCP timestamp. |
8331 | * Other consistency checks have already been done. | |
8332 | */ | |
7d3d0439 | 8333 | if (tcp->doff == 8) { |
c8855953 SR |
8334 | __be32 *ptr; |
8335 | ptr = (__be32 *)(tcp+1); | |
7d3d0439 | 8336 | lro->saw_ts = 1; |
c8855953 | 8337 | lro->cur_tsval = ntohl(*(ptr+1)); |
7d3d0439 RA |
8338 | lro->cur_tsecr = *(ptr+2); |
8339 | } | |
8340 | lro->in_use = 1; | |
8341 | } | |
8342 | ||
1ee6dd77 | 8343 | static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro) |
7d3d0439 RA |
8344 | { |
8345 | struct iphdr *ip = lro->iph; | |
8346 | struct tcphdr *tcp = lro->tcph; | |
bd4f3ae1 | 8347 | __sum16 nchk; |
ffb5df6c JP |
8348 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
8349 | ||
d44570e4 | 8350 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
7d3d0439 RA |
8351 | |
8352 | /* Update L3 header */ | |
8353 | ip->tot_len = htons(lro->total_len); | |
8354 | ip->check = 0; | |
8355 | nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl); | |
8356 | ip->check = nchk; | |
8357 | ||
8358 | /* Update L4 header */ | |
8359 | tcp->ack_seq = lro->tcp_ack; | |
8360 | tcp->window = lro->window; | |
8361 | ||
8362 | /* Update tsecr field if this session has timestamps enabled */ | |
8363 | if (lro->saw_ts) { | |
c8855953 | 8364 | __be32 *ptr = (__be32 *)(tcp + 1); |
7d3d0439 RA |
8365 | *(ptr+2) = lro->cur_tsecr; |
8366 | } | |
8367 | ||
8368 | /* Update counters required for calculation of | |
8369 | * average no. of packets aggregated. | |
8370 | */ | |
ffb5df6c JP |
8371 | swstats->sum_avg_pkts_aggregated += lro->sg_num; |
8372 | swstats->num_aggregations++; | |
7d3d0439 RA |
8373 | } |
8374 | ||
1ee6dd77 | 8375 | static void aggregate_new_rx(struct lro *lro, struct iphdr *ip, |
d44570e4 | 8376 | struct tcphdr *tcp, u32 l4_pyld) |
7d3d0439 | 8377 | { |
d44570e4 | 8378 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
7d3d0439 RA |
8379 | lro->total_len += l4_pyld; |
8380 | lro->frags_len += l4_pyld; | |
8381 | lro->tcp_next_seq += l4_pyld; | |
8382 | lro->sg_num++; | |
8383 | ||
8384 | /* Update ack seq no. and window ad(from this pkt) in LRO object */ | |
8385 | lro->tcp_ack = tcp->ack_seq; | |
8386 | lro->window = tcp->window; | |
6aa20a22 | 8387 | |
7d3d0439 | 8388 | if (lro->saw_ts) { |
c8855953 | 8389 | __be32 *ptr; |
7d3d0439 | 8390 | /* Update tsecr and tsval from this packet */ |
c8855953 SR |
8391 | ptr = (__be32 *)(tcp+1); |
8392 | lro->cur_tsval = ntohl(*(ptr+1)); | |
7d3d0439 RA |
8393 | lro->cur_tsecr = *(ptr + 2); |
8394 | } | |
8395 | } | |
8396 | ||
1ee6dd77 | 8397 | static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip, |
7d3d0439 RA |
8398 | struct tcphdr *tcp, u32 tcp_pyld_len) |
8399 | { | |
7d3d0439 RA |
8400 | u8 *ptr; |
8401 | ||
d44570e4 | 8402 | DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__); |
79dc1901 | 8403 | |
7d3d0439 RA |
8404 | if (!tcp_pyld_len) { |
8405 | /* Runt frame or a pure ack */ | |
8406 | return -1; | |
8407 | } | |
8408 | ||
8409 | if (ip->ihl != 5) /* IP has options */ | |
8410 | return -1; | |
8411 | ||
75c30b13 AR |
8412 | /* If we see CE codepoint in IP header, packet is not mergeable */ |
8413 | if (INET_ECN_is_ce(ipv4_get_dsfield(ip))) | |
8414 | return -1; | |
8415 | ||
8416 | /* If we see ECE or CWR flags in TCP header, packet is not mergeable */ | |
d44570e4 JP |
8417 | if (tcp->urg || tcp->psh || tcp->rst || |
8418 | tcp->syn || tcp->fin || | |
8419 | tcp->ece || tcp->cwr || !tcp->ack) { | |
7d3d0439 RA |
8420 | /* |
8421 | * Currently recognize only the ack control word and | |
8422 | * any other control field being set would result in | |
8423 | * flushing the LRO session | |
8424 | */ | |
8425 | return -1; | |
8426 | } | |
8427 | ||
6aa20a22 | 8428 | /* |
7d3d0439 RA |
8429 | * Allow only one TCP timestamp option. Don't aggregate if |
8430 | * any other options are detected. | |
8431 | */ | |
8432 | if (tcp->doff != 5 && tcp->doff != 8) | |
8433 | return -1; | |
8434 | ||
8435 | if (tcp->doff == 8) { | |
6aa20a22 | 8436 | ptr = (u8 *)(tcp + 1); |
7d3d0439 RA |
8437 | while (*ptr == TCPOPT_NOP) |
8438 | ptr++; | |
8439 | if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP) | |
8440 | return -1; | |
8441 | ||
8442 | /* Ensure timestamp value increases monotonically */ | |
8443 | if (l_lro) | |
c8855953 | 8444 | if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2)))) |
7d3d0439 RA |
8445 | return -1; |
8446 | ||
8447 | /* timestamp echo reply should be non-zero */ | |
c8855953 | 8448 | if (*((__be32 *)(ptr+6)) == 0) |
7d3d0439 RA |
8449 | return -1; |
8450 | } | |
8451 | ||
8452 | return 0; | |
8453 | } | |
8454 | ||
d44570e4 JP |
8455 | static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, |
8456 | u8 **tcp, u32 *tcp_len, struct lro **lro, | |
8457 | struct RxD_t *rxdp, struct s2io_nic *sp) | |
7d3d0439 RA |
8458 | { |
8459 | struct iphdr *ip; | |
8460 | struct tcphdr *tcph; | |
8461 | int ret = 0, i; | |
cdb5bf02 | 8462 | u16 vlan_tag = 0; |
ffb5df6c | 8463 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
7d3d0439 | 8464 | |
d44570e4 JP |
8465 | ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp, |
8466 | rxdp, sp); | |
8467 | if (ret) | |
7d3d0439 | 8468 | return ret; |
7d3d0439 | 8469 | |
d44570e4 JP |
8470 | DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr); |
8471 | ||
cdb5bf02 | 8472 | vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2); |
7d3d0439 RA |
8473 | tcph = (struct tcphdr *)*tcp; |
8474 | *tcp_len = get_l4_pyld_length(ip, tcph); | |
d44570e4 | 8475 | for (i = 0; i < MAX_LRO_SESSIONS; i++) { |
0425b46a | 8476 | struct lro *l_lro = &ring_data->lro0_n[i]; |
7d3d0439 RA |
8477 | if (l_lro->in_use) { |
8478 | if (check_for_socket_match(l_lro, ip, tcph)) | |
8479 | continue; | |
8480 | /* Sock pair matched */ | |
8481 | *lro = l_lro; | |
8482 | ||
8483 | if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) { | |
9e39f7c5 JP |
8484 | DBG_PRINT(INFO_DBG, "%s: Out of sequence. " |
8485 | "expected 0x%x, actual 0x%x\n", | |
8486 | __func__, | |
7d3d0439 RA |
8487 | (*lro)->tcp_next_seq, |
8488 | ntohl(tcph->seq)); | |
8489 | ||
ffb5df6c | 8490 | swstats->outof_sequence_pkts++; |
7d3d0439 RA |
8491 | ret = 2; |
8492 | break; | |
8493 | } | |
8494 | ||
d44570e4 JP |
8495 | if (!verify_l3_l4_lro_capable(l_lro, ip, tcph, |
8496 | *tcp_len)) | |
7d3d0439 RA |
8497 | ret = 1; /* Aggregate */ |
8498 | else | |
8499 | ret = 2; /* Flush both */ | |
8500 | break; | |
8501 | } | |
8502 | } | |
8503 | ||
8504 | if (ret == 0) { | |
8505 | /* Before searching for available LRO objects, | |
8506 | * check if the pkt is L3/L4 aggregatable. If not | |
8507 | * don't create new LRO session. Just send this | |
8508 | * packet up. | |
8509 | */ | |
d44570e4 | 8510 | if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) |
7d3d0439 | 8511 | return 5; |
7d3d0439 | 8512 | |
d44570e4 | 8513 | for (i = 0; i < MAX_LRO_SESSIONS; i++) { |
0425b46a | 8514 | struct lro *l_lro = &ring_data->lro0_n[i]; |
7d3d0439 RA |
8515 | if (!(l_lro->in_use)) { |
8516 | *lro = l_lro; | |
8517 | ret = 3; /* Begin anew */ | |
8518 | break; | |
8519 | } | |
8520 | } | |
8521 | } | |
8522 | ||
8523 | if (ret == 0) { /* sessions exceeded */ | |
9e39f7c5 | 8524 | DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n", |
b39d66a8 | 8525 | __func__); |
7d3d0439 RA |
8526 | *lro = NULL; |
8527 | return ret; | |
8528 | } | |
8529 | ||
8530 | switch (ret) { | |
d44570e4 JP |
8531 | case 3: |
8532 | initiate_new_session(*lro, buffer, ip, tcph, *tcp_len, | |
8533 | vlan_tag); | |
8534 | break; | |
8535 | case 2: | |
8536 | update_L3L4_header(sp, *lro); | |
8537 | break; | |
8538 | case 1: | |
8539 | aggregate_new_rx(*lro, ip, tcph, *tcp_len); | |
8540 | if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) { | |
7d3d0439 | 8541 | update_L3L4_header(sp, *lro); |
d44570e4 JP |
8542 | ret = 4; /* Flush the LRO */ |
8543 | } | |
8544 | break; | |
8545 | default: | |
9e39f7c5 | 8546 | DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__); |
d44570e4 | 8547 | break; |
7d3d0439 RA |
8548 | } |
8549 | ||
8550 | return ret; | |
8551 | } | |
8552 | ||
1ee6dd77 | 8553 | static void clear_lro_session(struct lro *lro) |
7d3d0439 | 8554 | { |
1ee6dd77 | 8555 | static u16 lro_struct_size = sizeof(struct lro); |
7d3d0439 RA |
8556 | |
8557 | memset(lro, 0, lro_struct_size); | |
8558 | } | |
8559 | ||
cdb5bf02 | 8560 | static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag) |
7d3d0439 RA |
8561 | { |
8562 | struct net_device *dev = skb->dev; | |
4cf1653a | 8563 | struct s2io_nic *sp = netdev_priv(dev); |
7d3d0439 RA |
8564 | |
8565 | skb->protocol = eth_type_trans(skb, dev); | |
b85da2c0 JP |
8566 | if (vlan_tag && sp->vlan_strip_flag) |
8567 | __vlan_hwaccel_put_tag(skb, vlan_tag); | |
8568 | if (sp->config.napi) | |
8569 | netif_receive_skb(skb); | |
8570 | else | |
8571 | netif_rx(skb); | |
7d3d0439 RA |
8572 | } |
8573 | ||
1ee6dd77 | 8574 | static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, |
d44570e4 | 8575 | struct sk_buff *skb, u32 tcp_len) |
7d3d0439 | 8576 | { |
75c30b13 | 8577 | struct sk_buff *first = lro->parent; |
ffb5df6c | 8578 | struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; |
7d3d0439 RA |
8579 | |
8580 | first->len += tcp_len; | |
8581 | first->data_len = lro->frags_len; | |
8582 | skb_pull(skb, (skb->len - tcp_len)); | |
75c30b13 AR |
8583 | if (skb_shinfo(first)->frag_list) |
8584 | lro->last_frag->next = skb; | |
7d3d0439 RA |
8585 | else |
8586 | skb_shinfo(first)->frag_list = skb; | |
372cc597 | 8587 | first->truesize += skb->truesize; |
75c30b13 | 8588 | lro->last_frag = skb; |
ffb5df6c | 8589 | swstats->clubbed_frms_cnt++; |
7d3d0439 | 8590 | } |
d796fdb7 LV |
8591 | |
8592 | /** | |
8593 | * s2io_io_error_detected - called when PCI error is detected | |
8594 | * @pdev: Pointer to PCI device | |
8453d43f | 8595 | * @state: The current pci connection state |
d796fdb7 LV |
8596 | * |
8597 | * This function is called after a PCI bus error affecting | |
8598 | * this device has been detected. | |
8599 | */ | |
8600 | static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev, | |
d44570e4 | 8601 | pci_channel_state_t state) |
d796fdb7 LV |
8602 | { |
8603 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4cf1653a | 8604 | struct s2io_nic *sp = netdev_priv(netdev); |
d796fdb7 LV |
8605 | |
8606 | netif_device_detach(netdev); | |
8607 | ||
1e3c8bd6 DN |
8608 | if (state == pci_channel_io_perm_failure) |
8609 | return PCI_ERS_RESULT_DISCONNECT; | |
8610 | ||
d796fdb7 LV |
8611 | if (netif_running(netdev)) { |
8612 | /* Bring down the card, while avoiding PCI I/O */ | |
8613 | do_s2io_card_down(sp, 0); | |
d796fdb7 LV |
8614 | } |
8615 | pci_disable_device(pdev); | |
8616 | ||
8617 | return PCI_ERS_RESULT_NEED_RESET; | |
8618 | } | |
8619 | ||
8620 | /** | |
8621 | * s2io_io_slot_reset - called after the pci bus has been reset. | |
8622 | * @pdev: Pointer to PCI device | |
8623 | * | |
8624 | * Restart the card from scratch, as if from a cold-boot. | |
8625 | * At this point, the card has exprienced a hard reset, | |
8626 | * followed by fixups by BIOS, and has its config space | |
8627 | * set up identically to what it was at cold boot. | |
8628 | */ | |
8629 | static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev) | |
8630 | { | |
8631 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4cf1653a | 8632 | struct s2io_nic *sp = netdev_priv(netdev); |
d796fdb7 LV |
8633 | |
8634 | if (pci_enable_device(pdev)) { | |
6cef2b8e | 8635 | pr_err("Cannot re-enable PCI device after reset.\n"); |
d796fdb7 LV |
8636 | return PCI_ERS_RESULT_DISCONNECT; |
8637 | } | |
8638 | ||
8639 | pci_set_master(pdev); | |
8640 | s2io_reset(sp); | |
8641 | ||
8642 | return PCI_ERS_RESULT_RECOVERED; | |
8643 | } | |
8644 | ||
8645 | /** | |
8646 | * s2io_io_resume - called when traffic can start flowing again. | |
8647 | * @pdev: Pointer to PCI device | |
8648 | * | |
8649 | * This callback is called when the error recovery driver tells | |
8650 | * us that its OK to resume normal operation. | |
8651 | */ | |
8652 | static void s2io_io_resume(struct pci_dev *pdev) | |
8653 | { | |
8654 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4cf1653a | 8655 | struct s2io_nic *sp = netdev_priv(netdev); |
d796fdb7 LV |
8656 | |
8657 | if (netif_running(netdev)) { | |
8658 | if (s2io_card_up(sp)) { | |
6cef2b8e | 8659 | pr_err("Can't bring device back up after reset.\n"); |
d796fdb7 LV |
8660 | return; |
8661 | } | |
8662 | ||
8663 | if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) { | |
8664 | s2io_card_down(sp); | |
6cef2b8e | 8665 | pr_err("Can't restore mac addr after reset.\n"); |
d796fdb7 LV |
8666 | return; |
8667 | } | |
8668 | } | |
8669 | ||
8670 | netif_device_attach(netdev); | |
fd2ea0a7 | 8671 | netif_tx_wake_all_queues(netdev); |
d796fdb7 | 8672 | } |