projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| db8bcaad HV |
1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| 2 | ||
| 3 | /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200. | |
| 4 | * Commit ID: 26db2002924973d36a30b369c94f025a678fe9ea (dirty) | |
| 5 | */ | |
| 6 | ||
| 7 | #ifndef _LAN966X_REGS_H_ | |
| 8 | #define _LAN966X_REGS_H_ | |
| 9 | ||
| 10 | #include <linux/bitfield.h> | |
| 11 | #include <linux/types.h> | |
| 12 | #include <linux/bug.h> | |
| 13 | ||
| 14 | enum lan966x_target { | |
| 15 | TARGET_AFI = 2, | |
| 16 | TARGET_ANA = 3, | |
| 17 | TARGET_CHIP_TOP = 5, | |
| 18 | TARGET_CPU = 6, | |
| 19 | TARGET_DEV = 13, | |
| 20 | TARGET_GCB = 27, | |
| 21 | TARGET_ORG = 36, | |
| 22 | TARGET_QS = 42, | |
| 23 | TARGET_QSYS = 46, | |
| 24 | TARGET_REW = 47, | |
| 25 | TARGET_SYS = 52, | |
| 26 | NUM_TARGETS = 66 | |
| 27 | }; | |
| 28 | ||
| 29 | #define __REG(...) __VA_ARGS__ | |
| 30 | ||
| 31 | /* AFI:PORT_TBL:PORT_FRM_OUT */ | |
| 32 | #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) | |
| 33 | ||
| 34 | #define AFI_PORT_FRM_OUT_FRM_OUT_CNT GENMASK(26, 16) | |
| 35 | #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_SET(x)\ | |
| 36 | FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) | |
| 37 | #define AFI_PORT_FRM_OUT_FRM_OUT_CNT_GET(x)\ | |
| 38 | FIELD_GET(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) | |
| 39 | ||
| 40 | /* AFI:PORT_TBL:PORT_CFG */ | |
| 41 | #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) | |
| 42 | ||
| 43 | #define AFI_PORT_CFG_FC_SKIP_TTI_INJ BIT(16) | |
| 44 | #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_SET(x)\ | |
| 45 | FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) | |
| 46 | #define AFI_PORT_CFG_FC_SKIP_TTI_INJ_GET(x)\ | |
| 47 | FIELD_GET(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) | |
| 48 | ||
| 49 | #define AFI_PORT_CFG_FRM_OUT_MAX GENMASK(9, 0) | |
| 50 | #define AFI_PORT_CFG_FRM_OUT_MAX_SET(x)\ | |
| 51 | FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) | |
| 52 | #define AFI_PORT_CFG_FRM_OUT_MAX_GET(x)\ | |
| 53 | FIELD_GET(AFI_PORT_CFG_FRM_OUT_MAX, x) | |
| 54 | ||
| 55 | /* ANA:ANA:ADVLEARN */ | |
| 56 | #define ANA_ADVLEARN __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 0, 0, 1, 4) | |
| 57 | ||
| 58 | #define ANA_ADVLEARN_VLAN_CHK BIT(0) | |
| 59 | #define ANA_ADVLEARN_VLAN_CHK_SET(x)\ | |
| 60 | FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) | |
| 61 | #define ANA_ADVLEARN_VLAN_CHK_GET(x)\ | |
| 62 | FIELD_GET(ANA_ADVLEARN_VLAN_CHK, x) | |
| 63 | ||
| 64 | /* ANA:ANA:ANAINTR */ | |
| 65 | #define ANA_ANAINTR __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 16, 0, 1, 4) | |
| 66 | ||
| 67 | #define ANA_ANAINTR_INTR BIT(1) | |
| 68 | #define ANA_ANAINTR_INTR_SET(x)\ | |
| 69 | FIELD_PREP(ANA_ANAINTR_INTR, x) | |
| 70 | #define ANA_ANAINTR_INTR_GET(x)\ | |
| 71 | FIELD_GET(ANA_ANAINTR_INTR, x) | |
| 72 | ||
| 73 | #define ANA_ANAINTR_INTR_ENA BIT(0) | |
| 74 | #define ANA_ANAINTR_INTR_ENA_SET(x)\ | |
| 75 | FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) | |
| 76 | #define ANA_ANAINTR_INTR_ENA_GET(x)\ | |
| 77 | FIELD_GET(ANA_ANAINTR_INTR_ENA, x) | |
| 78 | ||
| 79 | /* ANA:ANA:AUTOAGE */ | |
| 80 | #define ANA_AUTOAGE __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 44, 0, 1, 4) | |
| 81 | ||
| 82 | #define ANA_AUTOAGE_AGE_PERIOD GENMASK(20, 1) | |
| 83 | #define ANA_AUTOAGE_AGE_PERIOD_SET(x)\ | |
| 84 | FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) | |
| 85 | #define ANA_AUTOAGE_AGE_PERIOD_GET(x)\ | |
| 86 | FIELD_GET(ANA_AUTOAGE_AGE_PERIOD, x) | |
| 87 | ||
| 88 | /* ANA:ANA:FLOODING */ | |
| 89 | #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4) | |
| 90 | ||
| 91 | #define ANA_FLOODING_FLD_BROADCAST GENMASK(11, 6) | |
| 92 | #define ANA_FLOODING_FLD_BROADCAST_SET(x)\ | |
| 93 | FIELD_PREP(ANA_FLOODING_FLD_BROADCAST, x) | |
| 94 | #define ANA_FLOODING_FLD_BROADCAST_GET(x)\ | |
| 95 | FIELD_GET(ANA_FLOODING_FLD_BROADCAST, x) | |
| 96 | ||
| 97 | #define ANA_FLOODING_FLD_MULTICAST GENMASK(5, 0) | |
| 98 | #define ANA_FLOODING_FLD_MULTICAST_SET(x)\ | |
| 99 | FIELD_PREP(ANA_FLOODING_FLD_MULTICAST, x) | |
| 100 | #define ANA_FLOODING_FLD_MULTICAST_GET(x)\ | |
| 101 | FIELD_GET(ANA_FLOODING_FLD_MULTICAST, x) | |
| 102 | ||
| 103 | /* ANA:ANA:FLOODING_IPMC */ | |
| 104 | #define ANA_FLOODING_IPMC __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 100, 0, 1, 4) | |
| 105 | ||
| 106 | #define ANA_FLOODING_IPMC_FLD_MC4_CTRL GENMASK(23, 18) | |
| 107 | #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_SET(x)\ | |
| 108 | FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) | |
| 109 | #define ANA_FLOODING_IPMC_FLD_MC4_CTRL_GET(x)\ | |
| 110 | FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_CTRL, x) | |
| 111 | ||
| 112 | #define ANA_FLOODING_IPMC_FLD_MC4_DATA GENMASK(17, 12) | |
| 113 | #define ANA_FLOODING_IPMC_FLD_MC4_DATA_SET(x)\ | |
| 114 | FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) | |
| 115 | #define ANA_FLOODING_IPMC_FLD_MC4_DATA_GET(x)\ | |
| 116 | FIELD_GET(ANA_FLOODING_IPMC_FLD_MC4_DATA, x) | |
| 117 | ||
| 118 | #define ANA_FLOODING_IPMC_FLD_MC6_CTRL GENMASK(11, 6) | |
| 119 | #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_SET(x)\ | |
| 120 | FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) | |
| 121 | #define ANA_FLOODING_IPMC_FLD_MC6_CTRL_GET(x)\ | |
| 122 | FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_CTRL, x) | |
| 123 | ||
| 124 | #define ANA_FLOODING_IPMC_FLD_MC6_DATA GENMASK(5, 0) | |
| 125 | #define ANA_FLOODING_IPMC_FLD_MC6_DATA_SET(x)\ | |
| 126 | FIELD_PREP(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) | |
| 127 | #define ANA_FLOODING_IPMC_FLD_MC6_DATA_GET(x)\ | |
| 128 | FIELD_GET(ANA_FLOODING_IPMC_FLD_MC6_DATA, x) | |
| 129 | ||
| 130 | /* ANA:PGID:PGID */ | |
| 131 | #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) | |
| 132 | ||
| 133 | #define ANA_PGID_PGID GENMASK(8, 0) | |
| 134 | #define ANA_PGID_PGID_SET(x)\ | |
| 135 | FIELD_PREP(ANA_PGID_PGID, x) | |
| 136 | #define ANA_PGID_PGID_GET(x)\ | |
| 137 | FIELD_GET(ANA_PGID_PGID, x) | |
| 138 | ||
| 139 | /* ANA:PGID:PGID_CFG */ | |
| 140 | #define ANA_PGID_CFG(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 4, 0, 1, 4) | |
| 141 | ||
| 142 | #define ANA_PGID_CFG_OBEY_VLAN BIT(0) | |
| 143 | #define ANA_PGID_CFG_OBEY_VLAN_SET(x)\ | |
| 144 | FIELD_PREP(ANA_PGID_CFG_OBEY_VLAN, x) | |
| 145 | #define ANA_PGID_CFG_OBEY_VLAN_GET(x)\ | |
| 146 | FIELD_GET(ANA_PGID_CFG_OBEY_VLAN, x) | |
| 147 | ||
| 148 | /* ANA:ANA_TABLES:MACHDATA */ | |
| 149 | #define ANA_MACHDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 40, 0, 1, 4) | |
| 150 | ||
| 151 | /* ANA:ANA_TABLES:MACLDATA */ | |
| 152 | #define ANA_MACLDATA __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 44, 0, 1, 4) | |
| 153 | ||
| 154 | /* ANA:ANA_TABLES:MACACCESS */ | |
| 155 | #define ANA_MACACCESS __REG(TARGET_ANA, 0, 1, 27520, 0, 1, 128, 48, 0, 1, 4) | |
| 156 | ||
| 157 | #define ANA_MACACCESS_CHANGE2SW BIT(17) | |
| 158 | #define ANA_MACACCESS_CHANGE2SW_SET(x)\ | |
| 159 | FIELD_PREP(ANA_MACACCESS_CHANGE2SW, x) | |
| 160 | #define ANA_MACACCESS_CHANGE2SW_GET(x)\ | |
| 161 | FIELD_GET(ANA_MACACCESS_CHANGE2SW, x) | |
| 162 | ||
| 163 | #define ANA_MACACCESS_VALID BIT(12) | |
| 164 | #define ANA_MACACCESS_VALID_SET(x)\ | |
| 165 | FIELD_PREP(ANA_MACACCESS_VALID, x) | |
| 166 | #define ANA_MACACCESS_VALID_GET(x)\ | |
| 167 | FIELD_GET(ANA_MACACCESS_VALID, x) | |
| 168 | ||
| 169 | #define ANA_MACACCESS_ENTRYTYPE GENMASK(11, 10) | |
| 170 | #define ANA_MACACCESS_ENTRYTYPE_SET(x)\ | |
| 171 | FIELD_PREP(ANA_MACACCESS_ENTRYTYPE, x) | |
| 172 | #define ANA_MACACCESS_ENTRYTYPE_GET(x)\ | |
| 173 | FIELD_GET(ANA_MACACCESS_ENTRYTYPE, x) | |
| 174 | ||
| 175 | #define ANA_MACACCESS_DEST_IDX GENMASK(9, 4) | |
| 176 | #define ANA_MACACCESS_DEST_IDX_SET(x)\ | |
| 177 | FIELD_PREP(ANA_MACACCESS_DEST_IDX, x) | |
| 178 | #define ANA_MACACCESS_DEST_IDX_GET(x)\ | |
| 179 | FIELD_GET(ANA_MACACCESS_DEST_IDX, x) | |
| 180 | ||
| 181 | #define ANA_MACACCESS_MAC_TABLE_CMD GENMASK(3, 0) | |
| 182 | #define ANA_MACACCESS_MAC_TABLE_CMD_SET(x)\ | |
| 183 | FIELD_PREP(ANA_MACACCESS_MAC_TABLE_CMD, x) | |
| 184 | #define ANA_MACACCESS_MAC_TABLE_CMD_GET(x)\ | |
| 185 | FIELD_GET(ANA_MACACCESS_MAC_TABLE_CMD, x) | |
| 186 | ||
| 187 | /* ANA:PORT:CPU_FWD_CFG */ | |
| 188 | #define ANA_CPU_FWD_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 96, 0, 1, 4) | |
| 189 | ||
| 190 | #define ANA_CPU_FWD_CFG_SRC_COPY_ENA BIT(3) | |
| 191 | #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_SET(x)\ | |
| 192 | FIELD_PREP(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) | |
| 193 | #define ANA_CPU_FWD_CFG_SRC_COPY_ENA_GET(x)\ | |
| 194 | FIELD_GET(ANA_CPU_FWD_CFG_SRC_COPY_ENA, x) | |
| 195 | ||
| 196 | /* ANA:PORT:CPU_FWD_BPDU_CFG */ | |
| 197 | #define ANA_CPU_FWD_BPDU_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 100, 0, 1, 4) | |
| 198 | ||
| 199 | /* ANA:PORT:PORT_CFG */ | |
| 200 | #define ANA_PORT_CFG(g) __REG(TARGET_ANA, 0, 1, 28672, g, 9, 128, 112, 0, 1, 4) | |
| 201 | ||
| 202 | #define ANA_PORT_CFG_LEARNAUTO BIT(6) | |
| 203 | #define ANA_PORT_CFG_LEARNAUTO_SET(x)\ | |
| 204 | FIELD_PREP(ANA_PORT_CFG_LEARNAUTO, x) | |
| 205 | #define ANA_PORT_CFG_LEARNAUTO_GET(x)\ | |
| 206 | FIELD_GET(ANA_PORT_CFG_LEARNAUTO, x) | |
| 207 | ||
| 208 | #define ANA_PORT_CFG_LEARN_ENA BIT(5) | |
| 209 | #define ANA_PORT_CFG_LEARN_ENA_SET(x)\ | |
| 210 | FIELD_PREP(ANA_PORT_CFG_LEARN_ENA, x) | |
| 211 | #define ANA_PORT_CFG_LEARN_ENA_GET(x)\ | |
| 212 | FIELD_GET(ANA_PORT_CFG_LEARN_ENA, x) | |
| 213 | ||
| 214 | #define ANA_PORT_CFG_RECV_ENA BIT(4) | |
| 215 | #define ANA_PORT_CFG_RECV_ENA_SET(x)\ | |
| 216 | FIELD_PREP(ANA_PORT_CFG_RECV_ENA, x) | |
| 217 | #define ANA_PORT_CFG_RECV_ENA_GET(x)\ | |
| 218 | FIELD_GET(ANA_PORT_CFG_RECV_ENA, x) | |
| 219 | ||
| 220 | #define ANA_PORT_CFG_PORTID_VAL GENMASK(3, 0) | |
| 221 | #define ANA_PORT_CFG_PORTID_VAL_SET(x)\ | |
| 222 | FIELD_PREP(ANA_PORT_CFG_PORTID_VAL, x) | |
| 223 | #define ANA_PORT_CFG_PORTID_VAL_GET(x)\ | |
| 224 | FIELD_GET(ANA_PORT_CFG_PORTID_VAL, x) | |
| 225 | ||
| 226 | /* ANA:PFC:PFC_CFG */ | |
| 227 | #define ANA_PFC_CFG(g) __REG(TARGET_ANA, 0, 1, 30720, g, 8, 64, 0, 0, 1, 4) | |
| 228 | ||
| 229 | #define ANA_PFC_CFG_FC_LINK_SPEED GENMASK(1, 0) | |
| 230 | #define ANA_PFC_CFG_FC_LINK_SPEED_SET(x)\ | |
| 231 | FIELD_PREP(ANA_PFC_CFG_FC_LINK_SPEED, x) | |
| 232 | #define ANA_PFC_CFG_FC_LINK_SPEED_GET(x)\ | |
| 233 | FIELD_GET(ANA_PFC_CFG_FC_LINK_SPEED, x) | |
| 234 | ||
| 235 | /* CHIP_TOP:CUPHY_CFG:CUPHY_PORT_CFG */ | |
| 236 | #define CHIP_TOP_CUPHY_PORT_CFG(r) __REG(TARGET_CHIP_TOP, 0, 1, 16, 0, 1, 20, 8, r, 2, 4) | |
| 237 | ||
| 238 | #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA BIT(0) | |
| 239 | #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_SET(x)\ | |
| 240 | FIELD_PREP(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) | |
| 241 | #define CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA_GET(x)\ | |
| 242 | FIELD_GET(CHIP_TOP_CUPHY_PORT_CFG_GTX_CLK_ENA, x) | |
| 243 | ||
| 244 | /* DEV:PORT_MODE:CLOCK_CFG */ | |
| 245 | #define DEV_CLOCK_CFG(t) __REG(TARGET_DEV, t, 8, 0, 0, 1, 28, 0, 0, 1, 4) | |
| 246 | ||
| 247 | #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7) | |
| 248 | #define DEV_CLOCK_CFG_MAC_TX_RST_SET(x)\ | |
| 249 | FIELD_PREP(DEV_CLOCK_CFG_MAC_TX_RST, x) | |
| 250 | #define DEV_CLOCK_CFG_MAC_TX_RST_GET(x)\ | |
| 251 | FIELD_GET(DEV_CLOCK_CFG_MAC_TX_RST, x) | |
| 252 | ||
| 253 | #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6) | |
| 254 | #define DEV_CLOCK_CFG_MAC_RX_RST_SET(x)\ | |
| 255 | FIELD_PREP(DEV_CLOCK_CFG_MAC_RX_RST, x) | |
| 256 | #define DEV_CLOCK_CFG_MAC_RX_RST_GET(x)\ | |
| 257 | FIELD_GET(DEV_CLOCK_CFG_MAC_RX_RST, x) | |
| 258 | ||
| 259 | #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5) | |
| 260 | #define DEV_CLOCK_CFG_PCS_TX_RST_SET(x)\ | |
| 261 | FIELD_PREP(DEV_CLOCK_CFG_PCS_TX_RST, x) | |
| 262 | #define DEV_CLOCK_CFG_PCS_TX_RST_GET(x)\ | |
| 263 | FIELD_GET(DEV_CLOCK_CFG_PCS_TX_RST, x) | |
| 264 | ||
| 265 | #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4) | |
| 266 | #define DEV_CLOCK_CFG_PCS_RX_RST_SET(x)\ | |
| 267 | FIELD_PREP(DEV_CLOCK_CFG_PCS_RX_RST, x) | |
| 268 | #define DEV_CLOCK_CFG_PCS_RX_RST_GET(x)\ | |
| 269 | FIELD_GET(DEV_CLOCK_CFG_PCS_RX_RST, x) | |
| 270 | ||
| 271 | #define DEV_CLOCK_CFG_PORT_RST BIT(3) | |
| 272 | #define DEV_CLOCK_CFG_PORT_RST_SET(x)\ | |
| 273 | FIELD_PREP(DEV_CLOCK_CFG_PORT_RST, x) | |
| 274 | #define DEV_CLOCK_CFG_PORT_RST_GET(x)\ | |
| 275 | FIELD_GET(DEV_CLOCK_CFG_PORT_RST, x) | |
| 276 | ||
| 277 | #define DEV_CLOCK_CFG_LINK_SPEED GENMASK(1, 0) | |
| 278 | #define DEV_CLOCK_CFG_LINK_SPEED_SET(x)\ | |
| 279 | FIELD_PREP(DEV_CLOCK_CFG_LINK_SPEED, x) | |
| 280 | #define DEV_CLOCK_CFG_LINK_SPEED_GET(x)\ | |
| 281 | FIELD_GET(DEV_CLOCK_CFG_LINK_SPEED, x) | |
| 282 | ||
| 283 | /* DEV:MAC_CFG_STATUS:MAC_ENA_CFG */ | |
| 284 | #define DEV_MAC_ENA_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 0, 0, 1, 4) | |
| 285 | ||
| 286 | #define DEV_MAC_ENA_CFG_RX_ENA BIT(4) | |
| 287 | #define DEV_MAC_ENA_CFG_RX_ENA_SET(x)\ | |
| 288 | FIELD_PREP(DEV_MAC_ENA_CFG_RX_ENA, x) | |
| 289 | #define DEV_MAC_ENA_CFG_RX_ENA_GET(x)\ | |
| 290 | FIELD_GET(DEV_MAC_ENA_CFG_RX_ENA, x) | |
| 291 | ||
| 292 | #define DEV_MAC_ENA_CFG_TX_ENA BIT(0) | |
| 293 | #define DEV_MAC_ENA_CFG_TX_ENA_SET(x)\ | |
| 294 | FIELD_PREP(DEV_MAC_ENA_CFG_TX_ENA, x) | |
| 295 | #define DEV_MAC_ENA_CFG_TX_ENA_GET(x)\ | |
| 296 | FIELD_GET(DEV_MAC_ENA_CFG_TX_ENA, x) | |
| 297 | ||
| 298 | /* DEV:MAC_CFG_STATUS:MAC_MODE_CFG */ | |
| 299 | #define DEV_MAC_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 4, 0, 1, 4) | |
| 300 | ||
| 301 | #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4) | |
| 302 | #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\ | |
| 303 | FIELD_PREP(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) | |
| 304 | #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\ | |
| 305 | FIELD_GET(DEV_MAC_MODE_CFG_GIGA_MODE_ENA, x) | |
| 306 | ||
| 307 | /* DEV:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ | |
| 308 | #define DEV_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 8, 0, 1, 4) | |
| 309 | ||
| 310 | #define DEV_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) | |
| 311 | #define DEV_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ | |
| 312 | FIELD_PREP(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) | |
| 313 | #define DEV_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ | |
| 314 | FIELD_GET(DEV_MAC_MAXLEN_CFG_MAX_LEN, x) | |
| 315 | ||
| 316 | /* DEV:MAC_CFG_STATUS:MAC_IFG_CFG */ | |
| 317 | #define DEV_MAC_IFG_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 20, 0, 1, 4) | |
| 318 | ||
| 319 | #define DEV_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) | |
| 320 | #define DEV_MAC_IFG_CFG_TX_IFG_SET(x)\ | |
| 321 | FIELD_PREP(DEV_MAC_IFG_CFG_TX_IFG, x) | |
| 322 | #define DEV_MAC_IFG_CFG_TX_IFG_GET(x)\ | |
| 323 | FIELD_GET(DEV_MAC_IFG_CFG_TX_IFG, x) | |
| 324 | ||
| 325 | #define DEV_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) | |
| 326 | #define DEV_MAC_IFG_CFG_RX_IFG2_SET(x)\ | |
| 327 | FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG2, x) | |
| 328 | #define DEV_MAC_IFG_CFG_RX_IFG2_GET(x)\ | |
| 329 | FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG2, x) | |
| 330 | ||
| 331 | #define DEV_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) | |
| 332 | #define DEV_MAC_IFG_CFG_RX_IFG1_SET(x)\ | |
| 333 | FIELD_PREP(DEV_MAC_IFG_CFG_RX_IFG1, x) | |
| 334 | #define DEV_MAC_IFG_CFG_RX_IFG1_GET(x)\ | |
| 335 | FIELD_GET(DEV_MAC_IFG_CFG_RX_IFG1, x) | |
| 336 | ||
| 337 | /* DEV:MAC_CFG_STATUS:MAC_HDX_CFG */ | |
| 338 | #define DEV_MAC_HDX_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 24, 0, 1, 4) | |
| 339 | ||
| 340 | #define DEV_MAC_HDX_CFG_SEED GENMASK(23, 16) | |
| 341 | #define DEV_MAC_HDX_CFG_SEED_SET(x)\ | |
| 342 | FIELD_PREP(DEV_MAC_HDX_CFG_SEED, x) | |
| 343 | #define DEV_MAC_HDX_CFG_SEED_GET(x)\ | |
| 344 | FIELD_GET(DEV_MAC_HDX_CFG_SEED, x) | |
| 345 | ||
| 346 | #define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12) | |
| 347 | #define DEV_MAC_HDX_CFG_SEED_LOAD_SET(x)\ | |
| 348 | FIELD_PREP(DEV_MAC_HDX_CFG_SEED_LOAD, x) | |
| 349 | #define DEV_MAC_HDX_CFG_SEED_LOAD_GET(x)\ | |
| 350 | FIELD_GET(DEV_MAC_HDX_CFG_SEED_LOAD, x) | |
| 351 | ||
| 352 | /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_LOW_CFG */ | |
| 353 | #define DEV_FC_MAC_LOW_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 32, 0, 1, 4) | |
| 354 | ||
| 355 | /* DEV:MAC_CFG_STATUS:MAC_FC_MAC_HIGH_CFG */ | |
| 356 | #define DEV_FC_MAC_HIGH_CFG(t) __REG(TARGET_DEV, t, 8, 28, 0, 1, 44, 36, 0, 1, 4) | |
| 357 | ||
| 358 | /* DEV:PCS1G_CFG_STATUS:PCS1G_CFG */ | |
| 359 | #define DEV_PCS1G_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 0, 0, 1, 4) | |
| 360 | ||
| 361 | #define DEV_PCS1G_CFG_PCS_ENA BIT(0) | |
| 362 | #define DEV_PCS1G_CFG_PCS_ENA_SET(x)\ | |
| 363 | FIELD_PREP(DEV_PCS1G_CFG_PCS_ENA, x) | |
| 364 | #define DEV_PCS1G_CFG_PCS_ENA_GET(x)\ | |
| 365 | FIELD_GET(DEV_PCS1G_CFG_PCS_ENA, x) | |
| 366 | ||
| 367 | /* DEV:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ | |
| 368 | #define DEV_PCS1G_MODE_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 4, 0, 1, 4) | |
| 369 | ||
| 370 | #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0) | |
| 371 | #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\ | |
| 372 | FIELD_PREP(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) | |
| 373 | #define DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ | |
| 374 | FIELD_GET(DEV_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) | |
| 375 | ||
| 376 | /* DEV:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ | |
| 377 | #define DEV_PCS1G_SD_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 8, 0, 1, 4) | |
| 378 | ||
| 379 | #define DEV_PCS1G_SD_CFG_SD_ENA BIT(0) | |
| 380 | #define DEV_PCS1G_SD_CFG_SD_ENA_SET(x)\ | |
| 381 | FIELD_PREP(DEV_PCS1G_SD_CFG_SD_ENA, x) | |
| 382 | #define DEV_PCS1G_SD_CFG_SD_ENA_GET(x)\ | |
| 383 | FIELD_GET(DEV_PCS1G_SD_CFG_SD_ENA, x) | |
| 384 | ||
| 385 | /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ | |
| 386 | #define DEV_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 12, 0, 1, 4) | |
| 387 | ||
| 388 | #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) | |
| 389 | #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ | |
| 390 | FIELD_PREP(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) | |
| 391 | #define DEV_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\ | |
| 392 | FIELD_GET(DEV_PCS1G_ANEG_CFG_ADV_ABILITY, x) | |
| 393 | ||
| 394 | #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8) | |
| 395 | #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\ | |
| 396 | FIELD_PREP(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) | |
| 397 | #define DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\ | |
| 398 | FIELD_GET(DEV_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x) | |
| 399 | ||
| 400 | #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT BIT(1) | |
| 401 | #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_SET(x)\ | |
| 402 | FIELD_PREP(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) | |
| 403 | #define DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT_GET(x)\ | |
| 404 | FIELD_GET(DEV_PCS1G_ANEG_CFG_RESTART_ONE_SHOT, x) | |
| 405 | ||
| 406 | #define DEV_PCS1G_ANEG_CFG_ENA BIT(0) | |
| 407 | #define DEV_PCS1G_ANEG_CFG_ENA_SET(x)\ | |
| 408 | FIELD_PREP(DEV_PCS1G_ANEG_CFG_ENA, x) | |
| 409 | #define DEV_PCS1G_ANEG_CFG_ENA_GET(x)\ | |
| 410 | FIELD_GET(DEV_PCS1G_ANEG_CFG_ENA, x) | |
| 411 | ||
| 412 | /* DEV:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ | |
| 413 | #define DEV_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 32, 0, 1, 4) | |
| 414 | ||
| 415 | #define DEV_PCS1G_ANEG_STATUS_LP_ADV GENMASK(31, 16) | |
| 416 | #define DEV_PCS1G_ANEG_STATUS_LP_ADV_SET(x)\ | |
| 417 | FIELD_PREP(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) | |
| 418 | #define DEV_PCS1G_ANEG_STATUS_LP_ADV_GET(x)\ | |
| 419 | FIELD_GET(DEV_PCS1G_ANEG_STATUS_LP_ADV, x) | |
| 420 | ||
| 421 | #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0) | |
| 422 | #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\ | |
| 423 | FIELD_PREP(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) | |
| 424 | #define DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ | |
| 425 | FIELD_GET(DEV_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) | |
| 426 | ||
| 427 | /* DEV:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ | |
| 428 | #define DEV_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 40, 0, 1, 4) | |
| 429 | ||
| 430 | #define DEV_PCS1G_LINK_STATUS_LINK_STATUS BIT(4) | |
| 431 | #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\ | |
| 432 | FIELD_PREP(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) | |
| 433 | #define DEV_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\ | |
| 434 | FIELD_GET(DEV_PCS1G_LINK_STATUS_LINK_STATUS, x) | |
| 435 | ||
| 436 | #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS BIT(0) | |
| 437 | #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\ | |
| 438 | FIELD_PREP(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) | |
| 439 | #define DEV_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ | |
| 440 | FIELD_GET(DEV_PCS1G_LINK_STATUS_SYNC_STATUS, x) | |
| 441 | ||
| 442 | /* DEV:PCS1G_CFG_STATUS:PCS1G_STICKY */ | |
| 443 | #define DEV_PCS1G_STICKY(t) __REG(TARGET_DEV, t, 8, 72, 0, 1, 68, 48, 0, 1, 4) | |
| 444 | ||
| 445 | #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) | |
| 446 | #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ | |
| 447 | FIELD_PREP(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) | |
| 448 | #define DEV_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\ | |
| 449 | FIELD_GET(DEV_PCS1G_STICKY_LINK_DOWN_STICKY, x) | |
| 450 | ||
| 451 | /* DEVCPU_QS:XTR:XTR_GRP_CFG */ | |
| 452 | #define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) | |
| 453 | ||
| 454 | #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) | |
| 455 | #define QS_XTR_GRP_CFG_MODE_SET(x)\ | |
| 456 | FIELD_PREP(QS_XTR_GRP_CFG_MODE, x) | |
| 457 | #define QS_XTR_GRP_CFG_MODE_GET(x)\ | |
| 458 | FIELD_GET(QS_XTR_GRP_CFG_MODE, x) | |
| 459 | ||
| 460 | #define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0) | |
| 461 | #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\ | |
| 462 | FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x) | |
| 463 | #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ | |
| 464 | FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) | |
| 465 | ||
| 466 | /* DEVCPU_QS:XTR:XTR_RD */ | |
| 467 | #define QS_XTR_RD(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) | |
| 468 | ||
| 469 | /* DEVCPU_QS:XTR:XTR_FLUSH */ | |
| 470 | #define QS_XTR_FLUSH __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) | |
| 471 | ||
| 472 | /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ | |
| 473 | #define QS_XTR_DATA_PRESENT __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) | |
| 474 | ||
| 475 | /* DEVCPU_QS:INJ:INJ_GRP_CFG */ | |
| 476 | #define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) | |
| 477 | ||
| 478 | #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) | |
| 479 | #define QS_INJ_GRP_CFG_MODE_SET(x)\ | |
| 480 | FIELD_PREP(QS_INJ_GRP_CFG_MODE, x) | |
| 481 | #define QS_INJ_GRP_CFG_MODE_GET(x)\ | |
| 482 | FIELD_GET(QS_INJ_GRP_CFG_MODE, x) | |
| 483 | ||
| 484 | #define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0) | |
| 485 | #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\ | |
| 486 | FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x) | |
| 487 | #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ | |
| 488 | FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) | |
| 489 | ||
| 490 | /* DEVCPU_QS:INJ:INJ_WR */ | |
| 491 | #define QS_INJ_WR(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) | |
| 492 | ||
| 493 | /* DEVCPU_QS:INJ:INJ_CTRL */ | |
| 494 | #define QS_INJ_CTRL(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) | |
| 495 | ||
| 496 | #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) | |
| 497 | #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ | |
| 498 | FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x) | |
| 499 | #define QS_INJ_CTRL_GAP_SIZE_GET(x)\ | |
| 500 | FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x) | |
| 501 | ||
| 502 | #define QS_INJ_CTRL_EOF BIT(19) | |
| 503 | #define QS_INJ_CTRL_EOF_SET(x)\ | |
| 504 | FIELD_PREP(QS_INJ_CTRL_EOF, x) | |
| 505 | #define QS_INJ_CTRL_EOF_GET(x)\ | |
| 506 | FIELD_GET(QS_INJ_CTRL_EOF, x) | |
| 507 | ||
| 508 | #define QS_INJ_CTRL_SOF BIT(18) | |
| 509 | #define QS_INJ_CTRL_SOF_SET(x)\ | |
| 510 | FIELD_PREP(QS_INJ_CTRL_SOF, x) | |
| 511 | #define QS_INJ_CTRL_SOF_GET(x)\ | |
| 512 | FIELD_GET(QS_INJ_CTRL_SOF, x) | |
| 513 | ||
| 514 | #define QS_INJ_CTRL_VLD_BYTES GENMASK(17, 16) | |
| 515 | #define QS_INJ_CTRL_VLD_BYTES_SET(x)\ | |
| 516 | FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x) | |
| 517 | #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ | |
| 518 | FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) | |
| 519 | ||
| 520 | /* DEVCPU_QS:INJ:INJ_STATUS */ | |
| 521 | #define QS_INJ_STATUS __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) | |
| 522 | ||
| 523 | #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) | |
| 524 | #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ | |
| 525 | FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x) | |
| 526 | #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\ | |
| 527 | FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x) | |
| 528 | ||
| 529 | #define QS_INJ_STATUS_FIFO_RDY GENMASK(3, 2) | |
| 530 | #define QS_INJ_STATUS_FIFO_RDY_SET(x)\ | |
| 531 | FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x) | |
| 532 | #define QS_INJ_STATUS_FIFO_RDY_GET(x)\ | |
| 533 | FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x) | |
| 534 | ||
| 535 | /* QSYS:SYSTEM:PORT_MODE */ | |
| 536 | #define QSYS_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 0, r, 10, 4) | |
| 537 | ||
| 538 | #define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1) | |
| 539 | #define QSYS_PORT_MODE_DEQUEUE_DIS_SET(x)\ | |
| 540 | FIELD_PREP(QSYS_PORT_MODE_DEQUEUE_DIS, x) | |
| 541 | #define QSYS_PORT_MODE_DEQUEUE_DIS_GET(x)\ | |
| 542 | FIELD_GET(QSYS_PORT_MODE_DEQUEUE_DIS, x) | |
| 543 | ||
| 544 | /* QSYS:SYSTEM:SWITCH_PORT_MODE */ | |
| 545 | #define QSYS_SW_PORT_MODE(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 80, r, 9, 4) | |
| 546 | ||
| 547 | #define QSYS_SW_PORT_MODE_PORT_ENA BIT(18) | |
| 548 | #define QSYS_SW_PORT_MODE_PORT_ENA_SET(x)\ | |
| 549 | FIELD_PREP(QSYS_SW_PORT_MODE_PORT_ENA, x) | |
| 550 | #define QSYS_SW_PORT_MODE_PORT_ENA_GET(x)\ | |
| 551 | FIELD_GET(QSYS_SW_PORT_MODE_PORT_ENA, x) | |
| 552 | ||
| 553 | #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG GENMASK(16, 14) | |
| 554 | #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_SET(x)\ | |
| 555 | FIELD_PREP(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) | |
| 556 | #define QSYS_SW_PORT_MODE_SCH_NEXT_CFG_GET(x)\ | |
| 557 | FIELD_GET(QSYS_SW_PORT_MODE_SCH_NEXT_CFG, x) | |
| 558 | ||
| 559 | #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE BIT(12) | |
| 560 | #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_SET(x)\ | |
| 561 | FIELD_PREP(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) | |
| 562 | #define QSYS_SW_PORT_MODE_INGRESS_DROP_MODE_GET(x)\ | |
| 563 | FIELD_GET(QSYS_SW_PORT_MODE_INGRESS_DROP_MODE, x) | |
| 564 | ||
| 565 | #define QSYS_SW_PORT_MODE_TX_PFC_ENA GENMASK(11, 4) | |
| 566 | #define QSYS_SW_PORT_MODE_TX_PFC_ENA_SET(x)\ | |
| 567 | FIELD_PREP(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) | |
| 568 | #define QSYS_SW_PORT_MODE_TX_PFC_ENA_GET(x)\ | |
| 569 | FIELD_GET(QSYS_SW_PORT_MODE_TX_PFC_ENA, x) | |
| 570 | ||
| 571 | #define QSYS_SW_PORT_MODE_AGING_MODE GENMASK(1, 0) | |
| 572 | #define QSYS_SW_PORT_MODE_AGING_MODE_SET(x)\ | |
| 573 | FIELD_PREP(QSYS_SW_PORT_MODE_AGING_MODE, x) | |
| 574 | #define QSYS_SW_PORT_MODE_AGING_MODE_GET(x)\ | |
| 575 | FIELD_GET(QSYS_SW_PORT_MODE_AGING_MODE, x) | |
| 576 | ||
| 577 | /* QSYS:SYSTEM:SW_STATUS */ | |
| 578 | #define QSYS_SW_STATUS(r) __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 164, r, 9, 4) | |
| 579 | ||
| 580 | #define QSYS_SW_STATUS_EQ_AVAIL GENMASK(7, 0) | |
| 581 | #define QSYS_SW_STATUS_EQ_AVAIL_SET(x)\ | |
| 582 | FIELD_PREP(QSYS_SW_STATUS_EQ_AVAIL, x) | |
| 583 | #define QSYS_SW_STATUS_EQ_AVAIL_GET(x)\ | |
| 584 | FIELD_GET(QSYS_SW_STATUS_EQ_AVAIL, x) | |
| 585 | ||
| 586 | /* QSYS:SYSTEM:CPU_GROUP_MAP */ | |
| 587 | #define QSYS_CPU_GROUP_MAP __REG(TARGET_QSYS, 0, 1, 28008, 0, 1, 216, 204, 0, 1, 4) | |
| 588 | ||
| 589 | /* QSYS:RES_CTRL:RES_CFG */ | |
| 590 | #define QSYS_RES_CFG(g) __REG(TARGET_QSYS, 0, 1, 32768, g, 1024, 8, 0, 0, 1, 4) | |
| 591 | ||
| 592 | /* REW:PORT:PORT_CFG */ | |
| 593 | #define REW_PORT_CFG(g) __REG(TARGET_REW, 0, 1, 0, g, 10, 128, 8, 0, 1, 4) | |
| 594 | ||
| 595 | #define REW_PORT_CFG_NO_REWRITE BIT(0) | |
| 596 | #define REW_PORT_CFG_NO_REWRITE_SET(x)\ | |
| 597 | FIELD_PREP(REW_PORT_CFG_NO_REWRITE, x) | |
| 598 | #define REW_PORT_CFG_NO_REWRITE_GET(x)\ | |
| 599 | FIELD_GET(REW_PORT_CFG_NO_REWRITE, x) | |
| 600 | ||
| 601 | /* SYS:SYSTEM:RESET_CFG */ | |
| 602 | #define SYS_RESET_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 0, 0, 1, 4) | |
| 603 | ||
| 604 | #define SYS_RESET_CFG_CORE_ENA BIT(0) | |
| 605 | #define SYS_RESET_CFG_CORE_ENA_SET(x)\ | |
| 606 | FIELD_PREP(SYS_RESET_CFG_CORE_ENA, x) | |
| 607 | #define SYS_RESET_CFG_CORE_ENA_GET(x)\ | |
| 608 | FIELD_GET(SYS_RESET_CFG_CORE_ENA, x) | |
| 609 | ||
| 610 | /* SYS:SYSTEM:PORT_MODE */ | |
| 611 | #define SYS_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 44, r, 10, 4) | |
| 612 | ||
| 613 | #define SYS_PORT_MODE_INCL_INJ_HDR GENMASK(5, 4) | |
| 614 | #define SYS_PORT_MODE_INCL_INJ_HDR_SET(x)\ | |
| 615 | FIELD_PREP(SYS_PORT_MODE_INCL_INJ_HDR, x) | |
| 616 | #define SYS_PORT_MODE_INCL_INJ_HDR_GET(x)\ | |
| 617 | FIELD_GET(SYS_PORT_MODE_INCL_INJ_HDR, x) | |
| 618 | ||
| 619 | #define SYS_PORT_MODE_INCL_XTR_HDR GENMASK(3, 2) | |
| 620 | #define SYS_PORT_MODE_INCL_XTR_HDR_SET(x)\ | |
| 621 | FIELD_PREP(SYS_PORT_MODE_INCL_XTR_HDR, x) | |
| 622 | #define SYS_PORT_MODE_INCL_XTR_HDR_GET(x)\ | |
| 623 | FIELD_GET(SYS_PORT_MODE_INCL_XTR_HDR, x) | |
| 624 | ||
| 625 | /* SYS:SYSTEM:FRONT_PORT_MODE */ | |
| 626 | #define SYS_FRONT_PORT_MODE(r) __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 84, r, 8, 4) | |
| 627 | ||
| 628 | #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(1) | |
| 629 | #define SYS_FRONT_PORT_MODE_HDX_MODE_SET(x)\ | |
| 630 | FIELD_PREP(SYS_FRONT_PORT_MODE_HDX_MODE, x) | |
| 631 | #define SYS_FRONT_PORT_MODE_HDX_MODE_GET(x)\ | |
| 632 | FIELD_GET(SYS_FRONT_PORT_MODE_HDX_MODE, x) | |
| 633 | ||
| 634 | /* SYS:SYSTEM:FRM_AGING */ | |
| 635 | #define SYS_FRM_AGING __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 116, 0, 1, 4) | |
| 636 | ||
| 637 | #define SYS_FRM_AGING_AGE_TX_ENA BIT(20) | |
| 638 | #define SYS_FRM_AGING_AGE_TX_ENA_SET(x)\ | |
| 639 | FIELD_PREP(SYS_FRM_AGING_AGE_TX_ENA, x) | |
| 640 | #define SYS_FRM_AGING_AGE_TX_ENA_GET(x)\ | |
| 641 | FIELD_GET(SYS_FRM_AGING_AGE_TX_ENA, x) | |
| 642 | ||
| 643 | /* SYS:SYSTEM:STAT_CFG */ | |
| 644 | #define SYS_STAT_CFG __REG(TARGET_SYS, 0, 1, 4128, 0, 1, 168, 120, 0, 1, 4) | |
| 645 | ||
| 646 | #define SYS_STAT_CFG_STAT_VIEW GENMASK(9, 0) | |
| 647 | #define SYS_STAT_CFG_STAT_VIEW_SET(x)\ | |
| 648 | FIELD_PREP(SYS_STAT_CFG_STAT_VIEW, x) | |
| 649 | #define SYS_STAT_CFG_STAT_VIEW_GET(x)\ | |
| 650 | FIELD_GET(SYS_STAT_CFG_STAT_VIEW, x) | |
| 651 | ||
| 652 | /* SYS:PAUSE_CFG:PAUSE_CFG */ | |
| 653 | #define SYS_PAUSE_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 0, r, 9, 4) | |
| 654 | ||
| 655 | #define SYS_PAUSE_CFG_PAUSE_START GENMASK(18, 10) | |
| 656 | #define SYS_PAUSE_CFG_PAUSE_START_SET(x)\ | |
| 657 | FIELD_PREP(SYS_PAUSE_CFG_PAUSE_START, x) | |
| 658 | #define SYS_PAUSE_CFG_PAUSE_START_GET(x)\ | |
| 659 | FIELD_GET(SYS_PAUSE_CFG_PAUSE_START, x) | |
| 660 | ||
| 661 | #define SYS_PAUSE_CFG_PAUSE_STOP GENMASK(9, 1) | |
| 662 | #define SYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ | |
| 663 | FIELD_PREP(SYS_PAUSE_CFG_PAUSE_STOP, x) | |
| 664 | #define SYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ | |
| 665 | FIELD_GET(SYS_PAUSE_CFG_PAUSE_STOP, x) | |
| 666 | ||
| 667 | #define SYS_PAUSE_CFG_PAUSE_ENA BIT(0) | |
| 668 | #define SYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ | |
| 669 | FIELD_PREP(SYS_PAUSE_CFG_PAUSE_ENA, x) | |
| 670 | #define SYS_PAUSE_CFG_PAUSE_ENA_GET(x)\ | |
| 671 | FIELD_GET(SYS_PAUSE_CFG_PAUSE_ENA, x) | |
| 672 | ||
| 673 | /* SYS:PAUSE_CFG:ATOP */ | |
| 674 | #define SYS_ATOP(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 40, r, 9, 4) | |
| 675 | ||
| 676 | /* SYS:PAUSE_CFG:ATOP_TOT_CFG */ | |
| 677 | #define SYS_ATOP_TOT_CFG __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 76, 0, 1, 4) | |
| 678 | ||
| 679 | /* SYS:PAUSE_CFG:MAC_FC_CFG */ | |
| 680 | #define SYS_MAC_FC_CFG(r) __REG(TARGET_SYS, 0, 1, 4296, 0, 1, 112, 80, r, 8, 4) | |
| 681 | ||
| 682 | #define SYS_MAC_FC_CFG_FC_LINK_SPEED GENMASK(27, 26) | |
| 683 | #define SYS_MAC_FC_CFG_FC_LINK_SPEED_SET(x)\ | |
| 684 | FIELD_PREP(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) | |
| 685 | #define SYS_MAC_FC_CFG_FC_LINK_SPEED_GET(x)\ | |
| 686 | FIELD_GET(SYS_MAC_FC_CFG_FC_LINK_SPEED, x) | |
| 687 | ||
| 688 | #define SYS_MAC_FC_CFG_FC_LATENCY_CFG GENMASK(25, 20) | |
| 689 | #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_SET(x)\ | |
| 690 | FIELD_PREP(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) | |
| 691 | #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_GET(x)\ | |
| 692 | FIELD_GET(SYS_MAC_FC_CFG_FC_LATENCY_CFG, x) | |
| 693 | ||
| 694 | #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18) | |
| 695 | #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_SET(x)\ | |
| 696 | FIELD_PREP(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) | |
| 697 | #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA_GET(x)\ | |
| 698 | FIELD_GET(SYS_MAC_FC_CFG_ZERO_PAUSE_ENA, x) | |
| 699 | ||
| 700 | #define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17) | |
| 701 | #define SYS_MAC_FC_CFG_TX_FC_ENA_SET(x)\ | |
| 702 | FIELD_PREP(SYS_MAC_FC_CFG_TX_FC_ENA, x) | |
| 703 | #define SYS_MAC_FC_CFG_TX_FC_ENA_GET(x)\ | |
| 704 | FIELD_GET(SYS_MAC_FC_CFG_TX_FC_ENA, x) | |
| 705 | ||
| 706 | #define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16) | |
| 707 | #define SYS_MAC_FC_CFG_RX_FC_ENA_SET(x)\ | |
| 708 | FIELD_PREP(SYS_MAC_FC_CFG_RX_FC_ENA, x) | |
| 709 | #define SYS_MAC_FC_CFG_RX_FC_ENA_GET(x)\ | |
| 710 | FIELD_GET(SYS_MAC_FC_CFG_RX_FC_ENA, x) | |
| 711 | ||
| 712 | #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG GENMASK(15, 0) | |
| 713 | #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_SET(x)\ | |
| 714 | FIELD_PREP(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) | |
| 715 | #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_GET(x)\ | |
| 716 | FIELD_GET(SYS_MAC_FC_CFG_PAUSE_VAL_CFG, x) | |
| 717 | ||
| 718 | /* SYS:STAT:CNT */ | |
| 719 | #define SYS_CNT(g) __REG(TARGET_SYS, 0, 1, 0, g, 896, 4, 0, 0, 1, 4) | |
| 720 | ||
| 721 | /* SYS:RAM_CTRL:RAM_INIT */ | |
| 722 | #define SYS_RAM_INIT __REG(TARGET_SYS, 0, 1, 4432, 0, 1, 4, 0, 0, 1, 4) | |
| 723 | ||
| 724 | #define SYS_RAM_INIT_RAM_INIT BIT(1) | |
| 725 | #define SYS_RAM_INIT_RAM_INIT_SET(x)\ | |
| 726 | FIELD_PREP(SYS_RAM_INIT_RAM_INIT, x) | |
| 727 | #define SYS_RAM_INIT_RAM_INIT_GET(x)\ | |
| 728 | FIELD_GET(SYS_RAM_INIT_RAM_INIT, x) | |
| 729 | ||
| 730 | #endif /* _LAN966X_REGS_H_ */ |