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net: encx24j600_exit() can be static
[linux-2.6-block.git] / drivers / net / ethernet / microchip / encx24j600.c
CommitLineData
04fbfce7
JR		 1/**
2 * Microchip ENCX24J600 ethernet driver
3 *
4 * Copyright (C) 2015 Gridpoint
5 * Author: Jon Ringle <jringle@gridpoint.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/interrupt.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/netdevice.h>
22#include <linux/regmap.h>
23#include <linux/skbuff.h>
24#include <linux/spi/spi.h>
25
26#include "encx24j600_hw.h"
27
28#define DRV_NAME "encx24j600"
29#define DRV_VERSION "1.0"
30
31#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
32static int debug = -1;
33module_param(debug, int, 0);
34MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
35
36/* SRAM memory layout:
37 *
38 * 0x0000-0x05ff TX buffers 1.5KB (1*1536) reside in the GP area in SRAM
39 * 0x0600-0x5fff RX buffers 22.5KB (15*1536) reside in the RX area in SRAM
40 */
41#define ENC_TX_BUF_START 0x0000U
42#define ENC_RX_BUF_START 0x0600U
43#define ENC_RX_BUF_END 0x5fffU
44#define ENC_SRAM_SIZE 0x6000U
45
46enum {
47 RXFILTER_NORMAL,
48 RXFILTER_MULTI,
49 RXFILTER_PROMISC
50};
51
52struct encx24j600_priv {
53 struct net_device *ndev;
54 struct mutex lock; /* device access lock */
55 struct encx24j600_context ctx;
56 struct sk_buff *tx_skb;
57 struct task_struct *kworker_task;
58 struct kthread_worker kworker;
59 struct kthread_work tx_work;
60 struct kthread_work setrx_work;
61 u16 next_packet;
62 bool hw_enabled;
63 bool full_duplex;
64 bool autoneg;
65 u16 speed;
66 int rxfilter;
67 u32 msg_enable;
68};
69
70static void dump_packet(const char *msg, int len, const char *data)
71{
72 pr_debug(DRV_NAME ": %s - packet len:%d\n", msg, len);
73 print_hex_dump_bytes("pk data: ", DUMP_PREFIX_OFFSET, data, len);
74}
75
76static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg,
77 struct rsv *rsv)
78{
79 struct net_device *dev = priv->ndev;
80
81 netdev_info(dev, "RX packet Len:%d\n", rsv->len);
82 netdev_dbg(dev, "%s - NextPk: 0x%04x\n", msg,
83 rsv->next_packet);
84 netdev_dbg(dev, "RxOK: %d, DribbleNibble: %d\n",
85 RSV_GETBIT(rsv->rxstat, RSV_RXOK),
86 RSV_GETBIT(rsv->rxstat, RSV_DRIBBLENIBBLE));
87 netdev_dbg(dev, "CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
88 RSV_GETBIT(rsv->rxstat, RSV_CRCERROR),
89 RSV_GETBIT(rsv->rxstat, RSV_LENCHECKERR),
90 RSV_GETBIT(rsv->rxstat, RSV_LENOUTOFRANGE));
91 netdev_dbg(dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
92 RSV_GETBIT(rsv->rxstat, RSV_RXMULTICAST),
93 RSV_GETBIT(rsv->rxstat, RSV_RXBROADCAST),
94 RSV_GETBIT(rsv->rxstat, RSV_RXLONGEVDROPEV),
95 RSV_GETBIT(rsv->rxstat, RSV_CARRIEREV));
96 netdev_dbg(dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
97 RSV_GETBIT(rsv->rxstat, RSV_RXCONTROLFRAME),
98 RSV_GETBIT(rsv->rxstat, RSV_RXPAUSEFRAME),
99 RSV_GETBIT(rsv->rxstat, RSV_RXUNKNOWNOPCODE),
100 RSV_GETBIT(rsv->rxstat, RSV_RXTYPEVLAN));
101}
102
103static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg)
104{
105 struct net_device *dev = priv->ndev;
106 unsigned int val = 0;
107 int ret = regmap_read(priv->ctx.regmap, reg, &val);
108 if (unlikely(ret))
109 netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n",
110 __func__, ret, reg);
111 return val;
112}
113
114static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val)
115{
116 struct net_device *dev = priv->ndev;
117 int ret = regmap_write(priv->ctx.regmap, reg, val);
118 if (unlikely(ret))
119 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
120 __func__, ret, reg, val);
121}
122
123static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg,
124 u16 mask, u16 val)
125{
126 struct net_device *dev = priv->ndev;
127 int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val);
128 if (unlikely(ret))
129 netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n",
130 __func__, ret, reg, val, mask);
131}
132
133static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg)
134{
135 struct net_device *dev = priv->ndev;
136 unsigned int val = 0;
137 int ret = regmap_read(priv->ctx.phymap, reg, &val);
138 if (unlikely(ret))
139 netif_err(priv, drv, dev, "%s: error %d reading %02x\n",
140 __func__, ret, reg);
141 return val;
142}
143
144static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val)
145{
146 struct net_device *dev = priv->ndev;
147 int ret = regmap_write(priv->ctx.phymap, reg, val);
148 if (unlikely(ret))
149 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
150 __func__, ret, reg, val);
151}
152
153static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
154{
155 encx24j600_update_reg(priv, reg, mask, 0);
156}
157
158static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
159{
160 encx24j600_update_reg(priv, reg, mask, mask);
161}
162
163static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd)
164{
165 struct net_device *dev = priv->ndev;
166 int ret = regmap_write(priv->ctx.regmap, cmd, 0);
167 if (unlikely(ret))
168 netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n",
169 __func__, ret, cmd);
170}
171
172static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data,
173 size_t count)
174{
175 int ret;
176 mutex_lock(&priv->ctx.mutex);
177 ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count);
178 mutex_unlock(&priv->ctx.mutex);
179
180 return ret;
181}
182
183static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg,
184 const u8 *data, size_t count)
185{
186 int ret;
187 mutex_lock(&priv->ctx.mutex);
188 ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count);
189 mutex_unlock(&priv->ctx.mutex);
190
191 return ret;
192}
193
194static void encx24j600_update_phcon1(struct encx24j600_priv *priv)
195{
196 u16 phcon1 = encx24j600_read_phy(priv, PHCON1);
197 if (priv->autoneg == AUTONEG_ENABLE) {
198 phcon1 |= ANEN | RENEG;
199 } else {
200 phcon1 &= ~ANEN;
201 if (priv->speed == SPEED_100)
202 phcon1 |= SPD100;
203 else
204 phcon1 &= ~SPD100;
205
206 if (priv->full_duplex)
207 phcon1 |= PFULDPX;
208 else
209 phcon1 &= ~PFULDPX;
210 }
211 encx24j600_write_phy(priv, PHCON1, phcon1);
212}
213
214/* Waits for autonegotiation to complete. */
215static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv)
216{
217 struct net_device *dev = priv->ndev;
218 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
219 u16 phstat1;
220 u16 estat;
221 int ret = 0;
222
223 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
224 while ((phstat1 & ANDONE) == 0) {
225 if (time_after(jiffies, timeout)) {
226 u16 phstat3;
227
228 netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n");
229
230 priv->autoneg = AUTONEG_DISABLE;
231 phstat3 = encx24j600_read_phy(priv, PHSTAT3);
232 priv->speed = (phstat3 & PHY3SPD100)
233 ? SPEED_100 : SPEED_10;
234 priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0;
235 encx24j600_update_phcon1(priv);
236 netif_notice(priv, drv, dev, "Using parallel detection: %s/%s",
237 priv->speed == SPEED_100 ? "100" : "10",
238 priv->full_duplex ? "Full" : "Half");
239
240 return -ETIMEDOUT;
241 }
242 cpu_relax();
243 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
244 }
245
246 estat = encx24j600_read_reg(priv, ESTAT);
247 if (estat & PHYDPX) {
248 encx24j600_set_bits(priv, MACON2, FULDPX);
249 encx24j600_write_reg(priv, MABBIPG, 0x15);
250 } else {
251 encx24j600_clr_bits(priv, MACON2, FULDPX);
252 encx24j600_write_reg(priv, MABBIPG, 0x12);
253 /* Max retransmittions attempt */
254 encx24j600_write_reg(priv, MACLCON, 0x370f);
255 }
256
257 return ret;
258}
259
260/* Access the PHY to determine link status */
261static void encx24j600_check_link_status(struct encx24j600_priv *priv)
262{
263 struct net_device *dev = priv->ndev;
264 u16 estat;
265
266 estat = encx24j600_read_reg(priv, ESTAT);
267
268 if (estat & PHYLNK) {
269 if (priv->autoneg == AUTONEG_ENABLE)
270 encx24j600_wait_for_autoneg(priv);
271
272 netif_carrier_on(dev);
273 netif_info(priv, ifup, dev, "link up\n");
274 } else {
275 netif_info(priv, ifdown, dev, "link down\n");
276
277 /* Re-enable autoneg since we won't know what we might be
278 * connected to when the link is brought back up again.
279 */
280 priv->autoneg = AUTONEG_ENABLE;
281 priv->full_duplex = true;
282 priv->speed = SPEED_100;
283 netif_carrier_off(dev);
284 }
285}
286
287static void encx24j600_int_link_handler(struct encx24j600_priv *priv)
288{
289 struct net_device *dev = priv->ndev;
290
291 netif_dbg(priv, intr, dev, "%s", __func__);
292 encx24j600_check_link_status(priv);
293 encx24j600_clr_bits(priv, EIR, LINKIF);
294}
295
296static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err)
297{
298 struct net_device *dev = priv->ndev;
299
300 mutex_lock(&priv->lock);
301
302 if (err)
303 dev->stats.tx_errors++;
304 else
305 dev->stats.tx_packets++;
306
307 dev->stats.tx_bytes += priv->tx_skb->len;
308
309 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
310
311 netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : "");
312
313 if (priv->tx_skb) {
314 dev_kfree_skb(priv->tx_skb);
315 priv->tx_skb = NULL;
316 }
317
318 netif_wake_queue(dev);
319
320 mutex_unlock(&priv->lock);
321}
322
323static int encx24j600_receive_packet(struct encx24j600_priv *priv,
324 struct rsv *rsv)
325{
326 struct net_device *dev = priv->ndev;
327 struct sk_buff *skb = netdev_alloc_skb(dev, rsv->len + NET_IP_ALIGN);
328 if (!skb) {
329 pr_err_ratelimited("RX: OOM: packet dropped\n");
330 dev->stats.rx_dropped++;
331 return -ENOMEM;
332 }
333 skb_reserve(skb, NET_IP_ALIGN);
334 encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len);
335
336 if (netif_msg_pktdata(priv))
337 dump_packet("RX", skb->len, skb->data);
338
339 skb->dev = dev;
340 skb->protocol = eth_type_trans(skb, dev);
341 skb->ip_summed = CHECKSUM_COMPLETE;
342
343 /* Maintain stats */
344 dev->stats.rx_packets++;
345 dev->stats.rx_bytes += rsv->len;
346 priv->next_packet = rsv->next_packet;
347
348 netif_rx(skb);
349
350 return 0;
351}
352
353static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count)
354{
355 struct net_device *dev = priv->ndev;
356
357 while (packet_count--) {
358 struct rsv rsv;
359 u16 newrxtail;
360
361 encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
362 encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv));
363
364 if (netif_msg_rx_status(priv))
365 encx24j600_dump_rsv(priv, __func__, &rsv);
366
367 if (!RSV_GETBIT(rsv.rxstat, RSV_RXOK) ||
368 (rsv.len > MAX_FRAMELEN)) {
369 netif_err(priv, rx_err, dev, "RX Error %04x\n",
370 rsv.rxstat);
371 dev->stats.rx_errors++;
372
373 if (RSV_GETBIT(rsv.rxstat, RSV_CRCERROR))
374 dev->stats.rx_crc_errors++;
375 if (RSV_GETBIT(rsv.rxstat, RSV_LENCHECKERR))
376 dev->stats.rx_frame_errors++;
377 if (rsv.len > MAX_FRAMELEN)
378 dev->stats.rx_over_errors++;
379 } else {
380 encx24j600_receive_packet(priv, &rsv);
381 }
382
383 newrxtail = priv->next_packet - 2;
384 if (newrxtail == ENC_RX_BUF_START)
385 newrxtail = SRAM_SIZE - 2;
386
387 encx24j600_cmd(priv, SETPKTDEC);
388 encx24j600_write_reg(priv, ERXTAIL, newrxtail);
389 }
390}
391
392static irqreturn_t encx24j600_isr(int irq, void *dev_id)
393{
394 struct encx24j600_priv *priv = dev_id;
395 struct net_device *dev = priv->ndev;
396 int eir;
397
398 /* Clear interrupts */
399 encx24j600_cmd(priv, CLREIE);
400
401 eir = encx24j600_read_reg(priv, EIR);
402
403 if (eir & LINKIF)
404 encx24j600_int_link_handler(priv);
405
406 if (eir & TXIF)
407 encx24j600_tx_complete(priv, false);
408
409 if (eir & TXABTIF)
410 encx24j600_tx_complete(priv, true);
411
412 if (eir & RXABTIF) {
413 if (eir & PCFULIF) {
414 /* Packet counter is full */
415 netif_err(priv, rx_err, dev, "Packet counter full\n");
416 }
417 dev->stats.rx_dropped++;
418 encx24j600_clr_bits(priv, EIR, RXABTIF);
419 }
420
421 if (eir & PKTIF) {
422 u8 packet_count;
423
424 mutex_lock(&priv->lock);
425
426 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
427 while (packet_count) {
428 encx24j600_rx_packets(priv, packet_count);
429 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
430 }
431
432 mutex_unlock(&priv->lock);
433 }
434
435 /* Enable interrupts */
436 encx24j600_cmd(priv, SETEIE);
437
438 return IRQ_HANDLED;
439}
440
441static int encx24j600_soft_reset(struct encx24j600_priv *priv)
442{
443 int ret = 0;
444 int timeout;
445 u16 eudast;
446
447 /* Write and verify a test value to EUDAST */
448 regcache_cache_bypass(priv->ctx.regmap, true);
449 timeout = 10;
450 do {
451 encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
452 eudast = encx24j600_read_reg(priv, EUDAST);
453 usleep_range(25, 100);
454 } while ((eudast != EUDAST_TEST_VAL) && --timeout);
455 regcache_cache_bypass(priv->ctx.regmap, false);
456
457 if (timeout == 0) {
458 ret = -ETIMEDOUT;
459 goto err_out;
460 }
461
462 /* Wait for CLKRDY to become set */
463 timeout = 10;
464 while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout)
465 usleep_range(25, 100);
466
467 if (timeout == 0) {
468 ret = -ETIMEDOUT;
469 goto err_out;
470 }
471
472 /* Issue a System Reset command */
473 encx24j600_cmd(priv, SETETHRST);
474 usleep_range(25, 100);
475
476 /* Confirm that EUDAST has 0000h after system reset */
477 if (encx24j600_read_reg(priv, EUDAST) != 0) {
478 ret = -EINVAL;
479 goto err_out;
480 }
481
482 /* Wait for PHY register and status bits to become available */
483 usleep_range(256, 1000);
484
485err_out:
486 return ret;
487}
488
489static int encx24j600_hw_reset(struct encx24j600_priv *priv)
490{
491 int ret;
492
493 mutex_lock(&priv->lock);
494 ret = encx24j600_soft_reset(priv);
495 mutex_unlock(&priv->lock);
496
497 return ret;
498}
499
500static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv)
501{
502 encx24j600_set_bits(priv, ECON2, TXRST);
503 encx24j600_clr_bits(priv, ECON2, TXRST);
504}
505
506static void encx24j600_hw_init_tx(struct encx24j600_priv *priv)
507{
508 /* Reset TX */
509 encx24j600_reset_hw_tx(priv);
510
511 /* Clear the TXIF flag if were previously set */
512 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
513
514 /* Write the Tx Buffer pointer */
515 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
516}
517
518static void encx24j600_hw_init_rx(struct encx24j600_priv *priv)
519{
520 encx24j600_cmd(priv, DISABLERX);
521
522 /* Set up RX packet start address in the SRAM */
523 encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
524
525 /* Preload the RX Data pointer to the beginning of the RX area */
526 encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
527
528 priv->next_packet = ENC_RX_BUF_START;
529
530 /* Set up RX end address in the SRAM */
531 encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
532
533 /* Reset the user data pointers */
534 encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
535 encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
536
537 /* Set Max Frame length */
538 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
539}
540
541static void encx24j600_dump_config(struct encx24j600_priv *priv,
542 const char *msg)
543{
544 pr_info(DRV_NAME ": %s\n", msg);
545
546 /* CHIP configuration */
547 pr_info(DRV_NAME " ECON1: %04X\n", encx24j600_read_reg(priv, ECON1));
548 pr_info(DRV_NAME " ECON2: %04X\n", encx24j600_read_reg(priv, ECON2));
549 pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv,
550 ERXFCON));
551 pr_info(DRV_NAME " ESTAT: %04X\n", encx24j600_read_reg(priv, ESTAT));
552 pr_info(DRV_NAME " EIR: %04X\n", encx24j600_read_reg(priv, EIR));
553 pr_info(DRV_NAME " EIDLED: %04X\n", encx24j600_read_reg(priv, EIDLED));
554
555 /* MAC layer configuration */
556 pr_info(DRV_NAME " MACON1: %04X\n", encx24j600_read_reg(priv, MACON1));
557 pr_info(DRV_NAME " MACON2: %04X\n", encx24j600_read_reg(priv, MACON2));
558 pr_info(DRV_NAME " MAIPG: %04X\n", encx24j600_read_reg(priv, MAIPG));
559 pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv,
560 MACLCON));
561 pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv,
562 MABBIPG));
563
564 /* PHY configuation */
565 pr_info(DRV_NAME " PHCON1: %04X\n", encx24j600_read_phy(priv, PHCON1));
566 pr_info(DRV_NAME " PHCON2: %04X\n", encx24j600_read_phy(priv, PHCON2));
567 pr_info(DRV_NAME " PHANA: %04X\n", encx24j600_read_phy(priv, PHANA));
568 pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv,
569 PHANLPA));
570 pr_info(DRV_NAME " PHANE: %04X\n", encx24j600_read_phy(priv, PHANE));
571 pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv,
572 PHSTAT1));
573 pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv,
574 PHSTAT2));
575 pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv,
576 PHSTAT3));
577}
578
579static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv)
580{
581 switch (priv->rxfilter) {
582 case RXFILTER_PROMISC:
583 encx24j600_set_bits(priv, MACON1, PASSALL);
584 encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
585 break;
586 case RXFILTER_MULTI:
587 encx24j600_clr_bits(priv, MACON1, PASSALL);
588 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
589 break;
590 case RXFILTER_NORMAL:
591 default:
592 encx24j600_clr_bits(priv, MACON1, PASSALL);
593 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
594 break;
595 }
596}
597
598static int encx24j600_hw_init(struct encx24j600_priv *priv)
599{
600 struct net_device *dev = priv->ndev;
601 int ret = 0;
602 u16 eidled;
603 u16 macon2;
604
605 priv->hw_enabled = false;
606
607 eidled = encx24j600_read_reg(priv, EIDLED);
608 if (((eidled & DEVID_MASK) >> DEVID_SHIFT) != ENCX24J600_DEV_ID) {
609 ret = -EINVAL;
610 goto err_out;
611 }
612
613 netif_info(priv, drv, dev, "Silicon rev ID: 0x%02x\n",
614 (eidled & REVID_MASK) >> REVID_SHIFT);
615
616 /* PHY Leds: link status,
617 * LEDA: Link + transmit/receive events
618 * LEDB: Link State + colision events
619 */
620 encx24j600_update_reg(priv, EIDLED, 0xbc00, 0xbc00);
621
622 /* Loopback disabled */
623 encx24j600_write_reg(priv, MACON1, 0x9);
624
625 /* interpacket gap value */
626 encx24j600_write_reg(priv, MAIPG, 0x0c12);
627
628 /* Write the auto negotiation pattern */
629 encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT);
630
631 encx24j600_update_phcon1(priv);
632 encx24j600_check_link_status(priv);
633
634 macon2 = MACON2_RSV1 | TXCRCEN | PADCFG0 | PADCFG2 | MACON2_DEFER;
635 if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex)
636 macon2 |= FULDPX;
637
638 encx24j600_set_bits(priv, MACON2, macon2);
639
640 priv->rxfilter = RXFILTER_NORMAL;
641 encx24j600_set_rxfilter_mode(priv);
642
643 /* Program the Maximum frame length */
644 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
645
646 /* Init Tx pointers */
647 encx24j600_hw_init_tx(priv);
648
649 /* Init Rx pointers */
650 encx24j600_hw_init_rx(priv);
651
652 if (netif_msg_hw(priv))
653 encx24j600_dump_config(priv, "Hw is initialized");
654
655err_out:
656 return ret;
657}
658
659static void encx24j600_hw_enable(struct encx24j600_priv *priv)
660{
661 /* Clear the interrupt flags in case was set */
662 encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
663 PKTIF | LINKIF));
664
665 /* Enable the interrupts */
666 encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
667 PKTIE | LINKIE | INTIE));
668
669 /* Enable RX */
670 encx24j600_cmd(priv, ENABLERX);
671
672 priv->hw_enabled = true;
673}
674
675static void encx24j600_hw_disable(struct encx24j600_priv *priv)
676{
677 /* Disable all interrupts */
678 encx24j600_write_reg(priv, EIE, 0);
679
680 /* Disable RX */
681 encx24j600_cmd(priv, DISABLERX);
682
683 priv->hw_enabled = false;
684}
685
686static int encx24j600_setlink(struct net_device *dev, u8 autoneg, u16 speed,
687 u8 duplex)
688{
689 struct encx24j600_priv *priv = netdev_priv(dev);
690 int ret = 0;
691
692 if (!priv->hw_enabled) {
693 /* link is in low power mode now; duplex setting
694 * will take effect on next encx24j600_hw_init()
695 */
696 if (speed == SPEED_10 || speed == SPEED_100) {
697 priv->autoneg = (autoneg == AUTONEG_ENABLE);
698 priv->full_duplex = (duplex == DUPLEX_FULL);
699 priv->speed = (speed == SPEED_100);
700 } else {
701 netif_warn(priv, link, dev, "unsupported link speed setting\n");
702 /*speeds other than SPEED_10 and SPEED_100 */
703 /*are not supported by chip */
704 ret = -EOPNOTSUPP;
705 }
706 } else {
707 netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n");
708 ret = -EBUSY;
709 }
710 return ret;
711}
712
713static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv,
714 unsigned char *ethaddr)
715{
716 unsigned short val;
717
718 val = encx24j600_read_reg(priv, MAADR1);
719
720 ethaddr[0] = val & 0x00ff;
721 ethaddr[1] = (val & 0xff00) >> 8;
722
723 val = encx24j600_read_reg(priv, MAADR2);
724
725 ethaddr[2] = val & 0x00ffU;
726 ethaddr[3] = (val & 0xff00U) >> 8;
727
728 val = encx24j600_read_reg(priv, MAADR3);
729
730 ethaddr[4] = val & 0x00ffU;
731 ethaddr[5] = (val & 0xff00U) >> 8;
732}
733
734/* Program the hardware MAC address from dev->dev_addr.*/
735static int encx24j600_set_hw_macaddr(struct net_device *dev)
736{
737 struct encx24j600_priv *priv = netdev_priv(dev);
738
739 if (priv->hw_enabled) {
740 netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n");
741 return -EBUSY;
742 }
743
744 mutex_lock(&priv->lock);
745
746 netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n",
747 dev->name, dev->dev_addr);
748
749 encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
750 dev->dev_addr[5] << 8));
751 encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
752 dev->dev_addr[3] << 8));
753 encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
754 dev->dev_addr[1] << 8));
755
756 mutex_unlock(&priv->lock);
757
758 return 0;
759}
760
761/* Store the new hardware address in dev->dev_addr, and update the MAC.*/
762static int encx24j600_set_mac_address(struct net_device *dev, void *addr)
763{
764 struct sockaddr *address = addr;
765
766 if (netif_running(dev))
767 return -EBUSY;
768 if (!is_valid_ether_addr(address->sa_data))
769 return -EADDRNOTAVAIL;
770
771 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
772 return encx24j600_set_hw_macaddr(dev);
773}
774
775static int encx24j600_open(struct net_device *dev)
776{
777 struct encx24j600_priv *priv = netdev_priv(dev);
778
779 int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr,
780 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
781 DRV_NAME, priv);
782 if (unlikely(ret < 0)) {
783 netdev_err(dev, "request irq %d failed (ret = %d)\n",
784 priv->ctx.spi->irq, ret);
785 return ret;
786 }
787
788 encx24j600_hw_disable(priv);
789 encx24j600_hw_init(priv);
790 encx24j600_hw_enable(priv);
791 netif_start_queue(dev);
792
793 return 0;
794}
795
796static int encx24j600_stop(struct net_device *dev)
797{
798 struct encx24j600_priv *priv = netdev_priv(dev);
799
800 netif_stop_queue(dev);
801 free_irq(priv->ctx.spi->irq, priv);
802 return 0;
803}
804
805static void encx24j600_setrx_proc(struct kthread_work *ws)
806{
807 struct encx24j600_priv *priv =
808 container_of(ws, struct encx24j600_priv, setrx_work);
809
810 mutex_lock(&priv->lock);
811 encx24j600_set_rxfilter_mode(priv);
812 mutex_unlock(&priv->lock);
813}
814
815static void encx24j600_set_multicast_list(struct net_device *dev)
816{
817 struct encx24j600_priv *priv = netdev_priv(dev);
818 int oldfilter = priv->rxfilter;
819
820 if (dev->flags & IFF_PROMISC) {
821 netif_dbg(priv, link, dev, "promiscuous mode\n");
822 priv->rxfilter = RXFILTER_PROMISC;
823 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
824 netif_dbg(priv, link, dev, "%smulticast mode\n",
825 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
826 priv->rxfilter = RXFILTER_MULTI;
827 } else {
828 netif_dbg(priv, link, dev, "normal mode\n");
829 priv->rxfilter = RXFILTER_NORMAL;
830 }
831
832 if (oldfilter != priv->rxfilter)
833 queue_kthread_work(&priv->kworker, &priv->setrx_work);
834}
835
836static void encx24j600_hw_tx(struct encx24j600_priv *priv)
837{
838 struct net_device *dev = priv->ndev;
839 netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n",
840 priv->tx_skb->len);
841
842 if (netif_msg_pktdata(priv))
843 dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data);
844
845 if (encx24j600_read_reg(priv, EIR) & TXABTIF)
846 /* Last transmition aborted due to error. Reset TX interface */
847 encx24j600_reset_hw_tx(priv);
848
849 /* Clear the TXIF flag if were previously set */
850 encx24j600_clr_bits(priv, EIR, TXIF);
851
852 /* Set the data pointer to the TX buffer address in the SRAM */
853 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
854
855 /* Copy the packet into the SRAM */
856 encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data,
857 priv->tx_skb->len);
858
859 /* Program the Tx buffer start pointer */
860 encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
861
862 /* Program the packet length */
863 encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);
864
865 /* Start the transmission */
866 encx24j600_cmd(priv, SETTXRTS);
867}
868
869static void encx24j600_tx_proc(struct kthread_work *ws)
870{
871 struct encx24j600_priv *priv =
872 container_of(ws, struct encx24j600_priv, tx_work);
873
874 mutex_lock(&priv->lock);
875 encx24j600_hw_tx(priv);
876 mutex_unlock(&priv->lock);
877}
878
879static netdev_tx_t encx24j600_tx(struct sk_buff *skb, struct net_device *dev)
880{
881 struct encx24j600_priv *priv = netdev_priv(dev);
882
883 netif_stop_queue(dev);
884
885 /* save the timestamp */
886 dev->trans_start = jiffies;
887
888 /* Remember the skb for deferred processing */
889 priv->tx_skb = skb;
890
891 queue_kthread_work(&priv->kworker, &priv->tx_work);
892
893 return NETDEV_TX_OK;
894}
895
896/* Deal with a transmit timeout */
897static void encx24j600_tx_timeout(struct net_device *dev)
898{
899 struct encx24j600_priv *priv = netdev_priv(dev);
900
901 netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n",
902 jiffies, jiffies - dev->trans_start);
903
904 dev->stats.tx_errors++;
905 netif_wake_queue(dev);
906 return;
907}
908
909static int encx24j600_get_regs_len(struct net_device *dev)
910{
911 return SFR_REG_COUNT;
912}
913
914static void encx24j600_get_regs(struct net_device *dev,
915 struct ethtool_regs *regs, void *p)
916{
917 struct encx24j600_priv *priv = netdev_priv(dev);
918 u16 *buff = p;
919 u8 reg;
920
921 regs->version = 1;
922 mutex_lock(&priv->lock);
923 for (reg = 0; reg < SFR_REG_COUNT; reg += 2) {
924 unsigned int val = 0;
925 /* ignore errors for unreadable registers */
926 regmap_read(priv->ctx.regmap, reg, &val);
927 buff[reg] = val & 0xffff;
928 }
929 mutex_unlock(&priv->lock);
930}
931
932static void encx24j600_get_drvinfo(struct net_device *dev,
933 struct ethtool_drvinfo *info)
934{
935 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
936 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
937 strlcpy(info->bus_info, dev_name(dev->dev.parent),
938 sizeof(info->bus_info));
939}
940
941static int encx24j600_get_settings(struct net_device *dev,
942 struct ethtool_cmd *cmd)
943{
944 struct encx24j600_priv *priv = netdev_priv(dev);
945
946 cmd->transceiver = XCVR_INTERNAL;
947 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
948 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
949 SUPPORTED_Autoneg | SUPPORTED_TP;
950
951 ethtool_cmd_speed_set(cmd, priv->speed);
952 cmd->duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
953 cmd->port = PORT_TP;
954 cmd->autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
955
956 return 0;
957}
958
959static int encx24j600_set_settings(struct net_device *dev,
960 struct ethtool_cmd *cmd)
961{
962 return encx24j600_setlink(dev, cmd->autoneg,
963 ethtool_cmd_speed(cmd), cmd->duplex);
964}
965
966static u32 encx24j600_get_msglevel(struct net_device *dev)
967{
968 struct encx24j600_priv *priv = netdev_priv(dev);
969 return priv->msg_enable;
970}
971
972static void encx24j600_set_msglevel(struct net_device *dev, u32 val)
973{
974 struct encx24j600_priv *priv = netdev_priv(dev);
975 priv->msg_enable = val;
976}
977
978static const struct ethtool_ops encx24j600_ethtool_ops = {
979 .get_settings = encx24j600_get_settings,
980 .set_settings = encx24j600_set_settings,
981 .get_drvinfo = encx24j600_get_drvinfo,
982 .get_msglevel = encx24j600_get_msglevel,
983 .set_msglevel = encx24j600_set_msglevel,
984 .get_regs_len = encx24j600_get_regs_len,
985 .get_regs = encx24j600_get_regs,
986};
987
988static const struct net_device_ops encx24j600_netdev_ops = {
989 .ndo_open = encx24j600_open,
990 .ndo_stop = encx24j600_stop,
991 .ndo_start_xmit = encx24j600_tx,
992 .ndo_set_rx_mode = encx24j600_set_multicast_list,
993 .ndo_set_mac_address = encx24j600_set_mac_address,
994 .ndo_tx_timeout = encx24j600_tx_timeout,
995 .ndo_validate_addr = eth_validate_addr,
996};
997
998static int encx24j600_spi_probe(struct spi_device *spi)
999{
1000 int ret;
1001
1002 struct net_device *ndev;
1003 struct encx24j600_priv *priv;
1004
1005 ndev = alloc_etherdev(sizeof(struct encx24j600_priv));
1006
1007 if (!ndev) {
1008 ret = -ENOMEM;
1009 goto error_out;
1010 }
1011
1012 priv = netdev_priv(ndev);
1013 spi_set_drvdata(spi, priv);
1014 dev_set_drvdata(&spi->dev, priv);
1015 SET_NETDEV_DEV(ndev, &spi->dev);
1016
1017 priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1018 priv->ndev = ndev;
1019
1020 /* Default configuration PHY configuration */
1021 priv->full_duplex = true;
1022 priv->autoneg = AUTONEG_ENABLE;
1023 priv->speed = SPEED_100;
1024
1025 priv->ctx.spi = spi;
1026 devm_regmap_init_encx24j600(&spi->dev, &priv->ctx);
1027 ndev->irq = spi->irq;
1028 ndev->netdev_ops = &encx24j600_netdev_ops;
1029
1030 mutex_init(&priv->lock);
1031
1032 /* Reset device and check if it is connected */
1033 if (encx24j600_hw_reset(priv)) {
1034 netif_err(priv, probe, ndev,
1035 DRV_NAME ": Chip is not detected\n");
1036 ret = -EIO;
1037 goto out_free;
1038 }
1039
1040 /* Initialize the device HW to the consistent state */
1041 if (encx24j600_hw_init(priv)) {
1042 netif_err(priv, probe, ndev,
1043 DRV_NAME ": HW initialization error\n");
1044 ret = -EIO;
1045 goto out_free;
1046 }
1047
1048 init_kthread_worker(&priv->kworker);
1049 init_kthread_work(&priv->tx_work, encx24j600_tx_proc);
1050 init_kthread_work(&priv->setrx_work, encx24j600_setrx_proc);
1051
1052 priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker,
1053 "encx24j600");
1054
1055 if (IS_ERR(priv->kworker_task)) {
1056 ret = PTR_ERR(priv->kworker_task);
1057 goto out_free;
1058 }
1059
1060 /* Get the MAC address from the chip */
1061 encx24j600_hw_get_macaddr(priv, ndev->dev_addr);
1062
1063 ndev->ethtool_ops = &encx24j600_ethtool_ops;
1064
1065 ret = register_netdev(ndev);
1066 if (unlikely(ret)) {
1067 netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n",
1068 ret);
1069 goto out_free;
1070 }
1071
1072 netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr);
1073
1074 return ret;
1075
1076out_free:
1077 free_netdev(ndev);
1078
1079error_out:
1080 return ret;
1081}
1082
1083static int encx24j600_spi_remove(struct spi_device *spi)
1084{
1085 struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev);
1086
1087 unregister_netdev(priv->ndev);
1088
1089 free_netdev(priv->ndev);
1090
1091 return 0;
1092}
1093
1094static const struct spi_device_id encx24j600_spi_id_table = {
1095 .name = "encx24j600"
1096};
1097
1098static struct spi_driver encx24j600_spi_net_driver = {
1099 .driver = {
1100 .name = DRV_NAME,
1101 .owner = THIS_MODULE,
1102 .bus = &spi_bus_type,
1103 },
1104 .probe = encx24j600_spi_probe,
1105 .remove = encx24j600_spi_remove,
1106 .id_table = &encx24j600_spi_id_table,
1107};
1108
1109static int __init encx24j600_init(void)
1110{
1111 return spi_register_driver(&encx24j600_spi_net_driver);
1112}
1113module_init(encx24j600_init);
1114
9886ce2b 1115static void encx24j600_exit(void)
04fbfce7
JR		 1116{
1117 spi_unregister_driver(&encx24j600_spi_net_driver);
1118}
1119module_exit(encx24j600_exit);
1120
1121MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1122MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1123MODULE_LICENSE("GPL");
1124MODULE_ALIAS("spi:" DRV_NAME);
Linux 6.x block layer and io_uring tree(s)