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mlxsw: reg: Add Switch Virtual-Port Enabling register definition
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlxsw / reg.h
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4ec14b76
IS		 1/*
2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef _MLXSW_REG_H
38#define _MLXSW_REG_H
39
40#include <linux/string.h>
41#include <linux/bitops.h>
42#include <linux/if_vlan.h>
43
44#include "item.h"
45#include "port.h"
46
47struct mlxsw_reg_info {
48 u16 id;
49 u16 len; /* In u8 */
50};
51
52#define MLXSW_REG(type) (&mlxsw_reg_##type)
53#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
54#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
55
56/* SGCR - Switch General Configuration Register
57 * --------------------------------------------
58 * This register is used for configuration of the switch capabilities.
59 */
60#define MLXSW_REG_SGCR_ID 0x2000
61#define MLXSW_REG_SGCR_LEN 0x10
62
63static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
64 .id = MLXSW_REG_SGCR_ID,
65 .len = MLXSW_REG_SGCR_LEN,
66};
67
68/* reg_sgcr_llb
69 * Link Local Broadcast (Default=0)
70 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
71 * packets and ignore the IGMP snooping entries.
72 * Access: RW
73 */
74MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
75
76static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
77{
78 MLXSW_REG_ZERO(sgcr, payload);
79 mlxsw_reg_sgcr_llb_set(payload, !!llb);
80}
81
82/* SPAD - Switch Physical Address Register
83 * ---------------------------------------
84 * The SPAD register configures the switch physical MAC address.
85 */
86#define MLXSW_REG_SPAD_ID 0x2002
87#define MLXSW_REG_SPAD_LEN 0x10
88
89static const struct mlxsw_reg_info mlxsw_reg_spad = {
90 .id = MLXSW_REG_SPAD_ID,
91 .len = MLXSW_REG_SPAD_LEN,
92};
93
94/* reg_spad_base_mac
95 * Base MAC address for the switch partitions.
96 * Per switch partition MAC address is equal to:
97 * base_mac + swid
98 * Access: RW
99 */
100MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
101
e61011b5
IS		 102/* SSPR - Switch System Port Record Register
103 * -----------------------------------------
104 * Configures the system port to local port mapping.
105 */
106#define MLXSW_REG_SSPR_ID 0x2008
107#define MLXSW_REG_SSPR_LEN 0x8
108
109static const struct mlxsw_reg_info mlxsw_reg_sspr = {
110 .id = MLXSW_REG_SSPR_ID,
111 .len = MLXSW_REG_SSPR_LEN,
112};
113
114/* reg_sspr_m
115 * Master - if set, then the record describes the master system port.
116 * This is needed in case a local port is mapped into several system ports
117 * (for multipathing). That number will be reported as the source system
118 * port when packets are forwarded to the CPU. Only one master port is allowed
119 * per local port.
120 *
121 * Note: Must be set for Spectrum.
122 * Access: RW
123 */
124MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
125
126/* reg_sspr_local_port
127 * Local port number.
128 *
129 * Access: RW
130 */
131MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
132
133/* reg_sspr_sub_port
134 * Virtual port within the physical port.
135 * Should be set to 0 when virtual ports are not enabled on the port.
136 *
137 * Access: RW
138 */
139MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
140
141/* reg_sspr_system_port
142 * Unique identifier within the stacking domain that represents all the ports
143 * that are available in the system (external ports).
144 *
145 * Currently, only single-ASIC configurations are supported, so we default to
146 * 1:1 mapping between system ports and local ports.
147 * Access: Index
148 */
149MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
150
151static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
152{
153 MLXSW_REG_ZERO(sspr, payload);
154 mlxsw_reg_sspr_m_set(payload, 1);
155 mlxsw_reg_sspr_local_port_set(payload, local_port);
156 mlxsw_reg_sspr_sub_port_set(payload, 0);
157 mlxsw_reg_sspr_system_port_set(payload, local_port);
158}
159
236033b3
JP		 160/* SFD - Switch Filtering Database
161 * -------------------------------
162 * The following register defines the access to the filtering database.
163 * The register supports querying, adding, removing and modifying the database.
164 * The access is optimized for bulk updates in which case more than one
165 * FDB record is present in the same command.
166 */
167#define MLXSW_REG_SFD_ID 0x200A
168#define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
169#define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
170#define MLXSW_REG_SFD_REC_MAX_COUNT 64
171#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
172 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
173
174static const struct mlxsw_reg_info mlxsw_reg_sfd = {
175 .id = MLXSW_REG_SFD_ID,
176 .len = MLXSW_REG_SFD_LEN,
177};
178
179/* reg_sfd_swid
180 * Switch partition ID for queries. Reserved on Write.
181 * Access: Index
182 */
183MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
184
185enum mlxsw_reg_sfd_op {
186 /* Dump entire FDB a (process according to record_locator) */
187 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
188 /* Query records by {MAC, VID/FID} value */
189 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
190 /* Query and clear activity. Query records by {MAC, VID/FID} value */
191 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
192 /* Test. Response indicates if each of the records could be
193 * added to the FDB.
194 */
195 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
196 /* Add/modify. Aged-out records cannot be added. This command removes
197 * the learning notification of the {MAC, VID/FID}. Response includes
198 * the entries that were added to the FDB.
199 */
200 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
201 /* Remove record by {MAC, VID/FID}. This command also removes
202 * the learning notification and aged-out notifications
203 * of the {MAC, VID/FID}. The response provides current (pre-removal)
204 * entries as non-aged-out.
205 */
206 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
207 /* Remove learned notification by {MAC, VID/FID}. The response provides
208 * the removed learning notification.
209 */
210 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
211};
212
213/* reg_sfd_op
214 * Operation.
215 * Access: OP
216 */
217MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
218
219/* reg_sfd_record_locator
220 * Used for querying the FDB. Use record_locator=0 to initiate the
221 * query. When a record is returned, a new record_locator is
222 * returned to be used in the subsequent query.
223 * Reserved for database update.
224 * Access: Index
225 */
226MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
227
228/* reg_sfd_num_rec
229 * Request: Number of records to read/add/modify/remove
230 * Response: Number of records read/added/replaced/removed
231 * See above description for more details.
232 * Ranges 0..64
233 * Access: RW
234 */
235MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
236
237static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
238 u32 record_locator)
239{
240 MLXSW_REG_ZERO(sfd, payload);
241 mlxsw_reg_sfd_op_set(payload, op);
242 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
243}
244
245/* reg_sfd_rec_swid
246 * Switch partition ID.
247 * Access: Index
248 */
249MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
250 MLXSW_REG_SFD_REC_LEN, 0x00, false);
251
252enum mlxsw_reg_sfd_rec_type {
253 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
254};
255
256/* reg_sfd_rec_type
257 * FDB record type.
258 * Access: RW
259 */
260MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
261 MLXSW_REG_SFD_REC_LEN, 0x00, false);
262
263enum mlxsw_reg_sfd_rec_policy {
264 /* Replacement disabled, aging disabled. */
265 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
266 /* (mlag remote): Replacement enabled, aging disabled,
267 * learning notification enabled on this port.
268 */
269 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
270 /* (ingress device): Replacement enabled, aging enabled. */
271 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
272};
273
274/* reg_sfd_rec_policy
275 * Policy.
276 * Access: RW
277 */
278MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
279 MLXSW_REG_SFD_REC_LEN, 0x00, false);
280
281/* reg_sfd_rec_a
282 * Activity. Set for new static entries. Set for static entries if a frame SMAC
283 * lookup hits on the entry.
284 * To clear the a bit, use "query and clear activity" op.
285 * Access: RO
286 */
287MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
288 MLXSW_REG_SFD_REC_LEN, 0x00, false);
289
290/* reg_sfd_rec_mac
291 * MAC address.
292 * Access: Index
293 */
294MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
295 MLXSW_REG_SFD_REC_LEN, 0x02);
296
297enum mlxsw_reg_sfd_rec_action {
298 /* forward */
299 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
300 /* forward and trap, trap_id is FDB_TRAP */
301 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
302 /* trap and do not forward, trap_id is FDB_TRAP */
303 MLXSW_REG_SFD_REC_ACTION_TRAP = 3,
304 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
305};
306
307/* reg_sfd_rec_action
308 * Action to apply on the packet.
309 * Note: Dynamic entries can only be configured with NOP action.
310 * Access: RW
311 */
312MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
313 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
314
315/* reg_sfd_uc_sub_port
316 * LAG sub port.
317 * Must be 0 if multichannel VEPA is not enabled.
318 * Access: RW
319 */
320MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
321 MLXSW_REG_SFD_REC_LEN, 0x08, false);
322
323/* reg_sfd_uc_fid_vid
324 * Filtering ID or VLAN ID
325 * For SwitchX and SwitchX-2:
326 * - Dynamic entries (policy 2,3) use FID
327 * - Static entries (policy 0) use VID
328 * - When independent learning is configured, VID=FID
329 * For Spectrum: use FID for both Dynamic and Static entries.
330 * VID should not be used.
331 * Access: Index
332 */
333MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
334 MLXSW_REG_SFD_REC_LEN, 0x08, false);
335
336/* reg_sfd_uc_system_port
337 * Unique port identifier for the final destination of the packet.
338 * Access: RW
339 */
340MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
341 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
342
343static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
344 enum mlxsw_reg_sfd_rec_policy policy,
345 const char *mac, u16 vid,
346 enum mlxsw_reg_sfd_rec_action action,
347 u8 local_port)
348{
349 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
350
351 if (rec_index >= num_rec)
352 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
353 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
354 mlxsw_reg_sfd_rec_type_set(payload, rec_index,
355 MLXSW_REG_SFD_REC_TYPE_UNICAST);
356 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
357 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
358 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
359 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, vid);
360 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
361 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
362}
363
364static inline void
365mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
366 char *mac, u16 *p_vid,
367 u8 *p_local_port)
368{
369 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
370 *p_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
371 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
372}
373
f5d88f58
JP		 374/* SFN - Switch FDB Notification Register
375 * -------------------------------------------
376 * The switch provides notifications on newly learned FDB entries and
377 * aged out entries. The notifications can be polled by software.
378 */
379#define MLXSW_REG_SFN_ID 0x200B
380#define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
381#define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
382#define MLXSW_REG_SFN_REC_MAX_COUNT 64
383#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
384 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
385
386static const struct mlxsw_reg_info mlxsw_reg_sfn = {
387 .id = MLXSW_REG_SFN_ID,
388 .len = MLXSW_REG_SFN_LEN,
389};
390
391/* reg_sfn_swid
392 * Switch partition ID.
393 * Access: Index
394 */
395MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
396
397/* reg_sfn_num_rec
398 * Request: Number of learned notifications and aged-out notification
399 * records requested.
400 * Response: Number of notification records returned (must be smaller
401 * than or equal to the value requested)
402 * Ranges 0..64
403 * Access: OP
404 */
405MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
406
407static inline void mlxsw_reg_sfn_pack(char *payload)
408{
409 MLXSW_REG_ZERO(sfn, payload);
410 mlxsw_reg_sfn_swid_set(payload, 0);
411 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
412}
413
414/* reg_sfn_rec_swid
415 * Switch partition ID.
416 * Access: RO
417 */
418MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
419 MLXSW_REG_SFN_REC_LEN, 0x00, false);
420
421enum mlxsw_reg_sfn_rec_type {
422 /* MAC addresses learned on a regular port. */
423 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
424 /* Aged-out MAC address on a regular port */
425 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
426};
427
428/* reg_sfn_rec_type
429 * Notification record type.
430 * Access: RO
431 */
432MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
433 MLXSW_REG_SFN_REC_LEN, 0x00, false);
434
435/* reg_sfn_rec_mac
436 * MAC address.
437 * Access: RO
438 */
439MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
440 MLXSW_REG_SFN_REC_LEN, 0x02);
441
442/* reg_sfd_mac_sub_port
443 * VEPA channel on the local port.
444 * 0 if multichannel VEPA is not enabled.
445 * Access: RO
446 */
447MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
448 MLXSW_REG_SFN_REC_LEN, 0x08, false);
449
450/* reg_sfd_mac_fid
451 * Filtering identifier.
452 * Access: RO
453 */
454MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
455 MLXSW_REG_SFN_REC_LEN, 0x08, false);
456
457/* reg_sfd_mac_system_port
458 * Unique port identifier for the final destination of the packet.
459 * Access: RO
460 */
461MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
462 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
463
464static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
465 char *mac, u16 *p_vid,
466 u8 *p_local_port)
467{
468 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
469 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
470 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
471}
472
4ec14b76
IS		 473/* SPMS - Switch Port MSTP/RSTP State Register
474 * -------------------------------------------
475 * Configures the spanning tree state of a physical port.
476 */
3f0effd1 477#define MLXSW_REG_SPMS_ID 0x200D
4ec14b76
IS		 478#define MLXSW_REG_SPMS_LEN 0x404
479
480static const struct mlxsw_reg_info mlxsw_reg_spms = {
481 .id = MLXSW_REG_SPMS_ID,
482 .len = MLXSW_REG_SPMS_LEN,
483};
484
485/* reg_spms_local_port
486 * Local port number.
487 * Access: Index
488 */
489MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
490
491enum mlxsw_reg_spms_state {
492 MLXSW_REG_SPMS_STATE_NO_CHANGE,
493 MLXSW_REG_SPMS_STATE_DISCARDING,
494 MLXSW_REG_SPMS_STATE_LEARNING,
495 MLXSW_REG_SPMS_STATE_FORWARDING,
496};
497
498/* reg_spms_state
499 * Spanning tree state of each VLAN ID (VID) of the local port.
500 * 0 - Do not change spanning tree state (used only when writing).
501 * 1 - Discarding. No learning or forwarding to/from this port (default).
502 * 2 - Learning. Port is learning, but not forwarding.
503 * 3 - Forwarding. Port is learning and forwarding.
504 * Access: RW
505 */
506MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
507
ebb7963f 508static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
4ec14b76
IS		 509{
510 MLXSW_REG_ZERO(spms, payload);
511 mlxsw_reg_spms_local_port_set(payload, local_port);
ebb7963f
JP		 512}
513
514static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
515 enum mlxsw_reg_spms_state state)
516{
4ec14b76
IS		 517 mlxsw_reg_spms_state_set(payload, vid, state);
518}
519
b2e345f9
ER		 520/* SPVID - Switch Port VID
521 * -----------------------
522 * The switch port VID configures the default VID for a port.
523 */
524#define MLXSW_REG_SPVID_ID 0x200E
525#define MLXSW_REG_SPVID_LEN 0x08
526
527static const struct mlxsw_reg_info mlxsw_reg_spvid = {
528 .id = MLXSW_REG_SPVID_ID,
529 .len = MLXSW_REG_SPVID_LEN,
530};
531
532/* reg_spvid_local_port
533 * Local port number.
534 * Access: Index
535 */
536MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
537
538/* reg_spvid_sub_port
539 * Virtual port within the physical port.
540 * Should be set to 0 when virtual ports are not enabled on the port.
541 * Access: Index
542 */
543MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
544
545/* reg_spvid_pvid
546 * Port default VID
547 * Access: RW
548 */
549MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
550
551static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
552{
553 MLXSW_REG_ZERO(spvid, payload);
554 mlxsw_reg_spvid_local_port_set(payload, local_port);
555 mlxsw_reg_spvid_pvid_set(payload, pvid);
556}
557
558/* SPVM - Switch Port VLAN Membership
559 * ----------------------------------
560 * The Switch Port VLAN Membership register configures the VLAN membership
561 * of a port in a VLAN denoted by VID. VLAN membership is managed per
562 * virtual port. The register can be used to add and remove VID(s) from a port.
563 */
564#define MLXSW_REG_SPVM_ID 0x200F
565#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
566#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
567#define MLXSW_REG_SPVM_REC_MAX_COUNT 256
568#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
569 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
570
571static const struct mlxsw_reg_info mlxsw_reg_spvm = {
572 .id = MLXSW_REG_SPVM_ID,
573 .len = MLXSW_REG_SPVM_LEN,
574};
575
576/* reg_spvm_pt
577 * Priority tagged. If this bit is set, packets forwarded to the port with
578 * untagged VLAN membership (u bit is set) will be tagged with priority tag
579 * (VID=0)
580 * Access: RW
581 */
582MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
583
584/* reg_spvm_pte
585 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
586 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
587 * Access: WO
588 */
589MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
590
591/* reg_spvm_local_port
592 * Local port number.
593 * Access: Index
594 */
595MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
596
597/* reg_spvm_sub_port
598 * Virtual port within the physical port.
599 * Should be set to 0 when virtual ports are not enabled on the port.
600 * Access: Index
601 */
602MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
603
604/* reg_spvm_num_rec
605 * Number of records to update. Each record contains: i, e, u, vid.
606 * Access: OP
607 */
608MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
609
610/* reg_spvm_rec_i
611 * Ingress membership in VLAN ID.
612 * Access: Index
613 */
614MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
615 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
616 MLXSW_REG_SPVM_REC_LEN, 0, false);
617
618/* reg_spvm_rec_e
619 * Egress membership in VLAN ID.
620 * Access: Index
621 */
622MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
623 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
624 MLXSW_REG_SPVM_REC_LEN, 0, false);
625
626/* reg_spvm_rec_u
627 * Untagged - port is an untagged member - egress transmission uses untagged
628 * frames on VID<n>
629 * Access: Index
630 */
631MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
632 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
633 MLXSW_REG_SPVM_REC_LEN, 0, false);
634
635/* reg_spvm_rec_vid
636 * Egress membership in VLAN ID.
637 * Access: Index
638 */
639MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
640 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
641 MLXSW_REG_SPVM_REC_LEN, 0, false);
642
643static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
644 u16 vid_begin, u16 vid_end,
645 bool is_member, bool untagged)
646{
647 int size = vid_end - vid_begin + 1;
648 int i;
649
650 MLXSW_REG_ZERO(spvm, payload);
651 mlxsw_reg_spvm_local_port_set(payload, local_port);
652 mlxsw_reg_spvm_num_rec_set(payload, size);
653
654 for (i = 0; i < size; i++) {
655 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
656 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
657 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
658 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
659 }
660}
661
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IS		 662/* SFGC - Switch Flooding Group Configuration
663 * ------------------------------------------
664 * The following register controls the association of flooding tables and MIDs
665 * to packet types used for flooding.
666 */
36b78e8a 667#define MLXSW_REG_SFGC_ID 0x2011
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IS		 668#define MLXSW_REG_SFGC_LEN 0x10
669
670static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
671 .id = MLXSW_REG_SFGC_ID,
672 .len = MLXSW_REG_SFGC_LEN,
673};
674
675enum mlxsw_reg_sfgc_type {
fa6ad058
IS		 676 MLXSW_REG_SFGC_TYPE_BROADCAST,
677 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
678 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
679 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
680 MLXSW_REG_SFGC_TYPE_RESERVED,
681 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
682 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
683 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
684 MLXSW_REG_SFGC_TYPE_MAX,
4ec14b76
IS		 685};
686
687/* reg_sfgc_type
688 * The traffic type to reach the flooding table.
689 * Access: Index
690 */
691MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
692
693enum mlxsw_reg_sfgc_bridge_type {
694 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
695 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
696};
697
698/* reg_sfgc_bridge_type
699 * Access: Index
700 *
701 * Note: SwitchX-2 only supports 802.1Q mode.
702 */
703MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
704
705enum mlxsw_flood_table_type {
706 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
707 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
708 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
709 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
710 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
711};
712
713/* reg_sfgc_table_type
714 * See mlxsw_flood_table_type
715 * Access: RW
716 *
717 * Note: FID offset and FID types are not supported in SwitchX-2.
718 */
719MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
720
721/* reg_sfgc_flood_table
722 * Flooding table index to associate with the specific type on the specific
723 * switch partition.
724 * Access: RW
725 */
726MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
727
728/* reg_sfgc_mid
729 * The multicast ID for the swid. Not supported for Spectrum
730 * Access: RW
731 */
732MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
733
734/* reg_sfgc_counter_set_type
735 * Counter Set Type for flow counters.
736 * Access: RW
737 */
738MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
739
740/* reg_sfgc_counter_index
741 * Counter Index for flow counters.
742 * Access: RW
743 */
744MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
745
746static inline void
747mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
748 enum mlxsw_reg_sfgc_bridge_type bridge_type,
749 enum mlxsw_flood_table_type table_type,
750 unsigned int flood_table)
751{
752 MLXSW_REG_ZERO(sfgc, payload);
753 mlxsw_reg_sfgc_type_set(payload, type);
754 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
755 mlxsw_reg_sfgc_table_type_set(payload, table_type);
756 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
757 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
758}
759
760/* SFTR - Switch Flooding Table Register
761 * -------------------------------------
762 * The switch flooding table is used for flooding packet replication. The table
763 * defines a bit mask of ports for packet replication.
764 */
765#define MLXSW_REG_SFTR_ID 0x2012
766#define MLXSW_REG_SFTR_LEN 0x420
767
768static const struct mlxsw_reg_info mlxsw_reg_sftr = {
769 .id = MLXSW_REG_SFTR_ID,
770 .len = MLXSW_REG_SFTR_LEN,
771};
772
773/* reg_sftr_swid
774 * Switch partition ID with which to associate the port.
775 * Access: Index
776 */
777MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
778
779/* reg_sftr_flood_table
780 * Flooding table index to associate with the specific type on the specific
781 * switch partition.
782 * Access: Index
783 */
784MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
785
786/* reg_sftr_index
787 * Index. Used as an index into the Flooding Table in case the table is
788 * configured to use VID / FID or FID Offset.
789 * Access: Index
790 */
791MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
792
793/* reg_sftr_table_type
794 * See mlxsw_flood_table_type
795 * Access: RW
796 */
797MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
798
799/* reg_sftr_range
800 * Range of entries to update
801 * Access: Index
802 */
803MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
804
805/* reg_sftr_port
806 * Local port membership (1 bit per port).
807 * Access: RW
808 */
809MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
810
811/* reg_sftr_cpu_port_mask
812 * CPU port mask (1 bit per port).
813 * Access: W
814 */
815MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
816
817static inline void mlxsw_reg_sftr_pack(char *payload,
818 unsigned int flood_table,
819 unsigned int index,
820 enum mlxsw_flood_table_type table_type,
bc2055f8 821 unsigned int range, u8 port, bool set)
4ec14b76
IS		 822{
823 MLXSW_REG_ZERO(sftr, payload);
824 mlxsw_reg_sftr_swid_set(payload, 0);
825 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
826 mlxsw_reg_sftr_index_set(payload, index);
827 mlxsw_reg_sftr_table_type_set(payload, table_type);
828 mlxsw_reg_sftr_range_set(payload, range);
bc2055f8
IS		 829 mlxsw_reg_sftr_port_set(payload, port, set);
830 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
4ec14b76
IS		 831}
832
833/* SPMLR - Switch Port MAC Learning Register
834 * -----------------------------------------
835 * Controls the Switch MAC learning policy per port.
836 */
837#define MLXSW_REG_SPMLR_ID 0x2018
838#define MLXSW_REG_SPMLR_LEN 0x8
839
840static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
841 .id = MLXSW_REG_SPMLR_ID,
842 .len = MLXSW_REG_SPMLR_LEN,
843};
844
845/* reg_spmlr_local_port
846 * Local port number.
847 * Access: Index
848 */
849MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
850
851/* reg_spmlr_sub_port
852 * Virtual port within the physical port.
853 * Should be set to 0 when virtual ports are not enabled on the port.
854 * Access: Index
855 */
856MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
857
858enum mlxsw_reg_spmlr_learn_mode {
859 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
860 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
861 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
862};
863
864/* reg_spmlr_learn_mode
865 * Learning mode on the port.
866 * 0 - Learning disabled.
867 * 2 - Learning enabled.
868 * 3 - Security mode.
869 *
870 * In security mode the switch does not learn MACs on the port, but uses the
871 * SMAC to see if it exists on another ingress port. If so, the packet is
872 * classified as a bad packet and is discarded unless the software registers
873 * to receive port security error packets usign HPKT.
874 */
875MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
876
877static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
878 enum mlxsw_reg_spmlr_learn_mode mode)
879{
880 MLXSW_REG_ZERO(spmlr, payload);
881 mlxsw_reg_spmlr_local_port_set(payload, local_port);
882 mlxsw_reg_spmlr_sub_port_set(payload, 0);
883 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
884}
885
64790239
IS		 886/* SVFA - Switch VID to FID Allocation Register
887 * --------------------------------------------
888 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
889 * virtualized ports.
890 */
891#define MLXSW_REG_SVFA_ID 0x201C
892#define MLXSW_REG_SVFA_LEN 0x10
893
894static const struct mlxsw_reg_info mlxsw_reg_svfa = {
895 .id = MLXSW_REG_SVFA_ID,
896 .len = MLXSW_REG_SVFA_LEN,
897};
898
899/* reg_svfa_swid
900 * Switch partition ID.
901 * Access: Index
902 */
903MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
904
905/* reg_svfa_local_port
906 * Local port number.
907 * Access: Index
908 *
909 * Note: Reserved for 802.1Q FIDs.
910 */
911MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
912
913enum mlxsw_reg_svfa_mt {
914 MLXSW_REG_SVFA_MT_VID_TO_FID,
915 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
916};
917
918/* reg_svfa_mapping_table
919 * Mapping table:
920 * 0 - VID to FID
921 * 1 - {Port, VID} to FID
922 * Access: Index
923 *
924 * Note: Reserved for SwitchX-2.
925 */
926MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
927
928/* reg_svfa_v
929 * Valid.
930 * Valid if set.
931 * Access: RW
932 *
933 * Note: Reserved for SwitchX-2.
934 */
935MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
936
937/* reg_svfa_fid
938 * Filtering ID.
939 * Access: RW
940 */
941MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
942
943/* reg_svfa_vid
944 * VLAN ID.
945 * Access: Index
946 */
947MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
948
949/* reg_svfa_counter_set_type
950 * Counter set type for flow counters.
951 * Access: RW
952 *
953 * Note: Reserved for SwitchX-2.
954 */
955MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
956
957/* reg_svfa_counter_index
958 * Counter index for flow counters.
959 * Access: RW
960 *
961 * Note: Reserved for SwitchX-2.
962 */
963MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
964
965static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
966 enum mlxsw_reg_svfa_mt mt, bool valid,
967 u16 fid, u16 vid)
968{
969 MLXSW_REG_ZERO(svfa, payload);
970 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
971 mlxsw_reg_svfa_swid_set(payload, 0);
972 mlxsw_reg_svfa_local_port_set(payload, local_port);
973 mlxsw_reg_svfa_mapping_table_set(payload, mt);
974 mlxsw_reg_svfa_v_set(payload, valid);
975 mlxsw_reg_svfa_fid_set(payload, fid);
976 mlxsw_reg_svfa_vid_set(payload, vid);
977}
978
1f65da74
IS		 979/* SVPE - Switch Virtual-Port Enabling Register
980 * --------------------------------------------
981 * Enables port virtualization.
982 */
983#define MLXSW_REG_SVPE_ID 0x201E
984#define MLXSW_REG_SVPE_LEN 0x4
985
986static const struct mlxsw_reg_info mlxsw_reg_svpe = {
987 .id = MLXSW_REG_SVPE_ID,
988 .len = MLXSW_REG_SVPE_LEN,
989};
990
991/* reg_svpe_local_port
992 * Local port number
993 * Access: Index
994 *
995 * Note: CPU port is not supported (uses VLAN mode only).
996 */
997MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
998
999/* reg_svpe_vp_en
1000 * Virtual port enable.
1001 * 0 - Disable, VLAN mode (VID to FID).
1002 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1003 * Access: RW
1004 */
1005MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1006
1007static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1008 bool enable)
1009{
1010 MLXSW_REG_ZERO(svpe, payload);
1011 mlxsw_reg_svpe_local_port_set(payload, local_port);
1012 mlxsw_reg_svpe_vp_en_set(payload, enable);
1013}
1014
f1fb693a
IS		 1015/* SFMR - Switch FID Management Register
1016 * -------------------------------------
1017 * Creates and configures FIDs.
1018 */
1019#define MLXSW_REG_SFMR_ID 0x201F
1020#define MLXSW_REG_SFMR_LEN 0x18
1021
1022static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1023 .id = MLXSW_REG_SFMR_ID,
1024 .len = MLXSW_REG_SFMR_LEN,
1025};
1026
1027enum mlxsw_reg_sfmr_op {
1028 MLXSW_REG_SFMR_OP_CREATE_FID,
1029 MLXSW_REG_SFMR_OP_DESTROY_FID,
1030};
1031
1032/* reg_sfmr_op
1033 * Operation.
1034 * 0 - Create or edit FID.
1035 * 1 - Destroy FID.
1036 * Access: WO
1037 */
1038MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1039
1040/* reg_sfmr_fid
1041 * Filtering ID.
1042 * Access: Index
1043 */
1044MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1045
1046/* reg_sfmr_fid_offset
1047 * FID offset.
1048 * Used to point into the flooding table selected by SFGC register if
1049 * the table is of type FID-Offset. Otherwise, this field is reserved.
1050 * Access: RW
1051 */
1052MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1053
1054/* reg_sfmr_vtfp
1055 * Valid Tunnel Flood Pointer.
1056 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1057 * Access: RW
1058 *
1059 * Note: Reserved for 802.1Q FIDs.
1060 */
1061MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1062
1063/* reg_sfmr_nve_tunnel_flood_ptr
1064 * Underlay Flooding and BC Pointer.
1065 * Used as a pointer to the first entry of the group based link lists of
1066 * flooding or BC entries (for NVE tunnels).
1067 * Access: RW
1068 */
1069MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1070
1071/* reg_sfmr_vv
1072 * VNI Valid.
1073 * If not set, then vni is reserved.
1074 * Access: RW
1075 *
1076 * Note: Reserved for 802.1Q FIDs.
1077 */
1078MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1079
1080/* reg_sfmr_vni
1081 * Virtual Network Identifier.
1082 * Access: RW
1083 *
1084 * Note: A given VNI can only be assigned to one FID.
1085 */
1086MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1087
1088static inline void mlxsw_reg_sfmr_pack(char *payload,
1089 enum mlxsw_reg_sfmr_op op, u16 fid,
1090 u16 fid_offset)
1091{
1092 MLXSW_REG_ZERO(sfmr, payload);
1093 mlxsw_reg_sfmr_op_set(payload, op);
1094 mlxsw_reg_sfmr_fid_set(payload, fid);
1095 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1096 mlxsw_reg_sfmr_vtfp_set(payload, false);
1097 mlxsw_reg_sfmr_vv_set(payload, false);
1098}
1099
4ec14b76
IS		 1100/* PMLP - Ports Module to Local Port Register
1101 * ------------------------------------------
1102 * Configures the assignment of modules to local ports.
1103 */
1104#define MLXSW_REG_PMLP_ID 0x5002
1105#define MLXSW_REG_PMLP_LEN 0x40
1106
1107static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1108 .id = MLXSW_REG_PMLP_ID,
1109 .len = MLXSW_REG_PMLP_LEN,
1110};
1111
1112/* reg_pmlp_rxtx
1113 * 0 - Tx value is used for both Tx and Rx.
1114 * 1 - Rx value is taken from a separte field.
1115 * Access: RW
1116 */
1117MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
1118
1119/* reg_pmlp_local_port
1120 * Local port number.
1121 * Access: Index
1122 */
1123MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
1124
1125/* reg_pmlp_width
1126 * 0 - Unmap local port.
1127 * 1 - Lane 0 is used.
1128 * 2 - Lanes 0 and 1 are used.
1129 * 4 - Lanes 0, 1, 2 and 3 are used.
1130 * Access: RW
1131 */
1132MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
1133
1134/* reg_pmlp_module
1135 * Module number.
1136 * Access: RW
1137 */
1138MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0, false);
1139
1140/* reg_pmlp_tx_lane
1141 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
1142 * Access: RW
1143 */
1144MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 16, false);
1145
1146/* reg_pmlp_rx_lane
1147 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
1148 * equal to Tx lane.
1149 * Access: RW
1150 */
1151MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 24, false);
1152
1153static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
1154{
1155 MLXSW_REG_ZERO(pmlp, payload);
1156 mlxsw_reg_pmlp_local_port_set(payload, local_port);
1157}
1158
1159/* PMTU - Port MTU Register
1160 * ------------------------
1161 * Configures and reports the port MTU.
1162 */
1163#define MLXSW_REG_PMTU_ID 0x5003
1164#define MLXSW_REG_PMTU_LEN 0x10
1165
1166static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
1167 .id = MLXSW_REG_PMTU_ID,
1168 .len = MLXSW_REG_PMTU_LEN,
1169};
1170
1171/* reg_pmtu_local_port
1172 * Local port number.
1173 * Access: Index
1174 */
1175MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
1176
1177/* reg_pmtu_max_mtu
1178 * Maximum MTU.
1179 * When port type (e.g. Ethernet) is configured, the relevant MTU is
1180 * reported, otherwise the minimum between the max_mtu of the different
1181 * types is reported.
1182 * Access: RO
1183 */
1184MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
1185
1186/* reg_pmtu_admin_mtu
1187 * MTU value to set port to. Must be smaller or equal to max_mtu.
1188 * Note: If port type is Infiniband, then port must be disabled, when its
1189 * MTU is set.
1190 * Access: RW
1191 */
1192MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
1193
1194/* reg_pmtu_oper_mtu
1195 * The actual MTU configured on the port. Packets exceeding this size
1196 * will be dropped.
1197 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
1198 * oper_mtu might be smaller than admin_mtu.
1199 * Access: RO
1200 */
1201MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
1202
1203static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
1204 u16 new_mtu)
1205{
1206 MLXSW_REG_ZERO(pmtu, payload);
1207 mlxsw_reg_pmtu_local_port_set(payload, local_port);
1208 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
1209 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
1210 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
1211}
1212
1213/* PTYS - Port Type and Speed Register
1214 * -----------------------------------
1215 * Configures and reports the port speed type.
1216 *
1217 * Note: When set while the link is up, the changes will not take effect
1218 * until the port transitions from down to up state.
1219 */
1220#define MLXSW_REG_PTYS_ID 0x5004
1221#define MLXSW_REG_PTYS_LEN 0x40
1222
1223static const struct mlxsw_reg_info mlxsw_reg_ptys = {
1224 .id = MLXSW_REG_PTYS_ID,
1225 .len = MLXSW_REG_PTYS_LEN,
1226};
1227
1228/* reg_ptys_local_port
1229 * Local port number.
1230 * Access: Index
1231 */
1232MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
1233
1234#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
1235
1236/* reg_ptys_proto_mask
1237 * Protocol mask. Indicates which protocol is used.
1238 * 0 - Infiniband.
1239 * 1 - Fibre Channel.
1240 * 2 - Ethernet.
1241 * Access: Index
1242 */
1243MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
1244
1245#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
1246#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
1247#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
1248#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
1249#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
1250#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
1251#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
1252#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
1253#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
1254#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
1255#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
1256#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
1257#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
1258#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
1259#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
1260#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
1261#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
1262#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
1263#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
1264#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
1265#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
1266#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
1267#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
1268#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
1269#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
1270#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
1271#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
1272
1273/* reg_ptys_eth_proto_cap
1274 * Ethernet port supported speeds and protocols.
1275 * Access: RO
1276 */
1277MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
1278
1279/* reg_ptys_eth_proto_admin
1280 * Speed and protocol to set port to.
1281 * Access: RW
1282 */
1283MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
1284
1285/* reg_ptys_eth_proto_oper
1286 * The current speed and protocol configured for the port.
1287 * Access: RO
1288 */
1289MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
1290
1291static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
1292 u32 proto_admin)
1293{
1294 MLXSW_REG_ZERO(ptys, payload);
1295 mlxsw_reg_ptys_local_port_set(payload, local_port);
1296 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
1297 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
1298}
1299
1300static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
1301 u32 *p_eth_proto_adm,
1302 u32 *p_eth_proto_oper)
1303{
1304 if (p_eth_proto_cap)
1305 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
1306 if (p_eth_proto_adm)
1307 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
1308 if (p_eth_proto_oper)
1309 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
1310}
1311
1312/* PPAD - Port Physical Address Register
1313 * -------------------------------------
1314 * The PPAD register configures the per port physical MAC address.
1315 */
1316#define MLXSW_REG_PPAD_ID 0x5005
1317#define MLXSW_REG_PPAD_LEN 0x10
1318
1319static const struct mlxsw_reg_info mlxsw_reg_ppad = {
1320 .id = MLXSW_REG_PPAD_ID,
1321 .len = MLXSW_REG_PPAD_LEN,
1322};
1323
1324/* reg_ppad_single_base_mac
1325 * 0: base_mac, local port should be 0 and mac[7:0] is
1326 * reserved. HW will set incremental
1327 * 1: single_mac - mac of the local_port
1328 * Access: RW
1329 */
1330MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
1331
1332/* reg_ppad_local_port
1333 * port number, if single_base_mac = 0 then local_port is reserved
1334 * Access: RW
1335 */
1336MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
1337
1338/* reg_ppad_mac
1339 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
1340 * If single_base_mac = 1 - the per port MAC address
1341 * Access: RW
1342 */
1343MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
1344
1345static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
1346 u8 local_port)
1347{
1348 MLXSW_REG_ZERO(ppad, payload);
1349 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
1350 mlxsw_reg_ppad_local_port_set(payload, local_port);
1351}
1352
1353/* PAOS - Ports Administrative and Operational Status Register
1354 * -----------------------------------------------------------
1355 * Configures and retrieves per port administrative and operational status.
1356 */
1357#define MLXSW_REG_PAOS_ID 0x5006
1358#define MLXSW_REG_PAOS_LEN 0x10
1359
1360static const struct mlxsw_reg_info mlxsw_reg_paos = {
1361 .id = MLXSW_REG_PAOS_ID,
1362 .len = MLXSW_REG_PAOS_LEN,
1363};
1364
1365/* reg_paos_swid
1366 * Switch partition ID with which to associate the port.
1367 * Note: while external ports uses unique local port numbers (and thus swid is
1368 * redundant), router ports use the same local port number where swid is the
1369 * only indication for the relevant port.
1370 * Access: Index
1371 */
1372MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
1373
1374/* reg_paos_local_port
1375 * Local port number.
1376 * Access: Index
1377 */
1378MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
1379
1380/* reg_paos_admin_status
1381 * Port administrative state (the desired state of the port):
1382 * 1 - Up.
1383 * 2 - Down.
1384 * 3 - Up once. This means that in case of link failure, the port won't go
1385 * into polling mode, but will wait to be re-enabled by software.
1386 * 4 - Disabled by system. Can only be set by hardware.
1387 * Access: RW
1388 */
1389MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
1390
1391/* reg_paos_oper_status
1392 * Port operational state (the current state):
1393 * 1 - Up.
1394 * 2 - Down.
1395 * 3 - Down by port failure. This means that the device will not let the
1396 * port up again until explicitly specified by software.
1397 * Access: RO
1398 */
1399MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
1400
1401/* reg_paos_ase
1402 * Admin state update enabled.
1403 * Access: WO
1404 */
1405MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
1406
1407/* reg_paos_ee
1408 * Event update enable. If this bit is set, event generation will be
1409 * updated based on the e field.
1410 * Access: WO
1411 */
1412MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
1413
1414/* reg_paos_e
1415 * Event generation on operational state change:
1416 * 0 - Do not generate event.
1417 * 1 - Generate Event.
1418 * 2 - Generate Single Event.
1419 * Access: RW
1420 */
1421MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
1422
1423static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
1424 enum mlxsw_port_admin_status status)
1425{
1426 MLXSW_REG_ZERO(paos, payload);
1427 mlxsw_reg_paos_swid_set(payload, 0);
1428 mlxsw_reg_paos_local_port_set(payload, local_port);
1429 mlxsw_reg_paos_admin_status_set(payload, status);
1430 mlxsw_reg_paos_oper_status_set(payload, 0);
1431 mlxsw_reg_paos_ase_set(payload, 1);
1432 mlxsw_reg_paos_ee_set(payload, 1);
1433 mlxsw_reg_paos_e_set(payload, 1);
1434}
1435
1436/* PPCNT - Ports Performance Counters Register
1437 * -------------------------------------------
1438 * The PPCNT register retrieves per port performance counters.
1439 */
1440#define MLXSW_REG_PPCNT_ID 0x5008
1441#define MLXSW_REG_PPCNT_LEN 0x100
1442
1443static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
1444 .id = MLXSW_REG_PPCNT_ID,
1445 .len = MLXSW_REG_PPCNT_LEN,
1446};
1447
1448/* reg_ppcnt_swid
1449 * For HCA: must be always 0.
1450 * Switch partition ID to associate port with.
1451 * Switch partitions are numbered from 0 to 7 inclusively.
1452 * Switch partition 254 indicates stacking ports.
1453 * Switch partition 255 indicates all switch partitions.
1454 * Only valid on Set() operation with local_port=255.
1455 * Access: Index
1456 */
1457MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
1458
1459/* reg_ppcnt_local_port
1460 * Local port number.
1461 * 255 indicates all ports on the device, and is only allowed
1462 * for Set() operation.
1463 * Access: Index
1464 */
1465MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
1466
1467/* reg_ppcnt_pnat
1468 * Port number access type:
1469 * 0 - Local port number
1470 * 1 - IB port number
1471 * Access: Index
1472 */
1473MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
1474
1475/* reg_ppcnt_grp
1476 * Performance counter group.
1477 * Group 63 indicates all groups. Only valid on Set() operation with
1478 * clr bit set.
1479 * 0x0: IEEE 802.3 Counters
1480 * 0x1: RFC 2863 Counters
1481 * 0x2: RFC 2819 Counters
1482 * 0x3: RFC 3635 Counters
1483 * 0x5: Ethernet Extended Counters
1484 * 0x8: Link Level Retransmission Counters
1485 * 0x10: Per Priority Counters
1486 * 0x11: Per Traffic Class Counters
1487 * 0x12: Physical Layer Counters
1488 * Access: Index
1489 */
1490MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
1491
1492/* reg_ppcnt_clr
1493 * Clear counters. Setting the clr bit will reset the counter value
1494 * for all counters in the counter group. This bit can be set
1495 * for both Set() and Get() operation.
1496 * Access: OP
1497 */
1498MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
1499
1500/* reg_ppcnt_prio_tc
1501 * Priority for counter set that support per priority, valid values: 0-7.
1502 * Traffic class for counter set that support per traffic class,
1503 * valid values: 0- cap_max_tclass-1 .
1504 * For HCA: cap_max_tclass is always 8.
1505 * Otherwise must be 0.
1506 * Access: Index
1507 */
1508MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
1509
1510/* reg_ppcnt_a_frames_transmitted_ok
1511 * Access: RO
1512 */
1513MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
1514 0x08 + 0x00, 0, 64);
1515
1516/* reg_ppcnt_a_frames_received_ok
1517 * Access: RO
1518 */
1519MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
1520 0x08 + 0x08, 0, 64);
1521
1522/* reg_ppcnt_a_frame_check_sequence_errors
1523 * Access: RO
1524 */
1525MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
1526 0x08 + 0x10, 0, 64);
1527
1528/* reg_ppcnt_a_alignment_errors
1529 * Access: RO
1530 */
1531MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
1532 0x08 + 0x18, 0, 64);
1533
1534/* reg_ppcnt_a_octets_transmitted_ok
1535 * Access: RO
1536 */
1537MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
1538 0x08 + 0x20, 0, 64);
1539
1540/* reg_ppcnt_a_octets_received_ok
1541 * Access: RO
1542 */
1543MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
1544 0x08 + 0x28, 0, 64);
1545
1546/* reg_ppcnt_a_multicast_frames_xmitted_ok
1547 * Access: RO
1548 */
1549MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
1550 0x08 + 0x30, 0, 64);
1551
1552/* reg_ppcnt_a_broadcast_frames_xmitted_ok
1553 * Access: RO
1554 */
1555MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
1556 0x08 + 0x38, 0, 64);
1557
1558/* reg_ppcnt_a_multicast_frames_received_ok
1559 * Access: RO
1560 */
1561MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
1562 0x08 + 0x40, 0, 64);
1563
1564/* reg_ppcnt_a_broadcast_frames_received_ok
1565 * Access: RO
1566 */
1567MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
1568 0x08 + 0x48, 0, 64);
1569
1570/* reg_ppcnt_a_in_range_length_errors
1571 * Access: RO
1572 */
1573MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
1574 0x08 + 0x50, 0, 64);
1575
1576/* reg_ppcnt_a_out_of_range_length_field
1577 * Access: RO
1578 */
1579MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
1580 0x08 + 0x58, 0, 64);
1581
1582/* reg_ppcnt_a_frame_too_long_errors
1583 * Access: RO
1584 */
1585MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
1586 0x08 + 0x60, 0, 64);
1587
1588/* reg_ppcnt_a_symbol_error_during_carrier
1589 * Access: RO
1590 */
1591MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
1592 0x08 + 0x68, 0, 64);
1593
1594/* reg_ppcnt_a_mac_control_frames_transmitted
1595 * Access: RO
1596 */
1597MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
1598 0x08 + 0x70, 0, 64);
1599
1600/* reg_ppcnt_a_mac_control_frames_received
1601 * Access: RO
1602 */
1603MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
1604 0x08 + 0x78, 0, 64);
1605
1606/* reg_ppcnt_a_unsupported_opcodes_received
1607 * Access: RO
1608 */
1609MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
1610 0x08 + 0x80, 0, 64);
1611
1612/* reg_ppcnt_a_pause_mac_ctrl_frames_received
1613 * Access: RO
1614 */
1615MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
1616 0x08 + 0x88, 0, 64);
1617
1618/* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
1619 * Access: RO
1620 */
1621MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
1622 0x08 + 0x90, 0, 64);
1623
1624static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port)
1625{
1626 MLXSW_REG_ZERO(ppcnt, payload);
1627 mlxsw_reg_ppcnt_swid_set(payload, 0);
1628 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
1629 mlxsw_reg_ppcnt_pnat_set(payload, 0);
1630 mlxsw_reg_ppcnt_grp_set(payload, 0);
1631 mlxsw_reg_ppcnt_clr_set(payload, 0);
1632 mlxsw_reg_ppcnt_prio_tc_set(payload, 0);
1633}
1634
e0594369
JP		 1635/* PBMC - Port Buffer Management Control Register
1636 * ----------------------------------------------
1637 * The PBMC register configures and retrieves the port packet buffer
1638 * allocation for different Prios, and the Pause threshold management.
1639 */
1640#define MLXSW_REG_PBMC_ID 0x500C
1641#define MLXSW_REG_PBMC_LEN 0x68
1642
1643static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
1644 .id = MLXSW_REG_PBMC_ID,
1645 .len = MLXSW_REG_PBMC_LEN,
1646};
1647
1648/* reg_pbmc_local_port
1649 * Local port number.
1650 * Access: Index
1651 */
1652MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
1653
1654/* reg_pbmc_xoff_timer_value
1655 * When device generates a pause frame, it uses this value as the pause
1656 * timer (time for the peer port to pause in quota-512 bit time).
1657 * Access: RW
1658 */
1659MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
1660
1661/* reg_pbmc_xoff_refresh
1662 * The time before a new pause frame should be sent to refresh the pause RW
1663 * state. Using the same units as xoff_timer_value above (in quota-512 bit
1664 * time).
1665 * Access: RW
1666 */
1667MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
1668
1669/* reg_pbmc_buf_lossy
1670 * The field indicates if the buffer is lossy.
1671 * 0 - Lossless
1672 * 1 - Lossy
1673 * Access: RW
1674 */
1675MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
1676
1677/* reg_pbmc_buf_epsb
1678 * Eligible for Port Shared buffer.
1679 * If epsb is set, packets assigned to buffer are allowed to insert the port
1680 * shared buffer.
1681 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
1682 * Access: RW
1683 */
1684MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
1685
1686/* reg_pbmc_buf_size
1687 * The part of the packet buffer array is allocated for the specific buffer.
1688 * Units are represented in cells.
1689 * Access: RW
1690 */
1691MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
1692
1693static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
1694 u16 xoff_timer_value, u16 xoff_refresh)
1695{
1696 MLXSW_REG_ZERO(pbmc, payload);
1697 mlxsw_reg_pbmc_local_port_set(payload, local_port);
1698 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
1699 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
1700}
1701
1702static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
1703 int buf_index,
1704 u16 size)
1705{
1706 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
1707 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
1708 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
1709}
1710
4ec14b76
IS		 1711/* PSPA - Port Switch Partition Allocation
1712 * ---------------------------------------
1713 * Controls the association of a port with a switch partition and enables
1714 * configuring ports as stacking ports.
1715 */
3f0effd1 1716#define MLXSW_REG_PSPA_ID 0x500D
4ec14b76
IS		 1717#define MLXSW_REG_PSPA_LEN 0x8
1718
1719static const struct mlxsw_reg_info mlxsw_reg_pspa = {
1720 .id = MLXSW_REG_PSPA_ID,
1721 .len = MLXSW_REG_PSPA_LEN,
1722};
1723
1724/* reg_pspa_swid
1725 * Switch partition ID.
1726 * Access: RW
1727 */
1728MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
1729
1730/* reg_pspa_local_port
1731 * Local port number.
1732 * Access: Index
1733 */
1734MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
1735
1736/* reg_pspa_sub_port
1737 * Virtual port within the local port. Set to 0 when virtual ports are
1738 * disabled on the local port.
1739 * Access: Index
1740 */
1741MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
1742
1743static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
1744{
1745 MLXSW_REG_ZERO(pspa, payload);
1746 mlxsw_reg_pspa_swid_set(payload, swid);
1747 mlxsw_reg_pspa_local_port_set(payload, local_port);
1748 mlxsw_reg_pspa_sub_port_set(payload, 0);
1749}
1750
1751/* HTGT - Host Trap Group Table
1752 * ----------------------------
1753 * Configures the properties for forwarding to CPU.
1754 */
1755#define MLXSW_REG_HTGT_ID 0x7002
1756#define MLXSW_REG_HTGT_LEN 0x100
1757
1758static const struct mlxsw_reg_info mlxsw_reg_htgt = {
1759 .id = MLXSW_REG_HTGT_ID,
1760 .len = MLXSW_REG_HTGT_LEN,
1761};
1762
1763/* reg_htgt_swid
1764 * Switch partition ID.
1765 * Access: Index
1766 */
1767MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
1768
1769#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
1770
1771/* reg_htgt_type
1772 * CPU path type.
1773 * Access: RW
1774 */
1775MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
1776
801bd3de
IS		 1777enum mlxsw_reg_htgt_trap_group {
1778 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1779 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1780 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
1781};
4ec14b76
IS		 1782
1783/* reg_htgt_trap_group
1784 * Trap group number. User defined number specifying which trap groups
1785 * should be forwarded to the CPU. The mapping between trap IDs and trap
1786 * groups is configured using HPKT register.
1787 * Access: Index
1788 */
1789MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
1790
1791enum {
1792 MLXSW_REG_HTGT_POLICER_DISABLE,
1793 MLXSW_REG_HTGT_POLICER_ENABLE,
1794};
1795
1796/* reg_htgt_pide
1797 * Enable policer ID specified using 'pid' field.
1798 * Access: RW
1799 */
1800MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
1801
1802/* reg_htgt_pid
1803 * Policer ID for the trap group.
1804 * Access: RW
1805 */
1806MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
1807
1808#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
1809
1810/* reg_htgt_mirror_action
1811 * Mirror action to use.
1812 * 0 - Trap to CPU.
1813 * 1 - Trap to CPU and mirror to a mirroring agent.
1814 * 2 - Mirror to a mirroring agent and do not trap to CPU.
1815 * Access: RW
1816 *
1817 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
1818 */
1819MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
1820
1821/* reg_htgt_mirroring_agent
1822 * Mirroring agent.
1823 * Access: RW
1824 */
1825MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
1826
1827/* reg_htgt_priority
1828 * Trap group priority.
1829 * In case a packet matches multiple classification rules, the packet will
1830 * only be trapped once, based on the trap ID associated with the group (via
1831 * register HPKT) with the highest priority.
1832 * Supported values are 0-7, with 7 represnting the highest priority.
1833 * Access: RW
1834 *
1835 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
1836 * by the 'trap_group' field.
1837 */
1838MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
1839
1840/* reg_htgt_local_path_cpu_tclass
1841 * CPU ingress traffic class for the trap group.
1842 * Access: RW
1843 */
1844MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
1845
1846#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
1847#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
801bd3de 1848#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
4ec14b76
IS		 1849
1850/* reg_htgt_local_path_rdq
1851 * Receive descriptor queue (RDQ) to use for the trap group.
1852 * Access: RW
1853 */
1854MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
1855
801bd3de
IS		 1856static inline void mlxsw_reg_htgt_pack(char *payload,
1857 enum mlxsw_reg_htgt_trap_group group)
4ec14b76
IS		 1858{
1859 u8 swid, rdq;
1860
1861 MLXSW_REG_ZERO(htgt, payload);
801bd3de
IS		 1862 switch (group) {
1863 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
4ec14b76
IS		 1864 swid = MLXSW_PORT_SWID_ALL_SWIDS;
1865 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
801bd3de
IS		 1866 break;
1867 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
4ec14b76
IS		 1868 swid = 0;
1869 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
801bd3de
IS		 1870 break;
1871 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
1872 swid = 0;
1873 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
1874 break;
4ec14b76
IS		 1875 }
1876 mlxsw_reg_htgt_swid_set(payload, swid);
1877 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
801bd3de 1878 mlxsw_reg_htgt_trap_group_set(payload, group);
4ec14b76
IS		 1879 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
1880 mlxsw_reg_htgt_pid_set(payload, 0);
1881 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
1882 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
1883 mlxsw_reg_htgt_priority_set(payload, 0);
1884 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
1885 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
1886}
1887
1888/* HPKT - Host Packet Trap
1889 * -----------------------
1890 * Configures trap IDs inside trap groups.
1891 */
1892#define MLXSW_REG_HPKT_ID 0x7003
1893#define MLXSW_REG_HPKT_LEN 0x10
1894
1895static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
1896 .id = MLXSW_REG_HPKT_ID,
1897 .len = MLXSW_REG_HPKT_LEN,
1898};
1899
1900enum {
1901 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
1902 MLXSW_REG_HPKT_ACK_REQUIRED,
1903};
1904
1905/* reg_hpkt_ack
1906 * Require acknowledgements from the host for events.
1907 * If set, then the device will wait for the event it sent to be acknowledged
1908 * by the host. This option is only relevant for event trap IDs.
1909 * Access: RW
1910 *
1911 * Note: Currently not supported by firmware.
1912 */
1913MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
1914
1915enum mlxsw_reg_hpkt_action {
1916 MLXSW_REG_HPKT_ACTION_FORWARD,
1917 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1918 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
1919 MLXSW_REG_HPKT_ACTION_DISCARD,
1920 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
1921 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
1922};
1923
1924/* reg_hpkt_action
1925 * Action to perform on packet when trapped.
1926 * 0 - No action. Forward to CPU based on switching rules.
1927 * 1 - Trap to CPU (CPU receives sole copy).
1928 * 2 - Mirror to CPU (CPU receives a replica of the packet).
1929 * 3 - Discard.
1930 * 4 - Soft discard (allow other traps to act on the packet).
1931 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
1932 * Access: RW
1933 *
1934 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
1935 * addressed to the CPU.
1936 */
1937MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
1938
1939/* reg_hpkt_trap_group
1940 * Trap group to associate the trap with.
1941 * Access: RW
1942 */
1943MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
1944
1945/* reg_hpkt_trap_id
1946 * Trap ID.
1947 * Access: Index
1948 *
1949 * Note: A trap ID can only be associated with a single trap group. The device
1950 * will associate the trap ID with the last trap group configured.
1951 */
1952MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
1953
1954enum {
1955 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
1956 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
1957 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
1958};
1959
1960/* reg_hpkt_ctrl
1961 * Configure dedicated buffer resources for control packets.
1962 * 0 - Keep factory defaults.
1963 * 1 - Do not use control buffer for this trap ID.
1964 * 2 - Use control buffer for this trap ID.
1965 * Access: RW
1966 */
1967MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
1968
f24af330 1969static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
4ec14b76 1970{
801bd3de 1971 enum mlxsw_reg_htgt_trap_group trap_group;
f24af330 1972
4ec14b76
IS		 1973 MLXSW_REG_ZERO(hpkt, payload);
1974 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
1975 mlxsw_reg_hpkt_action_set(payload, action);
f24af330
IS		 1976 switch (trap_id) {
1977 case MLXSW_TRAP_ID_ETHEMAD:
1978 case MLXSW_TRAP_ID_PUDE:
1979 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
1980 break;
1981 default:
1982 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
1983 break;
1984 }
4ec14b76
IS		 1985 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
1986 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
1987 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
1988}
1989
e0594369
JP		 1990/* SBPR - Shared Buffer Pools Register
1991 * -----------------------------------
1992 * The SBPR configures and retrieves the shared buffer pools and configuration.
1993 */
1994#define MLXSW_REG_SBPR_ID 0xB001
1995#define MLXSW_REG_SBPR_LEN 0x14
1996
1997static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
1998 .id = MLXSW_REG_SBPR_ID,
1999 .len = MLXSW_REG_SBPR_LEN,
2000};
2001
2002enum mlxsw_reg_sbpr_dir {
2003 MLXSW_REG_SBPR_DIR_INGRESS,
2004 MLXSW_REG_SBPR_DIR_EGRESS,
2005};
2006
2007/* reg_sbpr_dir
2008 * Direction.
2009 * Access: Index
2010 */
2011MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
2012
2013/* reg_sbpr_pool
2014 * Pool index.
2015 * Access: Index
2016 */
2017MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
2018
2019/* reg_sbpr_size
2020 * Pool size in buffer cells.
2021 * Access: RW
2022 */
2023MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
2024
2025enum mlxsw_reg_sbpr_mode {
2026 MLXSW_REG_SBPR_MODE_STATIC,
2027 MLXSW_REG_SBPR_MODE_DYNAMIC,
2028};
2029
2030/* reg_sbpr_mode
2031 * Pool quota calculation mode.
2032 * Access: RW
2033 */
2034MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
2035
2036static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
2037 enum mlxsw_reg_sbpr_dir dir,
2038 enum mlxsw_reg_sbpr_mode mode, u32 size)
2039{
2040 MLXSW_REG_ZERO(sbpr, payload);
2041 mlxsw_reg_sbpr_pool_set(payload, pool);
2042 mlxsw_reg_sbpr_dir_set(payload, dir);
2043 mlxsw_reg_sbpr_mode_set(payload, mode);
2044 mlxsw_reg_sbpr_size_set(payload, size);
2045}
2046
2047/* SBCM - Shared Buffer Class Management Register
2048 * ----------------------------------------------
2049 * The SBCM register configures and retrieves the shared buffer allocation
2050 * and configuration according to Port-PG, including the binding to pool
2051 * and definition of the associated quota.
2052 */
2053#define MLXSW_REG_SBCM_ID 0xB002
2054#define MLXSW_REG_SBCM_LEN 0x28
2055
2056static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
2057 .id = MLXSW_REG_SBCM_ID,
2058 .len = MLXSW_REG_SBCM_LEN,
2059};
2060
2061/* reg_sbcm_local_port
2062 * Local port number.
2063 * For Ingress: excludes CPU port and Router port
2064 * For Egress: excludes IP Router
2065 * Access: Index
2066 */
2067MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
2068
2069/* reg_sbcm_pg_buff
2070 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
2071 * For PG buffer: range is 0..cap_max_pg_buffers - 1
2072 * For traffic class: range is 0..cap_max_tclass - 1
2073 * Note that when traffic class is in MC aware mode then the traffic
2074 * classes which are MC aware cannot be configured.
2075 * Access: Index
2076 */
2077MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
2078
2079enum mlxsw_reg_sbcm_dir {
2080 MLXSW_REG_SBCM_DIR_INGRESS,
2081 MLXSW_REG_SBCM_DIR_EGRESS,
2082};
2083
2084/* reg_sbcm_dir
2085 * Direction.
2086 * Access: Index
2087 */
2088MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
2089
2090/* reg_sbcm_min_buff
2091 * Minimum buffer size for the limiter, in cells.
2092 * Access: RW
2093 */
2094MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
2095
2096/* reg_sbcm_max_buff
2097 * When the pool associated to the port-pg/tclass is configured to
2098 * static, Maximum buffer size for the limiter configured in cells.
2099 * When the pool associated to the port-pg/tclass is configured to
2100 * dynamic, the max_buff holds the "alpha" parameter, supporting
2101 * the following values:
2102 * 0: 0
2103 * i: (1/128)*2^(i-1), for i=1..14
2104 * 0xFF: Infinity
2105 * Access: RW
2106 */
2107MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
2108
2109/* reg_sbcm_pool
2110 * Association of the port-priority to a pool.
2111 * Access: RW
2112 */
2113MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
2114
2115static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
2116 enum mlxsw_reg_sbcm_dir dir,
2117 u32 min_buff, u32 max_buff, u8 pool)
2118{
2119 MLXSW_REG_ZERO(sbcm, payload);
2120 mlxsw_reg_sbcm_local_port_set(payload, local_port);
2121 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
2122 mlxsw_reg_sbcm_dir_set(payload, dir);
2123 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
2124 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
2125 mlxsw_reg_sbcm_pool_set(payload, pool);
2126}
2127
2128/* SBPM - Shared Buffer Class Management Register
2129 * ----------------------------------------------
2130 * The SBPM register configures and retrieves the shared buffer allocation
2131 * and configuration according to Port-Pool, including the definition
2132 * of the associated quota.
2133 */
2134#define MLXSW_REG_SBPM_ID 0xB003
2135#define MLXSW_REG_SBPM_LEN 0x28
2136
2137static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
2138 .id = MLXSW_REG_SBPM_ID,
2139 .len = MLXSW_REG_SBPM_LEN,
2140};
2141
2142/* reg_sbpm_local_port
2143 * Local port number.
2144 * For Ingress: excludes CPU port and Router port
2145 * For Egress: excludes IP Router
2146 * Access: Index
2147 */
2148MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
2149
2150/* reg_sbpm_pool
2151 * The pool associated to quota counting on the local_port.
2152 * Access: Index
2153 */
2154MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
2155
2156enum mlxsw_reg_sbpm_dir {
2157 MLXSW_REG_SBPM_DIR_INGRESS,
2158 MLXSW_REG_SBPM_DIR_EGRESS,
2159};
2160
2161/* reg_sbpm_dir
2162 * Direction.
2163 * Access: Index
2164 */
2165MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
2166
2167/* reg_sbpm_min_buff
2168 * Minimum buffer size for the limiter, in cells.
2169 * Access: RW
2170 */
2171MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
2172
2173/* reg_sbpm_max_buff
2174 * When the pool associated to the port-pg/tclass is configured to
2175 * static, Maximum buffer size for the limiter configured in cells.
2176 * When the pool associated to the port-pg/tclass is configured to
2177 * dynamic, the max_buff holds the "alpha" parameter, supporting
2178 * the following values:
2179 * 0: 0
2180 * i: (1/128)*2^(i-1), for i=1..14
2181 * 0xFF: Infinity
2182 * Access: RW
2183 */
2184MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
2185
2186static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
2187 enum mlxsw_reg_sbpm_dir dir,
2188 u32 min_buff, u32 max_buff)
2189{
2190 MLXSW_REG_ZERO(sbpm, payload);
2191 mlxsw_reg_sbpm_local_port_set(payload, local_port);
2192 mlxsw_reg_sbpm_pool_set(payload, pool);
2193 mlxsw_reg_sbpm_dir_set(payload, dir);
2194 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
2195 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
2196}
2197
2198/* SBMM - Shared Buffer Multicast Management Register
2199 * --------------------------------------------------
2200 * The SBMM register configures and retrieves the shared buffer allocation
2201 * and configuration for MC packets according to Switch-Priority, including
2202 * the binding to pool and definition of the associated quota.
2203 */
2204#define MLXSW_REG_SBMM_ID 0xB004
2205#define MLXSW_REG_SBMM_LEN 0x28
2206
2207static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
2208 .id = MLXSW_REG_SBMM_ID,
2209 .len = MLXSW_REG_SBMM_LEN,
2210};
2211
2212/* reg_sbmm_prio
2213 * Switch Priority.
2214 * Access: Index
2215 */
2216MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
2217
2218/* reg_sbmm_min_buff
2219 * Minimum buffer size for the limiter, in cells.
2220 * Access: RW
2221 */
2222MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
2223
2224/* reg_sbmm_max_buff
2225 * When the pool associated to the port-pg/tclass is configured to
2226 * static, Maximum buffer size for the limiter configured in cells.
2227 * When the pool associated to the port-pg/tclass is configured to
2228 * dynamic, the max_buff holds the "alpha" parameter, supporting
2229 * the following values:
2230 * 0: 0
2231 * i: (1/128)*2^(i-1), for i=1..14
2232 * 0xFF: Infinity
2233 * Access: RW
2234 */
2235MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
2236
2237/* reg_sbmm_pool
2238 * Association of the port-priority to a pool.
2239 * Access: RW
2240 */
2241MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
2242
2243static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
2244 u32 max_buff, u8 pool)
2245{
2246 MLXSW_REG_ZERO(sbmm, payload);
2247 mlxsw_reg_sbmm_prio_set(payload, prio);
2248 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
2249 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
2250 mlxsw_reg_sbmm_pool_set(payload, pool);
2251}
2252
4ec14b76
IS		 2253static inline const char *mlxsw_reg_id_str(u16 reg_id)
2254{
2255 switch (reg_id) {
2256 case MLXSW_REG_SGCR_ID:
2257 return "SGCR";
2258 case MLXSW_REG_SPAD_ID:
2259 return "SPAD";
e61011b5
IS		 2260 case MLXSW_REG_SSPR_ID:
2261 return "SSPR";
236033b3
JP		 2262 case MLXSW_REG_SFD_ID:
2263 return "SFD";
f5d88f58
JP		 2264 case MLXSW_REG_SFN_ID:
2265 return "SFN";
4ec14b76
IS		 2266 case MLXSW_REG_SPMS_ID:
2267 return "SPMS";
b2e345f9
ER		 2268 case MLXSW_REG_SPVID_ID:
2269 return "SPVID";
2270 case MLXSW_REG_SPVM_ID:
2271 return "SPVM";
4ec14b76
IS		 2272 case MLXSW_REG_SFGC_ID:
2273 return "SFGC";
2274 case MLXSW_REG_SFTR_ID:
2275 return "SFTR";
2276 case MLXSW_REG_SPMLR_ID:
2277 return "SPMLR";
64790239
IS		 2278 case MLXSW_REG_SVFA_ID:
2279 return "SVFA";
1f65da74
IS		 2280 case MLXSW_REG_SVPE_ID:
2281 return "SVPE";
f1fb693a
IS		 2282 case MLXSW_REG_SFMR_ID:
2283 return "SFMR";
4ec14b76
IS		 2284 case MLXSW_REG_PMLP_ID:
2285 return "PMLP";
2286 case MLXSW_REG_PMTU_ID:
2287 return "PMTU";
2288 case MLXSW_REG_PTYS_ID:
2289 return "PTYS";
2290 case MLXSW_REG_PPAD_ID:
2291 return "PPAD";
2292 case MLXSW_REG_PAOS_ID:
2293 return "PAOS";
2294 case MLXSW_REG_PPCNT_ID:
2295 return "PPCNT";
e0594369
JP		 2296 case MLXSW_REG_PBMC_ID:
2297 return "PBMC";
4ec14b76
IS		 2298 case MLXSW_REG_PSPA_ID:
2299 return "PSPA";
2300 case MLXSW_REG_HTGT_ID:
2301 return "HTGT";
2302 case MLXSW_REG_HPKT_ID:
2303 return "HPKT";
e0594369
JP		 2304 case MLXSW_REG_SBPR_ID:
2305 return "SBPR";
2306 case MLXSW_REG_SBCM_ID:
2307 return "SBCM";
2308 case MLXSW_REG_SBPM_ID:
2309 return "SBPM";
2310 case MLXSW_REG_SBMM_ID:
2311 return "SBMM";
4ec14b76
IS		 2312 default:
2313 return "*UNKNOWN*";
2314 }
2315}
2316
2317/* PUDE - Port Up / Down Event
2318 * ---------------------------
2319 * Reports the operational state change of a port.
2320 */
2321#define MLXSW_REG_PUDE_LEN 0x10
2322
2323/* reg_pude_swid
2324 * Switch partition ID with which to associate the port.
2325 * Access: Index
2326 */
2327MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
2328
2329/* reg_pude_local_port
2330 * Local port number.
2331 * Access: Index
2332 */
2333MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
2334
2335/* reg_pude_admin_status
2336 * Port administrative state (the desired state).
2337 * 1 - Up.
2338 * 2 - Down.
2339 * 3 - Up once. This means that in case of link failure, the port won't go
2340 * into polling mode, but will wait to be re-enabled by software.
2341 * 4 - Disabled by system. Can only be set by hardware.
2342 * Access: RO
2343 */
2344MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
2345
2346/* reg_pude_oper_status
2347 * Port operatioanl state.
2348 * 1 - Up.
2349 * 2 - Down.
2350 * 3 - Down by port failure. This means that the device will not let the
2351 * port up again until explicitly specified by software.
2352 * Access: RO
2353 */
2354MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
2355
2356#endif
Linux 6.x block layer and io_uring tree(s)