[linux-block.git] / drivers / net / ethernet / mellanox / mlxsw / pci_hw.h

/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */

#ifndef _MLXSW_PCI_HW_H
#define _MLXSW_PCI_HW_H

#include <linux/bitops.h>

#include "item.h"

#define MLXSW_PCI_BAR0_SIZE		(1024 * 1024) /* 1MB */
#define MLXSW_PCI_PAGE_SIZE		4096

#define MLXSW_PCI_CIR_BASE			0x71000
#define MLXSW_PCI_CIR_IN_PARAM_HI		MLXSW_PCI_CIR_BASE
#define MLXSW_PCI_CIR_IN_PARAM_LO		(MLXSW_PCI_CIR_BASE + 0x04)
#define MLXSW_PCI_CIR_IN_MODIFIER		(MLXSW_PCI_CIR_BASE + 0x08)
#define MLXSW_PCI_CIR_OUT_PARAM_HI		(MLXSW_PCI_CIR_BASE + 0x0C)
#define MLXSW_PCI_CIR_OUT_PARAM_LO		(MLXSW_PCI_CIR_BASE + 0x10)
#define MLXSW_PCI_CIR_TOKEN			(MLXSW_PCI_CIR_BASE + 0x14)
#define MLXSW_PCI_CIR_CTRL			(MLXSW_PCI_CIR_BASE + 0x18)
#define MLXSW_PCI_CIR_CTRL_GO_BIT		BIT(23)
#define MLXSW_PCI_CIR_CTRL_EVREQ_BIT		BIT(22)
#define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT	12
#define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT		24
#define MLXSW_PCI_CIR_TIMEOUT_MSECS		1000

#define MLXSW_PCI_SW_RESET			0xF0010
#define MLXSW_PCI_SW_RESET_RST_BIT		BIT(0)
#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS	900000
#define MLXSW_PCI_SW_RESET_WAIT_MSECS		200
#define MLXSW_PCI_FW_READY			0xA1844
#define MLXSW_PCI_FW_READY_MASK			0xFFFF
#define MLXSW_PCI_FW_READY_MAGIC		0x5E

#define MLXSW_PCI_DOORBELL_SDQ_OFFSET		0x000
#define MLXSW_PCI_DOORBELL_RDQ_OFFSET		0x200
#define MLXSW_PCI_DOORBELL_CQ_OFFSET		0x400
#define MLXSW_PCI_DOORBELL_EQ_OFFSET		0x600
#define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET	0x800
#define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET	0xA00

#define MLXSW_PCI_DOORBELL(offset, type_offset, num)	\
	((offset) + (type_offset) + (num) * 4)

#define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset)	(offset)
#define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset)	((offset) + 4)

#define MLXSW_PCI_CQS_MAX	96
#define MLXSW_PCI_EQS_COUNT	2
#define MLXSW_PCI_EQ_ASYNC_NUM	0
#define MLXSW_PCI_EQ_COMP_NUM	1

#define MLXSW_PCI_SDQS_MIN	2 /* EMAD and control traffic */
#define MLXSW_PCI_SDQ_EMAD_INDEX	0
#define MLXSW_PCI_SDQ_EMAD_TC	0
#define MLXSW_PCI_SDQ_CTL_TC	3

#define MLXSW_PCI_AQ_PAGES	8
#define MLXSW_PCI_AQ_SIZE	(MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
#define MLXSW_PCI_WQE_SIZE	32 /* 32 bytes per element */
#define MLXSW_PCI_CQE01_SIZE	16 /* 16 bytes per element */
#define MLXSW_PCI_CQE2_SIZE	32 /* 32 bytes per element */
#define MLXSW_PCI_CQE_SIZE_MAX	MLXSW_PCI_CQE2_SIZE
#define MLXSW_PCI_EQE_SIZE	16 /* 16 bytes per element */
#define MLXSW_PCI_WQE_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
#define MLXSW_PCI_CQE01_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
#define MLXSW_PCI_CQE2_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
#define MLXSW_PCI_EQE_COUNT	(MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
#define MLXSW_PCI_EQE_UPDATE_COUNT	0x80

#define MLXSW_PCI_WQE_SG_ENTRIES	3
#define MLXSW_PCI_WQE_TYPE_ETHERNET	0xA

/* pci_wqe_c
 * If set it indicates that a completion should be reported upon
 * execution of this descriptor.
 */
MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);

/* pci_wqe_lp
 * Local Processing, set if packet should be processed by the local
 * switch hardware:
 * For Ethernet EMAD (Direct Route and non Direct Route) -
 * must be set if packet destination is local device
 * For InfiniBand CTL - must be set if packet destination is local device
 * Otherwise it must be clear
 * Local Process packets must not exceed the size of 2K (including payload
 * and headers).
 */
MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);

/* pci_wqe_type
 * Packet type.
 */
MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);

/* pci_wqe_byte_count
 * Size of i-th scatter/gather entry, 0 if entry is unused.
 */
MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);

/* pci_wqe_address
 * Physical address of i-th scatter/gather entry.
 * Gather Entries must be 2Byte aligned.
 */
MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);

enum mlxsw_pci_cqe_v {
	MLXSW_PCI_CQE_V0,
	MLXSW_PCI_CQE_V1,
	MLXSW_PCI_CQE_V2,
};

#define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2)				\
static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe)	\
{										\
	switch (v) {								\
	default:								\
	case MLXSW_PCI_CQE_V0:							\
		return mlxsw_pci_cqe##v0##_##name##_get(cqe);			\
	case MLXSW_PCI_CQE_V1:							\
		return mlxsw_pci_cqe##v1##_##name##_get(cqe);			\
	case MLXSW_PCI_CQE_V2:							\
		return mlxsw_pci_cqe##v2##_##name##_get(cqe);			\
	}									\
}										\
static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v,		\
					      char *cqe, u32 val)		\
{										\
	switch (v) {								\
	default:								\
	case MLXSW_PCI_CQE_V0:							\
		mlxsw_pci_cqe##v0##_##name##_set(cqe, val);			\
		break;								\
	case MLXSW_PCI_CQE_V1:							\
		mlxsw_pci_cqe##v1##_##name##_set(cqe, val);			\
		break;								\
	case MLXSW_PCI_CQE_V2:							\
		mlxsw_pci_cqe##v2##_##name##_set(cqe, val);			\
		break;								\
	}									\
}

/* pci_cqe_lag
 * Packet arrives from a port which is a LAG
 */
MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);

/* pci_cqe_system_port/lag_id
 * When lag=0: System port on which the packet was received
 * When lag=1:
 * bits [15:4] LAG ID on which the packet was received
 * bits [3:0] sub_port on which the packet was received
 */
MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);

/* pci_cqe_wqe_counter
 * WQE count of the WQEs completed on the associated dqn
 */
MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);

/* pci_cqe_byte_count
 * Byte count of received packets including additional two
 * Reserved Bytes that are append to the end of the frame.
 * Reserved for Send CQE.
 */
MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);

/* pci_cqe_trap_id
 * Trap ID that captured the packet.
 */
MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);

/* pci_cqe_crc
 * Length include CRC. Indicates the length field includes
 * the packet's CRC.
 */
MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);

/* pci_cqe_e
 * CQE with Error.
 */
MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);

/* pci_cqe_sr
 * 1 - Send Queue
 * 0 - Receive Queue
 */
MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);

/* pci_cqe_dqn
 * Descriptor Queue (DQ) Number.
 */
MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);

/* pci_cqe_owner
 * Ownership bit.
 */
MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);

/* pci_eqe_event_type
 * Event type.
 */
MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
#define MLXSW_PCI_EQE_EVENT_TYPE_COMP	0x00
#define MLXSW_PCI_EQE_EVENT_TYPE_CMD	0x0A

/* pci_eqe_event_sub_type
 * Event type.
 */
MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);

/* pci_eqe_cqn
 * Completion Queue that triggered this EQE.
 */
MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);

/* pci_eqe_owner
 * Ownership bit.
 */
MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);

/* pci_eqe_cmd_token
 * Command completion event - token
 */
MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);

/* pci_eqe_cmd_status
 * Command completion event - status
 */
MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);

/* pci_eqe_cmd_out_param_h
 * Command completion event - output parameter - higher part
 */
MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);

/* pci_eqe_cmd_out_param_l
 * Command completion event - output parameter - lower part
 */
MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);

#endif
Commit	Line	Data
9948a064 JP	1	/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
9948a064 JP	2	/* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
eda6500a	3
62e86f9e JP	4	#ifndef _MLXSW_PCI_HW_H
62e86f9e JP	5	#define _MLXSW_PCI_HW_H
eda6500a JP	6
	7	#include <linux/bitops.h>
	8
	9	#include "item.h"
	10
	11	#define MLXSW_PCI_BAR0_SIZE (1024 * 1024) /* 1MB */
	12	#define MLXSW_PCI_PAGE_SIZE 4096
	13
	14	#define MLXSW_PCI_CIR_BASE 0x71000
	15	#define MLXSW_PCI_CIR_IN_PARAM_HI MLXSW_PCI_CIR_BASE
	16	#define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
	17	#define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
	18	#define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
	19	#define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
	20	#define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
	21	#define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
	22	#define MLXSW_PCI_CIR_CTRL_GO_BIT BIT(23)
	23	#define MLXSW_PCI_CIR_CTRL_EVREQ_BIT BIT(22)
	24	#define MLXSW_PCI_CIR_CTRL_OPCODE_MOD_SHIFT 12
	25	#define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT 24
	26	#define MLXSW_PCI_CIR_TIMEOUT_MSECS 1000
	27
	28	#define MLXSW_PCI_SW_RESET 0xF0010
	29	#define MLXSW_PCI_SW_RESET_RST_BIT BIT(0)
ff298839	30	#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS 900000
ac004e84	31	#define MLXSW_PCI_SW_RESET_WAIT_MSECS 200
233fa44b	32	#define MLXSW_PCI_FW_READY 0xA1844
5e5f89e7	33	#define MLXSW_PCI_FW_READY_MASK 0xFFFF
233fa44b	34	#define MLXSW_PCI_FW_READY_MAGIC 0x5E
eda6500a JP	35
	36	#define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
	37	#define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
	38	#define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
	39	#define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
	40	#define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
	41	#define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
	42
	43	#define MLXSW_PCI_DOORBELL(offset, type_offset, num) \
	44	((offset) + (type_offset) + (num) * 4)
	45
8289169d ST	46	#define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset) (offset)
	47	#define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset) ((offset) + 4)
	48
e4c870b1	49	#define MLXSW_PCI_CQS_MAX 96
eda6500a JP	50	#define MLXSW_PCI_EQS_COUNT 2
	51	#define MLXSW_PCI_EQ_ASYNC_NUM 0
	52	#define MLXSW_PCI_EQ_COMP_NUM 1
	53
6aaee55c PM	54	#define MLXSW_PCI_SDQS_MIN 2 /* EMAD and control traffic */
	55	#define MLXSW_PCI_SDQ_EMAD_INDEX 0
	56	#define MLXSW_PCI_SDQ_EMAD_TC 0
	57	#define MLXSW_PCI_SDQ_CTL_TC 3
	58
eda6500a JP	59	#define MLXSW_PCI_AQ_PAGES 8
	60	#define MLXSW_PCI_AQ_SIZE (MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
	61	#define MLXSW_PCI_WQE_SIZE 32 /* 32 bytes per element */
b76550bb JP	62	#define MLXSW_PCI_CQE01_SIZE 16 /* 16 bytes per element */
b76550bb JP	63	#define MLXSW_PCI_CQE2_SIZE 32 /* 32 bytes per element */
c9ebea04	64	#define MLXSW_PCI_CQE_SIZE_MAX MLXSW_PCI_CQE2_SIZE
eda6500a JP	65	#define MLXSW_PCI_EQE_SIZE 16 /* 16 bytes per element */
eda6500a JP	66	#define MLXSW_PCI_WQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_WQE_SIZE)
b76550bb JP	67	#define MLXSW_PCI_CQE01_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE01_SIZE)
b76550bb JP	68	#define MLXSW_PCI_CQE2_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_CQE2_SIZE)
eda6500a JP	69	#define MLXSW_PCI_EQE_COUNT (MLXSW_PCI_AQ_SIZE / MLXSW_PCI_EQE_SIZE)
	70	#define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
	71
	72	#define MLXSW_PCI_WQE_SG_ENTRIES 3
	73	#define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
	74
	75	/* pci_wqe_c
	76	* If set it indicates that a completion should be reported upon
	77	* execution of this descriptor.
	78	*/
	79	MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
	80
	81	/* pci_wqe_lp
	82	* Local Processing, set if packet should be processed by the local
	83	* switch hardware:
	84	* For Ethernet EMAD (Direct Route and non Direct Route) -
	85	* must be set if packet destination is local device
	86	* For InfiniBand CTL - must be set if packet destination is local device
	87	* Otherwise it must be clear
	88	* Local Process packets must not exceed the size of 2K (including payload
	89	* and headers).
	90	*/
	91	MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
	92
	93	/* pci_wqe_type
	94	* Packet type.
	95	*/
	96	MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
	97
	98	/* pci_wqe_byte_count
	99	* Size of i-th scatter/gather entry, 0 if entry is unused.
	100	*/
	101	MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
	102
	103	/* pci_wqe_address
	104	* Physical address of i-th scatter/gather entry.
	105	* Gather Entries must be 2Byte aligned.
	106	*/
	107	MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
	108
b76550bb JP	109	enum mlxsw_pci_cqe_v {
	110	MLXSW_PCI_CQE_V0,
	111	MLXSW_PCI_CQE_V1,
	112	MLXSW_PCI_CQE_V2,
	113	};
	114
	115	#define mlxsw_pci_cqe_item_helpers(name, v0, v1, v2) \
	116	static inline u32 mlxsw_pci_cqe_##name##_get(enum mlxsw_pci_cqe_v v, char *cqe) \
	117	{ \
	118	switch (v) { \
	119	default: \
	120	case MLXSW_PCI_CQE_V0: \
	121	return mlxsw_pci_cqe##v0##_##name##_get(cqe); \
	122	case MLXSW_PCI_CQE_V1: \
	123	return mlxsw_pci_cqe##v1##_##name##_get(cqe); \
	124	case MLXSW_PCI_CQE_V2: \
	125	return mlxsw_pci_cqe##v2##_##name##_get(cqe); \
	126	} \
	127	} \
	128	static inline void mlxsw_pci_cqe_##name##_set(enum mlxsw_pci_cqe_v v, \
	129	char *cqe, u32 val) \
	130	{ \
	131	switch (v) { \
	132	default: \
	133	case MLXSW_PCI_CQE_V0: \
	134	mlxsw_pci_cqe##v0##_##name##_set(cqe, val); \
	135	break; \
	136	case MLXSW_PCI_CQE_V1: \
	137	mlxsw_pci_cqe##v1##_##name##_set(cqe, val); \
	138	break; \
	139	case MLXSW_PCI_CQE_V2: \
	140	mlxsw_pci_cqe##v2##_##name##_set(cqe, val); \
	141	break; \
	142	} \
	143	}
	144
eda6500a JP	145	/* pci_cqe_lag
	146	* Packet arrives from a port which is a LAG
	147	*/
b76550bb JP	148	MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
	149	MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
	150	mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
eda6500a	151
d2292e87	152	/* pci_cqe_system_port/lag_id
eda6500a JP	153	* When lag=0: System port on which the packet was received
	154	* When lag=1:
	155	* bits [15:4] LAG ID on which the packet was received
	156	* bits [3:0] sub_port on which the packet was received
	157	*/
	158	MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
b76550bb JP	159	MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
	160	MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
	161	mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
	162	MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
	163	MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
	164	mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
eda6500a JP	165
	166	/* pci_cqe_wqe_counter
	167	* WQE count of the WQEs completed on the associated dqn
	168	*/
	169	MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
	170
	171	/* pci_cqe_byte_count
	172	* Byte count of received packets including additional two
	173	* Reserved Bytes that are append to the end of the frame.
	174	* Reserved for Send CQE.
	175	*/
	176	MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
	177
	178	/* pci_cqe_trap_id
	179	* Trap ID that captured the packet.
	180	*/
be8408e1	181	MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
eda6500a	182
7b7b9cff JP	183	/* pci_cqe_crc
	184	* Length include CRC. Indicates the length field includes
	185	* the packet's CRC.
	186	*/
b76550bb JP	187	MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
	188	MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
	189	mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
7b7b9cff	190
eda6500a JP	191	/* pci_cqe_e
	192	* CQE with Error.
	193	*/
b76550bb JP	194	MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
	195	MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
	196	mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
eda6500a JP	197
	198	/* pci_cqe_sr
	199	* 1 - Send Queue
	200	* 0 - Receive Queue
	201	*/
b76550bb JP	202	MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
	203	MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
	204	mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
eda6500a JP	205
	206	/* pci_cqe_dqn
	207	* Descriptor Queue (DQ) Number.
	208	*/
b76550bb JP	209	MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
	210	MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
	211	mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
eda6500a JP	212
	213	/* pci_cqe_owner
	214	* Ownership bit.
	215	*/
b76550bb JP	216	MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
	217	MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
	218	mlxsw_pci_cqe_item_helpers(owner, 01, 01, 2);
eda6500a JP	219
	220	/* pci_eqe_event_type
	221	* Event type.
	222	*/
	223	MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
	224	#define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
	225	#define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
	226
	227	/* pci_eqe_event_sub_type
	228	* Event type.
	229	*/
	230	MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
	231
	232	/* pci_eqe_cqn
9e664316	233	* Completion Queue that triggered this EQE.
eda6500a JP	234	*/
	235	MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
	236
	237	/* pci_eqe_owner
	238	* Ownership bit.
	239	*/
	240	MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
	241
	242	/* pci_eqe_cmd_token
	243	* Command completion event - token
	244	*/
28e46a0f	245	MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
eda6500a JP	246
	247	/* pci_eqe_cmd_status
	248	* Command completion event - status
	249	*/
28e46a0f	250	MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
eda6500a JP	251
	252	/* pci_eqe_cmd_out_param_h
	253	* Command completion event - output parameter - higher part
	254	*/
28e46a0f	255	MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
eda6500a JP	256
	257	/* pci_eqe_cmd_out_param_l
	258	* Command completion event - output parameter - lower part
	259	*/
28e46a0f	260	MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);
eda6500a JP	261
eda6500a JP	262	#endif