[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / port.c

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/module.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/port.h>
#include <linux/mlx5/cmd.h>
#include "mlx5_core.h"

int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
			 int size_in, void *data_out, int size_out,
			 u16 reg_num, int arg, int write)
{
	struct mlx5_access_reg_mbox_in *in = NULL;
	struct mlx5_access_reg_mbox_out *out = NULL;
	int err = -ENOMEM;

	in = mlx5_vzalloc(sizeof(*in) + size_in);
	if (!in)
		return -ENOMEM;

	out = mlx5_vzalloc(sizeof(*out) + size_out);
	if (!out)
		goto ex1;

	memcpy(in->data, data_in, size_in);
	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
	in->hdr.opmod = cpu_to_be16(!write);
	in->arg = cpu_to_be32(arg);
	in->register_id = cpu_to_be16(reg_num);
	err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
			    sizeof(*out) + size_out);
	if (err)
		goto ex2;

	if (out->hdr.status)
		err = mlx5_cmd_status_to_err(&out->hdr);

	if (!err)
		memcpy(data_out, out->data, size_out);

ex2:
	kvfree(out);
ex1:
	kvfree(in);
	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_access_reg);


struct mlx5_reg_pcap {
	u8			rsvd0;
	u8			port_num;
	u8			rsvd1[2];
	__be32			caps_127_96;
	__be32			caps_95_64;
	__be32			caps_63_32;
	__be32			caps_31_0;
};

int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
{
	struct mlx5_reg_pcap in;
	struct mlx5_reg_pcap out;

	memset(&in, 0, sizeof(in));
	in.caps_127_96 = cpu_to_be32(caps);
	in.port_num = port_num;

	return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
				    sizeof(out), MLX5_REG_PCAP, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_caps);

int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
			 int ptys_size, int proto_mask, u8 local_port)
{
	u32 in[MLX5_ST_SZ_DW(ptys_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(ptys_reg, in, local_port, local_port);
	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);

	return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
				    ptys_size, MLX5_REG_PTYS, 0, 0);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);

int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
{
	u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
	u32 in[MLX5_ST_SZ_DW(mlcr_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(mlcr_reg, in, local_port, 1);
	MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_MLCR, 0, 1);
}

int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
			      u32 *proto_cap, int proto_mask)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
	else
		*proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);

int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
				u32 *proto_admin, int proto_mask)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
	else
		*proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);

int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
				    u8 *link_width_oper, u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
	if (err)
		return err;

	*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);

int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
			       u8 *proto_oper, int proto_mask,
			       u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
	else
		*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);

int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
			int proto_mask)
{
	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(ptys_reg, in, local_port, 1);
	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
	if (proto_mask == MLX5_PTYS_EN)
		MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
	else
		MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PTYS, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_proto);

int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
			       enum mlx5_port_status status)
{
	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	u32 out[MLX5_ST_SZ_DW(paos_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(paos_reg, in, local_port, 1);
	MLX5_SET(paos_reg, in, admin_status, status);
	MLX5_SET(paos_reg, in, ase, 1);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PAOS, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);

int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
				 enum mlx5_port_status *status)
{
	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	int err;

	memset(in, 0, sizeof(in));

	MLX5_SET(paos_reg, in, local_port, 1);

	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PAOS, 0, 0);
	if (err)
		return err;

	*status = MLX5_GET(paos_reg, out, admin_status);
	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);

static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, int *admin_mtu,
				int *max_mtu, int *oper_mtu, u8 port)
{
	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(pmtu_reg, in, local_port, port);

	mlx5_core_access_reg(dev, in, sizeof(in), out,
			     sizeof(out), MLX5_REG_PMTU, 0, 0);

	if (max_mtu)
		*max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
	if (oper_mtu)
		*oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
	if (admin_mtu)
		*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
}

int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)
{
	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
	MLX5_SET(pmtu_reg, in, local_port, port);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PMTU, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);

void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu,
			     u8 port)
{
	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);

void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
			      u8 port)
{
	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);

static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
				int pvlc_size,  u8 local_port)
{
	u32 in[MLX5_ST_SZ_DW(pvlc_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pvlc_reg, in, local_port, local_port);

	return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
				    pvlc_size, MLX5_REG_PVLC, 0, 0);
}

int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
			      u8 *vl_hw_cap, u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
	int err;

	err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
	if (err)
		return err;

	*vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);

int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
			     u8 port_num, void *out, size_t sz)
{
	u32 *in;
	int err;

	in  = mlx5_vzalloc(sz);
	if (!in) {
		err = -ENOMEM;
		return err;
	}

	MLX5_SET(ppcnt_reg, in, local_port, port_num);

	MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
	err = mlx5_core_access_reg(dev, in, sz, out,
				   sz, MLX5_REG_PPCNT, 0, 0);

	kvfree(in);
	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);

int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);
	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
	MLX5_SET(pfcc_reg, in, pprx, rx_pause);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PFCC, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_pause);

int mlx5_query_port_pause(struct mlx5_core_dev *dev,
			  u32 *rx_pause, u32 *tx_pause)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	int err;

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);

	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PFCC, 0, 0);
	if (err)
		return err;

	if (rx_pause)
		*rx_pause = MLX5_GET(pfcc_reg, out, pprx);

	if (tx_pause)
		*tx_pause = MLX5_GET(pfcc_reg, out, pptx);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_pause);

int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);
	MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
	MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PFCC, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);

int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	int err;

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);

	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PFCC, 0, 0);
	if (err)
		return err;

	if (pfc_en_tx)
		*pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);

	if (pfc_en_rx)
		*pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);

int mlx5_max_tc(struct mlx5_core_dev *mdev)
{
	u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;

	return num_tc - 1;
}

int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
{
	u32 in[MLX5_ST_SZ_DW(qtct_reg)];
	u32 out[MLX5_ST_SZ_DW(qtct_reg)];
	int err;
	int i;

	memset(in, 0, sizeof(in));
	for (i = 0; i < 8; i++) {
		if (prio_tc[i] > mlx5_max_tc(mdev))
			return -EINVAL;

		MLX5_SET(qtct_reg, in, prio, i);
		MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);

		err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
					   sizeof(out), MLX5_REG_QTCT, 0, 1);
		if (err)
			return err;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);

static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
				   int inlen)
{
	u32 out[MLX5_ST_SZ_DW(qtct_reg)];

	if (!MLX5_CAP_GEN(mdev, ets))
		return -ENOTSUPP;

	return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
				    MLX5_REG_QETCR, 0, 1);
}

static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *out,
				     int outlen)
{
	u32 in[MLX5_ST_SZ_DW(qtct_reg)];

	if (!MLX5_CAP_GEN(mdev, ets))
		return -ENOTSUPP;

	memset(in, 0, sizeof(in));
	return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
				    MLX5_REG_QETCR, 0, 0);
}

int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
{
	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	int i;

	memset(in, 0, sizeof(in));

	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
		MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
		MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
	}

	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
}
EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);

int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
{
	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	int i;

	memset(in, 0, sizeof(in));

	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
		MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
		MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
	}

	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
}
EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);

int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
				    u8 *max_bw_value,
				    u8 *max_bw_units)
{
	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	void *ets_tcn_conf;
	int i;

	memset(in, 0, sizeof(in));

	MLX5_SET(qetc_reg, in, port_number, 1);

	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
		ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);

		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
			 max_bw_units[i]);
		MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
			 max_bw_value[i]);
	}

	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
}
EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);

int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
				   u8 *max_bw_value,
				   u8 *max_bw_units)
{
	u32 out[MLX5_ST_SZ_DW(qetc_reg)];
	void *ets_tcn_conf;
	int err;
	int i;

	err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
	if (err)
		return err;

	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
		ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);

		max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
					   max_bw_value);
		max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
					   max_bw_units);
	}

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);

int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
{
	u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
	u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];

	memset(in, 0, sizeof(in));
	memset(out, 0, sizeof(out));

	MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
	MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
	MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);

	return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
					  out, sizeof(out));
}
EXPORT_SYMBOL_GPL(mlx5_set_port_wol);

int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode)
{
	u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
	u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
	int err;

	memset(in, 0, sizeof(in));
	memset(out, 0, sizeof(out));

	MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);

	err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
					 out, sizeof(out));

	if (!err)
		*wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);

	return err;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_wol);

static int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out,
				  int outlen)
{
	u32 in[MLX5_ST_SZ_DW(pcmr_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pcmr_reg, in, local_port, 1);

	return mlx5_core_access_reg(mdev, in, sizeof(in), out,
				    outlen, MLX5_REG_PCMR, 0, 0);
}

static int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen)
{
	u32 out[MLX5_ST_SZ_DW(pcmr_reg)];

	return mlx5_core_access_reg(mdev, in, inlen, out,
				    sizeof(out), MLX5_REG_PCMR, 0, 1);
}

int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
{
	u32 in[MLX5_ST_SZ_DW(pcmr_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pcmr_reg, in, local_port, 1);
	MLX5_SET(pcmr_reg, in, fcs_chk, enable);

	return mlx5_set_ports_check(mdev, in, sizeof(in));
}

void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
			 bool *enabled)
{
	u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
	/* Default values for FW which do not support MLX5_REG_PCMR */
	*supported = false;
	*enabled = true;

	if (!MLX5_CAP_GEN(mdev, ports_check))
		return;

	if (mlx5_query_ports_check(mdev, out, sizeof(out)))
		return;

	*supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
	*enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
}
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/module.h>
	34	#include <linux/mlx5/driver.h>
ada68c31	35	#include <linux/mlx5/port.h>
e126ba97 EC	36	#include <linux/mlx5/cmd.h>
	37	#include "mlx5_core.h"
	38
	39	int mlx5_core_access_reg(struct mlx5_core_dev dev, void data_in,
	40	int size_in, void *data_out, int size_out,
	41	u16 reg_num, int arg, int write)
	42	{
	43	struct mlx5_access_reg_mbox_in *in = NULL;
	44	struct mlx5_access_reg_mbox_out *out = NULL;
	45	int err = -ENOMEM;
	46
	47	in = mlx5_vzalloc(sizeof(*in) + size_in);
	48	if (!in)
	49	return -ENOMEM;
	50
	51	out = mlx5_vzalloc(sizeof(*out) + size_out);
	52	if (!out)
	53	goto ex1;
	54
	55	memcpy(in->data, data_in, size_in);
	56	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
	57	in->hdr.opmod = cpu_to_be16(!write);
	58	in->arg = cpu_to_be32(arg);
	59	in->register_id = cpu_to_be16(reg_num);
	60	err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
e08a8761	61	sizeof(*out) + size_out);
e126ba97 EC	62	if (err)
	63	goto ex2;
	64
	65	if (out->hdr.status)
	66	err = mlx5_cmd_status_to_err(&out->hdr);
	67
	68	if (!err)
	69	memcpy(data_out, out->data, size_out);
	70
	71	ex2:
479163f4	72	kvfree(out);
e126ba97	73	ex1:
479163f4	74	kvfree(in);
e126ba97 EC	75	return err;
	76	}
	77	EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
	78
	79
	80	struct mlx5_reg_pcap {
	81	u8 rsvd0;
	82	u8 port_num;
	83	u8 rsvd1[2];
	84	__be32 caps_127_96;
	85	__be32 caps_95_64;
	86	__be32 caps_63_32;
	87	__be32 caps_31_0;
	88	};
	89
f241e749	90	int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
e126ba97 EC	91	{
	92	struct mlx5_reg_pcap in;
	93	struct mlx5_reg_pcap out;
e126ba97 EC	94
	95	memset(&in, 0, sizeof(in));
	96	in.caps_127_96 = cpu_to_be32(caps);
	97	in.port_num = port_num;
	98
6c3dbd2d AS	99	return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
6c3dbd2d AS	100	sizeof(out), MLX5_REG_PCAP, 0, 1);
e126ba97 EC	101	}
e126ba97 EC	102	EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
adb0c954 SM	103
adb0c954 SM	104	int mlx5_query_port_ptys(struct mlx5_core_dev dev, u32 ptys,
a05bdefa	105	int ptys_size, int proto_mask, u8 local_port)
adb0c954 SM	106	{
adb0c954 SM	107	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
adb0c954 SM	108
adb0c954 SM	109	memset(in, 0, sizeof(in));
a05bdefa	110	MLX5_SET(ptys_reg, in, local_port, local_port);
adb0c954 SM	111	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
adb0c954 SM	112
6c3dbd2d AS	113	return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
6c3dbd2d AS	114	ptys_size, MLX5_REG_PTYS, 0, 0);
adb0c954 SM	115	}
	116	EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
	117
da54d24e GP	118	int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration)
	119	{
	120	u32 out[MLX5_ST_SZ_DW(mlcr_reg)];
	121	u32 in[MLX5_ST_SZ_DW(mlcr_reg)];
	122
	123	memset(in, 0, sizeof(in));
	124	MLX5_SET(mlcr_reg, in, local_port, 1);
	125	MLX5_SET(mlcr_reg, in, beacon_duration, beacon_duration);
	126
	127	return mlx5_core_access_reg(dev, in, sizeof(in), out,
	128	sizeof(out), MLX5_REG_MLCR, 0, 1);
	129	}
	130
adb0c954 SM	131	int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
	132	u32 *proto_cap, int proto_mask)
	133	{
	134	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	135	int err;
	136
a05bdefa	137	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
adb0c954 SM	138	if (err)
	139	return err;
	140
	141	if (proto_mask == MLX5_PTYS_EN)
	142	*proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
	143	else
	144	*proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
	145
	146	return 0;
	147	}
	148	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
	149
	150	int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
	151	u32 *proto_admin, int proto_mask)
	152	{
	153	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	154	int err;
	155
a05bdefa	156	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
adb0c954 SM	157	if (err)
	158	return err;
	159
	160	if (proto_mask == MLX5_PTYS_EN)
	161	*proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
	162	else
	163	*proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
	164
	165	return 0;
	166	}
	167	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
	168
a124d13e MD	169	int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
	170	u8 *link_width_oper, u8 local_port)
	171	{
	172	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	173	int err;
	174
	175	err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
	176	if (err)
	177	return err;
	178
	179	*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
	180
	181	return 0;
	182	}
	183	EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
	184
	185	int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
	186	u8 *proto_oper, int proto_mask,
	187	u8 local_port)
	188	{
	189	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	190	int err;
	191
	192	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
	193	if (err)
	194	return err;
	195
	196	if (proto_mask == MLX5_PTYS_EN)
	197	*proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
	198	else
	199	*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
	200
	201	return 0;
	202	}
	203	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
	204
adb0c954 SM	205	int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
	206	int proto_mask)
	207	{
	208	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
	209	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
adb0c954 SM	210
	211	memset(in, 0, sizeof(in));
	212
	213	MLX5_SET(ptys_reg, in, local_port, 1);
	214	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
	215	if (proto_mask == MLX5_PTYS_EN)
	216	MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
	217	else
	218	MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
	219
6c3dbd2d AS	220	return mlx5_core_access_reg(dev, in, sizeof(in), out,
6c3dbd2d AS	221	sizeof(out), MLX5_REG_PTYS, 0, 1);
adb0c954 SM	222	}
adb0c954 SM	223	EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
4c916a79	224
6fa1bcab AS	225	int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
6fa1bcab AS	226	enum mlx5_port_status status)
4c916a79 RS	227	{
	228	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	229	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	230
	231	memset(in, 0, sizeof(in));
	232
6fa1bcab	233	MLX5_SET(paos_reg, in, local_port, 1);
4c916a79 RS	234	MLX5_SET(paos_reg, in, admin_status, status);
	235	MLX5_SET(paos_reg, in, ase, 1);
	236
	237	return mlx5_core_access_reg(dev, in, sizeof(in), out,
	238	sizeof(out), MLX5_REG_PAOS, 0, 1);
	239	}
6fa1bcab	240	EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
4c916a79	241
6fa1bcab AS	242	int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
6fa1bcab AS	243	enum mlx5_port_status *status)
4c916a79 RS	244	{
	245	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	246	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	247	int err;
	248
	249	memset(in, 0, sizeof(in));
	250
6fa1bcab AS	251	MLX5_SET(paos_reg, in, local_port, 1);
6fa1bcab AS	252
4c916a79 RS	253	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
	254	sizeof(out), MLX5_REG_PAOS, 0, 0);
	255	if (err)
	256	return err;
	257
6fa1bcab	258	*status = MLX5_GET(paos_reg, out, admin_status);
6c3dbd2d	259	return 0;
4c916a79	260	}
6fa1bcab	261	EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
e725440e	262
facc9699 SM	263	static void mlx5_query_port_mtu(struct mlx5_core_dev dev, int admin_mtu,
facc9699 SM	264	int max_mtu, int oper_mtu, u8 port)
e725440e SM	265	{
	266	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	267	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
e725440e SM	268
	269	memset(in, 0, sizeof(in));
	270
facc9699	271	MLX5_SET(pmtu_reg, in, local_port, port);
e725440e	272
facc9699 SM	273	mlx5_core_access_reg(dev, in, sizeof(in), out,
facc9699 SM	274	sizeof(out), MLX5_REG_PMTU, 0, 0);
e725440e SM	275
	276	if (max_mtu)
	277	*max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
	278	if (oper_mtu)
	279	*oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
	280	if (admin_mtu)
	281	*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
e725440e SM	282	}
e725440e SM	283
facc9699	284	int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)
e725440e SM	285	{
	286	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	287	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
	288
	289	memset(in, 0, sizeof(in));
	290
	291	MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
facc9699	292	MLX5_SET(pmtu_reg, in, local_port, port);
e725440e	293
facc9699 SM	294	return mlx5_core_access_reg(dev, in, sizeof(in), out,
facc9699 SM	295	sizeof(out), MLX5_REG_PMTU, 0, 1);
e725440e SM	296	}
	297	EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
	298
facc9699 SM	299	void mlx5_query_port_max_mtu(struct mlx5_core_dev dev, int max_mtu,
facc9699 SM	300	u8 port)
e725440e	301	{
facc9699	302	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
e725440e SM	303	}
	304	EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
	305
facc9699 SM	306	void mlx5_query_port_oper_mtu(struct mlx5_core_dev dev, int oper_mtu,
facc9699 SM	307	u8 port)
e725440e	308	{
facc9699	309	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
e725440e SM	310	}
e725440e SM	311	EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
a124d13e MD	312
	313	static int mlx5_query_port_pvlc(struct mlx5_core_dev dev, u32 pvlc,
	314	int pvlc_size, u8 local_port)
	315	{
	316	u32 in[MLX5_ST_SZ_DW(pvlc_reg)];
a124d13e MD	317
a124d13e MD	318	memset(in, 0, sizeof(in));
13b79388	319	MLX5_SET(pvlc_reg, in, local_port, local_port);
a124d13e	320
6c3dbd2d AS	321	return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
6c3dbd2d AS	322	pvlc_size, MLX5_REG_PVLC, 0, 0);
a124d13e MD	323	}
	324
	325	int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
	326	u8 *vl_hw_cap, u8 local_port)
	327	{
	328	u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
	329	int err;
	330
	331	err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
	332	if (err)
	333	return err;
	334
	335	*vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
	336
	337	return 0;
	338	}
	339	EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
3c2d18ef	340
1c64bf6f MY	341	int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
	342	u8 port_num, void *out, size_t sz)
	343	{
	344	u32 *in;
	345	int err;
	346
	347	in = mlx5_vzalloc(sz);
	348	if (!in) {
	349	err = -ENOMEM;
	350	return err;
	351	}
	352
	353	MLX5_SET(ppcnt_reg, in, local_port, port_num);
	354
	355	MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
	356	err = mlx5_core_access_reg(dev, in, sz, out,
	357	sz, MLX5_REG_PPCNT, 0, 0);
	358
	359	kvfree(in);
	360	return err;
	361	}
	362	EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
	363
3c2d18ef AS	364	int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
	365	{
	366	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	367	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
3c2d18ef AS	368
	369	memset(in, 0, sizeof(in));
	370	MLX5_SET(pfcc_reg, in, local_port, 1);
	371	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
	372	MLX5_SET(pfcc_reg, in, pprx, rx_pause);
	373
6c3dbd2d AS	374	return mlx5_core_access_reg(dev, in, sizeof(in), out,
6c3dbd2d AS	375	sizeof(out), MLX5_REG_PFCC, 0, 1);
3c2d18ef AS	376	}
	377	EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
	378
	379	int mlx5_query_port_pause(struct mlx5_core_dev *dev,
	380	u32 rx_pause, u32 tx_pause)
	381	{
	382	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	383	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	384	int err;
	385
	386	memset(in, 0, sizeof(in));
	387	MLX5_SET(pfcc_reg, in, local_port, 1);
	388
	389	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
	390	sizeof(out), MLX5_REG_PFCC, 0, 0);
	391	if (err)
	392	return err;
	393
	394	if (rx_pause)
	395	*rx_pause = MLX5_GET(pfcc_reg, out, pprx);
	396
	397	if (tx_pause)
	398	*tx_pause = MLX5_GET(pfcc_reg, out, pptx);
	399
	400	return 0;
	401	}
	402	EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
ad909eb0 AS	403
	404	int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
	405	{
	406	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	407	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	408
	409	memset(in, 0, sizeof(in));
	410	MLX5_SET(pfcc_reg, in, local_port, 1);
	411	MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
	412	MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
	413	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
	414	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
	415
	416	return mlx5_core_access_reg(dev, in, sizeof(in), out,
	417	sizeof(out), MLX5_REG_PFCC, 0, 1);
	418	}
	419	EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
	420
	421	int mlx5_query_port_pfc(struct mlx5_core_dev dev, u8 pfc_en_tx, u8 *pfc_en_rx)
	422	{
	423	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	424	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	425	int err;
	426
	427	memset(in, 0, sizeof(in));
	428	MLX5_SET(pfcc_reg, in, local_port, 1);
	429
	430	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
	431	sizeof(out), MLX5_REG_PFCC, 0, 0);
	432	if (err)
	433	return err;
	434
	435	if (pfc_en_tx)
	436	*pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
	437
	438	if (pfc_en_rx)
	439	*pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
	440
	441	return 0;
	442	}
	443	EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
4f3961ee SM	444
	445	int mlx5_max_tc(struct mlx5_core_dev *mdev)
	446	{
	447	u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
	448
	449	return num_tc - 1;
	450	}
	451
	452	int mlx5_set_port_prio_tc(struct mlx5_core_dev mdev, u8 prio_tc)
	453	{
	454	u32 in[MLX5_ST_SZ_DW(qtct_reg)];
	455	u32 out[MLX5_ST_SZ_DW(qtct_reg)];
	456	int err;
	457	int i;
	458
	459	memset(in, 0, sizeof(in));
	460	for (i = 0; i < 8; i++) {
	461	if (prio_tc[i] > mlx5_max_tc(mdev))
	462	return -EINVAL;
	463
	464	MLX5_SET(qtct_reg, in, prio, i);
	465	MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
	466
	467	err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
	468	sizeof(out), MLX5_REG_QTCT, 0, 1);
	469	if (err)
	470	return err;
	471	}
	472
	473	return 0;
	474	}
	475	EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
	476
	477	static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev mdev, u32 in,
	478	int inlen)
	479	{
	480	u32 out[MLX5_ST_SZ_DW(qtct_reg)];
	481
	482	if (!MLX5_CAP_GEN(mdev, ets))
	483	return -ENOTSUPP;
	484
	485	return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
	486	MLX5_REG_QETCR, 0, 1);
	487	}
	488
d8880795 TT	489	static int mlx5_query_port_qetcr_reg(struct mlx5_core_dev mdev, u32 out,
	490	int outlen)
	491	{
	492	u32 in[MLX5_ST_SZ_DW(qtct_reg)];
	493
	494	if (!MLX5_CAP_GEN(mdev, ets))
	495	return -ENOTSUPP;
	496
	497	memset(in, 0, sizeof(in));
	498	return mlx5_core_access_reg(mdev, in, sizeof(in), out, outlen,
	499	MLX5_REG_QETCR, 0, 0);
	500	}
	501
4f3961ee SM	502	int mlx5_set_port_tc_group(struct mlx5_core_dev mdev, u8 tc_group)
	503	{
	504	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	505	int i;
	506
	507	memset(in, 0, sizeof(in));
	508
	509	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
	510	MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
	511	MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
	512	}
	513
	514	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
	515	}
	516	EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
	517
	518	int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev mdev, u8 tc_bw)
	519	{
	520	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	521	int i;
	522
	523	memset(in, 0, sizeof(in));
	524
	525	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
	526	MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
	527	MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
	528	}
	529
	530	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
	531	}
	532	EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
d8880795 TT	533
	534	int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
	535	u8 *max_bw_value,
	536	u8 *max_bw_units)
	537	{
	538	u32 in[MLX5_ST_SZ_DW(qetc_reg)];
	539	void *ets_tcn_conf;
	540	int i;
	541
	542	memset(in, 0, sizeof(in));
	543
	544	MLX5_SET(qetc_reg, in, port_number, 1);
	545
	546	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
	547	ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, in, tc_configuration[i]);
	548
	549	MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, r, 1);
	550	MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_units,
	551	max_bw_units[i]);
	552	MLX5_SET(ets_tcn_config_reg, ets_tcn_conf, max_bw_value,
	553	max_bw_value[i]);
	554	}
	555
	556	return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
	557	}
	558	EXPORT_SYMBOL_GPL(mlx5_modify_port_ets_rate_limit);
	559
	560	int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
	561	u8 *max_bw_value,
	562	u8 *max_bw_units)
	563	{
	564	u32 out[MLX5_ST_SZ_DW(qetc_reg)];
	565	void *ets_tcn_conf;
	566	int err;
	567	int i;
	568
	569	err = mlx5_query_port_qetcr_reg(mdev, out, sizeof(out));
	570	if (err)
	571	return err;
	572
	573	for (i = 0; i <= mlx5_max_tc(mdev); i++) {
	574	ets_tcn_conf = MLX5_ADDR_OF(qetc_reg, out, tc_configuration[i]);
	575
	576	max_bw_value[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
	577	max_bw_value);
	578	max_bw_units[i] = MLX5_GET(ets_tcn_config_reg, ets_tcn_conf,
	579	max_bw_units);
	580	}
	581
	582	return 0;
	583	}
	584	EXPORT_SYMBOL_GPL(mlx5_query_port_ets_rate_limit);
928cfe87 TT	585
	586	int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode)
	587	{
	588	u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
	589	u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];
	590
	591	memset(in, 0, sizeof(in));
	592	memset(out, 0, sizeof(out));
	593
	594	MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
	595	MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
	596	MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
	597
	598	return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
	599	out, sizeof(out));
	600	}
	601	EXPORT_SYMBOL_GPL(mlx5_set_port_wol);
	602
	603	int mlx5_query_port_wol(struct mlx5_core_dev mdev, u8 wol_mode)
	604	{
	605	u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
	606	u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
	607	int err;
	608
	609	memset(in, 0, sizeof(in));
	610	memset(out, 0, sizeof(out));
	611
	612	MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
	613
	614	err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
	615	out, sizeof(out));
	616
	617	if (!err)
	618	*wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
	619
	620	return err;
	621	}
	622	EXPORT_SYMBOL_GPL(mlx5_query_port_wol);
94cb1ebb EBE	623
	624	static int mlx5_query_ports_check(struct mlx5_core_dev mdev, u32 out,
	625	int outlen)
	626	{
	627	u32 in[MLX5_ST_SZ_DW(pcmr_reg)];
	628
	629	memset(in, 0, sizeof(in));
	630	MLX5_SET(pcmr_reg, in, local_port, 1);
	631
	632	return mlx5_core_access_reg(mdev, in, sizeof(in), out,
	633	outlen, MLX5_REG_PCMR, 0, 0);
	634	}
	635
	636	static int mlx5_set_ports_check(struct mlx5_core_dev mdev, u32 in, int inlen)
	637	{
	638	u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
	639
	640	return mlx5_core_access_reg(mdev, in, inlen, out,
	641	sizeof(out), MLX5_REG_PCMR, 0, 1);
	642	}
	643
	644	int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable)
	645	{
	646	u32 in[MLX5_ST_SZ_DW(pcmr_reg)];
	647
	648	memset(in, 0, sizeof(in));
	649	MLX5_SET(pcmr_reg, in, local_port, 1);
	650	MLX5_SET(pcmr_reg, in, fcs_chk, enable);
	651
	652	return mlx5_set_ports_check(mdev, in, sizeof(in));
	653	}
	654
	655	void mlx5_query_port_fcs(struct mlx5_core_dev mdev, bool supported,
	656	bool *enabled)
	657	{
	658	u32 out[MLX5_ST_SZ_DW(pcmr_reg)];
	659	/* Default values for FW which do not support MLX5_REG_PCMR */
	660	*supported = false;
	661	*enabled = true;
	662
	663	if (!MLX5_CAP_GEN(mdev, ports_check))
	664	return;
	665
	666	if (mlx5_query_ports_check(mdev, out, sizeof(out)))
	667	return;
	668
	669	*supported = !!(MLX5_GET(pcmr_reg, out, fcs_cap));
	670	*enabled = !!(MLX5_GET(pcmr_reg, out, fcs_chk));
	671	}