[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / port.c

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/module.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/cmd.h>
#include "mlx5_core.h"

int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
			 int size_in, void *data_out, int size_out,
			 u16 reg_num, int arg, int write)
{
	struct mlx5_access_reg_mbox_in *in = NULL;
	struct mlx5_access_reg_mbox_out *out = NULL;
	int err = -ENOMEM;

	in = mlx5_vzalloc(sizeof(*in) + size_in);
	if (!in)
		return -ENOMEM;

	out = mlx5_vzalloc(sizeof(*out) + size_out);
	if (!out)
		goto ex1;

	memcpy(in->data, data_in, size_in);
	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
	in->hdr.opmod = cpu_to_be16(!write);
	in->arg = cpu_to_be32(arg);
	in->register_id = cpu_to_be16(reg_num);
	err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
			    sizeof(*out) + size_out);
	if (err)
		goto ex2;

	if (out->hdr.status)
		err = mlx5_cmd_status_to_err(&out->hdr);

	if (!err)
		memcpy(data_out, out->data, size_out);

ex2:
	kvfree(out);
ex1:
	kvfree(in);
	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_access_reg);


struct mlx5_reg_pcap {
	u8			rsvd0;
	u8			port_num;
	u8			rsvd1[2];
	__be32			caps_127_96;
	__be32			caps_95_64;
	__be32			caps_63_32;
	__be32			caps_31_0;
};

int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
{
	struct mlx5_reg_pcap in;
	struct mlx5_reg_pcap out;

	memset(&in, 0, sizeof(in));
	in.caps_127_96 = cpu_to_be32(caps);
	in.port_num = port_num;

	return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
				    sizeof(out), MLX5_REG_PCAP, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_caps);

int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
			 int ptys_size, int proto_mask, u8 local_port)
{
	u32 in[MLX5_ST_SZ_DW(ptys_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(ptys_reg, in, local_port, local_port);
	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);

	return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
				    ptys_size, MLX5_REG_PTYS, 0, 0);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);

int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
			      u32 *proto_cap, int proto_mask)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
	else
		*proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);

int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
				u32 *proto_admin, int proto_mask)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
	else
		*proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);

int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
				    u8 *link_width_oper, u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
	if (err)
		return err;

	*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);

int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
			       u8 *proto_oper, int proto_mask,
			       u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	int err;

	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
	if (err)
		return err;

	if (proto_mask == MLX5_PTYS_EN)
		*proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
	else
		*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);

int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
			int proto_mask)
{
	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
	u32 out[MLX5_ST_SZ_DW(ptys_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(ptys_reg, in, local_port, 1);
	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
	if (proto_mask == MLX5_PTYS_EN)
		MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
	else
		MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PTYS, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_proto);

int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
			       enum mlx5_port_status status)
{
	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	u32 out[MLX5_ST_SZ_DW(paos_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(paos_reg, in, local_port, 1);
	MLX5_SET(paos_reg, in, admin_status, status);
	MLX5_SET(paos_reg, in, ase, 1);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PAOS, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);

int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
				 enum mlx5_port_status *status)
{
	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	int err;

	memset(in, 0, sizeof(in));

	MLX5_SET(paos_reg, in, local_port, 1);

	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PAOS, 0, 0);
	if (err)
		return err;

	*status = MLX5_GET(paos_reg, out, admin_status);
	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);

static void mlx5_query_port_mtu(struct mlx5_core_dev *dev, int *admin_mtu,
				int *max_mtu, int *oper_mtu, u8 port)
{
	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(pmtu_reg, in, local_port, port);

	mlx5_core_access_reg(dev, in, sizeof(in), out,
			     sizeof(out), MLX5_REG_PMTU, 0, 0);

	if (max_mtu)
		*max_mtu  = MLX5_GET(pmtu_reg, out, max_mtu);
	if (oper_mtu)
		*oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
	if (admin_mtu)
		*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
}

int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)
{
	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];

	memset(in, 0, sizeof(in));

	MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
	MLX5_SET(pmtu_reg, in, local_port, port);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PMTU, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);

void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu,
			     u8 port)
{
	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);

void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
			      u8 port)
{
	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
}
EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);

static int mlx5_query_port_pvlc(struct mlx5_core_dev *dev, u32 *pvlc,
				int pvlc_size,  u8 local_port)
{
	u32 in[MLX5_ST_SZ_DW(pvlc_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pvlc_reg, in, local_port, local_port);

	return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
				    pvlc_size, MLX5_REG_PVLC, 0, 0);
}

int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
			      u8 *vl_hw_cap, u8 local_port)
{
	u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
	int err;

	err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
	if (err)
		return err;

	*vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);

int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
			     u8 port_num, void *out, size_t sz)
{
	u32 *in;
	int err;

	in  = mlx5_vzalloc(sz);
	if (!in) {
		err = -ENOMEM;
		return err;
	}

	MLX5_SET(ppcnt_reg, in, local_port, port_num);

	MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
	err = mlx5_core_access_reg(dev, in, sz, out,
				   sz, MLX5_REG_PPCNT, 0, 0);

	kvfree(in);
	return err;
}
EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);

int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);
	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
	MLX5_SET(pfcc_reg, in, pprx, rx_pause);

	return mlx5_core_access_reg(dev, in, sizeof(in), out,
				    sizeof(out), MLX5_REG_PFCC, 0, 1);
}
EXPORT_SYMBOL_GPL(mlx5_set_port_pause);

int mlx5_query_port_pause(struct mlx5_core_dev *dev,
			  u32 *rx_pause, u32 *tx_pause)
{
	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	int err;

	memset(in, 0, sizeof(in));
	MLX5_SET(pfcc_reg, in, local_port, 1);

	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
				   sizeof(out), MLX5_REG_PFCC, 0, 0);
	if (err)
		return err;

	if (rx_pause)
		*rx_pause = MLX5_GET(pfcc_reg, out, pprx);

	if (tx_pause)
		*tx_pause = MLX5_GET(pfcc_reg, out, pptx);

	return 0;
}
EXPORT_SYMBOL_GPL(mlx5_query_port_pause);
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/module.h>
	34	#include <linux/mlx5/driver.h>
	35	#include <linux/mlx5/cmd.h>
	36	#include "mlx5_core.h"
	37
	38	int mlx5_core_access_reg(struct mlx5_core_dev dev, void data_in,
	39	int size_in, void *data_out, int size_out,
	40	u16 reg_num, int arg, int write)
	41	{
	42	struct mlx5_access_reg_mbox_in *in = NULL;
	43	struct mlx5_access_reg_mbox_out *out = NULL;
	44	int err = -ENOMEM;
	45
	46	in = mlx5_vzalloc(sizeof(*in) + size_in);
	47	if (!in)
	48	return -ENOMEM;
	49
	50	out = mlx5_vzalloc(sizeof(*out) + size_out);
	51	if (!out)
	52	goto ex1;
	53
	54	memcpy(in->data, data_in, size_in);
	55	in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
	56	in->hdr.opmod = cpu_to_be16(!write);
	57	in->arg = cpu_to_be32(arg);
	58	in->register_id = cpu_to_be16(reg_num);
	59	err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
e08a8761	60	sizeof(*out) + size_out);
e126ba97 EC	61	if (err)
	62	goto ex2;
	63
	64	if (out->hdr.status)
	65	err = mlx5_cmd_status_to_err(&out->hdr);
	66
	67	if (!err)
	68	memcpy(data_out, out->data, size_out);
	69
	70	ex2:
479163f4	71	kvfree(out);
e126ba97	72	ex1:
479163f4	73	kvfree(in);
e126ba97 EC	74	return err;
	75	}
	76	EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
	77
	78
	79	struct mlx5_reg_pcap {
	80	u8 rsvd0;
	81	u8 port_num;
	82	u8 rsvd1[2];
	83	__be32 caps_127_96;
	84	__be32 caps_95_64;
	85	__be32 caps_63_32;
	86	__be32 caps_31_0;
	87	};
	88
f241e749	89	int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
e126ba97 EC	90	{
	91	struct mlx5_reg_pcap in;
	92	struct mlx5_reg_pcap out;
e126ba97 EC	93
	94	memset(&in, 0, sizeof(in));
	95	in.caps_127_96 = cpu_to_be32(caps);
	96	in.port_num = port_num;
	97
6c3dbd2d AS	98	return mlx5_core_access_reg(dev, &in, sizeof(in), &out,
6c3dbd2d AS	99	sizeof(out), MLX5_REG_PCAP, 0, 1);
e126ba97 EC	100	}
e126ba97 EC	101	EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
adb0c954 SM	102
adb0c954 SM	103	int mlx5_query_port_ptys(struct mlx5_core_dev dev, u32 ptys,
a05bdefa	104	int ptys_size, int proto_mask, u8 local_port)
adb0c954 SM	105	{
adb0c954 SM	106	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
adb0c954 SM	107
adb0c954 SM	108	memset(in, 0, sizeof(in));
a05bdefa	109	MLX5_SET(ptys_reg, in, local_port, local_port);
adb0c954 SM	110	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
adb0c954 SM	111
6c3dbd2d AS	112	return mlx5_core_access_reg(dev, in, sizeof(in), ptys,
6c3dbd2d AS	113	ptys_size, MLX5_REG_PTYS, 0, 0);
adb0c954 SM	114	}
	115	EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
	116
	117	int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
	118	u32 *proto_cap, int proto_mask)
	119	{
	120	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	121	int err;
	122
a05bdefa	123	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
adb0c954 SM	124	if (err)
	125	return err;
	126
	127	if (proto_mask == MLX5_PTYS_EN)
	128	*proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
	129	else
	130	*proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
	131
	132	return 0;
	133	}
	134	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
	135
	136	int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
	137	u32 *proto_admin, int proto_mask)
	138	{
	139	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	140	int err;
	141
a05bdefa	142	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, 1);
adb0c954 SM	143	if (err)
	144	return err;
	145
	146	if (proto_mask == MLX5_PTYS_EN)
	147	*proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
	148	else
	149	*proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
	150
	151	return 0;
	152	}
	153	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
	154
a124d13e MD	155	int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
	156	u8 *link_width_oper, u8 local_port)
	157	{
	158	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	159	int err;
	160
	161	err = mlx5_query_port_ptys(dev, out, sizeof(out), MLX5_PTYS_IB, local_port);
	162	if (err)
	163	return err;
	164
	165	*link_width_oper = MLX5_GET(ptys_reg, out, ib_link_width_oper);
	166
	167	return 0;
	168	}
	169	EXPORT_SYMBOL_GPL(mlx5_query_port_link_width_oper);
	170
	171	int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
	172	u8 *proto_oper, int proto_mask,
	173	u8 local_port)
	174	{
	175	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
	176	int err;
	177
	178	err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask, local_port);
	179	if (err)
	180	return err;
	181
	182	if (proto_mask == MLX5_PTYS_EN)
	183	*proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
	184	else
	185	*proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
	186
	187	return 0;
	188	}
	189	EXPORT_SYMBOL_GPL(mlx5_query_port_proto_oper);
	190
adb0c954 SM	191	int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
	192	int proto_mask)
	193	{
	194	u32 in[MLX5_ST_SZ_DW(ptys_reg)];
	195	u32 out[MLX5_ST_SZ_DW(ptys_reg)];
adb0c954 SM	196
	197	memset(in, 0, sizeof(in));
	198
	199	MLX5_SET(ptys_reg, in, local_port, 1);
	200	MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
	201	if (proto_mask == MLX5_PTYS_EN)
	202	MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
	203	else
	204	MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
	205
6c3dbd2d AS	206	return mlx5_core_access_reg(dev, in, sizeof(in), out,
6c3dbd2d AS	207	sizeof(out), MLX5_REG_PTYS, 0, 1);
adb0c954 SM	208	}
adb0c954 SM	209	EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
4c916a79	210
6fa1bcab AS	211	int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
6fa1bcab AS	212	enum mlx5_port_status status)
4c916a79 RS	213	{
	214	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	215	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	216
	217	memset(in, 0, sizeof(in));
	218
6fa1bcab	219	MLX5_SET(paos_reg, in, local_port, 1);
4c916a79 RS	220	MLX5_SET(paos_reg, in, admin_status, status);
	221	MLX5_SET(paos_reg, in, ase, 1);
	222
	223	return mlx5_core_access_reg(dev, in, sizeof(in), out,
	224	sizeof(out), MLX5_REG_PAOS, 0, 1);
	225	}
6fa1bcab	226	EXPORT_SYMBOL_GPL(mlx5_set_port_admin_status);
4c916a79	227
6fa1bcab AS	228	int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
6fa1bcab AS	229	enum mlx5_port_status *status)
4c916a79 RS	230	{
	231	u32 in[MLX5_ST_SZ_DW(paos_reg)];
	232	u32 out[MLX5_ST_SZ_DW(paos_reg)];
	233	int err;
	234
	235	memset(in, 0, sizeof(in));
	236
6fa1bcab AS	237	MLX5_SET(paos_reg, in, local_port, 1);
6fa1bcab AS	238
4c916a79 RS	239	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
	240	sizeof(out), MLX5_REG_PAOS, 0, 0);
	241	if (err)
	242	return err;
	243
6fa1bcab	244	*status = MLX5_GET(paos_reg, out, admin_status);
6c3dbd2d	245	return 0;
4c916a79	246	}
6fa1bcab	247	EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
e725440e	248
facc9699 SM	249	static void mlx5_query_port_mtu(struct mlx5_core_dev dev, int admin_mtu,
facc9699 SM	250	int max_mtu, int oper_mtu, u8 port)
e725440e SM	251	{
	252	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	253	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
e725440e SM	254
	255	memset(in, 0, sizeof(in));
	256
facc9699	257	MLX5_SET(pmtu_reg, in, local_port, port);
e725440e	258
facc9699 SM	259	mlx5_core_access_reg(dev, in, sizeof(in), out,
facc9699 SM	260	sizeof(out), MLX5_REG_PMTU, 0, 0);
e725440e SM	261
	262	if (max_mtu)
	263	*max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
	264	if (oper_mtu)
	265	*oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
	266	if (admin_mtu)
	267	*admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
e725440e SM	268	}
e725440e SM	269
facc9699	270	int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port)
e725440e SM	271	{
	272	u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
	273	u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
	274
	275	memset(in, 0, sizeof(in));
	276
	277	MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
facc9699	278	MLX5_SET(pmtu_reg, in, local_port, port);
e725440e	279
facc9699 SM	280	return mlx5_core_access_reg(dev, in, sizeof(in), out,
facc9699 SM	281	sizeof(out), MLX5_REG_PMTU, 0, 1);
e725440e SM	282	}
	283	EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
	284
facc9699 SM	285	void mlx5_query_port_max_mtu(struct mlx5_core_dev dev, int max_mtu,
facc9699 SM	286	u8 port)
e725440e	287	{
facc9699	288	mlx5_query_port_mtu(dev, NULL, max_mtu, NULL, port);
e725440e SM	289	}
	290	EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
	291
facc9699 SM	292	void mlx5_query_port_oper_mtu(struct mlx5_core_dev dev, int oper_mtu,
facc9699 SM	293	u8 port)
e725440e	294	{
facc9699	295	mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu, port);
e725440e SM	296	}
e725440e SM	297	EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
a124d13e MD	298
	299	static int mlx5_query_port_pvlc(struct mlx5_core_dev dev, u32 pvlc,
	300	int pvlc_size, u8 local_port)
	301	{
	302	u32 in[MLX5_ST_SZ_DW(pvlc_reg)];
a124d13e MD	303
a124d13e MD	304	memset(in, 0, sizeof(in));
13b79388	305	MLX5_SET(pvlc_reg, in, local_port, local_port);
a124d13e	306
6c3dbd2d AS	307	return mlx5_core_access_reg(dev, in, sizeof(in), pvlc,
6c3dbd2d AS	308	pvlc_size, MLX5_REG_PVLC, 0, 0);
a124d13e MD	309	}
	310
	311	int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
	312	u8 *vl_hw_cap, u8 local_port)
	313	{
	314	u32 out[MLX5_ST_SZ_DW(pvlc_reg)];
	315	int err;
	316
	317	err = mlx5_query_port_pvlc(dev, out, sizeof(out), local_port);
	318	if (err)
	319	return err;
	320
	321	*vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
	322
	323	return 0;
	324	}
	325	EXPORT_SYMBOL_GPL(mlx5_query_port_vl_hw_cap);
3c2d18ef	326
1c64bf6f MY	327	int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
	328	u8 port_num, void *out, size_t sz)
	329	{
	330	u32 *in;
	331	int err;
	332
	333	in = mlx5_vzalloc(sz);
	334	if (!in) {
	335	err = -ENOMEM;
	336	return err;
	337	}
	338
	339	MLX5_SET(ppcnt_reg, in, local_port, port_num);
	340
	341	MLX5_SET(ppcnt_reg, in, grp, MLX5_INFINIBAND_PORT_COUNTERS_GROUP);
	342	err = mlx5_core_access_reg(dev, in, sz, out,
	343	sz, MLX5_REG_PPCNT, 0, 0);
	344
	345	kvfree(in);
	346	return err;
	347	}
	348	EXPORT_SYMBOL_GPL(mlx5_core_query_ib_ppcnt);
	349
3c2d18ef AS	350	int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause)
	351	{
	352	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	353	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
3c2d18ef AS	354
	355	memset(in, 0, sizeof(in));
	356	MLX5_SET(pfcc_reg, in, local_port, 1);
	357	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
	358	MLX5_SET(pfcc_reg, in, pprx, rx_pause);
	359
6c3dbd2d AS	360	return mlx5_core_access_reg(dev, in, sizeof(in), out,
6c3dbd2d AS	361	sizeof(out), MLX5_REG_PFCC, 0, 1);
3c2d18ef AS	362	}
	363	EXPORT_SYMBOL_GPL(mlx5_set_port_pause);
	364
	365	int mlx5_query_port_pause(struct mlx5_core_dev *dev,
	366	u32 rx_pause, u32 tx_pause)
	367	{
	368	u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
	369	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
	370	int err;
	371
	372	memset(in, 0, sizeof(in));
	373	MLX5_SET(pfcc_reg, in, local_port, 1);
	374
	375	err = mlx5_core_access_reg(dev, in, sizeof(in), out,
	376	sizeof(out), MLX5_REG_PFCC, 0, 0);
	377	if (err)
	378	return err;
	379
	380	if (rx_pause)
	381	*rx_pause = MLX5_GET(pfcc_reg, out, pprx);
	382
	383	if (tx_pause)
	384	*tx_pause = MLX5_GET(pfcc_reg, out, pptx);
	385
	386	return 0;
	387	}
	388	EXPORT_SYMBOL_GPL(mlx5_query_port_pause);