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mlx5: no need to check return value of debugfs_create functions
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / mlx5_core.h
CommitLineData
e126ba97 1/*
f62b8bb8 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef __MLX5_CORE_H__
34#define __MLX5_CORE_H__
35
36#include <linux/types.h>
37#include <linux/kernel.h>
38#include <linux/sched.h>
81848731 39#include <linux/if_link.h>
62bd22cf 40#include <linux/firmware.h>
4a0475d5 41#include <linux/ptp_clock_kernel.h>
d5c07157 42#include <linux/mlx5/cq.h>
31ca3648 43#include <linux/mlx5/fs.h>
27b942fb 44#include <linux/mlx5/driver.h>
e126ba97 45
f62b8bb8 46#define DRIVER_NAME "mlx5_core"
7913d205 47#define DRIVER_VERSION "5.0-0"
f62b8bb8 48
f663ad98 49extern uint mlx5_core_debug_mask;
e126ba97 50
5a788398 51#define mlx5_core_dbg(__dev, format, ...) \
27b942fb 52 dev_dbg((__dev)->device, "%s:%d:(pid %d): " format, \
9e5b2fc1 53 __func__, __LINE__, current->pid, \
1a91de28 54 ##__VA_ARGS__)
e126ba97 55
27b942fb
PP		 56#define mlx5_core_dbg_once(__dev, format, ...) \
57 dev_dbg_once((__dev)->device, \
58 "%s:%d:(pid %d): " format, \
59 __func__, __LINE__, current->pid, \
0608d4db
TT		 60 ##__VA_ARGS__)
61
27b942fb
PP		 62#define mlx5_core_dbg_mask(__dev, mask, format, ...) \
63do { \
64 if ((mask) & mlx5_core_debug_mask) \
65 mlx5_core_dbg(__dev, format, ##__VA_ARGS__); \
e126ba97
EC		 66} while (0)
67
27b942fb
PP		 68#define mlx5_core_err(__dev, format, ...) \
69 dev_err((__dev)->device, "%s:%d:(pid %d): " format, \
70 __func__, __LINE__, current->pid, \
1a91de28 71 ##__VA_ARGS__)
e126ba97 72
27b942fb
PP		 73#define mlx5_core_err_rl(__dev, format, ...) \
74 dev_err_ratelimited((__dev)->device, \
75 "%s:%d:(pid %d): " format, \
76 __func__, __LINE__, current->pid, \
77 ##__VA_ARGS__)
b30408d7 78
27b942fb
PP		 79#define mlx5_core_warn(__dev, format, ...) \
80 dev_warn((__dev)->device, "%s:%d:(pid %d): " format, \
81 __func__, __LINE__, current->pid, \
82 ##__VA_ARGS__)
e126ba97 83
0f597ed4 84#define mlx5_core_warn_once(__dev, format, ...) \
27b942fb 85 dev_warn_once((__dev)->device, "%s:%d:(pid %d): " format, \
0f597ed4
SM		 86 __func__, __LINE__, current->pid, \
87 ##__VA_ARGS__)
88
27b942fb
PP		 89#define mlx5_core_warn_rl(__dev, format, ...) \
90 dev_warn_ratelimited((__dev)->device, \
91 "%s:%d:(pid %d): " format, \
92 __func__, __LINE__, current->pid, \
93 ##__VA_ARGS__)
3732b972 94
27b942fb
PP		 95#define mlx5_core_info(__dev, format, ...) \
96 dev_info((__dev)->device, format, ##__VA_ARGS__)
108805fc 97
27b942fb
PP		 98#define mlx5_core_info_rl(__dev, format, ...) \
99 dev_info_ratelimited((__dev)->device, \
100 "%s:%d:(pid %d): " format, \
101 __func__, __LINE__, current->pid, \
102 ##__VA_ARGS__)
108805fc 103
e126ba97
EC		 104enum {
105 MLX5_CMD_DATA, /* print command payload only */
106 MLX5_CMD_TIME, /* print command execution time */
107};
108
f9c14e46
KH		 109enum {
110 MLX5_DRIVER_STATUS_ABORTED = 0xfe,
111 MLX5_DRIVER_SYND = 0xbadd00de,
112};
113
1ef6f1a1
FD		 114enum mlx5_semaphore_space_address {
115 MLX5_SEMAPHORE_SPACE_DOMAIN = 0xA,
3e5b72ac 116 MLX5_SEMAPHORE_SW_RESET = 0x20,
1ef6f1a1
FD		 117};
118
938fe83c 119int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
211e6c80 120int mlx5_query_board_id(struct mlx5_core_dev *dev);
8737f818 121int mlx5_cmd_init_hca(struct mlx5_core_dev *dev, uint32_t *sw_owner_id);
e126ba97 122int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
8812c24d 123int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev);
fcd29ad1 124int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev);
8812c24d 125void mlx5_enter_error_state(struct mlx5_core_dev *dev, bool force);
3e5b72ac 126void mlx5_error_sw_reset(struct mlx5_core_dev *dev);
89d44f0a 127void mlx5_disable_device(struct mlx5_core_dev *dev);
04c0c1ab 128void mlx5_recover_device(struct mlx5_core_dev *dev);
6b6adee3
MHY		 129int mlx5_sriov_init(struct mlx5_core_dev *dev);
130void mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
acab721b
MHY		 131int mlx5_sriov_attach(struct mlx5_core_dev *dev);
132void mlx5_sriov_detach(struct mlx5_core_dev *dev);
fc50db98 133int mlx5_core_sriov_configure(struct pci_dev *dev, int num_vfs);
0b107106
EC		 134int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id);
135int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id);
813f8540
MHY		 136int mlx5_create_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
137 void *context, u32 *element_id);
138int mlx5_modify_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
139 void *context, u32 element_id,
140 u32 modify_bitmask);
141int mlx5_destroy_scheduling_element_cmd(struct mlx5_core_dev *dev, u8 hierarchy,
142 u32 element_id);
591905ba 143int mlx5_wait_for_pages(struct mlx5_core_dev *dev, int *pages);
4a0475d5
ML		 144u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev,
145 struct ptp_system_timestamp *sts);
d5c07157 146
71edc69c 147void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev);
4cab346b 148void mlx5_cmd_flush(struct mlx5_core_dev *dev);
9f818c8a 149void mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
3ec5693b 150void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
e126ba97 151
c835ad64
GP		 152int mlx5_query_pcam_reg(struct mlx5_core_dev *dev, u32 *pcam, u8 feature_group,
153 u8 access_reg_group);
154int mlx5_query_mcam_reg(struct mlx5_core_dev *dev, u32 *mcap, u8 feature_group,
155 u8 access_reg_group);
c02762eb
HN		 156int mlx5_query_qcam_reg(struct mlx5_core_dev *mdev, u32 *qcam,
157 u8 feature_group, u8 access_reg_group);
c835ad64 158
7907f23a
AH		 159void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev);
160void mlx5_lag_remove(struct mlx5_core_dev *dev);
161
561aa15a
YA		 162int mlx5_irq_table_init(struct mlx5_core_dev *dev);
163void mlx5_irq_table_cleanup(struct mlx5_core_dev *dev);
e1706e62
YA		 164int mlx5_irq_table_create(struct mlx5_core_dev *dev);
165void mlx5_irq_table_destroy(struct mlx5_core_dev *dev);
256cf690
YA		 166int mlx5_irq_attach_nb(struct mlx5_irq_table *irq_table, int vecidx,
167 struct notifier_block *nb);
168int mlx5_irq_detach_nb(struct mlx5_irq_table *irq_table, int vecidx,
169 struct notifier_block *nb);
170struct cpumask *
171mlx5_irq_get_affinity_mask(struct mlx5_irq_table *irq_table, int vecidx);
172struct cpu_rmap *mlx5_irq_get_rmap(struct mlx5_irq_table *table);
173int mlx5_irq_get_num_comp(struct mlx5_irq_table *table);
561aa15a 174
69c1280b
SM		 175int mlx5_events_init(struct mlx5_core_dev *dev);
176void mlx5_events_cleanup(struct mlx5_core_dev *dev);
177void mlx5_events_start(struct mlx5_core_dev *dev);
178void mlx5_events_stop(struct mlx5_core_dev *dev);
179
f1ee87fe
MHY		 180void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
181void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv);
182void mlx5_attach_device(struct mlx5_core_dev *dev);
183void mlx5_detach_device(struct mlx5_core_dev *dev);
184bool mlx5_device_registered(struct mlx5_core_dev *dev);
185int mlx5_register_device(struct mlx5_core_dev *dev);
186void mlx5_unregister_device(struct mlx5_core_dev *dev);
7907f23a
AH		 187void mlx5_add_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
188void mlx5_remove_dev_by_protocol(struct mlx5_core_dev *dev, int protocol);
f1ee87fe
MHY		 189struct mlx5_core_dev *mlx5_get_next_phys_dev(struct mlx5_core_dev *dev);
190void mlx5_dev_list_lock(void);
191void mlx5_dev_list_unlock(void);
192int mlx5_dev_list_trylock(void);
2de24fed 193
917b41aa
AH		 194bool mlx5_lag_intf_add(struct mlx5_interface *intf, struct mlx5_priv *priv);
195
f9a1ef72
EE		 196int mlx5_query_mtpps(struct mlx5_core_dev *dev, u32 *mtpps, u32 mtpps_size);
197int mlx5_set_mtpps(struct mlx5_core_dev *mdev, u32 *mtpps, u32 mtpps_size);
198int mlx5_query_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 *arm, u8 *mode);
199int mlx5_set_mtppse(struct mlx5_core_dev *mdev, u8 pin, u8 arm, u8 mode);
200
fa367688
EE		 201#define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
202 MLX5_CAP_GEN((mdev), pps_modify) && \
203 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_fs) && \
204 MLX5_CAP_MCAM_FEATURE((mdev), mtpps_enh_out_per_adj))
205
44f18db5
JP		 206int mlx5_firmware_flash(struct mlx5_core_dev *dev, const struct firmware *fw,
207 struct netlink_ext_ack *extack);
9c86b07e
SA		 208int mlx5_fw_version_query(struct mlx5_core_dev *dev,
209 u32 *running_ver, u32 *stored_ver);
62bd22cf 210
f62b8bb8
AV		 211void mlx5e_init(void);
212void mlx5e_cleanup(void);
213
eb5cc431
PP		 214static inline bool mlx5_sriov_is_enabled(struct mlx5_core_dev *dev)
215{
216 return pci_num_vf(dev->pdev) ? true : false;
217}
218
db60b802
AH		 219static inline int mlx5_lag_is_lacp_owner(struct mlx5_core_dev *dev)
220{
221 /* LACP owner conditions:
222 * 1) Function is physical.
223 * 2) LAG is supported by FW.
224 * 3) LAG is managed by driver (currently the only option).
225 */
226 return MLX5_CAP_GEN(dev, vport_group_manager) &&
227 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) &&
228 MLX5_CAP_GEN(dev, lag_master);
229}
230
c5447c70 231void mlx5_reload_interface(struct mlx5_core_dev *mdev, int protocol);
eff849b2 232void mlx5_lag_update(struct mlx5_core_dev *dev);
fcd29ad1
FD		 233
234enum {
235 MLX5_NIC_IFC_FULL = 0,
236 MLX5_NIC_IFC_DISABLED = 1,
237 MLX5_NIC_IFC_NO_DRAM_NIC = 2,
63cbc552 238 MLX5_NIC_IFC_SW_RESET = 7
fcd29ad1
FD		 239};
240
241u8 mlx5_get_nic_state(struct mlx5_core_dev *dev);
242void mlx5_set_nic_state(struct mlx5_core_dev *dev, u8 state);
e126ba97 243#endif /* __MLX5_CORE_H__ */
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