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net/mlx5: Extend mlx5_core to support ConnectX-4 Ethernet functionality
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e126ba97
EC		 42#include <linux/mlx5/driver.h>
43#include <linux/mlx5/cq.h>
44#include <linux/mlx5/qp.h>
45#include <linux/mlx5/srq.h>
46#include <linux/debugfs.h>
f66f049f 47#include <linux/kmod.h>
b775516b 48#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 49#include "mlx5_core.h"
50
e126ba97 51MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 52MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 53MODULE_LICENSE("Dual BSD/GPL");
54MODULE_VERSION(DRIVER_VERSION);
55
56int mlx5_core_debug_mask;
57module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
58MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59
9603b61d
JM		 60#define MLX5_DEFAULT_PROF 2
61static int prof_sel = MLX5_DEFAULT_PROF;
62module_param_named(prof_sel, prof_sel, int, 0444);
63MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64
e126ba97 65struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 66static LIST_HEAD(intf_list);
67static LIST_HEAD(dev_list);
68static DEFINE_MUTEX(intf_mutex);
69
70struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
73 void *context;
74};
75
76static struct mlx5_profile profile[] = {
77 [0] = {
78 .mask = 0,
79 },
80 [1] = {
81 .mask = MLX5_PROF_MASK_QP_SIZE,
82 .log_max_qp = 12,
83 },
84 [2] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE |
86 MLX5_PROF_MASK_MR_CACHE,
87 .log_max_qp = 17,
88 .mr_cache[0] = {
89 .size = 500,
90 .limit = 250
91 },
92 .mr_cache[1] = {
93 .size = 500,
94 .limit = 250
95 },
96 .mr_cache[2] = {
97 .size = 500,
98 .limit = 250
99 },
100 .mr_cache[3] = {
101 .size = 500,
102 .limit = 250
103 },
104 .mr_cache[4] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[5] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[6] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[7] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[8] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[9] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[10] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[11] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[12] = {
137 .size = 64,
138 .limit = 32
139 },
140 .mr_cache[13] = {
141 .size = 32,
142 .limit = 16
143 },
144 .mr_cache[14] = {
145 .size = 16,
146 .limit = 8
147 },
148 .mr_cache[15] = {
149 .size = 8,
150 .limit = 4
151 },
152 },
153};
e126ba97
EC		 154
155static int set_dma_caps(struct pci_dev *pdev)
156{
157 int err;
158
159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
160 if (err) {
1a91de28 161 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
163 if (err) {
1a91de28 164 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 165 return err;
166 }
167 }
168
169 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
170 if (err) {
171 dev_warn(&pdev->dev,
1a91de28 172 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
174 if (err) {
175 dev_err(&pdev->dev,
1a91de28 176 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 177 return err;
178 }
179 }
180
181 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
182 return err;
183}
184
185static int request_bar(struct pci_dev *pdev)
186{
187 int err = 0;
188
189 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 190 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 191 return -ENODEV;
192 }
193
194 err = pci_request_regions(pdev, DRIVER_NAME);
195 if (err)
196 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
197
198 return err;
199}
200
201static void release_bar(struct pci_dev *pdev)
202{
203 pci_release_regions(pdev);
204}
205
206static int mlx5_enable_msix(struct mlx5_core_dev *dev)
207{
db058a18
SM		 208 struct mlx5_priv *priv = &dev->priv;
209 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 210 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 211 int nvec;
e126ba97
EC		 212 int i;
213
938fe83c
SM		 214 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
215 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 216 nvec = min_t(int, nvec, num_eqs);
217 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
218 return -ENOMEM;
219
db058a18
SM		 220 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
221
222 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
223 if (!priv->msix_arr || !priv->irq_info)
224 goto err_free_msix;
e126ba97
EC		 225
226 for (i = 0; i < nvec; i++)
db058a18 227 priv->msix_arr[i].entry = i;
e126ba97 228
db058a18 229 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 230 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 231 if (nvec < 0)
232 return nvec;
e126ba97 233
f3c9407b 234 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 235
236 return 0;
db058a18
SM		 237
238err_free_msix:
239 kfree(priv->irq_info);
240 kfree(priv->msix_arr);
241 return -ENOMEM;
e126ba97
EC		 242}
243
244static void mlx5_disable_msix(struct mlx5_core_dev *dev)
245{
db058a18 246 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 247
248 pci_disable_msix(dev->pdev);
db058a18
SM		 249 kfree(priv->irq_info);
250 kfree(priv->msix_arr);
e126ba97
EC		 251}
252
253struct mlx5_reg_host_endianess {
254 u8 he;
255 u8 rsvd[15];
256};
257
87b8de49
EC		 258
259#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
260
261enum {
c7a08ac7
EC		 262 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
263 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 264};
265
c7a08ac7
EC		 266static u16 to_fw_pkey_sz(u32 size)
267{
268 switch (size) {
269 case 128:
270 return 0;
271 case 256:
272 return 1;
273 case 512:
274 return 2;
275 case 1024:
276 return 3;
277 case 2048:
278 return 4;
279 case 4096:
280 return 5;
281 default:
282 pr_warn("invalid pkey table size %d\n", size);
283 return 0;
284 }
285}
286
938fe83c 287static u16 to_sw_pkey_sz(int pkey_sz)
c7a08ac7 288{
938fe83c 289 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
c7a08ac7 290 return 0;
87b8de49 291
938fe83c 292 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
c7a08ac7
EC		 293}
294
938fe83c
SM		 295int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
296 enum mlx5_cap_mode cap_mode)
c7a08ac7 297{
b775516b
EC		 298 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
299 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 300 void *out, *hca_caps;
301 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 302 int err;
303
b775516b
EC		 304 memset(in, 0, sizeof(in));
305 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 306 if (!out)
e126ba97 307 return -ENOMEM;
938fe83c 308
b775516b
EC		 309 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
310 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
311 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
312 if (err)
313 goto query_ex;
e126ba97 314
b775516b 315 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 316 if (err) {
938fe83c
SM		 317 mlx5_core_warn(dev,
318 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
319 cap_type, cap_mode, err);
e126ba97
EC		 320 goto query_ex;
321 }
c7a08ac7 322
938fe83c
SM		 323 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
324
325 switch (cap_mode) {
326 case HCA_CAP_OPMOD_GET_MAX:
327 memcpy(dev->hca_caps_max[cap_type], hca_caps,
328 MLX5_UN_SZ_BYTES(hca_cap_union));
329 break;
330 case HCA_CAP_OPMOD_GET_CUR:
331 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
332 MLX5_UN_SZ_BYTES(hca_cap_union));
333 break;
334 default:
335 mlx5_core_warn(dev,
336 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
337 cap_type, cap_mode);
338 err = -EINVAL;
339 break;
340 }
c7a08ac7
EC		 341query_ex:
342 kfree(out);
343 return err;
344}
345
b775516b 346static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 347{
b775516b 348 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 349 int err;
350
b775516b 351 memset(out, 0, sizeof(out));
e126ba97 352
b775516b
EC		 353 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
354 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 355 if (err)
c7a08ac7 356 return err;
e126ba97 357
b775516b 358 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 359
360 return err;
361}
362
363static int handle_hca_cap(struct mlx5_core_dev *dev)
364{
b775516b 365 void *set_ctx = NULL;
c7a08ac7 366 struct mlx5_profile *prof = dev->profile;
c7a08ac7 367 int err = -ENOMEM;
b775516b 368 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 369 void *set_hca_cap;
c7a08ac7 370
b775516b 371 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 372 if (!set_ctx)
e126ba97 373 goto query_ex;
e126ba97 374
938fe83c 375 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 376 if (err)
e126ba97 377 goto query_ex;
e126ba97 378
938fe83c 379 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 380 if (err)
381 goto query_ex;
382
938fe83c
SM		 383 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
384 capability);
385 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
386 MLX5_ST_SZ_BYTES(cmd_hca_cap));
387
388 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
389 to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
390 128);
c7a08ac7 391 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 392 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
393 to_fw_pkey_sz(128));
c7a08ac7
EC		 394
395 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 396 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
397 prof->log_max_qp);
c7a08ac7 398
938fe83c
SM		 399 /* disable cmdif checksum */
400 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 401
b775516b 402 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 403
e126ba97 404query_ex:
e126ba97 405 kfree(set_ctx);
e126ba97
EC		 406 return err;
407}
408
409static int set_hca_ctrl(struct mlx5_core_dev *dev)
410{
411 struct mlx5_reg_host_endianess he_in;
412 struct mlx5_reg_host_endianess he_out;
413 int err;
414
415 memset(&he_in, 0, sizeof(he_in));
416 he_in.he = MLX5_SET_HOST_ENDIANNESS;
417 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
418 &he_out, sizeof(he_out),
419 MLX5_REG_HOST_ENDIANNESS, 0, 1);
420 return err;
421}
422
cd23b14b
EC		 423static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
424{
425 int err;
426 struct mlx5_enable_hca_mbox_in in;
427 struct mlx5_enable_hca_mbox_out out;
428
429 memset(&in, 0, sizeof(in));
430 memset(&out, 0, sizeof(out));
431 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
432 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
433 if (err)
434 return err;
435
436 if (out.hdr.status)
437 return mlx5_cmd_status_to_err(&out.hdr);
438
439 return 0;
440}
441
442static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
443{
444 int err;
445 struct mlx5_disable_hca_mbox_in in;
446 struct mlx5_disable_hca_mbox_out out;
447
448 memset(&in, 0, sizeof(in));
449 memset(&out, 0, sizeof(out));
450 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
451 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
452 if (err)
453 return err;
454
455 if (out.hdr.status)
456 return mlx5_cmd_status_to_err(&out.hdr);
457
458 return 0;
459}
460
db058a18
SM		 461static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
462{
463 struct mlx5_priv *priv = &mdev->priv;
464 struct msix_entry *msix = priv->msix_arr;
465 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
466 int numa_node = dev_to_node(&mdev->pdev->dev);
467 int err;
468
469 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
470 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
471 return -ENOMEM;
472 }
473
474 err = cpumask_set_cpu_local_first(i, numa_node, priv->irq_info[i].mask);
475 if (err) {
476 mlx5_core_warn(mdev, "cpumask_set_cpu_local_first failed");
477 goto err_clear_mask;
478 }
479
480 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
481 if (err) {
482 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
483 irq);
484 goto err_clear_mask;
485 }
486
487 return 0;
488
489err_clear_mask:
490 free_cpumask_var(priv->irq_info[i].mask);
491 return err;
492}
493
494static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
495{
496 struct mlx5_priv *priv = &mdev->priv;
497 struct msix_entry *msix = priv->msix_arr;
498 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
499
500 irq_set_affinity_hint(irq, NULL);
501 free_cpumask_var(priv->irq_info[i].mask);
502}
503
504static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
505{
506 int err;
507 int i;
508
509 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
510 err = mlx5_irq_set_affinity_hint(mdev, i);
511 if (err)
512 goto err_out;
513 }
514
515 return 0;
516
517err_out:
518 for (i--; i >= 0; i--)
519 mlx5_irq_clear_affinity_hint(mdev, i);
520
521 return err;
522}
523
524static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
525{
526 int i;
527
528 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
529 mlx5_irq_clear_affinity_hint(mdev, i);
530}
531
233d05d2
SM		 532int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
533{
534 struct mlx5_eq_table *table = &dev->priv.eq_table;
535 struct mlx5_eq *eq, *n;
536 int err = -ENOENT;
537
538 spin_lock(&table->lock);
539 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
540 if (eq->index == vector) {
541 *eqn = eq->eqn;
542 *irqn = eq->irqn;
543 err = 0;
544 break;
545 }
546 }
547 spin_unlock(&table->lock);
548
549 return err;
550}
551EXPORT_SYMBOL(mlx5_vector2eqn);
552
553static void free_comp_eqs(struct mlx5_core_dev *dev)
554{
555 struct mlx5_eq_table *table = &dev->priv.eq_table;
556 struct mlx5_eq *eq, *n;
557
558 spin_lock(&table->lock);
559 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
560 list_del(&eq->list);
561 spin_unlock(&table->lock);
562 if (mlx5_destroy_unmap_eq(dev, eq))
563 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
564 eq->eqn);
565 kfree(eq);
566 spin_lock(&table->lock);
567 }
568 spin_unlock(&table->lock);
569}
570
571static int alloc_comp_eqs(struct mlx5_core_dev *dev)
572{
573 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 574 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 575 struct mlx5_eq *eq;
576 int ncomp_vec;
577 int nent;
578 int err;
579 int i;
580
581 INIT_LIST_HEAD(&table->comp_eqs_list);
582 ncomp_vec = table->num_comp_vectors;
583 nent = MLX5_COMP_EQ_SIZE;
584 for (i = 0; i < ncomp_vec; i++) {
585 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
586 if (!eq) {
587 err = -ENOMEM;
588 goto clean;
589 }
590
db058a18 591 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 592 err = mlx5_create_map_eq(dev, eq,
593 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
594 name, &dev->priv.uuari.uars[0]);
595 if (err) {
596 kfree(eq);
597 goto clean;
598 }
599 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
600 eq->index = i;
601 spin_lock(&table->lock);
602 list_add_tail(&eq->list, &table->comp_eqs_list);
603 spin_unlock(&table->lock);
604 }
605
606 return 0;
607
608clean:
609 free_comp_eqs(dev);
610 return err;
611}
612
f62b8bb8
AV		 613#ifdef CONFIG_MLX5_CORE_EN
614static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
615{
616 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
617 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
618 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
619 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
620 int err;
621 u32 sup_issi;
622
623 memset(query_in, 0, sizeof(query_in));
624 memset(query_out, 0, sizeof(query_out));
625
626 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
627
628 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
629 query_out, sizeof(query_out));
630 if (err) {
631 if (((struct mlx5_outbox_hdr *)query_out)->status ==
632 MLX5_CMD_STAT_BAD_OP_ERR) {
633 pr_debug("Only ISSI 0 is supported\n");
634 return 0;
635 }
636
637 pr_err("failed to query ISSI\n");
638 return err;
639 }
640
641 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
642
643 if (sup_issi & (1 << 1)) {
644 memset(set_in, 0, sizeof(set_in));
645 memset(set_out, 0, sizeof(set_out));
646
647 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
648 MLX5_SET(set_issi_in, set_in, current_issi, 1);
649
650 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
651 set_out, sizeof(set_out));
652 if (err) {
653 pr_err("failed to set ISSI=1\n");
654 return err;
655 }
656
657 dev->issi = 1;
658
659 return 0;
660 } else if (sup_issi & (1 << 0)) {
661 return 0;
662 }
663
664 return -ENOTSUPP;
665}
666#endif
667
9603b61d 668static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 669{
670 struct mlx5_priv *priv = &dev->priv;
671 int err;
672
673 dev->pdev = pdev;
674 pci_set_drvdata(dev->pdev, dev);
675 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
676 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
677
678 mutex_init(&priv->pgdir_mutex);
679 INIT_LIST_HEAD(&priv->pgdir_list);
680 spin_lock_init(&priv->mkey_lock);
681
682 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
683 if (!priv->dbg_root)
684 return -ENOMEM;
685
686 err = pci_enable_device(pdev);
687 if (err) {
1a91de28 688 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 689 goto err_dbg;
690 }
691
692 err = request_bar(pdev);
693 if (err) {
1a91de28 694 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 695 goto err_disable;
696 }
697
698 pci_set_master(pdev);
699
700 err = set_dma_caps(pdev);
701 if (err) {
702 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
703 goto err_clr_master;
704 }
705
706 dev->iseg_base = pci_resource_start(dev->pdev, 0);
707 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
708 if (!dev->iseg) {
709 err = -ENOMEM;
710 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
711 goto err_clr_master;
712 }
713 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
714 fw_rev_min(dev), fw_rev_sub(dev));
715
716 err = mlx5_cmd_init(dev);
717 if (err) {
718 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
719 goto err_unmap;
720 }
721
722 mlx5_pagealloc_init(dev);
cd23b14b
EC		 723
724 err = mlx5_core_enable_hca(dev);
725 if (err) {
726 dev_err(&pdev->dev, "enable hca failed\n");
727 goto err_pagealloc_cleanup;
728 }
729
f62b8bb8
AV		 730#ifdef CONFIG_MLX5_CORE_EN
731 err = mlx5_core_set_issi(dev);
732 if (err) {
733 dev_err(&pdev->dev, "failed to set issi\n");
734 goto err_disable_hca;
735 }
736#endif
737
cd23b14b
EC		 738 err = mlx5_satisfy_startup_pages(dev, 1);
739 if (err) {
740 dev_err(&pdev->dev, "failed to allocate boot pages\n");
741 goto err_disable_hca;
742 }
743
e126ba97
EC		 744 err = set_hca_ctrl(dev);
745 if (err) {
746 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 747 goto reclaim_boot_pages;
e126ba97
EC		 748 }
749
750 err = handle_hca_cap(dev);
751 if (err) {
752 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 753 goto reclaim_boot_pages;
e126ba97
EC		 754 }
755
cd23b14b 756 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 757 if (err) {
cd23b14b
EC		 758 dev_err(&pdev->dev, "failed to allocate init pages\n");
759 goto reclaim_boot_pages;
e126ba97
EC		 760 }
761
762 err = mlx5_pagealloc_start(dev);
763 if (err) {
764 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 765 goto reclaim_boot_pages;
e126ba97
EC		 766 }
767
768 err = mlx5_cmd_init_hca(dev);
769 if (err) {
770 dev_err(&pdev->dev, "init hca failed\n");
771 goto err_pagealloc_stop;
772 }
773
774 mlx5_start_health_poll(dev);
775
938fe83c 776 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 777 if (err) {
778 dev_err(&pdev->dev, "query hca failed\n");
779 goto err_stop_poll;
780 }
781
782 err = mlx5_cmd_query_adapter(dev);
783 if (err) {
784 dev_err(&pdev->dev, "query adapter failed\n");
785 goto err_stop_poll;
786 }
787
788 err = mlx5_enable_msix(dev);
789 if (err) {
790 dev_err(&pdev->dev, "enable msix failed\n");
791 goto err_stop_poll;
792 }
793
794 err = mlx5_eq_init(dev);
795 if (err) {
796 dev_err(&pdev->dev, "failed to initialize eq\n");
797 goto disable_msix;
798 }
799
800 err = mlx5_alloc_uuars(dev, &priv->uuari);
801 if (err) {
802 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
803 goto err_eq_cleanup;
804 }
805
806 err = mlx5_start_eqs(dev);
807 if (err) {
808 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
809 goto err_free_uar;
810 }
811
233d05d2
SM		 812 err = alloc_comp_eqs(dev);
813 if (err) {
814 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
815 goto err_stop_eqs;
816 }
817
db058a18
SM		 818 err = mlx5_irq_set_affinity_hints(dev);
819 if (err) {
820 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
821 goto err_free_comp_eqs;
822 }
823
e126ba97
EC		 824 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
825
826 mlx5_init_cq_table(dev);
827 mlx5_init_qp_table(dev);
828 mlx5_init_srq_table(dev);
3bcdb17a 829 mlx5_init_mr_table(dev);
e126ba97
EC		 830
831 return 0;
832
db058a18
SM		 833err_free_comp_eqs:
834 free_comp_eqs(dev);
835
233d05d2
SM		 836err_stop_eqs:
837 mlx5_stop_eqs(dev);
838
e126ba97
EC		 839err_free_uar:
840 mlx5_free_uuars(dev, &priv->uuari);
841
842err_eq_cleanup:
843 mlx5_eq_cleanup(dev);
844
845disable_msix:
846 mlx5_disable_msix(dev);
847
848err_stop_poll:
849 mlx5_stop_health_poll(dev);
1bde6e30
EC		 850 if (mlx5_cmd_teardown_hca(dev)) {
851 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
852 return err;
853 }
e126ba97
EC		 854
855err_pagealloc_stop:
856 mlx5_pagealloc_stop(dev);
857
cd23b14b 858reclaim_boot_pages:
e126ba97
EC		 859 mlx5_reclaim_startup_pages(dev);
860
cd23b14b
EC		 861err_disable_hca:
862 mlx5_core_disable_hca(dev);
863
e126ba97
EC		 864err_pagealloc_cleanup:
865 mlx5_pagealloc_cleanup(dev);
866 mlx5_cmd_cleanup(dev);
867
868err_unmap:
869 iounmap(dev->iseg);
870
871err_clr_master:
872 pci_clear_master(dev->pdev);
873 release_bar(dev->pdev);
874
875err_disable:
876 pci_disable_device(dev->pdev);
877
878err_dbg:
879 debugfs_remove(priv->dbg_root);
880 return err;
881}
e126ba97 882
9603b61d 883static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 884{
885 struct mlx5_priv *priv = &dev->priv;
886
887 mlx5_cleanup_srq_table(dev);
888 mlx5_cleanup_qp_table(dev);
889 mlx5_cleanup_cq_table(dev);
db058a18 890 mlx5_irq_clear_affinity_hints(dev);
233d05d2 891 free_comp_eqs(dev);
e126ba97
EC		 892 mlx5_stop_eqs(dev);
893 mlx5_free_uuars(dev, &priv->uuari);
894 mlx5_eq_cleanup(dev);
895 mlx5_disable_msix(dev);
896 mlx5_stop_health_poll(dev);
1bde6e30
EC		 897 if (mlx5_cmd_teardown_hca(dev)) {
898 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
899 return;
900 }
e126ba97
EC		 901 mlx5_pagealloc_stop(dev);
902 mlx5_reclaim_startup_pages(dev);
cd23b14b 903 mlx5_core_disable_hca(dev);
e126ba97
EC		 904 mlx5_pagealloc_cleanup(dev);
905 mlx5_cmd_cleanup(dev);
906 iounmap(dev->iseg);
907 pci_clear_master(dev->pdev);
908 release_bar(dev->pdev);
909 pci_disable_device(dev->pdev);
910 debugfs_remove(priv->dbg_root);
911}
9603b61d
JM		 912
913static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
914{
915 struct mlx5_device_context *dev_ctx;
916 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
917
918 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
919 if (!dev_ctx) {
920 pr_warn("mlx5_add_device: alloc context failed\n");
921 return;
922 }
923
924 dev_ctx->intf = intf;
925 dev_ctx->context = intf->add(dev);
926
927 if (dev_ctx->context) {
928 spin_lock_irq(&priv->ctx_lock);
929 list_add_tail(&dev_ctx->list, &priv->ctx_list);
930 spin_unlock_irq(&priv->ctx_lock);
931 } else {
932 kfree(dev_ctx);
933 }
934}
935
936static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
937{
938 struct mlx5_device_context *dev_ctx;
939 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
940
941 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
942 if (dev_ctx->intf == intf) {
943 spin_lock_irq(&priv->ctx_lock);
944 list_del(&dev_ctx->list);
945 spin_unlock_irq(&priv->ctx_lock);
946
947 intf->remove(dev, dev_ctx->context);
948 kfree(dev_ctx);
949 return;
950 }
951}
952static int mlx5_register_device(struct mlx5_core_dev *dev)
953{
954 struct mlx5_priv *priv = &dev->priv;
955 struct mlx5_interface *intf;
956
957 mutex_lock(&intf_mutex);
958 list_add_tail(&priv->dev_list, &dev_list);
959 list_for_each_entry(intf, &intf_list, list)
960 mlx5_add_device(intf, priv);
961 mutex_unlock(&intf_mutex);
962
963 return 0;
964}
965static void mlx5_unregister_device(struct mlx5_core_dev *dev)
966{
967 struct mlx5_priv *priv = &dev->priv;
968 struct mlx5_interface *intf;
969
970 mutex_lock(&intf_mutex);
971 list_for_each_entry(intf, &intf_list, list)
972 mlx5_remove_device(intf, priv);
973 list_del(&priv->dev_list);
974 mutex_unlock(&intf_mutex);
975}
976
977int mlx5_register_interface(struct mlx5_interface *intf)
978{
979 struct mlx5_priv *priv;
980
981 if (!intf->add || !intf->remove)
982 return -EINVAL;
983
984 mutex_lock(&intf_mutex);
985 list_add_tail(&intf->list, &intf_list);
986 list_for_each_entry(priv, &dev_list, dev_list)
987 mlx5_add_device(intf, priv);
988 mutex_unlock(&intf_mutex);
989
990 return 0;
991}
992EXPORT_SYMBOL(mlx5_register_interface);
993
994void mlx5_unregister_interface(struct mlx5_interface *intf)
995{
996 struct mlx5_priv *priv;
997
998 mutex_lock(&intf_mutex);
999 list_for_each_entry(priv, &dev_list, dev_list)
1000 mlx5_remove_device(intf, priv);
1001 list_del(&intf->list);
1002 mutex_unlock(&intf_mutex);
1003}
1004EXPORT_SYMBOL(mlx5_unregister_interface);
1005
64613d94
SM		 1006void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
1007{
1008 struct mlx5_priv *priv = &mdev->priv;
1009 struct mlx5_device_context *dev_ctx;
1010 unsigned long flags;
1011 void *result = NULL;
1012
1013 spin_lock_irqsave(&priv->ctx_lock, flags);
1014
1015 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
1016 if ((dev_ctx->intf->protocol == protocol) &&
1017 dev_ctx->intf->get_dev) {
1018 result = dev_ctx->intf->get_dev(dev_ctx->context);
1019 break;
1020 }
1021
1022 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1023
1024 return result;
1025}
1026EXPORT_SYMBOL(mlx5_get_protocol_dev);
1027
9603b61d 1028static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 1029 unsigned long param)
9603b61d
JM		 1030{
1031 struct mlx5_priv *priv = &dev->priv;
1032 struct mlx5_device_context *dev_ctx;
1033 unsigned long flags;
1034
1035 spin_lock_irqsave(&priv->ctx_lock, flags);
1036
1037 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1038 if (dev_ctx->intf->event)
4d2f9bbb 1039 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1040
1041 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1042}
1043
1044struct mlx5_core_event_handler {
1045 void (*event)(struct mlx5_core_dev *dev,
1046 enum mlx5_dev_event event,
1047 void *data);
1048};
1049
f66f049f
EC		 1050#define MLX5_IB_MOD "mlx5_ib"
1051
9603b61d
JM		 1052static int init_one(struct pci_dev *pdev,
1053 const struct pci_device_id *id)
1054{
1055 struct mlx5_core_dev *dev;
1056 struct mlx5_priv *priv;
1057 int err;
1058
1059 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1060 if (!dev) {
1061 dev_err(&pdev->dev, "kzalloc failed\n");
1062 return -ENOMEM;
1063 }
1064 priv = &dev->priv;
1065
1066 pci_set_drvdata(pdev, dev);
1067
1068 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1069 pr_warn("selected profile out of range, selecting default (%d)\n",
1070 MLX5_DEFAULT_PROF);
1071 prof_sel = MLX5_DEFAULT_PROF;
1072 }
1073 dev->profile = &profile[prof_sel];
1074 dev->event = mlx5_core_event;
1075
364d1798
EC		 1076 INIT_LIST_HEAD(&priv->ctx_list);
1077 spin_lock_init(&priv->ctx_lock);
9603b61d
JM		 1078 err = mlx5_dev_init(dev, pdev);
1079 if (err) {
1080 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
1081 goto out;
1082 }
1083
9603b61d
JM		 1084 err = mlx5_register_device(dev);
1085 if (err) {
1086 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1087 goto out_init;
1088 }
1089
f66f049f
EC		 1090 err = request_module_nowait(MLX5_IB_MOD);
1091 if (err)
1092 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1093
9603b61d
JM		 1094 return 0;
1095
1096out_init:
1097 mlx5_dev_cleanup(dev);
1098out:
1099 kfree(dev);
1100 return err;
1101}
1102static void remove_one(struct pci_dev *pdev)
1103{
1104 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1105
1106 mlx5_unregister_device(dev);
1107 mlx5_dev_cleanup(dev);
1108 kfree(dev);
1109}
1110
1111static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1112 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1113 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1114 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1115 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1116 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1117 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1118 { 0, }
1119};
1120
1121MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1122
1123static struct pci_driver mlx5_core_driver = {
1124 .name = DRIVER_NAME,
1125 .id_table = mlx5_core_pci_table,
1126 .probe = init_one,
1127 .remove = remove_one
1128};
e126ba97
EC		 1129
1130static int __init init(void)
1131{
1132 int err;
1133
1134 mlx5_register_debugfs();
1135 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1136 if (!mlx5_core_wq) {
1137 err = -ENOMEM;
1138 goto err_debug;
1139 }
1140 mlx5_health_init();
1141
9603b61d
JM		 1142 err = pci_register_driver(&mlx5_core_driver);
1143 if (err)
1144 goto err_health;
1145
f62b8bb8
AV		 1146#ifdef CONFIG_MLX5_CORE_EN
1147 mlx5e_init();
1148#endif
1149
e126ba97
EC		 1150 return 0;
1151
9603b61d
JM		 1152err_health:
1153 mlx5_health_cleanup();
1154 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 1155err_debug:
1156 mlx5_unregister_debugfs();
1157 return err;
1158}
1159
1160static void __exit cleanup(void)
1161{
f62b8bb8
AV		 1162#ifdef CONFIG_MLX5_CORE_EN
1163 mlx5e_cleanup();
1164#endif
9603b61d 1165 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1166 mlx5_health_cleanup();
1167 destroy_workqueue(mlx5_core_wq);
1168 mlx5_unregister_debugfs();
1169}
1170
1171module_init(init);
1172module_exit(cleanup);
Linux 6.x block layer and io_uring tree(s)