Commit | Line | Data |
---|---|---|
e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
e126ba97 | 46 | #include <linux/debugfs.h> |
f66f049f | 47 | #include <linux/kmod.h> |
b775516b | 48 | #include <linux/mlx5/mlx5_ifc.h> |
c85023e1 | 49 | #include <linux/mlx5/vport.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
feae9087 | 53 | #include <net/devlink.h> |
e126ba97 | 54 | #include "mlx5_core.h" |
f2f3df55 | 55 | #include "lib/eq.h" |
16d76083 | 56 | #include "fs_core.h" |
eeb66cdb | 57 | #include "lib/mpfs.h" |
073bb189 | 58 | #include "eswitch.h" |
1f28d776 | 59 | #include "devlink.h" |
52ec462e | 60 | #include "lib/mlx5.h" |
e29341fb | 61 | #include "fpga/core.h" |
05564d0a | 62 | #include "fpga/ipsec.h" |
bebb23e6 | 63 | #include "accel/ipsec.h" |
1ae17322 | 64 | #include "accel/tls.h" |
7c39afb3 | 65 | #include "lib/clock.h" |
358aa5ce | 66 | #include "lib/vxlan.h" |
0ccc171e | 67 | #include "lib/geneve.h" |
fadd59fc | 68 | #include "lib/devcom.h" |
b25bbc2f | 69 | #include "lib/pci_vsc.h" |
24406953 | 70 | #include "diag/fw_tracer.h" |
591905ba | 71 | #include "ecpf.h" |
87175120 | 72 | #include "lib/hv_vhca.h" |
12206b17 | 73 | #include "diag/rsc_dump.h" |
e126ba97 | 74 | |
e126ba97 | 75 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
048f3143 | 76 | MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); |
e126ba97 EC |
77 | MODULE_LICENSE("Dual BSD/GPL"); |
78 | MODULE_VERSION(DRIVER_VERSION); | |
79 | ||
f663ad98 KH |
80 | unsigned int mlx5_core_debug_mask; |
81 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
82 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
83 | ||
9603b61d | 84 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
85 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
86 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
87 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
88 | ||
8737f818 DJ |
89 | static u32 sw_owner_id[4]; |
90 | ||
f91e6d89 EBE |
91 | enum { |
92 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
93 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
94 | }; | |
95 | ||
9603b61d JM |
96 | static struct mlx5_profile profile[] = { |
97 | [0] = { | |
98 | .mask = 0, | |
99 | }, | |
100 | [1] = { | |
101 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
102 | .log_max_qp = 12, | |
103 | }, | |
104 | [2] = { | |
105 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
106 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 107 | .log_max_qp = 18, |
9603b61d JM |
108 | .mr_cache[0] = { |
109 | .size = 500, | |
110 | .limit = 250 | |
111 | }, | |
112 | .mr_cache[1] = { | |
113 | .size = 500, | |
114 | .limit = 250 | |
115 | }, | |
116 | .mr_cache[2] = { | |
117 | .size = 500, | |
118 | .limit = 250 | |
119 | }, | |
120 | .mr_cache[3] = { | |
121 | .size = 500, | |
122 | .limit = 250 | |
123 | }, | |
124 | .mr_cache[4] = { | |
125 | .size = 500, | |
126 | .limit = 250 | |
127 | }, | |
128 | .mr_cache[5] = { | |
129 | .size = 500, | |
130 | .limit = 250 | |
131 | }, | |
132 | .mr_cache[6] = { | |
133 | .size = 500, | |
134 | .limit = 250 | |
135 | }, | |
136 | .mr_cache[7] = { | |
137 | .size = 500, | |
138 | .limit = 250 | |
139 | }, | |
140 | .mr_cache[8] = { | |
141 | .size = 500, | |
142 | .limit = 250 | |
143 | }, | |
144 | .mr_cache[9] = { | |
145 | .size = 500, | |
146 | .limit = 250 | |
147 | }, | |
148 | .mr_cache[10] = { | |
149 | .size = 500, | |
150 | .limit = 250 | |
151 | }, | |
152 | .mr_cache[11] = { | |
153 | .size = 500, | |
154 | .limit = 250 | |
155 | }, | |
156 | .mr_cache[12] = { | |
157 | .size = 64, | |
158 | .limit = 32 | |
159 | }, | |
160 | .mr_cache[13] = { | |
161 | .size = 32, | |
162 | .limit = 16 | |
163 | }, | |
164 | .mr_cache[14] = { | |
165 | .size = 16, | |
166 | .limit = 8 | |
167 | }, | |
168 | .mr_cache[15] = { | |
169 | .size = 8, | |
170 | .limit = 4 | |
171 | }, | |
172 | }, | |
173 | }; | |
e126ba97 | 174 | |
6c780a02 EC |
175 | #define FW_INIT_TIMEOUT_MILI 2000 |
176 | #define FW_INIT_WAIT_MS 2 | |
b8a92577 DJ |
177 | #define FW_PRE_INIT_TIMEOUT_MILI 120000 |
178 | #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 | |
e3297246 | 179 | |
b8a92577 DJ |
180 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, |
181 | u32 warn_time_mili) | |
e3297246 | 182 | { |
b8a92577 | 183 | unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); |
e3297246 EC |
184 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); |
185 | int err = 0; | |
186 | ||
b8a92577 DJ |
187 | BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); |
188 | ||
e3297246 EC |
189 | while (fw_initializing(dev)) { |
190 | if (time_after(jiffies, end)) { | |
191 | err = -EBUSY; | |
192 | break; | |
193 | } | |
b8a92577 DJ |
194 | if (warn_time_mili && time_after(jiffies, warn)) { |
195 | mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", | |
196 | jiffies_to_msecs(end - warn) / 1000); | |
197 | warn = jiffies + msecs_to_jiffies(warn_time_mili); | |
198 | } | |
e3297246 EC |
199 | msleep(FW_INIT_WAIT_MS); |
200 | } | |
201 | ||
202 | return err; | |
203 | } | |
204 | ||
012e50e1 HN |
205 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
206 | { | |
207 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
208 | driver_version); | |
3ac0e69e | 209 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; |
012e50e1 HN |
210 | int remaining_size = driver_ver_sz; |
211 | char *string; | |
212 | ||
213 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
214 | return; | |
215 | ||
216 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
217 | ||
218 | strncpy(string, "Linux", remaining_size); | |
219 | ||
220 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
221 | strncat(string, ",", remaining_size); | |
222 | ||
223 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
224 | strncat(string, DRIVER_NAME, remaining_size); | |
225 | ||
226 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
227 | strncat(string, ",", remaining_size); | |
228 | ||
229 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
230 | strncat(string, DRIVER_VERSION, remaining_size); | |
231 | ||
232 | /*Send the command*/ | |
233 | MLX5_SET(set_driver_version_in, in, opcode, | |
234 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
235 | ||
3ac0e69e | 236 | mlx5_cmd_exec_in(dev, set_driver_version, in); |
012e50e1 HN |
237 | } |
238 | ||
e126ba97 EC |
239 | static int set_dma_caps(struct pci_dev *pdev) |
240 | { | |
241 | int err; | |
242 | ||
243 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
244 | if (err) { | |
1a91de28 | 245 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
246 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
247 | if (err) { | |
1a91de28 | 248 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
249 | return err; |
250 | } | |
251 | } | |
252 | ||
253 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
254 | if (err) { | |
255 | dev_warn(&pdev->dev, | |
1a91de28 | 256 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
257 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
258 | if (err) { | |
259 | dev_err(&pdev->dev, | |
1a91de28 | 260 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
261 | return err; |
262 | } | |
263 | } | |
264 | ||
265 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
266 | return err; | |
267 | } | |
268 | ||
89d44f0a MD |
269 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
270 | { | |
271 | struct pci_dev *pdev = dev->pdev; | |
272 | int err = 0; | |
273 | ||
274 | mutex_lock(&dev->pci_status_mutex); | |
275 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
276 | err = pci_enable_device(pdev); | |
277 | if (!err) | |
278 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
279 | } | |
280 | mutex_unlock(&dev->pci_status_mutex); | |
281 | ||
282 | return err; | |
283 | } | |
284 | ||
285 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
286 | { | |
287 | struct pci_dev *pdev = dev->pdev; | |
288 | ||
289 | mutex_lock(&dev->pci_status_mutex); | |
290 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
291 | pci_disable_device(pdev); | |
292 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
293 | } | |
294 | mutex_unlock(&dev->pci_status_mutex); | |
295 | } | |
296 | ||
e126ba97 EC |
297 | static int request_bar(struct pci_dev *pdev) |
298 | { | |
299 | int err = 0; | |
300 | ||
301 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 302 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
303 | return -ENODEV; |
304 | } | |
305 | ||
306 | err = pci_request_regions(pdev, DRIVER_NAME); | |
307 | if (err) | |
308 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
309 | ||
310 | return err; | |
311 | } | |
312 | ||
313 | static void release_bar(struct pci_dev *pdev) | |
314 | { | |
315 | pci_release_regions(pdev); | |
316 | } | |
317 | ||
bd10838a | 318 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
319 | u8 he; |
320 | u8 rsvd[15]; | |
321 | }; | |
322 | ||
87b8de49 EC |
323 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
324 | ||
325 | enum { | |
c7a08ac7 EC |
326 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
327 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
328 | }; |
329 | ||
2974ab6e | 330 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
331 | { |
332 | switch (size) { | |
333 | case 128: | |
334 | return 0; | |
335 | case 256: | |
336 | return 1; | |
337 | case 512: | |
338 | return 2; | |
339 | case 1024: | |
340 | return 3; | |
341 | case 2048: | |
342 | return 4; | |
343 | case 4096: | |
344 | return 5; | |
345 | default: | |
2974ab6e | 346 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
347 | return 0; |
348 | } | |
349 | } | |
350 | ||
b06e7de8 LR |
351 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
352 | enum mlx5_cap_type cap_type, | |
353 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 354 | { |
b775516b EC |
355 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
356 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
357 | void *out, *hca_caps; |
358 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
359 | int err; |
360 | ||
b775516b EC |
361 | memset(in, 0, sizeof(in)); |
362 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 363 | if (!out) |
e126ba97 | 364 | return -ENOMEM; |
938fe83c | 365 | |
b775516b EC |
366 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
367 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
3ac0e69e | 368 | err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); |
c7a08ac7 | 369 | if (err) { |
938fe83c SM |
370 | mlx5_core_warn(dev, |
371 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
372 | cap_type, cap_mode, err); | |
e126ba97 EC |
373 | goto query_ex; |
374 | } | |
c7a08ac7 | 375 | |
938fe83c SM |
376 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
377 | ||
378 | switch (cap_mode) { | |
379 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 380 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
381 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
382 | break; | |
383 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 384 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
385 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
386 | break; | |
387 | default: | |
388 | mlx5_core_warn(dev, | |
389 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
390 | cap_type, cap_mode); | |
391 | err = -EINVAL; | |
392 | break; | |
393 | } | |
c7a08ac7 EC |
394 | query_ex: |
395 | kfree(out); | |
396 | return err; | |
397 | } | |
398 | ||
b06e7de8 LR |
399 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
400 | { | |
401 | int ret; | |
402 | ||
403 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
404 | if (ret) | |
405 | return ret; | |
406 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
407 | } | |
408 | ||
a2a322f4 | 409 | static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) |
c7a08ac7 | 410 | { |
b775516b | 411 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 412 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
3ac0e69e | 413 | return mlx5_cmd_exec_in(dev, set_hca_cap, in); |
c7a08ac7 EC |
414 | } |
415 | ||
a2a322f4 | 416 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) |
f91e6d89 | 417 | { |
f91e6d89 | 418 | void *set_hca_cap; |
f91e6d89 EBE |
419 | int req_endianness; |
420 | int err; | |
421 | ||
a2a322f4 | 422 | if (!MLX5_CAP_GEN(dev, atomic)) |
f91e6d89 | 423 | return 0; |
a2a322f4 LR |
424 | |
425 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); | |
426 | if (err) | |
427 | return err; | |
f91e6d89 EBE |
428 | |
429 | req_endianness = | |
430 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 431 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
432 | |
433 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
434 | return 0; | |
435 | ||
f91e6d89 EBE |
436 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); |
437 | ||
438 | /* Set requestor to host endianness */ | |
bd10838a | 439 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
440 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
441 | ||
a2a322f4 | 442 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); |
f91e6d89 EBE |
443 | } |
444 | ||
a2a322f4 | 445 | static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) |
46861e3e | 446 | { |
46861e3e | 447 | void *set_hca_cap; |
fca22e7e | 448 | bool do_set = false; |
46861e3e MS |
449 | int err; |
450 | ||
37b6bb77 LR |
451 | if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || |
452 | !MLX5_CAP_GEN(dev, pg)) | |
46861e3e MS |
453 | return 0; |
454 | ||
455 | err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); | |
456 | if (err) | |
457 | return err; | |
458 | ||
46861e3e MS |
459 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); |
460 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], | |
461 | MLX5_ST_SZ_BYTES(odp_cap)); | |
462 | ||
fca22e7e MS |
463 | #define ODP_CAP_SET_MAX(dev, field) \ |
464 | do { \ | |
465 | u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ | |
466 | if (_res) { \ | |
467 | do_set = true; \ | |
468 | MLX5_SET(odp_cap, set_hca_cap, field, _res); \ | |
469 | } \ | |
470 | } while (0) | |
471 | ||
472 | ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); | |
473 | ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); | |
474 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); | |
475 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); | |
476 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); | |
477 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); | |
478 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); | |
479 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); | |
00679b63 MG |
480 | ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); |
481 | ODP_CAP_SET_MAX(dev, dc_odp_caps.send); | |
482 | ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); | |
483 | ODP_CAP_SET_MAX(dev, dc_odp_caps.write); | |
484 | ODP_CAP_SET_MAX(dev, dc_odp_caps.read); | |
485 | ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); | |
fca22e7e | 486 | |
a2a322f4 LR |
487 | if (!do_set) |
488 | return 0; | |
fca22e7e | 489 | |
a2a322f4 | 490 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); |
46861e3e MS |
491 | } |
492 | ||
a2a322f4 | 493 | static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) |
c7a08ac7 | 494 | { |
c7a08ac7 | 495 | struct mlx5_profile *prof = dev->profile; |
938fe83c | 496 | void *set_hca_cap; |
a2a322f4 | 497 | int err; |
e126ba97 | 498 | |
b06e7de8 | 499 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 | 500 | if (err) |
a2a322f4 | 501 | return err; |
e126ba97 | 502 | |
938fe83c SM |
503 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
504 | capability); | |
701052c5 | 505 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
506 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
507 | ||
508 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 509 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 510 | 128); |
c7a08ac7 | 511 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 512 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 513 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 514 | |
883371c4 NO |
515 | /* Check log_max_qp from HCA caps to set in current profile */ |
516 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
517 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
518 | profile[prof_sel].log_max_qp, | |
519 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
520 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
521 | } | |
c7a08ac7 | 522 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
523 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
524 | prof->log_max_qp); | |
c7a08ac7 | 525 | |
938fe83c SM |
526 | /* disable cmdif checksum */ |
527 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 528 | |
91828bd8 MD |
529 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
530 | * than 4K. | |
531 | */ | |
532 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
533 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
534 | ||
fe1e1876 CS |
535 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
536 | ||
f32f5bd2 DJ |
537 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
538 | MLX5_SET(cmd_hca_cap, | |
539 | set_hca_cap, | |
540 | cache_line_128byte, | |
c67f100e | 541 | cache_line_size() >= 128 ? 1 : 0); |
f32f5bd2 | 542 | |
dd44572a MS |
543 | if (MLX5_CAP_GEN_MAX(dev, dct)) |
544 | MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); | |
545 | ||
c4b76d8d DJ |
546 | if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) |
547 | MLX5_SET(cmd_hca_cap, | |
548 | set_hca_cap, | |
549 | num_vhca_ports, | |
550 | MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); | |
551 | ||
a2a322f4 | 552 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); |
e126ba97 | 553 | } |
c7a08ac7 | 554 | |
59e9e8e4 MZ |
555 | static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) |
556 | { | |
557 | void *set_hca_cap; | |
558 | int err; | |
559 | ||
560 | if (!MLX5_CAP_GEN(dev, roce)) | |
561 | return 0; | |
562 | ||
563 | err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); | |
564 | if (err) | |
565 | return err; | |
566 | ||
567 | if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || | |
568 | !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) | |
569 | return 0; | |
570 | ||
571 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
572 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], | |
573 | MLX5_ST_SZ_BYTES(roce_cap)); | |
574 | MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); | |
575 | ||
576 | err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); | |
e126ba97 EC |
577 | return err; |
578 | } | |
579 | ||
37b6bb77 LR |
580 | static int set_hca_cap(struct mlx5_core_dev *dev) |
581 | { | |
a2a322f4 LR |
582 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
583 | void *set_ctx; | |
37b6bb77 LR |
584 | int err; |
585 | ||
a2a322f4 LR |
586 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
587 | if (!set_ctx) | |
588 | return -ENOMEM; | |
589 | ||
590 | err = handle_hca_cap(dev, set_ctx); | |
37b6bb77 | 591 | if (err) { |
98a8e6fc | 592 | mlx5_core_err(dev, "handle_hca_cap failed\n"); |
37b6bb77 LR |
593 | goto out; |
594 | } | |
595 | ||
a2a322f4 LR |
596 | memset(set_ctx, 0, set_sz); |
597 | err = handle_hca_cap_atomic(dev, set_ctx); | |
37b6bb77 | 598 | if (err) { |
98a8e6fc | 599 | mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); |
37b6bb77 LR |
600 | goto out; |
601 | } | |
602 | ||
a2a322f4 LR |
603 | memset(set_ctx, 0, set_sz); |
604 | err = handle_hca_cap_odp(dev, set_ctx); | |
37b6bb77 | 605 | if (err) { |
98a8e6fc | 606 | mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); |
37b6bb77 LR |
607 | goto out; |
608 | } | |
609 | ||
59e9e8e4 MZ |
610 | memset(set_ctx, 0, set_sz); |
611 | err = handle_hca_cap_roce(dev, set_ctx); | |
612 | if (err) { | |
613 | mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); | |
614 | goto out; | |
615 | } | |
616 | ||
37b6bb77 | 617 | out: |
a2a322f4 | 618 | kfree(set_ctx); |
37b6bb77 LR |
619 | return err; |
620 | } | |
621 | ||
e126ba97 EC |
622 | static int set_hca_ctrl(struct mlx5_core_dev *dev) |
623 | { | |
bd10838a OG |
624 | struct mlx5_reg_host_endianness he_in; |
625 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
626 | int err; |
627 | ||
fc50db98 EC |
628 | if (!mlx5_core_is_pf(dev)) |
629 | return 0; | |
630 | ||
e126ba97 EC |
631 | memset(&he_in, 0, sizeof(he_in)); |
632 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
633 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
634 | &he_out, sizeof(he_out), | |
635 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
636 | return err; | |
637 | } | |
638 | ||
c85023e1 HN |
639 | static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) |
640 | { | |
641 | int ret = 0; | |
642 | ||
643 | /* Disable local_lb by default */ | |
8978cc92 | 644 | if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) |
c85023e1 HN |
645 | ret = mlx5_nic_vport_update_local_lb(dev, false); |
646 | ||
647 | return ret; | |
648 | } | |
649 | ||
0b107106 | 650 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 651 | { |
3ac0e69e | 652 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; |
cd23b14b | 653 | |
0b107106 EC |
654 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
655 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
656 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
657 | dev->caps.embedded_cpu); | |
3ac0e69e | 658 | return mlx5_cmd_exec_in(dev, enable_hca, in); |
cd23b14b EC |
659 | } |
660 | ||
0b107106 | 661 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 662 | { |
3ac0e69e | 663 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; |
cd23b14b | 664 | |
0b107106 EC |
665 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
666 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
667 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
668 | dev->caps.embedded_cpu); | |
3ac0e69e | 669 | return mlx5_cmd_exec_in(dev, disable_hca, in); |
cd23b14b EC |
670 | } |
671 | ||
4a0475d5 ML |
672 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, |
673 | struct ptp_system_timestamp *sts) | |
b0844444 EBE |
674 | { |
675 | u32 timer_h, timer_h1, timer_l; | |
676 | ||
677 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
4a0475d5 | 678 | ptp_read_system_prets(sts); |
b0844444 | 679 | timer_l = ioread32be(&dev->iseg->internal_timer_l); |
4a0475d5 | 680 | ptp_read_system_postts(sts); |
b0844444 | 681 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); |
4a0475d5 ML |
682 | if (timer_h != timer_h1) { |
683 | /* wrap around */ | |
684 | ptp_read_system_prets(sts); | |
b0844444 | 685 | timer_l = ioread32be(&dev->iseg->internal_timer_l); |
4a0475d5 ML |
686 | ptp_read_system_postts(sts); |
687 | } | |
b0844444 | 688 | |
a5a1d1c2 | 689 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
690 | } |
691 | ||
f62b8bb8 AV |
692 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
693 | { | |
3ac0e69e LR |
694 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; |
695 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; | |
f62b8bb8 | 696 | u32 sup_issi; |
c4f287c4 | 697 | int err; |
f62b8bb8 AV |
698 | |
699 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
3ac0e69e | 700 | err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); |
f62b8bb8 | 701 | if (err) { |
c4f287c4 SM |
702 | u32 syndrome; |
703 | u8 status; | |
704 | ||
705 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
706 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
707 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
708 | err, status, syndrome); | |
709 | return err; | |
f62b8bb8 AV |
710 | } |
711 | ||
f9c14e46 KH |
712 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
713 | dev->issi = 0; | |
714 | return 0; | |
f62b8bb8 AV |
715 | } |
716 | ||
717 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
718 | ||
719 | if (sup_issi & (1 << 1)) { | |
3ac0e69e | 720 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; |
f62b8bb8 AV |
721 | |
722 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
723 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
3ac0e69e | 724 | err = mlx5_cmd_exec_in(dev, set_issi, set_in); |
f62b8bb8 | 725 | if (err) { |
f9c14e46 KH |
726 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
727 | err); | |
f62b8bb8 AV |
728 | return err; |
729 | } | |
730 | ||
731 | dev->issi = 1; | |
732 | ||
733 | return 0; | |
e74a1db0 | 734 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
735 | return 0; |
736 | } | |
737 | ||
9eb78923 | 738 | return -EOPNOTSUPP; |
f62b8bb8 | 739 | } |
f62b8bb8 | 740 | |
11f3b84d SM |
741 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, |
742 | const struct pci_device_id *id) | |
a31208b1 | 743 | { |
868bc06b | 744 | struct mlx5_priv *priv = &dev->priv; |
a31208b1 | 745 | int err = 0; |
e126ba97 | 746 | |
d22663ed | 747 | mutex_init(&dev->pci_status_mutex); |
11f3b84d | 748 | pci_set_drvdata(dev->pdev, dev); |
311c7c71 | 749 | |
aa8106f1 | 750 | dev->bar_addr = pci_resource_start(pdev, 0); |
311c7c71 SM |
751 | priv->numa_node = dev_to_node(&dev->pdev->dev); |
752 | ||
89d44f0a | 753 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 754 | if (err) { |
98a8e6fc | 755 | mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); |
11f3b84d | 756 | return err; |
e126ba97 EC |
757 | } |
758 | ||
759 | err = request_bar(pdev); | |
760 | if (err) { | |
98a8e6fc | 761 | mlx5_core_err(dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
762 | goto err_disable; |
763 | } | |
764 | ||
765 | pci_set_master(pdev); | |
766 | ||
767 | err = set_dma_caps(pdev); | |
768 | if (err) { | |
98a8e6fc | 769 | mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); |
e126ba97 EC |
770 | goto err_clr_master; |
771 | } | |
772 | ||
ce4eee53 MG |
773 | if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && |
774 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && | |
775 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) | |
776 | mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); | |
777 | ||
aa8106f1 | 778 | dev->iseg_base = dev->bar_addr; |
e126ba97 EC |
779 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); |
780 | if (!dev->iseg) { | |
781 | err = -ENOMEM; | |
98a8e6fc | 782 | mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); |
e126ba97 EC |
783 | goto err_clr_master; |
784 | } | |
a31208b1 | 785 | |
b25bbc2f | 786 | mlx5_pci_vsc_init(dev); |
c89da067 | 787 | dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); |
a31208b1 MD |
788 | return 0; |
789 | ||
790 | err_clr_master: | |
791 | pci_clear_master(dev->pdev); | |
792 | release_bar(dev->pdev); | |
793 | err_disable: | |
89d44f0a | 794 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
795 | return err; |
796 | } | |
797 | ||
868bc06b | 798 | static void mlx5_pci_close(struct mlx5_core_dev *dev) |
a31208b1 MD |
799 | { |
800 | iounmap(dev->iseg); | |
801 | pci_clear_master(dev->pdev); | |
802 | release_bar(dev->pdev); | |
89d44f0a | 803 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
804 | } |
805 | ||
868bc06b | 806 | static int mlx5_init_once(struct mlx5_core_dev *dev) |
59211bd3 | 807 | { |
59211bd3 MHY |
808 | int err; |
809 | ||
868bc06b SM |
810 | dev->priv.devcom = mlx5_devcom_register_device(dev); |
811 | if (IS_ERR(dev->priv.devcom)) | |
98a8e6fc HN |
812 | mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", |
813 | dev->priv.devcom); | |
fadd59fc | 814 | |
59211bd3 MHY |
815 | err = mlx5_query_board_id(dev); |
816 | if (err) { | |
98a8e6fc | 817 | mlx5_core_err(dev, "query board id failed\n"); |
fadd59fc | 818 | goto err_devcom; |
59211bd3 MHY |
819 | } |
820 | ||
561aa15a YA |
821 | err = mlx5_irq_table_init(dev); |
822 | if (err) { | |
823 | mlx5_core_err(dev, "failed to initialize irq table\n"); | |
824 | goto err_devcom; | |
825 | } | |
826 | ||
f2f3df55 | 827 | err = mlx5_eq_table_init(dev); |
59211bd3 | 828 | if (err) { |
98a8e6fc | 829 | mlx5_core_err(dev, "failed to initialize eq\n"); |
561aa15a | 830 | goto err_irq_cleanup; |
59211bd3 MHY |
831 | } |
832 | ||
69c1280b SM |
833 | err = mlx5_events_init(dev); |
834 | if (err) { | |
98a8e6fc | 835 | mlx5_core_err(dev, "failed to initialize events\n"); |
69c1280b SM |
836 | goto err_eq_cleanup; |
837 | } | |
838 | ||
9f818c8a | 839 | mlx5_cq_debugfs_init(dev); |
59211bd3 | 840 | |
52ec462e IT |
841 | mlx5_init_reserved_gids(dev); |
842 | ||
7c39afb3 FD |
843 | mlx5_init_clock(dev); |
844 | ||
358aa5ce | 845 | dev->vxlan = mlx5_vxlan_create(dev); |
0ccc171e | 846 | dev->geneve = mlx5_geneve_create(dev); |
358aa5ce | 847 | |
59211bd3 MHY |
848 | err = mlx5_init_rl_table(dev); |
849 | if (err) { | |
98a8e6fc | 850 | mlx5_core_err(dev, "Failed to init rate limiting\n"); |
59211bd3 MHY |
851 | goto err_tables_cleanup; |
852 | } | |
853 | ||
eeb66cdb SM |
854 | err = mlx5_mpfs_init(dev); |
855 | if (err) { | |
98a8e6fc | 856 | mlx5_core_err(dev, "Failed to init l2 table %d\n", err); |
eeb66cdb SM |
857 | goto err_rl_cleanup; |
858 | } | |
859 | ||
86eec50b | 860 | err = mlx5_sriov_init(dev); |
c2d6e31a | 861 | if (err) { |
86eec50b | 862 | mlx5_core_err(dev, "Failed to init sriov %d\n", err); |
eeb66cdb | 863 | goto err_mpfs_cleanup; |
c2d6e31a | 864 | } |
c2d6e31a | 865 | |
86eec50b | 866 | err = mlx5_eswitch_init(dev); |
c2d6e31a | 867 | if (err) { |
86eec50b BW |
868 | mlx5_core_err(dev, "Failed to init eswitch %d\n", err); |
869 | goto err_sriov_cleanup; | |
c2d6e31a MHY |
870 | } |
871 | ||
9410733c IT |
872 | err = mlx5_fpga_init(dev); |
873 | if (err) { | |
98a8e6fc | 874 | mlx5_core_err(dev, "Failed to init fpga device %d\n", err); |
86eec50b | 875 | goto err_eswitch_cleanup; |
9410733c IT |
876 | } |
877 | ||
c9b9dcb4 AL |
878 | dev->dm = mlx5_dm_create(dev); |
879 | if (IS_ERR(dev->dm)) | |
880 | mlx5_core_warn(dev, "Failed to init device memory%d\n", err); | |
881 | ||
24406953 | 882 | dev->tracer = mlx5_fw_tracer_create(dev); |
87175120 | 883 | dev->hv_vhca = mlx5_hv_vhca_create(dev); |
12206b17 | 884 | dev->rsc_dump = mlx5_rsc_dump_create(dev); |
24406953 | 885 | |
59211bd3 MHY |
886 | return 0; |
887 | ||
c2d6e31a | 888 | err_eswitch_cleanup: |
c2d6e31a | 889 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
86eec50b BW |
890 | err_sriov_cleanup: |
891 | mlx5_sriov_cleanup(dev); | |
eeb66cdb | 892 | err_mpfs_cleanup: |
eeb66cdb | 893 | mlx5_mpfs_cleanup(dev); |
c2d6e31a | 894 | err_rl_cleanup: |
c2d6e31a | 895 | mlx5_cleanup_rl_table(dev); |
59211bd3 | 896 | err_tables_cleanup: |
0ccc171e | 897 | mlx5_geneve_destroy(dev->geneve); |
358aa5ce | 898 | mlx5_vxlan_destroy(dev->vxlan); |
02d92f79 | 899 | mlx5_cq_debugfs_cleanup(dev); |
69c1280b | 900 | mlx5_events_cleanup(dev); |
59211bd3 | 901 | err_eq_cleanup: |
f2f3df55 | 902 | mlx5_eq_table_cleanup(dev); |
561aa15a YA |
903 | err_irq_cleanup: |
904 | mlx5_irq_table_cleanup(dev); | |
fadd59fc AH |
905 | err_devcom: |
906 | mlx5_devcom_unregister_device(dev->priv.devcom); | |
59211bd3 | 907 | |
59211bd3 MHY |
908 | return err; |
909 | } | |
910 | ||
911 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
912 | { | |
12206b17 | 913 | mlx5_rsc_dump_destroy(dev); |
87175120 | 914 | mlx5_hv_vhca_destroy(dev->hv_vhca); |
24406953 | 915 | mlx5_fw_tracer_destroy(dev->tracer); |
c9b9dcb4 | 916 | mlx5_dm_cleanup(dev); |
9410733c | 917 | mlx5_fpga_cleanup(dev); |
c2d6e31a | 918 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
86eec50b | 919 | mlx5_sriov_cleanup(dev); |
eeb66cdb | 920 | mlx5_mpfs_cleanup(dev); |
59211bd3 | 921 | mlx5_cleanup_rl_table(dev); |
0ccc171e | 922 | mlx5_geneve_destroy(dev->geneve); |
358aa5ce | 923 | mlx5_vxlan_destroy(dev->vxlan); |
7c39afb3 | 924 | mlx5_cleanup_clock(dev); |
52ec462e | 925 | mlx5_cleanup_reserved_gids(dev); |
02d92f79 | 926 | mlx5_cq_debugfs_cleanup(dev); |
69c1280b | 927 | mlx5_events_cleanup(dev); |
f2f3df55 | 928 | mlx5_eq_table_cleanup(dev); |
561aa15a | 929 | mlx5_irq_table_cleanup(dev); |
fadd59fc | 930 | mlx5_devcom_unregister_device(dev->priv.devcom); |
59211bd3 MHY |
931 | } |
932 | ||
e161105e | 933 | static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) |
a31208b1 | 934 | { |
a31208b1 MD |
935 | int err; |
936 | ||
98a8e6fc HN |
937 | mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
938 | fw_rev_min(dev), fw_rev_sub(dev)); | |
e126ba97 | 939 | |
00c6bcb0 TG |
940 | /* Only PFs hold the relevant PCIe information for this query */ |
941 | if (mlx5_core_is_pf(dev)) | |
942 | pcie_print_link_status(dev->pdev); | |
943 | ||
6c780a02 EC |
944 | /* wait for firmware to accept initialization segments configurations |
945 | */ | |
b8a92577 | 946 | err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); |
6c780a02 | 947 | if (err) { |
98a8e6fc HN |
948 | mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", |
949 | FW_PRE_INIT_TIMEOUT_MILI); | |
e161105e | 950 | return err; |
6c780a02 EC |
951 | } |
952 | ||
e126ba97 EC |
953 | err = mlx5_cmd_init(dev); |
954 | if (err) { | |
98a8e6fc | 955 | mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); |
e161105e | 956 | return err; |
e126ba97 EC |
957 | } |
958 | ||
b8a92577 | 959 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); |
e3297246 | 960 | if (err) { |
98a8e6fc HN |
961 | mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", |
962 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 963 | goto err_cmd_cleanup; |
e3297246 EC |
964 | } |
965 | ||
0b107106 | 966 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b | 967 | if (err) { |
98a8e6fc | 968 | mlx5_core_err(dev, "enable hca failed\n"); |
59211bd3 | 969 | goto err_cmd_cleanup; |
cd23b14b EC |
970 | } |
971 | ||
f62b8bb8 AV |
972 | err = mlx5_core_set_issi(dev); |
973 | if (err) { | |
98a8e6fc | 974 | mlx5_core_err(dev, "failed to set issi\n"); |
f62b8bb8 AV |
975 | goto err_disable_hca; |
976 | } | |
f62b8bb8 | 977 | |
cd23b14b EC |
978 | err = mlx5_satisfy_startup_pages(dev, 1); |
979 | if (err) { | |
98a8e6fc | 980 | mlx5_core_err(dev, "failed to allocate boot pages\n"); |
cd23b14b EC |
981 | goto err_disable_hca; |
982 | } | |
983 | ||
e126ba97 EC |
984 | err = set_hca_ctrl(dev); |
985 | if (err) { | |
98a8e6fc | 986 | mlx5_core_err(dev, "set_hca_ctrl failed\n"); |
cd23b14b | 987 | goto reclaim_boot_pages; |
e126ba97 EC |
988 | } |
989 | ||
37b6bb77 | 990 | err = set_hca_cap(dev); |
f91e6d89 | 991 | if (err) { |
98a8e6fc | 992 | mlx5_core_err(dev, "set_hca_cap failed\n"); |
46861e3e MS |
993 | goto reclaim_boot_pages; |
994 | } | |
995 | ||
cd23b14b | 996 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 997 | if (err) { |
98a8e6fc | 998 | mlx5_core_err(dev, "failed to allocate init pages\n"); |
cd23b14b | 999 | goto reclaim_boot_pages; |
e126ba97 EC |
1000 | } |
1001 | ||
8737f818 | 1002 | err = mlx5_cmd_init_hca(dev, sw_owner_id); |
e126ba97 | 1003 | if (err) { |
98a8e6fc | 1004 | mlx5_core_err(dev, "init hca failed\n"); |
0cf53c12 | 1005 | goto reclaim_boot_pages; |
e126ba97 EC |
1006 | } |
1007 | ||
012e50e1 HN |
1008 | mlx5_set_driver_version(dev); |
1009 | ||
e126ba97 EC |
1010 | mlx5_start_health_poll(dev); |
1011 | ||
bba1574c DJ |
1012 | err = mlx5_query_hca_caps(dev); |
1013 | if (err) { | |
98a8e6fc | 1014 | mlx5_core_err(dev, "query hca failed\n"); |
e161105e | 1015 | goto stop_health; |
bba1574c DJ |
1016 | } |
1017 | ||
e161105e SM |
1018 | return 0; |
1019 | ||
1020 | stop_health: | |
1021 | mlx5_stop_health_poll(dev, boot); | |
1022 | reclaim_boot_pages: | |
1023 | mlx5_reclaim_startup_pages(dev); | |
1024 | err_disable_hca: | |
1025 | mlx5_core_disable_hca(dev, 0); | |
1026 | err_cmd_cleanup: | |
1027 | mlx5_cmd_cleanup(dev); | |
1028 | ||
1029 | return err; | |
1030 | } | |
1031 | ||
1032 | static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) | |
1033 | { | |
1034 | int err; | |
1035 | ||
1036 | mlx5_stop_health_poll(dev, boot); | |
1037 | err = mlx5_cmd_teardown_hca(dev); | |
1038 | if (err) { | |
98a8e6fc | 1039 | mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); |
e161105e | 1040 | return err; |
e126ba97 | 1041 | } |
e161105e SM |
1042 | mlx5_reclaim_startup_pages(dev); |
1043 | mlx5_core_disable_hca(dev, 0); | |
1044 | mlx5_cmd_cleanup(dev); | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
a80d1b68 | 1049 | static int mlx5_load(struct mlx5_core_dev *dev) |
e161105e | 1050 | { |
e161105e | 1051 | int err; |
e126ba97 | 1052 | |
01187175 | 1053 | dev->priv.uar = mlx5_get_uars_page(dev); |
72f36be0 | 1054 | if (IS_ERR(dev->priv.uar)) { |
98a8e6fc | 1055 | mlx5_core_err(dev, "Failed allocating uar, aborting\n"); |
72f36be0 | 1056 | err = PTR_ERR(dev->priv.uar); |
a80d1b68 | 1057 | return err; |
e126ba97 EC |
1058 | } |
1059 | ||
69c1280b | 1060 | mlx5_events_start(dev); |
0cf53c12 SM |
1061 | mlx5_pagealloc_start(dev); |
1062 | ||
e1706e62 YA |
1063 | err = mlx5_irq_table_create(dev); |
1064 | if (err) { | |
1065 | mlx5_core_err(dev, "Failed to alloc IRQs\n"); | |
1066 | goto err_irq_table; | |
1067 | } | |
1068 | ||
c8e21b3b | 1069 | err = mlx5_eq_table_create(dev); |
e126ba97 | 1070 | if (err) { |
98a8e6fc | 1071 | mlx5_core_err(dev, "Failed to create EQs\n"); |
c8e21b3b | 1072 | goto err_eq_table; |
e126ba97 EC |
1073 | } |
1074 | ||
24406953 FD |
1075 | err = mlx5_fw_tracer_init(dev->tracer); |
1076 | if (err) { | |
98a8e6fc | 1077 | mlx5_core_err(dev, "Failed to init FW tracer\n"); |
24406953 FD |
1078 | goto err_fw_tracer; |
1079 | } | |
1080 | ||
87175120 EBE |
1081 | mlx5_hv_vhca_init(dev->hv_vhca); |
1082 | ||
12206b17 AL |
1083 | err = mlx5_rsc_dump_init(dev); |
1084 | if (err) { | |
1085 | mlx5_core_err(dev, "Failed to init Resource dump\n"); | |
1086 | goto err_rsc_dump; | |
1087 | } | |
1088 | ||
04e87170 MB |
1089 | err = mlx5_fpga_device_start(dev); |
1090 | if (err) { | |
98a8e6fc | 1091 | mlx5_core_err(dev, "fpga device start failed %d\n", err); |
04e87170 MB |
1092 | goto err_fpga_start; |
1093 | } | |
1094 | ||
1095 | err = mlx5_accel_ipsec_init(dev); | |
1096 | if (err) { | |
98a8e6fc | 1097 | mlx5_core_err(dev, "IPSec device start failed %d\n", err); |
04e87170 MB |
1098 | goto err_ipsec_start; |
1099 | } | |
1100 | ||
1ae17322 IL |
1101 | err = mlx5_accel_tls_init(dev); |
1102 | if (err) { | |
98a8e6fc | 1103 | mlx5_core_err(dev, "TLS device start failed %d\n", err); |
1ae17322 IL |
1104 | goto err_tls_start; |
1105 | } | |
1106 | ||
86d722ad | 1107 | err = mlx5_init_fs(dev); |
59211bd3 | 1108 | if (err) { |
98a8e6fc | 1109 | mlx5_core_err(dev, "Failed to init flow steering\n"); |
c85023e1 | 1110 | goto err_fs; |
59211bd3 | 1111 | } |
e126ba97 | 1112 | |
c85023e1 | 1113 | err = mlx5_core_set_hca_defaults(dev); |
86d722ad | 1114 | if (err) { |
98a8e6fc | 1115 | mlx5_core_err(dev, "Failed to set hca defaults\n"); |
87883929 | 1116 | goto err_sriov; |
86d722ad | 1117 | } |
1466cc5b | 1118 | |
c2d6e31a | 1119 | err = mlx5_sriov_attach(dev); |
fc50db98 | 1120 | if (err) { |
98a8e6fc | 1121 | mlx5_core_err(dev, "sriov init failed %d\n", err); |
fc50db98 EC |
1122 | goto err_sriov; |
1123 | } | |
1124 | ||
22e939a9 BW |
1125 | err = mlx5_ec_init(dev); |
1126 | if (err) { | |
98a8e6fc | 1127 | mlx5_core_err(dev, "Failed to init embedded CPU\n"); |
22e939a9 BW |
1128 | goto err_ec; |
1129 | } | |
1130 | ||
e126ba97 EC |
1131 | return 0; |
1132 | ||
22e939a9 | 1133 | err_ec: |
c2d6e31a | 1134 | mlx5_sriov_detach(dev); |
59211bd3 | 1135 | err_sriov: |
86d722ad MG |
1136 | mlx5_cleanup_fs(dev); |
1137 | err_fs: | |
1ae17322 | 1138 | mlx5_accel_tls_cleanup(dev); |
1ae17322 | 1139 | err_tls_start: |
04e87170 | 1140 | mlx5_accel_ipsec_cleanup(dev); |
04e87170 MB |
1141 | err_ipsec_start: |
1142 | mlx5_fpga_device_stop(dev); | |
04e87170 | 1143 | err_fpga_start: |
12206b17 AL |
1144 | mlx5_rsc_dump_cleanup(dev); |
1145 | err_rsc_dump: | |
87175120 | 1146 | mlx5_hv_vhca_cleanup(dev->hv_vhca); |
24406953 | 1147 | mlx5_fw_tracer_cleanup(dev->tracer); |
24406953 | 1148 | err_fw_tracer: |
c8e21b3b | 1149 | mlx5_eq_table_destroy(dev); |
c8e21b3b | 1150 | err_eq_table: |
e1706e62 YA |
1151 | mlx5_irq_table_destroy(dev); |
1152 | err_irq_table: | |
0cf53c12 | 1153 | mlx5_pagealloc_stop(dev); |
69c1280b | 1154 | mlx5_events_stop(dev); |
868bc06b | 1155 | mlx5_put_uars_page(dev, dev->priv.uar); |
a80d1b68 SM |
1156 | return err; |
1157 | } | |
e126ba97 | 1158 | |
a80d1b68 SM |
1159 | static void mlx5_unload(struct mlx5_core_dev *dev) |
1160 | { | |
1161 | mlx5_ec_cleanup(dev); | |
1162 | mlx5_sriov_detach(dev); | |
1163 | mlx5_cleanup_fs(dev); | |
1164 | mlx5_accel_ipsec_cleanup(dev); | |
1165 | mlx5_accel_tls_cleanup(dev); | |
1166 | mlx5_fpga_device_stop(dev); | |
12206b17 | 1167 | mlx5_rsc_dump_cleanup(dev); |
87175120 | 1168 | mlx5_hv_vhca_cleanup(dev->hv_vhca); |
a80d1b68 SM |
1169 | mlx5_fw_tracer_cleanup(dev->tracer); |
1170 | mlx5_eq_table_destroy(dev); | |
e1706e62 | 1171 | mlx5_irq_table_destroy(dev); |
a80d1b68 SM |
1172 | mlx5_pagealloc_stop(dev); |
1173 | mlx5_events_stop(dev); | |
1174 | mlx5_put_uars_page(dev, dev->priv.uar); | |
1175 | } | |
59211bd3 | 1176 | |
4383cfcc | 1177 | int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) |
a80d1b68 | 1178 | { |
a80d1b68 SM |
1179 | int err = 0; |
1180 | ||
a80d1b68 SM |
1181 | mutex_lock(&dev->intf_state_mutex); |
1182 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { | |
1183 | mlx5_core_warn(dev, "interface is up, NOP\n"); | |
1184 | goto out; | |
1bde6e30 | 1185 | } |
a80d1b68 SM |
1186 | /* remove any previous indication of internal error */ |
1187 | dev->state = MLX5_DEVICE_STATE_UP; | |
e126ba97 | 1188 | |
a80d1b68 SM |
1189 | err = mlx5_function_setup(dev, boot); |
1190 | if (err) | |
1191 | goto out; | |
e126ba97 | 1192 | |
a80d1b68 SM |
1193 | if (boot) { |
1194 | err = mlx5_init_once(dev); | |
1195 | if (err) { | |
98a8e6fc | 1196 | mlx5_core_err(dev, "sw objs init failed\n"); |
a80d1b68 SM |
1197 | goto function_teardown; |
1198 | } | |
1199 | } | |
cd23b14b | 1200 | |
a80d1b68 SM |
1201 | err = mlx5_load(dev); |
1202 | if (err) | |
1203 | goto err_load; | |
e126ba97 | 1204 | |
a6f3b623 MG |
1205 | if (boot) { |
1206 | err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); | |
1207 | if (err) | |
1208 | goto err_devlink_reg; | |
1209 | } | |
1210 | ||
ecd01db8 | 1211 | if (mlx5_device_registered(dev)) |
a80d1b68 | 1212 | mlx5_attach_device(dev); |
ecd01db8 PP |
1213 | else |
1214 | mlx5_register_device(dev); | |
a80d1b68 SM |
1215 | |
1216 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
1217 | out: | |
1218 | mutex_unlock(&dev->intf_state_mutex); | |
e126ba97 | 1219 | |
a80d1b68 SM |
1220 | return err; |
1221 | ||
a6f3b623 | 1222 | err_devlink_reg: |
a80d1b68 SM |
1223 | mlx5_unload(dev); |
1224 | err_load: | |
59211bd3 MHY |
1225 | if (boot) |
1226 | mlx5_cleanup_once(dev); | |
e161105e SM |
1227 | function_teardown: |
1228 | mlx5_function_teardown(dev, boot); | |
89d44f0a MD |
1229 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; |
1230 | mutex_unlock(&dev->intf_state_mutex); | |
1231 | ||
e126ba97 EC |
1232 | return err; |
1233 | } | |
e126ba97 | 1234 | |
f999b706 | 1235 | void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) |
e126ba97 | 1236 | { |
0000a5f2 PP |
1237 | if (cleanup) { |
1238 | mlx5_unregister_device(dev); | |
63cbc552 | 1239 | mlx5_drain_health_wq(dev); |
0000a5f2 | 1240 | } |
689a248d | 1241 | |
89d44f0a | 1242 | mutex_lock(&dev->intf_state_mutex); |
b3cb5388 | 1243 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
98a8e6fc HN |
1244 | mlx5_core_warn(dev, "%s: interface is down, NOP\n", |
1245 | __func__); | |
59211bd3 MHY |
1246 | if (cleanup) |
1247 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1248 | goto out; |
1249 | } | |
6b6adee3 | 1250 | |
9ade8c7c | 1251 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
9ade8c7c | 1252 | |
737a234b MHY |
1253 | if (mlx5_device_registered(dev)) |
1254 | mlx5_detach_device(dev); | |
1255 | ||
a80d1b68 SM |
1256 | mlx5_unload(dev); |
1257 | ||
59211bd3 MHY |
1258 | if (cleanup) |
1259 | mlx5_cleanup_once(dev); | |
9603b61d | 1260 | |
e161105e | 1261 | mlx5_function_teardown(dev, cleanup); |
ac6ea6e8 | 1262 | out: |
89d44f0a | 1263 | mutex_unlock(&dev->intf_state_mutex); |
9603b61d | 1264 | } |
64613d94 | 1265 | |
27b942fb | 1266 | static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) |
9603b61d | 1267 | { |
11f3b84d | 1268 | struct mlx5_priv *priv = &dev->priv; |
9603b61d JM |
1269 | int err; |
1270 | ||
11f3b84d | 1271 | dev->profile = &profile[profile_idx]; |
9603b61d | 1272 | |
364d1798 EC |
1273 | INIT_LIST_HEAD(&priv->ctx_list); |
1274 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a | 1275 | mutex_init(&dev->intf_state_mutex); |
d9aaed83 | 1276 | |
01187175 EC |
1277 | mutex_init(&priv->bfregs.reg_head.lock); |
1278 | mutex_init(&priv->bfregs.wc_head.lock); | |
1279 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1280 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1281 | ||
11f3b84d SM |
1282 | mutex_init(&priv->alloc_mutex); |
1283 | mutex_init(&priv->pgdir_mutex); | |
1284 | INIT_LIST_HEAD(&priv->pgdir_list); | |
11f3b84d | 1285 | |
27b942fb PP |
1286 | priv->dbg_root = debugfs_create_dir(dev_name(dev->device), |
1287 | mlx5_debugfs_root); | |
11f3b84d | 1288 | if (!priv->dbg_root) { |
27b942fb | 1289 | dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); |
11f3b84d | 1290 | return -ENOMEM; |
9603b61d JM |
1291 | } |
1292 | ||
ac6ea6e8 | 1293 | err = mlx5_health_init(dev); |
52c368dc SM |
1294 | if (err) |
1295 | goto err_health_init; | |
ac6ea6e8 | 1296 | |
0cf53c12 SM |
1297 | err = mlx5_pagealloc_init(dev); |
1298 | if (err) | |
1299 | goto err_pagealloc_init; | |
59211bd3 | 1300 | |
11f3b84d | 1301 | return 0; |
52c368dc SM |
1302 | |
1303 | err_pagealloc_init: | |
1304 | mlx5_health_cleanup(dev); | |
1305 | err_health_init: | |
1306 | debugfs_remove(dev->priv.dbg_root); | |
1307 | ||
1308 | return err; | |
11f3b84d SM |
1309 | } |
1310 | ||
1311 | static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) | |
1312 | { | |
52c368dc SM |
1313 | mlx5_pagealloc_cleanup(dev); |
1314 | mlx5_health_cleanup(dev); | |
11f3b84d SM |
1315 | debugfs_remove_recursive(dev->priv.dbg_root); |
1316 | } | |
1317 | ||
59211bd3 | 1318 | #define MLX5_IB_MOD "mlx5_ib" |
11f3b84d | 1319 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
9603b61d JM |
1320 | { |
1321 | struct mlx5_core_dev *dev; | |
feae9087 | 1322 | struct devlink *devlink; |
9603b61d JM |
1323 | int err; |
1324 | ||
1f28d776 | 1325 | devlink = mlx5_devlink_alloc(); |
feae9087 | 1326 | if (!devlink) { |
1f28d776 | 1327 | dev_err(&pdev->dev, "devlink alloc failed\n"); |
9603b61d JM |
1328 | return -ENOMEM; |
1329 | } | |
feae9087 OG |
1330 | |
1331 | dev = devlink_priv(devlink); | |
27b942fb PP |
1332 | dev->device = &pdev->dev; |
1333 | dev->pdev = pdev; | |
9603b61d | 1334 | |
386e75af HN |
1335 | dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? |
1336 | MLX5_COREDEV_VF : MLX5_COREDEV_PF; | |
1337 | ||
27b942fb | 1338 | err = mlx5_mdev_init(dev, prof_sel); |
11f3b84d SM |
1339 | if (err) |
1340 | goto mdev_init_err; | |
01187175 | 1341 | |
11f3b84d | 1342 | err = mlx5_pci_init(dev, pdev, id); |
9603b61d | 1343 | if (err) { |
98a8e6fc HN |
1344 | mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", |
1345 | err); | |
11f3b84d | 1346 | goto pci_init_err; |
9603b61d JM |
1347 | } |
1348 | ||
868bc06b | 1349 | err = mlx5_load_one(dev, true); |
9603b61d | 1350 | if (err) { |
98a8e6fc HN |
1351 | mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", |
1352 | err); | |
0cf53c12 | 1353 | goto err_load_one; |
9603b61d | 1354 | } |
59211bd3 | 1355 | |
f82eed45 | 1356 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1357 | |
8b9d8baa AV |
1358 | err = mlx5_crdump_enable(dev); |
1359 | if (err) | |
1360 | dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); | |
1361 | ||
5d47f6c8 | 1362 | pci_save_state(pdev); |
9603b61d JM |
1363 | return 0; |
1364 | ||
0cf53c12 | 1365 | err_load_one: |
868bc06b | 1366 | mlx5_pci_close(dev); |
11f3b84d SM |
1367 | pci_init_err: |
1368 | mlx5_mdev_uninit(dev); | |
1369 | mdev_init_err: | |
1f28d776 | 1370 | mlx5_devlink_free(devlink); |
a31208b1 | 1371 | |
9603b61d JM |
1372 | return err; |
1373 | } | |
a31208b1 | 1374 | |
9603b61d JM |
1375 | static void remove_one(struct pci_dev *pdev) |
1376 | { | |
1377 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1378 | struct devlink *devlink = priv_to_devlink(dev); |
9603b61d | 1379 | |
8b9d8baa | 1380 | mlx5_crdump_disable(dev); |
1f28d776 | 1381 | mlx5_devlink_unregister(devlink); |
737a234b | 1382 | |
f999b706 | 1383 | mlx5_unload_one(dev, true); |
868bc06b | 1384 | mlx5_pci_close(dev); |
11f3b84d | 1385 | mlx5_mdev_uninit(dev); |
1f28d776 | 1386 | mlx5_devlink_free(devlink); |
9603b61d JM |
1387 | } |
1388 | ||
89d44f0a MD |
1389 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1390 | pci_channel_state_t state) | |
1391 | { | |
1392 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a | 1393 | |
98a8e6fc | 1394 | mlx5_core_info(dev, "%s was called\n", __func__); |
04c0c1ab | 1395 | |
8812c24d | 1396 | mlx5_enter_error_state(dev, false); |
3e5b72ac | 1397 | mlx5_error_sw_reset(dev); |
868bc06b | 1398 | mlx5_unload_one(dev, false); |
b3bd076f MS |
1399 | mlx5_drain_health_wq(dev); |
1400 | mlx5_pci_disable_device(dev); | |
05ac2c0b | 1401 | |
89d44f0a MD |
1402 | return state == pci_channel_io_perm_failure ? |
1403 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1404 | } | |
1405 | ||
d57847dc DJ |
1406 | /* wait for the device to show vital signs by waiting |
1407 | * for the health counter to start counting. | |
89d44f0a | 1408 | */ |
d57847dc | 1409 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1410 | { |
1411 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1412 | struct mlx5_core_health *health = &dev->priv.health; | |
1413 | const int niter = 100; | |
d57847dc | 1414 | u32 last_count = 0; |
89d44f0a | 1415 | u32 count; |
89d44f0a MD |
1416 | int i; |
1417 | ||
89d44f0a MD |
1418 | for (i = 0; i < niter; i++) { |
1419 | count = ioread32be(health->health_counter); | |
1420 | if (count && count != 0xffffffff) { | |
d57847dc | 1421 | if (last_count && last_count != count) { |
98a8e6fc HN |
1422 | mlx5_core_info(dev, |
1423 | "wait vital counter value 0x%x after %d iterations\n", | |
1424 | count, i); | |
d57847dc DJ |
1425 | return 0; |
1426 | } | |
1427 | last_count = count; | |
89d44f0a MD |
1428 | } |
1429 | msleep(50); | |
1430 | } | |
1431 | ||
d57847dc | 1432 | return -ETIMEDOUT; |
89d44f0a MD |
1433 | } |
1434 | ||
1061c90f | 1435 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1436 | { |
1437 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1438 | int err; |
1439 | ||
98a8e6fc | 1440 | mlx5_core_info(dev, "%s was called\n", __func__); |
89d44f0a | 1441 | |
1061c90f | 1442 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1443 | if (err) { |
98a8e6fc HN |
1444 | mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", |
1445 | __func__, err); | |
1061c90f MHY |
1446 | return PCI_ERS_RESULT_DISCONNECT; |
1447 | } | |
1448 | ||
1449 | pci_set_master(pdev); | |
1450 | pci_restore_state(pdev); | |
5d47f6c8 | 1451 | pci_save_state(pdev); |
1061c90f MHY |
1452 | |
1453 | if (wait_vital(pdev)) { | |
98a8e6fc | 1454 | mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1455 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1456 | } |
89d44f0a | 1457 | |
1061c90f MHY |
1458 | return PCI_ERS_RESULT_RECOVERED; |
1459 | } | |
1460 | ||
1061c90f MHY |
1461 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1462 | { | |
1463 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1061c90f MHY |
1464 | int err; |
1465 | ||
98a8e6fc | 1466 | mlx5_core_info(dev, "%s was called\n", __func__); |
1061c90f | 1467 | |
868bc06b | 1468 | err = mlx5_load_one(dev, false); |
89d44f0a | 1469 | if (err) |
98a8e6fc HN |
1470 | mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", |
1471 | __func__, err); | |
89d44f0a | 1472 | else |
98a8e6fc | 1473 | mlx5_core_info(dev, "%s: device recovered\n", __func__); |
89d44f0a MD |
1474 | } |
1475 | ||
1476 | static const struct pci_error_handlers mlx5_err_handler = { | |
1477 | .error_detected = mlx5_pci_err_detected, | |
1478 | .slot_reset = mlx5_pci_slot_reset, | |
1479 | .resume = mlx5_pci_resume | |
1480 | }; | |
1481 | ||
8812c24d MD |
1482 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1483 | { | |
fcd29ad1 FD |
1484 | bool fast_teardown = false, force_teardown = false; |
1485 | int ret = 1; | |
1486 | ||
1487 | fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); | |
1488 | force_teardown = MLX5_CAP_GEN(dev, force_teardown); | |
1489 | ||
1490 | mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); | |
1491 | mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); | |
8812c24d | 1492 | |
fcd29ad1 | 1493 | if (!fast_teardown && !force_teardown) |
8812c24d | 1494 | return -EOPNOTSUPP; |
8812c24d MD |
1495 | |
1496 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1497 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1498 | return -EAGAIN; | |
1499 | } | |
1500 | ||
d2aa060d HN |
1501 | /* Panic tear down fw command will stop the PCI bus communication |
1502 | * with the HCA, so the health polll is no longer needed. | |
1503 | */ | |
1504 | mlx5_drain_health_wq(dev); | |
76d5581c | 1505 | mlx5_stop_health_poll(dev, false); |
d2aa060d | 1506 | |
fcd29ad1 FD |
1507 | ret = mlx5_cmd_fast_teardown_hca(dev); |
1508 | if (!ret) | |
1509 | goto succeed; | |
1510 | ||
8812c24d | 1511 | ret = mlx5_cmd_force_teardown_hca(dev); |
fcd29ad1 FD |
1512 | if (!ret) |
1513 | goto succeed; | |
1514 | ||
1515 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1516 | mlx5_start_health_poll(dev); | |
1517 | return ret; | |
8812c24d | 1518 | |
fcd29ad1 | 1519 | succeed: |
8812c24d MD |
1520 | mlx5_enter_error_state(dev, true); |
1521 | ||
1ef903bf DJ |
1522 | /* Some platforms requiring freeing the IRQ's in the shutdown |
1523 | * flow. If they aren't freed they can't be allocated after | |
1524 | * kexec. There is no need to cleanup the mlx5_core software | |
1525 | * contexts. | |
1526 | */ | |
1ef903bf DJ |
1527 | mlx5_core_eq_free_irqs(dev); |
1528 | ||
8812c24d MD |
1529 | return 0; |
1530 | } | |
1531 | ||
5fc7197d MD |
1532 | static void shutdown(struct pci_dev *pdev) |
1533 | { | |
1534 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
8812c24d | 1535 | int err; |
5fc7197d | 1536 | |
98a8e6fc | 1537 | mlx5_core_info(dev, "Shutdown was called\n"); |
8812c24d MD |
1538 | err = mlx5_try_fast_unload(dev); |
1539 | if (err) | |
868bc06b | 1540 | mlx5_unload_one(dev, false); |
5fc7197d MD |
1541 | mlx5_pci_disable_device(dev); |
1542 | } | |
1543 | ||
9603b61d | 1544 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1545 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1546 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1547 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1548 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1549 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1550 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1551 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1552 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1553 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1554 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1555 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1556 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
85327a9c EBE |
1557 | { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ |
1558 | { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ | |
b7eca940 | 1559 | { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ |
505a7f54 | 1560 | { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ |
2e9d3e83 NO |
1561 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1562 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
d19a79ee | 1563 | { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ |
9603b61d JM |
1564 | { 0, } |
1565 | }; | |
1566 | ||
1567 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1568 | ||
04c0c1ab MHY |
1569 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1570 | { | |
b3bd076f MS |
1571 | mlx5_error_sw_reset(dev); |
1572 | mlx5_unload_one(dev, false); | |
04c0c1ab MHY |
1573 | } |
1574 | ||
1575 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1576 | { | |
1577 | mlx5_pci_disable_device(dev); | |
1578 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1579 | mlx5_pci_resume(dev->pdev); | |
1580 | } | |
1581 | ||
9603b61d JM |
1582 | static struct pci_driver mlx5_core_driver = { |
1583 | .name = DRIVER_NAME, | |
1584 | .id_table = mlx5_core_pci_table, | |
1585 | .probe = init_one, | |
89d44f0a | 1586 | .remove = remove_one, |
5fc7197d | 1587 | .shutdown = shutdown, |
fc50db98 EC |
1588 | .err_handler = &mlx5_err_handler, |
1589 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1590 | }; |
e126ba97 | 1591 | |
f663ad98 KH |
1592 | static void mlx5_core_verify_params(void) |
1593 | { | |
1594 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1595 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1596 | prof_sel, | |
1597 | ARRAY_SIZE(profile) - 1, | |
1598 | MLX5_DEFAULT_PROF); | |
1599 | prof_sel = MLX5_DEFAULT_PROF; | |
1600 | } | |
1601 | } | |
1602 | ||
e126ba97 EC |
1603 | static int __init init(void) |
1604 | { | |
1605 | int err; | |
1606 | ||
8737f818 DJ |
1607 | get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); |
1608 | ||
f663ad98 | 1609 | mlx5_core_verify_params(); |
c778dd31 | 1610 | mlx5_accel_ipsec_build_fs_cmds(); |
e126ba97 | 1611 | mlx5_register_debugfs(); |
e126ba97 | 1612 | |
9603b61d JM |
1613 | err = pci_register_driver(&mlx5_core_driver); |
1614 | if (err) | |
ac6ea6e8 | 1615 | goto err_debug; |
9603b61d | 1616 | |
f62b8bb8 AV |
1617 | #ifdef CONFIG_MLX5_CORE_EN |
1618 | mlx5e_init(); | |
1619 | #endif | |
1620 | ||
e126ba97 EC |
1621 | return 0; |
1622 | ||
e126ba97 EC |
1623 | err_debug: |
1624 | mlx5_unregister_debugfs(); | |
1625 | return err; | |
1626 | } | |
1627 | ||
1628 | static void __exit cleanup(void) | |
1629 | { | |
f62b8bb8 AV |
1630 | #ifdef CONFIG_MLX5_CORE_EN |
1631 | mlx5e_cleanup(); | |
1632 | #endif | |
9603b61d | 1633 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1634 | mlx5_unregister_debugfs(); |
1635 | } | |
1636 | ||
1637 | module_init(init); | |
1638 | module_exit(cleanup); |