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net/mlx5: Unify and improve command interface
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
89d44f0a 49#include <linux/delay.h>
b775516b 50#include <linux/mlx5/mlx5_ifc.h>
5a7b27eb
MG		 51#ifdef CONFIG_RFS_ACCEL
52#include <linux/cpu_rmap.h>
53#endif
feae9087 54#include <net/devlink.h>
e126ba97 55#include "mlx5_core.h"
86d722ad 56#include "fs_core.h"
073bb189
SM		 57#ifdef CONFIG_MLX5_CORE_EN
58#include "eswitch.h"
59#endif
e126ba97 60
e126ba97 61MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 62MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 63MODULE_LICENSE("Dual BSD/GPL");
64MODULE_VERSION(DRIVER_VERSION);
65
66int mlx5_core_debug_mask;
67module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
68MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
69
9603b61d
JM		 70#define MLX5_DEFAULT_PROF 2
71static int prof_sel = MLX5_DEFAULT_PROF;
72module_param_named(prof_sel, prof_sel, int, 0444);
73MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
74
9603b61d
JM		 75static LIST_HEAD(intf_list);
76static LIST_HEAD(dev_list);
77static DEFINE_MUTEX(intf_mutex);
78
79struct mlx5_device_context {
80 struct list_head list;
81 struct mlx5_interface *intf;
82 void *context;
83};
84
f91e6d89
EBE		 85enum {
86 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
87 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
88};
89
9603b61d
JM		 90static struct mlx5_profile profile[] = {
91 [0] = {
92 .mask = 0,
93 },
94 [1] = {
95 .mask = MLX5_PROF_MASK_QP_SIZE,
96 .log_max_qp = 12,
97 },
98 [2] = {
99 .mask = MLX5_PROF_MASK_QP_SIZE |
100 MLX5_PROF_MASK_MR_CACHE,
101 .log_max_qp = 17,
102 .mr_cache[0] = {
103 .size = 500,
104 .limit = 250
105 },
106 .mr_cache[1] = {
107 .size = 500,
108 .limit = 250
109 },
110 .mr_cache[2] = {
111 .size = 500,
112 .limit = 250
113 },
114 .mr_cache[3] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[4] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[5] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[6] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[7] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[8] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[9] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[10] = {
143 .size = 500,
144 .limit = 250
145 },
146 .mr_cache[11] = {
147 .size = 500,
148 .limit = 250
149 },
150 .mr_cache[12] = {
151 .size = 64,
152 .limit = 32
153 },
154 .mr_cache[13] = {
155 .size = 32,
156 .limit = 16
157 },
158 .mr_cache[14] = {
159 .size = 16,
160 .limit = 8
161 },
162 .mr_cache[15] = {
163 .size = 8,
164 .limit = 4
165 },
166 },
167};
e126ba97 168
e3297246
EC		 169#define FW_INIT_TIMEOUT_MILI 2000
170#define FW_INIT_WAIT_MS 2
171
172static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
173{
174 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
175 int err = 0;
176
177 while (fw_initializing(dev)) {
178 if (time_after(jiffies, end)) {
179 err = -EBUSY;
180 break;
181 }
182 msleep(FW_INIT_WAIT_MS);
183 }
184
185 return err;
186}
187
e126ba97
EC		 188static int set_dma_caps(struct pci_dev *pdev)
189{
190 int err;
191
192 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
193 if (err) {
1a91de28 194 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 195 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
196 if (err) {
1a91de28 197 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 198 return err;
199 }
200 }
201
202 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
203 if (err) {
204 dev_warn(&pdev->dev,
1a91de28 205 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 206 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
207 if (err) {
208 dev_err(&pdev->dev,
1a91de28 209 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 210 return err;
211 }
212 }
213
214 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
215 return err;
216}
217
89d44f0a
MD		 218static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
219{
220 struct pci_dev *pdev = dev->pdev;
221 int err = 0;
222
223 mutex_lock(&dev->pci_status_mutex);
224 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
225 err = pci_enable_device(pdev);
226 if (!err)
227 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
228 }
229 mutex_unlock(&dev->pci_status_mutex);
230
231 return err;
232}
233
234static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
235{
236 struct pci_dev *pdev = dev->pdev;
237
238 mutex_lock(&dev->pci_status_mutex);
239 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
240 pci_disable_device(pdev);
241 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
242 }
243 mutex_unlock(&dev->pci_status_mutex);
244}
245
e126ba97
EC		 246static int request_bar(struct pci_dev *pdev)
247{
248 int err = 0;
249
250 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 251 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 252 return -ENODEV;
253 }
254
255 err = pci_request_regions(pdev, DRIVER_NAME);
256 if (err)
257 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
258
259 return err;
260}
261
262static void release_bar(struct pci_dev *pdev)
263{
264 pci_release_regions(pdev);
265}
266
267static int mlx5_enable_msix(struct mlx5_core_dev *dev)
268{
db058a18
SM		 269 struct mlx5_priv *priv = &dev->priv;
270 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 271 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 272 int nvec;
e126ba97
EC		 273 int i;
274
938fe83c
SM		 275 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
276 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 277 nvec = min_t(int, nvec, num_eqs);
278 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
279 return -ENOMEM;
280
db058a18
SM		 281 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
282
283 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
284 if (!priv->msix_arr || !priv->irq_info)
285 goto err_free_msix;
e126ba97
EC		 286
287 for (i = 0; i < nvec; i++)
db058a18 288 priv->msix_arr[i].entry = i;
e126ba97 289
db058a18 290 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 291 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 292 if (nvec < 0)
293 return nvec;
e126ba97 294
f3c9407b 295 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 296
297 return 0;
db058a18
SM		 298
299err_free_msix:
300 kfree(priv->irq_info);
301 kfree(priv->msix_arr);
302 return -ENOMEM;
e126ba97
EC		 303}
304
305static void mlx5_disable_msix(struct mlx5_core_dev *dev)
306{
db058a18 307 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 308
309 pci_disable_msix(dev->pdev);
db058a18
SM		 310 kfree(priv->irq_info);
311 kfree(priv->msix_arr);
e126ba97
EC		 312}
313
314struct mlx5_reg_host_endianess {
315 u8 he;
316 u8 rsvd[15];
317};
318
87b8de49
EC		 319
320#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
321
322enum {
c7a08ac7
EC		 323 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
324 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 325};
326
c7a08ac7
EC		 327static u16 to_fw_pkey_sz(u32 size)
328{
329 switch (size) {
330 case 128:
331 return 0;
332 case 256:
333 return 1;
334 case 512:
335 return 2;
336 case 1024:
337 return 3;
338 case 2048:
339 return 4;
340 case 4096:
341 return 5;
342 default:
343 pr_warn("invalid pkey table size %d\n", size);
344 return 0;
345 }
346}
347
b06e7de8
LR		 348static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
349 enum mlx5_cap_type cap_type,
350 enum mlx5_cap_mode cap_mode)
c7a08ac7 351{
b775516b
EC		 352 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
353 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 354 void *out, *hca_caps;
355 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 356 int err;
357
b775516b
EC		 358 memset(in, 0, sizeof(in));
359 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 360 if (!out)
e126ba97 361 return -ENOMEM;
938fe83c 362
b775516b
EC		 363 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
364 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
365 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
c7a08ac7 366 if (err) {
938fe83c
SM		 367 mlx5_core_warn(dev,
368 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
369 cap_type, cap_mode, err);
e126ba97
EC		 370 goto query_ex;
371 }
c7a08ac7 372
938fe83c
SM		 373 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
374
375 switch (cap_mode) {
376 case HCA_CAP_OPMOD_GET_MAX:
377 memcpy(dev->hca_caps_max[cap_type], hca_caps,
378 MLX5_UN_SZ_BYTES(hca_cap_union));
379 break;
380 case HCA_CAP_OPMOD_GET_CUR:
381 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
382 MLX5_UN_SZ_BYTES(hca_cap_union));
383 break;
384 default:
385 mlx5_core_warn(dev,
386 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
387 cap_type, cap_mode);
388 err = -EINVAL;
389 break;
390 }
c7a08ac7
EC		 391query_ex:
392 kfree(out);
393 return err;
394}
395
b06e7de8
LR		 396int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
397{
398 int ret;
399
400 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
401 if (ret)
402 return ret;
403 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
404}
405
f91e6d89 406static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
c7a08ac7 407{
c4f287c4 408 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
e126ba97 409
b775516b 410 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
f91e6d89 411 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
c4f287c4 412 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
c7a08ac7
EC		 413}
414
f91e6d89
EBE		 415static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
416{
417 void *set_ctx;
418 void *set_hca_cap;
419 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
420 int req_endianness;
421 int err;
422
423 if (MLX5_CAP_GEN(dev, atomic)) {
b06e7de8 424 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
f91e6d89
EBE		 425 if (err)
426 return err;
427 } else {
428 return 0;
429 }
430
431 req_endianness =
432 MLX5_CAP_ATOMIC(dev,
433 supported_atomic_req_8B_endianess_mode_1);
434
435 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
436 return 0;
437
438 set_ctx = kzalloc(set_sz, GFP_KERNEL);
439 if (!set_ctx)
440 return -ENOMEM;
441
442 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
443
444 /* Set requestor to host endianness */
445 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
446 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
447
448 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
449
450 kfree(set_ctx);
451 return err;
452}
453
c7a08ac7
EC		 454static int handle_hca_cap(struct mlx5_core_dev *dev)
455{
b775516b 456 void *set_ctx = NULL;
c7a08ac7 457 struct mlx5_profile *prof = dev->profile;
c7a08ac7 458 int err = -ENOMEM;
b775516b 459 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 460 void *set_hca_cap;
c7a08ac7 461
b775516b 462 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 463 if (!set_ctx)
e126ba97 464 goto query_ex;
e126ba97 465
b06e7de8 466 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
e126ba97
EC		 467 if (err)
468 goto query_ex;
469
938fe83c
SM		 470 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
471 capability);
472 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
473 MLX5_ST_SZ_BYTES(cmd_hca_cap));
474
475 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 476 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 477 128);
c7a08ac7 478 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 479 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
480 to_fw_pkey_sz(128));
c7a08ac7
EC		 481
482 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 483 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
484 prof->log_max_qp);
c7a08ac7 485
938fe83c
SM		 486 /* disable cmdif checksum */
487 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 488
fe1e1876
CS		 489 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
490
f91e6d89
EBE		 491 err = set_caps(dev, set_ctx, set_sz,
492 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
c7a08ac7 493
e126ba97 494query_ex:
e126ba97 495 kfree(set_ctx);
e126ba97
EC		 496 return err;
497}
498
499static int set_hca_ctrl(struct mlx5_core_dev *dev)
500{
501 struct mlx5_reg_host_endianess he_in;
502 struct mlx5_reg_host_endianess he_out;
503 int err;
504
fc50db98
EC		 505 if (!mlx5_core_is_pf(dev))
506 return 0;
507
e126ba97
EC		 508 memset(&he_in, 0, sizeof(he_in));
509 he_in.he = MLX5_SET_HOST_ENDIANNESS;
510 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
511 &he_out, sizeof(he_out),
512 MLX5_REG_HOST_ENDIANNESS, 0, 1);
513 return err;
514}
515
0b107106 516int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 517{
c4f287c4
SM		 518 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
519 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
cd23b14b 520
0b107106
EC		 521 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
522 MLX5_SET(enable_hca_in, in, function_id, func_id);
c4f287c4 523 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
cd23b14b
EC		 524}
525
0b107106 526int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 527{
c4f287c4
SM		 528 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
529 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
cd23b14b 530
0b107106
EC		 531 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
532 MLX5_SET(disable_hca_in, in, function_id, func_id);
c4f287c4 533 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
cd23b14b
EC		 534}
535
b0844444
EBE		 536cycle_t mlx5_read_internal_timer(struct mlx5_core_dev *dev)
537{
538 u32 timer_h, timer_h1, timer_l;
539
540 timer_h = ioread32be(&dev->iseg->internal_timer_h);
541 timer_l = ioread32be(&dev->iseg->internal_timer_l);
542 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
543 if (timer_h != timer_h1) /* wrap around */
544 timer_l = ioread32be(&dev->iseg->internal_timer_l);
545
546 return (cycle_t)timer_l | (cycle_t)timer_h1 << 32;
547}
548
db058a18
SM		 549static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
550{
551 struct mlx5_priv *priv = &mdev->priv;
552 struct msix_entry *msix = priv->msix_arr;
553 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
311c7c71 554 int numa_node = priv->numa_node;
db058a18
SM		 555 int err;
556
557 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
558 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
559 return -ENOMEM;
560 }
561
dda922c8
DM		 562 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
563 priv->irq_info[i].mask);
db058a18
SM		 564
565 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
566 if (err) {
567 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
568 irq);
569 goto err_clear_mask;
570 }
571
572 return 0;
573
574err_clear_mask:
575 free_cpumask_var(priv->irq_info[i].mask);
576 return err;
577}
578
579static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
580{
581 struct mlx5_priv *priv = &mdev->priv;
582 struct msix_entry *msix = priv->msix_arr;
583 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
584
585 irq_set_affinity_hint(irq, NULL);
586 free_cpumask_var(priv->irq_info[i].mask);
587}
588
589static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
590{
591 int err;
592 int i;
593
594 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
595 err = mlx5_irq_set_affinity_hint(mdev, i);
596 if (err)
597 goto err_out;
598 }
599
600 return 0;
601
602err_out:
603 for (i--; i >= 0; i--)
604 mlx5_irq_clear_affinity_hint(mdev, i);
605
606 return err;
607}
608
609static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
610{
611 int i;
612
613 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
614 mlx5_irq_clear_affinity_hint(mdev, i);
615}
616
0b6e26ce
DT		 617int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
618 unsigned int *irqn)
233d05d2
SM		 619{
620 struct mlx5_eq_table *table = &dev->priv.eq_table;
621 struct mlx5_eq *eq, *n;
622 int err = -ENOENT;
623
624 spin_lock(&table->lock);
625 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
626 if (eq->index == vector) {
627 *eqn = eq->eqn;
628 *irqn = eq->irqn;
629 err = 0;
630 break;
631 }
632 }
633 spin_unlock(&table->lock);
634
635 return err;
636}
637EXPORT_SYMBOL(mlx5_vector2eqn);
638
94c6825e
MB		 639struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
640{
641 struct mlx5_eq_table *table = &dev->priv.eq_table;
642 struct mlx5_eq *eq;
643
644 spin_lock(&table->lock);
645 list_for_each_entry(eq, &table->comp_eqs_list, list)
646 if (eq->eqn == eqn) {
647 spin_unlock(&table->lock);
648 return eq;
649 }
650
651 spin_unlock(&table->lock);
652
653 return ERR_PTR(-ENOENT);
654}
655
233d05d2
SM		 656static void free_comp_eqs(struct mlx5_core_dev *dev)
657{
658 struct mlx5_eq_table *table = &dev->priv.eq_table;
659 struct mlx5_eq *eq, *n;
660
5a7b27eb
MG		 661#ifdef CONFIG_RFS_ACCEL
662 if (dev->rmap) {
663 free_irq_cpu_rmap(dev->rmap);
664 dev->rmap = NULL;
665 }
666#endif
233d05d2
SM		 667 spin_lock(&table->lock);
668 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
669 list_del(&eq->list);
670 spin_unlock(&table->lock);
671 if (mlx5_destroy_unmap_eq(dev, eq))
672 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
673 eq->eqn);
674 kfree(eq);
675 spin_lock(&table->lock);
676 }
677 spin_unlock(&table->lock);
678}
679
680static int alloc_comp_eqs(struct mlx5_core_dev *dev)
681{
682 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 683 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 684 struct mlx5_eq *eq;
685 int ncomp_vec;
686 int nent;
687 int err;
688 int i;
689
690 INIT_LIST_HEAD(&table->comp_eqs_list);
691 ncomp_vec = table->num_comp_vectors;
692 nent = MLX5_COMP_EQ_SIZE;
5a7b27eb
MG		 693#ifdef CONFIG_RFS_ACCEL
694 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
695 if (!dev->rmap)
696 return -ENOMEM;
697#endif
233d05d2
SM		 698 for (i = 0; i < ncomp_vec; i++) {
699 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
700 if (!eq) {
701 err = -ENOMEM;
702 goto clean;
703 }
704
5a7b27eb
MG		 705#ifdef CONFIG_RFS_ACCEL
706 irq_cpu_rmap_add(dev->rmap,
707 dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector);
708#endif
db058a18 709 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 710 err = mlx5_create_map_eq(dev, eq,
711 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
712 name, &dev->priv.uuari.uars[0]);
713 if (err) {
714 kfree(eq);
715 goto clean;
716 }
717 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
718 eq->index = i;
719 spin_lock(&table->lock);
720 list_add_tail(&eq->list, &table->comp_eqs_list);
721 spin_unlock(&table->lock);
722 }
723
724 return 0;
725
726clean:
727 free_comp_eqs(dev);
728 return err;
729}
730
f62b8bb8
AV		 731static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
732{
c4f287c4
SM		 733 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
734 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
f62b8bb8 735 u32 sup_issi;
c4f287c4 736 int err;
f62b8bb8
AV		 737
738 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
c4f287c4
SM		 739 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
740 query_out, sizeof(query_out));
f62b8bb8 741 if (err) {
c4f287c4
SM		 742 u32 syndrome;
743 u8 status;
744
745 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
746 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
f62b8bb8
AV		 747 pr_debug("Only ISSI 0 is supported\n");
748 return 0;
749 }
750
c4f287c4 751 pr_err("failed to query ISSI err(%d)\n", err);
f62b8bb8
AV		 752 return err;
753 }
754
755 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
756
757 if (sup_issi & (1 << 1)) {
c4f287c4
SM		 758 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
759 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
f62b8bb8
AV		 760
761 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
762 MLX5_SET(set_issi_in, set_in, current_issi, 1);
c4f287c4
SM		 763 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
764 set_out, sizeof(set_out));
f62b8bb8 765 if (err) {
c4f287c4 766 pr_err("failed to set ISSI=1 err(%d)\n", err);
f62b8bb8
AV		 767 return err;
768 }
769
770 dev->issi = 1;
771
772 return 0;
e74a1db0 773 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 774 return 0;
775 }
776
777 return -ENOTSUPP;
778}
f62b8bb8 779
a31208b1
MD		 780static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
781{
782 struct mlx5_device_context *dev_ctx;
783 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
784
785 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
786 if (!dev_ctx)
787 return;
788
789 dev_ctx->intf = intf;
790 dev_ctx->context = intf->add(dev);
791
792 if (dev_ctx->context) {
793 spin_lock_irq(&priv->ctx_lock);
794 list_add_tail(&dev_ctx->list, &priv->ctx_list);
795 spin_unlock_irq(&priv->ctx_lock);
796 } else {
797 kfree(dev_ctx);
798 }
799}
800
801static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
802{
803 struct mlx5_device_context *dev_ctx;
804 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
805
806 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
807 if (dev_ctx->intf == intf) {
808 spin_lock_irq(&priv->ctx_lock);
809 list_del(&dev_ctx->list);
810 spin_unlock_irq(&priv->ctx_lock);
811
812 intf->remove(dev, dev_ctx->context);
813 kfree(dev_ctx);
814 return;
815 }
816}
817
818static int mlx5_register_device(struct mlx5_core_dev *dev)
e126ba97
EC		 819{
820 struct mlx5_priv *priv = &dev->priv;
a31208b1
MD		 821 struct mlx5_interface *intf;
822
823 mutex_lock(&intf_mutex);
824 list_add_tail(&priv->dev_list, &dev_list);
825 list_for_each_entry(intf, &intf_list, list)
826 mlx5_add_device(intf, priv);
827 mutex_unlock(&intf_mutex);
828
829 return 0;
830}
831
832static void mlx5_unregister_device(struct mlx5_core_dev *dev)
833{
834 struct mlx5_priv *priv = &dev->priv;
835 struct mlx5_interface *intf;
836
837 mutex_lock(&intf_mutex);
838 list_for_each_entry(intf, &intf_list, list)
839 mlx5_remove_device(intf, priv);
840 list_del(&priv->dev_list);
841 mutex_unlock(&intf_mutex);
842}
843
844int mlx5_register_interface(struct mlx5_interface *intf)
845{
846 struct mlx5_priv *priv;
847
848 if (!intf->add || !intf->remove)
849 return -EINVAL;
850
851 mutex_lock(&intf_mutex);
852 list_add_tail(&intf->list, &intf_list);
853 list_for_each_entry(priv, &dev_list, dev_list)
854 mlx5_add_device(intf, priv);
855 mutex_unlock(&intf_mutex);
856
857 return 0;
858}
859EXPORT_SYMBOL(mlx5_register_interface);
860
861void mlx5_unregister_interface(struct mlx5_interface *intf)
862{
863 struct mlx5_priv *priv;
864
865 mutex_lock(&intf_mutex);
866 list_for_each_entry(priv, &dev_list, dev_list)
867 mlx5_remove_device(intf, priv);
868 list_del(&intf->list);
869 mutex_unlock(&intf_mutex);
870}
871EXPORT_SYMBOL(mlx5_unregister_interface);
872
873void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
874{
875 struct mlx5_priv *priv = &mdev->priv;
876 struct mlx5_device_context *dev_ctx;
877 unsigned long flags;
878 void *result = NULL;
879
880 spin_lock_irqsave(&priv->ctx_lock, flags);
881
882 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
883 if ((dev_ctx->intf->protocol == protocol) &&
884 dev_ctx->intf->get_dev) {
885 result = dev_ctx->intf->get_dev(dev_ctx->context);
886 break;
887 }
888
889 spin_unlock_irqrestore(&priv->ctx_lock, flags);
890
891 return result;
892}
893EXPORT_SYMBOL(mlx5_get_protocol_dev);
894
895static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
896{
897 struct pci_dev *pdev = dev->pdev;
898 int err = 0;
e126ba97 899
e126ba97
EC		 900 pci_set_drvdata(dev->pdev, dev);
901 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
902 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
903
904 mutex_init(&priv->pgdir_mutex);
905 INIT_LIST_HEAD(&priv->pgdir_list);
906 spin_lock_init(&priv->mkey_lock);
907
311c7c71
SM		 908 mutex_init(&priv->alloc_mutex);
909
910 priv->numa_node = dev_to_node(&dev->pdev->dev);
911
e126ba97
EC		 912 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
913 if (!priv->dbg_root)
914 return -ENOMEM;
915
89d44f0a 916 err = mlx5_pci_enable_device(dev);
e126ba97 917 if (err) {
1a91de28 918 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 919 goto err_dbg;
920 }
921
922 err = request_bar(pdev);
923 if (err) {
1a91de28 924 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 925 goto err_disable;
926 }
927
928 pci_set_master(pdev);
929
930 err = set_dma_caps(pdev);
931 if (err) {
932 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
933 goto err_clr_master;
934 }
935
936 dev->iseg_base = pci_resource_start(dev->pdev, 0);
937 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
938 if (!dev->iseg) {
939 err = -ENOMEM;
940 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
941 goto err_clr_master;
942 }
a31208b1
MD		 943
944 return 0;
945
946err_clr_master:
947 pci_clear_master(dev->pdev);
948 release_bar(dev->pdev);
949err_disable:
89d44f0a 950 mlx5_pci_disable_device(dev);
a31208b1
MD		 951
952err_dbg:
953 debugfs_remove(priv->dbg_root);
954 return err;
955}
956
957static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
958{
959 iounmap(dev->iseg);
960 pci_clear_master(dev->pdev);
961 release_bar(dev->pdev);
89d44f0a 962 mlx5_pci_disable_device(dev);
a31208b1
MD		 963 debugfs_remove(priv->dbg_root);
964}
965
966#define MLX5_IB_MOD "mlx5_ib"
967static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
968{
969 struct pci_dev *pdev = dev->pdev;
970 int err;
971
89d44f0a 972 mutex_lock(&dev->intf_state_mutex);
5fc7197d 973 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 974 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
975 __func__);
976 goto out;
977 }
978
e126ba97
EC		 979 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
980 fw_rev_min(dev), fw_rev_sub(dev));
981
89d44f0a
MD		 982 /* on load removing any previous indication of internal error, device is
983 * up
984 */
985 dev->state = MLX5_DEVICE_STATE_UP;
986
e126ba97
EC		 987 err = mlx5_cmd_init(dev);
988 if (err) {
989 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 990 goto out_err;
e126ba97
EC		 991 }
992
e3297246
EC		 993 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
994 if (err) {
995 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
996 FW_INIT_TIMEOUT_MILI);
997 goto out_err;
998 }
999
e126ba97 1000 mlx5_pagealloc_init(dev);
cd23b14b 1001
0b107106 1002 err = mlx5_core_enable_hca(dev, 0);
cd23b14b
EC		 1003 if (err) {
1004 dev_err(&pdev->dev, "enable hca failed\n");
1005 goto err_pagealloc_cleanup;
1006 }
1007
f62b8bb8
AV		 1008 err = mlx5_core_set_issi(dev);
1009 if (err) {
1010 dev_err(&pdev->dev, "failed to set issi\n");
1011 goto err_disable_hca;
1012 }
f62b8bb8 1013
cd23b14b
EC		 1014 err = mlx5_satisfy_startup_pages(dev, 1);
1015 if (err) {
1016 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1017 goto err_disable_hca;
1018 }
1019
e126ba97
EC		 1020 err = set_hca_ctrl(dev);
1021 if (err) {
1022 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 1023 goto reclaim_boot_pages;
e126ba97
EC		 1024 }
1025
1026 err = handle_hca_cap(dev);
1027 if (err) {
1028 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 1029 goto reclaim_boot_pages;
e126ba97
EC		 1030 }
1031
f91e6d89
EBE		 1032 err = handle_hca_cap_atomic(dev);
1033 if (err) {
1034 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1035 goto reclaim_boot_pages;
e126ba97
EC		 1036 }
1037
cd23b14b 1038 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 1039 if (err) {
cd23b14b
EC		 1040 dev_err(&pdev->dev, "failed to allocate init pages\n");
1041 goto reclaim_boot_pages;
e126ba97
EC		 1042 }
1043
1044 err = mlx5_pagealloc_start(dev);
1045 if (err) {
1046 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 1047 goto reclaim_boot_pages;
e126ba97
EC		 1048 }
1049
1050 err = mlx5_cmd_init_hca(dev);
1051 if (err) {
1052 dev_err(&pdev->dev, "init hca failed\n");
1053 goto err_pagealloc_stop;
1054 }
1055
1056 mlx5_start_health_poll(dev);
1057
938fe83c 1058 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 1059 if (err) {
1060 dev_err(&pdev->dev, "query hca failed\n");
1061 goto err_stop_poll;
1062 }
1063
211e6c80 1064 err = mlx5_query_board_id(dev);
e126ba97 1065 if (err) {
211e6c80 1066 dev_err(&pdev->dev, "query board id failed\n");
e126ba97
EC		 1067 goto err_stop_poll;
1068 }
1069
1070 err = mlx5_enable_msix(dev);
1071 if (err) {
1072 dev_err(&pdev->dev, "enable msix failed\n");
1073 goto err_stop_poll;
1074 }
1075
1076 err = mlx5_eq_init(dev);
1077 if (err) {
1078 dev_err(&pdev->dev, "failed to initialize eq\n");
1079 goto disable_msix;
1080 }
1081
1082 err = mlx5_alloc_uuars(dev, &priv->uuari);
1083 if (err) {
1084 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1085 goto err_eq_cleanup;
1086 }
1087
1088 err = mlx5_start_eqs(dev);
1089 if (err) {
1090 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1091 goto err_free_uar;
1092 }
1093
233d05d2
SM		 1094 err = alloc_comp_eqs(dev);
1095 if (err) {
1096 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1097 goto err_stop_eqs;
1098 }
1099
db058a18 1100 err = mlx5_irq_set_affinity_hints(dev);
0ba42241 1101 if (err)
db058a18 1102 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
db058a18 1103
e126ba97
EC		 1104 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1105
1106 mlx5_init_cq_table(dev);
1107 mlx5_init_qp_table(dev);
1108 mlx5_init_srq_table(dev);
a606b0f6 1109 mlx5_init_mkey_table(dev);
e126ba97 1110
86d722ad
MG		 1111 err = mlx5_init_fs(dev);
1112 if (err) {
1113 dev_err(&pdev->dev, "Failed to init flow steering\n");
1114 goto err_fs;
1115 }
1466cc5b
YP		 1116
1117 err = mlx5_init_rl_table(dev);
1118 if (err) {
1119 dev_err(&pdev->dev, "Failed to init rate limiting\n");
1120 goto err_rl;
1121 }
1122
073bb189
SM		 1123#ifdef CONFIG_MLX5_CORE_EN
1124 err = mlx5_eswitch_init(dev);
1125 if (err) {
1126 dev_err(&pdev->dev, "eswitch init failed %d\n", err);
1127 goto err_reg_dev;
1128 }
1129#endif
1130
fc50db98
EC		 1131 err = mlx5_sriov_init(dev);
1132 if (err) {
1133 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1134 goto err_sriov;
1135 }
1136
a31208b1
MD		 1137 err = mlx5_register_device(dev);
1138 if (err) {
1139 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1140 goto err_reg_dev;
1141 }
1142
1143 err = request_module_nowait(MLX5_IB_MOD);
1144 if (err)
1145 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1146
5fc7197d
MD		 1147 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1148 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
89d44f0a
MD		 1149out:
1150 mutex_unlock(&dev->intf_state_mutex);
1151
e126ba97
EC		 1152 return 0;
1153
fc50db98
EC		 1154err_sriov:
1155 if (mlx5_sriov_cleanup(dev))
1156 dev_err(&dev->pdev->dev, "sriov cleanup failed\n");
1157
073bb189
SM		 1158#ifdef CONFIG_MLX5_CORE_EN
1159 mlx5_eswitch_cleanup(dev->priv.eswitch);
1160#endif
a31208b1 1161err_reg_dev:
1466cc5b
YP		 1162 mlx5_cleanup_rl_table(dev);
1163err_rl:
86d722ad
MG		 1164 mlx5_cleanup_fs(dev);
1165err_fs:
a606b0f6 1166 mlx5_cleanup_mkey_table(dev);
a31208b1
MD		 1167 mlx5_cleanup_srq_table(dev);
1168 mlx5_cleanup_qp_table(dev);
1169 mlx5_cleanup_cq_table(dev);
1170 mlx5_irq_clear_affinity_hints(dev);
db058a18
SM		 1171 free_comp_eqs(dev);
1172
233d05d2
SM		 1173err_stop_eqs:
1174 mlx5_stop_eqs(dev);
1175
e126ba97
EC		 1176err_free_uar:
1177 mlx5_free_uuars(dev, &priv->uuari);
1178
1179err_eq_cleanup:
1180 mlx5_eq_cleanup(dev);
1181
1182disable_msix:
1183 mlx5_disable_msix(dev);
1184
1185err_stop_poll:
1186 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1187 if (mlx5_cmd_teardown_hca(dev)) {
1188 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1189 goto out_err;
1bde6e30 1190 }
e126ba97
EC		 1191
1192err_pagealloc_stop:
1193 mlx5_pagealloc_stop(dev);
1194
cd23b14b 1195reclaim_boot_pages:
e126ba97
EC		 1196 mlx5_reclaim_startup_pages(dev);
1197
cd23b14b 1198err_disable_hca:
0b107106 1199 mlx5_core_disable_hca(dev, 0);
cd23b14b 1200
e126ba97
EC		 1201err_pagealloc_cleanup:
1202 mlx5_pagealloc_cleanup(dev);
1203 mlx5_cmd_cleanup(dev);
1204
89d44f0a
MD		 1205out_err:
1206 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1207 mutex_unlock(&dev->intf_state_mutex);
1208
e126ba97
EC		 1209 return err;
1210}
e126ba97 1211
a31208b1 1212static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
e126ba97 1213{
89d44f0a 1214 int err = 0;
e126ba97 1215
fc50db98
EC		 1216 err = mlx5_sriov_cleanup(dev);
1217 if (err) {
1218 dev_warn(&dev->pdev->dev, "%s: sriov cleanup failed - abort\n",
1219 __func__);
1220 return err;
1221 }
1222
89d44f0a 1223 mutex_lock(&dev->intf_state_mutex);
5fc7197d 1224 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
89d44f0a
MD		 1225 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1226 __func__);
1227 goto out;
1228 }
a31208b1 1229 mlx5_unregister_device(dev);
073bb189
SM		 1230#ifdef CONFIG_MLX5_CORE_EN
1231 mlx5_eswitch_cleanup(dev->priv.eswitch);
1232#endif
1233
1466cc5b 1234 mlx5_cleanup_rl_table(dev);
86d722ad 1235 mlx5_cleanup_fs(dev);
a606b0f6 1236 mlx5_cleanup_mkey_table(dev);
e126ba97
EC		 1237 mlx5_cleanup_srq_table(dev);
1238 mlx5_cleanup_qp_table(dev);
1239 mlx5_cleanup_cq_table(dev);
db058a18 1240 mlx5_irq_clear_affinity_hints(dev);
233d05d2 1241 free_comp_eqs(dev);
e126ba97
EC		 1242 mlx5_stop_eqs(dev);
1243 mlx5_free_uuars(dev, &priv->uuari);
1244 mlx5_eq_cleanup(dev);
1245 mlx5_disable_msix(dev);
1246 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1247 err = mlx5_cmd_teardown_hca(dev);
1248 if (err) {
1bde6e30 1249 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1250 goto out;
1bde6e30 1251 }
e126ba97
EC		 1252 mlx5_pagealloc_stop(dev);
1253 mlx5_reclaim_startup_pages(dev);
0b107106 1254 mlx5_core_disable_hca(dev, 0);
e126ba97
EC		 1255 mlx5_pagealloc_cleanup(dev);
1256 mlx5_cmd_cleanup(dev);
9603b61d 1257
ac6ea6e8 1258out:
5fc7197d
MD		 1259 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1260 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
89d44f0a 1261 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1262 return err;
9603b61d 1263}
64613d94 1264
89d44f0a 1265void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
ac6ea6e8 1266 unsigned long param)
9603b61d
JM		 1267{
1268 struct mlx5_priv *priv = &dev->priv;
1269 struct mlx5_device_context *dev_ctx;
1270 unsigned long flags;
1271
1272 spin_lock_irqsave(&priv->ctx_lock, flags);
1273
1274 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1275 if (dev_ctx->intf->event)
4d2f9bbb 1276 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 1277
1278 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1279}
1280
1281struct mlx5_core_event_handler {
1282 void (*event)(struct mlx5_core_dev *dev,
1283 enum mlx5_dev_event event,
1284 void *data);
1285};
1286
feae9087
OG		 1287static const struct devlink_ops mlx5_devlink_ops = {
1288#ifdef CONFIG_MLX5_CORE_EN
1289 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1290 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1291#endif
1292};
f66f049f 1293
9603b61d
JM		 1294static int init_one(struct pci_dev *pdev,
1295 const struct pci_device_id *id)
1296{
1297 struct mlx5_core_dev *dev;
feae9087 1298 struct devlink *devlink;
9603b61d
JM		 1299 struct mlx5_priv *priv;
1300 int err;
1301
feae9087
OG		 1302 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1303 if (!devlink) {
9603b61d
JM		 1304 dev_err(&pdev->dev, "kzalloc failed\n");
1305 return -ENOMEM;
1306 }
feae9087
OG		 1307
1308 dev = devlink_priv(devlink);
9603b61d 1309 priv = &dev->priv;
fc50db98 1310 priv->pci_dev_data = id->driver_data;
9603b61d
JM		 1311
1312 pci_set_drvdata(pdev, dev);
1313
1314 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1315 pr_warn("selected profile out of range, selecting default (%d)\n",
1316 MLX5_DEFAULT_PROF);
1317 prof_sel = MLX5_DEFAULT_PROF;
1318 }
1319 dev->profile = &profile[prof_sel];
a31208b1 1320 dev->pdev = pdev;
9603b61d
JM		 1321 dev->event = mlx5_core_event;
1322
364d1798
EC		 1323 INIT_LIST_HEAD(&priv->ctx_list);
1324 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1325 mutex_init(&dev->pci_status_mutex);
1326 mutex_init(&dev->intf_state_mutex);
a31208b1 1327 err = mlx5_pci_init(dev, priv);
9603b61d 1328 if (err) {
a31208b1
MD		 1329 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1330 goto clean_dev;
9603b61d
JM		 1331 }
1332
ac6ea6e8
EC		 1333 err = mlx5_health_init(dev);
1334 if (err) {
1335 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1336 goto close_pci;
1337 }
1338
a31208b1 1339 err = mlx5_load_one(dev, priv);
9603b61d 1340 if (err) {
a31208b1 1341 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1342 goto clean_health;
9603b61d
JM		 1343 }
1344
feae9087
OG		 1345 err = devlink_register(devlink, &pdev->dev);
1346 if (err)
1347 goto clean_load;
1348
9603b61d
JM		 1349 return 0;
1350
feae9087
OG		 1351clean_load:
1352 mlx5_unload_one(dev, priv);
ac6ea6e8
EC		 1353clean_health:
1354 mlx5_health_cleanup(dev);
a31208b1
MD		 1355close_pci:
1356 mlx5_pci_close(dev, priv);
1357clean_dev:
1358 pci_set_drvdata(pdev, NULL);
feae9087 1359 devlink_free(devlink);
a31208b1 1360
9603b61d
JM		 1361 return err;
1362}
a31208b1 1363
9603b61d
JM		 1364static void remove_one(struct pci_dev *pdev)
1365{
1366 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
feae9087 1367 struct devlink *devlink = priv_to_devlink(dev);
a31208b1 1368 struct mlx5_priv *priv = &dev->priv;
9603b61d 1369
feae9087 1370 devlink_unregister(devlink);
a31208b1
MD		 1371 if (mlx5_unload_one(dev, priv)) {
1372 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1373 mlx5_health_cleanup(dev);
a31208b1
MD		 1374 return;
1375 }
ac6ea6e8 1376 mlx5_health_cleanup(dev);
a31208b1
MD		 1377 mlx5_pci_close(dev, priv);
1378 pci_set_drvdata(pdev, NULL);
feae9087 1379 devlink_free(devlink);
9603b61d
JM		 1380}
1381
89d44f0a
MD		 1382static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1383 pci_channel_state_t state)
1384{
1385 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1386 struct mlx5_priv *priv = &dev->priv;
1387
1388 dev_info(&pdev->dev, "%s was called\n", __func__);
1389 mlx5_enter_error_state(dev);
1390 mlx5_unload_one(dev, priv);
1391 mlx5_pci_disable_device(dev);
1392 return state == pci_channel_io_perm_failure ?
1393 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1394}
1395
1396static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1397{
1398 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1399 int err = 0;
1400
1401 dev_info(&pdev->dev, "%s was called\n", __func__);
1402
1403 err = mlx5_pci_enable_device(dev);
1404 if (err) {
1405 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1406 , __func__, err);
1407 return PCI_ERS_RESULT_DISCONNECT;
1408 }
1409 pci_set_master(pdev);
1410 pci_set_power_state(pdev, PCI_D0);
1411 pci_restore_state(pdev);
1412
1413 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1414}
1415
1416void mlx5_disable_device(struct mlx5_core_dev *dev)
1417{
1418 mlx5_pci_err_detected(dev->pdev, 0);
1419}
1420
d57847dc
DJ		 1421/* wait for the device to show vital signs by waiting
1422 * for the health counter to start counting.
89d44f0a 1423 */
d57847dc 1424static int wait_vital(struct pci_dev *pdev)
89d44f0a
MD		 1425{
1426 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1427 struct mlx5_core_health *health = &dev->priv.health;
1428 const int niter = 100;
d57847dc 1429 u32 last_count = 0;
89d44f0a 1430 u32 count;
89d44f0a
MD		 1431 int i;
1432
89d44f0a
MD		 1433 for (i = 0; i < niter; i++) {
1434 count = ioread32be(health->health_counter);
1435 if (count && count != 0xffffffff) {
d57847dc
DJ		 1436 if (last_count && last_count != count) {
1437 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1438 return 0;
1439 }
1440 last_count = count;
89d44f0a
MD		 1441 }
1442 msleep(50);
1443 }
1444
d57847dc 1445 return -ETIMEDOUT;
89d44f0a
MD		 1446}
1447
1448static void mlx5_pci_resume(struct pci_dev *pdev)
1449{
1450 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1451 struct mlx5_priv *priv = &dev->priv;
1452 int err;
1453
1454 dev_info(&pdev->dev, "%s was called\n", __func__);
1455
1456 pci_save_state(pdev);
d57847dc
DJ		 1457 err = wait_vital(pdev);
1458 if (err) {
1459 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1460 return;
1461 }
89d44f0a
MD		 1462
1463 err = mlx5_load_one(dev, priv);
1464 if (err)
1465 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1466 , __func__, err);
1467 else
1468 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1469}
1470
1471static const struct pci_error_handlers mlx5_err_handler = {
1472 .error_detected = mlx5_pci_err_detected,
1473 .slot_reset = mlx5_pci_slot_reset,
1474 .resume = mlx5_pci_resume
1475};
1476
5fc7197d
MD		 1477static void shutdown(struct pci_dev *pdev)
1478{
1479 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1480 struct mlx5_priv *priv = &dev->priv;
1481
1482 dev_info(&pdev->dev, "Shutdown was called\n");
1483 /* Notify mlx5 clients that the kernel is being shut down */
1484 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1485 mlx5_unload_one(dev, priv);
1486 mlx5_pci_disable_device(dev);
1487}
1488
9603b61d 1489static const struct pci_device_id mlx5_core_pci_table[] = {
fc50db98
EC		 1490 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1491 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
1492 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1493 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
1494 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1495 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
7092fe86 1496 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
64dbbdfe 1497 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
7092fe86 1498 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */
9603b61d
JM		 1499 { 0, }
1500};
1501
1502MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1503
1504static struct pci_driver mlx5_core_driver = {
1505 .name = DRIVER_NAME,
1506 .id_table = mlx5_core_pci_table,
1507 .probe = init_one,
89d44f0a 1508 .remove = remove_one,
5fc7197d 1509 .shutdown = shutdown,
fc50db98
EC		 1510 .err_handler = &mlx5_err_handler,
1511 .sriov_configure = mlx5_core_sriov_configure,
9603b61d 1512};
e126ba97
EC		 1513
1514static int __init init(void)
1515{
1516 int err;
1517
1518 mlx5_register_debugfs();
e126ba97 1519
9603b61d
JM		 1520 err = pci_register_driver(&mlx5_core_driver);
1521 if (err)
ac6ea6e8 1522 goto err_debug;
9603b61d 1523
f62b8bb8
AV		 1524#ifdef CONFIG_MLX5_CORE_EN
1525 mlx5e_init();
1526#endif
1527
e126ba97
EC		 1528 return 0;
1529
e126ba97
EC		 1530err_debug:
1531 mlx5_unregister_debugfs();
1532 return err;
1533}
1534
1535static void __exit cleanup(void)
1536{
f62b8bb8
AV		 1537#ifdef CONFIG_MLX5_CORE_EN
1538 mlx5e_cleanup();
1539#endif
9603b61d 1540 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1541 mlx5_unregister_debugfs();
1542}
1543
1544module_init(init);
1545module_exit(cleanup);
Linux 6.x block layer and io_uring tree(s)