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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
b775516b | 49 | #include <linux/mlx5/mlx5_ifc.h> |
c85023e1 | 50 | #include <linux/mlx5/vport.h> |
5a7b27eb MG |
51 | #ifdef CONFIG_RFS_ACCEL |
52 | #include <linux/cpu_rmap.h> | |
53 | #endif | |
feae9087 | 54 | #include <net/devlink.h> |
e126ba97 | 55 | #include "mlx5_core.h" |
86d722ad | 56 | #include "fs_core.h" |
eeb66cdb | 57 | #include "lib/mpfs.h" |
073bb189 | 58 | #include "eswitch.h" |
52ec462e | 59 | #include "lib/mlx5.h" |
e29341fb | 60 | #include "fpga/core.h" |
bebb23e6 | 61 | #include "accel/ipsec.h" |
e126ba97 | 62 | |
e126ba97 | 63 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 64 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
65 | MODULE_LICENSE("Dual BSD/GPL"); |
66 | MODULE_VERSION(DRIVER_VERSION); | |
67 | ||
f663ad98 KH |
68 | unsigned int mlx5_core_debug_mask; |
69 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
70 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
71 | ||
9603b61d | 72 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
73 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
74 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
75 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
76 | ||
f91e6d89 EBE |
77 | enum { |
78 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
79 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
80 | }; | |
81 | ||
9603b61d JM |
82 | static struct mlx5_profile profile[] = { |
83 | [0] = { | |
84 | .mask = 0, | |
85 | }, | |
86 | [1] = { | |
87 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
88 | .log_max_qp = 12, | |
89 | }, | |
90 | [2] = { | |
91 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
92 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 93 | .log_max_qp = 18, |
9603b61d JM |
94 | .mr_cache[0] = { |
95 | .size = 500, | |
96 | .limit = 250 | |
97 | }, | |
98 | .mr_cache[1] = { | |
99 | .size = 500, | |
100 | .limit = 250 | |
101 | }, | |
102 | .mr_cache[2] = { | |
103 | .size = 500, | |
104 | .limit = 250 | |
105 | }, | |
106 | .mr_cache[3] = { | |
107 | .size = 500, | |
108 | .limit = 250 | |
109 | }, | |
110 | .mr_cache[4] = { | |
111 | .size = 500, | |
112 | .limit = 250 | |
113 | }, | |
114 | .mr_cache[5] = { | |
115 | .size = 500, | |
116 | .limit = 250 | |
117 | }, | |
118 | .mr_cache[6] = { | |
119 | .size = 500, | |
120 | .limit = 250 | |
121 | }, | |
122 | .mr_cache[7] = { | |
123 | .size = 500, | |
124 | .limit = 250 | |
125 | }, | |
126 | .mr_cache[8] = { | |
127 | .size = 500, | |
128 | .limit = 250 | |
129 | }, | |
130 | .mr_cache[9] = { | |
131 | .size = 500, | |
132 | .limit = 250 | |
133 | }, | |
134 | .mr_cache[10] = { | |
135 | .size = 500, | |
136 | .limit = 250 | |
137 | }, | |
138 | .mr_cache[11] = { | |
139 | .size = 500, | |
140 | .limit = 250 | |
141 | }, | |
142 | .mr_cache[12] = { | |
143 | .size = 64, | |
144 | .limit = 32 | |
145 | }, | |
146 | .mr_cache[13] = { | |
147 | .size = 32, | |
148 | .limit = 16 | |
149 | }, | |
150 | .mr_cache[14] = { | |
151 | .size = 16, | |
152 | .limit = 8 | |
153 | }, | |
154 | .mr_cache[15] = { | |
155 | .size = 8, | |
156 | .limit = 4 | |
157 | }, | |
7d0cc6ed AK |
158 | .mr_cache[16] = { |
159 | .size = 8, | |
160 | .limit = 4 | |
161 | }, | |
162 | .mr_cache[17] = { | |
163 | .size = 8, | |
164 | .limit = 4 | |
165 | }, | |
166 | .mr_cache[18] = { | |
167 | .size = 8, | |
168 | .limit = 4 | |
169 | }, | |
170 | .mr_cache[19] = { | |
171 | .size = 4, | |
172 | .limit = 2 | |
173 | }, | |
174 | .mr_cache[20] = { | |
175 | .size = 4, | |
176 | .limit = 2 | |
177 | }, | |
9603b61d JM |
178 | }, |
179 | }; | |
e126ba97 | 180 | |
6c780a02 EC |
181 | #define FW_INIT_TIMEOUT_MILI 2000 |
182 | #define FW_INIT_WAIT_MS 2 | |
183 | #define FW_PRE_INIT_TIMEOUT_MILI 10000 | |
e3297246 EC |
184 | |
185 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
186 | { | |
187 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
188 | int err = 0; | |
189 | ||
190 | while (fw_initializing(dev)) { | |
191 | if (time_after(jiffies, end)) { | |
192 | err = -EBUSY; | |
193 | break; | |
194 | } | |
195 | msleep(FW_INIT_WAIT_MS); | |
196 | } | |
197 | ||
198 | return err; | |
199 | } | |
200 | ||
012e50e1 HN |
201 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
202 | { | |
203 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
204 | driver_version); | |
205 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; | |
206 | u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; | |
207 | int remaining_size = driver_ver_sz; | |
208 | char *string; | |
209 | ||
210 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
211 | return; | |
212 | ||
213 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
214 | ||
215 | strncpy(string, "Linux", remaining_size); | |
216 | ||
217 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
218 | strncat(string, ",", remaining_size); | |
219 | ||
220 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
221 | strncat(string, DRIVER_NAME, remaining_size); | |
222 | ||
223 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
224 | strncat(string, ",", remaining_size); | |
225 | ||
226 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
227 | strncat(string, DRIVER_VERSION, remaining_size); | |
228 | ||
229 | /*Send the command*/ | |
230 | MLX5_SET(set_driver_version_in, in, opcode, | |
231 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
232 | ||
233 | mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
234 | } | |
235 | ||
e126ba97 EC |
236 | static int set_dma_caps(struct pci_dev *pdev) |
237 | { | |
238 | int err; | |
239 | ||
240 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
241 | if (err) { | |
1a91de28 | 242 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
243 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
244 | if (err) { | |
1a91de28 | 245 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
246 | return err; |
247 | } | |
248 | } | |
249 | ||
250 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
251 | if (err) { | |
252 | dev_warn(&pdev->dev, | |
1a91de28 | 253 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
254 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
255 | if (err) { | |
256 | dev_err(&pdev->dev, | |
1a91de28 | 257 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
258 | return err; |
259 | } | |
260 | } | |
261 | ||
262 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
263 | return err; | |
264 | } | |
265 | ||
89d44f0a MD |
266 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
267 | { | |
268 | struct pci_dev *pdev = dev->pdev; | |
269 | int err = 0; | |
270 | ||
271 | mutex_lock(&dev->pci_status_mutex); | |
272 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
273 | err = pci_enable_device(pdev); | |
274 | if (!err) | |
275 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
276 | } | |
277 | mutex_unlock(&dev->pci_status_mutex); | |
278 | ||
279 | return err; | |
280 | } | |
281 | ||
282 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
283 | { | |
284 | struct pci_dev *pdev = dev->pdev; | |
285 | ||
286 | mutex_lock(&dev->pci_status_mutex); | |
287 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
288 | pci_disable_device(pdev); | |
289 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
290 | } | |
291 | mutex_unlock(&dev->pci_status_mutex); | |
292 | } | |
293 | ||
e126ba97 EC |
294 | static int request_bar(struct pci_dev *pdev) |
295 | { | |
296 | int err = 0; | |
297 | ||
298 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 299 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
300 | return -ENODEV; |
301 | } | |
302 | ||
303 | err = pci_request_regions(pdev, DRIVER_NAME); | |
304 | if (err) | |
305 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
306 | ||
307 | return err; | |
308 | } | |
309 | ||
310 | static void release_bar(struct pci_dev *pdev) | |
311 | { | |
312 | pci_release_regions(pdev); | |
313 | } | |
314 | ||
78249c42 | 315 | static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev) |
e126ba97 | 316 | { |
db058a18 SM |
317 | struct mlx5_priv *priv = &dev->priv; |
318 | struct mlx5_eq_table *table = &priv->eq_table; | |
a435393a SG |
319 | struct irq_affinity irqdesc = { |
320 | .pre_vectors = MLX5_EQ_VEC_COMP_BASE, | |
321 | }; | |
938fe83c | 322 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 323 | int nvec; |
e126ba97 | 324 | |
938fe83c SM |
325 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
326 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
327 | nvec = min_t(int, nvec, num_eqs); |
328 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
329 | return -ENOMEM; | |
330 | ||
db058a18 | 331 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); |
78249c42 | 332 | if (!priv->irq_info) |
db058a18 | 333 | goto err_free_msix; |
e126ba97 | 334 | |
a435393a | 335 | nvec = pci_alloc_irq_vectors_affinity(dev->pdev, |
78249c42 | 336 | MLX5_EQ_VEC_COMP_BASE + 1, nvec, |
a435393a SG |
337 | PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, |
338 | &irqdesc); | |
f3c9407b AG |
339 | if (nvec < 0) |
340 | return nvec; | |
e126ba97 | 341 | |
f3c9407b | 342 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
343 | |
344 | return 0; | |
db058a18 SM |
345 | |
346 | err_free_msix: | |
347 | kfree(priv->irq_info); | |
db058a18 | 348 | return -ENOMEM; |
e126ba97 EC |
349 | } |
350 | ||
78249c42 | 351 | static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev) |
e126ba97 | 352 | { |
db058a18 | 353 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 | 354 | |
78249c42 | 355 | pci_free_irq_vectors(dev->pdev); |
db058a18 | 356 | kfree(priv->irq_info); |
e126ba97 EC |
357 | } |
358 | ||
bd10838a | 359 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
360 | u8 he; |
361 | u8 rsvd[15]; | |
362 | }; | |
363 | ||
87b8de49 EC |
364 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
365 | ||
366 | enum { | |
c7a08ac7 EC |
367 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
368 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
369 | }; |
370 | ||
2974ab6e | 371 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
372 | { |
373 | switch (size) { | |
374 | case 128: | |
375 | return 0; | |
376 | case 256: | |
377 | return 1; | |
378 | case 512: | |
379 | return 2; | |
380 | case 1024: | |
381 | return 3; | |
382 | case 2048: | |
383 | return 4; | |
384 | case 4096: | |
385 | return 5; | |
386 | default: | |
2974ab6e | 387 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
388 | return 0; |
389 | } | |
390 | } | |
391 | ||
b06e7de8 LR |
392 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
393 | enum mlx5_cap_type cap_type, | |
394 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 395 | { |
b775516b EC |
396 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
397 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
398 | void *out, *hca_caps; |
399 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
400 | int err; |
401 | ||
b775516b EC |
402 | memset(in, 0, sizeof(in)); |
403 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 404 | if (!out) |
e126ba97 | 405 | return -ENOMEM; |
938fe83c | 406 | |
b775516b EC |
407 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
408 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
409 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 410 | if (err) { |
938fe83c SM |
411 | mlx5_core_warn(dev, |
412 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
413 | cap_type, cap_mode, err); | |
e126ba97 EC |
414 | goto query_ex; |
415 | } | |
c7a08ac7 | 416 | |
938fe83c SM |
417 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
418 | ||
419 | switch (cap_mode) { | |
420 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 421 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
422 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
423 | break; | |
424 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 425 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
426 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
427 | break; | |
428 | default: | |
429 | mlx5_core_warn(dev, | |
430 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
431 | cap_type, cap_mode); | |
432 | err = -EINVAL; | |
433 | break; | |
434 | } | |
c7a08ac7 EC |
435 | query_ex: |
436 | kfree(out); | |
437 | return err; | |
438 | } | |
439 | ||
b06e7de8 LR |
440 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
441 | { | |
442 | int ret; | |
443 | ||
444 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
445 | if (ret) | |
446 | return ret; | |
447 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
448 | } | |
449 | ||
f91e6d89 | 450 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 451 | { |
c4f287c4 | 452 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 453 | |
b775516b | 454 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 455 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 456 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
457 | } |
458 | ||
f91e6d89 EBE |
459 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
460 | { | |
461 | void *set_ctx; | |
462 | void *set_hca_cap; | |
463 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
464 | int req_endianness; | |
465 | int err; | |
466 | ||
467 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 468 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
469 | if (err) |
470 | return err; | |
471 | } else { | |
472 | return 0; | |
473 | } | |
474 | ||
475 | req_endianness = | |
476 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 477 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
478 | |
479 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
480 | return 0; | |
481 | ||
482 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
483 | if (!set_ctx) | |
484 | return -ENOMEM; | |
485 | ||
486 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
487 | ||
488 | /* Set requestor to host endianness */ | |
bd10838a | 489 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
490 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
491 | ||
492 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
493 | ||
494 | kfree(set_ctx); | |
495 | return err; | |
496 | } | |
497 | ||
c7a08ac7 EC |
498 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
499 | { | |
b775516b | 500 | void *set_ctx = NULL; |
c7a08ac7 | 501 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 502 | int err = -ENOMEM; |
b775516b | 503 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 504 | void *set_hca_cap; |
c7a08ac7 | 505 | |
b775516b | 506 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 507 | if (!set_ctx) |
e126ba97 | 508 | goto query_ex; |
e126ba97 | 509 | |
b06e7de8 | 510 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
511 | if (err) |
512 | goto query_ex; | |
513 | ||
938fe83c SM |
514 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
515 | capability); | |
701052c5 | 516 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
517 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
518 | ||
519 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 520 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 521 | 128); |
c7a08ac7 | 522 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 523 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 524 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 525 | |
883371c4 NO |
526 | /* Check log_max_qp from HCA caps to set in current profile */ |
527 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
528 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
529 | profile[prof_sel].log_max_qp, | |
530 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
531 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
532 | } | |
c7a08ac7 | 533 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
534 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
535 | prof->log_max_qp); | |
c7a08ac7 | 536 | |
938fe83c SM |
537 | /* disable cmdif checksum */ |
538 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 539 | |
91828bd8 MD |
540 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
541 | * than 4K. | |
542 | */ | |
543 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
544 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
545 | ||
fe1e1876 CS |
546 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
547 | ||
f32f5bd2 DJ |
548 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
549 | MLX5_SET(cmd_hca_cap, | |
550 | set_hca_cap, | |
551 | cache_line_128byte, | |
552 | cache_line_size() == 128 ? 1 : 0); | |
553 | ||
f91e6d89 EBE |
554 | err = set_caps(dev, set_ctx, set_sz, |
555 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 556 | |
e126ba97 | 557 | query_ex: |
e126ba97 | 558 | kfree(set_ctx); |
e126ba97 EC |
559 | return err; |
560 | } | |
561 | ||
562 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
563 | { | |
bd10838a OG |
564 | struct mlx5_reg_host_endianness he_in; |
565 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
566 | int err; |
567 | ||
fc50db98 EC |
568 | if (!mlx5_core_is_pf(dev)) |
569 | return 0; | |
570 | ||
e126ba97 EC |
571 | memset(&he_in, 0, sizeof(he_in)); |
572 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
573 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
574 | &he_out, sizeof(he_out), | |
575 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
576 | return err; | |
577 | } | |
578 | ||
c85023e1 HN |
579 | static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) |
580 | { | |
581 | int ret = 0; | |
582 | ||
583 | /* Disable local_lb by default */ | |
584 | if ((MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && | |
585 | MLX5_CAP_GEN(dev, disable_local_lb)) | |
586 | ret = mlx5_nic_vport_update_local_lb(dev, false); | |
587 | ||
588 | return ret; | |
589 | } | |
590 | ||
0b107106 | 591 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 592 | { |
c4f287c4 SM |
593 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
594 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 595 | |
0b107106 EC |
596 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
597 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
c4f287c4 | 598 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
599 | } |
600 | ||
0b107106 | 601 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 602 | { |
c4f287c4 SM |
603 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
604 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 605 | |
0b107106 EC |
606 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
607 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
c4f287c4 | 608 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
609 | } |
610 | ||
a5a1d1c2 | 611 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
b0844444 EBE |
612 | { |
613 | u32 timer_h, timer_h1, timer_l; | |
614 | ||
615 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
616 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
617 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
618 | if (timer_h != timer_h1) /* wrap around */ | |
619 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
620 | ||
a5a1d1c2 | 621 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
622 | } |
623 | ||
0b6e26ce DT |
624 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
625 | unsigned int *irqn) | |
233d05d2 SM |
626 | { |
627 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
628 | struct mlx5_eq *eq, *n; | |
629 | int err = -ENOENT; | |
630 | ||
631 | spin_lock(&table->lock); | |
632 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
633 | if (eq->index == vector) { | |
634 | *eqn = eq->eqn; | |
635 | *irqn = eq->irqn; | |
636 | err = 0; | |
637 | break; | |
638 | } | |
639 | } | |
640 | spin_unlock(&table->lock); | |
641 | ||
642 | return err; | |
643 | } | |
644 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
645 | ||
94c6825e MB |
646 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
647 | { | |
648 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
649 | struct mlx5_eq *eq; | |
650 | ||
651 | spin_lock(&table->lock); | |
652 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
653 | if (eq->eqn == eqn) { | |
654 | spin_unlock(&table->lock); | |
655 | return eq; | |
656 | } | |
657 | ||
658 | spin_unlock(&table->lock); | |
659 | ||
660 | return ERR_PTR(-ENOENT); | |
661 | } | |
662 | ||
233d05d2 SM |
663 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
664 | { | |
665 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
666 | struct mlx5_eq *eq, *n; | |
667 | ||
5a7b27eb MG |
668 | #ifdef CONFIG_RFS_ACCEL |
669 | if (dev->rmap) { | |
670 | free_irq_cpu_rmap(dev->rmap); | |
671 | dev->rmap = NULL; | |
672 | } | |
673 | #endif | |
233d05d2 SM |
674 | spin_lock(&table->lock); |
675 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
676 | list_del(&eq->list); | |
677 | spin_unlock(&table->lock); | |
678 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
679 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
680 | eq->eqn); | |
681 | kfree(eq); | |
682 | spin_lock(&table->lock); | |
683 | } | |
684 | spin_unlock(&table->lock); | |
685 | } | |
686 | ||
687 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
688 | { | |
689 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 690 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
691 | struct mlx5_eq *eq; |
692 | int ncomp_vec; | |
693 | int nent; | |
694 | int err; | |
695 | int i; | |
696 | ||
697 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
698 | ncomp_vec = table->num_comp_vectors; | |
699 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
700 | #ifdef CONFIG_RFS_ACCEL |
701 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
702 | if (!dev->rmap) | |
703 | return -ENOMEM; | |
704 | #endif | |
233d05d2 SM |
705 | for (i = 0; i < ncomp_vec; i++) { |
706 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
707 | if (!eq) { | |
708 | err = -ENOMEM; | |
709 | goto clean; | |
710 | } | |
711 | ||
5a7b27eb | 712 | #ifdef CONFIG_RFS_ACCEL |
78249c42 SG |
713 | irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev, |
714 | MLX5_EQ_VEC_COMP_BASE + i)); | |
5a7b27eb | 715 | #endif |
db058a18 | 716 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
717 | err = mlx5_create_map_eq(dev, eq, |
718 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
01187175 | 719 | name, MLX5_EQ_TYPE_COMP); |
233d05d2 SM |
720 | if (err) { |
721 | kfree(eq); | |
722 | goto clean; | |
723 | } | |
724 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
725 | eq->index = i; | |
726 | spin_lock(&table->lock); | |
727 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
728 | spin_unlock(&table->lock); | |
729 | } | |
730 | ||
731 | return 0; | |
732 | ||
733 | clean: | |
734 | free_comp_eqs(dev); | |
735 | return err; | |
736 | } | |
737 | ||
f62b8bb8 AV |
738 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
739 | { | |
c4f287c4 SM |
740 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
741 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 742 | u32 sup_issi; |
c4f287c4 | 743 | int err; |
f62b8bb8 AV |
744 | |
745 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
746 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
747 | query_out, sizeof(query_out)); | |
f62b8bb8 | 748 | if (err) { |
c4f287c4 SM |
749 | u32 syndrome; |
750 | u8 status; | |
751 | ||
752 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
753 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
754 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
755 | err, status, syndrome); | |
756 | return err; | |
f62b8bb8 AV |
757 | } |
758 | ||
f9c14e46 KH |
759 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
760 | dev->issi = 0; | |
761 | return 0; | |
f62b8bb8 AV |
762 | } |
763 | ||
764 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
765 | ||
766 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
767 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
768 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
769 | |
770 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
771 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
772 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
773 | set_out, sizeof(set_out)); | |
f62b8bb8 | 774 | if (err) { |
f9c14e46 KH |
775 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
776 | err); | |
f62b8bb8 AV |
777 | return err; |
778 | } | |
779 | ||
780 | dev->issi = 1; | |
781 | ||
782 | return 0; | |
e74a1db0 | 783 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
784 | return 0; |
785 | } | |
786 | ||
9eb78923 | 787 | return -EOPNOTSUPP; |
f62b8bb8 | 788 | } |
f62b8bb8 | 789 | |
a31208b1 MD |
790 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
791 | { | |
792 | struct pci_dev *pdev = dev->pdev; | |
793 | int err = 0; | |
e126ba97 | 794 | |
e126ba97 EC |
795 | pci_set_drvdata(dev->pdev, dev); |
796 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
797 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
798 | ||
799 | mutex_init(&priv->pgdir_mutex); | |
800 | INIT_LIST_HEAD(&priv->pgdir_list); | |
801 | spin_lock_init(&priv->mkey_lock); | |
802 | ||
311c7c71 SM |
803 | mutex_init(&priv->alloc_mutex); |
804 | ||
805 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
806 | ||
e126ba97 EC |
807 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
808 | if (!priv->dbg_root) | |
809 | return -ENOMEM; | |
810 | ||
89d44f0a | 811 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 812 | if (err) { |
1a91de28 | 813 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
814 | goto err_dbg; |
815 | } | |
816 | ||
817 | err = request_bar(pdev); | |
818 | if (err) { | |
1a91de28 | 819 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
820 | goto err_disable; |
821 | } | |
822 | ||
823 | pci_set_master(pdev); | |
824 | ||
825 | err = set_dma_caps(pdev); | |
826 | if (err) { | |
827 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
828 | goto err_clr_master; | |
829 | } | |
830 | ||
831 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
832 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
833 | if (!dev->iseg) { | |
834 | err = -ENOMEM; | |
835 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
836 | goto err_clr_master; | |
837 | } | |
a31208b1 MD |
838 | |
839 | return 0; | |
840 | ||
841 | err_clr_master: | |
842 | pci_clear_master(dev->pdev); | |
843 | release_bar(dev->pdev); | |
844 | err_disable: | |
89d44f0a | 845 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
846 | |
847 | err_dbg: | |
848 | debugfs_remove(priv->dbg_root); | |
849 | return err; | |
850 | } | |
851 | ||
852 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
853 | { | |
854 | iounmap(dev->iseg); | |
855 | pci_clear_master(dev->pdev); | |
856 | release_bar(dev->pdev); | |
89d44f0a | 857 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
858 | debugfs_remove(priv->dbg_root); |
859 | } | |
860 | ||
59211bd3 MHY |
861 | static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
862 | { | |
863 | struct pci_dev *pdev = dev->pdev; | |
864 | int err; | |
865 | ||
59211bd3 MHY |
866 | err = mlx5_query_board_id(dev); |
867 | if (err) { | |
868 | dev_err(&pdev->dev, "query board id failed\n"); | |
869 | goto out; | |
870 | } | |
871 | ||
872 | err = mlx5_eq_init(dev); | |
873 | if (err) { | |
874 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
875 | goto out; | |
876 | } | |
877 | ||
59211bd3 MHY |
878 | err = mlx5_init_cq_table(dev); |
879 | if (err) { | |
880 | dev_err(&pdev->dev, "failed to initialize cq table\n"); | |
881 | goto err_eq_cleanup; | |
882 | } | |
883 | ||
884 | mlx5_init_qp_table(dev); | |
885 | ||
886 | mlx5_init_srq_table(dev); | |
887 | ||
888 | mlx5_init_mkey_table(dev); | |
889 | ||
52ec462e IT |
890 | mlx5_init_reserved_gids(dev); |
891 | ||
59211bd3 MHY |
892 | err = mlx5_init_rl_table(dev); |
893 | if (err) { | |
894 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
895 | goto err_tables_cleanup; | |
896 | } | |
897 | ||
eeb66cdb SM |
898 | err = mlx5_mpfs_init(dev); |
899 | if (err) { | |
900 | dev_err(&pdev->dev, "Failed to init l2 table %d\n", err); | |
901 | goto err_rl_cleanup; | |
902 | } | |
903 | ||
c2d6e31a MHY |
904 | err = mlx5_eswitch_init(dev); |
905 | if (err) { | |
906 | dev_err(&pdev->dev, "Failed to init eswitch %d\n", err); | |
eeb66cdb | 907 | goto err_mpfs_cleanup; |
c2d6e31a | 908 | } |
c2d6e31a MHY |
909 | |
910 | err = mlx5_sriov_init(dev); | |
911 | if (err) { | |
912 | dev_err(&pdev->dev, "Failed to init sriov %d\n", err); | |
913 | goto err_eswitch_cleanup; | |
914 | } | |
915 | ||
9410733c IT |
916 | err = mlx5_fpga_init(dev); |
917 | if (err) { | |
918 | dev_err(&pdev->dev, "Failed to init fpga device %d\n", err); | |
919 | goto err_sriov_cleanup; | |
920 | } | |
921 | ||
59211bd3 MHY |
922 | return 0; |
923 | ||
9410733c IT |
924 | err_sriov_cleanup: |
925 | mlx5_sriov_cleanup(dev); | |
c2d6e31a | 926 | err_eswitch_cleanup: |
c2d6e31a | 927 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
eeb66cdb | 928 | err_mpfs_cleanup: |
eeb66cdb | 929 | mlx5_mpfs_cleanup(dev); |
c2d6e31a | 930 | err_rl_cleanup: |
c2d6e31a | 931 | mlx5_cleanup_rl_table(dev); |
59211bd3 MHY |
932 | err_tables_cleanup: |
933 | mlx5_cleanup_mkey_table(dev); | |
934 | mlx5_cleanup_srq_table(dev); | |
935 | mlx5_cleanup_qp_table(dev); | |
936 | mlx5_cleanup_cq_table(dev); | |
937 | ||
938 | err_eq_cleanup: | |
939 | mlx5_eq_cleanup(dev); | |
940 | ||
941 | out: | |
942 | return err; | |
943 | } | |
944 | ||
945 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
946 | { | |
9410733c | 947 | mlx5_fpga_cleanup(dev); |
c2d6e31a | 948 | mlx5_sriov_cleanup(dev); |
c2d6e31a | 949 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
eeb66cdb | 950 | mlx5_mpfs_cleanup(dev); |
59211bd3 | 951 | mlx5_cleanup_rl_table(dev); |
52ec462e | 952 | mlx5_cleanup_reserved_gids(dev); |
59211bd3 MHY |
953 | mlx5_cleanup_mkey_table(dev); |
954 | mlx5_cleanup_srq_table(dev); | |
955 | mlx5_cleanup_qp_table(dev); | |
956 | mlx5_cleanup_cq_table(dev); | |
957 | mlx5_eq_cleanup(dev); | |
958 | } | |
959 | ||
960 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |
961 | bool boot) | |
a31208b1 MD |
962 | { |
963 | struct pci_dev *pdev = dev->pdev; | |
964 | int err; | |
965 | ||
89d44f0a | 966 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 967 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
968 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
969 | __func__); | |
970 | goto out; | |
971 | } | |
972 | ||
e126ba97 EC |
973 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
974 | fw_rev_min(dev), fw_rev_sub(dev)); | |
975 | ||
89d44f0a MD |
976 | /* on load removing any previous indication of internal error, device is |
977 | * up | |
978 | */ | |
979 | dev->state = MLX5_DEVICE_STATE_UP; | |
980 | ||
6c780a02 EC |
981 | /* wait for firmware to accept initialization segments configurations |
982 | */ | |
983 | err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI); | |
984 | if (err) { | |
985 | dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n", | |
986 | FW_PRE_INIT_TIMEOUT_MILI); | |
8ce59b16 | 987 | goto out_err; |
6c780a02 EC |
988 | } |
989 | ||
e126ba97 EC |
990 | err = mlx5_cmd_init(dev); |
991 | if (err) { | |
992 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 993 | goto out_err; |
e126ba97 EC |
994 | } |
995 | ||
e3297246 EC |
996 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
997 | if (err) { | |
998 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
999 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 1000 | goto err_cmd_cleanup; |
e3297246 EC |
1001 | } |
1002 | ||
0b107106 | 1003 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
1004 | if (err) { |
1005 | dev_err(&pdev->dev, "enable hca failed\n"); | |
59211bd3 | 1006 | goto err_cmd_cleanup; |
cd23b14b EC |
1007 | } |
1008 | ||
f62b8bb8 AV |
1009 | err = mlx5_core_set_issi(dev); |
1010 | if (err) { | |
1011 | dev_err(&pdev->dev, "failed to set issi\n"); | |
1012 | goto err_disable_hca; | |
1013 | } | |
f62b8bb8 | 1014 | |
cd23b14b EC |
1015 | err = mlx5_satisfy_startup_pages(dev, 1); |
1016 | if (err) { | |
1017 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
1018 | goto err_disable_hca; | |
1019 | } | |
1020 | ||
e126ba97 EC |
1021 | err = set_hca_ctrl(dev); |
1022 | if (err) { | |
1023 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 1024 | goto reclaim_boot_pages; |
e126ba97 EC |
1025 | } |
1026 | ||
1027 | err = handle_hca_cap(dev); | |
1028 | if (err) { | |
1029 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 1030 | goto reclaim_boot_pages; |
e126ba97 EC |
1031 | } |
1032 | ||
f91e6d89 EBE |
1033 | err = handle_hca_cap_atomic(dev); |
1034 | if (err) { | |
1035 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
1036 | goto reclaim_boot_pages; | |
e126ba97 EC |
1037 | } |
1038 | ||
cd23b14b | 1039 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1040 | if (err) { |
cd23b14b EC |
1041 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1042 | goto reclaim_boot_pages; | |
e126ba97 EC |
1043 | } |
1044 | ||
1045 | err = mlx5_pagealloc_start(dev); | |
1046 | if (err) { | |
1047 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1048 | goto reclaim_boot_pages; |
e126ba97 EC |
1049 | } |
1050 | ||
1051 | err = mlx5_cmd_init_hca(dev); | |
1052 | if (err) { | |
1053 | dev_err(&pdev->dev, "init hca failed\n"); | |
1054 | goto err_pagealloc_stop; | |
1055 | } | |
1056 | ||
012e50e1 HN |
1057 | mlx5_set_driver_version(dev); |
1058 | ||
e126ba97 EC |
1059 | mlx5_start_health_poll(dev); |
1060 | ||
bba1574c DJ |
1061 | err = mlx5_query_hca_caps(dev); |
1062 | if (err) { | |
1063 | dev_err(&pdev->dev, "query hca failed\n"); | |
1064 | goto err_stop_poll; | |
1065 | } | |
1066 | ||
59211bd3 MHY |
1067 | if (boot && mlx5_init_once(dev, priv)) { |
1068 | dev_err(&pdev->dev, "sw objs init failed\n"); | |
e126ba97 EC |
1069 | goto err_stop_poll; |
1070 | } | |
1071 | ||
78249c42 | 1072 | err = mlx5_alloc_irq_vectors(dev); |
e126ba97 | 1073 | if (err) { |
78249c42 | 1074 | dev_err(&pdev->dev, "alloc irq vectors failed\n"); |
59211bd3 | 1075 | goto err_cleanup_once; |
e126ba97 EC |
1076 | } |
1077 | ||
01187175 EC |
1078 | dev->priv.uar = mlx5_get_uars_page(dev); |
1079 | if (!dev->priv.uar) { | |
e126ba97 | 1080 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); |
59211bd3 | 1081 | goto err_disable_msix; |
e126ba97 EC |
1082 | } |
1083 | ||
1084 | err = mlx5_start_eqs(dev); | |
1085 | if (err) { | |
1086 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
9410733c | 1087 | goto err_put_uars; |
e126ba97 EC |
1088 | } |
1089 | ||
233d05d2 SM |
1090 | err = alloc_comp_eqs(dev); |
1091 | if (err) { | |
1092 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1093 | goto err_stop_eqs; | |
1094 | } | |
1095 | ||
86d722ad | 1096 | err = mlx5_init_fs(dev); |
59211bd3 | 1097 | if (err) { |
86d722ad | 1098 | dev_err(&pdev->dev, "Failed to init flow steering\n"); |
c85023e1 | 1099 | goto err_fs; |
59211bd3 | 1100 | } |
e126ba97 | 1101 | |
c85023e1 | 1102 | err = mlx5_core_set_hca_defaults(dev); |
86d722ad | 1103 | if (err) { |
c85023e1 | 1104 | dev_err(&pdev->dev, "Failed to set hca defaults\n"); |
86d722ad MG |
1105 | goto err_fs; |
1106 | } | |
1466cc5b | 1107 | |
c2d6e31a | 1108 | err = mlx5_sriov_attach(dev); |
fc50db98 EC |
1109 | if (err) { |
1110 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1111 | goto err_sriov; | |
1112 | } | |
1113 | ||
e29341fb IT |
1114 | err = mlx5_fpga_device_start(dev); |
1115 | if (err) { | |
1116 | dev_err(&pdev->dev, "fpga device start failed %d\n", err); | |
52ec462e | 1117 | goto err_fpga_start; |
e29341fb | 1118 | } |
bebb23e6 IT |
1119 | err = mlx5_accel_ipsec_init(dev); |
1120 | if (err) { | |
1121 | dev_err(&pdev->dev, "IPSec device start failed %d\n", err); | |
1122 | goto err_ipsec_start; | |
1123 | } | |
e29341fb | 1124 | |
737a234b MHY |
1125 | if (mlx5_device_registered(dev)) { |
1126 | mlx5_attach_device(dev); | |
1127 | } else { | |
1128 | err = mlx5_register_device(dev); | |
1129 | if (err) { | |
1130 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1131 | goto err_reg_dev; | |
1132 | } | |
a31208b1 MD |
1133 | } |
1134 | ||
5fc7197d | 1135 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
89d44f0a MD |
1136 | out: |
1137 | mutex_unlock(&dev->intf_state_mutex); | |
1138 | ||
e126ba97 EC |
1139 | return 0; |
1140 | ||
59211bd3 | 1141 | err_reg_dev: |
bebb23e6 IT |
1142 | mlx5_accel_ipsec_cleanup(dev); |
1143 | err_ipsec_start: | |
52ec462e IT |
1144 | mlx5_fpga_device_stop(dev); |
1145 | ||
1146 | err_fpga_start: | |
c2d6e31a | 1147 | mlx5_sriov_detach(dev); |
fc50db98 | 1148 | |
59211bd3 | 1149 | err_sriov: |
86d722ad | 1150 | mlx5_cleanup_fs(dev); |
59211bd3 | 1151 | |
86d722ad | 1152 | err_fs: |
db058a18 SM |
1153 | free_comp_eqs(dev); |
1154 | ||
233d05d2 SM |
1155 | err_stop_eqs: |
1156 | mlx5_stop_eqs(dev); | |
1157 | ||
5fe9dec0 | 1158 | err_put_uars: |
01187175 | 1159 | mlx5_put_uars_page(dev, priv->uar); |
e126ba97 | 1160 | |
59211bd3 | 1161 | err_disable_msix: |
78249c42 | 1162 | mlx5_free_irq_vectors(dev); |
e126ba97 | 1163 | |
59211bd3 MHY |
1164 | err_cleanup_once: |
1165 | if (boot) | |
1166 | mlx5_cleanup_once(dev); | |
1167 | ||
e126ba97 EC |
1168 | err_stop_poll: |
1169 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1170 | if (mlx5_cmd_teardown_hca(dev)) { |
1171 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1172 | goto out_err; |
1bde6e30 | 1173 | } |
e126ba97 EC |
1174 | |
1175 | err_pagealloc_stop: | |
1176 | mlx5_pagealloc_stop(dev); | |
1177 | ||
cd23b14b | 1178 | reclaim_boot_pages: |
e126ba97 EC |
1179 | mlx5_reclaim_startup_pages(dev); |
1180 | ||
cd23b14b | 1181 | err_disable_hca: |
0b107106 | 1182 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1183 | |
59211bd3 | 1184 | err_cmd_cleanup: |
e126ba97 EC |
1185 | mlx5_cmd_cleanup(dev); |
1186 | ||
89d44f0a MD |
1187 | out_err: |
1188 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1189 | mutex_unlock(&dev->intf_state_mutex); | |
1190 | ||
e126ba97 EC |
1191 | return err; |
1192 | } | |
e126ba97 | 1193 | |
59211bd3 MHY |
1194 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, |
1195 | bool cleanup) | |
e126ba97 | 1196 | { |
89d44f0a | 1197 | int err = 0; |
e126ba97 | 1198 | |
5e44fca5 | 1199 | if (cleanup) |
2a0165a0 | 1200 | mlx5_drain_health_recovery(dev); |
689a248d | 1201 | |
89d44f0a | 1202 | mutex_lock(&dev->intf_state_mutex); |
b3cb5388 | 1203 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
1204 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1205 | __func__); | |
59211bd3 MHY |
1206 | if (cleanup) |
1207 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1208 | goto out; |
1209 | } | |
6b6adee3 | 1210 | |
9ade8c7c | 1211 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
9ade8c7c | 1212 | |
737a234b MHY |
1213 | if (mlx5_device_registered(dev)) |
1214 | mlx5_detach_device(dev); | |
1215 | ||
bebb23e6 | 1216 | mlx5_accel_ipsec_cleanup(dev); |
52ec462e IT |
1217 | mlx5_fpga_device_stop(dev); |
1218 | ||
c2d6e31a | 1219 | mlx5_sriov_detach(dev); |
86d722ad | 1220 | mlx5_cleanup_fs(dev); |
233d05d2 | 1221 | free_comp_eqs(dev); |
e126ba97 | 1222 | mlx5_stop_eqs(dev); |
01187175 | 1223 | mlx5_put_uars_page(dev, priv->uar); |
78249c42 | 1224 | mlx5_free_irq_vectors(dev); |
59211bd3 MHY |
1225 | if (cleanup) |
1226 | mlx5_cleanup_once(dev); | |
e126ba97 | 1227 | mlx5_stop_health_poll(dev); |
ac6ea6e8 EC |
1228 | err = mlx5_cmd_teardown_hca(dev); |
1229 | if (err) { | |
1bde6e30 | 1230 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1231 | goto out; |
1bde6e30 | 1232 | } |
e126ba97 EC |
1233 | mlx5_pagealloc_stop(dev); |
1234 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1235 | mlx5_core_disable_hca(dev, 0); |
e126ba97 | 1236 | mlx5_cmd_cleanup(dev); |
9603b61d | 1237 | |
ac6ea6e8 | 1238 | out: |
89d44f0a | 1239 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1240 | return err; |
9603b61d | 1241 | } |
64613d94 | 1242 | |
9603b61d JM |
1243 | struct mlx5_core_event_handler { |
1244 | void (*event)(struct mlx5_core_dev *dev, | |
1245 | enum mlx5_dev_event event, | |
1246 | void *data); | |
1247 | }; | |
1248 | ||
feae9087 | 1249 | static const struct devlink_ops mlx5_devlink_ops = { |
e80541ec | 1250 | #ifdef CONFIG_MLX5_ESWITCH |
feae9087 OG |
1251 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, |
1252 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
bffaa916 RD |
1253 | .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, |
1254 | .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, | |
7768d197 RD |
1255 | .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, |
1256 | .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, | |
feae9087 OG |
1257 | #endif |
1258 | }; | |
f66f049f | 1259 | |
59211bd3 | 1260 | #define MLX5_IB_MOD "mlx5_ib" |
9603b61d JM |
1261 | static int init_one(struct pci_dev *pdev, |
1262 | const struct pci_device_id *id) | |
1263 | { | |
1264 | struct mlx5_core_dev *dev; | |
feae9087 | 1265 | struct devlink *devlink; |
9603b61d JM |
1266 | struct mlx5_priv *priv; |
1267 | int err; | |
1268 | ||
feae9087 OG |
1269 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1270 | if (!devlink) { | |
9603b61d JM |
1271 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1272 | return -ENOMEM; | |
1273 | } | |
feae9087 OG |
1274 | |
1275 | dev = devlink_priv(devlink); | |
9603b61d | 1276 | priv = &dev->priv; |
fc50db98 | 1277 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1278 | |
1279 | pci_set_drvdata(pdev, dev); | |
1280 | ||
0e97a340 HN |
1281 | dev->pdev = pdev; |
1282 | dev->event = mlx5_core_event; | |
9603b61d | 1283 | dev->profile = &profile[prof_sel]; |
9603b61d | 1284 | |
364d1798 EC |
1285 | INIT_LIST_HEAD(&priv->ctx_list); |
1286 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1287 | mutex_init(&dev->pci_status_mutex); |
1288 | mutex_init(&dev->intf_state_mutex); | |
d9aaed83 | 1289 | |
97834eba ES |
1290 | INIT_LIST_HEAD(&priv->waiting_events_list); |
1291 | priv->is_accum_events = false; | |
1292 | ||
d9aaed83 AK |
1293 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1294 | err = init_srcu_struct(&priv->pfault_srcu); | |
1295 | if (err) { | |
1296 | dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n", | |
1297 | err); | |
1298 | goto clean_dev; | |
1299 | } | |
1300 | #endif | |
01187175 EC |
1301 | mutex_init(&priv->bfregs.reg_head.lock); |
1302 | mutex_init(&priv->bfregs.wc_head.lock); | |
1303 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1304 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1305 | ||
a31208b1 | 1306 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1307 | if (err) { |
a31208b1 | 1308 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
d9aaed83 | 1309 | goto clean_srcu; |
9603b61d JM |
1310 | } |
1311 | ||
ac6ea6e8 EC |
1312 | err = mlx5_health_init(dev); |
1313 | if (err) { | |
1314 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1315 | goto close_pci; | |
1316 | } | |
1317 | ||
59211bd3 MHY |
1318 | mlx5_pagealloc_init(dev); |
1319 | ||
1320 | err = mlx5_load_one(dev, priv, true); | |
9603b61d | 1321 | if (err) { |
a31208b1 | 1322 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1323 | goto clean_health; |
9603b61d | 1324 | } |
59211bd3 | 1325 | |
f82eed45 | 1326 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1327 | |
feae9087 OG |
1328 | err = devlink_register(devlink, &pdev->dev); |
1329 | if (err) | |
1330 | goto clean_load; | |
1331 | ||
5d47f6c8 | 1332 | pci_save_state(pdev); |
9603b61d JM |
1333 | return 0; |
1334 | ||
feae9087 | 1335 | clean_load: |
59211bd3 | 1336 | mlx5_unload_one(dev, priv, true); |
ac6ea6e8 | 1337 | clean_health: |
59211bd3 | 1338 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1339 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1340 | close_pci: |
1341 | mlx5_pci_close(dev, priv); | |
d9aaed83 AK |
1342 | clean_srcu: |
1343 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1344 | cleanup_srcu_struct(&priv->pfault_srcu); | |
a31208b1 | 1345 | clean_dev: |
d9aaed83 | 1346 | #endif |
feae9087 | 1347 | devlink_free(devlink); |
a31208b1 | 1348 | |
9603b61d JM |
1349 | return err; |
1350 | } | |
a31208b1 | 1351 | |
9603b61d JM |
1352 | static void remove_one(struct pci_dev *pdev) |
1353 | { | |
1354 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1355 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1356 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1357 | |
feae9087 | 1358 | devlink_unregister(devlink); |
737a234b MHY |
1359 | mlx5_unregister_device(dev); |
1360 | ||
59211bd3 | 1361 | if (mlx5_unload_one(dev, priv, true)) { |
a31208b1 | 1362 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); |
ac6ea6e8 | 1363 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1364 | return; |
1365 | } | |
737a234b | 1366 | |
59211bd3 | 1367 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1368 | mlx5_health_cleanup(dev); |
a31208b1 | 1369 | mlx5_pci_close(dev, priv); |
d9aaed83 AK |
1370 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1371 | cleanup_srcu_struct(&priv->pfault_srcu); | |
1372 | #endif | |
feae9087 | 1373 | devlink_free(devlink); |
9603b61d JM |
1374 | } |
1375 | ||
89d44f0a MD |
1376 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1377 | pci_channel_state_t state) | |
1378 | { | |
1379 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1380 | struct mlx5_priv *priv = &dev->priv; | |
1381 | ||
1382 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
04c0c1ab | 1383 | |
8812c24d | 1384 | mlx5_enter_error_state(dev, false); |
59211bd3 | 1385 | mlx5_unload_one(dev, priv, false); |
5d47f6c8 | 1386 | /* In case of kernel call drain the health wq */ |
05ac2c0b | 1387 | if (state) { |
5e44fca5 | 1388 | mlx5_drain_health_wq(dev); |
05ac2c0b MHY |
1389 | mlx5_pci_disable_device(dev); |
1390 | } | |
1391 | ||
89d44f0a MD |
1392 | return state == pci_channel_io_perm_failure ? |
1393 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1394 | } | |
1395 | ||
d57847dc DJ |
1396 | /* wait for the device to show vital signs by waiting |
1397 | * for the health counter to start counting. | |
89d44f0a | 1398 | */ |
d57847dc | 1399 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1400 | { |
1401 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1402 | struct mlx5_core_health *health = &dev->priv.health; | |
1403 | const int niter = 100; | |
d57847dc | 1404 | u32 last_count = 0; |
89d44f0a | 1405 | u32 count; |
89d44f0a MD |
1406 | int i; |
1407 | ||
89d44f0a MD |
1408 | for (i = 0; i < niter; i++) { |
1409 | count = ioread32be(health->health_counter); | |
1410 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1411 | if (last_count && last_count != count) { |
1412 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1413 | return 0; | |
1414 | } | |
1415 | last_count = count; | |
89d44f0a MD |
1416 | } |
1417 | msleep(50); | |
1418 | } | |
1419 | ||
d57847dc | 1420 | return -ETIMEDOUT; |
89d44f0a MD |
1421 | } |
1422 | ||
1061c90f | 1423 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1424 | { |
1425 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1426 | int err; |
1427 | ||
1428 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1429 | ||
1061c90f | 1430 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1431 | if (err) { |
1061c90f MHY |
1432 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" |
1433 | , __func__, err); | |
1434 | return PCI_ERS_RESULT_DISCONNECT; | |
1435 | } | |
1436 | ||
1437 | pci_set_master(pdev); | |
1438 | pci_restore_state(pdev); | |
5d47f6c8 | 1439 | pci_save_state(pdev); |
1061c90f MHY |
1440 | |
1441 | if (wait_vital(pdev)) { | |
d57847dc | 1442 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1443 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1444 | } |
89d44f0a | 1445 | |
1061c90f MHY |
1446 | return PCI_ERS_RESULT_RECOVERED; |
1447 | } | |
1448 | ||
1061c90f MHY |
1449 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1450 | { | |
1451 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1452 | struct mlx5_priv *priv = &dev->priv; | |
1453 | int err; | |
1454 | ||
1455 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1456 | ||
59211bd3 | 1457 | err = mlx5_load_one(dev, priv, false); |
89d44f0a MD |
1458 | if (err) |
1459 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1460 | , __func__, err); | |
1461 | else | |
1462 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1463 | } | |
1464 | ||
1465 | static const struct pci_error_handlers mlx5_err_handler = { | |
1466 | .error_detected = mlx5_pci_err_detected, | |
1467 | .slot_reset = mlx5_pci_slot_reset, | |
1468 | .resume = mlx5_pci_resume | |
1469 | }; | |
1470 | ||
8812c24d MD |
1471 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1472 | { | |
1473 | int ret; | |
1474 | ||
1475 | if (!MLX5_CAP_GEN(dev, force_teardown)) { | |
1476 | mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); | |
1477 | return -EOPNOTSUPP; | |
1478 | } | |
1479 | ||
1480 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1481 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1482 | return -EAGAIN; | |
1483 | } | |
1484 | ||
1485 | ret = mlx5_cmd_force_teardown_hca(dev); | |
1486 | if (ret) { | |
1487 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1488 | return ret; | |
1489 | } | |
1490 | ||
1491 | mlx5_enter_error_state(dev, true); | |
1492 | ||
1493 | return 0; | |
1494 | } | |
1495 | ||
5fc7197d MD |
1496 | static void shutdown(struct pci_dev *pdev) |
1497 | { | |
1498 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1499 | struct mlx5_priv *priv = &dev->priv; | |
8812c24d | 1500 | int err; |
5fc7197d MD |
1501 | |
1502 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
8812c24d MD |
1503 | err = mlx5_try_fast_unload(dev); |
1504 | if (err) | |
1505 | mlx5_unload_one(dev, priv, false); | |
5fc7197d MD |
1506 | mlx5_pci_disable_device(dev); |
1507 | } | |
1508 | ||
9603b61d | 1509 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1510 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1511 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1512 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1513 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1514 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1515 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1516 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1517 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1518 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1519 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1520 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1521 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
2e9d3e83 NO |
1522 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1523 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
9603b61d JM |
1524 | { 0, } |
1525 | }; | |
1526 | ||
1527 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1528 | ||
04c0c1ab MHY |
1529 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1530 | { | |
1531 | mlx5_pci_err_detected(dev->pdev, 0); | |
1532 | } | |
1533 | ||
1534 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1535 | { | |
1536 | mlx5_pci_disable_device(dev); | |
1537 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1538 | mlx5_pci_resume(dev->pdev); | |
1539 | } | |
1540 | ||
9603b61d JM |
1541 | static struct pci_driver mlx5_core_driver = { |
1542 | .name = DRIVER_NAME, | |
1543 | .id_table = mlx5_core_pci_table, | |
1544 | .probe = init_one, | |
89d44f0a | 1545 | .remove = remove_one, |
5fc7197d | 1546 | .shutdown = shutdown, |
fc50db98 EC |
1547 | .err_handler = &mlx5_err_handler, |
1548 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1549 | }; |
e126ba97 | 1550 | |
f663ad98 KH |
1551 | static void mlx5_core_verify_params(void) |
1552 | { | |
1553 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1554 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1555 | prof_sel, | |
1556 | ARRAY_SIZE(profile) - 1, | |
1557 | MLX5_DEFAULT_PROF); | |
1558 | prof_sel = MLX5_DEFAULT_PROF; | |
1559 | } | |
1560 | } | |
1561 | ||
e126ba97 EC |
1562 | static int __init init(void) |
1563 | { | |
1564 | int err; | |
1565 | ||
f663ad98 | 1566 | mlx5_core_verify_params(); |
e126ba97 | 1567 | mlx5_register_debugfs(); |
e126ba97 | 1568 | |
9603b61d JM |
1569 | err = pci_register_driver(&mlx5_core_driver); |
1570 | if (err) | |
ac6ea6e8 | 1571 | goto err_debug; |
9603b61d | 1572 | |
f62b8bb8 AV |
1573 | #ifdef CONFIG_MLX5_CORE_EN |
1574 | mlx5e_init(); | |
1575 | #endif | |
1576 | ||
e126ba97 EC |
1577 | return 0; |
1578 | ||
e126ba97 EC |
1579 | err_debug: |
1580 | mlx5_unregister_debugfs(); | |
1581 | return err; | |
1582 | } | |
1583 | ||
1584 | static void __exit cleanup(void) | |
1585 | { | |
f62b8bb8 AV |
1586 | #ifdef CONFIG_MLX5_CORE_EN |
1587 | mlx5e_cleanup(); | |
1588 | #endif | |
9603b61d | 1589 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1590 | mlx5_unregister_debugfs(); |
1591 | } | |
1592 | ||
1593 | module_init(init); | |
1594 | module_exit(cleanup); |