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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
b775516b | 49 | #include <linux/mlx5/mlx5_ifc.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
feae9087 | 53 | #include <net/devlink.h> |
e126ba97 | 54 | #include "mlx5_core.h" |
86d722ad | 55 | #include "fs_core.h" |
073bb189 SM |
56 | #ifdef CONFIG_MLX5_CORE_EN |
57 | #include "eswitch.h" | |
58 | #endif | |
52ec462e | 59 | #include "lib/mlx5.h" |
e29341fb | 60 | #include "fpga/core.h" |
bebb23e6 | 61 | #include "accel/ipsec.h" |
e126ba97 | 62 | |
e126ba97 | 63 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 64 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
65 | MODULE_LICENSE("Dual BSD/GPL"); |
66 | MODULE_VERSION(DRIVER_VERSION); | |
67 | ||
f663ad98 KH |
68 | unsigned int mlx5_core_debug_mask; |
69 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
70 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
71 | ||
9603b61d | 72 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
73 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
74 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
75 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
76 | ||
f91e6d89 EBE |
77 | enum { |
78 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
79 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
80 | }; | |
81 | ||
9603b61d JM |
82 | static struct mlx5_profile profile[] = { |
83 | [0] = { | |
84 | .mask = 0, | |
85 | }, | |
86 | [1] = { | |
87 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
88 | .log_max_qp = 12, | |
89 | }, | |
90 | [2] = { | |
91 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
92 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 93 | .log_max_qp = 18, |
9603b61d JM |
94 | .mr_cache[0] = { |
95 | .size = 500, | |
96 | .limit = 250 | |
97 | }, | |
98 | .mr_cache[1] = { | |
99 | .size = 500, | |
100 | .limit = 250 | |
101 | }, | |
102 | .mr_cache[2] = { | |
103 | .size = 500, | |
104 | .limit = 250 | |
105 | }, | |
106 | .mr_cache[3] = { | |
107 | .size = 500, | |
108 | .limit = 250 | |
109 | }, | |
110 | .mr_cache[4] = { | |
111 | .size = 500, | |
112 | .limit = 250 | |
113 | }, | |
114 | .mr_cache[5] = { | |
115 | .size = 500, | |
116 | .limit = 250 | |
117 | }, | |
118 | .mr_cache[6] = { | |
119 | .size = 500, | |
120 | .limit = 250 | |
121 | }, | |
122 | .mr_cache[7] = { | |
123 | .size = 500, | |
124 | .limit = 250 | |
125 | }, | |
126 | .mr_cache[8] = { | |
127 | .size = 500, | |
128 | .limit = 250 | |
129 | }, | |
130 | .mr_cache[9] = { | |
131 | .size = 500, | |
132 | .limit = 250 | |
133 | }, | |
134 | .mr_cache[10] = { | |
135 | .size = 500, | |
136 | .limit = 250 | |
137 | }, | |
138 | .mr_cache[11] = { | |
139 | .size = 500, | |
140 | .limit = 250 | |
141 | }, | |
142 | .mr_cache[12] = { | |
143 | .size = 64, | |
144 | .limit = 32 | |
145 | }, | |
146 | .mr_cache[13] = { | |
147 | .size = 32, | |
148 | .limit = 16 | |
149 | }, | |
150 | .mr_cache[14] = { | |
151 | .size = 16, | |
152 | .limit = 8 | |
153 | }, | |
154 | .mr_cache[15] = { | |
155 | .size = 8, | |
156 | .limit = 4 | |
157 | }, | |
7d0cc6ed AK |
158 | .mr_cache[16] = { |
159 | .size = 8, | |
160 | .limit = 4 | |
161 | }, | |
162 | .mr_cache[17] = { | |
163 | .size = 8, | |
164 | .limit = 4 | |
165 | }, | |
166 | .mr_cache[18] = { | |
167 | .size = 8, | |
168 | .limit = 4 | |
169 | }, | |
170 | .mr_cache[19] = { | |
171 | .size = 4, | |
172 | .limit = 2 | |
173 | }, | |
174 | .mr_cache[20] = { | |
175 | .size = 4, | |
176 | .limit = 2 | |
177 | }, | |
9603b61d JM |
178 | }, |
179 | }; | |
e126ba97 | 180 | |
6c780a02 EC |
181 | #define FW_INIT_TIMEOUT_MILI 2000 |
182 | #define FW_INIT_WAIT_MS 2 | |
183 | #define FW_PRE_INIT_TIMEOUT_MILI 10000 | |
e3297246 EC |
184 | |
185 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
186 | { | |
187 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
188 | int err = 0; | |
189 | ||
190 | while (fw_initializing(dev)) { | |
191 | if (time_after(jiffies, end)) { | |
192 | err = -EBUSY; | |
193 | break; | |
194 | } | |
195 | msleep(FW_INIT_WAIT_MS); | |
196 | } | |
197 | ||
198 | return err; | |
199 | } | |
200 | ||
012e50e1 HN |
201 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
202 | { | |
203 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
204 | driver_version); | |
205 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; | |
206 | u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; | |
207 | int remaining_size = driver_ver_sz; | |
208 | char *string; | |
209 | ||
210 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
211 | return; | |
212 | ||
213 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
214 | ||
215 | strncpy(string, "Linux", remaining_size); | |
216 | ||
217 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
218 | strncat(string, ",", remaining_size); | |
219 | ||
220 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
221 | strncat(string, DRIVER_NAME, remaining_size); | |
222 | ||
223 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
224 | strncat(string, ",", remaining_size); | |
225 | ||
226 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
227 | strncat(string, DRIVER_VERSION, remaining_size); | |
228 | ||
229 | /*Send the command*/ | |
230 | MLX5_SET(set_driver_version_in, in, opcode, | |
231 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
232 | ||
233 | mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
234 | } | |
235 | ||
e126ba97 EC |
236 | static int set_dma_caps(struct pci_dev *pdev) |
237 | { | |
238 | int err; | |
239 | ||
240 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
241 | if (err) { | |
1a91de28 | 242 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
243 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
244 | if (err) { | |
1a91de28 | 245 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
246 | return err; |
247 | } | |
248 | } | |
249 | ||
250 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
251 | if (err) { | |
252 | dev_warn(&pdev->dev, | |
1a91de28 | 253 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
254 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
255 | if (err) { | |
256 | dev_err(&pdev->dev, | |
1a91de28 | 257 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
258 | return err; |
259 | } | |
260 | } | |
261 | ||
262 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
263 | return err; | |
264 | } | |
265 | ||
89d44f0a MD |
266 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
267 | { | |
268 | struct pci_dev *pdev = dev->pdev; | |
269 | int err = 0; | |
270 | ||
271 | mutex_lock(&dev->pci_status_mutex); | |
272 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
273 | err = pci_enable_device(pdev); | |
274 | if (!err) | |
275 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
276 | } | |
277 | mutex_unlock(&dev->pci_status_mutex); | |
278 | ||
279 | return err; | |
280 | } | |
281 | ||
282 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
283 | { | |
284 | struct pci_dev *pdev = dev->pdev; | |
285 | ||
286 | mutex_lock(&dev->pci_status_mutex); | |
287 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
288 | pci_disable_device(pdev); | |
289 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
290 | } | |
291 | mutex_unlock(&dev->pci_status_mutex); | |
292 | } | |
293 | ||
e126ba97 EC |
294 | static int request_bar(struct pci_dev *pdev) |
295 | { | |
296 | int err = 0; | |
297 | ||
298 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 299 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
300 | return -ENODEV; |
301 | } | |
302 | ||
303 | err = pci_request_regions(pdev, DRIVER_NAME); | |
304 | if (err) | |
305 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
306 | ||
307 | return err; | |
308 | } | |
309 | ||
310 | static void release_bar(struct pci_dev *pdev) | |
311 | { | |
312 | pci_release_regions(pdev); | |
313 | } | |
314 | ||
315 | static int mlx5_enable_msix(struct mlx5_core_dev *dev) | |
316 | { | |
db058a18 SM |
317 | struct mlx5_priv *priv = &dev->priv; |
318 | struct mlx5_eq_table *table = &priv->eq_table; | |
938fe83c | 319 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 320 | int nvec; |
e126ba97 EC |
321 | int i; |
322 | ||
938fe83c SM |
323 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
324 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
325 | nvec = min_t(int, nvec, num_eqs); |
326 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
327 | return -ENOMEM; | |
328 | ||
db058a18 SM |
329 | priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL); |
330 | ||
331 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); | |
332 | if (!priv->msix_arr || !priv->irq_info) | |
333 | goto err_free_msix; | |
e126ba97 EC |
334 | |
335 | for (i = 0; i < nvec; i++) | |
db058a18 | 336 | priv->msix_arr[i].entry = i; |
e126ba97 | 337 | |
db058a18 | 338 | nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, |
3a9e161a | 339 | MLX5_EQ_VEC_COMP_BASE + 1, nvec); |
f3c9407b AG |
340 | if (nvec < 0) |
341 | return nvec; | |
e126ba97 | 342 | |
f3c9407b | 343 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
344 | |
345 | return 0; | |
db058a18 SM |
346 | |
347 | err_free_msix: | |
348 | kfree(priv->irq_info); | |
349 | kfree(priv->msix_arr); | |
350 | return -ENOMEM; | |
e126ba97 EC |
351 | } |
352 | ||
353 | static void mlx5_disable_msix(struct mlx5_core_dev *dev) | |
354 | { | |
db058a18 | 355 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 EC |
356 | |
357 | pci_disable_msix(dev->pdev); | |
db058a18 SM |
358 | kfree(priv->irq_info); |
359 | kfree(priv->msix_arr); | |
e126ba97 EC |
360 | } |
361 | ||
bd10838a | 362 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
363 | u8 he; |
364 | u8 rsvd[15]; | |
365 | }; | |
366 | ||
87b8de49 EC |
367 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
368 | ||
369 | enum { | |
c7a08ac7 EC |
370 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
371 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
372 | }; |
373 | ||
2974ab6e | 374 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
375 | { |
376 | switch (size) { | |
377 | case 128: | |
378 | return 0; | |
379 | case 256: | |
380 | return 1; | |
381 | case 512: | |
382 | return 2; | |
383 | case 1024: | |
384 | return 3; | |
385 | case 2048: | |
386 | return 4; | |
387 | case 4096: | |
388 | return 5; | |
389 | default: | |
2974ab6e | 390 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
391 | return 0; |
392 | } | |
393 | } | |
394 | ||
b06e7de8 LR |
395 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
396 | enum mlx5_cap_type cap_type, | |
397 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 398 | { |
b775516b EC |
399 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
400 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
401 | void *out, *hca_caps; |
402 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
403 | int err; |
404 | ||
b775516b EC |
405 | memset(in, 0, sizeof(in)); |
406 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 407 | if (!out) |
e126ba97 | 408 | return -ENOMEM; |
938fe83c | 409 | |
b775516b EC |
410 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
411 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
412 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 413 | if (err) { |
938fe83c SM |
414 | mlx5_core_warn(dev, |
415 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
416 | cap_type, cap_mode, err); | |
e126ba97 EC |
417 | goto query_ex; |
418 | } | |
c7a08ac7 | 419 | |
938fe83c SM |
420 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
421 | ||
422 | switch (cap_mode) { | |
423 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 424 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
425 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
426 | break; | |
427 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 428 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
429 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
430 | break; | |
431 | default: | |
432 | mlx5_core_warn(dev, | |
433 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
434 | cap_type, cap_mode); | |
435 | err = -EINVAL; | |
436 | break; | |
437 | } | |
c7a08ac7 EC |
438 | query_ex: |
439 | kfree(out); | |
440 | return err; | |
441 | } | |
442 | ||
b06e7de8 LR |
443 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
444 | { | |
445 | int ret; | |
446 | ||
447 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
448 | if (ret) | |
449 | return ret; | |
450 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
451 | } | |
452 | ||
f91e6d89 | 453 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 454 | { |
c4f287c4 | 455 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 456 | |
b775516b | 457 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 458 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 459 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
460 | } |
461 | ||
f91e6d89 EBE |
462 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
463 | { | |
464 | void *set_ctx; | |
465 | void *set_hca_cap; | |
466 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
467 | int req_endianness; | |
468 | int err; | |
469 | ||
470 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 471 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
472 | if (err) |
473 | return err; | |
474 | } else { | |
475 | return 0; | |
476 | } | |
477 | ||
478 | req_endianness = | |
479 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 480 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
481 | |
482 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
483 | return 0; | |
484 | ||
485 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
486 | if (!set_ctx) | |
487 | return -ENOMEM; | |
488 | ||
489 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
490 | ||
491 | /* Set requestor to host endianness */ | |
bd10838a | 492 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
493 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
494 | ||
495 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
496 | ||
497 | kfree(set_ctx); | |
498 | return err; | |
499 | } | |
500 | ||
c7a08ac7 EC |
501 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
502 | { | |
b775516b | 503 | void *set_ctx = NULL; |
c7a08ac7 | 504 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 505 | int err = -ENOMEM; |
b775516b | 506 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 507 | void *set_hca_cap; |
c7a08ac7 | 508 | |
b775516b | 509 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 510 | if (!set_ctx) |
e126ba97 | 511 | goto query_ex; |
e126ba97 | 512 | |
b06e7de8 | 513 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
514 | if (err) |
515 | goto query_ex; | |
516 | ||
938fe83c SM |
517 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
518 | capability); | |
701052c5 | 519 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
520 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
521 | ||
522 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 523 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 524 | 128); |
c7a08ac7 | 525 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 526 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 527 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 528 | |
883371c4 NO |
529 | /* Check log_max_qp from HCA caps to set in current profile */ |
530 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
531 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
532 | profile[prof_sel].log_max_qp, | |
533 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
534 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
535 | } | |
c7a08ac7 | 536 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
537 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
538 | prof->log_max_qp); | |
c7a08ac7 | 539 | |
938fe83c SM |
540 | /* disable cmdif checksum */ |
541 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 542 | |
91828bd8 MD |
543 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
544 | * than 4K. | |
545 | */ | |
546 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
547 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
548 | ||
fe1e1876 CS |
549 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
550 | ||
f32f5bd2 DJ |
551 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
552 | MLX5_SET(cmd_hca_cap, | |
553 | set_hca_cap, | |
554 | cache_line_128byte, | |
555 | cache_line_size() == 128 ? 1 : 0); | |
556 | ||
f91e6d89 EBE |
557 | err = set_caps(dev, set_ctx, set_sz, |
558 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 559 | |
e126ba97 | 560 | query_ex: |
e126ba97 | 561 | kfree(set_ctx); |
e126ba97 EC |
562 | return err; |
563 | } | |
564 | ||
565 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
566 | { | |
bd10838a OG |
567 | struct mlx5_reg_host_endianness he_in; |
568 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
569 | int err; |
570 | ||
fc50db98 EC |
571 | if (!mlx5_core_is_pf(dev)) |
572 | return 0; | |
573 | ||
e126ba97 EC |
574 | memset(&he_in, 0, sizeof(he_in)); |
575 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
576 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
577 | &he_out, sizeof(he_out), | |
578 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
579 | return err; | |
580 | } | |
581 | ||
0b107106 | 582 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 583 | { |
c4f287c4 SM |
584 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
585 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 586 | |
0b107106 EC |
587 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
588 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
c4f287c4 | 589 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
590 | } |
591 | ||
0b107106 | 592 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 593 | { |
c4f287c4 SM |
594 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
595 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 596 | |
0b107106 EC |
597 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
598 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
c4f287c4 | 599 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
600 | } |
601 | ||
a5a1d1c2 | 602 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
b0844444 EBE |
603 | { |
604 | u32 timer_h, timer_h1, timer_l; | |
605 | ||
606 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
607 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
608 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
609 | if (timer_h != timer_h1) /* wrap around */ | |
610 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
611 | ||
a5a1d1c2 | 612 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
613 | } |
614 | ||
db058a18 SM |
615 | static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) |
616 | { | |
617 | struct mlx5_priv *priv = &mdev->priv; | |
618 | struct msix_entry *msix = priv->msix_arr; | |
619 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
db058a18 SM |
620 | |
621 | if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { | |
622 | mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); | |
623 | return -ENOMEM; | |
624 | } | |
625 | ||
d151d73d | 626 | cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node), |
dda922c8 | 627 | priv->irq_info[i].mask); |
db058a18 | 628 | |
f0d7ae95 AB |
629 | if (IS_ENABLED(CONFIG_SMP) && |
630 | irq_set_affinity_hint(irq, priv->irq_info[i].mask)) | |
b665d98e | 631 | mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq); |
db058a18 SM |
632 | |
633 | return 0; | |
db058a18 SM |
634 | } |
635 | ||
636 | static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) | |
637 | { | |
638 | struct mlx5_priv *priv = &mdev->priv; | |
639 | struct msix_entry *msix = priv->msix_arr; | |
640 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
641 | ||
642 | irq_set_affinity_hint(irq, NULL); | |
643 | free_cpumask_var(priv->irq_info[i].mask); | |
644 | } | |
645 | ||
646 | static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) | |
647 | { | |
648 | int err; | |
649 | int i; | |
650 | ||
651 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { | |
652 | err = mlx5_irq_set_affinity_hint(mdev, i); | |
653 | if (err) | |
654 | goto err_out; | |
655 | } | |
656 | ||
657 | return 0; | |
658 | ||
659 | err_out: | |
660 | for (i--; i >= 0; i--) | |
661 | mlx5_irq_clear_affinity_hint(mdev, i); | |
662 | ||
663 | return err; | |
664 | } | |
665 | ||
666 | static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) | |
667 | { | |
668 | int i; | |
669 | ||
670 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) | |
671 | mlx5_irq_clear_affinity_hint(mdev, i); | |
672 | } | |
673 | ||
0b6e26ce DT |
674 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
675 | unsigned int *irqn) | |
233d05d2 SM |
676 | { |
677 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
678 | struct mlx5_eq *eq, *n; | |
679 | int err = -ENOENT; | |
680 | ||
681 | spin_lock(&table->lock); | |
682 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
683 | if (eq->index == vector) { | |
684 | *eqn = eq->eqn; | |
685 | *irqn = eq->irqn; | |
686 | err = 0; | |
687 | break; | |
688 | } | |
689 | } | |
690 | spin_unlock(&table->lock); | |
691 | ||
692 | return err; | |
693 | } | |
694 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
695 | ||
94c6825e MB |
696 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
697 | { | |
698 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
699 | struct mlx5_eq *eq; | |
700 | ||
701 | spin_lock(&table->lock); | |
702 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
703 | if (eq->eqn == eqn) { | |
704 | spin_unlock(&table->lock); | |
705 | return eq; | |
706 | } | |
707 | ||
708 | spin_unlock(&table->lock); | |
709 | ||
710 | return ERR_PTR(-ENOENT); | |
711 | } | |
712 | ||
233d05d2 SM |
713 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
714 | { | |
715 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
716 | struct mlx5_eq *eq, *n; | |
717 | ||
5a7b27eb MG |
718 | #ifdef CONFIG_RFS_ACCEL |
719 | if (dev->rmap) { | |
720 | free_irq_cpu_rmap(dev->rmap); | |
721 | dev->rmap = NULL; | |
722 | } | |
723 | #endif | |
233d05d2 SM |
724 | spin_lock(&table->lock); |
725 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
726 | list_del(&eq->list); | |
727 | spin_unlock(&table->lock); | |
728 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
729 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
730 | eq->eqn); | |
731 | kfree(eq); | |
732 | spin_lock(&table->lock); | |
733 | } | |
734 | spin_unlock(&table->lock); | |
735 | } | |
736 | ||
737 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
738 | { | |
739 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 740 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
741 | struct mlx5_eq *eq; |
742 | int ncomp_vec; | |
743 | int nent; | |
744 | int err; | |
745 | int i; | |
746 | ||
747 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
748 | ncomp_vec = table->num_comp_vectors; | |
749 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
750 | #ifdef CONFIG_RFS_ACCEL |
751 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
752 | if (!dev->rmap) | |
753 | return -ENOMEM; | |
754 | #endif | |
233d05d2 SM |
755 | for (i = 0; i < ncomp_vec; i++) { |
756 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
757 | if (!eq) { | |
758 | err = -ENOMEM; | |
759 | goto clean; | |
760 | } | |
761 | ||
5a7b27eb MG |
762 | #ifdef CONFIG_RFS_ACCEL |
763 | irq_cpu_rmap_add(dev->rmap, | |
764 | dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector); | |
765 | #endif | |
db058a18 | 766 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
767 | err = mlx5_create_map_eq(dev, eq, |
768 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
01187175 | 769 | name, MLX5_EQ_TYPE_COMP); |
233d05d2 SM |
770 | if (err) { |
771 | kfree(eq); | |
772 | goto clean; | |
773 | } | |
774 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
775 | eq->index = i; | |
776 | spin_lock(&table->lock); | |
777 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
778 | spin_unlock(&table->lock); | |
779 | } | |
780 | ||
781 | return 0; | |
782 | ||
783 | clean: | |
784 | free_comp_eqs(dev); | |
785 | return err; | |
786 | } | |
787 | ||
f62b8bb8 AV |
788 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
789 | { | |
c4f287c4 SM |
790 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
791 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 792 | u32 sup_issi; |
c4f287c4 | 793 | int err; |
f62b8bb8 AV |
794 | |
795 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
796 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
797 | query_out, sizeof(query_out)); | |
f62b8bb8 | 798 | if (err) { |
c4f287c4 SM |
799 | u32 syndrome; |
800 | u8 status; | |
801 | ||
802 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
803 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
804 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
805 | err, status, syndrome); | |
806 | return err; | |
f62b8bb8 AV |
807 | } |
808 | ||
f9c14e46 KH |
809 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
810 | dev->issi = 0; | |
811 | return 0; | |
f62b8bb8 AV |
812 | } |
813 | ||
814 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
815 | ||
816 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
817 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
818 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
819 | |
820 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
821 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
822 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
823 | set_out, sizeof(set_out)); | |
f62b8bb8 | 824 | if (err) { |
f9c14e46 KH |
825 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
826 | err); | |
f62b8bb8 AV |
827 | return err; |
828 | } | |
829 | ||
830 | dev->issi = 1; | |
831 | ||
832 | return 0; | |
e74a1db0 | 833 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
834 | return 0; |
835 | } | |
836 | ||
9eb78923 | 837 | return -EOPNOTSUPP; |
f62b8bb8 | 838 | } |
f62b8bb8 | 839 | |
7907f23a | 840 | |
a31208b1 MD |
841 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
842 | { | |
843 | struct pci_dev *pdev = dev->pdev; | |
844 | int err = 0; | |
e126ba97 | 845 | |
e126ba97 EC |
846 | pci_set_drvdata(dev->pdev, dev); |
847 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
848 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
849 | ||
850 | mutex_init(&priv->pgdir_mutex); | |
851 | INIT_LIST_HEAD(&priv->pgdir_list); | |
852 | spin_lock_init(&priv->mkey_lock); | |
853 | ||
311c7c71 SM |
854 | mutex_init(&priv->alloc_mutex); |
855 | ||
856 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
857 | ||
e126ba97 EC |
858 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
859 | if (!priv->dbg_root) | |
860 | return -ENOMEM; | |
861 | ||
89d44f0a | 862 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 863 | if (err) { |
1a91de28 | 864 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
865 | goto err_dbg; |
866 | } | |
867 | ||
868 | err = request_bar(pdev); | |
869 | if (err) { | |
1a91de28 | 870 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
871 | goto err_disable; |
872 | } | |
873 | ||
874 | pci_set_master(pdev); | |
875 | ||
876 | err = set_dma_caps(pdev); | |
877 | if (err) { | |
878 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
879 | goto err_clr_master; | |
880 | } | |
881 | ||
882 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
883 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
884 | if (!dev->iseg) { | |
885 | err = -ENOMEM; | |
886 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
887 | goto err_clr_master; | |
888 | } | |
a31208b1 MD |
889 | |
890 | return 0; | |
891 | ||
892 | err_clr_master: | |
893 | pci_clear_master(dev->pdev); | |
894 | release_bar(dev->pdev); | |
895 | err_disable: | |
89d44f0a | 896 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
897 | |
898 | err_dbg: | |
899 | debugfs_remove(priv->dbg_root); | |
900 | return err; | |
901 | } | |
902 | ||
903 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
904 | { | |
905 | iounmap(dev->iseg); | |
906 | pci_clear_master(dev->pdev); | |
907 | release_bar(dev->pdev); | |
89d44f0a | 908 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
909 | debugfs_remove(priv->dbg_root); |
910 | } | |
911 | ||
59211bd3 MHY |
912 | static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
913 | { | |
914 | struct pci_dev *pdev = dev->pdev; | |
915 | int err; | |
916 | ||
59211bd3 MHY |
917 | err = mlx5_query_board_id(dev); |
918 | if (err) { | |
919 | dev_err(&pdev->dev, "query board id failed\n"); | |
920 | goto out; | |
921 | } | |
922 | ||
923 | err = mlx5_eq_init(dev); | |
924 | if (err) { | |
925 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
926 | goto out; | |
927 | } | |
928 | ||
59211bd3 MHY |
929 | err = mlx5_init_cq_table(dev); |
930 | if (err) { | |
931 | dev_err(&pdev->dev, "failed to initialize cq table\n"); | |
932 | goto err_eq_cleanup; | |
933 | } | |
934 | ||
935 | mlx5_init_qp_table(dev); | |
936 | ||
937 | mlx5_init_srq_table(dev); | |
938 | ||
939 | mlx5_init_mkey_table(dev); | |
940 | ||
52ec462e IT |
941 | mlx5_init_reserved_gids(dev); |
942 | ||
59211bd3 MHY |
943 | err = mlx5_init_rl_table(dev); |
944 | if (err) { | |
945 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
946 | goto err_tables_cleanup; | |
947 | } | |
948 | ||
c2d6e31a MHY |
949 | #ifdef CONFIG_MLX5_CORE_EN |
950 | err = mlx5_eswitch_init(dev); | |
951 | if (err) { | |
952 | dev_err(&pdev->dev, "Failed to init eswitch %d\n", err); | |
953 | goto err_rl_cleanup; | |
954 | } | |
955 | #endif | |
956 | ||
957 | err = mlx5_sriov_init(dev); | |
958 | if (err) { | |
959 | dev_err(&pdev->dev, "Failed to init sriov %d\n", err); | |
960 | goto err_eswitch_cleanup; | |
961 | } | |
962 | ||
9410733c IT |
963 | err = mlx5_fpga_init(dev); |
964 | if (err) { | |
965 | dev_err(&pdev->dev, "Failed to init fpga device %d\n", err); | |
966 | goto err_sriov_cleanup; | |
967 | } | |
968 | ||
59211bd3 MHY |
969 | return 0; |
970 | ||
9410733c IT |
971 | err_sriov_cleanup: |
972 | mlx5_sriov_cleanup(dev); | |
c2d6e31a MHY |
973 | err_eswitch_cleanup: |
974 | #ifdef CONFIG_MLX5_CORE_EN | |
975 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
976 | ||
977 | err_rl_cleanup: | |
978 | #endif | |
979 | mlx5_cleanup_rl_table(dev); | |
980 | ||
59211bd3 MHY |
981 | err_tables_cleanup: |
982 | mlx5_cleanup_mkey_table(dev); | |
983 | mlx5_cleanup_srq_table(dev); | |
984 | mlx5_cleanup_qp_table(dev); | |
985 | mlx5_cleanup_cq_table(dev); | |
986 | ||
987 | err_eq_cleanup: | |
988 | mlx5_eq_cleanup(dev); | |
989 | ||
990 | out: | |
991 | return err; | |
992 | } | |
993 | ||
994 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
995 | { | |
9410733c | 996 | mlx5_fpga_cleanup(dev); |
c2d6e31a MHY |
997 | mlx5_sriov_cleanup(dev); |
998 | #ifdef CONFIG_MLX5_CORE_EN | |
999 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
1000 | #endif | |
59211bd3 | 1001 | mlx5_cleanup_rl_table(dev); |
52ec462e | 1002 | mlx5_cleanup_reserved_gids(dev); |
59211bd3 MHY |
1003 | mlx5_cleanup_mkey_table(dev); |
1004 | mlx5_cleanup_srq_table(dev); | |
1005 | mlx5_cleanup_qp_table(dev); | |
1006 | mlx5_cleanup_cq_table(dev); | |
1007 | mlx5_eq_cleanup(dev); | |
1008 | } | |
1009 | ||
1010 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |
1011 | bool boot) | |
a31208b1 MD |
1012 | { |
1013 | struct pci_dev *pdev = dev->pdev; | |
1014 | int err; | |
1015 | ||
89d44f0a | 1016 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1017 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
1018 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
1019 | __func__); | |
1020 | goto out; | |
1021 | } | |
1022 | ||
e126ba97 EC |
1023 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
1024 | fw_rev_min(dev), fw_rev_sub(dev)); | |
1025 | ||
89d44f0a MD |
1026 | /* on load removing any previous indication of internal error, device is |
1027 | * up | |
1028 | */ | |
1029 | dev->state = MLX5_DEVICE_STATE_UP; | |
1030 | ||
6c780a02 EC |
1031 | /* wait for firmware to accept initialization segments configurations |
1032 | */ | |
1033 | err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI); | |
1034 | if (err) { | |
1035 | dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n", | |
1036 | FW_PRE_INIT_TIMEOUT_MILI); | |
8ce59b16 | 1037 | goto out_err; |
6c780a02 EC |
1038 | } |
1039 | ||
e126ba97 EC |
1040 | err = mlx5_cmd_init(dev); |
1041 | if (err) { | |
1042 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 1043 | goto out_err; |
e126ba97 EC |
1044 | } |
1045 | ||
e3297246 EC |
1046 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
1047 | if (err) { | |
1048 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
1049 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 1050 | goto err_cmd_cleanup; |
e3297246 EC |
1051 | } |
1052 | ||
0b107106 | 1053 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
1054 | if (err) { |
1055 | dev_err(&pdev->dev, "enable hca failed\n"); | |
59211bd3 | 1056 | goto err_cmd_cleanup; |
cd23b14b EC |
1057 | } |
1058 | ||
f62b8bb8 AV |
1059 | err = mlx5_core_set_issi(dev); |
1060 | if (err) { | |
1061 | dev_err(&pdev->dev, "failed to set issi\n"); | |
1062 | goto err_disable_hca; | |
1063 | } | |
f62b8bb8 | 1064 | |
cd23b14b EC |
1065 | err = mlx5_satisfy_startup_pages(dev, 1); |
1066 | if (err) { | |
1067 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
1068 | goto err_disable_hca; | |
1069 | } | |
1070 | ||
e126ba97 EC |
1071 | err = set_hca_ctrl(dev); |
1072 | if (err) { | |
1073 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 1074 | goto reclaim_boot_pages; |
e126ba97 EC |
1075 | } |
1076 | ||
1077 | err = handle_hca_cap(dev); | |
1078 | if (err) { | |
1079 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 1080 | goto reclaim_boot_pages; |
e126ba97 EC |
1081 | } |
1082 | ||
f91e6d89 EBE |
1083 | err = handle_hca_cap_atomic(dev); |
1084 | if (err) { | |
1085 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
1086 | goto reclaim_boot_pages; | |
e126ba97 EC |
1087 | } |
1088 | ||
cd23b14b | 1089 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1090 | if (err) { |
cd23b14b EC |
1091 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1092 | goto reclaim_boot_pages; | |
e126ba97 EC |
1093 | } |
1094 | ||
1095 | err = mlx5_pagealloc_start(dev); | |
1096 | if (err) { | |
1097 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1098 | goto reclaim_boot_pages; |
e126ba97 EC |
1099 | } |
1100 | ||
1101 | err = mlx5_cmd_init_hca(dev); | |
1102 | if (err) { | |
1103 | dev_err(&pdev->dev, "init hca failed\n"); | |
1104 | goto err_pagealloc_stop; | |
1105 | } | |
1106 | ||
012e50e1 HN |
1107 | mlx5_set_driver_version(dev); |
1108 | ||
e126ba97 EC |
1109 | mlx5_start_health_poll(dev); |
1110 | ||
bba1574c DJ |
1111 | err = mlx5_query_hca_caps(dev); |
1112 | if (err) { | |
1113 | dev_err(&pdev->dev, "query hca failed\n"); | |
1114 | goto err_stop_poll; | |
1115 | } | |
1116 | ||
59211bd3 MHY |
1117 | if (boot && mlx5_init_once(dev, priv)) { |
1118 | dev_err(&pdev->dev, "sw objs init failed\n"); | |
e126ba97 EC |
1119 | goto err_stop_poll; |
1120 | } | |
1121 | ||
1122 | err = mlx5_enable_msix(dev); | |
1123 | if (err) { | |
1124 | dev_err(&pdev->dev, "enable msix failed\n"); | |
59211bd3 | 1125 | goto err_cleanup_once; |
e126ba97 EC |
1126 | } |
1127 | ||
01187175 EC |
1128 | dev->priv.uar = mlx5_get_uars_page(dev); |
1129 | if (!dev->priv.uar) { | |
e126ba97 | 1130 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); |
59211bd3 | 1131 | goto err_disable_msix; |
e126ba97 EC |
1132 | } |
1133 | ||
1134 | err = mlx5_start_eqs(dev); | |
1135 | if (err) { | |
1136 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
9410733c | 1137 | goto err_put_uars; |
e126ba97 EC |
1138 | } |
1139 | ||
233d05d2 SM |
1140 | err = alloc_comp_eqs(dev); |
1141 | if (err) { | |
1142 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1143 | goto err_stop_eqs; | |
1144 | } | |
1145 | ||
db058a18 | 1146 | err = mlx5_irq_set_affinity_hints(dev); |
59211bd3 | 1147 | if (err) { |
db058a18 | 1148 | dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); |
59211bd3 MHY |
1149 | goto err_affinity_hints; |
1150 | } | |
e126ba97 | 1151 | |
86d722ad MG |
1152 | err = mlx5_init_fs(dev); |
1153 | if (err) { | |
1154 | dev_err(&pdev->dev, "Failed to init flow steering\n"); | |
1155 | goto err_fs; | |
1156 | } | |
1466cc5b | 1157 | |
073bb189 | 1158 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1159 | mlx5_eswitch_attach(dev->priv.eswitch); |
073bb189 SM |
1160 | #endif |
1161 | ||
c2d6e31a | 1162 | err = mlx5_sriov_attach(dev); |
fc50db98 EC |
1163 | if (err) { |
1164 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1165 | goto err_sriov; | |
1166 | } | |
1167 | ||
e29341fb IT |
1168 | err = mlx5_fpga_device_start(dev); |
1169 | if (err) { | |
1170 | dev_err(&pdev->dev, "fpga device start failed %d\n", err); | |
52ec462e | 1171 | goto err_fpga_start; |
e29341fb | 1172 | } |
bebb23e6 IT |
1173 | err = mlx5_accel_ipsec_init(dev); |
1174 | if (err) { | |
1175 | dev_err(&pdev->dev, "IPSec device start failed %d\n", err); | |
1176 | goto err_ipsec_start; | |
1177 | } | |
e29341fb | 1178 | |
737a234b MHY |
1179 | if (mlx5_device_registered(dev)) { |
1180 | mlx5_attach_device(dev); | |
1181 | } else { | |
1182 | err = mlx5_register_device(dev); | |
1183 | if (err) { | |
1184 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1185 | goto err_reg_dev; | |
1186 | } | |
a31208b1 MD |
1187 | } |
1188 | ||
5fc7197d MD |
1189 | clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); |
1190 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
89d44f0a MD |
1191 | out: |
1192 | mutex_unlock(&dev->intf_state_mutex); | |
1193 | ||
e126ba97 EC |
1194 | return 0; |
1195 | ||
59211bd3 | 1196 | err_reg_dev: |
bebb23e6 IT |
1197 | mlx5_accel_ipsec_cleanup(dev); |
1198 | err_ipsec_start: | |
52ec462e IT |
1199 | mlx5_fpga_device_stop(dev); |
1200 | ||
1201 | err_fpga_start: | |
c2d6e31a | 1202 | mlx5_sriov_detach(dev); |
fc50db98 | 1203 | |
59211bd3 | 1204 | err_sriov: |
073bb189 | 1205 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1206 | mlx5_eswitch_detach(dev->priv.eswitch); |
073bb189 | 1207 | #endif |
86d722ad | 1208 | mlx5_cleanup_fs(dev); |
59211bd3 | 1209 | |
86d722ad | 1210 | err_fs: |
a31208b1 | 1211 | mlx5_irq_clear_affinity_hints(dev); |
59211bd3 MHY |
1212 | |
1213 | err_affinity_hints: | |
db058a18 SM |
1214 | free_comp_eqs(dev); |
1215 | ||
233d05d2 SM |
1216 | err_stop_eqs: |
1217 | mlx5_stop_eqs(dev); | |
1218 | ||
5fe9dec0 | 1219 | err_put_uars: |
01187175 | 1220 | mlx5_put_uars_page(dev, priv->uar); |
e126ba97 | 1221 | |
59211bd3 | 1222 | err_disable_msix: |
e126ba97 EC |
1223 | mlx5_disable_msix(dev); |
1224 | ||
59211bd3 MHY |
1225 | err_cleanup_once: |
1226 | if (boot) | |
1227 | mlx5_cleanup_once(dev); | |
1228 | ||
e126ba97 EC |
1229 | err_stop_poll: |
1230 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1231 | if (mlx5_cmd_teardown_hca(dev)) { |
1232 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1233 | goto out_err; |
1bde6e30 | 1234 | } |
e126ba97 EC |
1235 | |
1236 | err_pagealloc_stop: | |
1237 | mlx5_pagealloc_stop(dev); | |
1238 | ||
cd23b14b | 1239 | reclaim_boot_pages: |
e126ba97 EC |
1240 | mlx5_reclaim_startup_pages(dev); |
1241 | ||
cd23b14b | 1242 | err_disable_hca: |
0b107106 | 1243 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1244 | |
59211bd3 | 1245 | err_cmd_cleanup: |
e126ba97 EC |
1246 | mlx5_cmd_cleanup(dev); |
1247 | ||
89d44f0a MD |
1248 | out_err: |
1249 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1250 | mutex_unlock(&dev->intf_state_mutex); | |
1251 | ||
e126ba97 EC |
1252 | return err; |
1253 | } | |
e126ba97 | 1254 | |
59211bd3 MHY |
1255 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, |
1256 | bool cleanup) | |
e126ba97 | 1257 | { |
89d44f0a | 1258 | int err = 0; |
e126ba97 | 1259 | |
5e44fca5 | 1260 | if (cleanup) |
2a0165a0 | 1261 | mlx5_drain_health_recovery(dev); |
689a248d | 1262 | |
89d44f0a | 1263 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1264 | if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) { |
89d44f0a MD |
1265 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1266 | __func__); | |
59211bd3 MHY |
1267 | if (cleanup) |
1268 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1269 | goto out; |
1270 | } | |
6b6adee3 | 1271 | |
9ade8c7c IT |
1272 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
1273 | set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); | |
1274 | ||
737a234b MHY |
1275 | if (mlx5_device_registered(dev)) |
1276 | mlx5_detach_device(dev); | |
1277 | ||
bebb23e6 | 1278 | mlx5_accel_ipsec_cleanup(dev); |
52ec462e IT |
1279 | mlx5_fpga_device_stop(dev); |
1280 | ||
c2d6e31a | 1281 | mlx5_sriov_detach(dev); |
073bb189 | 1282 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1283 | mlx5_eswitch_detach(dev->priv.eswitch); |
073bb189 | 1284 | #endif |
86d722ad | 1285 | mlx5_cleanup_fs(dev); |
db058a18 | 1286 | mlx5_irq_clear_affinity_hints(dev); |
233d05d2 | 1287 | free_comp_eqs(dev); |
e126ba97 | 1288 | mlx5_stop_eqs(dev); |
01187175 | 1289 | mlx5_put_uars_page(dev, priv->uar); |
e126ba97 | 1290 | mlx5_disable_msix(dev); |
59211bd3 MHY |
1291 | if (cleanup) |
1292 | mlx5_cleanup_once(dev); | |
e126ba97 | 1293 | mlx5_stop_health_poll(dev); |
ac6ea6e8 EC |
1294 | err = mlx5_cmd_teardown_hca(dev); |
1295 | if (err) { | |
1bde6e30 | 1296 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1297 | goto out; |
1bde6e30 | 1298 | } |
e126ba97 EC |
1299 | mlx5_pagealloc_stop(dev); |
1300 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1301 | mlx5_core_disable_hca(dev, 0); |
e126ba97 | 1302 | mlx5_cmd_cleanup(dev); |
9603b61d | 1303 | |
ac6ea6e8 | 1304 | out: |
89d44f0a | 1305 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1306 | return err; |
9603b61d | 1307 | } |
64613d94 | 1308 | |
9603b61d JM |
1309 | struct mlx5_core_event_handler { |
1310 | void (*event)(struct mlx5_core_dev *dev, | |
1311 | enum mlx5_dev_event event, | |
1312 | void *data); | |
1313 | }; | |
1314 | ||
feae9087 OG |
1315 | static const struct devlink_ops mlx5_devlink_ops = { |
1316 | #ifdef CONFIG_MLX5_CORE_EN | |
1317 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, | |
1318 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
bffaa916 RD |
1319 | .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, |
1320 | .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, | |
7768d197 RD |
1321 | .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, |
1322 | .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, | |
feae9087 OG |
1323 | #endif |
1324 | }; | |
f66f049f | 1325 | |
59211bd3 | 1326 | #define MLX5_IB_MOD "mlx5_ib" |
9603b61d JM |
1327 | static int init_one(struct pci_dev *pdev, |
1328 | const struct pci_device_id *id) | |
1329 | { | |
1330 | struct mlx5_core_dev *dev; | |
feae9087 | 1331 | struct devlink *devlink; |
9603b61d JM |
1332 | struct mlx5_priv *priv; |
1333 | int err; | |
1334 | ||
feae9087 OG |
1335 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1336 | if (!devlink) { | |
9603b61d JM |
1337 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1338 | return -ENOMEM; | |
1339 | } | |
feae9087 OG |
1340 | |
1341 | dev = devlink_priv(devlink); | |
9603b61d | 1342 | priv = &dev->priv; |
fc50db98 | 1343 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1344 | |
1345 | pci_set_drvdata(pdev, dev); | |
1346 | ||
0e97a340 HN |
1347 | dev->pdev = pdev; |
1348 | dev->event = mlx5_core_event; | |
9603b61d | 1349 | dev->profile = &profile[prof_sel]; |
9603b61d | 1350 | |
364d1798 EC |
1351 | INIT_LIST_HEAD(&priv->ctx_list); |
1352 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1353 | mutex_init(&dev->pci_status_mutex); |
1354 | mutex_init(&dev->intf_state_mutex); | |
d9aaed83 AK |
1355 | |
1356 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1357 | err = init_srcu_struct(&priv->pfault_srcu); | |
1358 | if (err) { | |
1359 | dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n", | |
1360 | err); | |
1361 | goto clean_dev; | |
1362 | } | |
1363 | #endif | |
01187175 EC |
1364 | mutex_init(&priv->bfregs.reg_head.lock); |
1365 | mutex_init(&priv->bfregs.wc_head.lock); | |
1366 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1367 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1368 | ||
a31208b1 | 1369 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1370 | if (err) { |
a31208b1 | 1371 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
d9aaed83 | 1372 | goto clean_srcu; |
9603b61d JM |
1373 | } |
1374 | ||
ac6ea6e8 EC |
1375 | err = mlx5_health_init(dev); |
1376 | if (err) { | |
1377 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1378 | goto close_pci; | |
1379 | } | |
1380 | ||
59211bd3 MHY |
1381 | mlx5_pagealloc_init(dev); |
1382 | ||
1383 | err = mlx5_load_one(dev, priv, true); | |
9603b61d | 1384 | if (err) { |
a31208b1 | 1385 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1386 | goto clean_health; |
9603b61d | 1387 | } |
59211bd3 | 1388 | |
f82eed45 | 1389 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1390 | |
feae9087 OG |
1391 | err = devlink_register(devlink, &pdev->dev); |
1392 | if (err) | |
1393 | goto clean_load; | |
1394 | ||
5d47f6c8 | 1395 | pci_save_state(pdev); |
9603b61d JM |
1396 | return 0; |
1397 | ||
feae9087 | 1398 | clean_load: |
59211bd3 | 1399 | mlx5_unload_one(dev, priv, true); |
ac6ea6e8 | 1400 | clean_health: |
59211bd3 | 1401 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1402 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1403 | close_pci: |
1404 | mlx5_pci_close(dev, priv); | |
d9aaed83 AK |
1405 | clean_srcu: |
1406 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1407 | cleanup_srcu_struct(&priv->pfault_srcu); | |
a31208b1 | 1408 | clean_dev: |
d9aaed83 | 1409 | #endif |
a31208b1 | 1410 | pci_set_drvdata(pdev, NULL); |
feae9087 | 1411 | devlink_free(devlink); |
a31208b1 | 1412 | |
9603b61d JM |
1413 | return err; |
1414 | } | |
a31208b1 | 1415 | |
9603b61d JM |
1416 | static void remove_one(struct pci_dev *pdev) |
1417 | { | |
1418 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1419 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1420 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1421 | |
feae9087 | 1422 | devlink_unregister(devlink); |
737a234b MHY |
1423 | mlx5_unregister_device(dev); |
1424 | ||
59211bd3 | 1425 | if (mlx5_unload_one(dev, priv, true)) { |
a31208b1 | 1426 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); |
ac6ea6e8 | 1427 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1428 | return; |
1429 | } | |
737a234b | 1430 | |
59211bd3 | 1431 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1432 | mlx5_health_cleanup(dev); |
a31208b1 | 1433 | mlx5_pci_close(dev, priv); |
d9aaed83 AK |
1434 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1435 | cleanup_srcu_struct(&priv->pfault_srcu); | |
1436 | #endif | |
a31208b1 | 1437 | pci_set_drvdata(pdev, NULL); |
feae9087 | 1438 | devlink_free(devlink); |
9603b61d JM |
1439 | } |
1440 | ||
89d44f0a MD |
1441 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1442 | pci_channel_state_t state) | |
1443 | { | |
1444 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1445 | struct mlx5_priv *priv = &dev->priv; | |
1446 | ||
1447 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
04c0c1ab | 1448 | |
8812c24d | 1449 | mlx5_enter_error_state(dev, false); |
59211bd3 | 1450 | mlx5_unload_one(dev, priv, false); |
5d47f6c8 | 1451 | /* In case of kernel call drain the health wq */ |
05ac2c0b | 1452 | if (state) { |
5e44fca5 | 1453 | mlx5_drain_health_wq(dev); |
05ac2c0b MHY |
1454 | mlx5_pci_disable_device(dev); |
1455 | } | |
1456 | ||
89d44f0a MD |
1457 | return state == pci_channel_io_perm_failure ? |
1458 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1459 | } | |
1460 | ||
d57847dc DJ |
1461 | /* wait for the device to show vital signs by waiting |
1462 | * for the health counter to start counting. | |
89d44f0a | 1463 | */ |
d57847dc | 1464 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1465 | { |
1466 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1467 | struct mlx5_core_health *health = &dev->priv.health; | |
1468 | const int niter = 100; | |
d57847dc | 1469 | u32 last_count = 0; |
89d44f0a | 1470 | u32 count; |
89d44f0a MD |
1471 | int i; |
1472 | ||
89d44f0a MD |
1473 | for (i = 0; i < niter; i++) { |
1474 | count = ioread32be(health->health_counter); | |
1475 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1476 | if (last_count && last_count != count) { |
1477 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1478 | return 0; | |
1479 | } | |
1480 | last_count = count; | |
89d44f0a MD |
1481 | } |
1482 | msleep(50); | |
1483 | } | |
1484 | ||
d57847dc | 1485 | return -ETIMEDOUT; |
89d44f0a MD |
1486 | } |
1487 | ||
1061c90f | 1488 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1489 | { |
1490 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1491 | int err; |
1492 | ||
1493 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1494 | ||
1061c90f | 1495 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1496 | if (err) { |
1061c90f MHY |
1497 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" |
1498 | , __func__, err); | |
1499 | return PCI_ERS_RESULT_DISCONNECT; | |
1500 | } | |
1501 | ||
1502 | pci_set_master(pdev); | |
1503 | pci_restore_state(pdev); | |
5d47f6c8 | 1504 | pci_save_state(pdev); |
1061c90f MHY |
1505 | |
1506 | if (wait_vital(pdev)) { | |
d57847dc | 1507 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1508 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1509 | } |
89d44f0a | 1510 | |
1061c90f MHY |
1511 | return PCI_ERS_RESULT_RECOVERED; |
1512 | } | |
1513 | ||
1061c90f MHY |
1514 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1515 | { | |
1516 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1517 | struct mlx5_priv *priv = &dev->priv; | |
1518 | int err; | |
1519 | ||
1520 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1521 | ||
59211bd3 | 1522 | err = mlx5_load_one(dev, priv, false); |
89d44f0a MD |
1523 | if (err) |
1524 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1525 | , __func__, err); | |
1526 | else | |
1527 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1528 | } | |
1529 | ||
1530 | static const struct pci_error_handlers mlx5_err_handler = { | |
1531 | .error_detected = mlx5_pci_err_detected, | |
1532 | .slot_reset = mlx5_pci_slot_reset, | |
1533 | .resume = mlx5_pci_resume | |
1534 | }; | |
1535 | ||
8812c24d MD |
1536 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1537 | { | |
1538 | int ret; | |
1539 | ||
1540 | if (!MLX5_CAP_GEN(dev, force_teardown)) { | |
1541 | mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); | |
1542 | return -EOPNOTSUPP; | |
1543 | } | |
1544 | ||
1545 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1546 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1547 | return -EAGAIN; | |
1548 | } | |
1549 | ||
1550 | ret = mlx5_cmd_force_teardown_hca(dev); | |
1551 | if (ret) { | |
1552 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1553 | return ret; | |
1554 | } | |
1555 | ||
1556 | mlx5_enter_error_state(dev, true); | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
5fc7197d MD |
1561 | static void shutdown(struct pci_dev *pdev) |
1562 | { | |
1563 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1564 | struct mlx5_priv *priv = &dev->priv; | |
8812c24d | 1565 | int err; |
5fc7197d MD |
1566 | |
1567 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
1568 | /* Notify mlx5 clients that the kernel is being shut down */ | |
1569 | set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state); | |
8812c24d MD |
1570 | err = mlx5_try_fast_unload(dev); |
1571 | if (err) | |
1572 | mlx5_unload_one(dev, priv, false); | |
5fc7197d MD |
1573 | mlx5_pci_disable_device(dev); |
1574 | } | |
1575 | ||
9603b61d | 1576 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1577 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1578 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1579 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1580 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1581 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1582 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1583 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1584 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1585 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1586 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1587 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1588 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
2e9d3e83 NO |
1589 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1590 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
9603b61d JM |
1591 | { 0, } |
1592 | }; | |
1593 | ||
1594 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1595 | ||
04c0c1ab MHY |
1596 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1597 | { | |
1598 | mlx5_pci_err_detected(dev->pdev, 0); | |
1599 | } | |
1600 | ||
1601 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1602 | { | |
1603 | mlx5_pci_disable_device(dev); | |
1604 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1605 | mlx5_pci_resume(dev->pdev); | |
1606 | } | |
1607 | ||
9603b61d JM |
1608 | static struct pci_driver mlx5_core_driver = { |
1609 | .name = DRIVER_NAME, | |
1610 | .id_table = mlx5_core_pci_table, | |
1611 | .probe = init_one, | |
89d44f0a | 1612 | .remove = remove_one, |
5fc7197d | 1613 | .shutdown = shutdown, |
fc50db98 EC |
1614 | .err_handler = &mlx5_err_handler, |
1615 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1616 | }; |
e126ba97 | 1617 | |
f663ad98 KH |
1618 | static void mlx5_core_verify_params(void) |
1619 | { | |
1620 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1621 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1622 | prof_sel, | |
1623 | ARRAY_SIZE(profile) - 1, | |
1624 | MLX5_DEFAULT_PROF); | |
1625 | prof_sel = MLX5_DEFAULT_PROF; | |
1626 | } | |
1627 | } | |
1628 | ||
e126ba97 EC |
1629 | static int __init init(void) |
1630 | { | |
1631 | int err; | |
1632 | ||
f663ad98 | 1633 | mlx5_core_verify_params(); |
e126ba97 | 1634 | mlx5_register_debugfs(); |
e126ba97 | 1635 | |
9603b61d JM |
1636 | err = pci_register_driver(&mlx5_core_driver); |
1637 | if (err) | |
ac6ea6e8 | 1638 | goto err_debug; |
9603b61d | 1639 | |
f62b8bb8 AV |
1640 | #ifdef CONFIG_MLX5_CORE_EN |
1641 | mlx5e_init(); | |
1642 | #endif | |
1643 | ||
e126ba97 EC |
1644 | return 0; |
1645 | ||
e126ba97 EC |
1646 | err_debug: |
1647 | mlx5_unregister_debugfs(); | |
1648 | return err; | |
1649 | } | |
1650 | ||
1651 | static void __exit cleanup(void) | |
1652 | { | |
f62b8bb8 AV |
1653 | #ifdef CONFIG_MLX5_CORE_EN |
1654 | mlx5e_cleanup(); | |
1655 | #endif | |
9603b61d | 1656 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1657 | mlx5_unregister_debugfs(); |
1658 | } | |
1659 | ||
1660 | module_init(init); | |
1661 | module_exit(cleanup); |