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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
b775516b | 49 | #include <linux/mlx5/mlx5_ifc.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
feae9087 | 53 | #include <net/devlink.h> |
e126ba97 | 54 | #include "mlx5_core.h" |
86d722ad | 55 | #include "fs_core.h" |
073bb189 SM |
56 | #ifdef CONFIG_MLX5_CORE_EN |
57 | #include "eswitch.h" | |
58 | #endif | |
e126ba97 | 59 | |
e126ba97 | 60 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 61 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
62 | MODULE_LICENSE("Dual BSD/GPL"); |
63 | MODULE_VERSION(DRIVER_VERSION); | |
64 | ||
f663ad98 KH |
65 | unsigned int mlx5_core_debug_mask; |
66 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
67 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
68 | ||
9603b61d | 69 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
70 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
71 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
72 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
73 | ||
f91e6d89 EBE |
74 | enum { |
75 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
76 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
77 | }; | |
78 | ||
9603b61d JM |
79 | static struct mlx5_profile profile[] = { |
80 | [0] = { | |
81 | .mask = 0, | |
82 | }, | |
83 | [1] = { | |
84 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
85 | .log_max_qp = 12, | |
86 | }, | |
87 | [2] = { | |
88 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
89 | MLX5_PROF_MASK_MR_CACHE, | |
90 | .log_max_qp = 17, | |
91 | .mr_cache[0] = { | |
92 | .size = 500, | |
93 | .limit = 250 | |
94 | }, | |
95 | .mr_cache[1] = { | |
96 | .size = 500, | |
97 | .limit = 250 | |
98 | }, | |
99 | .mr_cache[2] = { | |
100 | .size = 500, | |
101 | .limit = 250 | |
102 | }, | |
103 | .mr_cache[3] = { | |
104 | .size = 500, | |
105 | .limit = 250 | |
106 | }, | |
107 | .mr_cache[4] = { | |
108 | .size = 500, | |
109 | .limit = 250 | |
110 | }, | |
111 | .mr_cache[5] = { | |
112 | .size = 500, | |
113 | .limit = 250 | |
114 | }, | |
115 | .mr_cache[6] = { | |
116 | .size = 500, | |
117 | .limit = 250 | |
118 | }, | |
119 | .mr_cache[7] = { | |
120 | .size = 500, | |
121 | .limit = 250 | |
122 | }, | |
123 | .mr_cache[8] = { | |
124 | .size = 500, | |
125 | .limit = 250 | |
126 | }, | |
127 | .mr_cache[9] = { | |
128 | .size = 500, | |
129 | .limit = 250 | |
130 | }, | |
131 | .mr_cache[10] = { | |
132 | .size = 500, | |
133 | .limit = 250 | |
134 | }, | |
135 | .mr_cache[11] = { | |
136 | .size = 500, | |
137 | .limit = 250 | |
138 | }, | |
139 | .mr_cache[12] = { | |
140 | .size = 64, | |
141 | .limit = 32 | |
142 | }, | |
143 | .mr_cache[13] = { | |
144 | .size = 32, | |
145 | .limit = 16 | |
146 | }, | |
147 | .mr_cache[14] = { | |
148 | .size = 16, | |
149 | .limit = 8 | |
150 | }, | |
151 | .mr_cache[15] = { | |
152 | .size = 8, | |
153 | .limit = 4 | |
154 | }, | |
155 | }, | |
156 | }; | |
e126ba97 | 157 | |
e3297246 EC |
158 | #define FW_INIT_TIMEOUT_MILI 2000 |
159 | #define FW_INIT_WAIT_MS 2 | |
160 | ||
161 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
162 | { | |
163 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
164 | int err = 0; | |
165 | ||
166 | while (fw_initializing(dev)) { | |
167 | if (time_after(jiffies, end)) { | |
168 | err = -EBUSY; | |
169 | break; | |
170 | } | |
171 | msleep(FW_INIT_WAIT_MS); | |
172 | } | |
173 | ||
174 | return err; | |
175 | } | |
176 | ||
012e50e1 HN |
177 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
178 | { | |
179 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
180 | driver_version); | |
181 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; | |
182 | u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; | |
183 | int remaining_size = driver_ver_sz; | |
184 | char *string; | |
185 | ||
186 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
187 | return; | |
188 | ||
189 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
190 | ||
191 | strncpy(string, "Linux", remaining_size); | |
192 | ||
193 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
194 | strncat(string, ",", remaining_size); | |
195 | ||
196 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
197 | strncat(string, DRIVER_NAME, remaining_size); | |
198 | ||
199 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
200 | strncat(string, ",", remaining_size); | |
201 | ||
202 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
203 | strncat(string, DRIVER_VERSION, remaining_size); | |
204 | ||
205 | /*Send the command*/ | |
206 | MLX5_SET(set_driver_version_in, in, opcode, | |
207 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
208 | ||
209 | mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
210 | } | |
211 | ||
e126ba97 EC |
212 | static int set_dma_caps(struct pci_dev *pdev) |
213 | { | |
214 | int err; | |
215 | ||
216 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
217 | if (err) { | |
1a91de28 | 218 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
219 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
220 | if (err) { | |
1a91de28 | 221 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
222 | return err; |
223 | } | |
224 | } | |
225 | ||
226 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
227 | if (err) { | |
228 | dev_warn(&pdev->dev, | |
1a91de28 | 229 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
230 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
231 | if (err) { | |
232 | dev_err(&pdev->dev, | |
1a91de28 | 233 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
234 | return err; |
235 | } | |
236 | } | |
237 | ||
238 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
239 | return err; | |
240 | } | |
241 | ||
89d44f0a MD |
242 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
243 | { | |
244 | struct pci_dev *pdev = dev->pdev; | |
245 | int err = 0; | |
246 | ||
247 | mutex_lock(&dev->pci_status_mutex); | |
248 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
249 | err = pci_enable_device(pdev); | |
250 | if (!err) | |
251 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
252 | } | |
253 | mutex_unlock(&dev->pci_status_mutex); | |
254 | ||
255 | return err; | |
256 | } | |
257 | ||
258 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
259 | { | |
260 | struct pci_dev *pdev = dev->pdev; | |
261 | ||
262 | mutex_lock(&dev->pci_status_mutex); | |
263 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
264 | pci_disable_device(pdev); | |
265 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
266 | } | |
267 | mutex_unlock(&dev->pci_status_mutex); | |
268 | } | |
269 | ||
e126ba97 EC |
270 | static int request_bar(struct pci_dev *pdev) |
271 | { | |
272 | int err = 0; | |
273 | ||
274 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 275 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
276 | return -ENODEV; |
277 | } | |
278 | ||
279 | err = pci_request_regions(pdev, DRIVER_NAME); | |
280 | if (err) | |
281 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
282 | ||
283 | return err; | |
284 | } | |
285 | ||
286 | static void release_bar(struct pci_dev *pdev) | |
287 | { | |
288 | pci_release_regions(pdev); | |
289 | } | |
290 | ||
291 | static int mlx5_enable_msix(struct mlx5_core_dev *dev) | |
292 | { | |
db058a18 SM |
293 | struct mlx5_priv *priv = &dev->priv; |
294 | struct mlx5_eq_table *table = &priv->eq_table; | |
938fe83c | 295 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 296 | int nvec; |
e126ba97 EC |
297 | int i; |
298 | ||
938fe83c SM |
299 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
300 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
301 | nvec = min_t(int, nvec, num_eqs); |
302 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
303 | return -ENOMEM; | |
304 | ||
db058a18 SM |
305 | priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL); |
306 | ||
307 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); | |
308 | if (!priv->msix_arr || !priv->irq_info) | |
309 | goto err_free_msix; | |
e126ba97 EC |
310 | |
311 | for (i = 0; i < nvec; i++) | |
db058a18 | 312 | priv->msix_arr[i].entry = i; |
e126ba97 | 313 | |
db058a18 | 314 | nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, |
3a9e161a | 315 | MLX5_EQ_VEC_COMP_BASE + 1, nvec); |
f3c9407b AG |
316 | if (nvec < 0) |
317 | return nvec; | |
e126ba97 | 318 | |
f3c9407b | 319 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
320 | |
321 | return 0; | |
db058a18 SM |
322 | |
323 | err_free_msix: | |
324 | kfree(priv->irq_info); | |
325 | kfree(priv->msix_arr); | |
326 | return -ENOMEM; | |
e126ba97 EC |
327 | } |
328 | ||
329 | static void mlx5_disable_msix(struct mlx5_core_dev *dev) | |
330 | { | |
db058a18 | 331 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 EC |
332 | |
333 | pci_disable_msix(dev->pdev); | |
db058a18 SM |
334 | kfree(priv->irq_info); |
335 | kfree(priv->msix_arr); | |
e126ba97 EC |
336 | } |
337 | ||
338 | struct mlx5_reg_host_endianess { | |
339 | u8 he; | |
340 | u8 rsvd[15]; | |
341 | }; | |
342 | ||
87b8de49 EC |
343 | |
344 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) | |
345 | ||
346 | enum { | |
c7a08ac7 EC |
347 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
348 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
349 | }; |
350 | ||
2974ab6e | 351 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
352 | { |
353 | switch (size) { | |
354 | case 128: | |
355 | return 0; | |
356 | case 256: | |
357 | return 1; | |
358 | case 512: | |
359 | return 2; | |
360 | case 1024: | |
361 | return 3; | |
362 | case 2048: | |
363 | return 4; | |
364 | case 4096: | |
365 | return 5; | |
366 | default: | |
2974ab6e | 367 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
368 | return 0; |
369 | } | |
370 | } | |
371 | ||
b06e7de8 LR |
372 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
373 | enum mlx5_cap_type cap_type, | |
374 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 375 | { |
b775516b EC |
376 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
377 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
378 | void *out, *hca_caps; |
379 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
380 | int err; |
381 | ||
b775516b EC |
382 | memset(in, 0, sizeof(in)); |
383 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 384 | if (!out) |
e126ba97 | 385 | return -ENOMEM; |
938fe83c | 386 | |
b775516b EC |
387 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
388 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
389 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 390 | if (err) { |
938fe83c SM |
391 | mlx5_core_warn(dev, |
392 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
393 | cap_type, cap_mode, err); | |
e126ba97 EC |
394 | goto query_ex; |
395 | } | |
c7a08ac7 | 396 | |
938fe83c SM |
397 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
398 | ||
399 | switch (cap_mode) { | |
400 | case HCA_CAP_OPMOD_GET_MAX: | |
401 | memcpy(dev->hca_caps_max[cap_type], hca_caps, | |
402 | MLX5_UN_SZ_BYTES(hca_cap_union)); | |
403 | break; | |
404 | case HCA_CAP_OPMOD_GET_CUR: | |
405 | memcpy(dev->hca_caps_cur[cap_type], hca_caps, | |
406 | MLX5_UN_SZ_BYTES(hca_cap_union)); | |
407 | break; | |
408 | default: | |
409 | mlx5_core_warn(dev, | |
410 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
411 | cap_type, cap_mode); | |
412 | err = -EINVAL; | |
413 | break; | |
414 | } | |
c7a08ac7 EC |
415 | query_ex: |
416 | kfree(out); | |
417 | return err; | |
418 | } | |
419 | ||
b06e7de8 LR |
420 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
421 | { | |
422 | int ret; | |
423 | ||
424 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
425 | if (ret) | |
426 | return ret; | |
427 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
428 | } | |
429 | ||
f91e6d89 | 430 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 431 | { |
c4f287c4 | 432 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 433 | |
b775516b | 434 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 435 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 436 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
437 | } |
438 | ||
f91e6d89 EBE |
439 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
440 | { | |
441 | void *set_ctx; | |
442 | void *set_hca_cap; | |
443 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
444 | int req_endianness; | |
445 | int err; | |
446 | ||
447 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 448 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
449 | if (err) |
450 | return err; | |
451 | } else { | |
452 | return 0; | |
453 | } | |
454 | ||
455 | req_endianness = | |
456 | MLX5_CAP_ATOMIC(dev, | |
457 | supported_atomic_req_8B_endianess_mode_1); | |
458 | ||
459 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
460 | return 0; | |
461 | ||
462 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
463 | if (!set_ctx) | |
464 | return -ENOMEM; | |
465 | ||
466 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
467 | ||
468 | /* Set requestor to host endianness */ | |
469 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, | |
470 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); | |
471 | ||
472 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
473 | ||
474 | kfree(set_ctx); | |
475 | return err; | |
476 | } | |
477 | ||
c7a08ac7 EC |
478 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
479 | { | |
b775516b | 480 | void *set_ctx = NULL; |
c7a08ac7 | 481 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 482 | int err = -ENOMEM; |
b775516b | 483 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 484 | void *set_hca_cap; |
c7a08ac7 | 485 | |
b775516b | 486 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 487 | if (!set_ctx) |
e126ba97 | 488 | goto query_ex; |
e126ba97 | 489 | |
b06e7de8 | 490 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
491 | if (err) |
492 | goto query_ex; | |
493 | ||
938fe83c SM |
494 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
495 | capability); | |
496 | memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], | |
497 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); | |
498 | ||
499 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 500 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 501 | 128); |
c7a08ac7 | 502 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 503 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 504 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 EC |
505 | |
506 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) | |
938fe83c SM |
507 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
508 | prof->log_max_qp); | |
c7a08ac7 | 509 | |
938fe83c SM |
510 | /* disable cmdif checksum */ |
511 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 512 | |
fe1e1876 CS |
513 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
514 | ||
f91e6d89 EBE |
515 | err = set_caps(dev, set_ctx, set_sz, |
516 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 517 | |
e126ba97 | 518 | query_ex: |
e126ba97 | 519 | kfree(set_ctx); |
e126ba97 EC |
520 | return err; |
521 | } | |
522 | ||
523 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
524 | { | |
525 | struct mlx5_reg_host_endianess he_in; | |
526 | struct mlx5_reg_host_endianess he_out; | |
527 | int err; | |
528 | ||
fc50db98 EC |
529 | if (!mlx5_core_is_pf(dev)) |
530 | return 0; | |
531 | ||
e126ba97 EC |
532 | memset(&he_in, 0, sizeof(he_in)); |
533 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
534 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
535 | &he_out, sizeof(he_out), | |
536 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
537 | return err; | |
538 | } | |
539 | ||
0b107106 | 540 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 541 | { |
c4f287c4 SM |
542 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
543 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 544 | |
0b107106 EC |
545 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
546 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
c4f287c4 | 547 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
548 | } |
549 | ||
0b107106 | 550 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 551 | { |
c4f287c4 SM |
552 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
553 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 554 | |
0b107106 EC |
555 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
556 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
c4f287c4 | 557 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
558 | } |
559 | ||
a5a1d1c2 | 560 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
b0844444 EBE |
561 | { |
562 | u32 timer_h, timer_h1, timer_l; | |
563 | ||
564 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
565 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
566 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
567 | if (timer_h != timer_h1) /* wrap around */ | |
568 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
569 | ||
a5a1d1c2 | 570 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
571 | } |
572 | ||
db058a18 SM |
573 | static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) |
574 | { | |
575 | struct mlx5_priv *priv = &mdev->priv; | |
576 | struct msix_entry *msix = priv->msix_arr; | |
577 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
311c7c71 | 578 | int numa_node = priv->numa_node; |
db058a18 SM |
579 | int err; |
580 | ||
581 | if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { | |
582 | mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); | |
583 | return -ENOMEM; | |
584 | } | |
585 | ||
dda922c8 DM |
586 | cpumask_set_cpu(cpumask_local_spread(i, numa_node), |
587 | priv->irq_info[i].mask); | |
db058a18 SM |
588 | |
589 | err = irq_set_affinity_hint(irq, priv->irq_info[i].mask); | |
590 | if (err) { | |
591 | mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x", | |
592 | irq); | |
593 | goto err_clear_mask; | |
594 | } | |
595 | ||
596 | return 0; | |
597 | ||
598 | err_clear_mask: | |
599 | free_cpumask_var(priv->irq_info[i].mask); | |
600 | return err; | |
601 | } | |
602 | ||
603 | static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) | |
604 | { | |
605 | struct mlx5_priv *priv = &mdev->priv; | |
606 | struct msix_entry *msix = priv->msix_arr; | |
607 | int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector; | |
608 | ||
609 | irq_set_affinity_hint(irq, NULL); | |
610 | free_cpumask_var(priv->irq_info[i].mask); | |
611 | } | |
612 | ||
613 | static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) | |
614 | { | |
615 | int err; | |
616 | int i; | |
617 | ||
618 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { | |
619 | err = mlx5_irq_set_affinity_hint(mdev, i); | |
620 | if (err) | |
621 | goto err_out; | |
622 | } | |
623 | ||
624 | return 0; | |
625 | ||
626 | err_out: | |
627 | for (i--; i >= 0; i--) | |
628 | mlx5_irq_clear_affinity_hint(mdev, i); | |
629 | ||
630 | return err; | |
631 | } | |
632 | ||
633 | static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) | |
634 | { | |
635 | int i; | |
636 | ||
637 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) | |
638 | mlx5_irq_clear_affinity_hint(mdev, i); | |
639 | } | |
640 | ||
0b6e26ce DT |
641 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
642 | unsigned int *irqn) | |
233d05d2 SM |
643 | { |
644 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
645 | struct mlx5_eq *eq, *n; | |
646 | int err = -ENOENT; | |
647 | ||
648 | spin_lock(&table->lock); | |
649 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
650 | if (eq->index == vector) { | |
651 | *eqn = eq->eqn; | |
652 | *irqn = eq->irqn; | |
653 | err = 0; | |
654 | break; | |
655 | } | |
656 | } | |
657 | spin_unlock(&table->lock); | |
658 | ||
659 | return err; | |
660 | } | |
661 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
662 | ||
94c6825e MB |
663 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
664 | { | |
665 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
666 | struct mlx5_eq *eq; | |
667 | ||
668 | spin_lock(&table->lock); | |
669 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
670 | if (eq->eqn == eqn) { | |
671 | spin_unlock(&table->lock); | |
672 | return eq; | |
673 | } | |
674 | ||
675 | spin_unlock(&table->lock); | |
676 | ||
677 | return ERR_PTR(-ENOENT); | |
678 | } | |
679 | ||
233d05d2 SM |
680 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
681 | { | |
682 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
683 | struct mlx5_eq *eq, *n; | |
684 | ||
5a7b27eb MG |
685 | #ifdef CONFIG_RFS_ACCEL |
686 | if (dev->rmap) { | |
687 | free_irq_cpu_rmap(dev->rmap); | |
688 | dev->rmap = NULL; | |
689 | } | |
690 | #endif | |
233d05d2 SM |
691 | spin_lock(&table->lock); |
692 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
693 | list_del(&eq->list); | |
694 | spin_unlock(&table->lock); | |
695 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
696 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
697 | eq->eqn); | |
698 | kfree(eq); | |
699 | spin_lock(&table->lock); | |
700 | } | |
701 | spin_unlock(&table->lock); | |
702 | } | |
703 | ||
704 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
705 | { | |
706 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 707 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
708 | struct mlx5_eq *eq; |
709 | int ncomp_vec; | |
710 | int nent; | |
711 | int err; | |
712 | int i; | |
713 | ||
714 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
715 | ncomp_vec = table->num_comp_vectors; | |
716 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
717 | #ifdef CONFIG_RFS_ACCEL |
718 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
719 | if (!dev->rmap) | |
720 | return -ENOMEM; | |
721 | #endif | |
233d05d2 SM |
722 | for (i = 0; i < ncomp_vec; i++) { |
723 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
724 | if (!eq) { | |
725 | err = -ENOMEM; | |
726 | goto clean; | |
727 | } | |
728 | ||
5a7b27eb MG |
729 | #ifdef CONFIG_RFS_ACCEL |
730 | irq_cpu_rmap_add(dev->rmap, | |
731 | dev->priv.msix_arr[i + MLX5_EQ_VEC_COMP_BASE].vector); | |
732 | #endif | |
db058a18 | 733 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
734 | err = mlx5_create_map_eq(dev, eq, |
735 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
736 | name, &dev->priv.uuari.uars[0]); | |
737 | if (err) { | |
738 | kfree(eq); | |
739 | goto clean; | |
740 | } | |
741 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
742 | eq->index = i; | |
743 | spin_lock(&table->lock); | |
744 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
745 | spin_unlock(&table->lock); | |
746 | } | |
747 | ||
748 | return 0; | |
749 | ||
750 | clean: | |
751 | free_comp_eqs(dev); | |
752 | return err; | |
753 | } | |
754 | ||
f62b8bb8 AV |
755 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
756 | { | |
c4f287c4 SM |
757 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
758 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 759 | u32 sup_issi; |
c4f287c4 | 760 | int err; |
f62b8bb8 AV |
761 | |
762 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
763 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
764 | query_out, sizeof(query_out)); | |
f62b8bb8 | 765 | if (err) { |
c4f287c4 SM |
766 | u32 syndrome; |
767 | u8 status; | |
768 | ||
769 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
770 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
771 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
772 | err, status, syndrome); | |
773 | return err; | |
f62b8bb8 AV |
774 | } |
775 | ||
f9c14e46 KH |
776 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
777 | dev->issi = 0; | |
778 | return 0; | |
f62b8bb8 AV |
779 | } |
780 | ||
781 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
782 | ||
783 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
784 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
785 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
786 | |
787 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
788 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
789 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
790 | set_out, sizeof(set_out)); | |
f62b8bb8 | 791 | if (err) { |
f9c14e46 KH |
792 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
793 | err); | |
f62b8bb8 AV |
794 | return err; |
795 | } | |
796 | ||
797 | dev->issi = 1; | |
798 | ||
799 | return 0; | |
e74a1db0 | 800 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
801 | return 0; |
802 | } | |
803 | ||
804 | return -ENOTSUPP; | |
805 | } | |
f62b8bb8 | 806 | |
7907f23a | 807 | |
a31208b1 MD |
808 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
809 | { | |
810 | struct pci_dev *pdev = dev->pdev; | |
811 | int err = 0; | |
e126ba97 | 812 | |
e126ba97 EC |
813 | pci_set_drvdata(dev->pdev, dev); |
814 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
815 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
816 | ||
817 | mutex_init(&priv->pgdir_mutex); | |
818 | INIT_LIST_HEAD(&priv->pgdir_list); | |
819 | spin_lock_init(&priv->mkey_lock); | |
820 | ||
311c7c71 SM |
821 | mutex_init(&priv->alloc_mutex); |
822 | ||
823 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
824 | ||
e126ba97 EC |
825 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
826 | if (!priv->dbg_root) | |
827 | return -ENOMEM; | |
828 | ||
89d44f0a | 829 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 830 | if (err) { |
1a91de28 | 831 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
832 | goto err_dbg; |
833 | } | |
834 | ||
835 | err = request_bar(pdev); | |
836 | if (err) { | |
1a91de28 | 837 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
838 | goto err_disable; |
839 | } | |
840 | ||
841 | pci_set_master(pdev); | |
842 | ||
843 | err = set_dma_caps(pdev); | |
844 | if (err) { | |
845 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
846 | goto err_clr_master; | |
847 | } | |
848 | ||
849 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
850 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
851 | if (!dev->iseg) { | |
852 | err = -ENOMEM; | |
853 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
854 | goto err_clr_master; | |
855 | } | |
a31208b1 MD |
856 | |
857 | return 0; | |
858 | ||
859 | err_clr_master: | |
860 | pci_clear_master(dev->pdev); | |
861 | release_bar(dev->pdev); | |
862 | err_disable: | |
89d44f0a | 863 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
864 | |
865 | err_dbg: | |
866 | debugfs_remove(priv->dbg_root); | |
867 | return err; | |
868 | } | |
869 | ||
870 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
871 | { | |
872 | iounmap(dev->iseg); | |
873 | pci_clear_master(dev->pdev); | |
874 | release_bar(dev->pdev); | |
89d44f0a | 875 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
876 | debugfs_remove(priv->dbg_root); |
877 | } | |
878 | ||
59211bd3 MHY |
879 | static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
880 | { | |
881 | struct pci_dev *pdev = dev->pdev; | |
882 | int err; | |
883 | ||
59211bd3 MHY |
884 | err = mlx5_query_board_id(dev); |
885 | if (err) { | |
886 | dev_err(&pdev->dev, "query board id failed\n"); | |
887 | goto out; | |
888 | } | |
889 | ||
890 | err = mlx5_eq_init(dev); | |
891 | if (err) { | |
892 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
893 | goto out; | |
894 | } | |
895 | ||
896 | MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); | |
897 | ||
898 | err = mlx5_init_cq_table(dev); | |
899 | if (err) { | |
900 | dev_err(&pdev->dev, "failed to initialize cq table\n"); | |
901 | goto err_eq_cleanup; | |
902 | } | |
903 | ||
904 | mlx5_init_qp_table(dev); | |
905 | ||
906 | mlx5_init_srq_table(dev); | |
907 | ||
908 | mlx5_init_mkey_table(dev); | |
909 | ||
910 | err = mlx5_init_rl_table(dev); | |
911 | if (err) { | |
912 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
913 | goto err_tables_cleanup; | |
914 | } | |
915 | ||
c2d6e31a MHY |
916 | #ifdef CONFIG_MLX5_CORE_EN |
917 | err = mlx5_eswitch_init(dev); | |
918 | if (err) { | |
919 | dev_err(&pdev->dev, "Failed to init eswitch %d\n", err); | |
920 | goto err_rl_cleanup; | |
921 | } | |
922 | #endif | |
923 | ||
924 | err = mlx5_sriov_init(dev); | |
925 | if (err) { | |
926 | dev_err(&pdev->dev, "Failed to init sriov %d\n", err); | |
927 | goto err_eswitch_cleanup; | |
928 | } | |
929 | ||
59211bd3 MHY |
930 | return 0; |
931 | ||
c2d6e31a MHY |
932 | err_eswitch_cleanup: |
933 | #ifdef CONFIG_MLX5_CORE_EN | |
934 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
935 | ||
936 | err_rl_cleanup: | |
937 | #endif | |
938 | mlx5_cleanup_rl_table(dev); | |
939 | ||
59211bd3 MHY |
940 | err_tables_cleanup: |
941 | mlx5_cleanup_mkey_table(dev); | |
942 | mlx5_cleanup_srq_table(dev); | |
943 | mlx5_cleanup_qp_table(dev); | |
944 | mlx5_cleanup_cq_table(dev); | |
945 | ||
946 | err_eq_cleanup: | |
947 | mlx5_eq_cleanup(dev); | |
948 | ||
949 | out: | |
950 | return err; | |
951 | } | |
952 | ||
953 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
954 | { | |
c2d6e31a MHY |
955 | mlx5_sriov_cleanup(dev); |
956 | #ifdef CONFIG_MLX5_CORE_EN | |
957 | mlx5_eswitch_cleanup(dev->priv.eswitch); | |
958 | #endif | |
59211bd3 MHY |
959 | mlx5_cleanup_rl_table(dev); |
960 | mlx5_cleanup_mkey_table(dev); | |
961 | mlx5_cleanup_srq_table(dev); | |
962 | mlx5_cleanup_qp_table(dev); | |
963 | mlx5_cleanup_cq_table(dev); | |
964 | mlx5_eq_cleanup(dev); | |
965 | } | |
966 | ||
967 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |
968 | bool boot) | |
a31208b1 MD |
969 | { |
970 | struct pci_dev *pdev = dev->pdev; | |
971 | int err; | |
972 | ||
89d44f0a | 973 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 974 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
975 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
976 | __func__); | |
977 | goto out; | |
978 | } | |
979 | ||
e126ba97 EC |
980 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
981 | fw_rev_min(dev), fw_rev_sub(dev)); | |
982 | ||
89d44f0a MD |
983 | /* on load removing any previous indication of internal error, device is |
984 | * up | |
985 | */ | |
986 | dev->state = MLX5_DEVICE_STATE_UP; | |
987 | ||
e126ba97 EC |
988 | err = mlx5_cmd_init(dev); |
989 | if (err) { | |
990 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 991 | goto out_err; |
e126ba97 EC |
992 | } |
993 | ||
e3297246 EC |
994 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
995 | if (err) { | |
996 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
997 | FW_INIT_TIMEOUT_MILI); | |
998 | goto out_err; | |
999 | } | |
1000 | ||
0b107106 | 1001 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
1002 | if (err) { |
1003 | dev_err(&pdev->dev, "enable hca failed\n"); | |
59211bd3 | 1004 | goto err_cmd_cleanup; |
cd23b14b EC |
1005 | } |
1006 | ||
f62b8bb8 AV |
1007 | err = mlx5_core_set_issi(dev); |
1008 | if (err) { | |
1009 | dev_err(&pdev->dev, "failed to set issi\n"); | |
1010 | goto err_disable_hca; | |
1011 | } | |
f62b8bb8 | 1012 | |
cd23b14b EC |
1013 | err = mlx5_satisfy_startup_pages(dev, 1); |
1014 | if (err) { | |
1015 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
1016 | goto err_disable_hca; | |
1017 | } | |
1018 | ||
e126ba97 EC |
1019 | err = set_hca_ctrl(dev); |
1020 | if (err) { | |
1021 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 1022 | goto reclaim_boot_pages; |
e126ba97 EC |
1023 | } |
1024 | ||
1025 | err = handle_hca_cap(dev); | |
1026 | if (err) { | |
1027 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 1028 | goto reclaim_boot_pages; |
e126ba97 EC |
1029 | } |
1030 | ||
f91e6d89 EBE |
1031 | err = handle_hca_cap_atomic(dev); |
1032 | if (err) { | |
1033 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
1034 | goto reclaim_boot_pages; | |
e126ba97 EC |
1035 | } |
1036 | ||
cd23b14b | 1037 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1038 | if (err) { |
cd23b14b EC |
1039 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1040 | goto reclaim_boot_pages; | |
e126ba97 EC |
1041 | } |
1042 | ||
1043 | err = mlx5_pagealloc_start(dev); | |
1044 | if (err) { | |
1045 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1046 | goto reclaim_boot_pages; |
e126ba97 EC |
1047 | } |
1048 | ||
1049 | err = mlx5_cmd_init_hca(dev); | |
1050 | if (err) { | |
1051 | dev_err(&pdev->dev, "init hca failed\n"); | |
1052 | goto err_pagealloc_stop; | |
1053 | } | |
1054 | ||
012e50e1 HN |
1055 | mlx5_set_driver_version(dev); |
1056 | ||
e126ba97 EC |
1057 | mlx5_start_health_poll(dev); |
1058 | ||
bba1574c DJ |
1059 | err = mlx5_query_hca_caps(dev); |
1060 | if (err) { | |
1061 | dev_err(&pdev->dev, "query hca failed\n"); | |
1062 | goto err_stop_poll; | |
1063 | } | |
1064 | ||
59211bd3 MHY |
1065 | if (boot && mlx5_init_once(dev, priv)) { |
1066 | dev_err(&pdev->dev, "sw objs init failed\n"); | |
e126ba97 EC |
1067 | goto err_stop_poll; |
1068 | } | |
1069 | ||
1070 | err = mlx5_enable_msix(dev); | |
1071 | if (err) { | |
1072 | dev_err(&pdev->dev, "enable msix failed\n"); | |
59211bd3 | 1073 | goto err_cleanup_once; |
e126ba97 EC |
1074 | } |
1075 | ||
1076 | err = mlx5_alloc_uuars(dev, &priv->uuari); | |
1077 | if (err) { | |
1078 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); | |
59211bd3 | 1079 | goto err_disable_msix; |
e126ba97 EC |
1080 | } |
1081 | ||
1082 | err = mlx5_start_eqs(dev); | |
1083 | if (err) { | |
1084 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
1085 | goto err_free_uar; | |
1086 | } | |
1087 | ||
233d05d2 SM |
1088 | err = alloc_comp_eqs(dev); |
1089 | if (err) { | |
1090 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1091 | goto err_stop_eqs; | |
1092 | } | |
1093 | ||
db058a18 | 1094 | err = mlx5_irq_set_affinity_hints(dev); |
59211bd3 | 1095 | if (err) { |
db058a18 | 1096 | dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); |
59211bd3 MHY |
1097 | goto err_affinity_hints; |
1098 | } | |
e126ba97 | 1099 | |
86d722ad MG |
1100 | err = mlx5_init_fs(dev); |
1101 | if (err) { | |
1102 | dev_err(&pdev->dev, "Failed to init flow steering\n"); | |
1103 | goto err_fs; | |
1104 | } | |
1466cc5b | 1105 | |
073bb189 | 1106 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1107 | mlx5_eswitch_attach(dev->priv.eswitch); |
073bb189 SM |
1108 | #endif |
1109 | ||
c2d6e31a | 1110 | err = mlx5_sriov_attach(dev); |
fc50db98 EC |
1111 | if (err) { |
1112 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1113 | goto err_sriov; | |
1114 | } | |
1115 | ||
737a234b MHY |
1116 | if (mlx5_device_registered(dev)) { |
1117 | mlx5_attach_device(dev); | |
1118 | } else { | |
1119 | err = mlx5_register_device(dev); | |
1120 | if (err) { | |
1121 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1122 | goto err_reg_dev; | |
1123 | } | |
a31208b1 MD |
1124 | } |
1125 | ||
5fc7197d MD |
1126 | clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); |
1127 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
89d44f0a MD |
1128 | out: |
1129 | mutex_unlock(&dev->intf_state_mutex); | |
1130 | ||
e126ba97 EC |
1131 | return 0; |
1132 | ||
59211bd3 | 1133 | err_reg_dev: |
c2d6e31a | 1134 | mlx5_sriov_detach(dev); |
fc50db98 | 1135 | |
59211bd3 | 1136 | err_sriov: |
073bb189 | 1137 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1138 | mlx5_eswitch_detach(dev->priv.eswitch); |
073bb189 | 1139 | #endif |
86d722ad | 1140 | mlx5_cleanup_fs(dev); |
59211bd3 | 1141 | |
86d722ad | 1142 | err_fs: |
a31208b1 | 1143 | mlx5_irq_clear_affinity_hints(dev); |
59211bd3 MHY |
1144 | |
1145 | err_affinity_hints: | |
db058a18 SM |
1146 | free_comp_eqs(dev); |
1147 | ||
233d05d2 SM |
1148 | err_stop_eqs: |
1149 | mlx5_stop_eqs(dev); | |
1150 | ||
e126ba97 EC |
1151 | err_free_uar: |
1152 | mlx5_free_uuars(dev, &priv->uuari); | |
1153 | ||
59211bd3 | 1154 | err_disable_msix: |
e126ba97 EC |
1155 | mlx5_disable_msix(dev); |
1156 | ||
59211bd3 MHY |
1157 | err_cleanup_once: |
1158 | if (boot) | |
1159 | mlx5_cleanup_once(dev); | |
1160 | ||
e126ba97 EC |
1161 | err_stop_poll: |
1162 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1163 | if (mlx5_cmd_teardown_hca(dev)) { |
1164 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1165 | goto out_err; |
1bde6e30 | 1166 | } |
e126ba97 EC |
1167 | |
1168 | err_pagealloc_stop: | |
1169 | mlx5_pagealloc_stop(dev); | |
1170 | ||
cd23b14b | 1171 | reclaim_boot_pages: |
e126ba97 EC |
1172 | mlx5_reclaim_startup_pages(dev); |
1173 | ||
cd23b14b | 1174 | err_disable_hca: |
0b107106 | 1175 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1176 | |
59211bd3 | 1177 | err_cmd_cleanup: |
e126ba97 EC |
1178 | mlx5_cmd_cleanup(dev); |
1179 | ||
89d44f0a MD |
1180 | out_err: |
1181 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1182 | mutex_unlock(&dev->intf_state_mutex); | |
1183 | ||
e126ba97 EC |
1184 | return err; |
1185 | } | |
e126ba97 | 1186 | |
59211bd3 MHY |
1187 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, |
1188 | bool cleanup) | |
e126ba97 | 1189 | { |
89d44f0a | 1190 | int err = 0; |
e126ba97 | 1191 | |
89d44f0a | 1192 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1193 | if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) { |
89d44f0a MD |
1194 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1195 | __func__); | |
59211bd3 MHY |
1196 | if (cleanup) |
1197 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1198 | goto out; |
1199 | } | |
6b6adee3 | 1200 | |
737a234b MHY |
1201 | if (mlx5_device_registered(dev)) |
1202 | mlx5_detach_device(dev); | |
1203 | ||
c2d6e31a | 1204 | mlx5_sriov_detach(dev); |
073bb189 | 1205 | #ifdef CONFIG_MLX5_CORE_EN |
c2d6e31a | 1206 | mlx5_eswitch_detach(dev->priv.eswitch); |
073bb189 | 1207 | #endif |
86d722ad | 1208 | mlx5_cleanup_fs(dev); |
db058a18 | 1209 | mlx5_irq_clear_affinity_hints(dev); |
233d05d2 | 1210 | free_comp_eqs(dev); |
e126ba97 EC |
1211 | mlx5_stop_eqs(dev); |
1212 | mlx5_free_uuars(dev, &priv->uuari); | |
e126ba97 | 1213 | mlx5_disable_msix(dev); |
59211bd3 MHY |
1214 | if (cleanup) |
1215 | mlx5_cleanup_once(dev); | |
e126ba97 | 1216 | mlx5_stop_health_poll(dev); |
ac6ea6e8 EC |
1217 | err = mlx5_cmd_teardown_hca(dev); |
1218 | if (err) { | |
1bde6e30 | 1219 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1220 | goto out; |
1bde6e30 | 1221 | } |
e126ba97 EC |
1222 | mlx5_pagealloc_stop(dev); |
1223 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1224 | mlx5_core_disable_hca(dev, 0); |
e126ba97 | 1225 | mlx5_cmd_cleanup(dev); |
9603b61d | 1226 | |
ac6ea6e8 | 1227 | out: |
5fc7197d MD |
1228 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
1229 | set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state); | |
89d44f0a | 1230 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1231 | return err; |
9603b61d | 1232 | } |
64613d94 | 1233 | |
9603b61d JM |
1234 | struct mlx5_core_event_handler { |
1235 | void (*event)(struct mlx5_core_dev *dev, | |
1236 | enum mlx5_dev_event event, | |
1237 | void *data); | |
1238 | }; | |
1239 | ||
feae9087 OG |
1240 | static const struct devlink_ops mlx5_devlink_ops = { |
1241 | #ifdef CONFIG_MLX5_CORE_EN | |
1242 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, | |
1243 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
bffaa916 RD |
1244 | .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, |
1245 | .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, | |
feae9087 OG |
1246 | #endif |
1247 | }; | |
f66f049f | 1248 | |
59211bd3 | 1249 | #define MLX5_IB_MOD "mlx5_ib" |
9603b61d JM |
1250 | static int init_one(struct pci_dev *pdev, |
1251 | const struct pci_device_id *id) | |
1252 | { | |
1253 | struct mlx5_core_dev *dev; | |
feae9087 | 1254 | struct devlink *devlink; |
9603b61d JM |
1255 | struct mlx5_priv *priv; |
1256 | int err; | |
1257 | ||
feae9087 OG |
1258 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1259 | if (!devlink) { | |
9603b61d JM |
1260 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1261 | return -ENOMEM; | |
1262 | } | |
feae9087 OG |
1263 | |
1264 | dev = devlink_priv(devlink); | |
9603b61d | 1265 | priv = &dev->priv; |
fc50db98 | 1266 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1267 | |
1268 | pci_set_drvdata(pdev, dev); | |
1269 | ||
0e97a340 HN |
1270 | dev->pdev = pdev; |
1271 | dev->event = mlx5_core_event; | |
9603b61d | 1272 | dev->profile = &profile[prof_sel]; |
9603b61d | 1273 | |
364d1798 EC |
1274 | INIT_LIST_HEAD(&priv->ctx_list); |
1275 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1276 | mutex_init(&dev->pci_status_mutex); |
1277 | mutex_init(&dev->intf_state_mutex); | |
a31208b1 | 1278 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1279 | if (err) { |
a31208b1 MD |
1280 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
1281 | goto clean_dev; | |
9603b61d JM |
1282 | } |
1283 | ||
ac6ea6e8 EC |
1284 | err = mlx5_health_init(dev); |
1285 | if (err) { | |
1286 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1287 | goto close_pci; | |
1288 | } | |
1289 | ||
59211bd3 MHY |
1290 | mlx5_pagealloc_init(dev); |
1291 | ||
1292 | err = mlx5_load_one(dev, priv, true); | |
9603b61d | 1293 | if (err) { |
a31208b1 | 1294 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1295 | goto clean_health; |
9603b61d | 1296 | } |
59211bd3 | 1297 | |
737a234b MHY |
1298 | err = request_module_nowait(MLX5_IB_MOD); |
1299 | if (err) | |
1300 | pr_info("failed request module on %s\n", MLX5_IB_MOD); | |
9603b61d | 1301 | |
feae9087 OG |
1302 | err = devlink_register(devlink, &pdev->dev); |
1303 | if (err) | |
1304 | goto clean_load; | |
1305 | ||
9603b61d JM |
1306 | return 0; |
1307 | ||
feae9087 | 1308 | clean_load: |
59211bd3 | 1309 | mlx5_unload_one(dev, priv, true); |
ac6ea6e8 | 1310 | clean_health: |
59211bd3 | 1311 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1312 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1313 | close_pci: |
1314 | mlx5_pci_close(dev, priv); | |
1315 | clean_dev: | |
1316 | pci_set_drvdata(pdev, NULL); | |
feae9087 | 1317 | devlink_free(devlink); |
a31208b1 | 1318 | |
9603b61d JM |
1319 | return err; |
1320 | } | |
a31208b1 | 1321 | |
9603b61d JM |
1322 | static void remove_one(struct pci_dev *pdev) |
1323 | { | |
1324 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1325 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1326 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1327 | |
feae9087 | 1328 | devlink_unregister(devlink); |
737a234b MHY |
1329 | mlx5_unregister_device(dev); |
1330 | ||
59211bd3 | 1331 | if (mlx5_unload_one(dev, priv, true)) { |
a31208b1 | 1332 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); |
ac6ea6e8 | 1333 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1334 | return; |
1335 | } | |
737a234b | 1336 | |
59211bd3 | 1337 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1338 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1339 | mlx5_pci_close(dev, priv); |
1340 | pci_set_drvdata(pdev, NULL); | |
feae9087 | 1341 | devlink_free(devlink); |
9603b61d JM |
1342 | } |
1343 | ||
89d44f0a MD |
1344 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1345 | pci_channel_state_t state) | |
1346 | { | |
1347 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1348 | struct mlx5_priv *priv = &dev->priv; | |
1349 | ||
1350 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
04c0c1ab | 1351 | |
89d44f0a | 1352 | mlx5_enter_error_state(dev); |
59211bd3 | 1353 | mlx5_unload_one(dev, priv, false); |
05ac2c0b MHY |
1354 | /* In case of kernel call save the pci state and drain health wq */ |
1355 | if (state) { | |
1356 | pci_save_state(pdev); | |
1357 | mlx5_drain_health_wq(dev); | |
1358 | mlx5_pci_disable_device(dev); | |
1359 | } | |
1360 | ||
89d44f0a MD |
1361 | return state == pci_channel_io_perm_failure ? |
1362 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1363 | } | |
1364 | ||
d57847dc DJ |
1365 | /* wait for the device to show vital signs by waiting |
1366 | * for the health counter to start counting. | |
89d44f0a | 1367 | */ |
d57847dc | 1368 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1369 | { |
1370 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1371 | struct mlx5_core_health *health = &dev->priv.health; | |
1372 | const int niter = 100; | |
d57847dc | 1373 | u32 last_count = 0; |
89d44f0a | 1374 | u32 count; |
89d44f0a MD |
1375 | int i; |
1376 | ||
89d44f0a MD |
1377 | for (i = 0; i < niter; i++) { |
1378 | count = ioread32be(health->health_counter); | |
1379 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1380 | if (last_count && last_count != count) { |
1381 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1382 | return 0; | |
1383 | } | |
1384 | last_count = count; | |
89d44f0a MD |
1385 | } |
1386 | msleep(50); | |
1387 | } | |
1388 | ||
d57847dc | 1389 | return -ETIMEDOUT; |
89d44f0a MD |
1390 | } |
1391 | ||
1061c90f | 1392 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1393 | { |
1394 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1395 | int err; |
1396 | ||
1397 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1398 | ||
1061c90f | 1399 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1400 | if (err) { |
1061c90f MHY |
1401 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" |
1402 | , __func__, err); | |
1403 | return PCI_ERS_RESULT_DISCONNECT; | |
1404 | } | |
1405 | ||
1406 | pci_set_master(pdev); | |
1407 | pci_restore_state(pdev); | |
1408 | ||
1409 | if (wait_vital(pdev)) { | |
d57847dc | 1410 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1411 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1412 | } |
89d44f0a | 1413 | |
1061c90f MHY |
1414 | return PCI_ERS_RESULT_RECOVERED; |
1415 | } | |
1416 | ||
1061c90f MHY |
1417 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1418 | { | |
1419 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1420 | struct mlx5_priv *priv = &dev->priv; | |
1421 | int err; | |
1422 | ||
1423 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1424 | ||
59211bd3 | 1425 | err = mlx5_load_one(dev, priv, false); |
89d44f0a MD |
1426 | if (err) |
1427 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1428 | , __func__, err); | |
1429 | else | |
1430 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1431 | } | |
1432 | ||
1433 | static const struct pci_error_handlers mlx5_err_handler = { | |
1434 | .error_detected = mlx5_pci_err_detected, | |
1435 | .slot_reset = mlx5_pci_slot_reset, | |
1436 | .resume = mlx5_pci_resume | |
1437 | }; | |
1438 | ||
5fc7197d MD |
1439 | static void shutdown(struct pci_dev *pdev) |
1440 | { | |
1441 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1442 | struct mlx5_priv *priv = &dev->priv; | |
1443 | ||
1444 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
1445 | /* Notify mlx5 clients that the kernel is being shut down */ | |
1446 | set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state); | |
59211bd3 | 1447 | mlx5_unload_one(dev, priv, false); |
5fc7197d MD |
1448 | mlx5_pci_disable_device(dev); |
1449 | } | |
1450 | ||
9603b61d | 1451 | static const struct pci_device_id mlx5_core_pci_table[] = { |
fc50db98 EC |
1452 | { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */ |
1453 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ | |
1454 | { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */ | |
1455 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ | |
1456 | { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */ | |
1457 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ | |
7092fe86 | 1458 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1459 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
7092fe86 | 1460 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5, PCIe 4.0 */ |
86490d9a | 1461 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5, PCIe 4.0 VF */ |
9603b61d JM |
1462 | { 0, } |
1463 | }; | |
1464 | ||
1465 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1466 | ||
04c0c1ab MHY |
1467 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1468 | { | |
1469 | mlx5_pci_err_detected(dev->pdev, 0); | |
1470 | } | |
1471 | ||
1472 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1473 | { | |
1474 | mlx5_pci_disable_device(dev); | |
1475 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1476 | mlx5_pci_resume(dev->pdev); | |
1477 | } | |
1478 | ||
9603b61d JM |
1479 | static struct pci_driver mlx5_core_driver = { |
1480 | .name = DRIVER_NAME, | |
1481 | .id_table = mlx5_core_pci_table, | |
1482 | .probe = init_one, | |
89d44f0a | 1483 | .remove = remove_one, |
5fc7197d | 1484 | .shutdown = shutdown, |
fc50db98 EC |
1485 | .err_handler = &mlx5_err_handler, |
1486 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1487 | }; |
e126ba97 | 1488 | |
f663ad98 KH |
1489 | static void mlx5_core_verify_params(void) |
1490 | { | |
1491 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1492 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1493 | prof_sel, | |
1494 | ARRAY_SIZE(profile) - 1, | |
1495 | MLX5_DEFAULT_PROF); | |
1496 | prof_sel = MLX5_DEFAULT_PROF; | |
1497 | } | |
1498 | } | |
1499 | ||
e126ba97 EC |
1500 | static int __init init(void) |
1501 | { | |
1502 | int err; | |
1503 | ||
f663ad98 | 1504 | mlx5_core_verify_params(); |
e126ba97 | 1505 | mlx5_register_debugfs(); |
e126ba97 | 1506 | |
9603b61d JM |
1507 | err = pci_register_driver(&mlx5_core_driver); |
1508 | if (err) | |
ac6ea6e8 | 1509 | goto err_debug; |
9603b61d | 1510 | |
f62b8bb8 AV |
1511 | #ifdef CONFIG_MLX5_CORE_EN |
1512 | mlx5e_init(); | |
1513 | #endif | |
1514 | ||
e126ba97 EC |
1515 | return 0; |
1516 | ||
e126ba97 EC |
1517 | err_debug: |
1518 | mlx5_unregister_debugfs(); | |
1519 | return err; | |
1520 | } | |
1521 | ||
1522 | static void __exit cleanup(void) | |
1523 | { | |
f62b8bb8 AV |
1524 | #ifdef CONFIG_MLX5_CORE_EN |
1525 | mlx5e_cleanup(); | |
1526 | #endif | |
9603b61d | 1527 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1528 | mlx5_unregister_debugfs(); |
1529 | } | |
1530 | ||
1531 | module_init(init); | |
1532 | module_exit(cleanup); |