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mlx5: Move pci device handling from mlx5_ib to mlx5_core
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/mlx5/driver.h>
42#include <linux/mlx5/cq.h>
43#include <linux/mlx5/qp.h>
44#include <linux/mlx5/srq.h>
45#include <linux/debugfs.h>
46#include "mlx5_core.h"
47
48#define DRIVER_NAME "mlx5_core"
169a1d85
AV		 49#define DRIVER_VERSION "2.2-1"
50#define DRIVER_RELDATE "Feb 2014"
e126ba97
EC		 51
52MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
53MODULE_DESCRIPTION("Mellanox ConnectX-IB HCA core library");
54MODULE_LICENSE("Dual BSD/GPL");
55MODULE_VERSION(DRIVER_VERSION);
56
57int mlx5_core_debug_mask;
58module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
59MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
60
9603b61d
JM		 61#define MLX5_DEFAULT_PROF 2
62static int prof_sel = MLX5_DEFAULT_PROF;
63module_param_named(prof_sel, prof_sel, int, 0444);
64MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
65
e126ba97 66struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 67static LIST_HEAD(intf_list);
68static LIST_HEAD(dev_list);
69static DEFINE_MUTEX(intf_mutex);
70
71struct mlx5_device_context {
72 struct list_head list;
73 struct mlx5_interface *intf;
74 void *context;
75};
76
77static struct mlx5_profile profile[] = {
78 [0] = {
79 .mask = 0,
80 },
81 [1] = {
82 .mask = MLX5_PROF_MASK_QP_SIZE,
83 .log_max_qp = 12,
84 },
85 [2] = {
86 .mask = MLX5_PROF_MASK_QP_SIZE |
87 MLX5_PROF_MASK_MR_CACHE,
88 .log_max_qp = 17,
89 .mr_cache[0] = {
90 .size = 500,
91 .limit = 250
92 },
93 .mr_cache[1] = {
94 .size = 500,
95 .limit = 250
96 },
97 .mr_cache[2] = {
98 .size = 500,
99 .limit = 250
100 },
101 .mr_cache[3] = {
102 .size = 500,
103 .limit = 250
104 },
105 .mr_cache[4] = {
106 .size = 500,
107 .limit = 250
108 },
109 .mr_cache[5] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[6] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[7] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[8] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[9] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[10] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[11] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[12] = {
138 .size = 64,
139 .limit = 32
140 },
141 .mr_cache[13] = {
142 .size = 32,
143 .limit = 16
144 },
145 .mr_cache[14] = {
146 .size = 16,
147 .limit = 8
148 },
149 .mr_cache[15] = {
150 .size = 8,
151 .limit = 4
152 },
153 },
154};
e126ba97
EC		 155
156static int set_dma_caps(struct pci_dev *pdev)
157{
158 int err;
159
160 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
161 if (err) {
1a91de28 162 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 163 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
164 if (err) {
1a91de28 165 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 166 return err;
167 }
168 }
169
170 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
171 if (err) {
172 dev_warn(&pdev->dev,
1a91de28 173 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
175 if (err) {
176 dev_err(&pdev->dev,
1a91de28 177 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 178 return err;
179 }
180 }
181
182 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
183 return err;
184}
185
186static int request_bar(struct pci_dev *pdev)
187{
188 int err = 0;
189
190 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 191 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 192 return -ENODEV;
193 }
194
195 err = pci_request_regions(pdev, DRIVER_NAME);
196 if (err)
197 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
198
199 return err;
200}
201
202static void release_bar(struct pci_dev *pdev)
203{
204 pci_release_regions(pdev);
205}
206
207static int mlx5_enable_msix(struct mlx5_core_dev *dev)
208{
209 struct mlx5_eq_table *table = &dev->priv.eq_table;
210 int num_eqs = 1 << dev->caps.log_max_eq;
211 int nvec;
e126ba97
EC		 212 int i;
213
214 nvec = dev->caps.num_ports * num_online_cpus() + MLX5_EQ_VEC_COMP_BASE;
215 nvec = min_t(int, nvec, num_eqs);
216 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
217 return -ENOMEM;
218
219 table->msix_arr = kzalloc(nvec * sizeof(*table->msix_arr), GFP_KERNEL);
220 if (!table->msix_arr)
221 return -ENOMEM;
222
223 for (i = 0; i < nvec; i++)
224 table->msix_arr[i].entry = i;
225
f3c9407b
AG		 226 nvec = pci_enable_msix_range(dev->pdev, table->msix_arr,
227 MLX5_EQ_VEC_COMP_BASE, nvec);
228 if (nvec < 0)
229 return nvec;
e126ba97 230
f3c9407b 231 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 232
233 return 0;
234}
235
236static void mlx5_disable_msix(struct mlx5_core_dev *dev)
237{
238 struct mlx5_eq_table *table = &dev->priv.eq_table;
239
240 pci_disable_msix(dev->pdev);
241 kfree(table->msix_arr);
242}
243
244struct mlx5_reg_host_endianess {
245 u8 he;
246 u8 rsvd[15];
247};
248
87b8de49
EC		 249
250#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
251
252enum {
253 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
254 CAP_MASK(MLX5_CAP_OFF_DCT, 1),
255};
256
257/* selectively copy writable fields clearing any reserved area
258 */
259static void copy_rw_fields(struct mlx5_hca_cap *to, struct mlx5_hca_cap *from)
260{
261 u64 v64;
262
263 to->log_max_qp = from->log_max_qp & 0x1f;
264 to->log_max_ra_req_dc = from->log_max_ra_req_dc & 0x3f;
265 to->log_max_ra_res_dc = from->log_max_ra_res_dc & 0x3f;
266 to->log_max_ra_req_qp = from->log_max_ra_req_qp & 0x3f;
267 to->log_max_ra_res_qp = from->log_max_ra_res_qp & 0x3f;
268 to->log_max_atomic_size_qp = from->log_max_atomic_size_qp;
269 to->log_max_atomic_size_dc = from->log_max_atomic_size_dc;
270 v64 = be64_to_cpu(from->flags) & MLX5_CAP_BITS_RW_MASK;
271 to->flags = cpu_to_be64(v64);
272}
273
274enum {
275 HCA_CAP_OPMOD_GET_MAX = 0,
276 HCA_CAP_OPMOD_GET_CUR = 1,
277};
278
e126ba97
EC		 279static int handle_hca_cap(struct mlx5_core_dev *dev)
280{
281 struct mlx5_cmd_query_hca_cap_mbox_out *query_out = NULL;
282 struct mlx5_cmd_set_hca_cap_mbox_in *set_ctx = NULL;
283 struct mlx5_cmd_query_hca_cap_mbox_in query_ctx;
284 struct mlx5_cmd_set_hca_cap_mbox_out set_out;
e126ba97 285 u64 flags;
e126ba97
EC		 286 int err;
287
288 memset(&query_ctx, 0, sizeof(query_ctx));
289 query_out = kzalloc(sizeof(*query_out), GFP_KERNEL);
290 if (!query_out)
291 return -ENOMEM;
292
293 set_ctx = kzalloc(sizeof(*set_ctx), GFP_KERNEL);
294 if (!set_ctx) {
295 err = -ENOMEM;
296 goto query_ex;
297 }
298
299 query_ctx.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_HCA_CAP);
87b8de49 300 query_ctx.hdr.opmod = cpu_to_be16(HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 301 err = mlx5_cmd_exec(dev, &query_ctx, sizeof(query_ctx),
302 query_out, sizeof(*query_out));
303 if (err)
304 goto query_ex;
305
306 err = mlx5_cmd_status_to_err(&query_out->hdr);
307 if (err) {
308 mlx5_core_warn(dev, "query hca cap failed, %d\n", err);
309 goto query_ex;
310 }
311
87b8de49 312 copy_rw_fields(&set_ctx->hca_cap, &query_out->hca_cap);
e126ba97 313
e126ba97
EC		 314 if (dev->profile->mask & MLX5_PROF_MASK_QP_SIZE)
315 set_ctx->hca_cap.log_max_qp = dev->profile->log_max_qp;
316
c1868b82
EC		 317 flags = be64_to_cpu(query_out->hca_cap.flags);
318 /* disable checksum */
319 flags &= ~MLX5_DEV_CAP_FLAG_CMDIF_CSUM;
320
321 set_ctx->hca_cap.flags = cpu_to_be64(flags);
e126ba97 322 memset(&set_out, 0, sizeof(set_out));
288dde9f 323 set_ctx->hca_cap.log_uar_page_sz = cpu_to_be16(PAGE_SHIFT - 12);
e126ba97
EC		 324 set_ctx->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_SET_HCA_CAP);
325 err = mlx5_cmd_exec(dev, set_ctx, sizeof(*set_ctx),
326 &set_out, sizeof(set_out));
327 if (err) {
328 mlx5_core_warn(dev, "set hca cap failed, %d\n", err);
329 goto query_ex;
330 }
331
332 err = mlx5_cmd_status_to_err(&set_out.hdr);
333 if (err)
334 goto query_ex;
335
e126ba97
EC		 336query_ex:
337 kfree(query_out);
338 kfree(set_ctx);
339
340 return err;
341}
342
343static int set_hca_ctrl(struct mlx5_core_dev *dev)
344{
345 struct mlx5_reg_host_endianess he_in;
346 struct mlx5_reg_host_endianess he_out;
347 int err;
348
349 memset(&he_in, 0, sizeof(he_in));
350 he_in.he = MLX5_SET_HOST_ENDIANNESS;
351 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
352 &he_out, sizeof(he_out),
353 MLX5_REG_HOST_ENDIANNESS, 0, 1);
354 return err;
355}
356
cd23b14b
EC		 357static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
358{
359 int err;
360 struct mlx5_enable_hca_mbox_in in;
361 struct mlx5_enable_hca_mbox_out out;
362
363 memset(&in, 0, sizeof(in));
364 memset(&out, 0, sizeof(out));
365 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
366 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
367 if (err)
368 return err;
369
370 if (out.hdr.status)
371 return mlx5_cmd_status_to_err(&out.hdr);
372
373 return 0;
374}
375
376static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
377{
378 int err;
379 struct mlx5_disable_hca_mbox_in in;
380 struct mlx5_disable_hca_mbox_out out;
381
382 memset(&in, 0, sizeof(in));
383 memset(&out, 0, sizeof(out));
384 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
385 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
386 if (err)
387 return err;
388
389 if (out.hdr.status)
390 return mlx5_cmd_status_to_err(&out.hdr);
391
392 return 0;
393}
394
9603b61d 395static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 396{
397 struct mlx5_priv *priv = &dev->priv;
398 int err;
399
400 dev->pdev = pdev;
401 pci_set_drvdata(dev->pdev, dev);
402 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
403 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
404
405 mutex_init(&priv->pgdir_mutex);
406 INIT_LIST_HEAD(&priv->pgdir_list);
407 spin_lock_init(&priv->mkey_lock);
408
409 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
410 if (!priv->dbg_root)
411 return -ENOMEM;
412
413 err = pci_enable_device(pdev);
414 if (err) {
1a91de28 415 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 416 goto err_dbg;
417 }
418
419 err = request_bar(pdev);
420 if (err) {
1a91de28 421 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 422 goto err_disable;
423 }
424
425 pci_set_master(pdev);
426
427 err = set_dma_caps(pdev);
428 if (err) {
429 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
430 goto err_clr_master;
431 }
432
433 dev->iseg_base = pci_resource_start(dev->pdev, 0);
434 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
435 if (!dev->iseg) {
436 err = -ENOMEM;
437 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
438 goto err_clr_master;
439 }
440 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
441 fw_rev_min(dev), fw_rev_sub(dev));
442
443 err = mlx5_cmd_init(dev);
444 if (err) {
445 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
446 goto err_unmap;
447 }
448
449 mlx5_pagealloc_init(dev);
cd23b14b
EC		 450
451 err = mlx5_core_enable_hca(dev);
452 if (err) {
453 dev_err(&pdev->dev, "enable hca failed\n");
454 goto err_pagealloc_cleanup;
455 }
456
457 err = mlx5_satisfy_startup_pages(dev, 1);
458 if (err) {
459 dev_err(&pdev->dev, "failed to allocate boot pages\n");
460 goto err_disable_hca;
461 }
462
e126ba97
EC		 463 err = set_hca_ctrl(dev);
464 if (err) {
465 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 466 goto reclaim_boot_pages;
e126ba97
EC		 467 }
468
469 err = handle_hca_cap(dev);
470 if (err) {
471 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 472 goto reclaim_boot_pages;
e126ba97
EC		 473 }
474
cd23b14b 475 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 476 if (err) {
cd23b14b
EC		 477 dev_err(&pdev->dev, "failed to allocate init pages\n");
478 goto reclaim_boot_pages;
e126ba97
EC		 479 }
480
481 err = mlx5_pagealloc_start(dev);
482 if (err) {
483 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 484 goto reclaim_boot_pages;
e126ba97
EC		 485 }
486
487 err = mlx5_cmd_init_hca(dev);
488 if (err) {
489 dev_err(&pdev->dev, "init hca failed\n");
490 goto err_pagealloc_stop;
491 }
492
493 mlx5_start_health_poll(dev);
494
495 err = mlx5_cmd_query_hca_cap(dev, &dev->caps);
496 if (err) {
497 dev_err(&pdev->dev, "query hca failed\n");
498 goto err_stop_poll;
499 }
500
501 err = mlx5_cmd_query_adapter(dev);
502 if (err) {
503 dev_err(&pdev->dev, "query adapter failed\n");
504 goto err_stop_poll;
505 }
506
507 err = mlx5_enable_msix(dev);
508 if (err) {
509 dev_err(&pdev->dev, "enable msix failed\n");
510 goto err_stop_poll;
511 }
512
513 err = mlx5_eq_init(dev);
514 if (err) {
515 dev_err(&pdev->dev, "failed to initialize eq\n");
516 goto disable_msix;
517 }
518
519 err = mlx5_alloc_uuars(dev, &priv->uuari);
520 if (err) {
521 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
522 goto err_eq_cleanup;
523 }
524
525 err = mlx5_start_eqs(dev);
526 if (err) {
527 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
528 goto err_free_uar;
529 }
530
531 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
532
533 mlx5_init_cq_table(dev);
534 mlx5_init_qp_table(dev);
535 mlx5_init_srq_table(dev);
3bcdb17a 536 mlx5_init_mr_table(dev);
e126ba97
EC		 537
538 return 0;
539
540err_free_uar:
541 mlx5_free_uuars(dev, &priv->uuari);
542
543err_eq_cleanup:
544 mlx5_eq_cleanup(dev);
545
546disable_msix:
547 mlx5_disable_msix(dev);
548
549err_stop_poll:
550 mlx5_stop_health_poll(dev);
1bde6e30
EC		 551 if (mlx5_cmd_teardown_hca(dev)) {
552 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
553 return err;
554 }
e126ba97
EC		 555
556err_pagealloc_stop:
557 mlx5_pagealloc_stop(dev);
558
cd23b14b 559reclaim_boot_pages:
e126ba97
EC		 560 mlx5_reclaim_startup_pages(dev);
561
cd23b14b
EC		 562err_disable_hca:
563 mlx5_core_disable_hca(dev);
564
e126ba97
EC		 565err_pagealloc_cleanup:
566 mlx5_pagealloc_cleanup(dev);
567 mlx5_cmd_cleanup(dev);
568
569err_unmap:
570 iounmap(dev->iseg);
571
572err_clr_master:
573 pci_clear_master(dev->pdev);
574 release_bar(dev->pdev);
575
576err_disable:
577 pci_disable_device(dev->pdev);
578
579err_dbg:
580 debugfs_remove(priv->dbg_root);
581 return err;
582}
583EXPORT_SYMBOL(mlx5_dev_init);
584
9603b61d 585static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 586{
587 struct mlx5_priv *priv = &dev->priv;
588
589 mlx5_cleanup_srq_table(dev);
590 mlx5_cleanup_qp_table(dev);
591 mlx5_cleanup_cq_table(dev);
592 mlx5_stop_eqs(dev);
593 mlx5_free_uuars(dev, &priv->uuari);
594 mlx5_eq_cleanup(dev);
595 mlx5_disable_msix(dev);
596 mlx5_stop_health_poll(dev);
1bde6e30
EC		 597 if (mlx5_cmd_teardown_hca(dev)) {
598 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
599 return;
600 }
e126ba97
EC		 601 mlx5_pagealloc_stop(dev);
602 mlx5_reclaim_startup_pages(dev);
cd23b14b 603 mlx5_core_disable_hca(dev);
e126ba97
EC		 604 mlx5_pagealloc_cleanup(dev);
605 mlx5_cmd_cleanup(dev);
606 iounmap(dev->iseg);
607 pci_clear_master(dev->pdev);
608 release_bar(dev->pdev);
609 pci_disable_device(dev->pdev);
610 debugfs_remove(priv->dbg_root);
611}
9603b61d
JM		 612
613static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
614{
615 struct mlx5_device_context *dev_ctx;
616 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
617
618 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
619 if (!dev_ctx) {
620 pr_warn("mlx5_add_device: alloc context failed\n");
621 return;
622 }
623
624 dev_ctx->intf = intf;
625 dev_ctx->context = intf->add(dev);
626
627 if (dev_ctx->context) {
628 spin_lock_irq(&priv->ctx_lock);
629 list_add_tail(&dev_ctx->list, &priv->ctx_list);
630 spin_unlock_irq(&priv->ctx_lock);
631 } else {
632 kfree(dev_ctx);
633 }
634}
635
636static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
637{
638 struct mlx5_device_context *dev_ctx;
639 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
640
641 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
642 if (dev_ctx->intf == intf) {
643 spin_lock_irq(&priv->ctx_lock);
644 list_del(&dev_ctx->list);
645 spin_unlock_irq(&priv->ctx_lock);
646
647 intf->remove(dev, dev_ctx->context);
648 kfree(dev_ctx);
649 return;
650 }
651}
652static int mlx5_register_device(struct mlx5_core_dev *dev)
653{
654 struct mlx5_priv *priv = &dev->priv;
655 struct mlx5_interface *intf;
656
657 mutex_lock(&intf_mutex);
658 list_add_tail(&priv->dev_list, &dev_list);
659 list_for_each_entry(intf, &intf_list, list)
660 mlx5_add_device(intf, priv);
661 mutex_unlock(&intf_mutex);
662
663 return 0;
664}
665static void mlx5_unregister_device(struct mlx5_core_dev *dev)
666{
667 struct mlx5_priv *priv = &dev->priv;
668 struct mlx5_interface *intf;
669
670 mutex_lock(&intf_mutex);
671 list_for_each_entry(intf, &intf_list, list)
672 mlx5_remove_device(intf, priv);
673 list_del(&priv->dev_list);
674 mutex_unlock(&intf_mutex);
675}
676
677int mlx5_register_interface(struct mlx5_interface *intf)
678{
679 struct mlx5_priv *priv;
680
681 if (!intf->add || !intf->remove)
682 return -EINVAL;
683
684 mutex_lock(&intf_mutex);
685 list_add_tail(&intf->list, &intf_list);
686 list_for_each_entry(priv, &dev_list, dev_list)
687 mlx5_add_device(intf, priv);
688 mutex_unlock(&intf_mutex);
689
690 return 0;
691}
692EXPORT_SYMBOL(mlx5_register_interface);
693
694void mlx5_unregister_interface(struct mlx5_interface *intf)
695{
696 struct mlx5_priv *priv;
697
698 mutex_lock(&intf_mutex);
699 list_for_each_entry(priv, &dev_list, dev_list)
700 mlx5_remove_device(intf, priv);
701 list_del(&intf->list);
702 mutex_unlock(&intf_mutex);
703}
704EXPORT_SYMBOL(mlx5_unregister_interface);
705
706static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
707 void *data)
708{
709 struct mlx5_priv *priv = &dev->priv;
710 struct mlx5_device_context *dev_ctx;
711 unsigned long flags;
712
713 spin_lock_irqsave(&priv->ctx_lock, flags);
714
715 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
716 if (dev_ctx->intf->event)
717 dev_ctx->intf->event(dev, dev_ctx->context, event, data);
718
719 spin_unlock_irqrestore(&priv->ctx_lock, flags);
720}
721
722struct mlx5_core_event_handler {
723 void (*event)(struct mlx5_core_dev *dev,
724 enum mlx5_dev_event event,
725 void *data);
726};
727
728static int init_one(struct pci_dev *pdev,
729 const struct pci_device_id *id)
730{
731 struct mlx5_core_dev *dev;
732 struct mlx5_priv *priv;
733 int err;
734
735 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
736 if (!dev) {
737 dev_err(&pdev->dev, "kzalloc failed\n");
738 return -ENOMEM;
739 }
740 priv = &dev->priv;
741
742 pci_set_drvdata(pdev, dev);
743
744 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
745 pr_warn("selected profile out of range, selecting default (%d)\n",
746 MLX5_DEFAULT_PROF);
747 prof_sel = MLX5_DEFAULT_PROF;
748 }
749 dev->profile = &profile[prof_sel];
750 dev->event = mlx5_core_event;
751
752 err = mlx5_dev_init(dev, pdev);
753 if (err) {
754 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
755 goto out;
756 }
757
758 INIT_LIST_HEAD(&priv->ctx_list);
759 spin_lock_init(&priv->ctx_lock);
760 err = mlx5_register_device(dev);
761 if (err) {
762 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
763 goto out_init;
764 }
765
766 return 0;
767
768out_init:
769 mlx5_dev_cleanup(dev);
770out:
771 kfree(dev);
772 return err;
773}
774static void remove_one(struct pci_dev *pdev)
775{
776 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
777
778 mlx5_unregister_device(dev);
779 mlx5_dev_cleanup(dev);
780 kfree(dev);
781}
782
783static const struct pci_device_id mlx5_core_pci_table[] = {
784 { PCI_VDEVICE(MELLANOX, 4113) }, /* MT4113 Connect-IB */
785 { 0, }
786};
787
788MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
789
790static struct pci_driver mlx5_core_driver = {
791 .name = DRIVER_NAME,
792 .id_table = mlx5_core_pci_table,
793 .probe = init_one,
794 .remove = remove_one
795};
e126ba97
EC		 796
797static int __init init(void)
798{
799 int err;
800
801 mlx5_register_debugfs();
802 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
803 if (!mlx5_core_wq) {
804 err = -ENOMEM;
805 goto err_debug;
806 }
807 mlx5_health_init();
808
9603b61d
JM		 809 err = pci_register_driver(&mlx5_core_driver);
810 if (err)
811 goto err_health;
812
e126ba97
EC		 813 return 0;
814
9603b61d
JM		 815err_health:
816 mlx5_health_cleanup();
817 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 818err_debug:
819 mlx5_unregister_debugfs();
820 return err;
821}
822
823static void __exit cleanup(void)
824{
9603b61d 825 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 826 mlx5_health_cleanup();
827 destroy_workqueue(mlx5_core_wq);
828 mlx5_unregister_debugfs();
829}
830
831module_init(init);
832module_exit(cleanup);
Linux 6.x block layer and io_uring tree(s)