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net/mlx5_core: New device capabilities handling
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e126ba97
EC		 42#include <linux/mlx5/driver.h>
43#include <linux/mlx5/cq.h>
44#include <linux/mlx5/qp.h>
45#include <linux/mlx5/srq.h>
46#include <linux/debugfs.h>
f66f049f 47#include <linux/kmod.h>
b775516b 48#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 49#include "mlx5_core.h"
50
51#define DRIVER_NAME "mlx5_core"
4ae6c18c
AS		 52#define DRIVER_VERSION "3.0"
53#define DRIVER_RELDATE "January 2015"
e126ba97
EC		 54
55MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 56MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 57MODULE_LICENSE("Dual BSD/GPL");
58MODULE_VERSION(DRIVER_VERSION);
59
60int mlx5_core_debug_mask;
61module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
62MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
63
9603b61d
JM		 64#define MLX5_DEFAULT_PROF 2
65static int prof_sel = MLX5_DEFAULT_PROF;
66module_param_named(prof_sel, prof_sel, int, 0444);
67MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
68
e126ba97 69struct workqueue_struct *mlx5_core_wq;
9603b61d
JM		 70static LIST_HEAD(intf_list);
71static LIST_HEAD(dev_list);
72static DEFINE_MUTEX(intf_mutex);
73
74struct mlx5_device_context {
75 struct list_head list;
76 struct mlx5_interface *intf;
77 void *context;
78};
79
80static struct mlx5_profile profile[] = {
81 [0] = {
82 .mask = 0,
83 },
84 [1] = {
85 .mask = MLX5_PROF_MASK_QP_SIZE,
86 .log_max_qp = 12,
87 },
88 [2] = {
89 .mask = MLX5_PROF_MASK_QP_SIZE |
90 MLX5_PROF_MASK_MR_CACHE,
91 .log_max_qp = 17,
92 .mr_cache[0] = {
93 .size = 500,
94 .limit = 250
95 },
96 .mr_cache[1] = {
97 .size = 500,
98 .limit = 250
99 },
100 .mr_cache[2] = {
101 .size = 500,
102 .limit = 250
103 },
104 .mr_cache[3] = {
105 .size = 500,
106 .limit = 250
107 },
108 .mr_cache[4] = {
109 .size = 500,
110 .limit = 250
111 },
112 .mr_cache[5] = {
113 .size = 500,
114 .limit = 250
115 },
116 .mr_cache[6] = {
117 .size = 500,
118 .limit = 250
119 },
120 .mr_cache[7] = {
121 .size = 500,
122 .limit = 250
123 },
124 .mr_cache[8] = {
125 .size = 500,
126 .limit = 250
127 },
128 .mr_cache[9] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[10] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[11] = {
137 .size = 500,
138 .limit = 250
139 },
140 .mr_cache[12] = {
141 .size = 64,
142 .limit = 32
143 },
144 .mr_cache[13] = {
145 .size = 32,
146 .limit = 16
147 },
148 .mr_cache[14] = {
149 .size = 16,
150 .limit = 8
151 },
152 .mr_cache[15] = {
153 .size = 8,
154 .limit = 4
155 },
156 },
157};
e126ba97
EC		 158
159static int set_dma_caps(struct pci_dev *pdev)
160{
161 int err;
162
163 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
164 if (err) {
1a91de28 165 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 166 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
167 if (err) {
1a91de28 168 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 169 return err;
170 }
171 }
172
173 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
174 if (err) {
175 dev_warn(&pdev->dev,
1a91de28 176 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
178 if (err) {
179 dev_err(&pdev->dev,
1a91de28 180 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 181 return err;
182 }
183 }
184
185 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
186 return err;
187}
188
189static int request_bar(struct pci_dev *pdev)
190{
191 int err = 0;
192
193 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 194 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 195 return -ENODEV;
196 }
197
198 err = pci_request_regions(pdev, DRIVER_NAME);
199 if (err)
200 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
201
202 return err;
203}
204
205static void release_bar(struct pci_dev *pdev)
206{
207 pci_release_regions(pdev);
208}
209
210static int mlx5_enable_msix(struct mlx5_core_dev *dev)
211{
db058a18
SM		 212 struct mlx5_priv *priv = &dev->priv;
213 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 214 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 215 int nvec;
e126ba97
EC		 216 int i;
217
938fe83c
SM		 218 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
219 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 220 nvec = min_t(int, nvec, num_eqs);
221 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
222 return -ENOMEM;
223
db058a18
SM		 224 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
225
226 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
227 if (!priv->msix_arr || !priv->irq_info)
228 goto err_free_msix;
e126ba97
EC		 229
230 for (i = 0; i < nvec; i++)
db058a18 231 priv->msix_arr[i].entry = i;
e126ba97 232
db058a18 233 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
3a9e161a 234 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
f3c9407b
AG		 235 if (nvec < 0)
236 return nvec;
e126ba97 237
f3c9407b 238 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 239
240 return 0;
db058a18
SM		 241
242err_free_msix:
243 kfree(priv->irq_info);
244 kfree(priv->msix_arr);
245 return -ENOMEM;
e126ba97
EC		 246}
247
248static void mlx5_disable_msix(struct mlx5_core_dev *dev)
249{
db058a18 250 struct mlx5_priv *priv = &dev->priv;
e126ba97
EC		 251
252 pci_disable_msix(dev->pdev);
db058a18
SM		 253 kfree(priv->irq_info);
254 kfree(priv->msix_arr);
e126ba97
EC		 255}
256
257struct mlx5_reg_host_endianess {
258 u8 he;
259 u8 rsvd[15];
260};
261
87b8de49
EC		 262
263#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
264
265enum {
c7a08ac7
EC		 266 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
267 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 268};
269
c7a08ac7
EC		 270static u16 to_fw_pkey_sz(u32 size)
271{
272 switch (size) {
273 case 128:
274 return 0;
275 case 256:
276 return 1;
277 case 512:
278 return 2;
279 case 1024:
280 return 3;
281 case 2048:
282 return 4;
283 case 4096:
284 return 5;
285 default:
286 pr_warn("invalid pkey table size %d\n", size);
287 return 0;
288 }
289}
290
938fe83c 291static u16 to_sw_pkey_sz(int pkey_sz)
c7a08ac7 292{
938fe83c 293 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
c7a08ac7 294 return 0;
87b8de49 295
938fe83c 296 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
c7a08ac7
EC		 297}
298
938fe83c
SM		 299int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
300 enum mlx5_cap_mode cap_mode)
c7a08ac7 301{
b775516b
EC		 302 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
303 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 304 void *out, *hca_caps;
305 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 306 int err;
307
b775516b
EC		 308 memset(in, 0, sizeof(in));
309 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 310 if (!out)
e126ba97 311 return -ENOMEM;
938fe83c 312
b775516b
EC		 313 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
314 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
315 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
316 if (err)
317 goto query_ex;
e126ba97 318
b775516b 319 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7 320 if (err) {
938fe83c
SM		 321 mlx5_core_warn(dev,
322 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
323 cap_type, cap_mode, err);
e126ba97
EC		 324 goto query_ex;
325 }
c7a08ac7 326
938fe83c
SM		 327 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
328
329 switch (cap_mode) {
330 case HCA_CAP_OPMOD_GET_MAX:
331 memcpy(dev->hca_caps_max[cap_type], hca_caps,
332 MLX5_UN_SZ_BYTES(hca_cap_union));
333 break;
334 case HCA_CAP_OPMOD_GET_CUR:
335 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
336 MLX5_UN_SZ_BYTES(hca_cap_union));
337 break;
338 default:
339 mlx5_core_warn(dev,
340 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
341 cap_type, cap_mode);
342 err = -EINVAL;
343 break;
344 }
c7a08ac7
EC		 345query_ex:
346 kfree(out);
347 return err;
348}
349
b775516b 350static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
c7a08ac7 351{
b775516b 352 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
c7a08ac7
EC		 353 int err;
354
b775516b 355 memset(out, 0, sizeof(out));
e126ba97 356
b775516b
EC		 357 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
358 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
e126ba97 359 if (err)
c7a08ac7 360 return err;
e126ba97 361
b775516b 362 err = mlx5_cmd_status_to_err_v2(out);
c7a08ac7
EC		 363
364 return err;
365}
366
367static int handle_hca_cap(struct mlx5_core_dev *dev)
368{
b775516b 369 void *set_ctx = NULL;
c7a08ac7 370 struct mlx5_profile *prof = dev->profile;
c7a08ac7 371 int err = -ENOMEM;
b775516b 372 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 373 void *set_hca_cap;
c7a08ac7 374
b775516b 375 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 376 if (!set_ctx)
e126ba97 377 goto query_ex;
e126ba97 378
938fe83c 379 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
c7a08ac7 380 if (err)
e126ba97 381 goto query_ex;
e126ba97 382
938fe83c 383 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
e126ba97
EC		 384 if (err)
385 goto query_ex;
386
938fe83c
SM		 387 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
388 capability);
389 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
390 MLX5_ST_SZ_BYTES(cmd_hca_cap));
391
392 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
393 to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
394 128);
c7a08ac7 395 /* we limit the size of the pkey table to 128 entries for now */
938fe83c
SM		 396 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
397 to_fw_pkey_sz(128));
c7a08ac7
EC		 398
399 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 400 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
401 prof->log_max_qp);
c7a08ac7 402
938fe83c
SM		 403 /* disable cmdif checksum */
404 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 405
b775516b 406 err = set_caps(dev, set_ctx, set_sz);
c7a08ac7 407
e126ba97 408query_ex:
e126ba97 409 kfree(set_ctx);
e126ba97
EC		 410 return err;
411}
412
413static int set_hca_ctrl(struct mlx5_core_dev *dev)
414{
415 struct mlx5_reg_host_endianess he_in;
416 struct mlx5_reg_host_endianess he_out;
417 int err;
418
419 memset(&he_in, 0, sizeof(he_in));
420 he_in.he = MLX5_SET_HOST_ENDIANNESS;
421 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
422 &he_out, sizeof(he_out),
423 MLX5_REG_HOST_ENDIANNESS, 0, 1);
424 return err;
425}
426
cd23b14b
EC		 427static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
428{
429 int err;
430 struct mlx5_enable_hca_mbox_in in;
431 struct mlx5_enable_hca_mbox_out out;
432
433 memset(&in, 0, sizeof(in));
434 memset(&out, 0, sizeof(out));
435 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
436 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
437 if (err)
438 return err;
439
440 if (out.hdr.status)
441 return mlx5_cmd_status_to_err(&out.hdr);
442
443 return 0;
444}
445
446static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
447{
448 int err;
449 struct mlx5_disable_hca_mbox_in in;
450 struct mlx5_disable_hca_mbox_out out;
451
452 memset(&in, 0, sizeof(in));
453 memset(&out, 0, sizeof(out));
454 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
455 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
456 if (err)
457 return err;
458
459 if (out.hdr.status)
460 return mlx5_cmd_status_to_err(&out.hdr);
461
462 return 0;
463}
464
db058a18
SM		 465static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
466{
467 struct mlx5_priv *priv = &mdev->priv;
468 struct msix_entry *msix = priv->msix_arr;
469 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
470 int numa_node = dev_to_node(&mdev->pdev->dev);
471 int err;
472
473 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
474 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
475 return -ENOMEM;
476 }
477
478 err = cpumask_set_cpu_local_first(i, numa_node, priv->irq_info[i].mask);
479 if (err) {
480 mlx5_core_warn(mdev, "cpumask_set_cpu_local_first failed");
481 goto err_clear_mask;
482 }
483
484 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
485 if (err) {
486 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
487 irq);
488 goto err_clear_mask;
489 }
490
491 return 0;
492
493err_clear_mask:
494 free_cpumask_var(priv->irq_info[i].mask);
495 return err;
496}
497
498static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
499{
500 struct mlx5_priv *priv = &mdev->priv;
501 struct msix_entry *msix = priv->msix_arr;
502 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
503
504 irq_set_affinity_hint(irq, NULL);
505 free_cpumask_var(priv->irq_info[i].mask);
506}
507
508static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
509{
510 int err;
511 int i;
512
513 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
514 err = mlx5_irq_set_affinity_hint(mdev, i);
515 if (err)
516 goto err_out;
517 }
518
519 return 0;
520
521err_out:
522 for (i--; i >= 0; i--)
523 mlx5_irq_clear_affinity_hint(mdev, i);
524
525 return err;
526}
527
528static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
529{
530 int i;
531
532 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
533 mlx5_irq_clear_affinity_hint(mdev, i);
534}
535
233d05d2
SM		 536int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
537{
538 struct mlx5_eq_table *table = &dev->priv.eq_table;
539 struct mlx5_eq *eq, *n;
540 int err = -ENOENT;
541
542 spin_lock(&table->lock);
543 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
544 if (eq->index == vector) {
545 *eqn = eq->eqn;
546 *irqn = eq->irqn;
547 err = 0;
548 break;
549 }
550 }
551 spin_unlock(&table->lock);
552
553 return err;
554}
555EXPORT_SYMBOL(mlx5_vector2eqn);
556
557static void free_comp_eqs(struct mlx5_core_dev *dev)
558{
559 struct mlx5_eq_table *table = &dev->priv.eq_table;
560 struct mlx5_eq *eq, *n;
561
562 spin_lock(&table->lock);
563 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
564 list_del(&eq->list);
565 spin_unlock(&table->lock);
566 if (mlx5_destroy_unmap_eq(dev, eq))
567 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
568 eq->eqn);
569 kfree(eq);
570 spin_lock(&table->lock);
571 }
572 spin_unlock(&table->lock);
573}
574
575static int alloc_comp_eqs(struct mlx5_core_dev *dev)
576{
577 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 578 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 579 struct mlx5_eq *eq;
580 int ncomp_vec;
581 int nent;
582 int err;
583 int i;
584
585 INIT_LIST_HEAD(&table->comp_eqs_list);
586 ncomp_vec = table->num_comp_vectors;
587 nent = MLX5_COMP_EQ_SIZE;
588 for (i = 0; i < ncomp_vec; i++) {
589 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
590 if (!eq) {
591 err = -ENOMEM;
592 goto clean;
593 }
594
db058a18 595 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 596 err = mlx5_create_map_eq(dev, eq,
597 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
598 name, &dev->priv.uuari.uars[0]);
599 if (err) {
600 kfree(eq);
601 goto clean;
602 }
603 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
604 eq->index = i;
605 spin_lock(&table->lock);
606 list_add_tail(&eq->list, &table->comp_eqs_list);
607 spin_unlock(&table->lock);
608 }
609
610 return 0;
611
612clean:
613 free_comp_eqs(dev);
614 return err;
615}
616
9603b61d 617static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
e126ba97
EC		 618{
619 struct mlx5_priv *priv = &dev->priv;
620 int err;
621
622 dev->pdev = pdev;
623 pci_set_drvdata(dev->pdev, dev);
624 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
625 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
626
627 mutex_init(&priv->pgdir_mutex);
628 INIT_LIST_HEAD(&priv->pgdir_list);
629 spin_lock_init(&priv->mkey_lock);
630
631 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
632 if (!priv->dbg_root)
633 return -ENOMEM;
634
635 err = pci_enable_device(pdev);
636 if (err) {
1a91de28 637 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 638 goto err_dbg;
639 }
640
641 err = request_bar(pdev);
642 if (err) {
1a91de28 643 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 644 goto err_disable;
645 }
646
647 pci_set_master(pdev);
648
649 err = set_dma_caps(pdev);
650 if (err) {
651 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
652 goto err_clr_master;
653 }
654
655 dev->iseg_base = pci_resource_start(dev->pdev, 0);
656 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
657 if (!dev->iseg) {
658 err = -ENOMEM;
659 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
660 goto err_clr_master;
661 }
662 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
663 fw_rev_min(dev), fw_rev_sub(dev));
664
665 err = mlx5_cmd_init(dev);
666 if (err) {
667 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
668 goto err_unmap;
669 }
670
671 mlx5_pagealloc_init(dev);
cd23b14b
EC		 672
673 err = mlx5_core_enable_hca(dev);
674 if (err) {
675 dev_err(&pdev->dev, "enable hca failed\n");
676 goto err_pagealloc_cleanup;
677 }
678
679 err = mlx5_satisfy_startup_pages(dev, 1);
680 if (err) {
681 dev_err(&pdev->dev, "failed to allocate boot pages\n");
682 goto err_disable_hca;
683 }
684
e126ba97
EC		 685 err = set_hca_ctrl(dev);
686 if (err) {
687 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 688 goto reclaim_boot_pages;
e126ba97
EC		 689 }
690
691 err = handle_hca_cap(dev);
692 if (err) {
693 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 694 goto reclaim_boot_pages;
e126ba97
EC		 695 }
696
cd23b14b 697 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 698 if (err) {
cd23b14b
EC		 699 dev_err(&pdev->dev, "failed to allocate init pages\n");
700 goto reclaim_boot_pages;
e126ba97
EC		 701 }
702
703 err = mlx5_pagealloc_start(dev);
704 if (err) {
705 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 706 goto reclaim_boot_pages;
e126ba97
EC		 707 }
708
709 err = mlx5_cmd_init_hca(dev);
710 if (err) {
711 dev_err(&pdev->dev, "init hca failed\n");
712 goto err_pagealloc_stop;
713 }
714
715 mlx5_start_health_poll(dev);
716
938fe83c 717 err = mlx5_query_hca_caps(dev);
e126ba97
EC		 718 if (err) {
719 dev_err(&pdev->dev, "query hca failed\n");
720 goto err_stop_poll;
721 }
722
723 err = mlx5_cmd_query_adapter(dev);
724 if (err) {
725 dev_err(&pdev->dev, "query adapter failed\n");
726 goto err_stop_poll;
727 }
728
729 err = mlx5_enable_msix(dev);
730 if (err) {
731 dev_err(&pdev->dev, "enable msix failed\n");
732 goto err_stop_poll;
733 }
734
735 err = mlx5_eq_init(dev);
736 if (err) {
737 dev_err(&pdev->dev, "failed to initialize eq\n");
738 goto disable_msix;
739 }
740
741 err = mlx5_alloc_uuars(dev, &priv->uuari);
742 if (err) {
743 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
744 goto err_eq_cleanup;
745 }
746
747 err = mlx5_start_eqs(dev);
748 if (err) {
749 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
750 goto err_free_uar;
751 }
752
233d05d2
SM		 753 err = alloc_comp_eqs(dev);
754 if (err) {
755 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
756 goto err_stop_eqs;
757 }
758
db058a18
SM		 759 err = mlx5_irq_set_affinity_hints(dev);
760 if (err) {
761 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
762 goto err_free_comp_eqs;
763 }
764
e126ba97
EC		 765 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
766
767 mlx5_init_cq_table(dev);
768 mlx5_init_qp_table(dev);
769 mlx5_init_srq_table(dev);
3bcdb17a 770 mlx5_init_mr_table(dev);
e126ba97
EC		 771
772 return 0;
773
db058a18
SM		 774err_free_comp_eqs:
775 free_comp_eqs(dev);
776
233d05d2
SM		 777err_stop_eqs:
778 mlx5_stop_eqs(dev);
779
e126ba97
EC		 780err_free_uar:
781 mlx5_free_uuars(dev, &priv->uuari);
782
783err_eq_cleanup:
784 mlx5_eq_cleanup(dev);
785
786disable_msix:
787 mlx5_disable_msix(dev);
788
789err_stop_poll:
790 mlx5_stop_health_poll(dev);
1bde6e30
EC		 791 if (mlx5_cmd_teardown_hca(dev)) {
792 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
793 return err;
794 }
e126ba97
EC		 795
796err_pagealloc_stop:
797 mlx5_pagealloc_stop(dev);
798
cd23b14b 799reclaim_boot_pages:
e126ba97
EC		 800 mlx5_reclaim_startup_pages(dev);
801
cd23b14b
EC		 802err_disable_hca:
803 mlx5_core_disable_hca(dev);
804
e126ba97
EC		 805err_pagealloc_cleanup:
806 mlx5_pagealloc_cleanup(dev);
807 mlx5_cmd_cleanup(dev);
808
809err_unmap:
810 iounmap(dev->iseg);
811
812err_clr_master:
813 pci_clear_master(dev->pdev);
814 release_bar(dev->pdev);
815
816err_disable:
817 pci_disable_device(dev->pdev);
818
819err_dbg:
820 debugfs_remove(priv->dbg_root);
821 return err;
822}
e126ba97 823
9603b61d 824static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
e126ba97
EC		 825{
826 struct mlx5_priv *priv = &dev->priv;
827
828 mlx5_cleanup_srq_table(dev);
829 mlx5_cleanup_qp_table(dev);
830 mlx5_cleanup_cq_table(dev);
db058a18 831 mlx5_irq_clear_affinity_hints(dev);
233d05d2 832 free_comp_eqs(dev);
e126ba97
EC		 833 mlx5_stop_eqs(dev);
834 mlx5_free_uuars(dev, &priv->uuari);
835 mlx5_eq_cleanup(dev);
836 mlx5_disable_msix(dev);
837 mlx5_stop_health_poll(dev);
1bde6e30
EC		 838 if (mlx5_cmd_teardown_hca(dev)) {
839 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
840 return;
841 }
e126ba97
EC		 842 mlx5_pagealloc_stop(dev);
843 mlx5_reclaim_startup_pages(dev);
cd23b14b 844 mlx5_core_disable_hca(dev);
e126ba97
EC		 845 mlx5_pagealloc_cleanup(dev);
846 mlx5_cmd_cleanup(dev);
847 iounmap(dev->iseg);
848 pci_clear_master(dev->pdev);
849 release_bar(dev->pdev);
850 pci_disable_device(dev->pdev);
851 debugfs_remove(priv->dbg_root);
852}
9603b61d
JM		 853
854static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
855{
856 struct mlx5_device_context *dev_ctx;
857 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
858
859 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
860 if (!dev_ctx) {
861 pr_warn("mlx5_add_device: alloc context failed\n");
862 return;
863 }
864
865 dev_ctx->intf = intf;
866 dev_ctx->context = intf->add(dev);
867
868 if (dev_ctx->context) {
869 spin_lock_irq(&priv->ctx_lock);
870 list_add_tail(&dev_ctx->list, &priv->ctx_list);
871 spin_unlock_irq(&priv->ctx_lock);
872 } else {
873 kfree(dev_ctx);
874 }
875}
876
877static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
878{
879 struct mlx5_device_context *dev_ctx;
880 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
881
882 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
883 if (dev_ctx->intf == intf) {
884 spin_lock_irq(&priv->ctx_lock);
885 list_del(&dev_ctx->list);
886 spin_unlock_irq(&priv->ctx_lock);
887
888 intf->remove(dev, dev_ctx->context);
889 kfree(dev_ctx);
890 return;
891 }
892}
893static int mlx5_register_device(struct mlx5_core_dev *dev)
894{
895 struct mlx5_priv *priv = &dev->priv;
896 struct mlx5_interface *intf;
897
898 mutex_lock(&intf_mutex);
899 list_add_tail(&priv->dev_list, &dev_list);
900 list_for_each_entry(intf, &intf_list, list)
901 mlx5_add_device(intf, priv);
902 mutex_unlock(&intf_mutex);
903
904 return 0;
905}
906static void mlx5_unregister_device(struct mlx5_core_dev *dev)
907{
908 struct mlx5_priv *priv = &dev->priv;
909 struct mlx5_interface *intf;
910
911 mutex_lock(&intf_mutex);
912 list_for_each_entry(intf, &intf_list, list)
913 mlx5_remove_device(intf, priv);
914 list_del(&priv->dev_list);
915 mutex_unlock(&intf_mutex);
916}
917
918int mlx5_register_interface(struct mlx5_interface *intf)
919{
920 struct mlx5_priv *priv;
921
922 if (!intf->add || !intf->remove)
923 return -EINVAL;
924
925 mutex_lock(&intf_mutex);
926 list_add_tail(&intf->list, &intf_list);
927 list_for_each_entry(priv, &dev_list, dev_list)
928 mlx5_add_device(intf, priv);
929 mutex_unlock(&intf_mutex);
930
931 return 0;
932}
933EXPORT_SYMBOL(mlx5_register_interface);
934
935void mlx5_unregister_interface(struct mlx5_interface *intf)
936{
937 struct mlx5_priv *priv;
938
939 mutex_lock(&intf_mutex);
940 list_for_each_entry(priv, &dev_list, dev_list)
941 mlx5_remove_device(intf, priv);
942 list_del(&intf->list);
943 mutex_unlock(&intf_mutex);
944}
945EXPORT_SYMBOL(mlx5_unregister_interface);
946
64613d94
SM		 947void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
948{
949 struct mlx5_priv *priv = &mdev->priv;
950 struct mlx5_device_context *dev_ctx;
951 unsigned long flags;
952 void *result = NULL;
953
954 spin_lock_irqsave(&priv->ctx_lock, flags);
955
956 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
957 if ((dev_ctx->intf->protocol == protocol) &&
958 dev_ctx->intf->get_dev) {
959 result = dev_ctx->intf->get_dev(dev_ctx->context);
960 break;
961 }
962
963 spin_unlock_irqrestore(&priv->ctx_lock, flags);
964
965 return result;
966}
967EXPORT_SYMBOL(mlx5_get_protocol_dev);
968
9603b61d 969static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
4d2f9bbb 970 unsigned long param)
9603b61d
JM		 971{
972 struct mlx5_priv *priv = &dev->priv;
973 struct mlx5_device_context *dev_ctx;
974 unsigned long flags;
975
976 spin_lock_irqsave(&priv->ctx_lock, flags);
977
978 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
979 if (dev_ctx->intf->event)
4d2f9bbb 980 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
9603b61d
JM		 981
982 spin_unlock_irqrestore(&priv->ctx_lock, flags);
983}
984
985struct mlx5_core_event_handler {
986 void (*event)(struct mlx5_core_dev *dev,
987 enum mlx5_dev_event event,
988 void *data);
989};
990
f66f049f
EC		 991#define MLX5_IB_MOD "mlx5_ib"
992
9603b61d
JM		 993static int init_one(struct pci_dev *pdev,
994 const struct pci_device_id *id)
995{
996 struct mlx5_core_dev *dev;
997 struct mlx5_priv *priv;
998 int err;
999
1000 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1001 if (!dev) {
1002 dev_err(&pdev->dev, "kzalloc failed\n");
1003 return -ENOMEM;
1004 }
1005 priv = &dev->priv;
1006
1007 pci_set_drvdata(pdev, dev);
1008
1009 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1010 pr_warn("selected profile out of range, selecting default (%d)\n",
1011 MLX5_DEFAULT_PROF);
1012 prof_sel = MLX5_DEFAULT_PROF;
1013 }
1014 dev->profile = &profile[prof_sel];
1015 dev->event = mlx5_core_event;
1016
364d1798
EC		 1017 INIT_LIST_HEAD(&priv->ctx_list);
1018 spin_lock_init(&priv->ctx_lock);
9603b61d
JM		 1019 err = mlx5_dev_init(dev, pdev);
1020 if (err) {
1021 dev_err(&pdev->dev, "mlx5_dev_init failed %d\n", err);
1022 goto out;
1023 }
1024
9603b61d
JM		 1025 err = mlx5_register_device(dev);
1026 if (err) {
1027 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1028 goto out_init;
1029 }
1030
f66f049f
EC		 1031 err = request_module_nowait(MLX5_IB_MOD);
1032 if (err)
1033 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1034
9603b61d
JM		 1035 return 0;
1036
1037out_init:
1038 mlx5_dev_cleanup(dev);
1039out:
1040 kfree(dev);
1041 return err;
1042}
1043static void remove_one(struct pci_dev *pdev)
1044{
1045 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1046
1047 mlx5_unregister_device(dev);
1048 mlx5_dev_cleanup(dev);
1049 kfree(dev);
1050}
1051
1052static const struct pci_device_id mlx5_core_pci_table[] = {
1c755cc5
OG		 1053 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1054 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1055 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1056 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1057 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1058 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
9603b61d
JM		 1059 { 0, }
1060};
1061
1062MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1063
1064static struct pci_driver mlx5_core_driver = {
1065 .name = DRIVER_NAME,
1066 .id_table = mlx5_core_pci_table,
1067 .probe = init_one,
1068 .remove = remove_one
1069};
e126ba97
EC		 1070
1071static int __init init(void)
1072{
1073 int err;
1074
1075 mlx5_register_debugfs();
1076 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1077 if (!mlx5_core_wq) {
1078 err = -ENOMEM;
1079 goto err_debug;
1080 }
1081 mlx5_health_init();
1082
9603b61d
JM		 1083 err = pci_register_driver(&mlx5_core_driver);
1084 if (err)
1085 goto err_health;
1086
e126ba97
EC		 1087 return 0;
1088
9603b61d
JM		 1089err_health:
1090 mlx5_health_cleanup();
1091 destroy_workqueue(mlx5_core_wq);
e126ba97
EC		 1092err_debug:
1093 mlx5_unregister_debugfs();
1094 return err;
1095}
1096
1097static void __exit cleanup(void)
1098{
9603b61d 1099 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1100 mlx5_health_cleanup();
1101 destroy_workqueue(mlx5_core_wq);
1102 mlx5_unregister_debugfs();
1103}
1104
1105module_init(init);
1106module_exit(cleanup);
Linux 6.x block layer and io_uring tree(s)