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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
e126ba97 | 46 | #include <linux/debugfs.h> |
f66f049f | 47 | #include <linux/kmod.h> |
b775516b | 48 | #include <linux/mlx5/mlx5_ifc.h> |
c85023e1 | 49 | #include <linux/mlx5/vport.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
feae9087 | 53 | #include <net/devlink.h> |
e126ba97 | 54 | #include "mlx5_core.h" |
f2f3df55 | 55 | #include "lib/eq.h" |
16d76083 | 56 | #include "fs_core.h" |
eeb66cdb | 57 | #include "lib/mpfs.h" |
073bb189 | 58 | #include "eswitch.h" |
52ec462e | 59 | #include "lib/mlx5.h" |
e29341fb | 60 | #include "fpga/core.h" |
05564d0a | 61 | #include "fpga/ipsec.h" |
bebb23e6 | 62 | #include "accel/ipsec.h" |
1ae17322 | 63 | #include "accel/tls.h" |
7c39afb3 | 64 | #include "lib/clock.h" |
358aa5ce | 65 | #include "lib/vxlan.h" |
fadd59fc | 66 | #include "lib/devcom.h" |
24406953 | 67 | #include "diag/fw_tracer.h" |
591905ba | 68 | #include "ecpf.h" |
e126ba97 | 69 | |
e126ba97 | 70 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
048f3143 | 71 | MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); |
e126ba97 EC |
72 | MODULE_LICENSE("Dual BSD/GPL"); |
73 | MODULE_VERSION(DRIVER_VERSION); | |
74 | ||
f663ad98 KH |
75 | unsigned int mlx5_core_debug_mask; |
76 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
77 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
78 | ||
9603b61d | 79 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
80 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
81 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
82 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
83 | ||
8737f818 DJ |
84 | static u32 sw_owner_id[4]; |
85 | ||
f91e6d89 EBE |
86 | enum { |
87 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
88 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
89 | }; | |
90 | ||
9603b61d JM |
91 | static struct mlx5_profile profile[] = { |
92 | [0] = { | |
93 | .mask = 0, | |
94 | }, | |
95 | [1] = { | |
96 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
97 | .log_max_qp = 12, | |
98 | }, | |
99 | [2] = { | |
100 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
101 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 102 | .log_max_qp = 18, |
9603b61d JM |
103 | .mr_cache[0] = { |
104 | .size = 500, | |
105 | .limit = 250 | |
106 | }, | |
107 | .mr_cache[1] = { | |
108 | .size = 500, | |
109 | .limit = 250 | |
110 | }, | |
111 | .mr_cache[2] = { | |
112 | .size = 500, | |
113 | .limit = 250 | |
114 | }, | |
115 | .mr_cache[3] = { | |
116 | .size = 500, | |
117 | .limit = 250 | |
118 | }, | |
119 | .mr_cache[4] = { | |
120 | .size = 500, | |
121 | .limit = 250 | |
122 | }, | |
123 | .mr_cache[5] = { | |
124 | .size = 500, | |
125 | .limit = 250 | |
126 | }, | |
127 | .mr_cache[6] = { | |
128 | .size = 500, | |
129 | .limit = 250 | |
130 | }, | |
131 | .mr_cache[7] = { | |
132 | .size = 500, | |
133 | .limit = 250 | |
134 | }, | |
135 | .mr_cache[8] = { | |
136 | .size = 500, | |
137 | .limit = 250 | |
138 | }, | |
139 | .mr_cache[9] = { | |
140 | .size = 500, | |
141 | .limit = 250 | |
142 | }, | |
143 | .mr_cache[10] = { | |
144 | .size = 500, | |
145 | .limit = 250 | |
146 | }, | |
147 | .mr_cache[11] = { | |
148 | .size = 500, | |
149 | .limit = 250 | |
150 | }, | |
151 | .mr_cache[12] = { | |
152 | .size = 64, | |
153 | .limit = 32 | |
154 | }, | |
155 | .mr_cache[13] = { | |
156 | .size = 32, | |
157 | .limit = 16 | |
158 | }, | |
159 | .mr_cache[14] = { | |
160 | .size = 16, | |
161 | .limit = 8 | |
162 | }, | |
163 | .mr_cache[15] = { | |
164 | .size = 8, | |
165 | .limit = 4 | |
166 | }, | |
167 | }, | |
168 | }; | |
e126ba97 | 169 | |
6c780a02 EC |
170 | #define FW_INIT_TIMEOUT_MILI 2000 |
171 | #define FW_INIT_WAIT_MS 2 | |
b8a92577 DJ |
172 | #define FW_PRE_INIT_TIMEOUT_MILI 120000 |
173 | #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 | |
e3297246 | 174 | |
b8a92577 DJ |
175 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, |
176 | u32 warn_time_mili) | |
e3297246 | 177 | { |
b8a92577 | 178 | unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); |
e3297246 EC |
179 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); |
180 | int err = 0; | |
181 | ||
b8a92577 DJ |
182 | BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); |
183 | ||
e3297246 EC |
184 | while (fw_initializing(dev)) { |
185 | if (time_after(jiffies, end)) { | |
186 | err = -EBUSY; | |
187 | break; | |
188 | } | |
b8a92577 DJ |
189 | if (warn_time_mili && time_after(jiffies, warn)) { |
190 | mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", | |
191 | jiffies_to_msecs(end - warn) / 1000); | |
192 | warn = jiffies + msecs_to_jiffies(warn_time_mili); | |
193 | } | |
e3297246 EC |
194 | msleep(FW_INIT_WAIT_MS); |
195 | } | |
196 | ||
197 | return err; | |
198 | } | |
199 | ||
012e50e1 HN |
200 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
201 | { | |
202 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
203 | driver_version); | |
204 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; | |
205 | u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; | |
206 | int remaining_size = driver_ver_sz; | |
207 | char *string; | |
208 | ||
209 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
210 | return; | |
211 | ||
212 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
213 | ||
214 | strncpy(string, "Linux", remaining_size); | |
215 | ||
216 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
217 | strncat(string, ",", remaining_size); | |
218 | ||
219 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
220 | strncat(string, DRIVER_NAME, remaining_size); | |
221 | ||
222 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
223 | strncat(string, ",", remaining_size); | |
224 | ||
225 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
226 | strncat(string, DRIVER_VERSION, remaining_size); | |
227 | ||
228 | /*Send the command*/ | |
229 | MLX5_SET(set_driver_version_in, in, opcode, | |
230 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
231 | ||
232 | mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
233 | } | |
234 | ||
e126ba97 EC |
235 | static int set_dma_caps(struct pci_dev *pdev) |
236 | { | |
237 | int err; | |
238 | ||
239 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
240 | if (err) { | |
1a91de28 | 241 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
242 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
243 | if (err) { | |
1a91de28 | 244 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
245 | return err; |
246 | } | |
247 | } | |
248 | ||
249 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
250 | if (err) { | |
251 | dev_warn(&pdev->dev, | |
1a91de28 | 252 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
253 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
254 | if (err) { | |
255 | dev_err(&pdev->dev, | |
1a91de28 | 256 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
257 | return err; |
258 | } | |
259 | } | |
260 | ||
261 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
262 | return err; | |
263 | } | |
264 | ||
89d44f0a MD |
265 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
266 | { | |
267 | struct pci_dev *pdev = dev->pdev; | |
268 | int err = 0; | |
269 | ||
270 | mutex_lock(&dev->pci_status_mutex); | |
271 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
272 | err = pci_enable_device(pdev); | |
273 | if (!err) | |
274 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
275 | } | |
276 | mutex_unlock(&dev->pci_status_mutex); | |
277 | ||
278 | return err; | |
279 | } | |
280 | ||
281 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
282 | { | |
283 | struct pci_dev *pdev = dev->pdev; | |
284 | ||
285 | mutex_lock(&dev->pci_status_mutex); | |
286 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
287 | pci_disable_device(pdev); | |
288 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
289 | } | |
290 | mutex_unlock(&dev->pci_status_mutex); | |
291 | } | |
292 | ||
e126ba97 EC |
293 | static int request_bar(struct pci_dev *pdev) |
294 | { | |
295 | int err = 0; | |
296 | ||
297 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 298 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
299 | return -ENODEV; |
300 | } | |
301 | ||
302 | err = pci_request_regions(pdev, DRIVER_NAME); | |
303 | if (err) | |
304 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
305 | ||
306 | return err; | |
307 | } | |
308 | ||
309 | static void release_bar(struct pci_dev *pdev) | |
310 | { | |
311 | pci_release_regions(pdev); | |
312 | } | |
313 | ||
bd10838a | 314 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
315 | u8 he; |
316 | u8 rsvd[15]; | |
317 | }; | |
318 | ||
87b8de49 EC |
319 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
320 | ||
321 | enum { | |
c7a08ac7 EC |
322 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
323 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
324 | }; |
325 | ||
2974ab6e | 326 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
327 | { |
328 | switch (size) { | |
329 | case 128: | |
330 | return 0; | |
331 | case 256: | |
332 | return 1; | |
333 | case 512: | |
334 | return 2; | |
335 | case 1024: | |
336 | return 3; | |
337 | case 2048: | |
338 | return 4; | |
339 | case 4096: | |
340 | return 5; | |
341 | default: | |
2974ab6e | 342 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
343 | return 0; |
344 | } | |
345 | } | |
346 | ||
b06e7de8 LR |
347 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
348 | enum mlx5_cap_type cap_type, | |
349 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 350 | { |
b775516b EC |
351 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
352 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
353 | void *out, *hca_caps; |
354 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
355 | int err; |
356 | ||
b775516b EC |
357 | memset(in, 0, sizeof(in)); |
358 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 359 | if (!out) |
e126ba97 | 360 | return -ENOMEM; |
938fe83c | 361 | |
b775516b EC |
362 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
363 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
364 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 365 | if (err) { |
938fe83c SM |
366 | mlx5_core_warn(dev, |
367 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
368 | cap_type, cap_mode, err); | |
e126ba97 EC |
369 | goto query_ex; |
370 | } | |
c7a08ac7 | 371 | |
938fe83c SM |
372 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
373 | ||
374 | switch (cap_mode) { | |
375 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 376 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
377 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
378 | break; | |
379 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 380 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
381 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
382 | break; | |
383 | default: | |
384 | mlx5_core_warn(dev, | |
385 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
386 | cap_type, cap_mode); | |
387 | err = -EINVAL; | |
388 | break; | |
389 | } | |
c7a08ac7 EC |
390 | query_ex: |
391 | kfree(out); | |
392 | return err; | |
393 | } | |
394 | ||
b06e7de8 LR |
395 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
396 | { | |
397 | int ret; | |
398 | ||
399 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
400 | if (ret) | |
401 | return ret; | |
402 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
403 | } | |
404 | ||
f91e6d89 | 405 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 406 | { |
c4f287c4 | 407 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 408 | |
b775516b | 409 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 410 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 411 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
412 | } |
413 | ||
f91e6d89 EBE |
414 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
415 | { | |
416 | void *set_ctx; | |
417 | void *set_hca_cap; | |
418 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
419 | int req_endianness; | |
420 | int err; | |
421 | ||
422 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 423 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
424 | if (err) |
425 | return err; | |
426 | } else { | |
427 | return 0; | |
428 | } | |
429 | ||
430 | req_endianness = | |
431 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 432 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
433 | |
434 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
435 | return 0; | |
436 | ||
437 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
438 | if (!set_ctx) | |
439 | return -ENOMEM; | |
440 | ||
441 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
442 | ||
443 | /* Set requestor to host endianness */ | |
bd10838a | 444 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
445 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
446 | ||
447 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
448 | ||
449 | kfree(set_ctx); | |
450 | return err; | |
451 | } | |
452 | ||
46861e3e MS |
453 | static int handle_hca_cap_odp(struct mlx5_core_dev *dev) |
454 | { | |
46861e3e | 455 | void *set_hca_cap; |
224d71cc LR |
456 | void *set_ctx; |
457 | int set_sz; | |
fca22e7e | 458 | bool do_set = false; |
46861e3e MS |
459 | int err; |
460 | ||
37b6bb77 LR |
461 | if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || |
462 | !MLX5_CAP_GEN(dev, pg)) | |
46861e3e MS |
463 | return 0; |
464 | ||
465 | err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); | |
466 | if (err) | |
467 | return err; | |
468 | ||
224d71cc | 469 | set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
46861e3e MS |
470 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
471 | if (!set_ctx) | |
472 | return -ENOMEM; | |
473 | ||
474 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
475 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], | |
476 | MLX5_ST_SZ_BYTES(odp_cap)); | |
477 | ||
fca22e7e MS |
478 | #define ODP_CAP_SET_MAX(dev, field) \ |
479 | do { \ | |
480 | u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ | |
481 | if (_res) { \ | |
482 | do_set = true; \ | |
483 | MLX5_SET(odp_cap, set_hca_cap, field, _res); \ | |
484 | } \ | |
485 | } while (0) | |
486 | ||
487 | ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); | |
488 | ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); | |
489 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); | |
490 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); | |
491 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); | |
492 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); | |
493 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); | |
494 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); | |
495 | ||
496 | if (do_set) | |
497 | err = set_caps(dev, set_ctx, set_sz, | |
498 | MLX5_SET_HCA_CAP_OP_MOD_ODP); | |
46861e3e MS |
499 | |
500 | kfree(set_ctx); | |
fca22e7e | 501 | |
46861e3e MS |
502 | return err; |
503 | } | |
504 | ||
c7a08ac7 EC |
505 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
506 | { | |
b775516b | 507 | void *set_ctx = NULL; |
c7a08ac7 | 508 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 509 | int err = -ENOMEM; |
b775516b | 510 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 511 | void *set_hca_cap; |
c7a08ac7 | 512 | |
b775516b | 513 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 514 | if (!set_ctx) |
e126ba97 | 515 | goto query_ex; |
e126ba97 | 516 | |
b06e7de8 | 517 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
518 | if (err) |
519 | goto query_ex; | |
520 | ||
938fe83c SM |
521 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
522 | capability); | |
701052c5 | 523 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
524 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
525 | ||
526 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 527 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 528 | 128); |
c7a08ac7 | 529 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 530 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 531 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 532 | |
883371c4 NO |
533 | /* Check log_max_qp from HCA caps to set in current profile */ |
534 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
535 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
536 | profile[prof_sel].log_max_qp, | |
537 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
538 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
539 | } | |
c7a08ac7 | 540 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
541 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
542 | prof->log_max_qp); | |
c7a08ac7 | 543 | |
938fe83c SM |
544 | /* disable cmdif checksum */ |
545 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 546 | |
91828bd8 MD |
547 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
548 | * than 4K. | |
549 | */ | |
550 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
551 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
552 | ||
fe1e1876 CS |
553 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
554 | ||
f32f5bd2 DJ |
555 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
556 | MLX5_SET(cmd_hca_cap, | |
557 | set_hca_cap, | |
558 | cache_line_128byte, | |
c67f100e | 559 | cache_line_size() >= 128 ? 1 : 0); |
f32f5bd2 | 560 | |
dd44572a MS |
561 | if (MLX5_CAP_GEN_MAX(dev, dct)) |
562 | MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); | |
563 | ||
c4b76d8d DJ |
564 | if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) |
565 | MLX5_SET(cmd_hca_cap, | |
566 | set_hca_cap, | |
567 | num_vhca_ports, | |
568 | MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); | |
569 | ||
f91e6d89 EBE |
570 | err = set_caps(dev, set_ctx, set_sz, |
571 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 572 | |
e126ba97 | 573 | query_ex: |
e126ba97 | 574 | kfree(set_ctx); |
e126ba97 EC |
575 | return err; |
576 | } | |
577 | ||
37b6bb77 LR |
578 | static int set_hca_cap(struct mlx5_core_dev *dev) |
579 | { | |
37b6bb77 LR |
580 | int err; |
581 | ||
582 | err = handle_hca_cap(dev); | |
583 | if (err) { | |
98a8e6fc | 584 | mlx5_core_err(dev, "handle_hca_cap failed\n"); |
37b6bb77 LR |
585 | goto out; |
586 | } | |
587 | ||
588 | err = handle_hca_cap_atomic(dev); | |
589 | if (err) { | |
98a8e6fc | 590 | mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); |
37b6bb77 LR |
591 | goto out; |
592 | } | |
593 | ||
594 | err = handle_hca_cap_odp(dev); | |
595 | if (err) { | |
98a8e6fc | 596 | mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); |
37b6bb77 LR |
597 | goto out; |
598 | } | |
599 | ||
600 | out: | |
601 | return err; | |
602 | } | |
603 | ||
e126ba97 EC |
604 | static int set_hca_ctrl(struct mlx5_core_dev *dev) |
605 | { | |
bd10838a OG |
606 | struct mlx5_reg_host_endianness he_in; |
607 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
608 | int err; |
609 | ||
fc50db98 EC |
610 | if (!mlx5_core_is_pf(dev)) |
611 | return 0; | |
612 | ||
e126ba97 EC |
613 | memset(&he_in, 0, sizeof(he_in)); |
614 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
615 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
616 | &he_out, sizeof(he_out), | |
617 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
618 | return err; | |
619 | } | |
620 | ||
c85023e1 HN |
621 | static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) |
622 | { | |
623 | int ret = 0; | |
624 | ||
625 | /* Disable local_lb by default */ | |
8978cc92 | 626 | if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) |
c85023e1 HN |
627 | ret = mlx5_nic_vport_update_local_lb(dev, false); |
628 | ||
629 | return ret; | |
630 | } | |
631 | ||
0b107106 | 632 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 633 | { |
c4f287c4 SM |
634 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
635 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 636 | |
0b107106 EC |
637 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
638 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
639 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
640 | dev->caps.embedded_cpu); | |
c4f287c4 | 641 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
642 | } |
643 | ||
0b107106 | 644 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 645 | { |
c4f287c4 SM |
646 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
647 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 648 | |
0b107106 EC |
649 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
650 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
651 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
652 | dev->caps.embedded_cpu); | |
c4f287c4 | 653 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
654 | } |
655 | ||
4a0475d5 ML |
656 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, |
657 | struct ptp_system_timestamp *sts) | |
b0844444 EBE |
658 | { |
659 | u32 timer_h, timer_h1, timer_l; | |
660 | ||
661 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
4a0475d5 | 662 | ptp_read_system_prets(sts); |
b0844444 | 663 | timer_l = ioread32be(&dev->iseg->internal_timer_l); |
4a0475d5 | 664 | ptp_read_system_postts(sts); |
b0844444 | 665 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); |
4a0475d5 ML |
666 | if (timer_h != timer_h1) { |
667 | /* wrap around */ | |
668 | ptp_read_system_prets(sts); | |
b0844444 | 669 | timer_l = ioread32be(&dev->iseg->internal_timer_l); |
4a0475d5 ML |
670 | ptp_read_system_postts(sts); |
671 | } | |
b0844444 | 672 | |
a5a1d1c2 | 673 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
674 | } |
675 | ||
f62b8bb8 AV |
676 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
677 | { | |
c4f287c4 SM |
678 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
679 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 680 | u32 sup_issi; |
c4f287c4 | 681 | int err; |
f62b8bb8 AV |
682 | |
683 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
684 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
685 | query_out, sizeof(query_out)); | |
f62b8bb8 | 686 | if (err) { |
c4f287c4 SM |
687 | u32 syndrome; |
688 | u8 status; | |
689 | ||
690 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
691 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
692 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
693 | err, status, syndrome); | |
694 | return err; | |
f62b8bb8 AV |
695 | } |
696 | ||
f9c14e46 KH |
697 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
698 | dev->issi = 0; | |
699 | return 0; | |
f62b8bb8 AV |
700 | } |
701 | ||
702 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
703 | ||
704 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
705 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
706 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
707 | |
708 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
709 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
710 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
711 | set_out, sizeof(set_out)); | |
f62b8bb8 | 712 | if (err) { |
f9c14e46 KH |
713 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
714 | err); | |
f62b8bb8 AV |
715 | return err; |
716 | } | |
717 | ||
718 | dev->issi = 1; | |
719 | ||
720 | return 0; | |
e74a1db0 | 721 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
722 | return 0; |
723 | } | |
724 | ||
9eb78923 | 725 | return -EOPNOTSUPP; |
f62b8bb8 | 726 | } |
f62b8bb8 | 727 | |
11f3b84d SM |
728 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, |
729 | const struct pci_device_id *id) | |
a31208b1 | 730 | { |
868bc06b | 731 | struct mlx5_priv *priv = &dev->priv; |
a31208b1 | 732 | int err = 0; |
e126ba97 | 733 | |
11f3b84d | 734 | priv->pci_dev_data = id->driver_data; |
e126ba97 | 735 | |
11f3b84d | 736 | pci_set_drvdata(dev->pdev, dev); |
311c7c71 | 737 | |
aa8106f1 | 738 | dev->bar_addr = pci_resource_start(pdev, 0); |
311c7c71 SM |
739 | priv->numa_node = dev_to_node(&dev->pdev->dev); |
740 | ||
89d44f0a | 741 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 742 | if (err) { |
98a8e6fc | 743 | mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); |
11f3b84d | 744 | return err; |
e126ba97 EC |
745 | } |
746 | ||
747 | err = request_bar(pdev); | |
748 | if (err) { | |
98a8e6fc | 749 | mlx5_core_err(dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
750 | goto err_disable; |
751 | } | |
752 | ||
753 | pci_set_master(pdev); | |
754 | ||
755 | err = set_dma_caps(pdev); | |
756 | if (err) { | |
98a8e6fc | 757 | mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); |
e126ba97 EC |
758 | goto err_clr_master; |
759 | } | |
760 | ||
ce4eee53 MG |
761 | if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && |
762 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && | |
763 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) | |
764 | mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); | |
765 | ||
aa8106f1 | 766 | dev->iseg_base = dev->bar_addr; |
e126ba97 EC |
767 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); |
768 | if (!dev->iseg) { | |
769 | err = -ENOMEM; | |
98a8e6fc | 770 | mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); |
e126ba97 EC |
771 | goto err_clr_master; |
772 | } | |
a31208b1 MD |
773 | |
774 | return 0; | |
775 | ||
776 | err_clr_master: | |
777 | pci_clear_master(dev->pdev); | |
778 | release_bar(dev->pdev); | |
779 | err_disable: | |
89d44f0a | 780 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
781 | return err; |
782 | } | |
783 | ||
868bc06b | 784 | static void mlx5_pci_close(struct mlx5_core_dev *dev) |
a31208b1 MD |
785 | { |
786 | iounmap(dev->iseg); | |
787 | pci_clear_master(dev->pdev); | |
788 | release_bar(dev->pdev); | |
89d44f0a | 789 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
790 | } |
791 | ||
868bc06b | 792 | static int mlx5_init_once(struct mlx5_core_dev *dev) |
59211bd3 | 793 | { |
59211bd3 MHY |
794 | int err; |
795 | ||
868bc06b SM |
796 | dev->priv.devcom = mlx5_devcom_register_device(dev); |
797 | if (IS_ERR(dev->priv.devcom)) | |
98a8e6fc HN |
798 | mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", |
799 | dev->priv.devcom); | |
fadd59fc | 800 | |
59211bd3 MHY |
801 | err = mlx5_query_board_id(dev); |
802 | if (err) { | |
98a8e6fc | 803 | mlx5_core_err(dev, "query board id failed\n"); |
fadd59fc | 804 | goto err_devcom; |
59211bd3 MHY |
805 | } |
806 | ||
561aa15a YA |
807 | err = mlx5_irq_table_init(dev); |
808 | if (err) { | |
809 | mlx5_core_err(dev, "failed to initialize irq table\n"); | |
810 | goto err_devcom; | |
811 | } | |
812 | ||
f2f3df55 | 813 | err = mlx5_eq_table_init(dev); |
59211bd3 | 814 | if (err) { |
98a8e6fc | 815 | mlx5_core_err(dev, "failed to initialize eq\n"); |
561aa15a | 816 | goto err_irq_cleanup; |
59211bd3 MHY |
817 | } |
818 | ||
69c1280b SM |
819 | err = mlx5_events_init(dev); |
820 | if (err) { | |
98a8e6fc | 821 | mlx5_core_err(dev, "failed to initialize events\n"); |
69c1280b SM |
822 | goto err_eq_cleanup; |
823 | } | |
824 | ||
02d92f79 | 825 | err = mlx5_cq_debugfs_init(dev); |
59211bd3 | 826 | if (err) { |
98a8e6fc | 827 | mlx5_core_err(dev, "failed to initialize cq debugfs\n"); |
69c1280b | 828 | goto err_events_cleanup; |
59211bd3 MHY |
829 | } |
830 | ||
831 | mlx5_init_qp_table(dev); | |
832 | ||
59211bd3 MHY |
833 | mlx5_init_mkey_table(dev); |
834 | ||
52ec462e IT |
835 | mlx5_init_reserved_gids(dev); |
836 | ||
7c39afb3 FD |
837 | mlx5_init_clock(dev); |
838 | ||
358aa5ce SM |
839 | dev->vxlan = mlx5_vxlan_create(dev); |
840 | ||
59211bd3 MHY |
841 | err = mlx5_init_rl_table(dev); |
842 | if (err) { | |
98a8e6fc | 843 | mlx5_core_err(dev, "Failed to init rate limiting\n"); |
59211bd3 MHY |
844 | goto err_tables_cleanup; |
845 | } | |
846 | ||
eeb66cdb SM |
847 | err = mlx5_mpfs_init(dev); |
848 | if (err) { | |
98a8e6fc | 849 | mlx5_core_err(dev, "Failed to init l2 table %d\n", err); |
eeb66cdb SM |
850 | goto err_rl_cleanup; |
851 | } | |
852 | ||
86eec50b | 853 | err = mlx5_sriov_init(dev); |
c2d6e31a | 854 | if (err) { |
86eec50b | 855 | mlx5_core_err(dev, "Failed to init sriov %d\n", err); |
eeb66cdb | 856 | goto err_mpfs_cleanup; |
c2d6e31a | 857 | } |
c2d6e31a | 858 | |
86eec50b | 859 | err = mlx5_eswitch_init(dev); |
c2d6e31a | 860 | if (err) { |
86eec50b BW |
861 | mlx5_core_err(dev, "Failed to init eswitch %d\n", err); |
862 | goto err_sriov_cleanup; | |
c2d6e31a MHY |
863 | } |
864 | ||
9410733c IT |
865 | err = mlx5_fpga_init(dev); |
866 | if (err) { | |
98a8e6fc | 867 | mlx5_core_err(dev, "Failed to init fpga device %d\n", err); |
86eec50b | 868 | goto err_eswitch_cleanup; |
9410733c IT |
869 | } |
870 | ||
24406953 FD |
871 | dev->tracer = mlx5_fw_tracer_create(dev); |
872 | ||
59211bd3 MHY |
873 | return 0; |
874 | ||
c2d6e31a | 875 | err_eswitch_cleanup: |
c2d6e31a | 876 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
86eec50b BW |
877 | err_sriov_cleanup: |
878 | mlx5_sriov_cleanup(dev); | |
eeb66cdb | 879 | err_mpfs_cleanup: |
eeb66cdb | 880 | mlx5_mpfs_cleanup(dev); |
c2d6e31a | 881 | err_rl_cleanup: |
c2d6e31a | 882 | mlx5_cleanup_rl_table(dev); |
59211bd3 | 883 | err_tables_cleanup: |
358aa5ce | 884 | mlx5_vxlan_destroy(dev->vxlan); |
59211bd3 | 885 | mlx5_cleanup_mkey_table(dev); |
59211bd3 | 886 | mlx5_cleanup_qp_table(dev); |
02d92f79 | 887 | mlx5_cq_debugfs_cleanup(dev); |
69c1280b SM |
888 | err_events_cleanup: |
889 | mlx5_events_cleanup(dev); | |
59211bd3 | 890 | err_eq_cleanup: |
f2f3df55 | 891 | mlx5_eq_table_cleanup(dev); |
561aa15a YA |
892 | err_irq_cleanup: |
893 | mlx5_irq_table_cleanup(dev); | |
fadd59fc AH |
894 | err_devcom: |
895 | mlx5_devcom_unregister_device(dev->priv.devcom); | |
59211bd3 | 896 | |
59211bd3 MHY |
897 | return err; |
898 | } | |
899 | ||
900 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
901 | { | |
24406953 | 902 | mlx5_fw_tracer_destroy(dev->tracer); |
9410733c | 903 | mlx5_fpga_cleanup(dev); |
c2d6e31a | 904 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
86eec50b | 905 | mlx5_sriov_cleanup(dev); |
eeb66cdb | 906 | mlx5_mpfs_cleanup(dev); |
59211bd3 | 907 | mlx5_cleanup_rl_table(dev); |
358aa5ce | 908 | mlx5_vxlan_destroy(dev->vxlan); |
7c39afb3 | 909 | mlx5_cleanup_clock(dev); |
52ec462e | 910 | mlx5_cleanup_reserved_gids(dev); |
59211bd3 | 911 | mlx5_cleanup_mkey_table(dev); |
59211bd3 | 912 | mlx5_cleanup_qp_table(dev); |
02d92f79 | 913 | mlx5_cq_debugfs_cleanup(dev); |
69c1280b | 914 | mlx5_events_cleanup(dev); |
f2f3df55 | 915 | mlx5_eq_table_cleanup(dev); |
561aa15a | 916 | mlx5_irq_table_cleanup(dev); |
fadd59fc | 917 | mlx5_devcom_unregister_device(dev->priv.devcom); |
59211bd3 MHY |
918 | } |
919 | ||
e161105e | 920 | static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) |
a31208b1 | 921 | { |
a31208b1 MD |
922 | int err; |
923 | ||
98a8e6fc HN |
924 | mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
925 | fw_rev_min(dev), fw_rev_sub(dev)); | |
e126ba97 | 926 | |
00c6bcb0 TG |
927 | /* Only PFs hold the relevant PCIe information for this query */ |
928 | if (mlx5_core_is_pf(dev)) | |
929 | pcie_print_link_status(dev->pdev); | |
930 | ||
6c780a02 EC |
931 | /* wait for firmware to accept initialization segments configurations |
932 | */ | |
b8a92577 | 933 | err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); |
6c780a02 | 934 | if (err) { |
98a8e6fc HN |
935 | mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", |
936 | FW_PRE_INIT_TIMEOUT_MILI); | |
e161105e | 937 | return err; |
6c780a02 EC |
938 | } |
939 | ||
e126ba97 EC |
940 | err = mlx5_cmd_init(dev); |
941 | if (err) { | |
98a8e6fc | 942 | mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); |
e161105e | 943 | return err; |
e126ba97 EC |
944 | } |
945 | ||
b8a92577 | 946 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); |
e3297246 | 947 | if (err) { |
98a8e6fc HN |
948 | mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", |
949 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 950 | goto err_cmd_cleanup; |
e3297246 EC |
951 | } |
952 | ||
0b107106 | 953 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b | 954 | if (err) { |
98a8e6fc | 955 | mlx5_core_err(dev, "enable hca failed\n"); |
59211bd3 | 956 | goto err_cmd_cleanup; |
cd23b14b EC |
957 | } |
958 | ||
f62b8bb8 AV |
959 | err = mlx5_core_set_issi(dev); |
960 | if (err) { | |
98a8e6fc | 961 | mlx5_core_err(dev, "failed to set issi\n"); |
f62b8bb8 AV |
962 | goto err_disable_hca; |
963 | } | |
f62b8bb8 | 964 | |
cd23b14b EC |
965 | err = mlx5_satisfy_startup_pages(dev, 1); |
966 | if (err) { | |
98a8e6fc | 967 | mlx5_core_err(dev, "failed to allocate boot pages\n"); |
cd23b14b EC |
968 | goto err_disable_hca; |
969 | } | |
970 | ||
e126ba97 EC |
971 | err = set_hca_ctrl(dev); |
972 | if (err) { | |
98a8e6fc | 973 | mlx5_core_err(dev, "set_hca_ctrl failed\n"); |
cd23b14b | 974 | goto reclaim_boot_pages; |
e126ba97 EC |
975 | } |
976 | ||
37b6bb77 | 977 | err = set_hca_cap(dev); |
f91e6d89 | 978 | if (err) { |
98a8e6fc | 979 | mlx5_core_err(dev, "set_hca_cap failed\n"); |
46861e3e MS |
980 | goto reclaim_boot_pages; |
981 | } | |
982 | ||
cd23b14b | 983 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 984 | if (err) { |
98a8e6fc | 985 | mlx5_core_err(dev, "failed to allocate init pages\n"); |
cd23b14b | 986 | goto reclaim_boot_pages; |
e126ba97 EC |
987 | } |
988 | ||
8737f818 | 989 | err = mlx5_cmd_init_hca(dev, sw_owner_id); |
e126ba97 | 990 | if (err) { |
98a8e6fc | 991 | mlx5_core_err(dev, "init hca failed\n"); |
0cf53c12 | 992 | goto reclaim_boot_pages; |
e126ba97 EC |
993 | } |
994 | ||
012e50e1 HN |
995 | mlx5_set_driver_version(dev); |
996 | ||
e126ba97 EC |
997 | mlx5_start_health_poll(dev); |
998 | ||
bba1574c DJ |
999 | err = mlx5_query_hca_caps(dev); |
1000 | if (err) { | |
98a8e6fc | 1001 | mlx5_core_err(dev, "query hca failed\n"); |
e161105e | 1002 | goto stop_health; |
bba1574c DJ |
1003 | } |
1004 | ||
e161105e SM |
1005 | return 0; |
1006 | ||
1007 | stop_health: | |
1008 | mlx5_stop_health_poll(dev, boot); | |
1009 | reclaim_boot_pages: | |
1010 | mlx5_reclaim_startup_pages(dev); | |
1011 | err_disable_hca: | |
1012 | mlx5_core_disable_hca(dev, 0); | |
1013 | err_cmd_cleanup: | |
1014 | mlx5_cmd_cleanup(dev); | |
1015 | ||
1016 | return err; | |
1017 | } | |
1018 | ||
1019 | static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) | |
1020 | { | |
1021 | int err; | |
1022 | ||
1023 | mlx5_stop_health_poll(dev, boot); | |
1024 | err = mlx5_cmd_teardown_hca(dev); | |
1025 | if (err) { | |
98a8e6fc | 1026 | mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); |
e161105e | 1027 | return err; |
e126ba97 | 1028 | } |
e161105e SM |
1029 | mlx5_reclaim_startup_pages(dev); |
1030 | mlx5_core_disable_hca(dev, 0); | |
1031 | mlx5_cmd_cleanup(dev); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
a80d1b68 | 1036 | static int mlx5_load(struct mlx5_core_dev *dev) |
e161105e | 1037 | { |
e161105e | 1038 | int err; |
e126ba97 | 1039 | |
01187175 | 1040 | dev->priv.uar = mlx5_get_uars_page(dev); |
72f36be0 | 1041 | if (IS_ERR(dev->priv.uar)) { |
98a8e6fc | 1042 | mlx5_core_err(dev, "Failed allocating uar, aborting\n"); |
72f36be0 | 1043 | err = PTR_ERR(dev->priv.uar); |
a80d1b68 | 1044 | return err; |
e126ba97 EC |
1045 | } |
1046 | ||
69c1280b | 1047 | mlx5_events_start(dev); |
0cf53c12 SM |
1048 | mlx5_pagealloc_start(dev); |
1049 | ||
c8e21b3b | 1050 | err = mlx5_eq_table_create(dev); |
e126ba97 | 1051 | if (err) { |
98a8e6fc | 1052 | mlx5_core_err(dev, "Failed to create EQs\n"); |
c8e21b3b | 1053 | goto err_eq_table; |
e126ba97 EC |
1054 | } |
1055 | ||
24406953 FD |
1056 | err = mlx5_fw_tracer_init(dev->tracer); |
1057 | if (err) { | |
98a8e6fc | 1058 | mlx5_core_err(dev, "Failed to init FW tracer\n"); |
24406953 FD |
1059 | goto err_fw_tracer; |
1060 | } | |
1061 | ||
04e87170 MB |
1062 | err = mlx5_fpga_device_start(dev); |
1063 | if (err) { | |
98a8e6fc | 1064 | mlx5_core_err(dev, "fpga device start failed %d\n", err); |
04e87170 MB |
1065 | goto err_fpga_start; |
1066 | } | |
1067 | ||
1068 | err = mlx5_accel_ipsec_init(dev); | |
1069 | if (err) { | |
98a8e6fc | 1070 | mlx5_core_err(dev, "IPSec device start failed %d\n", err); |
04e87170 MB |
1071 | goto err_ipsec_start; |
1072 | } | |
1073 | ||
1ae17322 IL |
1074 | err = mlx5_accel_tls_init(dev); |
1075 | if (err) { | |
98a8e6fc | 1076 | mlx5_core_err(dev, "TLS device start failed %d\n", err); |
1ae17322 IL |
1077 | goto err_tls_start; |
1078 | } | |
1079 | ||
86d722ad | 1080 | err = mlx5_init_fs(dev); |
59211bd3 | 1081 | if (err) { |
98a8e6fc | 1082 | mlx5_core_err(dev, "Failed to init flow steering\n"); |
c85023e1 | 1083 | goto err_fs; |
59211bd3 | 1084 | } |
e126ba97 | 1085 | |
c85023e1 | 1086 | err = mlx5_core_set_hca_defaults(dev); |
86d722ad | 1087 | if (err) { |
98a8e6fc | 1088 | mlx5_core_err(dev, "Failed to set hca defaults\n"); |
86d722ad MG |
1089 | goto err_fs; |
1090 | } | |
1466cc5b | 1091 | |
c2d6e31a | 1092 | err = mlx5_sriov_attach(dev); |
fc50db98 | 1093 | if (err) { |
98a8e6fc | 1094 | mlx5_core_err(dev, "sriov init failed %d\n", err); |
fc50db98 EC |
1095 | goto err_sriov; |
1096 | } | |
1097 | ||
22e939a9 BW |
1098 | err = mlx5_ec_init(dev); |
1099 | if (err) { | |
98a8e6fc | 1100 | mlx5_core_err(dev, "Failed to init embedded CPU\n"); |
22e939a9 BW |
1101 | goto err_ec; |
1102 | } | |
1103 | ||
e126ba97 EC |
1104 | return 0; |
1105 | ||
22e939a9 | 1106 | err_ec: |
c2d6e31a | 1107 | mlx5_sriov_detach(dev); |
59211bd3 | 1108 | err_sriov: |
86d722ad MG |
1109 | mlx5_cleanup_fs(dev); |
1110 | err_fs: | |
1ae17322 | 1111 | mlx5_accel_tls_cleanup(dev); |
1ae17322 | 1112 | err_tls_start: |
04e87170 | 1113 | mlx5_accel_ipsec_cleanup(dev); |
04e87170 MB |
1114 | err_ipsec_start: |
1115 | mlx5_fpga_device_stop(dev); | |
04e87170 | 1116 | err_fpga_start: |
24406953 | 1117 | mlx5_fw_tracer_cleanup(dev->tracer); |
24406953 | 1118 | err_fw_tracer: |
c8e21b3b | 1119 | mlx5_eq_table_destroy(dev); |
c8e21b3b | 1120 | err_eq_table: |
0cf53c12 | 1121 | mlx5_pagealloc_stop(dev); |
69c1280b | 1122 | mlx5_events_stop(dev); |
868bc06b | 1123 | mlx5_put_uars_page(dev, dev->priv.uar); |
a80d1b68 SM |
1124 | return err; |
1125 | } | |
e126ba97 | 1126 | |
a80d1b68 SM |
1127 | static void mlx5_unload(struct mlx5_core_dev *dev) |
1128 | { | |
1129 | mlx5_ec_cleanup(dev); | |
1130 | mlx5_sriov_detach(dev); | |
1131 | mlx5_cleanup_fs(dev); | |
1132 | mlx5_accel_ipsec_cleanup(dev); | |
1133 | mlx5_accel_tls_cleanup(dev); | |
1134 | mlx5_fpga_device_stop(dev); | |
1135 | mlx5_fw_tracer_cleanup(dev->tracer); | |
1136 | mlx5_eq_table_destroy(dev); | |
1137 | mlx5_pagealloc_stop(dev); | |
1138 | mlx5_events_stop(dev); | |
1139 | mlx5_put_uars_page(dev, dev->priv.uar); | |
1140 | } | |
59211bd3 | 1141 | |
a80d1b68 SM |
1142 | static int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) |
1143 | { | |
a80d1b68 SM |
1144 | int err = 0; |
1145 | ||
1146 | dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); | |
1147 | mutex_lock(&dev->intf_state_mutex); | |
1148 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { | |
1149 | mlx5_core_warn(dev, "interface is up, NOP\n"); | |
1150 | goto out; | |
1bde6e30 | 1151 | } |
a80d1b68 SM |
1152 | /* remove any previous indication of internal error */ |
1153 | dev->state = MLX5_DEVICE_STATE_UP; | |
e126ba97 | 1154 | |
a80d1b68 SM |
1155 | err = mlx5_function_setup(dev, boot); |
1156 | if (err) | |
1157 | goto out; | |
e126ba97 | 1158 | |
a80d1b68 SM |
1159 | if (boot) { |
1160 | err = mlx5_init_once(dev); | |
1161 | if (err) { | |
98a8e6fc | 1162 | mlx5_core_err(dev, "sw objs init failed\n"); |
a80d1b68 SM |
1163 | goto function_teardown; |
1164 | } | |
1165 | } | |
cd23b14b | 1166 | |
a80d1b68 SM |
1167 | err = mlx5_load(dev); |
1168 | if (err) | |
1169 | goto err_load; | |
e126ba97 | 1170 | |
a80d1b68 SM |
1171 | if (mlx5_device_registered(dev)) { |
1172 | mlx5_attach_device(dev); | |
1173 | } else { | |
1174 | err = mlx5_register_device(dev); | |
1175 | if (err) { | |
98a8e6fc | 1176 | mlx5_core_err(dev, "register device failed %d\n", err); |
a80d1b68 SM |
1177 | goto err_reg_dev; |
1178 | } | |
1179 | } | |
1180 | ||
1181 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
1182 | out: | |
1183 | mutex_unlock(&dev->intf_state_mutex); | |
e126ba97 | 1184 | |
a80d1b68 SM |
1185 | return err; |
1186 | ||
1187 | err_reg_dev: | |
1188 | mlx5_unload(dev); | |
1189 | err_load: | |
59211bd3 MHY |
1190 | if (boot) |
1191 | mlx5_cleanup_once(dev); | |
e161105e SM |
1192 | function_teardown: |
1193 | mlx5_function_teardown(dev, boot); | |
89d44f0a MD |
1194 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; |
1195 | mutex_unlock(&dev->intf_state_mutex); | |
1196 | ||
e126ba97 EC |
1197 | return err; |
1198 | } | |
e126ba97 | 1199 | |
868bc06b | 1200 | static int mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) |
e126ba97 | 1201 | { |
89d44f0a | 1202 | int err = 0; |
e126ba97 | 1203 | |
5e44fca5 | 1204 | if (cleanup) |
2a0165a0 | 1205 | mlx5_drain_health_recovery(dev); |
689a248d | 1206 | |
89d44f0a | 1207 | mutex_lock(&dev->intf_state_mutex); |
b3cb5388 | 1208 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
98a8e6fc HN |
1209 | mlx5_core_warn(dev, "%s: interface is down, NOP\n", |
1210 | __func__); | |
59211bd3 MHY |
1211 | if (cleanup) |
1212 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1213 | goto out; |
1214 | } | |
6b6adee3 | 1215 | |
9ade8c7c | 1216 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
9ade8c7c | 1217 | |
737a234b MHY |
1218 | if (mlx5_device_registered(dev)) |
1219 | mlx5_detach_device(dev); | |
1220 | ||
a80d1b68 SM |
1221 | mlx5_unload(dev); |
1222 | ||
59211bd3 MHY |
1223 | if (cleanup) |
1224 | mlx5_cleanup_once(dev); | |
9603b61d | 1225 | |
e161105e | 1226 | mlx5_function_teardown(dev, cleanup); |
ac6ea6e8 | 1227 | out: |
89d44f0a | 1228 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1229 | return err; |
9603b61d | 1230 | } |
64613d94 | 1231 | |
feae9087 | 1232 | static const struct devlink_ops mlx5_devlink_ops = { |
e80541ec | 1233 | #ifdef CONFIG_MLX5_ESWITCH |
feae9087 OG |
1234 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, |
1235 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
bffaa916 RD |
1236 | .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, |
1237 | .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, | |
7768d197 RD |
1238 | .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, |
1239 | .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, | |
feae9087 OG |
1240 | #endif |
1241 | }; | |
f66f049f | 1242 | |
27b942fb | 1243 | static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) |
9603b61d | 1244 | { |
11f3b84d | 1245 | struct mlx5_priv *priv = &dev->priv; |
9603b61d JM |
1246 | int err; |
1247 | ||
11f3b84d | 1248 | dev->profile = &profile[profile_idx]; |
9603b61d | 1249 | |
364d1798 EC |
1250 | INIT_LIST_HEAD(&priv->ctx_list); |
1251 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1252 | mutex_init(&dev->pci_status_mutex); |
1253 | mutex_init(&dev->intf_state_mutex); | |
d9aaed83 | 1254 | |
01187175 EC |
1255 | mutex_init(&priv->bfregs.reg_head.lock); |
1256 | mutex_init(&priv->bfregs.wc_head.lock); | |
1257 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1258 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1259 | ||
11f3b84d SM |
1260 | mutex_init(&priv->alloc_mutex); |
1261 | mutex_init(&priv->pgdir_mutex); | |
1262 | INIT_LIST_HEAD(&priv->pgdir_list); | |
1263 | spin_lock_init(&priv->mkey_lock); | |
1264 | ||
27b942fb PP |
1265 | priv->dbg_root = debugfs_create_dir(dev_name(dev->device), |
1266 | mlx5_debugfs_root); | |
11f3b84d | 1267 | if (!priv->dbg_root) { |
27b942fb | 1268 | dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); |
11f3b84d | 1269 | return -ENOMEM; |
9603b61d JM |
1270 | } |
1271 | ||
ac6ea6e8 | 1272 | err = mlx5_health_init(dev); |
52c368dc SM |
1273 | if (err) |
1274 | goto err_health_init; | |
ac6ea6e8 | 1275 | |
0cf53c12 SM |
1276 | err = mlx5_pagealloc_init(dev); |
1277 | if (err) | |
1278 | goto err_pagealloc_init; | |
59211bd3 | 1279 | |
11f3b84d | 1280 | return 0; |
52c368dc SM |
1281 | |
1282 | err_pagealloc_init: | |
1283 | mlx5_health_cleanup(dev); | |
1284 | err_health_init: | |
1285 | debugfs_remove(dev->priv.dbg_root); | |
1286 | ||
1287 | return err; | |
11f3b84d SM |
1288 | } |
1289 | ||
1290 | static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) | |
1291 | { | |
52c368dc SM |
1292 | mlx5_pagealloc_cleanup(dev); |
1293 | mlx5_health_cleanup(dev); | |
11f3b84d SM |
1294 | debugfs_remove_recursive(dev->priv.dbg_root); |
1295 | } | |
1296 | ||
59211bd3 | 1297 | #define MLX5_IB_MOD "mlx5_ib" |
11f3b84d | 1298 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
9603b61d JM |
1299 | { |
1300 | struct mlx5_core_dev *dev; | |
feae9087 | 1301 | struct devlink *devlink; |
9603b61d JM |
1302 | int err; |
1303 | ||
feae9087 OG |
1304 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1305 | if (!devlink) { | |
9603b61d JM |
1306 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1307 | return -ENOMEM; | |
1308 | } | |
feae9087 OG |
1309 | |
1310 | dev = devlink_priv(devlink); | |
27b942fb PP |
1311 | dev->device = &pdev->dev; |
1312 | dev->pdev = pdev; | |
9603b61d | 1313 | |
27b942fb | 1314 | err = mlx5_mdev_init(dev, prof_sel); |
11f3b84d SM |
1315 | if (err) |
1316 | goto mdev_init_err; | |
01187175 | 1317 | |
11f3b84d | 1318 | err = mlx5_pci_init(dev, pdev, id); |
9603b61d | 1319 | if (err) { |
98a8e6fc HN |
1320 | mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", |
1321 | err); | |
11f3b84d | 1322 | goto pci_init_err; |
9603b61d JM |
1323 | } |
1324 | ||
868bc06b | 1325 | err = mlx5_load_one(dev, true); |
9603b61d | 1326 | if (err) { |
98a8e6fc HN |
1327 | mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", |
1328 | err); | |
0cf53c12 | 1329 | goto err_load_one; |
9603b61d | 1330 | } |
59211bd3 | 1331 | |
f82eed45 | 1332 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1333 | |
feae9087 OG |
1334 | err = devlink_register(devlink, &pdev->dev); |
1335 | if (err) | |
1336 | goto clean_load; | |
1337 | ||
5d47f6c8 | 1338 | pci_save_state(pdev); |
9603b61d JM |
1339 | return 0; |
1340 | ||
feae9087 | 1341 | clean_load: |
868bc06b | 1342 | mlx5_unload_one(dev, true); |
52c368dc | 1343 | |
0cf53c12 | 1344 | err_load_one: |
868bc06b | 1345 | mlx5_pci_close(dev); |
11f3b84d SM |
1346 | pci_init_err: |
1347 | mlx5_mdev_uninit(dev); | |
1348 | mdev_init_err: | |
feae9087 | 1349 | devlink_free(devlink); |
a31208b1 | 1350 | |
9603b61d JM |
1351 | return err; |
1352 | } | |
a31208b1 | 1353 | |
9603b61d JM |
1354 | static void remove_one(struct pci_dev *pdev) |
1355 | { | |
1356 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1357 | struct devlink *devlink = priv_to_devlink(dev); |
9603b61d | 1358 | |
feae9087 | 1359 | devlink_unregister(devlink); |
737a234b MHY |
1360 | mlx5_unregister_device(dev); |
1361 | ||
868bc06b | 1362 | if (mlx5_unload_one(dev, true)) { |
98a8e6fc | 1363 | mlx5_core_err(dev, "mlx5_unload_one failed\n"); |
52c368dc | 1364 | mlx5_health_flush(dev); |
a31208b1 MD |
1365 | return; |
1366 | } | |
737a234b | 1367 | |
868bc06b | 1368 | mlx5_pci_close(dev); |
11f3b84d | 1369 | mlx5_mdev_uninit(dev); |
feae9087 | 1370 | devlink_free(devlink); |
9603b61d JM |
1371 | } |
1372 | ||
89d44f0a MD |
1373 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1374 | pci_channel_state_t state) | |
1375 | { | |
1376 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a | 1377 | |
98a8e6fc | 1378 | mlx5_core_info(dev, "%s was called\n", __func__); |
04c0c1ab | 1379 | |
8812c24d | 1380 | mlx5_enter_error_state(dev, false); |
868bc06b | 1381 | mlx5_unload_one(dev, false); |
5d47f6c8 | 1382 | /* In case of kernel call drain the health wq */ |
05ac2c0b | 1383 | if (state) { |
5e44fca5 | 1384 | mlx5_drain_health_wq(dev); |
05ac2c0b MHY |
1385 | mlx5_pci_disable_device(dev); |
1386 | } | |
1387 | ||
89d44f0a MD |
1388 | return state == pci_channel_io_perm_failure ? |
1389 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1390 | } | |
1391 | ||
d57847dc DJ |
1392 | /* wait for the device to show vital signs by waiting |
1393 | * for the health counter to start counting. | |
89d44f0a | 1394 | */ |
d57847dc | 1395 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1396 | { |
1397 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1398 | struct mlx5_core_health *health = &dev->priv.health; | |
1399 | const int niter = 100; | |
d57847dc | 1400 | u32 last_count = 0; |
89d44f0a | 1401 | u32 count; |
89d44f0a MD |
1402 | int i; |
1403 | ||
89d44f0a MD |
1404 | for (i = 0; i < niter; i++) { |
1405 | count = ioread32be(health->health_counter); | |
1406 | if (count && count != 0xffffffff) { | |
d57847dc | 1407 | if (last_count && last_count != count) { |
98a8e6fc HN |
1408 | mlx5_core_info(dev, |
1409 | "wait vital counter value 0x%x after %d iterations\n", | |
1410 | count, i); | |
d57847dc DJ |
1411 | return 0; |
1412 | } | |
1413 | last_count = count; | |
89d44f0a MD |
1414 | } |
1415 | msleep(50); | |
1416 | } | |
1417 | ||
d57847dc | 1418 | return -ETIMEDOUT; |
89d44f0a MD |
1419 | } |
1420 | ||
1061c90f | 1421 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1422 | { |
1423 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1424 | int err; |
1425 | ||
98a8e6fc | 1426 | mlx5_core_info(dev, "%s was called\n", __func__); |
89d44f0a | 1427 | |
1061c90f | 1428 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1429 | if (err) { |
98a8e6fc HN |
1430 | mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", |
1431 | __func__, err); | |
1061c90f MHY |
1432 | return PCI_ERS_RESULT_DISCONNECT; |
1433 | } | |
1434 | ||
1435 | pci_set_master(pdev); | |
1436 | pci_restore_state(pdev); | |
5d47f6c8 | 1437 | pci_save_state(pdev); |
1061c90f MHY |
1438 | |
1439 | if (wait_vital(pdev)) { | |
98a8e6fc | 1440 | mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1441 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1442 | } |
89d44f0a | 1443 | |
1061c90f MHY |
1444 | return PCI_ERS_RESULT_RECOVERED; |
1445 | } | |
1446 | ||
1061c90f MHY |
1447 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1448 | { | |
1449 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1061c90f MHY |
1450 | int err; |
1451 | ||
98a8e6fc | 1452 | mlx5_core_info(dev, "%s was called\n", __func__); |
1061c90f | 1453 | |
868bc06b | 1454 | err = mlx5_load_one(dev, false); |
89d44f0a | 1455 | if (err) |
98a8e6fc HN |
1456 | mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", |
1457 | __func__, err); | |
89d44f0a | 1458 | else |
98a8e6fc | 1459 | mlx5_core_info(dev, "%s: device recovered\n", __func__); |
89d44f0a MD |
1460 | } |
1461 | ||
1462 | static const struct pci_error_handlers mlx5_err_handler = { | |
1463 | .error_detected = mlx5_pci_err_detected, | |
1464 | .slot_reset = mlx5_pci_slot_reset, | |
1465 | .resume = mlx5_pci_resume | |
1466 | }; | |
1467 | ||
8812c24d MD |
1468 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1469 | { | |
fcd29ad1 FD |
1470 | bool fast_teardown = false, force_teardown = false; |
1471 | int ret = 1; | |
1472 | ||
1473 | fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); | |
1474 | force_teardown = MLX5_CAP_GEN(dev, force_teardown); | |
1475 | ||
1476 | mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); | |
1477 | mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); | |
8812c24d | 1478 | |
fcd29ad1 | 1479 | if (!fast_teardown && !force_teardown) |
8812c24d | 1480 | return -EOPNOTSUPP; |
8812c24d MD |
1481 | |
1482 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1483 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1484 | return -EAGAIN; | |
1485 | } | |
1486 | ||
d2aa060d HN |
1487 | /* Panic tear down fw command will stop the PCI bus communication |
1488 | * with the HCA, so the health polll is no longer needed. | |
1489 | */ | |
1490 | mlx5_drain_health_wq(dev); | |
76d5581c | 1491 | mlx5_stop_health_poll(dev, false); |
d2aa060d | 1492 | |
fcd29ad1 FD |
1493 | ret = mlx5_cmd_fast_teardown_hca(dev); |
1494 | if (!ret) | |
1495 | goto succeed; | |
1496 | ||
8812c24d | 1497 | ret = mlx5_cmd_force_teardown_hca(dev); |
fcd29ad1 FD |
1498 | if (!ret) |
1499 | goto succeed; | |
1500 | ||
1501 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1502 | mlx5_start_health_poll(dev); | |
1503 | return ret; | |
8812c24d | 1504 | |
fcd29ad1 | 1505 | succeed: |
8812c24d MD |
1506 | mlx5_enter_error_state(dev, true); |
1507 | ||
1ef903bf DJ |
1508 | /* Some platforms requiring freeing the IRQ's in the shutdown |
1509 | * flow. If they aren't freed they can't be allocated after | |
1510 | * kexec. There is no need to cleanup the mlx5_core software | |
1511 | * contexts. | |
1512 | */ | |
1ef903bf DJ |
1513 | mlx5_core_eq_free_irqs(dev); |
1514 | ||
8812c24d MD |
1515 | return 0; |
1516 | } | |
1517 | ||
5fc7197d MD |
1518 | static void shutdown(struct pci_dev *pdev) |
1519 | { | |
1520 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
8812c24d | 1521 | int err; |
5fc7197d | 1522 | |
98a8e6fc | 1523 | mlx5_core_info(dev, "Shutdown was called\n"); |
8812c24d MD |
1524 | err = mlx5_try_fast_unload(dev); |
1525 | if (err) | |
868bc06b | 1526 | mlx5_unload_one(dev, false); |
5fc7197d MD |
1527 | mlx5_pci_disable_device(dev); |
1528 | } | |
1529 | ||
9603b61d | 1530 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1531 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1532 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1533 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1534 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1535 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1536 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1537 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1538 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1539 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1540 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1541 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1542 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
85327a9c EBE |
1543 | { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ |
1544 | { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ | |
2e9d3e83 NO |
1545 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1546 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
9603b61d JM |
1547 | { 0, } |
1548 | }; | |
1549 | ||
1550 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1551 | ||
04c0c1ab MHY |
1552 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1553 | { | |
1554 | mlx5_pci_err_detected(dev->pdev, 0); | |
1555 | } | |
1556 | ||
1557 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1558 | { | |
1559 | mlx5_pci_disable_device(dev); | |
1560 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1561 | mlx5_pci_resume(dev->pdev); | |
1562 | } | |
1563 | ||
9603b61d JM |
1564 | static struct pci_driver mlx5_core_driver = { |
1565 | .name = DRIVER_NAME, | |
1566 | .id_table = mlx5_core_pci_table, | |
1567 | .probe = init_one, | |
89d44f0a | 1568 | .remove = remove_one, |
5fc7197d | 1569 | .shutdown = shutdown, |
fc50db98 EC |
1570 | .err_handler = &mlx5_err_handler, |
1571 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1572 | }; |
e126ba97 | 1573 | |
f663ad98 KH |
1574 | static void mlx5_core_verify_params(void) |
1575 | { | |
1576 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1577 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1578 | prof_sel, | |
1579 | ARRAY_SIZE(profile) - 1, | |
1580 | MLX5_DEFAULT_PROF); | |
1581 | prof_sel = MLX5_DEFAULT_PROF; | |
1582 | } | |
1583 | } | |
1584 | ||
e126ba97 EC |
1585 | static int __init init(void) |
1586 | { | |
1587 | int err; | |
1588 | ||
8737f818 DJ |
1589 | get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); |
1590 | ||
f663ad98 | 1591 | mlx5_core_verify_params(); |
05564d0a | 1592 | mlx5_fpga_ipsec_build_fs_cmds(); |
e126ba97 | 1593 | mlx5_register_debugfs(); |
e126ba97 | 1594 | |
9603b61d JM |
1595 | err = pci_register_driver(&mlx5_core_driver); |
1596 | if (err) | |
ac6ea6e8 | 1597 | goto err_debug; |
9603b61d | 1598 | |
f62b8bb8 AV |
1599 | #ifdef CONFIG_MLX5_CORE_EN |
1600 | mlx5e_init(); | |
1601 | #endif | |
1602 | ||
e126ba97 EC |
1603 | return 0; |
1604 | ||
e126ba97 EC |
1605 | err_debug: |
1606 | mlx5_unregister_debugfs(); | |
1607 | return err; | |
1608 | } | |
1609 | ||
1610 | static void __exit cleanup(void) | |
1611 | { | |
f62b8bb8 AV |
1612 | #ifdef CONFIG_MLX5_CORE_EN |
1613 | mlx5e_cleanup(); | |
1614 | #endif | |
9603b61d | 1615 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1616 | mlx5_unregister_debugfs(); |
1617 | } | |
1618 | ||
1619 | module_init(init); | |
1620 | module_exit(cleanup); |