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IB/mlx5: Don't advertise RAW QP support in dual port mode
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
b775516b 49#include <linux/mlx5/mlx5_ifc.h>
c85023e1 50#include <linux/mlx5/vport.h>
5a7b27eb
MG		 51#ifdef CONFIG_RFS_ACCEL
52#include <linux/cpu_rmap.h>
53#endif
feae9087 54#include <net/devlink.h>
e126ba97 55#include "mlx5_core.h"
86d722ad 56#include "fs_core.h"
eeb66cdb 57#include "lib/mpfs.h"
073bb189 58#include "eswitch.h"
52ec462e 59#include "lib/mlx5.h"
e29341fb 60#include "fpga/core.h"
bebb23e6 61#include "accel/ipsec.h"
7c39afb3 62#include "lib/clock.h"
e126ba97 63
e126ba97 64MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 65MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 66MODULE_LICENSE("Dual BSD/GPL");
67MODULE_VERSION(DRIVER_VERSION);
68
f663ad98
KH		 69unsigned int mlx5_core_debug_mask;
70module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
e126ba97
EC		 71MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
72
9603b61d 73#define MLX5_DEFAULT_PROF 2
f663ad98
KH		 74static unsigned int prof_sel = MLX5_DEFAULT_PROF;
75module_param_named(prof_sel, prof_sel, uint, 0444);
9603b61d
JM		 76MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
77
8737f818
DJ		 78static u32 sw_owner_id[4];
79
f91e6d89
EBE		 80enum {
81 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
82 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
83};
84
9603b61d
JM		 85static struct mlx5_profile profile[] = {
86 [0] = {
87 .mask = 0,
88 },
89 [1] = {
90 .mask = MLX5_PROF_MASK_QP_SIZE,
91 .log_max_qp = 12,
92 },
93 [2] = {
94 .mask = MLX5_PROF_MASK_QP_SIZE |
95 MLX5_PROF_MASK_MR_CACHE,
5f40b4ed 96 .log_max_qp = 18,
9603b61d
JM		 97 .mr_cache[0] = {
98 .size = 500,
99 .limit = 250
100 },
101 .mr_cache[1] = {
102 .size = 500,
103 .limit = 250
104 },
105 .mr_cache[2] = {
106 .size = 500,
107 .limit = 250
108 },
109 .mr_cache[3] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[4] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[5] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[6] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[7] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[8] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[9] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[10] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[11] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[12] = {
146 .size = 64,
147 .limit = 32
148 },
149 .mr_cache[13] = {
150 .size = 32,
151 .limit = 16
152 },
153 .mr_cache[14] = {
154 .size = 16,
155 .limit = 8
156 },
157 .mr_cache[15] = {
158 .size = 8,
159 .limit = 4
160 },
7d0cc6ed
AK		 161 .mr_cache[16] = {
162 .size = 8,
163 .limit = 4
164 },
165 .mr_cache[17] = {
166 .size = 8,
167 .limit = 4
168 },
169 .mr_cache[18] = {
170 .size = 8,
171 .limit = 4
172 },
173 .mr_cache[19] = {
174 .size = 4,
175 .limit = 2
176 },
177 .mr_cache[20] = {
178 .size = 4,
179 .limit = 2
180 },
9603b61d
JM		 181 },
182};
e126ba97 183
6c780a02
EC		 184#define FW_INIT_TIMEOUT_MILI 2000
185#define FW_INIT_WAIT_MS 2
186#define FW_PRE_INIT_TIMEOUT_MILI 10000
e3297246
EC		 187
188static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
189{
190 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
191 int err = 0;
192
193 while (fw_initializing(dev)) {
194 if (time_after(jiffies, end)) {
195 err = -EBUSY;
196 break;
197 }
198 msleep(FW_INIT_WAIT_MS);
199 }
200
201 return err;
202}
203
012e50e1
HN		 204static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
205{
206 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
207 driver_version);
208 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
209 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
210 int remaining_size = driver_ver_sz;
211 char *string;
212
213 if (!MLX5_CAP_GEN(dev, driver_version))
214 return;
215
216 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
217
218 strncpy(string, "Linux", remaining_size);
219
220 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
221 strncat(string, ",", remaining_size);
222
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, DRIVER_NAME, remaining_size);
225
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, ",", remaining_size);
228
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, DRIVER_VERSION, remaining_size);
231
232 /*Send the command*/
233 MLX5_SET(set_driver_version_in, in, opcode,
234 MLX5_CMD_OP_SET_DRIVER_VERSION);
235
236 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
237}
238
e126ba97
EC		 239static int set_dma_caps(struct pci_dev *pdev)
240{
241 int err;
242
243 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
244 if (err) {
1a91de28 245 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 246 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
247 if (err) {
1a91de28 248 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 249 return err;
250 }
251 }
252
253 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
254 if (err) {
255 dev_warn(&pdev->dev,
1a91de28 256 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 257 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
258 if (err) {
259 dev_err(&pdev->dev,
1a91de28 260 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 261 return err;
262 }
263 }
264
265 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
266 return err;
267}
268
89d44f0a
MD		 269static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
270{
271 struct pci_dev *pdev = dev->pdev;
272 int err = 0;
273
274 mutex_lock(&dev->pci_status_mutex);
275 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
276 err = pci_enable_device(pdev);
277 if (!err)
278 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
279 }
280 mutex_unlock(&dev->pci_status_mutex);
281
282 return err;
283}
284
285static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
286{
287 struct pci_dev *pdev = dev->pdev;
288
289 mutex_lock(&dev->pci_status_mutex);
290 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
291 pci_disable_device(pdev);
292 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
293 }
294 mutex_unlock(&dev->pci_status_mutex);
295}
296
e126ba97
EC		 297static int request_bar(struct pci_dev *pdev)
298{
299 int err = 0;
300
301 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 302 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 303 return -ENODEV;
304 }
305
306 err = pci_request_regions(pdev, DRIVER_NAME);
307 if (err)
308 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
309
310 return err;
311}
312
313static void release_bar(struct pci_dev *pdev)
314{
315 pci_release_regions(pdev);
316}
317
78249c42 318static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
e126ba97 319{
db058a18
SM		 320 struct mlx5_priv *priv = &dev->priv;
321 struct mlx5_eq_table *table = &priv->eq_table;
a435393a
SG		 322 struct irq_affinity irqdesc = {
323 .pre_vectors = MLX5_EQ_VEC_COMP_BASE,
324 };
938fe83c 325 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 326 int nvec;
e126ba97 327
938fe83c
SM		 328 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
329 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 330 nvec = min_t(int, nvec, num_eqs);
331 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
332 return -ENOMEM;
333
db058a18 334 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
78249c42 335 if (!priv->irq_info)
db058a18 336 goto err_free_msix;
e126ba97 337
a435393a 338 nvec = pci_alloc_irq_vectors_affinity(dev->pdev,
78249c42 339 MLX5_EQ_VEC_COMP_BASE + 1, nvec,
a435393a
SG		 340 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
341 &irqdesc);
f3c9407b
AG		 342 if (nvec < 0)
343 return nvec;
e126ba97 344
f3c9407b 345 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 346
347 return 0;
db058a18
SM		 348
349err_free_msix:
350 kfree(priv->irq_info);
db058a18 351 return -ENOMEM;
e126ba97
EC		 352}
353
78249c42 354static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
e126ba97 355{
db058a18 356 struct mlx5_priv *priv = &dev->priv;
e126ba97 357
78249c42 358 pci_free_irq_vectors(dev->pdev);
db058a18 359 kfree(priv->irq_info);
e126ba97
EC		 360}
361
bd10838a 362struct mlx5_reg_host_endianness {
e126ba97
EC		 363 u8 he;
364 u8 rsvd[15];
365};
366
87b8de49
EC		 367#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
368
369enum {
c7a08ac7
EC		 370 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
371 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 372};
373
2974ab6e 374static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
c7a08ac7
EC		 375{
376 switch (size) {
377 case 128:
378 return 0;
379 case 256:
380 return 1;
381 case 512:
382 return 2;
383 case 1024:
384 return 3;
385 case 2048:
386 return 4;
387 case 4096:
388 return 5;
389 default:
2974ab6e 390 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
c7a08ac7
EC		 391 return 0;
392 }
393}
394
b06e7de8
LR		 395static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
396 enum mlx5_cap_type cap_type,
397 enum mlx5_cap_mode cap_mode)
c7a08ac7 398{
b775516b
EC		 399 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
400 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 401 void *out, *hca_caps;
402 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 403 int err;
404
b775516b
EC		 405 memset(in, 0, sizeof(in));
406 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 407 if (!out)
e126ba97 408 return -ENOMEM;
938fe83c 409
b775516b
EC		 410 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
411 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
412 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
c7a08ac7 413 if (err) {
938fe83c
SM		 414 mlx5_core_warn(dev,
415 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
416 cap_type, cap_mode, err);
e126ba97
EC		 417 goto query_ex;
418 }
c7a08ac7 419
938fe83c
SM		 420 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
421
422 switch (cap_mode) {
423 case HCA_CAP_OPMOD_GET_MAX:
701052c5 424 memcpy(dev->caps.hca_max[cap_type], hca_caps,
938fe83c
SM		 425 MLX5_UN_SZ_BYTES(hca_cap_union));
426 break;
427 case HCA_CAP_OPMOD_GET_CUR:
701052c5 428 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
938fe83c
SM		 429 MLX5_UN_SZ_BYTES(hca_cap_union));
430 break;
431 default:
432 mlx5_core_warn(dev,
433 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
434 cap_type, cap_mode);
435 err = -EINVAL;
436 break;
437 }
c7a08ac7
EC		 438query_ex:
439 kfree(out);
440 return err;
441}
442
b06e7de8
LR		 443int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
444{
445 int ret;
446
447 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
448 if (ret)
449 return ret;
450 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
451}
452
f91e6d89 453static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
c7a08ac7 454{
c4f287c4 455 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
e126ba97 456
b775516b 457 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
f91e6d89 458 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
c4f287c4 459 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
c7a08ac7
EC		 460}
461
f91e6d89
EBE		 462static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
463{
464 void *set_ctx;
465 void *set_hca_cap;
466 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
467 int req_endianness;
468 int err;
469
470 if (MLX5_CAP_GEN(dev, atomic)) {
b06e7de8 471 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
f91e6d89
EBE		 472 if (err)
473 return err;
474 } else {
475 return 0;
476 }
477
478 req_endianness =
479 MLX5_CAP_ATOMIC(dev,
bd10838a 480 supported_atomic_req_8B_endianness_mode_1);
f91e6d89
EBE		 481
482 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
483 return 0;
484
485 set_ctx = kzalloc(set_sz, GFP_KERNEL);
486 if (!set_ctx)
487 return -ENOMEM;
488
489 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
490
491 /* Set requestor to host endianness */
bd10838a 492 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
f91e6d89
EBE		 493 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
494
495 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
496
497 kfree(set_ctx);
498 return err;
499}
500
c7a08ac7
EC		 501static int handle_hca_cap(struct mlx5_core_dev *dev)
502{
b775516b 503 void *set_ctx = NULL;
c7a08ac7 504 struct mlx5_profile *prof = dev->profile;
c7a08ac7 505 int err = -ENOMEM;
b775516b 506 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 507 void *set_hca_cap;
c7a08ac7 508
b775516b 509 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 510 if (!set_ctx)
e126ba97 511 goto query_ex;
e126ba97 512
b06e7de8 513 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
e126ba97
EC		 514 if (err)
515 goto query_ex;
516
938fe83c
SM		 517 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
518 capability);
701052c5 519 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
938fe83c
SM		 520 MLX5_ST_SZ_BYTES(cmd_hca_cap));
521
522 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 523 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 524 128);
c7a08ac7 525 /* we limit the size of the pkey table to 128 entries for now */
938fe83c 526 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
2974ab6e 527 to_fw_pkey_sz(dev, 128));
c7a08ac7 528
883371c4
NO		 529 /* Check log_max_qp from HCA caps to set in current profile */
530 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
531 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
532 profile[prof_sel].log_max_qp,
533 MLX5_CAP_GEN_MAX(dev, log_max_qp));
534 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
535 }
c7a08ac7 536 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 537 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
538 prof->log_max_qp);
c7a08ac7 539
938fe83c
SM		 540 /* disable cmdif checksum */
541 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 542
91828bd8
MD		 543 /* Enable 4K UAR only when HCA supports it and page size is bigger
544 * than 4K.
545 */
546 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
f502d834
EC		 547 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
548
fe1e1876
CS		 549 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
550
f32f5bd2
DJ		 551 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
552 MLX5_SET(cmd_hca_cap,
553 set_hca_cap,
554 cache_line_128byte,
555 cache_line_size() == 128 ? 1 : 0);
556
dd44572a
MS		 557 if (MLX5_CAP_GEN_MAX(dev, dct))
558 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
559
f91e6d89
EBE		 560 err = set_caps(dev, set_ctx, set_sz,
561 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
c7a08ac7 562
e126ba97 563query_ex:
e126ba97 564 kfree(set_ctx);
e126ba97
EC		 565 return err;
566}
567
568static int set_hca_ctrl(struct mlx5_core_dev *dev)
569{
bd10838a
OG		 570 struct mlx5_reg_host_endianness he_in;
571 struct mlx5_reg_host_endianness he_out;
e126ba97
EC		 572 int err;
573
fc50db98
EC		 574 if (!mlx5_core_is_pf(dev))
575 return 0;
576
e126ba97
EC		 577 memset(&he_in, 0, sizeof(he_in));
578 he_in.he = MLX5_SET_HOST_ENDIANNESS;
579 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
580 &he_out, sizeof(he_out),
581 MLX5_REG_HOST_ENDIANNESS, 0, 1);
582 return err;
583}
584
c85023e1
HN		 585static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
586{
587 int ret = 0;
588
589 /* Disable local_lb by default */
590 if ((MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
591 MLX5_CAP_GEN(dev, disable_local_lb))
592 ret = mlx5_nic_vport_update_local_lb(dev, false);
593
594 return ret;
595}
596
0b107106 597int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 598{
c4f287c4
SM		 599 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
600 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
cd23b14b 601
0b107106
EC		 602 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
603 MLX5_SET(enable_hca_in, in, function_id, func_id);
c4f287c4 604 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
cd23b14b
EC		 605}
606
0b107106 607int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 608{
c4f287c4
SM		 609 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
610 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
cd23b14b 611
0b107106
EC		 612 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
613 MLX5_SET(disable_hca_in, in, function_id, func_id);
c4f287c4 614 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
cd23b14b
EC		 615}
616
a5a1d1c2 617u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
b0844444
EBE		 618{
619 u32 timer_h, timer_h1, timer_l;
620
621 timer_h = ioread32be(&dev->iseg->internal_timer_h);
622 timer_l = ioread32be(&dev->iseg->internal_timer_l);
623 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
624 if (timer_h != timer_h1) /* wrap around */
625 timer_l = ioread32be(&dev->iseg->internal_timer_l);
626
a5a1d1c2 627 return (u64)timer_l | (u64)timer_h1 << 32;
b0844444
EBE		 628}
629
0b6e26ce
DT		 630int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
631 unsigned int *irqn)
233d05d2
SM		 632{
633 struct mlx5_eq_table *table = &dev->priv.eq_table;
634 struct mlx5_eq *eq, *n;
635 int err = -ENOENT;
636
637 spin_lock(&table->lock);
638 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
639 if (eq->index == vector) {
640 *eqn = eq->eqn;
641 *irqn = eq->irqn;
642 err = 0;
643 break;
644 }
645 }
646 spin_unlock(&table->lock);
647
648 return err;
649}
650EXPORT_SYMBOL(mlx5_vector2eqn);
651
94c6825e
MB		 652struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
653{
654 struct mlx5_eq_table *table = &dev->priv.eq_table;
655 struct mlx5_eq *eq;
656
657 spin_lock(&table->lock);
658 list_for_each_entry(eq, &table->comp_eqs_list, list)
659 if (eq->eqn == eqn) {
660 spin_unlock(&table->lock);
661 return eq;
662 }
663
664 spin_unlock(&table->lock);
665
666 return ERR_PTR(-ENOENT);
667}
668
233d05d2
SM		 669static void free_comp_eqs(struct mlx5_core_dev *dev)
670{
671 struct mlx5_eq_table *table = &dev->priv.eq_table;
672 struct mlx5_eq *eq, *n;
673
5a7b27eb
MG		 674#ifdef CONFIG_RFS_ACCEL
675 if (dev->rmap) {
676 free_irq_cpu_rmap(dev->rmap);
677 dev->rmap = NULL;
678 }
679#endif
233d05d2
SM		 680 spin_lock(&table->lock);
681 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
682 list_del(&eq->list);
683 spin_unlock(&table->lock);
684 if (mlx5_destroy_unmap_eq(dev, eq))
685 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
686 eq->eqn);
687 kfree(eq);
688 spin_lock(&table->lock);
689 }
690 spin_unlock(&table->lock);
691}
692
693static int alloc_comp_eqs(struct mlx5_core_dev *dev)
694{
695 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 696 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 697 struct mlx5_eq *eq;
698 int ncomp_vec;
699 int nent;
700 int err;
701 int i;
702
703 INIT_LIST_HEAD(&table->comp_eqs_list);
704 ncomp_vec = table->num_comp_vectors;
705 nent = MLX5_COMP_EQ_SIZE;
5a7b27eb
MG		 706#ifdef CONFIG_RFS_ACCEL
707 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
708 if (!dev->rmap)
709 return -ENOMEM;
710#endif
233d05d2
SM		 711 for (i = 0; i < ncomp_vec; i++) {
712 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
713 if (!eq) {
714 err = -ENOMEM;
715 goto clean;
716 }
717
5a7b27eb 718#ifdef CONFIG_RFS_ACCEL
78249c42
SG		 719 irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
720 MLX5_EQ_VEC_COMP_BASE + i));
5a7b27eb 721#endif
db058a18 722 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 723 err = mlx5_create_map_eq(dev, eq,
724 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
01187175 725 name, MLX5_EQ_TYPE_COMP);
233d05d2
SM		 726 if (err) {
727 kfree(eq);
728 goto clean;
729 }
730 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
731 eq->index = i;
732 spin_lock(&table->lock);
733 list_add_tail(&eq->list, &table->comp_eqs_list);
734 spin_unlock(&table->lock);
735 }
736
737 return 0;
738
739clean:
740 free_comp_eqs(dev);
741 return err;
742}
743
f62b8bb8
AV		 744static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
745{
c4f287c4
SM		 746 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
747 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
f62b8bb8 748 u32 sup_issi;
c4f287c4 749 int err;
f62b8bb8
AV		 750
751 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
c4f287c4
SM		 752 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
753 query_out, sizeof(query_out));
f62b8bb8 754 if (err) {
c4f287c4
SM		 755 u32 syndrome;
756 u8 status;
757
758 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
f9c14e46
KH		 759 if (!status || syndrome == MLX5_DRIVER_SYND) {
760 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
761 err, status, syndrome);
762 return err;
f62b8bb8
AV		 763 }
764
f9c14e46
KH		 765 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
766 dev->issi = 0;
767 return 0;
f62b8bb8
AV		 768 }
769
770 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
771
772 if (sup_issi & (1 << 1)) {
c4f287c4
SM		 773 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
774 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
f62b8bb8
AV		 775
776 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
777 MLX5_SET(set_issi_in, set_in, current_issi, 1);
c4f287c4
SM		 778 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
779 set_out, sizeof(set_out));
f62b8bb8 780 if (err) {
f9c14e46
KH		 781 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
782 err);
f62b8bb8
AV		 783 return err;
784 }
785
786 dev->issi = 1;
787
788 return 0;
e74a1db0 789 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 790 return 0;
791 }
792
9eb78923 793 return -EOPNOTSUPP;
f62b8bb8 794}
f62b8bb8 795
a31208b1
MD		 796static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
797{
798 struct pci_dev *pdev = dev->pdev;
799 int err = 0;
e126ba97 800
e126ba97
EC		 801 pci_set_drvdata(dev->pdev, dev);
802 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
803 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
804
805 mutex_init(&priv->pgdir_mutex);
806 INIT_LIST_HEAD(&priv->pgdir_list);
807 spin_lock_init(&priv->mkey_lock);
808
311c7c71
SM		 809 mutex_init(&priv->alloc_mutex);
810
811 priv->numa_node = dev_to_node(&dev->pdev->dev);
812
e126ba97
EC		 813 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
814 if (!priv->dbg_root)
815 return -ENOMEM;
816
89d44f0a 817 err = mlx5_pci_enable_device(dev);
e126ba97 818 if (err) {
1a91de28 819 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 820 goto err_dbg;
821 }
822
823 err = request_bar(pdev);
824 if (err) {
1a91de28 825 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 826 goto err_disable;
827 }
828
829 pci_set_master(pdev);
830
831 err = set_dma_caps(pdev);
832 if (err) {
833 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
834 goto err_clr_master;
835 }
836
837 dev->iseg_base = pci_resource_start(dev->pdev, 0);
838 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
839 if (!dev->iseg) {
840 err = -ENOMEM;
841 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
842 goto err_clr_master;
843 }
a31208b1
MD		 844
845 return 0;
846
847err_clr_master:
848 pci_clear_master(dev->pdev);
849 release_bar(dev->pdev);
850err_disable:
89d44f0a 851 mlx5_pci_disable_device(dev);
a31208b1
MD		 852
853err_dbg:
854 debugfs_remove(priv->dbg_root);
855 return err;
856}
857
858static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
859{
860 iounmap(dev->iseg);
861 pci_clear_master(dev->pdev);
862 release_bar(dev->pdev);
89d44f0a 863 mlx5_pci_disable_device(dev);
a31208b1
MD		 864 debugfs_remove(priv->dbg_root);
865}
866
59211bd3
MHY		 867static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
868{
869 struct pci_dev *pdev = dev->pdev;
870 int err;
871
59211bd3
MHY		 872 err = mlx5_query_board_id(dev);
873 if (err) {
874 dev_err(&pdev->dev, "query board id failed\n");
875 goto out;
876 }
877
878 err = mlx5_eq_init(dev);
879 if (err) {
880 dev_err(&pdev->dev, "failed to initialize eq\n");
881 goto out;
882 }
883
59211bd3
MHY		 884 err = mlx5_init_cq_table(dev);
885 if (err) {
886 dev_err(&pdev->dev, "failed to initialize cq table\n");
887 goto err_eq_cleanup;
888 }
889
890 mlx5_init_qp_table(dev);
891
892 mlx5_init_srq_table(dev);
893
894 mlx5_init_mkey_table(dev);
895
52ec462e
IT		 896 mlx5_init_reserved_gids(dev);
897
7c39afb3
FD		 898 mlx5_init_clock(dev);
899
59211bd3
MHY		 900 err = mlx5_init_rl_table(dev);
901 if (err) {
902 dev_err(&pdev->dev, "Failed to init rate limiting\n");
903 goto err_tables_cleanup;
904 }
905
eeb66cdb
SM		 906 err = mlx5_mpfs_init(dev);
907 if (err) {
908 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
909 goto err_rl_cleanup;
910 }
911
c2d6e31a
MHY		 912 err = mlx5_eswitch_init(dev);
913 if (err) {
914 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
eeb66cdb 915 goto err_mpfs_cleanup;
c2d6e31a 916 }
c2d6e31a
MHY		 917
918 err = mlx5_sriov_init(dev);
919 if (err) {
920 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
921 goto err_eswitch_cleanup;
922 }
923
9410733c
IT		 924 err = mlx5_fpga_init(dev);
925 if (err) {
926 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
927 goto err_sriov_cleanup;
928 }
929
59211bd3
MHY		 930 return 0;
931
9410733c
IT		 932err_sriov_cleanup:
933 mlx5_sriov_cleanup(dev);
c2d6e31a 934err_eswitch_cleanup:
c2d6e31a 935 mlx5_eswitch_cleanup(dev->priv.eswitch);
eeb66cdb 936err_mpfs_cleanup:
eeb66cdb 937 mlx5_mpfs_cleanup(dev);
c2d6e31a 938err_rl_cleanup:
c2d6e31a 939 mlx5_cleanup_rl_table(dev);
59211bd3
MHY		 940err_tables_cleanup:
941 mlx5_cleanup_mkey_table(dev);
942 mlx5_cleanup_srq_table(dev);
943 mlx5_cleanup_qp_table(dev);
944 mlx5_cleanup_cq_table(dev);
945
946err_eq_cleanup:
947 mlx5_eq_cleanup(dev);
948
949out:
950 return err;
951}
952
953static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
954{
9410733c 955 mlx5_fpga_cleanup(dev);
c2d6e31a 956 mlx5_sriov_cleanup(dev);
c2d6e31a 957 mlx5_eswitch_cleanup(dev->priv.eswitch);
eeb66cdb 958 mlx5_mpfs_cleanup(dev);
59211bd3 959 mlx5_cleanup_rl_table(dev);
7c39afb3 960 mlx5_cleanup_clock(dev);
52ec462e 961 mlx5_cleanup_reserved_gids(dev);
59211bd3
MHY		 962 mlx5_cleanup_mkey_table(dev);
963 mlx5_cleanup_srq_table(dev);
964 mlx5_cleanup_qp_table(dev);
965 mlx5_cleanup_cq_table(dev);
966 mlx5_eq_cleanup(dev);
967}
968
969static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
970 bool boot)
a31208b1
MD		 971{
972 struct pci_dev *pdev = dev->pdev;
973 int err;
974
89d44f0a 975 mutex_lock(&dev->intf_state_mutex);
5fc7197d 976 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 977 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
978 __func__);
979 goto out;
980 }
981
e126ba97
EC		 982 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
983 fw_rev_min(dev), fw_rev_sub(dev));
984
89d44f0a
MD		 985 /* on load removing any previous indication of internal error, device is
986 * up
987 */
988 dev->state = MLX5_DEVICE_STATE_UP;
989
6c780a02
EC		 990 /* wait for firmware to accept initialization segments configurations
991 */
992 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
993 if (err) {
994 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
995 FW_PRE_INIT_TIMEOUT_MILI);
8ce59b16 996 goto out_err;
6c780a02
EC		 997 }
998
e126ba97
EC		 999 err = mlx5_cmd_init(dev);
1000 if (err) {
1001 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 1002 goto out_err;
e126ba97
EC		 1003 }
1004
e3297246
EC		 1005 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1006 if (err) {
1007 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1008 FW_INIT_TIMEOUT_MILI);
55378a23 1009 goto err_cmd_cleanup;
e3297246
EC		 1010 }
1011
0b107106 1012 err = mlx5_core_enable_hca(dev, 0);
cd23b14b
EC		 1013 if (err) {
1014 dev_err(&pdev->dev, "enable hca failed\n");
59211bd3 1015 goto err_cmd_cleanup;
cd23b14b
EC		 1016 }
1017
f62b8bb8
AV		 1018 err = mlx5_core_set_issi(dev);
1019 if (err) {
1020 dev_err(&pdev->dev, "failed to set issi\n");
1021 goto err_disable_hca;
1022 }
f62b8bb8 1023
cd23b14b
EC		 1024 err = mlx5_satisfy_startup_pages(dev, 1);
1025 if (err) {
1026 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1027 goto err_disable_hca;
1028 }
1029
e126ba97
EC		 1030 err = set_hca_ctrl(dev);
1031 if (err) {
1032 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 1033 goto reclaim_boot_pages;
e126ba97
EC		 1034 }
1035
1036 err = handle_hca_cap(dev);
1037 if (err) {
1038 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 1039 goto reclaim_boot_pages;
e126ba97
EC		 1040 }
1041
f91e6d89
EBE		 1042 err = handle_hca_cap_atomic(dev);
1043 if (err) {
1044 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1045 goto reclaim_boot_pages;
e126ba97
EC		 1046 }
1047
cd23b14b 1048 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 1049 if (err) {
cd23b14b
EC		 1050 dev_err(&pdev->dev, "failed to allocate init pages\n");
1051 goto reclaim_boot_pages;
e126ba97
EC		 1052 }
1053
1054 err = mlx5_pagealloc_start(dev);
1055 if (err) {
1056 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 1057 goto reclaim_boot_pages;
e126ba97
EC		 1058 }
1059
8737f818 1060 err = mlx5_cmd_init_hca(dev, sw_owner_id);
e126ba97
EC		 1061 if (err) {
1062 dev_err(&pdev->dev, "init hca failed\n");
1063 goto err_pagealloc_stop;
1064 }
1065
012e50e1
HN		 1066 mlx5_set_driver_version(dev);
1067
e126ba97
EC		 1068 mlx5_start_health_poll(dev);
1069
bba1574c
DJ		 1070 err = mlx5_query_hca_caps(dev);
1071 if (err) {
1072 dev_err(&pdev->dev, "query hca failed\n");
1073 goto err_stop_poll;
1074 }
1075
59211bd3
MHY		 1076 if (boot && mlx5_init_once(dev, priv)) {
1077 dev_err(&pdev->dev, "sw objs init failed\n");
e126ba97
EC		 1078 goto err_stop_poll;
1079 }
1080
78249c42 1081 err = mlx5_alloc_irq_vectors(dev);
e126ba97 1082 if (err) {
78249c42 1083 dev_err(&pdev->dev, "alloc irq vectors failed\n");
59211bd3 1084 goto err_cleanup_once;
e126ba97
EC		 1085 }
1086
01187175
EC		 1087 dev->priv.uar = mlx5_get_uars_page(dev);
1088 if (!dev->priv.uar) {
e126ba97 1089 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
59211bd3 1090 goto err_disable_msix;
e126ba97
EC		 1091 }
1092
1093 err = mlx5_start_eqs(dev);
1094 if (err) {
1095 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
9410733c 1096 goto err_put_uars;
e126ba97
EC		 1097 }
1098
233d05d2
SM		 1099 err = alloc_comp_eqs(dev);
1100 if (err) {
1101 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1102 goto err_stop_eqs;
1103 }
1104
86d722ad 1105 err = mlx5_init_fs(dev);
59211bd3 1106 if (err) {
86d722ad 1107 dev_err(&pdev->dev, "Failed to init flow steering\n");
c85023e1 1108 goto err_fs;
59211bd3 1109 }
e126ba97 1110
c85023e1 1111 err = mlx5_core_set_hca_defaults(dev);
86d722ad 1112 if (err) {
c85023e1 1113 dev_err(&pdev->dev, "Failed to set hca defaults\n");
86d722ad
MG		 1114 goto err_fs;
1115 }
1466cc5b 1116
c2d6e31a 1117 err = mlx5_sriov_attach(dev);
fc50db98
EC		 1118 if (err) {
1119 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1120 goto err_sriov;
1121 }
1122
e29341fb
IT		 1123 err = mlx5_fpga_device_start(dev);
1124 if (err) {
1125 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
52ec462e 1126 goto err_fpga_start;
e29341fb 1127 }
bebb23e6
IT		 1128 err = mlx5_accel_ipsec_init(dev);
1129 if (err) {
1130 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1131 goto err_ipsec_start;
1132 }
e29341fb 1133
737a234b
MHY		 1134 if (mlx5_device_registered(dev)) {
1135 mlx5_attach_device(dev);
1136 } else {
1137 err = mlx5_register_device(dev);
1138 if (err) {
1139 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1140 goto err_reg_dev;
1141 }
a31208b1
MD		 1142 }
1143
5fc7197d 1144 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
89d44f0a
MD		 1145out:
1146 mutex_unlock(&dev->intf_state_mutex);
1147
e126ba97
EC		 1148 return 0;
1149
59211bd3 1150err_reg_dev:
bebb23e6
IT		 1151 mlx5_accel_ipsec_cleanup(dev);
1152err_ipsec_start:
52ec462e
IT		 1153 mlx5_fpga_device_stop(dev);
1154
1155err_fpga_start:
c2d6e31a 1156 mlx5_sriov_detach(dev);
fc50db98 1157
59211bd3 1158err_sriov:
86d722ad 1159 mlx5_cleanup_fs(dev);
59211bd3 1160
86d722ad 1161err_fs:
db058a18
SM		 1162 free_comp_eqs(dev);
1163
233d05d2
SM		 1164err_stop_eqs:
1165 mlx5_stop_eqs(dev);
1166
5fe9dec0 1167err_put_uars:
01187175 1168 mlx5_put_uars_page(dev, priv->uar);
e126ba97 1169
59211bd3 1170err_disable_msix:
78249c42 1171 mlx5_free_irq_vectors(dev);
e126ba97 1172
59211bd3
MHY		 1173err_cleanup_once:
1174 if (boot)
1175 mlx5_cleanup_once(dev);
1176
e126ba97
EC		 1177err_stop_poll:
1178 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1179 if (mlx5_cmd_teardown_hca(dev)) {
1180 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1181 goto out_err;
1bde6e30 1182 }
e126ba97
EC		 1183
1184err_pagealloc_stop:
1185 mlx5_pagealloc_stop(dev);
1186
cd23b14b 1187reclaim_boot_pages:
e126ba97
EC		 1188 mlx5_reclaim_startup_pages(dev);
1189
cd23b14b 1190err_disable_hca:
0b107106 1191 mlx5_core_disable_hca(dev, 0);
cd23b14b 1192
59211bd3 1193err_cmd_cleanup:
e126ba97
EC		 1194 mlx5_cmd_cleanup(dev);
1195
89d44f0a
MD		 1196out_err:
1197 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1198 mutex_unlock(&dev->intf_state_mutex);
1199
e126ba97
EC		 1200 return err;
1201}
e126ba97 1202
59211bd3
MHY		 1203static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1204 bool cleanup)
e126ba97 1205{
89d44f0a 1206 int err = 0;
e126ba97 1207
5e44fca5 1208 if (cleanup)
2a0165a0 1209 mlx5_drain_health_recovery(dev);
689a248d 1210
89d44f0a 1211 mutex_lock(&dev->intf_state_mutex);
b3cb5388 1212 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 1213 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1214 __func__);
59211bd3
MHY		 1215 if (cleanup)
1216 mlx5_cleanup_once(dev);
89d44f0a
MD		 1217 goto out;
1218 }
6b6adee3 1219
9ade8c7c 1220 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
9ade8c7c 1221
737a234b
MHY		 1222 if (mlx5_device_registered(dev))
1223 mlx5_detach_device(dev);
1224
bebb23e6 1225 mlx5_accel_ipsec_cleanup(dev);
52ec462e
IT		 1226 mlx5_fpga_device_stop(dev);
1227
c2d6e31a 1228 mlx5_sriov_detach(dev);
86d722ad 1229 mlx5_cleanup_fs(dev);
233d05d2 1230 free_comp_eqs(dev);
e126ba97 1231 mlx5_stop_eqs(dev);
01187175 1232 mlx5_put_uars_page(dev, priv->uar);
78249c42 1233 mlx5_free_irq_vectors(dev);
59211bd3
MHY		 1234 if (cleanup)
1235 mlx5_cleanup_once(dev);
e126ba97 1236 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1237 err = mlx5_cmd_teardown_hca(dev);
1238 if (err) {
1bde6e30 1239 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1240 goto out;
1bde6e30 1241 }
e126ba97
EC		 1242 mlx5_pagealloc_stop(dev);
1243 mlx5_reclaim_startup_pages(dev);
0b107106 1244 mlx5_core_disable_hca(dev, 0);
e126ba97 1245 mlx5_cmd_cleanup(dev);
9603b61d 1246
ac6ea6e8 1247out:
89d44f0a 1248 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1249 return err;
9603b61d 1250}
64613d94 1251
9603b61d
JM		 1252struct mlx5_core_event_handler {
1253 void (*event)(struct mlx5_core_dev *dev,
1254 enum mlx5_dev_event event,
1255 void *data);
1256};
1257
feae9087 1258static const struct devlink_ops mlx5_devlink_ops = {
e80541ec 1259#ifdef CONFIG_MLX5_ESWITCH
feae9087
OG		 1260 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1261 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
bffaa916
RD		 1262 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1263 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
7768d197
RD		 1264 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1265 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
feae9087
OG		 1266#endif
1267};
f66f049f 1268
59211bd3 1269#define MLX5_IB_MOD "mlx5_ib"
9603b61d
JM		 1270static int init_one(struct pci_dev *pdev,
1271 const struct pci_device_id *id)
1272{
1273 struct mlx5_core_dev *dev;
feae9087 1274 struct devlink *devlink;
9603b61d
JM		 1275 struct mlx5_priv *priv;
1276 int err;
1277
feae9087
OG		 1278 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1279 if (!devlink) {
9603b61d
JM		 1280 dev_err(&pdev->dev, "kzalloc failed\n");
1281 return -ENOMEM;
1282 }
feae9087
OG		 1283
1284 dev = devlink_priv(devlink);
9603b61d 1285 priv = &dev->priv;
fc50db98 1286 priv->pci_dev_data = id->driver_data;
9603b61d
JM		 1287
1288 pci_set_drvdata(pdev, dev);
1289
0e97a340
HN		 1290 dev->pdev = pdev;
1291 dev->event = mlx5_core_event;
9603b61d 1292 dev->profile = &profile[prof_sel];
9603b61d 1293
364d1798
EC		 1294 INIT_LIST_HEAD(&priv->ctx_list);
1295 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1296 mutex_init(&dev->pci_status_mutex);
1297 mutex_init(&dev->intf_state_mutex);
d9aaed83 1298
97834eba
ES		 1299 INIT_LIST_HEAD(&priv->waiting_events_list);
1300 priv->is_accum_events = false;
1301
d9aaed83
AK		 1302#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1303 err = init_srcu_struct(&priv->pfault_srcu);
1304 if (err) {
1305 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1306 err);
1307 goto clean_dev;
1308 }
1309#endif
01187175
EC		 1310 mutex_init(&priv->bfregs.reg_head.lock);
1311 mutex_init(&priv->bfregs.wc_head.lock);
1312 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1313 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1314
a31208b1 1315 err = mlx5_pci_init(dev, priv);
9603b61d 1316 if (err) {
a31208b1 1317 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
d9aaed83 1318 goto clean_srcu;
9603b61d
JM		 1319 }
1320
ac6ea6e8
EC		 1321 err = mlx5_health_init(dev);
1322 if (err) {
1323 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1324 goto close_pci;
1325 }
1326
59211bd3
MHY		 1327 mlx5_pagealloc_init(dev);
1328
1329 err = mlx5_load_one(dev, priv, true);
9603b61d 1330 if (err) {
a31208b1 1331 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1332 goto clean_health;
9603b61d 1333 }
59211bd3 1334
f82eed45 1335 request_module_nowait(MLX5_IB_MOD);
9603b61d 1336
feae9087
OG		 1337 err = devlink_register(devlink, &pdev->dev);
1338 if (err)
1339 goto clean_load;
1340
5d47f6c8 1341 pci_save_state(pdev);
9603b61d
JM		 1342 return 0;
1343
feae9087 1344clean_load:
59211bd3 1345 mlx5_unload_one(dev, priv, true);
ac6ea6e8 1346clean_health:
59211bd3 1347 mlx5_pagealloc_cleanup(dev);
ac6ea6e8 1348 mlx5_health_cleanup(dev);
a31208b1
MD		 1349close_pci:
1350 mlx5_pci_close(dev, priv);
d9aaed83
AK		 1351clean_srcu:
1352#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1353 cleanup_srcu_struct(&priv->pfault_srcu);
a31208b1 1354clean_dev:
d9aaed83 1355#endif
feae9087 1356 devlink_free(devlink);
a31208b1 1357
9603b61d
JM		 1358 return err;
1359}
a31208b1 1360
9603b61d
JM		 1361static void remove_one(struct pci_dev *pdev)
1362{
1363 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
feae9087 1364 struct devlink *devlink = priv_to_devlink(dev);
a31208b1 1365 struct mlx5_priv *priv = &dev->priv;
9603b61d 1366
feae9087 1367 devlink_unregister(devlink);
737a234b
MHY		 1368 mlx5_unregister_device(dev);
1369
59211bd3 1370 if (mlx5_unload_one(dev, priv, true)) {
a31208b1 1371 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1372 mlx5_health_cleanup(dev);
a31208b1
MD		 1373 return;
1374 }
737a234b 1375
59211bd3 1376 mlx5_pagealloc_cleanup(dev);
ac6ea6e8 1377 mlx5_health_cleanup(dev);
a31208b1 1378 mlx5_pci_close(dev, priv);
d9aaed83
AK		 1379#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1380 cleanup_srcu_struct(&priv->pfault_srcu);
1381#endif
feae9087 1382 devlink_free(devlink);
9603b61d
JM		 1383}
1384
89d44f0a
MD		 1385static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1386 pci_channel_state_t state)
1387{
1388 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1389 struct mlx5_priv *priv = &dev->priv;
1390
1391 dev_info(&pdev->dev, "%s was called\n", __func__);
04c0c1ab 1392
8812c24d 1393 mlx5_enter_error_state(dev, false);
59211bd3 1394 mlx5_unload_one(dev, priv, false);
5d47f6c8 1395 /* In case of kernel call drain the health wq */
05ac2c0b 1396 if (state) {
5e44fca5 1397 mlx5_drain_health_wq(dev);
05ac2c0b
MHY		 1398 mlx5_pci_disable_device(dev);
1399 }
1400
89d44f0a
MD		 1401 return state == pci_channel_io_perm_failure ?
1402 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1403}
1404
d57847dc
DJ		 1405/* wait for the device to show vital signs by waiting
1406 * for the health counter to start counting.
89d44f0a 1407 */
d57847dc 1408static int wait_vital(struct pci_dev *pdev)
89d44f0a
MD		 1409{
1410 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1411 struct mlx5_core_health *health = &dev->priv.health;
1412 const int niter = 100;
d57847dc 1413 u32 last_count = 0;
89d44f0a 1414 u32 count;
89d44f0a
MD		 1415 int i;
1416
89d44f0a
MD		 1417 for (i = 0; i < niter; i++) {
1418 count = ioread32be(health->health_counter);
1419 if (count && count != 0xffffffff) {
d57847dc
DJ		 1420 if (last_count && last_count != count) {
1421 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1422 return 0;
1423 }
1424 last_count = count;
89d44f0a
MD		 1425 }
1426 msleep(50);
1427 }
1428
d57847dc 1429 return -ETIMEDOUT;
89d44f0a
MD		 1430}
1431
1061c90f 1432static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
89d44f0a
MD		 1433{
1434 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
89d44f0a
MD		 1435 int err;
1436
1437 dev_info(&pdev->dev, "%s was called\n", __func__);
1438
1061c90f 1439 err = mlx5_pci_enable_device(dev);
d57847dc 1440 if (err) {
1061c90f
MHY		 1441 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1442 , __func__, err);
1443 return PCI_ERS_RESULT_DISCONNECT;
1444 }
1445
1446 pci_set_master(pdev);
1447 pci_restore_state(pdev);
5d47f6c8 1448 pci_save_state(pdev);
1061c90f
MHY		 1449
1450 if (wait_vital(pdev)) {
d57847dc 1451 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1061c90f 1452 return PCI_ERS_RESULT_DISCONNECT;
d57847dc 1453 }
89d44f0a 1454
1061c90f
MHY		 1455 return PCI_ERS_RESULT_RECOVERED;
1456}
1457
1061c90f
MHY		 1458static void mlx5_pci_resume(struct pci_dev *pdev)
1459{
1460 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1461 struct mlx5_priv *priv = &dev->priv;
1462 int err;
1463
1464 dev_info(&pdev->dev, "%s was called\n", __func__);
1465
59211bd3 1466 err = mlx5_load_one(dev, priv, false);
89d44f0a
MD		 1467 if (err)
1468 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1469 , __func__, err);
1470 else
1471 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1472}
1473
1474static const struct pci_error_handlers mlx5_err_handler = {
1475 .error_detected = mlx5_pci_err_detected,
1476 .slot_reset = mlx5_pci_slot_reset,
1477 .resume = mlx5_pci_resume
1478};
1479
8812c24d
MD		 1480static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1481{
1482 int ret;
1483
1484 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1485 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1486 return -EOPNOTSUPP;
1487 }
1488
1489 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1490 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1491 return -EAGAIN;
1492 }
1493
d2aa060d
HN		 1494 /* Panic tear down fw command will stop the PCI bus communication
1495 * with the HCA, so the health polll is no longer needed.
1496 */
1497 mlx5_drain_health_wq(dev);
1498 mlx5_stop_health_poll(dev);
1499
8812c24d
MD		 1500 ret = mlx5_cmd_force_teardown_hca(dev);
1501 if (ret) {
1502 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
d2aa060d 1503 mlx5_start_health_poll(dev);
8812c24d
MD		 1504 return ret;
1505 }
1506
1507 mlx5_enter_error_state(dev, true);
1508
1509 return 0;
1510}
1511
5fc7197d
MD		 1512static void shutdown(struct pci_dev *pdev)
1513{
1514 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1515 struct mlx5_priv *priv = &dev->priv;
8812c24d 1516 int err;
5fc7197d
MD		 1517
1518 dev_info(&pdev->dev, "Shutdown was called\n");
8812c24d
MD		 1519 err = mlx5_try_fast_unload(dev);
1520 if (err)
1521 mlx5_unload_one(dev, priv, false);
5fc7197d
MD		 1522 mlx5_pci_disable_device(dev);
1523}
1524
9603b61d 1525static const struct pci_device_id mlx5_core_pci_table[] = {
bbad7c21 1526 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
fc50db98 1527 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
bbad7c21 1528 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
fc50db98 1529 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
bbad7c21 1530 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
fc50db98 1531 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
7092fe86 1532 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
64dbbdfe 1533 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
d0dd989f
MD		 1534 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1535 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1536 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1537 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2e9d3e83
NO		 1538 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1539 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
9603b61d
JM		 1540 { 0, }
1541};
1542
1543MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1544
04c0c1ab
MHY		 1545void mlx5_disable_device(struct mlx5_core_dev *dev)
1546{
1547 mlx5_pci_err_detected(dev->pdev, 0);
1548}
1549
1550void mlx5_recover_device(struct mlx5_core_dev *dev)
1551{
1552 mlx5_pci_disable_device(dev);
1553 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1554 mlx5_pci_resume(dev->pdev);
1555}
1556
9603b61d
JM		 1557static struct pci_driver mlx5_core_driver = {
1558 .name = DRIVER_NAME,
1559 .id_table = mlx5_core_pci_table,
1560 .probe = init_one,
89d44f0a 1561 .remove = remove_one,
5fc7197d 1562 .shutdown = shutdown,
fc50db98
EC		 1563 .err_handler = &mlx5_err_handler,
1564 .sriov_configure = mlx5_core_sriov_configure,
9603b61d 1565};
e126ba97 1566
f663ad98
KH		 1567static void mlx5_core_verify_params(void)
1568{
1569 if (prof_sel >= ARRAY_SIZE(profile)) {
1570 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1571 prof_sel,
1572 ARRAY_SIZE(profile) - 1,
1573 MLX5_DEFAULT_PROF);
1574 prof_sel = MLX5_DEFAULT_PROF;
1575 }
1576}
1577
e126ba97
EC		 1578static int __init init(void)
1579{
1580 int err;
1581
8737f818
DJ		 1582 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1583
f663ad98 1584 mlx5_core_verify_params();
e126ba97 1585 mlx5_register_debugfs();
e126ba97 1586
9603b61d
JM		 1587 err = pci_register_driver(&mlx5_core_driver);
1588 if (err)
ac6ea6e8 1589 goto err_debug;
9603b61d 1590
f62b8bb8
AV		 1591#ifdef CONFIG_MLX5_CORE_EN
1592 mlx5e_init();
1593#endif
1594
e126ba97
EC		 1595 return 0;
1596
e126ba97
EC		 1597err_debug:
1598 mlx5_unregister_debugfs();
1599 return err;
1600}
1601
1602static void __exit cleanup(void)
1603{
f62b8bb8
AV		 1604#ifdef CONFIG_MLX5_CORE_EN
1605 mlx5e_cleanup();
1606#endif
9603b61d 1607 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1608 mlx5_unregister_debugfs();
1609}
1610
1611module_init(init);
1612module_exit(cleanup);
Linux 6.x block layer and io_uring tree(s)