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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
b775516b | 49 | #include <linux/mlx5/mlx5_ifc.h> |
c85023e1 | 50 | #include <linux/mlx5/vport.h> |
5a7b27eb MG |
51 | #ifdef CONFIG_RFS_ACCEL |
52 | #include <linux/cpu_rmap.h> | |
53 | #endif | |
feae9087 | 54 | #include <net/devlink.h> |
e126ba97 | 55 | #include "mlx5_core.h" |
86d722ad | 56 | #include "fs_core.h" |
eeb66cdb | 57 | #include "lib/mpfs.h" |
073bb189 | 58 | #include "eswitch.h" |
52ec462e | 59 | #include "lib/mlx5.h" |
e29341fb | 60 | #include "fpga/core.h" |
bebb23e6 | 61 | #include "accel/ipsec.h" |
7c39afb3 | 62 | #include "lib/clock.h" |
e126ba97 | 63 | |
e126ba97 | 64 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 65 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
66 | MODULE_LICENSE("Dual BSD/GPL"); |
67 | MODULE_VERSION(DRIVER_VERSION); | |
68 | ||
f663ad98 KH |
69 | unsigned int mlx5_core_debug_mask; |
70 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
71 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
72 | ||
9603b61d | 73 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
74 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
75 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
76 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
77 | ||
f91e6d89 EBE |
78 | enum { |
79 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
80 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
81 | }; | |
82 | ||
9603b61d JM |
83 | static struct mlx5_profile profile[] = { |
84 | [0] = { | |
85 | .mask = 0, | |
86 | }, | |
87 | [1] = { | |
88 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
89 | .log_max_qp = 12, | |
90 | }, | |
91 | [2] = { | |
92 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
93 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 94 | .log_max_qp = 18, |
9603b61d JM |
95 | .mr_cache[0] = { |
96 | .size = 500, | |
97 | .limit = 250 | |
98 | }, | |
99 | .mr_cache[1] = { | |
100 | .size = 500, | |
101 | .limit = 250 | |
102 | }, | |
103 | .mr_cache[2] = { | |
104 | .size = 500, | |
105 | .limit = 250 | |
106 | }, | |
107 | .mr_cache[3] = { | |
108 | .size = 500, | |
109 | .limit = 250 | |
110 | }, | |
111 | .mr_cache[4] = { | |
112 | .size = 500, | |
113 | .limit = 250 | |
114 | }, | |
115 | .mr_cache[5] = { | |
116 | .size = 500, | |
117 | .limit = 250 | |
118 | }, | |
119 | .mr_cache[6] = { | |
120 | .size = 500, | |
121 | .limit = 250 | |
122 | }, | |
123 | .mr_cache[7] = { | |
124 | .size = 500, | |
125 | .limit = 250 | |
126 | }, | |
127 | .mr_cache[8] = { | |
128 | .size = 500, | |
129 | .limit = 250 | |
130 | }, | |
131 | .mr_cache[9] = { | |
132 | .size = 500, | |
133 | .limit = 250 | |
134 | }, | |
135 | .mr_cache[10] = { | |
136 | .size = 500, | |
137 | .limit = 250 | |
138 | }, | |
139 | .mr_cache[11] = { | |
140 | .size = 500, | |
141 | .limit = 250 | |
142 | }, | |
143 | .mr_cache[12] = { | |
144 | .size = 64, | |
145 | .limit = 32 | |
146 | }, | |
147 | .mr_cache[13] = { | |
148 | .size = 32, | |
149 | .limit = 16 | |
150 | }, | |
151 | .mr_cache[14] = { | |
152 | .size = 16, | |
153 | .limit = 8 | |
154 | }, | |
155 | .mr_cache[15] = { | |
156 | .size = 8, | |
157 | .limit = 4 | |
158 | }, | |
7d0cc6ed AK |
159 | .mr_cache[16] = { |
160 | .size = 8, | |
161 | .limit = 4 | |
162 | }, | |
163 | .mr_cache[17] = { | |
164 | .size = 8, | |
165 | .limit = 4 | |
166 | }, | |
167 | .mr_cache[18] = { | |
168 | .size = 8, | |
169 | .limit = 4 | |
170 | }, | |
171 | .mr_cache[19] = { | |
172 | .size = 4, | |
173 | .limit = 2 | |
174 | }, | |
175 | .mr_cache[20] = { | |
176 | .size = 4, | |
177 | .limit = 2 | |
178 | }, | |
9603b61d JM |
179 | }, |
180 | }; | |
e126ba97 | 181 | |
6c780a02 EC |
182 | #define FW_INIT_TIMEOUT_MILI 2000 |
183 | #define FW_INIT_WAIT_MS 2 | |
184 | #define FW_PRE_INIT_TIMEOUT_MILI 10000 | |
e3297246 EC |
185 | |
186 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
187 | { | |
188 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
189 | int err = 0; | |
190 | ||
191 | while (fw_initializing(dev)) { | |
192 | if (time_after(jiffies, end)) { | |
193 | err = -EBUSY; | |
194 | break; | |
195 | } | |
196 | msleep(FW_INIT_WAIT_MS); | |
197 | } | |
198 | ||
199 | return err; | |
200 | } | |
201 | ||
012e50e1 HN |
202 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
203 | { | |
204 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
205 | driver_version); | |
206 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; | |
207 | u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; | |
208 | int remaining_size = driver_ver_sz; | |
209 | char *string; | |
210 | ||
211 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
212 | return; | |
213 | ||
214 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
215 | ||
216 | strncpy(string, "Linux", remaining_size); | |
217 | ||
218 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
219 | strncat(string, ",", remaining_size); | |
220 | ||
221 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
222 | strncat(string, DRIVER_NAME, remaining_size); | |
223 | ||
224 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
225 | strncat(string, ",", remaining_size); | |
226 | ||
227 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
228 | strncat(string, DRIVER_VERSION, remaining_size); | |
229 | ||
230 | /*Send the command*/ | |
231 | MLX5_SET(set_driver_version_in, in, opcode, | |
232 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
233 | ||
234 | mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
235 | } | |
236 | ||
e126ba97 EC |
237 | static int set_dma_caps(struct pci_dev *pdev) |
238 | { | |
239 | int err; | |
240 | ||
241 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
242 | if (err) { | |
1a91de28 | 243 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
244 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
245 | if (err) { | |
1a91de28 | 246 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
247 | return err; |
248 | } | |
249 | } | |
250 | ||
251 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
252 | if (err) { | |
253 | dev_warn(&pdev->dev, | |
1a91de28 | 254 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
255 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
256 | if (err) { | |
257 | dev_err(&pdev->dev, | |
1a91de28 | 258 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
259 | return err; |
260 | } | |
261 | } | |
262 | ||
263 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
264 | return err; | |
265 | } | |
266 | ||
89d44f0a MD |
267 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
268 | { | |
269 | struct pci_dev *pdev = dev->pdev; | |
270 | int err = 0; | |
271 | ||
272 | mutex_lock(&dev->pci_status_mutex); | |
273 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
274 | err = pci_enable_device(pdev); | |
275 | if (!err) | |
276 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
277 | } | |
278 | mutex_unlock(&dev->pci_status_mutex); | |
279 | ||
280 | return err; | |
281 | } | |
282 | ||
283 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
284 | { | |
285 | struct pci_dev *pdev = dev->pdev; | |
286 | ||
287 | mutex_lock(&dev->pci_status_mutex); | |
288 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
289 | pci_disable_device(pdev); | |
290 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
291 | } | |
292 | mutex_unlock(&dev->pci_status_mutex); | |
293 | } | |
294 | ||
e126ba97 EC |
295 | static int request_bar(struct pci_dev *pdev) |
296 | { | |
297 | int err = 0; | |
298 | ||
299 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 300 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
301 | return -ENODEV; |
302 | } | |
303 | ||
304 | err = pci_request_regions(pdev, DRIVER_NAME); | |
305 | if (err) | |
306 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
307 | ||
308 | return err; | |
309 | } | |
310 | ||
311 | static void release_bar(struct pci_dev *pdev) | |
312 | { | |
313 | pci_release_regions(pdev); | |
314 | } | |
315 | ||
78249c42 | 316 | static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev) |
e126ba97 | 317 | { |
db058a18 SM |
318 | struct mlx5_priv *priv = &dev->priv; |
319 | struct mlx5_eq_table *table = &priv->eq_table; | |
a435393a SG |
320 | struct irq_affinity irqdesc = { |
321 | .pre_vectors = MLX5_EQ_VEC_COMP_BASE, | |
322 | }; | |
938fe83c | 323 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 324 | int nvec; |
e126ba97 | 325 | |
938fe83c SM |
326 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
327 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
328 | nvec = min_t(int, nvec, num_eqs); |
329 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
330 | return -ENOMEM; | |
331 | ||
db058a18 | 332 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); |
78249c42 | 333 | if (!priv->irq_info) |
db058a18 | 334 | goto err_free_msix; |
e126ba97 | 335 | |
a435393a | 336 | nvec = pci_alloc_irq_vectors_affinity(dev->pdev, |
78249c42 | 337 | MLX5_EQ_VEC_COMP_BASE + 1, nvec, |
a435393a SG |
338 | PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, |
339 | &irqdesc); | |
f3c9407b AG |
340 | if (nvec < 0) |
341 | return nvec; | |
e126ba97 | 342 | |
f3c9407b | 343 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
344 | |
345 | return 0; | |
db058a18 SM |
346 | |
347 | err_free_msix: | |
348 | kfree(priv->irq_info); | |
db058a18 | 349 | return -ENOMEM; |
e126ba97 EC |
350 | } |
351 | ||
78249c42 | 352 | static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev) |
e126ba97 | 353 | { |
db058a18 | 354 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 | 355 | |
78249c42 | 356 | pci_free_irq_vectors(dev->pdev); |
db058a18 | 357 | kfree(priv->irq_info); |
e126ba97 EC |
358 | } |
359 | ||
bd10838a | 360 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
361 | u8 he; |
362 | u8 rsvd[15]; | |
363 | }; | |
364 | ||
87b8de49 EC |
365 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
366 | ||
367 | enum { | |
c7a08ac7 EC |
368 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
369 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
370 | }; |
371 | ||
2974ab6e | 372 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
373 | { |
374 | switch (size) { | |
375 | case 128: | |
376 | return 0; | |
377 | case 256: | |
378 | return 1; | |
379 | case 512: | |
380 | return 2; | |
381 | case 1024: | |
382 | return 3; | |
383 | case 2048: | |
384 | return 4; | |
385 | case 4096: | |
386 | return 5; | |
387 | default: | |
2974ab6e | 388 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
389 | return 0; |
390 | } | |
391 | } | |
392 | ||
b06e7de8 LR |
393 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
394 | enum mlx5_cap_type cap_type, | |
395 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 396 | { |
b775516b EC |
397 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
398 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
399 | void *out, *hca_caps; |
400 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
401 | int err; |
402 | ||
b775516b EC |
403 | memset(in, 0, sizeof(in)); |
404 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 405 | if (!out) |
e126ba97 | 406 | return -ENOMEM; |
938fe83c | 407 | |
b775516b EC |
408 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
409 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
410 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 411 | if (err) { |
938fe83c SM |
412 | mlx5_core_warn(dev, |
413 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
414 | cap_type, cap_mode, err); | |
e126ba97 EC |
415 | goto query_ex; |
416 | } | |
c7a08ac7 | 417 | |
938fe83c SM |
418 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
419 | ||
420 | switch (cap_mode) { | |
421 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 422 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
423 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
424 | break; | |
425 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 426 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
427 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
428 | break; | |
429 | default: | |
430 | mlx5_core_warn(dev, | |
431 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
432 | cap_type, cap_mode); | |
433 | err = -EINVAL; | |
434 | break; | |
435 | } | |
c7a08ac7 EC |
436 | query_ex: |
437 | kfree(out); | |
438 | return err; | |
439 | } | |
440 | ||
b06e7de8 LR |
441 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
442 | { | |
443 | int ret; | |
444 | ||
445 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
446 | if (ret) | |
447 | return ret; | |
448 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
449 | } | |
450 | ||
f91e6d89 | 451 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 452 | { |
c4f287c4 | 453 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 454 | |
b775516b | 455 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 456 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 457 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
458 | } |
459 | ||
f91e6d89 EBE |
460 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
461 | { | |
462 | void *set_ctx; | |
463 | void *set_hca_cap; | |
464 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
465 | int req_endianness; | |
466 | int err; | |
467 | ||
468 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 469 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
470 | if (err) |
471 | return err; | |
472 | } else { | |
473 | return 0; | |
474 | } | |
475 | ||
476 | req_endianness = | |
477 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 478 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
479 | |
480 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
481 | return 0; | |
482 | ||
483 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
484 | if (!set_ctx) | |
485 | return -ENOMEM; | |
486 | ||
487 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
488 | ||
489 | /* Set requestor to host endianness */ | |
bd10838a | 490 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
491 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
492 | ||
493 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
494 | ||
495 | kfree(set_ctx); | |
496 | return err; | |
497 | } | |
498 | ||
c7a08ac7 EC |
499 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
500 | { | |
b775516b | 501 | void *set_ctx = NULL; |
c7a08ac7 | 502 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 503 | int err = -ENOMEM; |
b775516b | 504 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 505 | void *set_hca_cap; |
c7a08ac7 | 506 | |
b775516b | 507 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 508 | if (!set_ctx) |
e126ba97 | 509 | goto query_ex; |
e126ba97 | 510 | |
b06e7de8 | 511 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
512 | if (err) |
513 | goto query_ex; | |
514 | ||
938fe83c SM |
515 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
516 | capability); | |
701052c5 | 517 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
518 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
519 | ||
520 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 521 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 522 | 128); |
c7a08ac7 | 523 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 524 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 525 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 526 | |
883371c4 NO |
527 | /* Check log_max_qp from HCA caps to set in current profile */ |
528 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
529 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
530 | profile[prof_sel].log_max_qp, | |
531 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
532 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
533 | } | |
c7a08ac7 | 534 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
535 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
536 | prof->log_max_qp); | |
c7a08ac7 | 537 | |
938fe83c SM |
538 | /* disable cmdif checksum */ |
539 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 540 | |
91828bd8 MD |
541 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
542 | * than 4K. | |
543 | */ | |
544 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
545 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
546 | ||
fe1e1876 CS |
547 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
548 | ||
f32f5bd2 DJ |
549 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
550 | MLX5_SET(cmd_hca_cap, | |
551 | set_hca_cap, | |
552 | cache_line_128byte, | |
553 | cache_line_size() == 128 ? 1 : 0); | |
554 | ||
f91e6d89 EBE |
555 | err = set_caps(dev, set_ctx, set_sz, |
556 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 557 | |
e126ba97 | 558 | query_ex: |
e126ba97 | 559 | kfree(set_ctx); |
e126ba97 EC |
560 | return err; |
561 | } | |
562 | ||
563 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
564 | { | |
bd10838a OG |
565 | struct mlx5_reg_host_endianness he_in; |
566 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
567 | int err; |
568 | ||
fc50db98 EC |
569 | if (!mlx5_core_is_pf(dev)) |
570 | return 0; | |
571 | ||
e126ba97 EC |
572 | memset(&he_in, 0, sizeof(he_in)); |
573 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
574 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
575 | &he_out, sizeof(he_out), | |
576 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
577 | return err; | |
578 | } | |
579 | ||
c85023e1 HN |
580 | static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) |
581 | { | |
582 | int ret = 0; | |
583 | ||
584 | /* Disable local_lb by default */ | |
585 | if ((MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && | |
586 | MLX5_CAP_GEN(dev, disable_local_lb)) | |
587 | ret = mlx5_nic_vport_update_local_lb(dev, false); | |
588 | ||
589 | return ret; | |
590 | } | |
591 | ||
0b107106 | 592 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 593 | { |
c4f287c4 SM |
594 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
595 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 596 | |
0b107106 EC |
597 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
598 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
c4f287c4 | 599 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
600 | } |
601 | ||
0b107106 | 602 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 603 | { |
c4f287c4 SM |
604 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
605 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 606 | |
0b107106 EC |
607 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
608 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
c4f287c4 | 609 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
610 | } |
611 | ||
a5a1d1c2 | 612 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
b0844444 EBE |
613 | { |
614 | u32 timer_h, timer_h1, timer_l; | |
615 | ||
616 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
617 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
618 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
619 | if (timer_h != timer_h1) /* wrap around */ | |
620 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
621 | ||
a5a1d1c2 | 622 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
623 | } |
624 | ||
0b6e26ce DT |
625 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
626 | unsigned int *irqn) | |
233d05d2 SM |
627 | { |
628 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
629 | struct mlx5_eq *eq, *n; | |
630 | int err = -ENOENT; | |
631 | ||
632 | spin_lock(&table->lock); | |
633 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
634 | if (eq->index == vector) { | |
635 | *eqn = eq->eqn; | |
636 | *irqn = eq->irqn; | |
637 | err = 0; | |
638 | break; | |
639 | } | |
640 | } | |
641 | spin_unlock(&table->lock); | |
642 | ||
643 | return err; | |
644 | } | |
645 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
646 | ||
94c6825e MB |
647 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
648 | { | |
649 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
650 | struct mlx5_eq *eq; | |
651 | ||
652 | spin_lock(&table->lock); | |
653 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
654 | if (eq->eqn == eqn) { | |
655 | spin_unlock(&table->lock); | |
656 | return eq; | |
657 | } | |
658 | ||
659 | spin_unlock(&table->lock); | |
660 | ||
661 | return ERR_PTR(-ENOENT); | |
662 | } | |
663 | ||
233d05d2 SM |
664 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
665 | { | |
666 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
667 | struct mlx5_eq *eq, *n; | |
668 | ||
5a7b27eb MG |
669 | #ifdef CONFIG_RFS_ACCEL |
670 | if (dev->rmap) { | |
671 | free_irq_cpu_rmap(dev->rmap); | |
672 | dev->rmap = NULL; | |
673 | } | |
674 | #endif | |
233d05d2 SM |
675 | spin_lock(&table->lock); |
676 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
677 | list_del(&eq->list); | |
678 | spin_unlock(&table->lock); | |
679 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
680 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
681 | eq->eqn); | |
682 | kfree(eq); | |
683 | spin_lock(&table->lock); | |
684 | } | |
685 | spin_unlock(&table->lock); | |
686 | } | |
687 | ||
688 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
689 | { | |
690 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 691 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
692 | struct mlx5_eq *eq; |
693 | int ncomp_vec; | |
694 | int nent; | |
695 | int err; | |
696 | int i; | |
697 | ||
698 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
699 | ncomp_vec = table->num_comp_vectors; | |
700 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
701 | #ifdef CONFIG_RFS_ACCEL |
702 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
703 | if (!dev->rmap) | |
704 | return -ENOMEM; | |
705 | #endif | |
233d05d2 SM |
706 | for (i = 0; i < ncomp_vec; i++) { |
707 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
708 | if (!eq) { | |
709 | err = -ENOMEM; | |
710 | goto clean; | |
711 | } | |
712 | ||
5a7b27eb | 713 | #ifdef CONFIG_RFS_ACCEL |
78249c42 SG |
714 | irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev, |
715 | MLX5_EQ_VEC_COMP_BASE + i)); | |
5a7b27eb | 716 | #endif |
db058a18 | 717 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
718 | err = mlx5_create_map_eq(dev, eq, |
719 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
01187175 | 720 | name, MLX5_EQ_TYPE_COMP); |
233d05d2 SM |
721 | if (err) { |
722 | kfree(eq); | |
723 | goto clean; | |
724 | } | |
725 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
726 | eq->index = i; | |
727 | spin_lock(&table->lock); | |
728 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
729 | spin_unlock(&table->lock); | |
730 | } | |
731 | ||
732 | return 0; | |
733 | ||
734 | clean: | |
735 | free_comp_eqs(dev); | |
736 | return err; | |
737 | } | |
738 | ||
f62b8bb8 AV |
739 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
740 | { | |
c4f287c4 SM |
741 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
742 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 743 | u32 sup_issi; |
c4f287c4 | 744 | int err; |
f62b8bb8 AV |
745 | |
746 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
747 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
748 | query_out, sizeof(query_out)); | |
f62b8bb8 | 749 | if (err) { |
c4f287c4 SM |
750 | u32 syndrome; |
751 | u8 status; | |
752 | ||
753 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
754 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
755 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
756 | err, status, syndrome); | |
757 | return err; | |
f62b8bb8 AV |
758 | } |
759 | ||
f9c14e46 KH |
760 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
761 | dev->issi = 0; | |
762 | return 0; | |
f62b8bb8 AV |
763 | } |
764 | ||
765 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
766 | ||
767 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
768 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
769 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
770 | |
771 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
772 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
773 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
774 | set_out, sizeof(set_out)); | |
f62b8bb8 | 775 | if (err) { |
f9c14e46 KH |
776 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
777 | err); | |
f62b8bb8 AV |
778 | return err; |
779 | } | |
780 | ||
781 | dev->issi = 1; | |
782 | ||
783 | return 0; | |
e74a1db0 | 784 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
785 | return 0; |
786 | } | |
787 | ||
9eb78923 | 788 | return -EOPNOTSUPP; |
f62b8bb8 | 789 | } |
f62b8bb8 | 790 | |
a31208b1 MD |
791 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
792 | { | |
793 | struct pci_dev *pdev = dev->pdev; | |
794 | int err = 0; | |
e126ba97 | 795 | |
e126ba97 EC |
796 | pci_set_drvdata(dev->pdev, dev); |
797 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
798 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
799 | ||
800 | mutex_init(&priv->pgdir_mutex); | |
801 | INIT_LIST_HEAD(&priv->pgdir_list); | |
802 | spin_lock_init(&priv->mkey_lock); | |
803 | ||
311c7c71 SM |
804 | mutex_init(&priv->alloc_mutex); |
805 | ||
806 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
807 | ||
e126ba97 EC |
808 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
809 | if (!priv->dbg_root) | |
810 | return -ENOMEM; | |
811 | ||
89d44f0a | 812 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 813 | if (err) { |
1a91de28 | 814 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
815 | goto err_dbg; |
816 | } | |
817 | ||
818 | err = request_bar(pdev); | |
819 | if (err) { | |
1a91de28 | 820 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
821 | goto err_disable; |
822 | } | |
823 | ||
824 | pci_set_master(pdev); | |
825 | ||
826 | err = set_dma_caps(pdev); | |
827 | if (err) { | |
828 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
829 | goto err_clr_master; | |
830 | } | |
831 | ||
832 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
833 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
834 | if (!dev->iseg) { | |
835 | err = -ENOMEM; | |
836 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
837 | goto err_clr_master; | |
838 | } | |
a31208b1 MD |
839 | |
840 | return 0; | |
841 | ||
842 | err_clr_master: | |
843 | pci_clear_master(dev->pdev); | |
844 | release_bar(dev->pdev); | |
845 | err_disable: | |
89d44f0a | 846 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
847 | |
848 | err_dbg: | |
849 | debugfs_remove(priv->dbg_root); | |
850 | return err; | |
851 | } | |
852 | ||
853 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
854 | { | |
855 | iounmap(dev->iseg); | |
856 | pci_clear_master(dev->pdev); | |
857 | release_bar(dev->pdev); | |
89d44f0a | 858 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
859 | debugfs_remove(priv->dbg_root); |
860 | } | |
861 | ||
59211bd3 MHY |
862 | static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
863 | { | |
864 | struct pci_dev *pdev = dev->pdev; | |
865 | int err; | |
866 | ||
59211bd3 MHY |
867 | err = mlx5_query_board_id(dev); |
868 | if (err) { | |
869 | dev_err(&pdev->dev, "query board id failed\n"); | |
870 | goto out; | |
871 | } | |
872 | ||
873 | err = mlx5_eq_init(dev); | |
874 | if (err) { | |
875 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
876 | goto out; | |
877 | } | |
878 | ||
59211bd3 MHY |
879 | err = mlx5_init_cq_table(dev); |
880 | if (err) { | |
881 | dev_err(&pdev->dev, "failed to initialize cq table\n"); | |
882 | goto err_eq_cleanup; | |
883 | } | |
884 | ||
885 | mlx5_init_qp_table(dev); | |
886 | ||
887 | mlx5_init_srq_table(dev); | |
888 | ||
889 | mlx5_init_mkey_table(dev); | |
890 | ||
52ec462e IT |
891 | mlx5_init_reserved_gids(dev); |
892 | ||
7c39afb3 FD |
893 | mlx5_init_clock(dev); |
894 | ||
59211bd3 MHY |
895 | err = mlx5_init_rl_table(dev); |
896 | if (err) { | |
897 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
898 | goto err_tables_cleanup; | |
899 | } | |
900 | ||
eeb66cdb SM |
901 | err = mlx5_mpfs_init(dev); |
902 | if (err) { | |
903 | dev_err(&pdev->dev, "Failed to init l2 table %d\n", err); | |
904 | goto err_rl_cleanup; | |
905 | } | |
906 | ||
c2d6e31a MHY |
907 | err = mlx5_eswitch_init(dev); |
908 | if (err) { | |
909 | dev_err(&pdev->dev, "Failed to init eswitch %d\n", err); | |
eeb66cdb | 910 | goto err_mpfs_cleanup; |
c2d6e31a | 911 | } |
c2d6e31a MHY |
912 | |
913 | err = mlx5_sriov_init(dev); | |
914 | if (err) { | |
915 | dev_err(&pdev->dev, "Failed to init sriov %d\n", err); | |
916 | goto err_eswitch_cleanup; | |
917 | } | |
918 | ||
9410733c IT |
919 | err = mlx5_fpga_init(dev); |
920 | if (err) { | |
921 | dev_err(&pdev->dev, "Failed to init fpga device %d\n", err); | |
922 | goto err_sriov_cleanup; | |
923 | } | |
924 | ||
59211bd3 MHY |
925 | return 0; |
926 | ||
9410733c IT |
927 | err_sriov_cleanup: |
928 | mlx5_sriov_cleanup(dev); | |
c2d6e31a | 929 | err_eswitch_cleanup: |
c2d6e31a | 930 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
eeb66cdb | 931 | err_mpfs_cleanup: |
eeb66cdb | 932 | mlx5_mpfs_cleanup(dev); |
c2d6e31a | 933 | err_rl_cleanup: |
c2d6e31a | 934 | mlx5_cleanup_rl_table(dev); |
59211bd3 MHY |
935 | err_tables_cleanup: |
936 | mlx5_cleanup_mkey_table(dev); | |
937 | mlx5_cleanup_srq_table(dev); | |
938 | mlx5_cleanup_qp_table(dev); | |
939 | mlx5_cleanup_cq_table(dev); | |
940 | ||
941 | err_eq_cleanup: | |
942 | mlx5_eq_cleanup(dev); | |
943 | ||
944 | out: | |
945 | return err; | |
946 | } | |
947 | ||
948 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
949 | { | |
9410733c | 950 | mlx5_fpga_cleanup(dev); |
c2d6e31a | 951 | mlx5_sriov_cleanup(dev); |
c2d6e31a | 952 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
eeb66cdb | 953 | mlx5_mpfs_cleanup(dev); |
59211bd3 | 954 | mlx5_cleanup_rl_table(dev); |
7c39afb3 | 955 | mlx5_cleanup_clock(dev); |
52ec462e | 956 | mlx5_cleanup_reserved_gids(dev); |
59211bd3 MHY |
957 | mlx5_cleanup_mkey_table(dev); |
958 | mlx5_cleanup_srq_table(dev); | |
959 | mlx5_cleanup_qp_table(dev); | |
960 | mlx5_cleanup_cq_table(dev); | |
961 | mlx5_eq_cleanup(dev); | |
962 | } | |
963 | ||
964 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |
965 | bool boot) | |
a31208b1 MD |
966 | { |
967 | struct pci_dev *pdev = dev->pdev; | |
968 | int err; | |
969 | ||
89d44f0a | 970 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 971 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
972 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
973 | __func__); | |
974 | goto out; | |
975 | } | |
976 | ||
e126ba97 EC |
977 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
978 | fw_rev_min(dev), fw_rev_sub(dev)); | |
979 | ||
89d44f0a MD |
980 | /* on load removing any previous indication of internal error, device is |
981 | * up | |
982 | */ | |
983 | dev->state = MLX5_DEVICE_STATE_UP; | |
984 | ||
6c780a02 EC |
985 | /* wait for firmware to accept initialization segments configurations |
986 | */ | |
987 | err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI); | |
988 | if (err) { | |
989 | dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n", | |
990 | FW_PRE_INIT_TIMEOUT_MILI); | |
8ce59b16 | 991 | goto out_err; |
6c780a02 EC |
992 | } |
993 | ||
e126ba97 EC |
994 | err = mlx5_cmd_init(dev); |
995 | if (err) { | |
996 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 997 | goto out_err; |
e126ba97 EC |
998 | } |
999 | ||
e3297246 EC |
1000 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
1001 | if (err) { | |
1002 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
1003 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 1004 | goto err_cmd_cleanup; |
e3297246 EC |
1005 | } |
1006 | ||
0b107106 | 1007 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
1008 | if (err) { |
1009 | dev_err(&pdev->dev, "enable hca failed\n"); | |
59211bd3 | 1010 | goto err_cmd_cleanup; |
cd23b14b EC |
1011 | } |
1012 | ||
f62b8bb8 AV |
1013 | err = mlx5_core_set_issi(dev); |
1014 | if (err) { | |
1015 | dev_err(&pdev->dev, "failed to set issi\n"); | |
1016 | goto err_disable_hca; | |
1017 | } | |
f62b8bb8 | 1018 | |
cd23b14b EC |
1019 | err = mlx5_satisfy_startup_pages(dev, 1); |
1020 | if (err) { | |
1021 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
1022 | goto err_disable_hca; | |
1023 | } | |
1024 | ||
e126ba97 EC |
1025 | err = set_hca_ctrl(dev); |
1026 | if (err) { | |
1027 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 1028 | goto reclaim_boot_pages; |
e126ba97 EC |
1029 | } |
1030 | ||
1031 | err = handle_hca_cap(dev); | |
1032 | if (err) { | |
1033 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 1034 | goto reclaim_boot_pages; |
e126ba97 EC |
1035 | } |
1036 | ||
f91e6d89 EBE |
1037 | err = handle_hca_cap_atomic(dev); |
1038 | if (err) { | |
1039 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
1040 | goto reclaim_boot_pages; | |
e126ba97 EC |
1041 | } |
1042 | ||
cd23b14b | 1043 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1044 | if (err) { |
cd23b14b EC |
1045 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1046 | goto reclaim_boot_pages; | |
e126ba97 EC |
1047 | } |
1048 | ||
1049 | err = mlx5_pagealloc_start(dev); | |
1050 | if (err) { | |
1051 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1052 | goto reclaim_boot_pages; |
e126ba97 EC |
1053 | } |
1054 | ||
1055 | err = mlx5_cmd_init_hca(dev); | |
1056 | if (err) { | |
1057 | dev_err(&pdev->dev, "init hca failed\n"); | |
1058 | goto err_pagealloc_stop; | |
1059 | } | |
1060 | ||
012e50e1 HN |
1061 | mlx5_set_driver_version(dev); |
1062 | ||
e126ba97 EC |
1063 | mlx5_start_health_poll(dev); |
1064 | ||
bba1574c DJ |
1065 | err = mlx5_query_hca_caps(dev); |
1066 | if (err) { | |
1067 | dev_err(&pdev->dev, "query hca failed\n"); | |
1068 | goto err_stop_poll; | |
1069 | } | |
1070 | ||
59211bd3 MHY |
1071 | if (boot && mlx5_init_once(dev, priv)) { |
1072 | dev_err(&pdev->dev, "sw objs init failed\n"); | |
e126ba97 EC |
1073 | goto err_stop_poll; |
1074 | } | |
1075 | ||
78249c42 | 1076 | err = mlx5_alloc_irq_vectors(dev); |
e126ba97 | 1077 | if (err) { |
78249c42 | 1078 | dev_err(&pdev->dev, "alloc irq vectors failed\n"); |
59211bd3 | 1079 | goto err_cleanup_once; |
e126ba97 EC |
1080 | } |
1081 | ||
01187175 EC |
1082 | dev->priv.uar = mlx5_get_uars_page(dev); |
1083 | if (!dev->priv.uar) { | |
e126ba97 | 1084 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); |
59211bd3 | 1085 | goto err_disable_msix; |
e126ba97 EC |
1086 | } |
1087 | ||
1088 | err = mlx5_start_eqs(dev); | |
1089 | if (err) { | |
1090 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
9410733c | 1091 | goto err_put_uars; |
e126ba97 EC |
1092 | } |
1093 | ||
233d05d2 SM |
1094 | err = alloc_comp_eqs(dev); |
1095 | if (err) { | |
1096 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1097 | goto err_stop_eqs; | |
1098 | } | |
1099 | ||
86d722ad | 1100 | err = mlx5_init_fs(dev); |
59211bd3 | 1101 | if (err) { |
86d722ad | 1102 | dev_err(&pdev->dev, "Failed to init flow steering\n"); |
c85023e1 | 1103 | goto err_fs; |
59211bd3 | 1104 | } |
e126ba97 | 1105 | |
c85023e1 | 1106 | err = mlx5_core_set_hca_defaults(dev); |
86d722ad | 1107 | if (err) { |
c85023e1 | 1108 | dev_err(&pdev->dev, "Failed to set hca defaults\n"); |
86d722ad MG |
1109 | goto err_fs; |
1110 | } | |
1466cc5b | 1111 | |
c2d6e31a | 1112 | err = mlx5_sriov_attach(dev); |
fc50db98 EC |
1113 | if (err) { |
1114 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1115 | goto err_sriov; | |
1116 | } | |
1117 | ||
e29341fb IT |
1118 | err = mlx5_fpga_device_start(dev); |
1119 | if (err) { | |
1120 | dev_err(&pdev->dev, "fpga device start failed %d\n", err); | |
52ec462e | 1121 | goto err_fpga_start; |
e29341fb | 1122 | } |
bebb23e6 IT |
1123 | err = mlx5_accel_ipsec_init(dev); |
1124 | if (err) { | |
1125 | dev_err(&pdev->dev, "IPSec device start failed %d\n", err); | |
1126 | goto err_ipsec_start; | |
1127 | } | |
e29341fb | 1128 | |
737a234b MHY |
1129 | if (mlx5_device_registered(dev)) { |
1130 | mlx5_attach_device(dev); | |
1131 | } else { | |
1132 | err = mlx5_register_device(dev); | |
1133 | if (err) { | |
1134 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1135 | goto err_reg_dev; | |
1136 | } | |
a31208b1 MD |
1137 | } |
1138 | ||
5fc7197d | 1139 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
89d44f0a MD |
1140 | out: |
1141 | mutex_unlock(&dev->intf_state_mutex); | |
1142 | ||
e126ba97 EC |
1143 | return 0; |
1144 | ||
59211bd3 | 1145 | err_reg_dev: |
bebb23e6 IT |
1146 | mlx5_accel_ipsec_cleanup(dev); |
1147 | err_ipsec_start: | |
52ec462e IT |
1148 | mlx5_fpga_device_stop(dev); |
1149 | ||
1150 | err_fpga_start: | |
c2d6e31a | 1151 | mlx5_sriov_detach(dev); |
fc50db98 | 1152 | |
59211bd3 | 1153 | err_sriov: |
86d722ad | 1154 | mlx5_cleanup_fs(dev); |
59211bd3 | 1155 | |
86d722ad | 1156 | err_fs: |
db058a18 SM |
1157 | free_comp_eqs(dev); |
1158 | ||
233d05d2 SM |
1159 | err_stop_eqs: |
1160 | mlx5_stop_eqs(dev); | |
1161 | ||
5fe9dec0 | 1162 | err_put_uars: |
01187175 | 1163 | mlx5_put_uars_page(dev, priv->uar); |
e126ba97 | 1164 | |
59211bd3 | 1165 | err_disable_msix: |
78249c42 | 1166 | mlx5_free_irq_vectors(dev); |
e126ba97 | 1167 | |
59211bd3 MHY |
1168 | err_cleanup_once: |
1169 | if (boot) | |
1170 | mlx5_cleanup_once(dev); | |
1171 | ||
e126ba97 EC |
1172 | err_stop_poll: |
1173 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1174 | if (mlx5_cmd_teardown_hca(dev)) { |
1175 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1176 | goto out_err; |
1bde6e30 | 1177 | } |
e126ba97 EC |
1178 | |
1179 | err_pagealloc_stop: | |
1180 | mlx5_pagealloc_stop(dev); | |
1181 | ||
cd23b14b | 1182 | reclaim_boot_pages: |
e126ba97 EC |
1183 | mlx5_reclaim_startup_pages(dev); |
1184 | ||
cd23b14b | 1185 | err_disable_hca: |
0b107106 | 1186 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1187 | |
59211bd3 | 1188 | err_cmd_cleanup: |
e126ba97 EC |
1189 | mlx5_cmd_cleanup(dev); |
1190 | ||
89d44f0a MD |
1191 | out_err: |
1192 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1193 | mutex_unlock(&dev->intf_state_mutex); | |
1194 | ||
e126ba97 EC |
1195 | return err; |
1196 | } | |
e126ba97 | 1197 | |
59211bd3 MHY |
1198 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, |
1199 | bool cleanup) | |
e126ba97 | 1200 | { |
89d44f0a | 1201 | int err = 0; |
e126ba97 | 1202 | |
5e44fca5 | 1203 | if (cleanup) |
2a0165a0 | 1204 | mlx5_drain_health_recovery(dev); |
689a248d | 1205 | |
89d44f0a | 1206 | mutex_lock(&dev->intf_state_mutex); |
b3cb5388 | 1207 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
1208 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1209 | __func__); | |
59211bd3 MHY |
1210 | if (cleanup) |
1211 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1212 | goto out; |
1213 | } | |
6b6adee3 | 1214 | |
9ade8c7c | 1215 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
9ade8c7c | 1216 | |
737a234b MHY |
1217 | if (mlx5_device_registered(dev)) |
1218 | mlx5_detach_device(dev); | |
1219 | ||
bebb23e6 | 1220 | mlx5_accel_ipsec_cleanup(dev); |
52ec462e IT |
1221 | mlx5_fpga_device_stop(dev); |
1222 | ||
c2d6e31a | 1223 | mlx5_sriov_detach(dev); |
86d722ad | 1224 | mlx5_cleanup_fs(dev); |
233d05d2 | 1225 | free_comp_eqs(dev); |
e126ba97 | 1226 | mlx5_stop_eqs(dev); |
01187175 | 1227 | mlx5_put_uars_page(dev, priv->uar); |
78249c42 | 1228 | mlx5_free_irq_vectors(dev); |
59211bd3 MHY |
1229 | if (cleanup) |
1230 | mlx5_cleanup_once(dev); | |
e126ba97 | 1231 | mlx5_stop_health_poll(dev); |
ac6ea6e8 EC |
1232 | err = mlx5_cmd_teardown_hca(dev); |
1233 | if (err) { | |
1bde6e30 | 1234 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1235 | goto out; |
1bde6e30 | 1236 | } |
e126ba97 EC |
1237 | mlx5_pagealloc_stop(dev); |
1238 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1239 | mlx5_core_disable_hca(dev, 0); |
e126ba97 | 1240 | mlx5_cmd_cleanup(dev); |
9603b61d | 1241 | |
ac6ea6e8 | 1242 | out: |
89d44f0a | 1243 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1244 | return err; |
9603b61d | 1245 | } |
64613d94 | 1246 | |
9603b61d JM |
1247 | struct mlx5_core_event_handler { |
1248 | void (*event)(struct mlx5_core_dev *dev, | |
1249 | enum mlx5_dev_event event, | |
1250 | void *data); | |
1251 | }; | |
1252 | ||
feae9087 | 1253 | static const struct devlink_ops mlx5_devlink_ops = { |
e80541ec | 1254 | #ifdef CONFIG_MLX5_ESWITCH |
feae9087 OG |
1255 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, |
1256 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
bffaa916 RD |
1257 | .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, |
1258 | .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, | |
7768d197 RD |
1259 | .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, |
1260 | .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, | |
feae9087 OG |
1261 | #endif |
1262 | }; | |
f66f049f | 1263 | |
59211bd3 | 1264 | #define MLX5_IB_MOD "mlx5_ib" |
9603b61d JM |
1265 | static int init_one(struct pci_dev *pdev, |
1266 | const struct pci_device_id *id) | |
1267 | { | |
1268 | struct mlx5_core_dev *dev; | |
feae9087 | 1269 | struct devlink *devlink; |
9603b61d JM |
1270 | struct mlx5_priv *priv; |
1271 | int err; | |
1272 | ||
feae9087 OG |
1273 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1274 | if (!devlink) { | |
9603b61d JM |
1275 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1276 | return -ENOMEM; | |
1277 | } | |
feae9087 OG |
1278 | |
1279 | dev = devlink_priv(devlink); | |
9603b61d | 1280 | priv = &dev->priv; |
fc50db98 | 1281 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1282 | |
1283 | pci_set_drvdata(pdev, dev); | |
1284 | ||
0e97a340 HN |
1285 | dev->pdev = pdev; |
1286 | dev->event = mlx5_core_event; | |
9603b61d | 1287 | dev->profile = &profile[prof_sel]; |
9603b61d | 1288 | |
364d1798 EC |
1289 | INIT_LIST_HEAD(&priv->ctx_list); |
1290 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1291 | mutex_init(&dev->pci_status_mutex); |
1292 | mutex_init(&dev->intf_state_mutex); | |
d9aaed83 | 1293 | |
97834eba ES |
1294 | INIT_LIST_HEAD(&priv->waiting_events_list); |
1295 | priv->is_accum_events = false; | |
1296 | ||
d9aaed83 AK |
1297 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1298 | err = init_srcu_struct(&priv->pfault_srcu); | |
1299 | if (err) { | |
1300 | dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n", | |
1301 | err); | |
1302 | goto clean_dev; | |
1303 | } | |
1304 | #endif | |
01187175 EC |
1305 | mutex_init(&priv->bfregs.reg_head.lock); |
1306 | mutex_init(&priv->bfregs.wc_head.lock); | |
1307 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1308 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1309 | ||
a31208b1 | 1310 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1311 | if (err) { |
a31208b1 | 1312 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
d9aaed83 | 1313 | goto clean_srcu; |
9603b61d JM |
1314 | } |
1315 | ||
ac6ea6e8 EC |
1316 | err = mlx5_health_init(dev); |
1317 | if (err) { | |
1318 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1319 | goto close_pci; | |
1320 | } | |
1321 | ||
59211bd3 MHY |
1322 | mlx5_pagealloc_init(dev); |
1323 | ||
1324 | err = mlx5_load_one(dev, priv, true); | |
9603b61d | 1325 | if (err) { |
a31208b1 | 1326 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1327 | goto clean_health; |
9603b61d | 1328 | } |
59211bd3 | 1329 | |
f82eed45 | 1330 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1331 | |
feae9087 OG |
1332 | err = devlink_register(devlink, &pdev->dev); |
1333 | if (err) | |
1334 | goto clean_load; | |
1335 | ||
5d47f6c8 | 1336 | pci_save_state(pdev); |
9603b61d JM |
1337 | return 0; |
1338 | ||
feae9087 | 1339 | clean_load: |
59211bd3 | 1340 | mlx5_unload_one(dev, priv, true); |
ac6ea6e8 | 1341 | clean_health: |
59211bd3 | 1342 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1343 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1344 | close_pci: |
1345 | mlx5_pci_close(dev, priv); | |
d9aaed83 AK |
1346 | clean_srcu: |
1347 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1348 | cleanup_srcu_struct(&priv->pfault_srcu); | |
a31208b1 | 1349 | clean_dev: |
d9aaed83 | 1350 | #endif |
feae9087 | 1351 | devlink_free(devlink); |
a31208b1 | 1352 | |
9603b61d JM |
1353 | return err; |
1354 | } | |
a31208b1 | 1355 | |
9603b61d JM |
1356 | static void remove_one(struct pci_dev *pdev) |
1357 | { | |
1358 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1359 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1360 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1361 | |
feae9087 | 1362 | devlink_unregister(devlink); |
737a234b MHY |
1363 | mlx5_unregister_device(dev); |
1364 | ||
59211bd3 | 1365 | if (mlx5_unload_one(dev, priv, true)) { |
a31208b1 | 1366 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); |
ac6ea6e8 | 1367 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1368 | return; |
1369 | } | |
737a234b | 1370 | |
59211bd3 | 1371 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1372 | mlx5_health_cleanup(dev); |
a31208b1 | 1373 | mlx5_pci_close(dev, priv); |
d9aaed83 AK |
1374 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1375 | cleanup_srcu_struct(&priv->pfault_srcu); | |
1376 | #endif | |
feae9087 | 1377 | devlink_free(devlink); |
9603b61d JM |
1378 | } |
1379 | ||
89d44f0a MD |
1380 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1381 | pci_channel_state_t state) | |
1382 | { | |
1383 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1384 | struct mlx5_priv *priv = &dev->priv; | |
1385 | ||
1386 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
04c0c1ab | 1387 | |
8812c24d | 1388 | mlx5_enter_error_state(dev, false); |
59211bd3 | 1389 | mlx5_unload_one(dev, priv, false); |
5d47f6c8 | 1390 | /* In case of kernel call drain the health wq */ |
05ac2c0b | 1391 | if (state) { |
5e44fca5 | 1392 | mlx5_drain_health_wq(dev); |
05ac2c0b MHY |
1393 | mlx5_pci_disable_device(dev); |
1394 | } | |
1395 | ||
89d44f0a MD |
1396 | return state == pci_channel_io_perm_failure ? |
1397 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1398 | } | |
1399 | ||
d57847dc DJ |
1400 | /* wait for the device to show vital signs by waiting |
1401 | * for the health counter to start counting. | |
89d44f0a | 1402 | */ |
d57847dc | 1403 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1404 | { |
1405 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1406 | struct mlx5_core_health *health = &dev->priv.health; | |
1407 | const int niter = 100; | |
d57847dc | 1408 | u32 last_count = 0; |
89d44f0a | 1409 | u32 count; |
89d44f0a MD |
1410 | int i; |
1411 | ||
89d44f0a MD |
1412 | for (i = 0; i < niter; i++) { |
1413 | count = ioread32be(health->health_counter); | |
1414 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1415 | if (last_count && last_count != count) { |
1416 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1417 | return 0; | |
1418 | } | |
1419 | last_count = count; | |
89d44f0a MD |
1420 | } |
1421 | msleep(50); | |
1422 | } | |
1423 | ||
d57847dc | 1424 | return -ETIMEDOUT; |
89d44f0a MD |
1425 | } |
1426 | ||
1061c90f | 1427 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1428 | { |
1429 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1430 | int err; |
1431 | ||
1432 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1433 | ||
1061c90f | 1434 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1435 | if (err) { |
1061c90f MHY |
1436 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" |
1437 | , __func__, err); | |
1438 | return PCI_ERS_RESULT_DISCONNECT; | |
1439 | } | |
1440 | ||
1441 | pci_set_master(pdev); | |
1442 | pci_restore_state(pdev); | |
5d47f6c8 | 1443 | pci_save_state(pdev); |
1061c90f MHY |
1444 | |
1445 | if (wait_vital(pdev)) { | |
d57847dc | 1446 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1447 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1448 | } |
89d44f0a | 1449 | |
1061c90f MHY |
1450 | return PCI_ERS_RESULT_RECOVERED; |
1451 | } | |
1452 | ||
1061c90f MHY |
1453 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1454 | { | |
1455 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1456 | struct mlx5_priv *priv = &dev->priv; | |
1457 | int err; | |
1458 | ||
1459 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1460 | ||
59211bd3 | 1461 | err = mlx5_load_one(dev, priv, false); |
89d44f0a MD |
1462 | if (err) |
1463 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1464 | , __func__, err); | |
1465 | else | |
1466 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1467 | } | |
1468 | ||
1469 | static const struct pci_error_handlers mlx5_err_handler = { | |
1470 | .error_detected = mlx5_pci_err_detected, | |
1471 | .slot_reset = mlx5_pci_slot_reset, | |
1472 | .resume = mlx5_pci_resume | |
1473 | }; | |
1474 | ||
8812c24d MD |
1475 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1476 | { | |
1477 | int ret; | |
1478 | ||
1479 | if (!MLX5_CAP_GEN(dev, force_teardown)) { | |
1480 | mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); | |
1481 | return -EOPNOTSUPP; | |
1482 | } | |
1483 | ||
1484 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1485 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1486 | return -EAGAIN; | |
1487 | } | |
1488 | ||
1489 | ret = mlx5_cmd_force_teardown_hca(dev); | |
1490 | if (ret) { | |
1491 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1492 | return ret; | |
1493 | } | |
1494 | ||
1495 | mlx5_enter_error_state(dev, true); | |
1496 | ||
1497 | return 0; | |
1498 | } | |
1499 | ||
5fc7197d MD |
1500 | static void shutdown(struct pci_dev *pdev) |
1501 | { | |
1502 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1503 | struct mlx5_priv *priv = &dev->priv; | |
8812c24d | 1504 | int err; |
5fc7197d MD |
1505 | |
1506 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
8812c24d MD |
1507 | err = mlx5_try_fast_unload(dev); |
1508 | if (err) | |
1509 | mlx5_unload_one(dev, priv, false); | |
5fc7197d MD |
1510 | mlx5_pci_disable_device(dev); |
1511 | } | |
1512 | ||
9603b61d | 1513 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1514 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1515 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1516 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1517 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1518 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1519 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1520 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1521 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1522 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1523 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1524 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1525 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
2e9d3e83 NO |
1526 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1527 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
9603b61d JM |
1528 | { 0, } |
1529 | }; | |
1530 | ||
1531 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1532 | ||
04c0c1ab MHY |
1533 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1534 | { | |
1535 | mlx5_pci_err_detected(dev->pdev, 0); | |
1536 | } | |
1537 | ||
1538 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1539 | { | |
1540 | mlx5_pci_disable_device(dev); | |
1541 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1542 | mlx5_pci_resume(dev->pdev); | |
1543 | } | |
1544 | ||
9603b61d JM |
1545 | static struct pci_driver mlx5_core_driver = { |
1546 | .name = DRIVER_NAME, | |
1547 | .id_table = mlx5_core_pci_table, | |
1548 | .probe = init_one, | |
89d44f0a | 1549 | .remove = remove_one, |
5fc7197d | 1550 | .shutdown = shutdown, |
fc50db98 EC |
1551 | .err_handler = &mlx5_err_handler, |
1552 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1553 | }; |
e126ba97 | 1554 | |
f663ad98 KH |
1555 | static void mlx5_core_verify_params(void) |
1556 | { | |
1557 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1558 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1559 | prof_sel, | |
1560 | ARRAY_SIZE(profile) - 1, | |
1561 | MLX5_DEFAULT_PROF); | |
1562 | prof_sel = MLX5_DEFAULT_PROF; | |
1563 | } | |
1564 | } | |
1565 | ||
e126ba97 EC |
1566 | static int __init init(void) |
1567 | { | |
1568 | int err; | |
1569 | ||
f663ad98 | 1570 | mlx5_core_verify_params(); |
e126ba97 | 1571 | mlx5_register_debugfs(); |
e126ba97 | 1572 | |
9603b61d JM |
1573 | err = pci_register_driver(&mlx5_core_driver); |
1574 | if (err) | |
ac6ea6e8 | 1575 | goto err_debug; |
9603b61d | 1576 | |
f62b8bb8 AV |
1577 | #ifdef CONFIG_MLX5_CORE_EN |
1578 | mlx5e_init(); | |
1579 | #endif | |
1580 | ||
e126ba97 EC |
1581 | return 0; |
1582 | ||
e126ba97 EC |
1583 | err_debug: |
1584 | mlx5_unregister_debugfs(); | |
1585 | return err; | |
1586 | } | |
1587 | ||
1588 | static void __exit cleanup(void) | |
1589 | { | |
f62b8bb8 AV |
1590 | #ifdef CONFIG_MLX5_CORE_EN |
1591 | mlx5e_cleanup(); | |
1592 | #endif | |
9603b61d | 1593 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1594 | mlx5_unregister_debugfs(); |
1595 | } | |
1596 | ||
1597 | module_init(init); | |
1598 | module_exit(cleanup); |