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net/mlx5: Fix use-after-free in self-healing flow
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
b775516b 49#include <linux/mlx5/mlx5_ifc.h>
c85023e1 50#include <linux/mlx5/vport.h>
5a7b27eb
MG		 51#ifdef CONFIG_RFS_ACCEL
52#include <linux/cpu_rmap.h>
53#endif
feae9087 54#include <net/devlink.h>
e126ba97 55#include "mlx5_core.h"
86d722ad 56#include "fs_core.h"
eeb66cdb 57#include "lib/mpfs.h"
073bb189 58#include "eswitch.h"
52ec462e 59#include "lib/mlx5.h"
e29341fb 60#include "fpga/core.h"
05564d0a 61#include "fpga/ipsec.h"
bebb23e6 62#include "accel/ipsec.h"
1ae17322 63#include "accel/tls.h"
7c39afb3 64#include "lib/clock.h"
358aa5ce 65#include "lib/vxlan.h"
24406953 66#include "diag/fw_tracer.h"
e126ba97 67
e126ba97 68MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
048f3143 69MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver");
e126ba97
EC		 70MODULE_LICENSE("Dual BSD/GPL");
71MODULE_VERSION(DRIVER_VERSION);
72
f663ad98
KH		 73unsigned int mlx5_core_debug_mask;
74module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
e126ba97
EC		 75MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
76
9603b61d 77#define MLX5_DEFAULT_PROF 2
f663ad98
KH		 78static unsigned int prof_sel = MLX5_DEFAULT_PROF;
79module_param_named(prof_sel, prof_sel, uint, 0444);
9603b61d
JM		 80MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
81
8737f818
DJ		 82static u32 sw_owner_id[4];
83
f91e6d89
EBE		 84enum {
85 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
86 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
87};
88
9603b61d
JM		 89static struct mlx5_profile profile[] = {
90 [0] = {
91 .mask = 0,
92 },
93 [1] = {
94 .mask = MLX5_PROF_MASK_QP_SIZE,
95 .log_max_qp = 12,
96 },
97 [2] = {
98 .mask = MLX5_PROF_MASK_QP_SIZE |
99 MLX5_PROF_MASK_MR_CACHE,
5f40b4ed 100 .log_max_qp = 18,
9603b61d
JM		 101 .mr_cache[0] = {
102 .size = 500,
103 .limit = 250
104 },
105 .mr_cache[1] = {
106 .size = 500,
107 .limit = 250
108 },
109 .mr_cache[2] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[3] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[4] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[5] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[6] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[7] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[8] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[9] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[10] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[11] = {
146 .size = 500,
147 .limit = 250
148 },
149 .mr_cache[12] = {
150 .size = 64,
151 .limit = 32
152 },
153 .mr_cache[13] = {
154 .size = 32,
155 .limit = 16
156 },
157 .mr_cache[14] = {
158 .size = 16,
159 .limit = 8
160 },
161 .mr_cache[15] = {
162 .size = 8,
163 .limit = 4
164 },
7d0cc6ed
AK		 165 .mr_cache[16] = {
166 .size = 8,
167 .limit = 4
168 },
169 .mr_cache[17] = {
170 .size = 8,
171 .limit = 4
172 },
173 .mr_cache[18] = {
174 .size = 8,
175 .limit = 4
176 },
177 .mr_cache[19] = {
178 .size = 4,
179 .limit = 2
180 },
181 .mr_cache[20] = {
182 .size = 4,
183 .limit = 2
184 },
9603b61d
JM		 185 },
186};
e126ba97 187
6c780a02
EC		 188#define FW_INIT_TIMEOUT_MILI 2000
189#define FW_INIT_WAIT_MS 2
190#define FW_PRE_INIT_TIMEOUT_MILI 10000
e3297246
EC		 191
192static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
193{
194 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
195 int err = 0;
196
197 while (fw_initializing(dev)) {
198 if (time_after(jiffies, end)) {
199 err = -EBUSY;
200 break;
201 }
202 msleep(FW_INIT_WAIT_MS);
203 }
204
205 return err;
206}
207
012e50e1
HN		 208static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
209{
210 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
211 driver_version);
212 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
213 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
214 int remaining_size = driver_ver_sz;
215 char *string;
216
217 if (!MLX5_CAP_GEN(dev, driver_version))
218 return;
219
220 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
221
222 strncpy(string, "Linux", remaining_size);
223
224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
225 strncat(string, ",", remaining_size);
226
227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
228 strncat(string, DRIVER_NAME, remaining_size);
229
230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
231 strncat(string, ",", remaining_size);
232
233 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
234 strncat(string, DRIVER_VERSION, remaining_size);
235
236 /*Send the command*/
237 MLX5_SET(set_driver_version_in, in, opcode,
238 MLX5_CMD_OP_SET_DRIVER_VERSION);
239
240 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
241}
242
e126ba97
EC		 243static int set_dma_caps(struct pci_dev *pdev)
244{
245 int err;
246
247 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
248 if (err) {
1a91de28 249 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 250 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
251 if (err) {
1a91de28 252 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 253 return err;
254 }
255 }
256
257 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
258 if (err) {
259 dev_warn(&pdev->dev,
1a91de28 260 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 261 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
262 if (err) {
263 dev_err(&pdev->dev,
1a91de28 264 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 265 return err;
266 }
267 }
268
269 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
270 return err;
271}
272
89d44f0a
MD		 273static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
274{
275 struct pci_dev *pdev = dev->pdev;
276 int err = 0;
277
278 mutex_lock(&dev->pci_status_mutex);
279 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
280 err = pci_enable_device(pdev);
281 if (!err)
282 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
283 }
284 mutex_unlock(&dev->pci_status_mutex);
285
286 return err;
287}
288
289static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
290{
291 struct pci_dev *pdev = dev->pdev;
292
293 mutex_lock(&dev->pci_status_mutex);
294 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
295 pci_disable_device(pdev);
296 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
297 }
298 mutex_unlock(&dev->pci_status_mutex);
299}
300
e126ba97
EC		 301static int request_bar(struct pci_dev *pdev)
302{
303 int err = 0;
304
305 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 306 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 307 return -ENODEV;
308 }
309
310 err = pci_request_regions(pdev, DRIVER_NAME);
311 if (err)
312 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
313
314 return err;
315}
316
317static void release_bar(struct pci_dev *pdev)
318{
319 pci_release_regions(pdev);
320}
321
78249c42 322static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
e126ba97 323{
db058a18
SM		 324 struct mlx5_priv *priv = &dev->priv;
325 struct mlx5_eq_table *table = &priv->eq_table;
342ac844
DD		 326 int num_eqs = MLX5_CAP_GEN(dev, max_num_eqs) ?
327 MLX5_CAP_GEN(dev, max_num_eqs) :
328 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 329 int nvec;
b6908c29 330 int err;
e126ba97 331
938fe83c
SM		 332 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
333 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 334 nvec = min_t(int, nvec, num_eqs);
335 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
336 return -ENOMEM;
337
db058a18 338 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
78249c42 339 if (!priv->irq_info)
b6908c29 340 return -ENOMEM;
e126ba97 341
231243c8 342 nvec = pci_alloc_irq_vectors(dev->pdev,
78249c42 343 MLX5_EQ_VEC_COMP_BASE + 1, nvec,
231243c8 344 PCI_IRQ_MSIX);
b6908c29
AH		 345 if (nvec < 0) {
346 err = nvec;
347 goto err_free_irq_info;
348 }
e126ba97 349
f3c9407b 350 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 351
352 return 0;
db058a18 353
b6908c29 354err_free_irq_info:
db058a18 355 kfree(priv->irq_info);
b6908c29 356 return err;
e126ba97
EC		 357}
358
78249c42 359static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
e126ba97 360{
db058a18 361 struct mlx5_priv *priv = &dev->priv;
e126ba97 362
78249c42 363 pci_free_irq_vectors(dev->pdev);
db058a18 364 kfree(priv->irq_info);
e126ba97
EC		 365}
366
bd10838a 367struct mlx5_reg_host_endianness {
e126ba97
EC		 368 u8 he;
369 u8 rsvd[15];
370};
371
87b8de49
EC		 372#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
373
374enum {
c7a08ac7
EC		 375 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
376 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 377};
378
2974ab6e 379static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
c7a08ac7
EC		 380{
381 switch (size) {
382 case 128:
383 return 0;
384 case 256:
385 return 1;
386 case 512:
387 return 2;
388 case 1024:
389 return 3;
390 case 2048:
391 return 4;
392 case 4096:
393 return 5;
394 default:
2974ab6e 395 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
c7a08ac7
EC		 396 return 0;
397 }
398}
399
b06e7de8
LR		 400static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
401 enum mlx5_cap_type cap_type,
402 enum mlx5_cap_mode cap_mode)
c7a08ac7 403{
b775516b
EC		 404 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
405 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 406 void *out, *hca_caps;
407 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 408 int err;
409
b775516b
EC		 410 memset(in, 0, sizeof(in));
411 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 412 if (!out)
e126ba97 413 return -ENOMEM;
938fe83c 414
b775516b
EC		 415 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
416 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
417 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
c7a08ac7 418 if (err) {
938fe83c
SM		 419 mlx5_core_warn(dev,
420 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
421 cap_type, cap_mode, err);
e126ba97
EC		 422 goto query_ex;
423 }
c7a08ac7 424
938fe83c
SM		 425 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
426
427 switch (cap_mode) {
428 case HCA_CAP_OPMOD_GET_MAX:
701052c5 429 memcpy(dev->caps.hca_max[cap_type], hca_caps,
938fe83c
SM		 430 MLX5_UN_SZ_BYTES(hca_cap_union));
431 break;
432 case HCA_CAP_OPMOD_GET_CUR:
701052c5 433 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
938fe83c
SM		 434 MLX5_UN_SZ_BYTES(hca_cap_union));
435 break;
436 default:
437 mlx5_core_warn(dev,
438 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
439 cap_type, cap_mode);
440 err = -EINVAL;
441 break;
442 }
c7a08ac7
EC		 443query_ex:
444 kfree(out);
445 return err;
446}
447
b06e7de8
LR		 448int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
449{
450 int ret;
451
452 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
453 if (ret)
454 return ret;
455 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
456}
457
f91e6d89 458static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
c7a08ac7 459{
c4f287c4 460 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
e126ba97 461
b775516b 462 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
f91e6d89 463 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
c4f287c4 464 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
c7a08ac7
EC		 465}
466
f91e6d89
EBE		 467static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
468{
469 void *set_ctx;
470 void *set_hca_cap;
471 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
472 int req_endianness;
473 int err;
474
475 if (MLX5_CAP_GEN(dev, atomic)) {
b06e7de8 476 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
f91e6d89
EBE		 477 if (err)
478 return err;
479 } else {
480 return 0;
481 }
482
483 req_endianness =
484 MLX5_CAP_ATOMIC(dev,
bd10838a 485 supported_atomic_req_8B_endianness_mode_1);
f91e6d89
EBE		 486
487 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
488 return 0;
489
490 set_ctx = kzalloc(set_sz, GFP_KERNEL);
491 if (!set_ctx)
492 return -ENOMEM;
493
494 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
495
496 /* Set requestor to host endianness */
bd10838a 497 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
f91e6d89
EBE		 498 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
499
500 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
501
502 kfree(set_ctx);
503 return err;
504}
505
c7a08ac7
EC		 506static int handle_hca_cap(struct mlx5_core_dev *dev)
507{
b775516b 508 void *set_ctx = NULL;
c7a08ac7 509 struct mlx5_profile *prof = dev->profile;
c7a08ac7 510 int err = -ENOMEM;
b775516b 511 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 512 void *set_hca_cap;
c7a08ac7 513
b775516b 514 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 515 if (!set_ctx)
e126ba97 516 goto query_ex;
e126ba97 517
b06e7de8 518 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
e126ba97
EC		 519 if (err)
520 goto query_ex;
521
938fe83c
SM		 522 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
523 capability);
701052c5 524 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
938fe83c
SM		 525 MLX5_ST_SZ_BYTES(cmd_hca_cap));
526
527 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 528 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 529 128);
c7a08ac7 530 /* we limit the size of the pkey table to 128 entries for now */
938fe83c 531 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
2974ab6e 532 to_fw_pkey_sz(dev, 128));
c7a08ac7 533
883371c4
NO		 534 /* Check log_max_qp from HCA caps to set in current profile */
535 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
536 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
537 profile[prof_sel].log_max_qp,
538 MLX5_CAP_GEN_MAX(dev, log_max_qp));
539 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
540 }
c7a08ac7 541 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 542 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
543 prof->log_max_qp);
c7a08ac7 544
938fe83c
SM		 545 /* disable cmdif checksum */
546 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 547
91828bd8
MD		 548 /* Enable 4K UAR only when HCA supports it and page size is bigger
549 * than 4K.
550 */
551 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
f502d834
EC		 552 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
553
fe1e1876
CS		 554 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
555
f32f5bd2
DJ		 556 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
557 MLX5_SET(cmd_hca_cap,
558 set_hca_cap,
559 cache_line_128byte,
c67f100e 560 cache_line_size() >= 128 ? 1 : 0);
f32f5bd2 561
dd44572a
MS		 562 if (MLX5_CAP_GEN_MAX(dev, dct))
563 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
564
c4b76d8d
DJ		 565 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
566 MLX5_SET(cmd_hca_cap,
567 set_hca_cap,
568 num_vhca_ports,
569 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
570
f91e6d89
EBE		 571 err = set_caps(dev, set_ctx, set_sz,
572 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
c7a08ac7 573
e126ba97 574query_ex:
e126ba97 575 kfree(set_ctx);
e126ba97
EC		 576 return err;
577}
578
579static int set_hca_ctrl(struct mlx5_core_dev *dev)
580{
bd10838a
OG		 581 struct mlx5_reg_host_endianness he_in;
582 struct mlx5_reg_host_endianness he_out;
e126ba97
EC		 583 int err;
584
fc50db98
EC		 585 if (!mlx5_core_is_pf(dev))
586 return 0;
587
e126ba97
EC		 588 memset(&he_in, 0, sizeof(he_in));
589 he_in.he = MLX5_SET_HOST_ENDIANNESS;
590 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
591 &he_out, sizeof(he_out),
592 MLX5_REG_HOST_ENDIANNESS, 0, 1);
593 return err;
594}
595
c85023e1
HN		 596static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
597{
598 int ret = 0;
599
600 /* Disable local_lb by default */
8978cc92 601 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
c85023e1
HN		 602 ret = mlx5_nic_vport_update_local_lb(dev, false);
603
604 return ret;
605}
606
0b107106 607int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 608{
c4f287c4
SM		 609 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
610 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
cd23b14b 611
0b107106
EC		 612 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
613 MLX5_SET(enable_hca_in, in, function_id, func_id);
c4f287c4 614 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
cd23b14b
EC		 615}
616
0b107106 617int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 618{
c4f287c4
SM		 619 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
620 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
cd23b14b 621
0b107106
EC		 622 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
623 MLX5_SET(disable_hca_in, in, function_id, func_id);
c4f287c4 624 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
cd23b14b
EC		 625}
626
a5a1d1c2 627u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
b0844444
EBE		 628{
629 u32 timer_h, timer_h1, timer_l;
630
631 timer_h = ioread32be(&dev->iseg->internal_timer_h);
632 timer_l = ioread32be(&dev->iseg->internal_timer_l);
633 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
634 if (timer_h != timer_h1) /* wrap around */
635 timer_l = ioread32be(&dev->iseg->internal_timer_l);
636
a5a1d1c2 637 return (u64)timer_l | (u64)timer_h1 << 32;
b0844444
EBE		 638}
639
231243c8
SM		 640static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
641{
642 struct mlx5_priv *priv = &mdev->priv;
643 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
644
645 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
646 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
647 return -ENOMEM;
648 }
649
650 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
651 priv->irq_info[i].mask);
652
653 if (IS_ENABLED(CONFIG_SMP) &&
654 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
655 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
656
657 return 0;
658}
659
660static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
661{
662 struct mlx5_priv *priv = &mdev->priv;
663 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
664
665 irq_set_affinity_hint(irq, NULL);
666 free_cpumask_var(priv->irq_info[i].mask);
667}
668
669static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
670{
671 int err;
672 int i;
673
674 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
675 err = mlx5_irq_set_affinity_hint(mdev, i);
676 if (err)
677 goto err_out;
678 }
679
680 return 0;
681
682err_out:
683 for (i--; i >= 0; i--)
684 mlx5_irq_clear_affinity_hint(mdev, i);
685
686 return err;
687}
688
689static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
690{
691 int i;
692
693 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
694 mlx5_irq_clear_affinity_hint(mdev, i);
695}
696
0b6e26ce
DT		 697int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
698 unsigned int *irqn)
233d05d2
SM		 699{
700 struct mlx5_eq_table *table = &dev->priv.eq_table;
701 struct mlx5_eq *eq, *n;
702 int err = -ENOENT;
703
704 spin_lock(&table->lock);
705 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
706 if (eq->index == vector) {
707 *eqn = eq->eqn;
708 *irqn = eq->irqn;
709 err = 0;
710 break;
711 }
712 }
713 spin_unlock(&table->lock);
714
715 return err;
716}
717EXPORT_SYMBOL(mlx5_vector2eqn);
718
94c6825e
MB		 719struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
720{
721 struct mlx5_eq_table *table = &dev->priv.eq_table;
722 struct mlx5_eq *eq;
723
724 spin_lock(&table->lock);
725 list_for_each_entry(eq, &table->comp_eqs_list, list)
726 if (eq->eqn == eqn) {
727 spin_unlock(&table->lock);
728 return eq;
729 }
730
731 spin_unlock(&table->lock);
732
733 return ERR_PTR(-ENOENT);
734}
735
233d05d2
SM		 736static void free_comp_eqs(struct mlx5_core_dev *dev)
737{
738 struct mlx5_eq_table *table = &dev->priv.eq_table;
739 struct mlx5_eq *eq, *n;
740
5a7b27eb
MG		 741#ifdef CONFIG_RFS_ACCEL
742 if (dev->rmap) {
743 free_irq_cpu_rmap(dev->rmap);
744 dev->rmap = NULL;
745 }
746#endif
233d05d2
SM		 747 spin_lock(&table->lock);
748 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
749 list_del(&eq->list);
750 spin_unlock(&table->lock);
751 if (mlx5_destroy_unmap_eq(dev, eq))
752 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
753 eq->eqn);
754 kfree(eq);
755 spin_lock(&table->lock);
756 }
757 spin_unlock(&table->lock);
758}
759
760static int alloc_comp_eqs(struct mlx5_core_dev *dev)
761{
762 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 763 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 764 struct mlx5_eq *eq;
765 int ncomp_vec;
766 int nent;
767 int err;
768 int i;
769
770 INIT_LIST_HEAD(&table->comp_eqs_list);
771 ncomp_vec = table->num_comp_vectors;
772 nent = MLX5_COMP_EQ_SIZE;
5a7b27eb
MG		 773#ifdef CONFIG_RFS_ACCEL
774 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
775 if (!dev->rmap)
776 return -ENOMEM;
777#endif
233d05d2
SM		 778 for (i = 0; i < ncomp_vec; i++) {
779 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
780 if (!eq) {
781 err = -ENOMEM;
782 goto clean;
783 }
784
5a7b27eb 785#ifdef CONFIG_RFS_ACCEL
78249c42
SG		 786 irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
787 MLX5_EQ_VEC_COMP_BASE + i));
5a7b27eb 788#endif
db058a18 789 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 790 err = mlx5_create_map_eq(dev, eq,
791 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
01187175 792 name, MLX5_EQ_TYPE_COMP);
233d05d2
SM		 793 if (err) {
794 kfree(eq);
795 goto clean;
796 }
797 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
798 eq->index = i;
799 spin_lock(&table->lock);
800 list_add_tail(&eq->list, &table->comp_eqs_list);
801 spin_unlock(&table->lock);
802 }
803
804 return 0;
805
806clean:
807 free_comp_eqs(dev);
808 return err;
809}
810
f62b8bb8
AV		 811static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
812{
c4f287c4
SM		 813 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
814 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
f62b8bb8 815 u32 sup_issi;
c4f287c4 816 int err;
f62b8bb8
AV		 817
818 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
c4f287c4
SM		 819 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
820 query_out, sizeof(query_out));
f62b8bb8 821 if (err) {
c4f287c4
SM		 822 u32 syndrome;
823 u8 status;
824
825 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
f9c14e46
KH		 826 if (!status || syndrome == MLX5_DRIVER_SYND) {
827 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
828 err, status, syndrome);
829 return err;
f62b8bb8
AV		 830 }
831
f9c14e46
KH		 832 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
833 dev->issi = 0;
834 return 0;
f62b8bb8
AV		 835 }
836
837 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
838
839 if (sup_issi & (1 << 1)) {
c4f287c4
SM		 840 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
841 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
f62b8bb8
AV		 842
843 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
844 MLX5_SET(set_issi_in, set_in, current_issi, 1);
c4f287c4
SM		 845 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
846 set_out, sizeof(set_out));
f62b8bb8 847 if (err) {
f9c14e46
KH		 848 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
849 err);
f62b8bb8
AV		 850 return err;
851 }
852
853 dev->issi = 1;
854
855 return 0;
e74a1db0 856 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 857 return 0;
858 }
859
9eb78923 860 return -EOPNOTSUPP;
f62b8bb8 861}
f62b8bb8 862
a31208b1
MD		 863static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
864{
865 struct pci_dev *pdev = dev->pdev;
866 int err = 0;
e126ba97 867
e126ba97
EC		 868 pci_set_drvdata(dev->pdev, dev);
869 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
870 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
871
872 mutex_init(&priv->pgdir_mutex);
873 INIT_LIST_HEAD(&priv->pgdir_list);
874 spin_lock_init(&priv->mkey_lock);
875
311c7c71
SM		 876 mutex_init(&priv->alloc_mutex);
877
878 priv->numa_node = dev_to_node(&dev->pdev->dev);
879
e126ba97
EC		 880 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
881 if (!priv->dbg_root)
882 return -ENOMEM;
883
89d44f0a 884 err = mlx5_pci_enable_device(dev);
e126ba97 885 if (err) {
1a91de28 886 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 887 goto err_dbg;
888 }
889
890 err = request_bar(pdev);
891 if (err) {
1a91de28 892 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 893 goto err_disable;
894 }
895
896 pci_set_master(pdev);
897
898 err = set_dma_caps(pdev);
899 if (err) {
900 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
901 goto err_clr_master;
902 }
903
904 dev->iseg_base = pci_resource_start(dev->pdev, 0);
905 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
906 if (!dev->iseg) {
907 err = -ENOMEM;
908 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
909 goto err_clr_master;
910 }
a31208b1
MD		 911
912 return 0;
913
914err_clr_master:
915 pci_clear_master(dev->pdev);
916 release_bar(dev->pdev);
917err_disable:
89d44f0a 918 mlx5_pci_disable_device(dev);
a31208b1
MD		 919
920err_dbg:
921 debugfs_remove(priv->dbg_root);
922 return err;
923}
924
925static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
926{
927 iounmap(dev->iseg);
928 pci_clear_master(dev->pdev);
929 release_bar(dev->pdev);
89d44f0a 930 mlx5_pci_disable_device(dev);
a31208b1
MD		 931 debugfs_remove(priv->dbg_root);
932}
933
59211bd3
MHY		 934static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
935{
936 struct pci_dev *pdev = dev->pdev;
937 int err;
938
59211bd3
MHY		 939 err = mlx5_query_board_id(dev);
940 if (err) {
941 dev_err(&pdev->dev, "query board id failed\n");
942 goto out;
943 }
944
945 err = mlx5_eq_init(dev);
946 if (err) {
947 dev_err(&pdev->dev, "failed to initialize eq\n");
948 goto out;
949 }
950
02d92f79 951 err = mlx5_cq_debugfs_init(dev);
59211bd3 952 if (err) {
02d92f79 953 dev_err(&pdev->dev, "failed to initialize cq debugfs\n");
59211bd3
MHY		 954 goto err_eq_cleanup;
955 }
956
957 mlx5_init_qp_table(dev);
958
959 mlx5_init_srq_table(dev);
960
961 mlx5_init_mkey_table(dev);
962
52ec462e
IT		 963 mlx5_init_reserved_gids(dev);
964
7c39afb3
FD		 965 mlx5_init_clock(dev);
966
358aa5ce
SM		 967 dev->vxlan = mlx5_vxlan_create(dev);
968
59211bd3
MHY		 969 err = mlx5_init_rl_table(dev);
970 if (err) {
971 dev_err(&pdev->dev, "Failed to init rate limiting\n");
972 goto err_tables_cleanup;
973 }
974
eeb66cdb
SM		 975 err = mlx5_mpfs_init(dev);
976 if (err) {
977 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
978 goto err_rl_cleanup;
979 }
980
c2d6e31a
MHY		 981 err = mlx5_eswitch_init(dev);
982 if (err) {
983 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
eeb66cdb 984 goto err_mpfs_cleanup;
c2d6e31a 985 }
c2d6e31a
MHY		 986
987 err = mlx5_sriov_init(dev);
988 if (err) {
989 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
990 goto err_eswitch_cleanup;
991 }
992
9410733c
IT		 993 err = mlx5_fpga_init(dev);
994 if (err) {
995 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
996 goto err_sriov_cleanup;
997 }
998
24406953
FD		 999 dev->tracer = mlx5_fw_tracer_create(dev);
1000
59211bd3
MHY		 1001 return 0;
1002
9410733c
IT		 1003err_sriov_cleanup:
1004 mlx5_sriov_cleanup(dev);
c2d6e31a 1005err_eswitch_cleanup:
c2d6e31a 1006 mlx5_eswitch_cleanup(dev->priv.eswitch);
eeb66cdb 1007err_mpfs_cleanup:
eeb66cdb 1008 mlx5_mpfs_cleanup(dev);
c2d6e31a 1009err_rl_cleanup:
c2d6e31a 1010 mlx5_cleanup_rl_table(dev);
59211bd3 1011err_tables_cleanup:
358aa5ce 1012 mlx5_vxlan_destroy(dev->vxlan);
59211bd3
MHY		 1013 mlx5_cleanup_mkey_table(dev);
1014 mlx5_cleanup_srq_table(dev);
1015 mlx5_cleanup_qp_table(dev);
02d92f79 1016 mlx5_cq_debugfs_cleanup(dev);
59211bd3
MHY		 1017
1018err_eq_cleanup:
1019 mlx5_eq_cleanup(dev);
1020
1021out:
1022 return err;
1023}
1024
1025static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1026{
24406953 1027 mlx5_fw_tracer_destroy(dev->tracer);
9410733c 1028 mlx5_fpga_cleanup(dev);
c2d6e31a 1029 mlx5_sriov_cleanup(dev);
c2d6e31a 1030 mlx5_eswitch_cleanup(dev->priv.eswitch);
eeb66cdb 1031 mlx5_mpfs_cleanup(dev);
59211bd3 1032 mlx5_cleanup_rl_table(dev);
358aa5ce 1033 mlx5_vxlan_destroy(dev->vxlan);
7c39afb3 1034 mlx5_cleanup_clock(dev);
52ec462e 1035 mlx5_cleanup_reserved_gids(dev);
59211bd3
MHY		 1036 mlx5_cleanup_mkey_table(dev);
1037 mlx5_cleanup_srq_table(dev);
1038 mlx5_cleanup_qp_table(dev);
02d92f79 1039 mlx5_cq_debugfs_cleanup(dev);
59211bd3
MHY		 1040 mlx5_eq_cleanup(dev);
1041}
1042
1043static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1044 bool boot)
a31208b1
MD		 1045{
1046 struct pci_dev *pdev = dev->pdev;
1047 int err;
1048
89d44f0a 1049 mutex_lock(&dev->intf_state_mutex);
5fc7197d 1050 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 1051 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1052 __func__);
1053 goto out;
1054 }
1055
e126ba97
EC		 1056 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1057 fw_rev_min(dev), fw_rev_sub(dev));
1058
00c6bcb0
TG		 1059 /* Only PFs hold the relevant PCIe information for this query */
1060 if (mlx5_core_is_pf(dev))
1061 pcie_print_link_status(dev->pdev);
1062
89d44f0a
MD		 1063 /* on load removing any previous indication of internal error, device is
1064 * up
1065 */
1066 dev->state = MLX5_DEVICE_STATE_UP;
1067
6c780a02
EC		 1068 /* wait for firmware to accept initialization segments configurations
1069 */
1070 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
1071 if (err) {
1072 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
1073 FW_PRE_INIT_TIMEOUT_MILI);
8ce59b16 1074 goto out_err;
6c780a02
EC		 1075 }
1076
e126ba97
EC		 1077 err = mlx5_cmd_init(dev);
1078 if (err) {
1079 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 1080 goto out_err;
e126ba97
EC		 1081 }
1082
e3297246
EC		 1083 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1084 if (err) {
1085 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1086 FW_INIT_TIMEOUT_MILI);
55378a23 1087 goto err_cmd_cleanup;
e3297246
EC		 1088 }
1089
0b107106 1090 err = mlx5_core_enable_hca(dev, 0);
cd23b14b
EC		 1091 if (err) {
1092 dev_err(&pdev->dev, "enable hca failed\n");
59211bd3 1093 goto err_cmd_cleanup;
cd23b14b
EC		 1094 }
1095
f62b8bb8
AV		 1096 err = mlx5_core_set_issi(dev);
1097 if (err) {
1098 dev_err(&pdev->dev, "failed to set issi\n");
1099 goto err_disable_hca;
1100 }
f62b8bb8 1101
cd23b14b
EC		 1102 err = mlx5_satisfy_startup_pages(dev, 1);
1103 if (err) {
1104 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1105 goto err_disable_hca;
1106 }
1107
e126ba97
EC		 1108 err = set_hca_ctrl(dev);
1109 if (err) {
1110 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 1111 goto reclaim_boot_pages;
e126ba97
EC		 1112 }
1113
1114 err = handle_hca_cap(dev);
1115 if (err) {
1116 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 1117 goto reclaim_boot_pages;
e126ba97
EC		 1118 }
1119
f91e6d89
EBE		 1120 err = handle_hca_cap_atomic(dev);
1121 if (err) {
1122 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1123 goto reclaim_boot_pages;
e126ba97
EC		 1124 }
1125
cd23b14b 1126 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 1127 if (err) {
cd23b14b
EC		 1128 dev_err(&pdev->dev, "failed to allocate init pages\n");
1129 goto reclaim_boot_pages;
e126ba97
EC		 1130 }
1131
1132 err = mlx5_pagealloc_start(dev);
1133 if (err) {
1134 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 1135 goto reclaim_boot_pages;
e126ba97
EC		 1136 }
1137
8737f818 1138 err = mlx5_cmd_init_hca(dev, sw_owner_id);
e126ba97
EC		 1139 if (err) {
1140 dev_err(&pdev->dev, "init hca failed\n");
1141 goto err_pagealloc_stop;
1142 }
1143
012e50e1
HN		 1144 mlx5_set_driver_version(dev);
1145
e126ba97
EC		 1146 mlx5_start_health_poll(dev);
1147
bba1574c
DJ		 1148 err = mlx5_query_hca_caps(dev);
1149 if (err) {
1150 dev_err(&pdev->dev, "query hca failed\n");
1151 goto err_stop_poll;
1152 }
1153
259bbc57
MG		 1154 if (boot) {
1155 err = mlx5_init_once(dev, priv);
1156 if (err) {
1157 dev_err(&pdev->dev, "sw objs init failed\n");
1158 goto err_stop_poll;
1159 }
e126ba97
EC		 1160 }
1161
78249c42 1162 err = mlx5_alloc_irq_vectors(dev);
e126ba97 1163 if (err) {
78249c42 1164 dev_err(&pdev->dev, "alloc irq vectors failed\n");
59211bd3 1165 goto err_cleanup_once;
e126ba97
EC		 1166 }
1167
01187175 1168 dev->priv.uar = mlx5_get_uars_page(dev);
72f36be0 1169 if (IS_ERR(dev->priv.uar)) {
e126ba97 1170 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
72f36be0 1171 err = PTR_ERR(dev->priv.uar);
59211bd3 1172 goto err_disable_msix;
e126ba97
EC		 1173 }
1174
1175 err = mlx5_start_eqs(dev);
1176 if (err) {
1177 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
9410733c 1178 goto err_put_uars;
e126ba97
EC		 1179 }
1180
24406953
FD		 1181 err = mlx5_fw_tracer_init(dev->tracer);
1182 if (err) {
1183 dev_err(&pdev->dev, "Failed to init FW tracer\n");
1184 goto err_fw_tracer;
1185 }
1186
233d05d2
SM		 1187 err = alloc_comp_eqs(dev);
1188 if (err) {
1189 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
24406953 1190 goto err_comp_eqs;
233d05d2
SM		 1191 }
1192
231243c8
SM		 1193 err = mlx5_irq_set_affinity_hints(dev);
1194 if (err) {
1195 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1196 goto err_affinity_hints;
1197 }
1198
04e87170
MB		 1199 err = mlx5_fpga_device_start(dev);
1200 if (err) {
1201 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1202 goto err_fpga_start;
1203 }
1204
1205 err = mlx5_accel_ipsec_init(dev);
1206 if (err) {
1207 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1208 goto err_ipsec_start;
1209 }
1210
1ae17322
IL		 1211 err = mlx5_accel_tls_init(dev);
1212 if (err) {
1213 dev_err(&pdev->dev, "TLS device start failed %d\n", err);
1214 goto err_tls_start;
1215 }
1216
86d722ad 1217 err = mlx5_init_fs(dev);
59211bd3 1218 if (err) {
86d722ad 1219 dev_err(&pdev->dev, "Failed to init flow steering\n");
c85023e1 1220 goto err_fs;
59211bd3 1221 }
e126ba97 1222
c85023e1 1223 err = mlx5_core_set_hca_defaults(dev);
86d722ad 1224 if (err) {
c85023e1 1225 dev_err(&pdev->dev, "Failed to set hca defaults\n");
86d722ad
MG		 1226 goto err_fs;
1227 }
1466cc5b 1228
c2d6e31a 1229 err = mlx5_sriov_attach(dev);
fc50db98
EC		 1230 if (err) {
1231 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1232 goto err_sriov;
1233 }
1234
737a234b
MHY		 1235 if (mlx5_device_registered(dev)) {
1236 mlx5_attach_device(dev);
1237 } else {
1238 err = mlx5_register_device(dev);
1239 if (err) {
1240 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1241 goto err_reg_dev;
1242 }
a31208b1
MD		 1243 }
1244
5fc7197d 1245 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
89d44f0a
MD		 1246out:
1247 mutex_unlock(&dev->intf_state_mutex);
1248
e126ba97
EC		 1249 return 0;
1250
59211bd3 1251err_reg_dev:
c2d6e31a 1252 mlx5_sriov_detach(dev);
fc50db98 1253
59211bd3 1254err_sriov:
86d722ad 1255 mlx5_cleanup_fs(dev);
59211bd3 1256
86d722ad 1257err_fs:
1ae17322
IL		 1258 mlx5_accel_tls_cleanup(dev);
1259
1260err_tls_start:
04e87170
MB		 1261 mlx5_accel_ipsec_cleanup(dev);
1262
1263err_ipsec_start:
1264 mlx5_fpga_device_stop(dev);
1265
1266err_fpga_start:
231243c8
SM		 1267 mlx5_irq_clear_affinity_hints(dev);
1268
1269err_affinity_hints:
db058a18
SM		 1270 free_comp_eqs(dev);
1271
24406953
FD		 1272err_comp_eqs:
1273 mlx5_fw_tracer_cleanup(dev->tracer);
1274
1275err_fw_tracer:
233d05d2
SM		 1276 mlx5_stop_eqs(dev);
1277
5fe9dec0 1278err_put_uars:
01187175 1279 mlx5_put_uars_page(dev, priv->uar);
e126ba97 1280
59211bd3 1281err_disable_msix:
78249c42 1282 mlx5_free_irq_vectors(dev);
e126ba97 1283
59211bd3
MHY		 1284err_cleanup_once:
1285 if (boot)
1286 mlx5_cleanup_once(dev);
1287
e126ba97 1288err_stop_poll:
76d5581c 1289 mlx5_stop_health_poll(dev, boot);
1bde6e30
EC		 1290 if (mlx5_cmd_teardown_hca(dev)) {
1291 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1292 goto out_err;
1bde6e30 1293 }
e126ba97
EC		 1294
1295err_pagealloc_stop:
1296 mlx5_pagealloc_stop(dev);
1297
cd23b14b 1298reclaim_boot_pages:
e126ba97
EC		 1299 mlx5_reclaim_startup_pages(dev);
1300
cd23b14b 1301err_disable_hca:
0b107106 1302 mlx5_core_disable_hca(dev, 0);
cd23b14b 1303
59211bd3 1304err_cmd_cleanup:
e126ba97
EC		 1305 mlx5_cmd_cleanup(dev);
1306
89d44f0a
MD		 1307out_err:
1308 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1309 mutex_unlock(&dev->intf_state_mutex);
1310
e126ba97
EC		 1311 return err;
1312}
e126ba97 1313
59211bd3
MHY		 1314static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1315 bool cleanup)
e126ba97 1316{
89d44f0a 1317 int err = 0;
e126ba97 1318
5e44fca5 1319 if (cleanup)
2a0165a0 1320 mlx5_drain_health_recovery(dev);
689a248d 1321
89d44f0a 1322 mutex_lock(&dev->intf_state_mutex);
b3cb5388 1323 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 1324 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1325 __func__);
59211bd3
MHY		 1326 if (cleanup)
1327 mlx5_cleanup_once(dev);
89d44f0a
MD		 1328 goto out;
1329 }
6b6adee3 1330
9ade8c7c 1331 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
9ade8c7c 1332
737a234b
MHY		 1333 if (mlx5_device_registered(dev))
1334 mlx5_detach_device(dev);
1335
c2d6e31a 1336 mlx5_sriov_detach(dev);
86d722ad 1337 mlx5_cleanup_fs(dev);
04e87170 1338 mlx5_accel_ipsec_cleanup(dev);
1ae17322 1339 mlx5_accel_tls_cleanup(dev);
04e87170 1340 mlx5_fpga_device_stop(dev);
231243c8 1341 mlx5_irq_clear_affinity_hints(dev);
233d05d2 1342 free_comp_eqs(dev);
24406953 1343 mlx5_fw_tracer_cleanup(dev->tracer);
e126ba97 1344 mlx5_stop_eqs(dev);
01187175 1345 mlx5_put_uars_page(dev, priv->uar);
78249c42 1346 mlx5_free_irq_vectors(dev);
59211bd3
MHY		 1347 if (cleanup)
1348 mlx5_cleanup_once(dev);
76d5581c 1349 mlx5_stop_health_poll(dev, cleanup);
ac6ea6e8
EC		 1350 err = mlx5_cmd_teardown_hca(dev);
1351 if (err) {
1bde6e30 1352 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1353 goto out;
1bde6e30 1354 }
e126ba97
EC		 1355 mlx5_pagealloc_stop(dev);
1356 mlx5_reclaim_startup_pages(dev);
0b107106 1357 mlx5_core_disable_hca(dev, 0);
e126ba97 1358 mlx5_cmd_cleanup(dev);
9603b61d 1359
ac6ea6e8 1360out:
89d44f0a 1361 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1362 return err;
9603b61d 1363}
64613d94 1364
9603b61d
JM		 1365struct mlx5_core_event_handler {
1366 void (*event)(struct mlx5_core_dev *dev,
1367 enum mlx5_dev_event event,
1368 void *data);
1369};
1370
feae9087 1371static const struct devlink_ops mlx5_devlink_ops = {
e80541ec 1372#ifdef CONFIG_MLX5_ESWITCH
feae9087
OG		 1373 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1374 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
bffaa916
RD		 1375 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1376 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
7768d197
RD		 1377 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1378 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
feae9087
OG		 1379#endif
1380};
f66f049f 1381
59211bd3 1382#define MLX5_IB_MOD "mlx5_ib"
9603b61d
JM		 1383static int init_one(struct pci_dev *pdev,
1384 const struct pci_device_id *id)
1385{
1386 struct mlx5_core_dev *dev;
feae9087 1387 struct devlink *devlink;
9603b61d
JM		 1388 struct mlx5_priv *priv;
1389 int err;
1390
feae9087
OG		 1391 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1392 if (!devlink) {
9603b61d
JM		 1393 dev_err(&pdev->dev, "kzalloc failed\n");
1394 return -ENOMEM;
1395 }
feae9087
OG		 1396
1397 dev = devlink_priv(devlink);
9603b61d 1398 priv = &dev->priv;
fc50db98 1399 priv->pci_dev_data = id->driver_data;
9603b61d
JM		 1400
1401 pci_set_drvdata(pdev, dev);
1402
0e97a340
HN		 1403 dev->pdev = pdev;
1404 dev->event = mlx5_core_event;
9603b61d 1405 dev->profile = &profile[prof_sel];
9603b61d 1406
364d1798
EC		 1407 INIT_LIST_HEAD(&priv->ctx_list);
1408 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1409 mutex_init(&dev->pci_status_mutex);
1410 mutex_init(&dev->intf_state_mutex);
d9aaed83 1411
97834eba
ES		 1412 INIT_LIST_HEAD(&priv->waiting_events_list);
1413 priv->is_accum_events = false;
1414
d9aaed83
AK		 1415#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1416 err = init_srcu_struct(&priv->pfault_srcu);
1417 if (err) {
1418 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1419 err);
1420 goto clean_dev;
1421 }
1422#endif
01187175
EC		 1423 mutex_init(&priv->bfregs.reg_head.lock);
1424 mutex_init(&priv->bfregs.wc_head.lock);
1425 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1426 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1427
a31208b1 1428 err = mlx5_pci_init(dev, priv);
9603b61d 1429 if (err) {
a31208b1 1430 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
d9aaed83 1431 goto clean_srcu;
9603b61d
JM		 1432 }
1433
ac6ea6e8
EC		 1434 err = mlx5_health_init(dev);
1435 if (err) {
1436 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1437 goto close_pci;
1438 }
1439
59211bd3
MHY		 1440 mlx5_pagealloc_init(dev);
1441
1442 err = mlx5_load_one(dev, priv, true);
9603b61d 1443 if (err) {
a31208b1 1444 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1445 goto clean_health;
9603b61d 1446 }
59211bd3 1447
f82eed45 1448 request_module_nowait(MLX5_IB_MOD);
9603b61d 1449
feae9087
OG		 1450 err = devlink_register(devlink, &pdev->dev);
1451 if (err)
1452 goto clean_load;
1453
5d47f6c8 1454 pci_save_state(pdev);
9603b61d
JM		 1455 return 0;
1456
feae9087 1457clean_load:
59211bd3 1458 mlx5_unload_one(dev, priv, true);
ac6ea6e8 1459clean_health:
59211bd3 1460 mlx5_pagealloc_cleanup(dev);
ac6ea6e8 1461 mlx5_health_cleanup(dev);
a31208b1
MD		 1462close_pci:
1463 mlx5_pci_close(dev, priv);
d9aaed83
AK		 1464clean_srcu:
1465#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1466 cleanup_srcu_struct(&priv->pfault_srcu);
a31208b1 1467clean_dev:
d9aaed83 1468#endif
feae9087 1469 devlink_free(devlink);
a31208b1 1470
9603b61d
JM		 1471 return err;
1472}
a31208b1 1473
9603b61d
JM		 1474static void remove_one(struct pci_dev *pdev)
1475{
1476 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
feae9087 1477 struct devlink *devlink = priv_to_devlink(dev);
a31208b1 1478 struct mlx5_priv *priv = &dev->priv;
9603b61d 1479
feae9087 1480 devlink_unregister(devlink);
737a234b
MHY		 1481 mlx5_unregister_device(dev);
1482
59211bd3 1483 if (mlx5_unload_one(dev, priv, true)) {
a31208b1 1484 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1485 mlx5_health_cleanup(dev);
a31208b1
MD		 1486 return;
1487 }
737a234b 1488
59211bd3 1489 mlx5_pagealloc_cleanup(dev);
ac6ea6e8 1490 mlx5_health_cleanup(dev);
a31208b1 1491 mlx5_pci_close(dev, priv);
d9aaed83
AK		 1492#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1493 cleanup_srcu_struct(&priv->pfault_srcu);
1494#endif
feae9087 1495 devlink_free(devlink);
9603b61d
JM		 1496}
1497
89d44f0a
MD		 1498static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1499 pci_channel_state_t state)
1500{
1501 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1502 struct mlx5_priv *priv = &dev->priv;
1503
1504 dev_info(&pdev->dev, "%s was called\n", __func__);
04c0c1ab 1505
8812c24d 1506 mlx5_enter_error_state(dev, false);
59211bd3 1507 mlx5_unload_one(dev, priv, false);
5d47f6c8 1508 /* In case of kernel call drain the health wq */
05ac2c0b 1509 if (state) {
5e44fca5 1510 mlx5_drain_health_wq(dev);
05ac2c0b
MHY		 1511 mlx5_pci_disable_device(dev);
1512 }
1513
89d44f0a
MD		 1514 return state == pci_channel_io_perm_failure ?
1515 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1516}
1517
d57847dc
DJ		 1518/* wait for the device to show vital signs by waiting
1519 * for the health counter to start counting.
89d44f0a 1520 */
d57847dc 1521static int wait_vital(struct pci_dev *pdev)
89d44f0a
MD		 1522{
1523 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1524 struct mlx5_core_health *health = &dev->priv.health;
1525 const int niter = 100;
d57847dc 1526 u32 last_count = 0;
89d44f0a 1527 u32 count;
89d44f0a
MD		 1528 int i;
1529
89d44f0a
MD		 1530 for (i = 0; i < niter; i++) {
1531 count = ioread32be(health->health_counter);
1532 if (count && count != 0xffffffff) {
d57847dc
DJ		 1533 if (last_count && last_count != count) {
1534 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1535 return 0;
1536 }
1537 last_count = count;
89d44f0a
MD		 1538 }
1539 msleep(50);
1540 }
1541
d57847dc 1542 return -ETIMEDOUT;
89d44f0a
MD		 1543}
1544
1061c90f 1545static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
89d44f0a
MD		 1546{
1547 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
89d44f0a
MD		 1548 int err;
1549
1550 dev_info(&pdev->dev, "%s was called\n", __func__);
1551
1061c90f 1552 err = mlx5_pci_enable_device(dev);
d57847dc 1553 if (err) {
1061c90f
MHY		 1554 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1555 , __func__, err);
1556 return PCI_ERS_RESULT_DISCONNECT;
1557 }
1558
1559 pci_set_master(pdev);
1560 pci_restore_state(pdev);
5d47f6c8 1561 pci_save_state(pdev);
1061c90f
MHY		 1562
1563 if (wait_vital(pdev)) {
d57847dc 1564 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1061c90f 1565 return PCI_ERS_RESULT_DISCONNECT;
d57847dc 1566 }
89d44f0a 1567
1061c90f
MHY		 1568 return PCI_ERS_RESULT_RECOVERED;
1569}
1570
1061c90f
MHY		 1571static void mlx5_pci_resume(struct pci_dev *pdev)
1572{
1573 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1574 struct mlx5_priv *priv = &dev->priv;
1575 int err;
1576
1577 dev_info(&pdev->dev, "%s was called\n", __func__);
1578
59211bd3 1579 err = mlx5_load_one(dev, priv, false);
89d44f0a
MD		 1580 if (err)
1581 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1582 , __func__, err);
1583 else
1584 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1585}
1586
1587static const struct pci_error_handlers mlx5_err_handler = {
1588 .error_detected = mlx5_pci_err_detected,
1589 .slot_reset = mlx5_pci_slot_reset,
1590 .resume = mlx5_pci_resume
1591};
1592
8812c24d
MD		 1593static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1594{
1595 int ret;
1596
1597 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1598 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1599 return -EOPNOTSUPP;
1600 }
1601
1602 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1603 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1604 return -EAGAIN;
1605 }
1606
d2aa060d
HN		 1607 /* Panic tear down fw command will stop the PCI bus communication
1608 * with the HCA, so the health polll is no longer needed.
1609 */
1610 mlx5_drain_health_wq(dev);
76d5581c 1611 mlx5_stop_health_poll(dev, false);
d2aa060d 1612
8812c24d
MD		 1613 ret = mlx5_cmd_force_teardown_hca(dev);
1614 if (ret) {
1615 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
d2aa060d 1616 mlx5_start_health_poll(dev);
8812c24d
MD		 1617 return ret;
1618 }
1619
1620 mlx5_enter_error_state(dev, true);
1621
1ef903bf
DJ		 1622 /* Some platforms requiring freeing the IRQ's in the shutdown
1623 * flow. If they aren't freed they can't be allocated after
1624 * kexec. There is no need to cleanup the mlx5_core software
1625 * contexts.
1626 */
1627 mlx5_irq_clear_affinity_hints(dev);
1628 mlx5_core_eq_free_irqs(dev);
1629
8812c24d
MD		 1630 return 0;
1631}
1632
5fc7197d
MD		 1633static void shutdown(struct pci_dev *pdev)
1634{
1635 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1636 struct mlx5_priv *priv = &dev->priv;
8812c24d 1637 int err;
5fc7197d
MD		 1638
1639 dev_info(&pdev->dev, "Shutdown was called\n");
8812c24d
MD		 1640 err = mlx5_try_fast_unload(dev);
1641 if (err)
1642 mlx5_unload_one(dev, priv, false);
5fc7197d
MD		 1643 mlx5_pci_disable_device(dev);
1644}
1645
9603b61d 1646static const struct pci_device_id mlx5_core_pci_table[] = {
bbad7c21 1647 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
fc50db98 1648 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
bbad7c21 1649 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
fc50db98 1650 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
bbad7c21 1651 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
fc50db98 1652 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
7092fe86 1653 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
64dbbdfe 1654 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
d0dd989f
MD		 1655 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1656 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1657 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1658 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2e9d3e83
NO		 1659 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1660 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
9603b61d
JM		 1661 { 0, }
1662};
1663
1664MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1665
04c0c1ab
MHY		 1666void mlx5_disable_device(struct mlx5_core_dev *dev)
1667{
1668 mlx5_pci_err_detected(dev->pdev, 0);
1669}
1670
1671void mlx5_recover_device(struct mlx5_core_dev *dev)
1672{
1673 mlx5_pci_disable_device(dev);
1674 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1675 mlx5_pci_resume(dev->pdev);
1676}
1677
9603b61d
JM		 1678static struct pci_driver mlx5_core_driver = {
1679 .name = DRIVER_NAME,
1680 .id_table = mlx5_core_pci_table,
1681 .probe = init_one,
89d44f0a 1682 .remove = remove_one,
5fc7197d 1683 .shutdown = shutdown,
fc50db98
EC		 1684 .err_handler = &mlx5_err_handler,
1685 .sriov_configure = mlx5_core_sriov_configure,
9603b61d 1686};
e126ba97 1687
f663ad98
KH		 1688static void mlx5_core_verify_params(void)
1689{
1690 if (prof_sel >= ARRAY_SIZE(profile)) {
1691 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1692 prof_sel,
1693 ARRAY_SIZE(profile) - 1,
1694 MLX5_DEFAULT_PROF);
1695 prof_sel = MLX5_DEFAULT_PROF;
1696 }
1697}
1698
e126ba97
EC		 1699static int __init init(void)
1700{
1701 int err;
1702
8737f818
DJ		 1703 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1704
f663ad98 1705 mlx5_core_verify_params();
05564d0a 1706 mlx5_fpga_ipsec_build_fs_cmds();
e126ba97 1707 mlx5_register_debugfs();
e126ba97 1708
9603b61d
JM		 1709 err = pci_register_driver(&mlx5_core_driver);
1710 if (err)
ac6ea6e8 1711 goto err_debug;
9603b61d 1712
f62b8bb8
AV		 1713#ifdef CONFIG_MLX5_CORE_EN
1714 mlx5e_init();
1715#endif
1716
e126ba97
EC		 1717 return 0;
1718
e126ba97
EC		 1719err_debug:
1720 mlx5_unregister_debugfs();
1721 return err;
1722}
1723
1724static void __exit cleanup(void)
1725{
f62b8bb8
AV		 1726#ifdef CONFIG_MLX5_CORE_EN
1727 mlx5e_cleanup();
1728#endif
9603b61d 1729 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1730 mlx5_unregister_debugfs();
1731}
1732
1733module_init(init);
1734module_exit(cleanup);
Linux 6.x block layer and io_uring tree(s)