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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
e126ba97 | 46 | #include <linux/debugfs.h> |
f66f049f | 47 | #include <linux/kmod.h> |
b775516b | 48 | #include <linux/mlx5/mlx5_ifc.h> |
c85023e1 | 49 | #include <linux/mlx5/vport.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
feae9087 | 53 | #include <net/devlink.h> |
e126ba97 | 54 | #include "mlx5_core.h" |
f2f3df55 | 55 | #include "lib/eq.h" |
16d76083 | 56 | #include "fs_core.h" |
eeb66cdb | 57 | #include "lib/mpfs.h" |
073bb189 | 58 | #include "eswitch.h" |
1f28d776 | 59 | #include "devlink.h" |
52ec462e | 60 | #include "lib/mlx5.h" |
e29341fb | 61 | #include "fpga/core.h" |
05564d0a | 62 | #include "fpga/ipsec.h" |
bebb23e6 | 63 | #include "accel/ipsec.h" |
1ae17322 | 64 | #include "accel/tls.h" |
7c39afb3 | 65 | #include "lib/clock.h" |
358aa5ce | 66 | #include "lib/vxlan.h" |
0ccc171e | 67 | #include "lib/geneve.h" |
fadd59fc | 68 | #include "lib/devcom.h" |
b25bbc2f | 69 | #include "lib/pci_vsc.h" |
24406953 | 70 | #include "diag/fw_tracer.h" |
591905ba | 71 | #include "ecpf.h" |
87175120 | 72 | #include "lib/hv_vhca.h" |
12206b17 | 73 | #include "diag/rsc_dump.h" |
e126ba97 | 74 | |
e126ba97 | 75 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
048f3143 | 76 | MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); |
e126ba97 EC |
77 | MODULE_LICENSE("Dual BSD/GPL"); |
78 | MODULE_VERSION(DRIVER_VERSION); | |
79 | ||
f663ad98 KH |
80 | unsigned int mlx5_core_debug_mask; |
81 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
82 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
83 | ||
9603b61d | 84 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
85 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
86 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
87 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
88 | ||
8737f818 DJ |
89 | static u32 sw_owner_id[4]; |
90 | ||
f91e6d89 EBE |
91 | enum { |
92 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
93 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
94 | }; | |
95 | ||
9603b61d JM |
96 | static struct mlx5_profile profile[] = { |
97 | [0] = { | |
98 | .mask = 0, | |
99 | }, | |
100 | [1] = { | |
101 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
102 | .log_max_qp = 12, | |
103 | }, | |
104 | [2] = { | |
105 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
106 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 107 | .log_max_qp = 18, |
9603b61d JM |
108 | .mr_cache[0] = { |
109 | .size = 500, | |
110 | .limit = 250 | |
111 | }, | |
112 | .mr_cache[1] = { | |
113 | .size = 500, | |
114 | .limit = 250 | |
115 | }, | |
116 | .mr_cache[2] = { | |
117 | .size = 500, | |
118 | .limit = 250 | |
119 | }, | |
120 | .mr_cache[3] = { | |
121 | .size = 500, | |
122 | .limit = 250 | |
123 | }, | |
124 | .mr_cache[4] = { | |
125 | .size = 500, | |
126 | .limit = 250 | |
127 | }, | |
128 | .mr_cache[5] = { | |
129 | .size = 500, | |
130 | .limit = 250 | |
131 | }, | |
132 | .mr_cache[6] = { | |
133 | .size = 500, | |
134 | .limit = 250 | |
135 | }, | |
136 | .mr_cache[7] = { | |
137 | .size = 500, | |
138 | .limit = 250 | |
139 | }, | |
140 | .mr_cache[8] = { | |
141 | .size = 500, | |
142 | .limit = 250 | |
143 | }, | |
144 | .mr_cache[9] = { | |
145 | .size = 500, | |
146 | .limit = 250 | |
147 | }, | |
148 | .mr_cache[10] = { | |
149 | .size = 500, | |
150 | .limit = 250 | |
151 | }, | |
152 | .mr_cache[11] = { | |
153 | .size = 500, | |
154 | .limit = 250 | |
155 | }, | |
156 | .mr_cache[12] = { | |
157 | .size = 64, | |
158 | .limit = 32 | |
159 | }, | |
160 | .mr_cache[13] = { | |
161 | .size = 32, | |
162 | .limit = 16 | |
163 | }, | |
164 | .mr_cache[14] = { | |
165 | .size = 16, | |
166 | .limit = 8 | |
167 | }, | |
168 | .mr_cache[15] = { | |
169 | .size = 8, | |
170 | .limit = 4 | |
171 | }, | |
172 | }, | |
173 | }; | |
e126ba97 | 174 | |
6c780a02 EC |
175 | #define FW_INIT_TIMEOUT_MILI 2000 |
176 | #define FW_INIT_WAIT_MS 2 | |
b8a92577 DJ |
177 | #define FW_PRE_INIT_TIMEOUT_MILI 120000 |
178 | #define FW_INIT_WARN_MESSAGE_INTERVAL 20000 | |
e3297246 | 179 | |
555af0c3 PP |
180 | static int fw_initializing(struct mlx5_core_dev *dev) |
181 | { | |
182 | return ioread32be(&dev->iseg->initializing) >> 31; | |
183 | } | |
184 | ||
b8a92577 DJ |
185 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, |
186 | u32 warn_time_mili) | |
e3297246 | 187 | { |
b8a92577 | 188 | unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); |
e3297246 EC |
189 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); |
190 | int err = 0; | |
191 | ||
b8a92577 DJ |
192 | BUILD_BUG_ON(FW_PRE_INIT_TIMEOUT_MILI < FW_INIT_WARN_MESSAGE_INTERVAL); |
193 | ||
e3297246 EC |
194 | while (fw_initializing(dev)) { |
195 | if (time_after(jiffies, end)) { | |
196 | err = -EBUSY; | |
197 | break; | |
198 | } | |
b8a92577 DJ |
199 | if (warn_time_mili && time_after(jiffies, warn)) { |
200 | mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds\n", | |
201 | jiffies_to_msecs(end - warn) / 1000); | |
202 | warn = jiffies + msecs_to_jiffies(warn_time_mili); | |
203 | } | |
e3297246 EC |
204 | msleep(FW_INIT_WAIT_MS); |
205 | } | |
206 | ||
207 | return err; | |
208 | } | |
209 | ||
012e50e1 HN |
210 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
211 | { | |
212 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
213 | driver_version); | |
3ac0e69e | 214 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; |
012e50e1 HN |
215 | int remaining_size = driver_ver_sz; |
216 | char *string; | |
217 | ||
218 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
219 | return; | |
220 | ||
221 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
222 | ||
223 | strncpy(string, "Linux", remaining_size); | |
224 | ||
225 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
226 | strncat(string, ",", remaining_size); | |
227 | ||
228 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
229 | strncat(string, DRIVER_NAME, remaining_size); | |
230 | ||
231 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
232 | strncat(string, ",", remaining_size); | |
233 | ||
234 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
235 | strncat(string, DRIVER_VERSION, remaining_size); | |
236 | ||
237 | /*Send the command*/ | |
238 | MLX5_SET(set_driver_version_in, in, opcode, | |
239 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
240 | ||
3ac0e69e | 241 | mlx5_cmd_exec_in(dev, set_driver_version, in); |
012e50e1 HN |
242 | } |
243 | ||
e126ba97 EC |
244 | static int set_dma_caps(struct pci_dev *pdev) |
245 | { | |
246 | int err; | |
247 | ||
248 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
249 | if (err) { | |
1a91de28 | 250 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
251 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
252 | if (err) { | |
1a91de28 | 253 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
254 | return err; |
255 | } | |
256 | } | |
257 | ||
258 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
259 | if (err) { | |
260 | dev_warn(&pdev->dev, | |
1a91de28 | 261 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
262 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
263 | if (err) { | |
264 | dev_err(&pdev->dev, | |
1a91de28 | 265 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
266 | return err; |
267 | } | |
268 | } | |
269 | ||
270 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
271 | return err; | |
272 | } | |
273 | ||
89d44f0a MD |
274 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
275 | { | |
276 | struct pci_dev *pdev = dev->pdev; | |
277 | int err = 0; | |
278 | ||
279 | mutex_lock(&dev->pci_status_mutex); | |
280 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
281 | err = pci_enable_device(pdev); | |
282 | if (!err) | |
283 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
284 | } | |
285 | mutex_unlock(&dev->pci_status_mutex); | |
286 | ||
287 | return err; | |
288 | } | |
289 | ||
290 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
291 | { | |
292 | struct pci_dev *pdev = dev->pdev; | |
293 | ||
294 | mutex_lock(&dev->pci_status_mutex); | |
295 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
296 | pci_disable_device(pdev); | |
297 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
298 | } | |
299 | mutex_unlock(&dev->pci_status_mutex); | |
300 | } | |
301 | ||
e126ba97 EC |
302 | static int request_bar(struct pci_dev *pdev) |
303 | { | |
304 | int err = 0; | |
305 | ||
306 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 307 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
308 | return -ENODEV; |
309 | } | |
310 | ||
311 | err = pci_request_regions(pdev, DRIVER_NAME); | |
312 | if (err) | |
313 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
314 | ||
315 | return err; | |
316 | } | |
317 | ||
318 | static void release_bar(struct pci_dev *pdev) | |
319 | { | |
320 | pci_release_regions(pdev); | |
321 | } | |
322 | ||
bd10838a | 323 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
324 | u8 he; |
325 | u8 rsvd[15]; | |
326 | }; | |
327 | ||
87b8de49 EC |
328 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
329 | ||
330 | enum { | |
c7a08ac7 EC |
331 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
332 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
333 | }; |
334 | ||
2974ab6e | 335 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
336 | { |
337 | switch (size) { | |
338 | case 128: | |
339 | return 0; | |
340 | case 256: | |
341 | return 1; | |
342 | case 512: | |
343 | return 2; | |
344 | case 1024: | |
345 | return 3; | |
346 | case 2048: | |
347 | return 4; | |
348 | case 4096: | |
349 | return 5; | |
350 | default: | |
2974ab6e | 351 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
352 | return 0; |
353 | } | |
354 | } | |
355 | ||
b06e7de8 LR |
356 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
357 | enum mlx5_cap_type cap_type, | |
358 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 359 | { |
b775516b EC |
360 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
361 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
362 | void *out, *hca_caps; |
363 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
364 | int err; |
365 | ||
b775516b EC |
366 | memset(in, 0, sizeof(in)); |
367 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 368 | if (!out) |
e126ba97 | 369 | return -ENOMEM; |
938fe83c | 370 | |
b775516b EC |
371 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
372 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
3ac0e69e | 373 | err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); |
c7a08ac7 | 374 | if (err) { |
938fe83c SM |
375 | mlx5_core_warn(dev, |
376 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
377 | cap_type, cap_mode, err); | |
e126ba97 EC |
378 | goto query_ex; |
379 | } | |
c7a08ac7 | 380 | |
938fe83c SM |
381 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
382 | ||
383 | switch (cap_mode) { | |
384 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 385 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
386 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
387 | break; | |
388 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 389 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
390 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
391 | break; | |
392 | default: | |
393 | mlx5_core_warn(dev, | |
394 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
395 | cap_type, cap_mode); | |
396 | err = -EINVAL; | |
397 | break; | |
398 | } | |
c7a08ac7 EC |
399 | query_ex: |
400 | kfree(out); | |
401 | return err; | |
402 | } | |
403 | ||
b06e7de8 LR |
404 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
405 | { | |
406 | int ret; | |
407 | ||
408 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
409 | if (ret) | |
410 | return ret; | |
411 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
412 | } | |
413 | ||
a2a322f4 | 414 | static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) |
c7a08ac7 | 415 | { |
b775516b | 416 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 417 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
3ac0e69e | 418 | return mlx5_cmd_exec_in(dev, set_hca_cap, in); |
c7a08ac7 EC |
419 | } |
420 | ||
a2a322f4 | 421 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) |
f91e6d89 | 422 | { |
f91e6d89 | 423 | void *set_hca_cap; |
f91e6d89 EBE |
424 | int req_endianness; |
425 | int err; | |
426 | ||
a2a322f4 | 427 | if (!MLX5_CAP_GEN(dev, atomic)) |
f91e6d89 | 428 | return 0; |
a2a322f4 LR |
429 | |
430 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); | |
431 | if (err) | |
432 | return err; | |
f91e6d89 EBE |
433 | |
434 | req_endianness = | |
435 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 436 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
437 | |
438 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
439 | return 0; | |
440 | ||
f91e6d89 EBE |
441 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); |
442 | ||
443 | /* Set requestor to host endianness */ | |
bd10838a | 444 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
445 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
446 | ||
a2a322f4 | 447 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); |
f91e6d89 EBE |
448 | } |
449 | ||
a2a322f4 | 450 | static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) |
46861e3e | 451 | { |
46861e3e | 452 | void *set_hca_cap; |
fca22e7e | 453 | bool do_set = false; |
46861e3e MS |
454 | int err; |
455 | ||
37b6bb77 LR |
456 | if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || |
457 | !MLX5_CAP_GEN(dev, pg)) | |
46861e3e MS |
458 | return 0; |
459 | ||
460 | err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); | |
461 | if (err) | |
462 | return err; | |
463 | ||
46861e3e MS |
464 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); |
465 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ODP], | |
466 | MLX5_ST_SZ_BYTES(odp_cap)); | |
467 | ||
fca22e7e MS |
468 | #define ODP_CAP_SET_MAX(dev, field) \ |
469 | do { \ | |
470 | u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ | |
471 | if (_res) { \ | |
472 | do_set = true; \ | |
473 | MLX5_SET(odp_cap, set_hca_cap, field, _res); \ | |
474 | } \ | |
475 | } while (0) | |
476 | ||
477 | ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); | |
478 | ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); | |
479 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); | |
480 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); | |
481 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); | |
482 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); | |
483 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); | |
484 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); | |
00679b63 MG |
485 | ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); |
486 | ODP_CAP_SET_MAX(dev, dc_odp_caps.send); | |
487 | ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); | |
488 | ODP_CAP_SET_MAX(dev, dc_odp_caps.write); | |
489 | ODP_CAP_SET_MAX(dev, dc_odp_caps.read); | |
490 | ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); | |
fca22e7e | 491 | |
a2a322f4 LR |
492 | if (!do_set) |
493 | return 0; | |
fca22e7e | 494 | |
a2a322f4 | 495 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); |
46861e3e MS |
496 | } |
497 | ||
a2a322f4 | 498 | static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) |
c7a08ac7 | 499 | { |
c7a08ac7 | 500 | struct mlx5_profile *prof = dev->profile; |
938fe83c | 501 | void *set_hca_cap; |
a2a322f4 | 502 | int err; |
e126ba97 | 503 | |
b06e7de8 | 504 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 | 505 | if (err) |
a2a322f4 | 506 | return err; |
e126ba97 | 507 | |
938fe83c SM |
508 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
509 | capability); | |
701052c5 | 510 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
511 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
512 | ||
513 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 514 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 515 | 128); |
c7a08ac7 | 516 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 517 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 518 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 519 | |
883371c4 NO |
520 | /* Check log_max_qp from HCA caps to set in current profile */ |
521 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
522 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
523 | profile[prof_sel].log_max_qp, | |
524 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
525 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
526 | } | |
c7a08ac7 | 527 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
528 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
529 | prof->log_max_qp); | |
c7a08ac7 | 530 | |
938fe83c SM |
531 | /* disable cmdif checksum */ |
532 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 533 | |
91828bd8 MD |
534 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
535 | * than 4K. | |
536 | */ | |
537 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
538 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
539 | ||
fe1e1876 CS |
540 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
541 | ||
f32f5bd2 DJ |
542 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
543 | MLX5_SET(cmd_hca_cap, | |
544 | set_hca_cap, | |
545 | cache_line_128byte, | |
c67f100e | 546 | cache_line_size() >= 128 ? 1 : 0); |
f32f5bd2 | 547 | |
dd44572a MS |
548 | if (MLX5_CAP_GEN_MAX(dev, dct)) |
549 | MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); | |
550 | ||
c4b76d8d DJ |
551 | if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) |
552 | MLX5_SET(cmd_hca_cap, | |
553 | set_hca_cap, | |
554 | num_vhca_ports, | |
555 | MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); | |
556 | ||
c6168161 EBE |
557 | if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) |
558 | MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); | |
559 | ||
a2a322f4 | 560 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); |
e126ba97 | 561 | } |
c7a08ac7 | 562 | |
59e9e8e4 MZ |
563 | static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) |
564 | { | |
565 | void *set_hca_cap; | |
566 | int err; | |
567 | ||
568 | if (!MLX5_CAP_GEN(dev, roce)) | |
569 | return 0; | |
570 | ||
571 | err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); | |
572 | if (err) | |
573 | return err; | |
574 | ||
575 | if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || | |
576 | !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) | |
577 | return 0; | |
578 | ||
579 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
580 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_ROCE], | |
581 | MLX5_ST_SZ_BYTES(roce_cap)); | |
582 | MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); | |
583 | ||
584 | err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); | |
e126ba97 EC |
585 | return err; |
586 | } | |
587 | ||
37b6bb77 LR |
588 | static int set_hca_cap(struct mlx5_core_dev *dev) |
589 | { | |
a2a322f4 LR |
590 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
591 | void *set_ctx; | |
37b6bb77 LR |
592 | int err; |
593 | ||
a2a322f4 LR |
594 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
595 | if (!set_ctx) | |
596 | return -ENOMEM; | |
597 | ||
598 | err = handle_hca_cap(dev, set_ctx); | |
37b6bb77 | 599 | if (err) { |
98a8e6fc | 600 | mlx5_core_err(dev, "handle_hca_cap failed\n"); |
37b6bb77 LR |
601 | goto out; |
602 | } | |
603 | ||
a2a322f4 LR |
604 | memset(set_ctx, 0, set_sz); |
605 | err = handle_hca_cap_atomic(dev, set_ctx); | |
37b6bb77 | 606 | if (err) { |
98a8e6fc | 607 | mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); |
37b6bb77 LR |
608 | goto out; |
609 | } | |
610 | ||
a2a322f4 LR |
611 | memset(set_ctx, 0, set_sz); |
612 | err = handle_hca_cap_odp(dev, set_ctx); | |
37b6bb77 | 613 | if (err) { |
98a8e6fc | 614 | mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); |
37b6bb77 LR |
615 | goto out; |
616 | } | |
617 | ||
59e9e8e4 MZ |
618 | memset(set_ctx, 0, set_sz); |
619 | err = handle_hca_cap_roce(dev, set_ctx); | |
620 | if (err) { | |
621 | mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); | |
622 | goto out; | |
623 | } | |
624 | ||
37b6bb77 | 625 | out: |
a2a322f4 | 626 | kfree(set_ctx); |
37b6bb77 LR |
627 | return err; |
628 | } | |
629 | ||
e126ba97 EC |
630 | static int set_hca_ctrl(struct mlx5_core_dev *dev) |
631 | { | |
bd10838a OG |
632 | struct mlx5_reg_host_endianness he_in; |
633 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
634 | int err; |
635 | ||
fc50db98 EC |
636 | if (!mlx5_core_is_pf(dev)) |
637 | return 0; | |
638 | ||
e126ba97 EC |
639 | memset(&he_in, 0, sizeof(he_in)); |
640 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
641 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
642 | &he_out, sizeof(he_out), | |
643 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
644 | return err; | |
645 | } | |
646 | ||
c85023e1 HN |
647 | static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) |
648 | { | |
649 | int ret = 0; | |
650 | ||
651 | /* Disable local_lb by default */ | |
8978cc92 | 652 | if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) |
c85023e1 HN |
653 | ret = mlx5_nic_vport_update_local_lb(dev, false); |
654 | ||
655 | return ret; | |
656 | } | |
657 | ||
0b107106 | 658 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 659 | { |
3ac0e69e | 660 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; |
cd23b14b | 661 | |
0b107106 EC |
662 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
663 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
664 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
665 | dev->caps.embedded_cpu); | |
3ac0e69e | 666 | return mlx5_cmd_exec_in(dev, enable_hca, in); |
cd23b14b EC |
667 | } |
668 | ||
0b107106 | 669 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 670 | { |
3ac0e69e | 671 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; |
cd23b14b | 672 | |
0b107106 EC |
673 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
674 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
675 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
676 | dev->caps.embedded_cpu); | |
3ac0e69e | 677 | return mlx5_cmd_exec_in(dev, disable_hca, in); |
cd23b14b EC |
678 | } |
679 | ||
f62b8bb8 AV |
680 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
681 | { | |
3ac0e69e LR |
682 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; |
683 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; | |
f62b8bb8 | 684 | u32 sup_issi; |
c4f287c4 | 685 | int err; |
f62b8bb8 AV |
686 | |
687 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
3ac0e69e | 688 | err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); |
f62b8bb8 | 689 | if (err) { |
c4f287c4 SM |
690 | u32 syndrome; |
691 | u8 status; | |
692 | ||
693 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
694 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
695 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
696 | err, status, syndrome); | |
697 | return err; | |
f62b8bb8 AV |
698 | } |
699 | ||
f9c14e46 KH |
700 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
701 | dev->issi = 0; | |
702 | return 0; | |
f62b8bb8 AV |
703 | } |
704 | ||
705 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
706 | ||
707 | if (sup_issi & (1 << 1)) { | |
3ac0e69e | 708 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; |
f62b8bb8 AV |
709 | |
710 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
711 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
3ac0e69e | 712 | err = mlx5_cmd_exec_in(dev, set_issi, set_in); |
f62b8bb8 | 713 | if (err) { |
f9c14e46 KH |
714 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
715 | err); | |
f62b8bb8 AV |
716 | return err; |
717 | } | |
718 | ||
719 | dev->issi = 1; | |
720 | ||
721 | return 0; | |
e74a1db0 | 722 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
723 | return 0; |
724 | } | |
725 | ||
9eb78923 | 726 | return -EOPNOTSUPP; |
f62b8bb8 | 727 | } |
f62b8bb8 | 728 | |
11f3b84d SM |
729 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, |
730 | const struct pci_device_id *id) | |
a31208b1 | 731 | { |
868bc06b | 732 | struct mlx5_priv *priv = &dev->priv; |
a31208b1 | 733 | int err = 0; |
e126ba97 | 734 | |
d22663ed | 735 | mutex_init(&dev->pci_status_mutex); |
11f3b84d | 736 | pci_set_drvdata(dev->pdev, dev); |
311c7c71 | 737 | |
aa8106f1 | 738 | dev->bar_addr = pci_resource_start(pdev, 0); |
311c7c71 SM |
739 | priv->numa_node = dev_to_node(&dev->pdev->dev); |
740 | ||
89d44f0a | 741 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 742 | if (err) { |
98a8e6fc | 743 | mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); |
11f3b84d | 744 | return err; |
e126ba97 EC |
745 | } |
746 | ||
747 | err = request_bar(pdev); | |
748 | if (err) { | |
98a8e6fc | 749 | mlx5_core_err(dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
750 | goto err_disable; |
751 | } | |
752 | ||
753 | pci_set_master(pdev); | |
754 | ||
755 | err = set_dma_caps(pdev); | |
756 | if (err) { | |
98a8e6fc | 757 | mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); |
e126ba97 EC |
758 | goto err_clr_master; |
759 | } | |
760 | ||
ce4eee53 MG |
761 | if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && |
762 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && | |
763 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) | |
764 | mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); | |
765 | ||
aa8106f1 | 766 | dev->iseg_base = dev->bar_addr; |
e126ba97 EC |
767 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); |
768 | if (!dev->iseg) { | |
769 | err = -ENOMEM; | |
98a8e6fc | 770 | mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); |
e126ba97 EC |
771 | goto err_clr_master; |
772 | } | |
a31208b1 | 773 | |
b25bbc2f | 774 | mlx5_pci_vsc_init(dev); |
c89da067 | 775 | dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); |
a31208b1 MD |
776 | return 0; |
777 | ||
778 | err_clr_master: | |
779 | pci_clear_master(dev->pdev); | |
780 | release_bar(dev->pdev); | |
781 | err_disable: | |
89d44f0a | 782 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
783 | return err; |
784 | } | |
785 | ||
868bc06b | 786 | static void mlx5_pci_close(struct mlx5_core_dev *dev) |
a31208b1 | 787 | { |
42ea9f1b SD |
788 | /* health work might still be active, and it needs pci bar in |
789 | * order to know the NIC state. Therefore, drain the health WQ | |
790 | * before removing the pci bars | |
791 | */ | |
792 | mlx5_drain_health_wq(dev); | |
a31208b1 MD |
793 | iounmap(dev->iseg); |
794 | pci_clear_master(dev->pdev); | |
795 | release_bar(dev->pdev); | |
89d44f0a | 796 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
797 | } |
798 | ||
868bc06b | 799 | static int mlx5_init_once(struct mlx5_core_dev *dev) |
59211bd3 | 800 | { |
59211bd3 MHY |
801 | int err; |
802 | ||
868bc06b SM |
803 | dev->priv.devcom = mlx5_devcom_register_device(dev); |
804 | if (IS_ERR(dev->priv.devcom)) | |
98a8e6fc HN |
805 | mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", |
806 | dev->priv.devcom); | |
fadd59fc | 807 | |
59211bd3 MHY |
808 | err = mlx5_query_board_id(dev); |
809 | if (err) { | |
98a8e6fc | 810 | mlx5_core_err(dev, "query board id failed\n"); |
fadd59fc | 811 | goto err_devcom; |
59211bd3 MHY |
812 | } |
813 | ||
561aa15a YA |
814 | err = mlx5_irq_table_init(dev); |
815 | if (err) { | |
816 | mlx5_core_err(dev, "failed to initialize irq table\n"); | |
817 | goto err_devcom; | |
818 | } | |
819 | ||
f2f3df55 | 820 | err = mlx5_eq_table_init(dev); |
59211bd3 | 821 | if (err) { |
98a8e6fc | 822 | mlx5_core_err(dev, "failed to initialize eq\n"); |
561aa15a | 823 | goto err_irq_cleanup; |
59211bd3 MHY |
824 | } |
825 | ||
69c1280b SM |
826 | err = mlx5_events_init(dev); |
827 | if (err) { | |
98a8e6fc | 828 | mlx5_core_err(dev, "failed to initialize events\n"); |
69c1280b SM |
829 | goto err_eq_cleanup; |
830 | } | |
831 | ||
9f818c8a | 832 | mlx5_cq_debugfs_init(dev); |
59211bd3 | 833 | |
52ec462e IT |
834 | mlx5_init_reserved_gids(dev); |
835 | ||
7c39afb3 FD |
836 | mlx5_init_clock(dev); |
837 | ||
358aa5ce | 838 | dev->vxlan = mlx5_vxlan_create(dev); |
0ccc171e | 839 | dev->geneve = mlx5_geneve_create(dev); |
358aa5ce | 840 | |
59211bd3 MHY |
841 | err = mlx5_init_rl_table(dev); |
842 | if (err) { | |
98a8e6fc | 843 | mlx5_core_err(dev, "Failed to init rate limiting\n"); |
59211bd3 MHY |
844 | goto err_tables_cleanup; |
845 | } | |
846 | ||
eeb66cdb SM |
847 | err = mlx5_mpfs_init(dev); |
848 | if (err) { | |
98a8e6fc | 849 | mlx5_core_err(dev, "Failed to init l2 table %d\n", err); |
eeb66cdb SM |
850 | goto err_rl_cleanup; |
851 | } | |
852 | ||
86eec50b | 853 | err = mlx5_sriov_init(dev); |
c2d6e31a | 854 | if (err) { |
86eec50b | 855 | mlx5_core_err(dev, "Failed to init sriov %d\n", err); |
eeb66cdb | 856 | goto err_mpfs_cleanup; |
c2d6e31a | 857 | } |
c2d6e31a | 858 | |
86eec50b | 859 | err = mlx5_eswitch_init(dev); |
c2d6e31a | 860 | if (err) { |
86eec50b BW |
861 | mlx5_core_err(dev, "Failed to init eswitch %d\n", err); |
862 | goto err_sriov_cleanup; | |
c2d6e31a MHY |
863 | } |
864 | ||
9410733c IT |
865 | err = mlx5_fpga_init(dev); |
866 | if (err) { | |
98a8e6fc | 867 | mlx5_core_err(dev, "Failed to init fpga device %d\n", err); |
86eec50b | 868 | goto err_eswitch_cleanup; |
9410733c IT |
869 | } |
870 | ||
c9b9dcb4 AL |
871 | dev->dm = mlx5_dm_create(dev); |
872 | if (IS_ERR(dev->dm)) | |
873 | mlx5_core_warn(dev, "Failed to init device memory%d\n", err); | |
874 | ||
24406953 | 875 | dev->tracer = mlx5_fw_tracer_create(dev); |
87175120 | 876 | dev->hv_vhca = mlx5_hv_vhca_create(dev); |
12206b17 | 877 | dev->rsc_dump = mlx5_rsc_dump_create(dev); |
24406953 | 878 | |
59211bd3 MHY |
879 | return 0; |
880 | ||
c2d6e31a | 881 | err_eswitch_cleanup: |
c2d6e31a | 882 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
86eec50b BW |
883 | err_sriov_cleanup: |
884 | mlx5_sriov_cleanup(dev); | |
eeb66cdb | 885 | err_mpfs_cleanup: |
eeb66cdb | 886 | mlx5_mpfs_cleanup(dev); |
c2d6e31a | 887 | err_rl_cleanup: |
c2d6e31a | 888 | mlx5_cleanup_rl_table(dev); |
59211bd3 | 889 | err_tables_cleanup: |
0ccc171e | 890 | mlx5_geneve_destroy(dev->geneve); |
358aa5ce | 891 | mlx5_vxlan_destroy(dev->vxlan); |
02d92f79 | 892 | mlx5_cq_debugfs_cleanup(dev); |
69c1280b | 893 | mlx5_events_cleanup(dev); |
59211bd3 | 894 | err_eq_cleanup: |
f2f3df55 | 895 | mlx5_eq_table_cleanup(dev); |
561aa15a YA |
896 | err_irq_cleanup: |
897 | mlx5_irq_table_cleanup(dev); | |
fadd59fc AH |
898 | err_devcom: |
899 | mlx5_devcom_unregister_device(dev->priv.devcom); | |
59211bd3 | 900 | |
59211bd3 MHY |
901 | return err; |
902 | } | |
903 | ||
904 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
905 | { | |
12206b17 | 906 | mlx5_rsc_dump_destroy(dev); |
87175120 | 907 | mlx5_hv_vhca_destroy(dev->hv_vhca); |
24406953 | 908 | mlx5_fw_tracer_destroy(dev->tracer); |
c9b9dcb4 | 909 | mlx5_dm_cleanup(dev); |
9410733c | 910 | mlx5_fpga_cleanup(dev); |
c2d6e31a | 911 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
86eec50b | 912 | mlx5_sriov_cleanup(dev); |
eeb66cdb | 913 | mlx5_mpfs_cleanup(dev); |
59211bd3 | 914 | mlx5_cleanup_rl_table(dev); |
0ccc171e | 915 | mlx5_geneve_destroy(dev->geneve); |
358aa5ce | 916 | mlx5_vxlan_destroy(dev->vxlan); |
7c39afb3 | 917 | mlx5_cleanup_clock(dev); |
52ec462e | 918 | mlx5_cleanup_reserved_gids(dev); |
02d92f79 | 919 | mlx5_cq_debugfs_cleanup(dev); |
69c1280b | 920 | mlx5_events_cleanup(dev); |
f2f3df55 | 921 | mlx5_eq_table_cleanup(dev); |
561aa15a | 922 | mlx5_irq_table_cleanup(dev); |
fadd59fc | 923 | mlx5_devcom_unregister_device(dev->priv.devcom); |
59211bd3 MHY |
924 | } |
925 | ||
e161105e | 926 | static int mlx5_function_setup(struct mlx5_core_dev *dev, bool boot) |
a31208b1 | 927 | { |
a31208b1 MD |
928 | int err; |
929 | ||
98a8e6fc HN |
930 | mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
931 | fw_rev_min(dev), fw_rev_sub(dev)); | |
e126ba97 | 932 | |
00c6bcb0 TG |
933 | /* Only PFs hold the relevant PCIe information for this query */ |
934 | if (mlx5_core_is_pf(dev)) | |
935 | pcie_print_link_status(dev->pdev); | |
936 | ||
6c780a02 EC |
937 | /* wait for firmware to accept initialization segments configurations |
938 | */ | |
b8a92577 | 939 | err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, FW_INIT_WARN_MESSAGE_INTERVAL); |
6c780a02 | 940 | if (err) { |
98a8e6fc HN |
941 | mlx5_core_err(dev, "Firmware over %d MS in pre-initializing state, aborting\n", |
942 | FW_PRE_INIT_TIMEOUT_MILI); | |
e161105e | 943 | return err; |
6c780a02 EC |
944 | } |
945 | ||
e126ba97 EC |
946 | err = mlx5_cmd_init(dev); |
947 | if (err) { | |
98a8e6fc | 948 | mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); |
e161105e | 949 | return err; |
e126ba97 EC |
950 | } |
951 | ||
b8a92577 | 952 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); |
e3297246 | 953 | if (err) { |
98a8e6fc HN |
954 | mlx5_core_err(dev, "Firmware over %d MS in initializing state, aborting\n", |
955 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 956 | goto err_cmd_cleanup; |
e3297246 EC |
957 | } |
958 | ||
f7936ddd EBE |
959 | mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); |
960 | ||
0b107106 | 961 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b | 962 | if (err) { |
98a8e6fc | 963 | mlx5_core_err(dev, "enable hca failed\n"); |
59211bd3 | 964 | goto err_cmd_cleanup; |
cd23b14b EC |
965 | } |
966 | ||
f62b8bb8 AV |
967 | err = mlx5_core_set_issi(dev); |
968 | if (err) { | |
98a8e6fc | 969 | mlx5_core_err(dev, "failed to set issi\n"); |
f62b8bb8 AV |
970 | goto err_disable_hca; |
971 | } | |
f62b8bb8 | 972 | |
cd23b14b EC |
973 | err = mlx5_satisfy_startup_pages(dev, 1); |
974 | if (err) { | |
98a8e6fc | 975 | mlx5_core_err(dev, "failed to allocate boot pages\n"); |
cd23b14b EC |
976 | goto err_disable_hca; |
977 | } | |
978 | ||
e126ba97 EC |
979 | err = set_hca_ctrl(dev); |
980 | if (err) { | |
98a8e6fc | 981 | mlx5_core_err(dev, "set_hca_ctrl failed\n"); |
cd23b14b | 982 | goto reclaim_boot_pages; |
e126ba97 EC |
983 | } |
984 | ||
37b6bb77 | 985 | err = set_hca_cap(dev); |
f91e6d89 | 986 | if (err) { |
98a8e6fc | 987 | mlx5_core_err(dev, "set_hca_cap failed\n"); |
46861e3e MS |
988 | goto reclaim_boot_pages; |
989 | } | |
990 | ||
cd23b14b | 991 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 992 | if (err) { |
98a8e6fc | 993 | mlx5_core_err(dev, "failed to allocate init pages\n"); |
cd23b14b | 994 | goto reclaim_boot_pages; |
e126ba97 EC |
995 | } |
996 | ||
8737f818 | 997 | err = mlx5_cmd_init_hca(dev, sw_owner_id); |
e126ba97 | 998 | if (err) { |
98a8e6fc | 999 | mlx5_core_err(dev, "init hca failed\n"); |
0cf53c12 | 1000 | goto reclaim_boot_pages; |
e126ba97 EC |
1001 | } |
1002 | ||
012e50e1 HN |
1003 | mlx5_set_driver_version(dev); |
1004 | ||
e126ba97 EC |
1005 | mlx5_start_health_poll(dev); |
1006 | ||
bba1574c DJ |
1007 | err = mlx5_query_hca_caps(dev); |
1008 | if (err) { | |
98a8e6fc | 1009 | mlx5_core_err(dev, "query hca failed\n"); |
e161105e | 1010 | goto stop_health; |
bba1574c DJ |
1011 | } |
1012 | ||
e161105e SM |
1013 | return 0; |
1014 | ||
1015 | stop_health: | |
1016 | mlx5_stop_health_poll(dev, boot); | |
1017 | reclaim_boot_pages: | |
1018 | mlx5_reclaim_startup_pages(dev); | |
1019 | err_disable_hca: | |
1020 | mlx5_core_disable_hca(dev, 0); | |
1021 | err_cmd_cleanup: | |
f7936ddd | 1022 | mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); |
e161105e SM |
1023 | mlx5_cmd_cleanup(dev); |
1024 | ||
1025 | return err; | |
1026 | } | |
1027 | ||
1028 | static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) | |
1029 | { | |
1030 | int err; | |
1031 | ||
1032 | mlx5_stop_health_poll(dev, boot); | |
1033 | err = mlx5_cmd_teardown_hca(dev); | |
1034 | if (err) { | |
98a8e6fc | 1035 | mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); |
e161105e | 1036 | return err; |
e126ba97 | 1037 | } |
e161105e SM |
1038 | mlx5_reclaim_startup_pages(dev); |
1039 | mlx5_core_disable_hca(dev, 0); | |
f7936ddd | 1040 | mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); |
e161105e SM |
1041 | mlx5_cmd_cleanup(dev); |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
a80d1b68 | 1046 | static int mlx5_load(struct mlx5_core_dev *dev) |
e161105e | 1047 | { |
e161105e | 1048 | int err; |
e126ba97 | 1049 | |
01187175 | 1050 | dev->priv.uar = mlx5_get_uars_page(dev); |
72f36be0 | 1051 | if (IS_ERR(dev->priv.uar)) { |
98a8e6fc | 1052 | mlx5_core_err(dev, "Failed allocating uar, aborting\n"); |
72f36be0 | 1053 | err = PTR_ERR(dev->priv.uar); |
a80d1b68 | 1054 | return err; |
e126ba97 EC |
1055 | } |
1056 | ||
69c1280b | 1057 | mlx5_events_start(dev); |
0cf53c12 SM |
1058 | mlx5_pagealloc_start(dev); |
1059 | ||
e1706e62 YA |
1060 | err = mlx5_irq_table_create(dev); |
1061 | if (err) { | |
1062 | mlx5_core_err(dev, "Failed to alloc IRQs\n"); | |
1063 | goto err_irq_table; | |
1064 | } | |
1065 | ||
c8e21b3b | 1066 | err = mlx5_eq_table_create(dev); |
e126ba97 | 1067 | if (err) { |
98a8e6fc | 1068 | mlx5_core_err(dev, "Failed to create EQs\n"); |
c8e21b3b | 1069 | goto err_eq_table; |
e126ba97 EC |
1070 | } |
1071 | ||
24406953 FD |
1072 | err = mlx5_fw_tracer_init(dev->tracer); |
1073 | if (err) { | |
98a8e6fc | 1074 | mlx5_core_err(dev, "Failed to init FW tracer\n"); |
24406953 FD |
1075 | goto err_fw_tracer; |
1076 | } | |
1077 | ||
87175120 EBE |
1078 | mlx5_hv_vhca_init(dev->hv_vhca); |
1079 | ||
12206b17 AL |
1080 | err = mlx5_rsc_dump_init(dev); |
1081 | if (err) { | |
1082 | mlx5_core_err(dev, "Failed to init Resource dump\n"); | |
1083 | goto err_rsc_dump; | |
1084 | } | |
1085 | ||
04e87170 MB |
1086 | err = mlx5_fpga_device_start(dev); |
1087 | if (err) { | |
98a8e6fc | 1088 | mlx5_core_err(dev, "fpga device start failed %d\n", err); |
04e87170 MB |
1089 | goto err_fpga_start; |
1090 | } | |
1091 | ||
1092 | err = mlx5_accel_ipsec_init(dev); | |
1093 | if (err) { | |
98a8e6fc | 1094 | mlx5_core_err(dev, "IPSec device start failed %d\n", err); |
04e87170 MB |
1095 | goto err_ipsec_start; |
1096 | } | |
1097 | ||
1ae17322 IL |
1098 | err = mlx5_accel_tls_init(dev); |
1099 | if (err) { | |
98a8e6fc | 1100 | mlx5_core_err(dev, "TLS device start failed %d\n", err); |
1ae17322 IL |
1101 | goto err_tls_start; |
1102 | } | |
1103 | ||
86d722ad | 1104 | err = mlx5_init_fs(dev); |
59211bd3 | 1105 | if (err) { |
98a8e6fc | 1106 | mlx5_core_err(dev, "Failed to init flow steering\n"); |
c85023e1 | 1107 | goto err_fs; |
59211bd3 | 1108 | } |
e126ba97 | 1109 | |
c85023e1 | 1110 | err = mlx5_core_set_hca_defaults(dev); |
86d722ad | 1111 | if (err) { |
98a8e6fc | 1112 | mlx5_core_err(dev, "Failed to set hca defaults\n"); |
87883929 | 1113 | goto err_sriov; |
86d722ad | 1114 | } |
1466cc5b | 1115 | |
c2d6e31a | 1116 | err = mlx5_sriov_attach(dev); |
fc50db98 | 1117 | if (err) { |
98a8e6fc | 1118 | mlx5_core_err(dev, "sriov init failed %d\n", err); |
fc50db98 EC |
1119 | goto err_sriov; |
1120 | } | |
1121 | ||
22e939a9 BW |
1122 | err = mlx5_ec_init(dev); |
1123 | if (err) { | |
98a8e6fc | 1124 | mlx5_core_err(dev, "Failed to init embedded CPU\n"); |
22e939a9 BW |
1125 | goto err_ec; |
1126 | } | |
1127 | ||
e126ba97 EC |
1128 | return 0; |
1129 | ||
22e939a9 | 1130 | err_ec: |
c2d6e31a | 1131 | mlx5_sriov_detach(dev); |
59211bd3 | 1132 | err_sriov: |
86d722ad MG |
1133 | mlx5_cleanup_fs(dev); |
1134 | err_fs: | |
1ae17322 | 1135 | mlx5_accel_tls_cleanup(dev); |
1ae17322 | 1136 | err_tls_start: |
04e87170 | 1137 | mlx5_accel_ipsec_cleanup(dev); |
04e87170 MB |
1138 | err_ipsec_start: |
1139 | mlx5_fpga_device_stop(dev); | |
04e87170 | 1140 | err_fpga_start: |
12206b17 AL |
1141 | mlx5_rsc_dump_cleanup(dev); |
1142 | err_rsc_dump: | |
87175120 | 1143 | mlx5_hv_vhca_cleanup(dev->hv_vhca); |
24406953 | 1144 | mlx5_fw_tracer_cleanup(dev->tracer); |
24406953 | 1145 | err_fw_tracer: |
c8e21b3b | 1146 | mlx5_eq_table_destroy(dev); |
c8e21b3b | 1147 | err_eq_table: |
e1706e62 YA |
1148 | mlx5_irq_table_destroy(dev); |
1149 | err_irq_table: | |
0cf53c12 | 1150 | mlx5_pagealloc_stop(dev); |
69c1280b | 1151 | mlx5_events_stop(dev); |
868bc06b | 1152 | mlx5_put_uars_page(dev, dev->priv.uar); |
a80d1b68 SM |
1153 | return err; |
1154 | } | |
e126ba97 | 1155 | |
a80d1b68 SM |
1156 | static void mlx5_unload(struct mlx5_core_dev *dev) |
1157 | { | |
1158 | mlx5_ec_cleanup(dev); | |
1159 | mlx5_sriov_detach(dev); | |
1160 | mlx5_cleanup_fs(dev); | |
1161 | mlx5_accel_ipsec_cleanup(dev); | |
1162 | mlx5_accel_tls_cleanup(dev); | |
1163 | mlx5_fpga_device_stop(dev); | |
12206b17 | 1164 | mlx5_rsc_dump_cleanup(dev); |
87175120 | 1165 | mlx5_hv_vhca_cleanup(dev->hv_vhca); |
a80d1b68 SM |
1166 | mlx5_fw_tracer_cleanup(dev->tracer); |
1167 | mlx5_eq_table_destroy(dev); | |
e1706e62 | 1168 | mlx5_irq_table_destroy(dev); |
a80d1b68 SM |
1169 | mlx5_pagealloc_stop(dev); |
1170 | mlx5_events_stop(dev); | |
1171 | mlx5_put_uars_page(dev, dev->priv.uar); | |
1172 | } | |
59211bd3 | 1173 | |
4383cfcc | 1174 | int mlx5_load_one(struct mlx5_core_dev *dev, bool boot) |
a80d1b68 | 1175 | { |
a80d1b68 SM |
1176 | int err = 0; |
1177 | ||
a80d1b68 SM |
1178 | mutex_lock(&dev->intf_state_mutex); |
1179 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { | |
1180 | mlx5_core_warn(dev, "interface is up, NOP\n"); | |
1181 | goto out; | |
1bde6e30 | 1182 | } |
a80d1b68 SM |
1183 | /* remove any previous indication of internal error */ |
1184 | dev->state = MLX5_DEVICE_STATE_UP; | |
e126ba97 | 1185 | |
a80d1b68 SM |
1186 | err = mlx5_function_setup(dev, boot); |
1187 | if (err) | |
4f7400d5 | 1188 | goto err_function; |
e126ba97 | 1189 | |
a80d1b68 SM |
1190 | if (boot) { |
1191 | err = mlx5_init_once(dev); | |
1192 | if (err) { | |
98a8e6fc | 1193 | mlx5_core_err(dev, "sw objs init failed\n"); |
a80d1b68 SM |
1194 | goto function_teardown; |
1195 | } | |
1196 | } | |
cd23b14b | 1197 | |
a80d1b68 SM |
1198 | err = mlx5_load(dev); |
1199 | if (err) | |
1200 | goto err_load; | |
e126ba97 | 1201 | |
a6f3b623 MG |
1202 | if (boot) { |
1203 | err = mlx5_devlink_register(priv_to_devlink(dev), dev->device); | |
1204 | if (err) | |
1205 | goto err_devlink_reg; | |
1206 | } | |
1207 | ||
ecd01db8 | 1208 | if (mlx5_device_registered(dev)) |
a80d1b68 | 1209 | mlx5_attach_device(dev); |
ecd01db8 PP |
1210 | else |
1211 | mlx5_register_device(dev); | |
a80d1b68 SM |
1212 | |
1213 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
e126ba97 | 1214 | |
4162f58b PP |
1215 | mutex_unlock(&dev->intf_state_mutex); |
1216 | return 0; | |
a80d1b68 | 1217 | |
a6f3b623 | 1218 | err_devlink_reg: |
a80d1b68 SM |
1219 | mlx5_unload(dev); |
1220 | err_load: | |
59211bd3 MHY |
1221 | if (boot) |
1222 | mlx5_cleanup_once(dev); | |
e161105e SM |
1223 | function_teardown: |
1224 | mlx5_function_teardown(dev, boot); | |
4f7400d5 | 1225 | err_function: |
89d44f0a | 1226 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; |
4162f58b | 1227 | out: |
89d44f0a | 1228 | mutex_unlock(&dev->intf_state_mutex); |
e126ba97 EC |
1229 | return err; |
1230 | } | |
e126ba97 | 1231 | |
f999b706 | 1232 | void mlx5_unload_one(struct mlx5_core_dev *dev, bool cleanup) |
e126ba97 | 1233 | { |
41798df9 | 1234 | if (cleanup) |
0000a5f2 | 1235 | mlx5_unregister_device(dev); |
689a248d | 1236 | |
89d44f0a | 1237 | mutex_lock(&dev->intf_state_mutex); |
b3cb5388 | 1238 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
98a8e6fc HN |
1239 | mlx5_core_warn(dev, "%s: interface is down, NOP\n", |
1240 | __func__); | |
59211bd3 MHY |
1241 | if (cleanup) |
1242 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1243 | goto out; |
1244 | } | |
6b6adee3 | 1245 | |
9ade8c7c | 1246 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
9ade8c7c | 1247 | |
737a234b MHY |
1248 | if (mlx5_device_registered(dev)) |
1249 | mlx5_detach_device(dev); | |
1250 | ||
a80d1b68 SM |
1251 | mlx5_unload(dev); |
1252 | ||
59211bd3 MHY |
1253 | if (cleanup) |
1254 | mlx5_cleanup_once(dev); | |
9603b61d | 1255 | |
e161105e | 1256 | mlx5_function_teardown(dev, cleanup); |
ac6ea6e8 | 1257 | out: |
89d44f0a | 1258 | mutex_unlock(&dev->intf_state_mutex); |
9603b61d | 1259 | } |
64613d94 | 1260 | |
27b942fb | 1261 | static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) |
9603b61d | 1262 | { |
11f3b84d | 1263 | struct mlx5_priv *priv = &dev->priv; |
9603b61d JM |
1264 | int err; |
1265 | ||
11f3b84d | 1266 | dev->profile = &profile[profile_idx]; |
9603b61d | 1267 | |
364d1798 EC |
1268 | INIT_LIST_HEAD(&priv->ctx_list); |
1269 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a | 1270 | mutex_init(&dev->intf_state_mutex); |
d9aaed83 | 1271 | |
01187175 EC |
1272 | mutex_init(&priv->bfregs.reg_head.lock); |
1273 | mutex_init(&priv->bfregs.wc_head.lock); | |
1274 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1275 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1276 | ||
11f3b84d SM |
1277 | mutex_init(&priv->alloc_mutex); |
1278 | mutex_init(&priv->pgdir_mutex); | |
1279 | INIT_LIST_HEAD(&priv->pgdir_list); | |
11f3b84d | 1280 | |
27b942fb PP |
1281 | priv->dbg_root = debugfs_create_dir(dev_name(dev->device), |
1282 | mlx5_debugfs_root); | |
11f3b84d | 1283 | if (!priv->dbg_root) { |
27b942fb | 1284 | dev_err(dev->device, "mlx5_core: error, Cannot create debugfs dir, aborting\n"); |
810cbb25 | 1285 | goto err_dbg_root; |
9603b61d JM |
1286 | } |
1287 | ||
ac6ea6e8 | 1288 | err = mlx5_health_init(dev); |
52c368dc SM |
1289 | if (err) |
1290 | goto err_health_init; | |
ac6ea6e8 | 1291 | |
0cf53c12 SM |
1292 | err = mlx5_pagealloc_init(dev); |
1293 | if (err) | |
1294 | goto err_pagealloc_init; | |
59211bd3 | 1295 | |
11f3b84d | 1296 | return 0; |
52c368dc SM |
1297 | |
1298 | err_pagealloc_init: | |
1299 | mlx5_health_cleanup(dev); | |
1300 | err_health_init: | |
1301 | debugfs_remove(dev->priv.dbg_root); | |
810cbb25 PP |
1302 | err_dbg_root: |
1303 | mutex_destroy(&priv->pgdir_mutex); | |
1304 | mutex_destroy(&priv->alloc_mutex); | |
1305 | mutex_destroy(&priv->bfregs.wc_head.lock); | |
1306 | mutex_destroy(&priv->bfregs.reg_head.lock); | |
1307 | mutex_destroy(&dev->intf_state_mutex); | |
52c368dc | 1308 | return err; |
11f3b84d SM |
1309 | } |
1310 | ||
1311 | static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) | |
1312 | { | |
810cbb25 PP |
1313 | struct mlx5_priv *priv = &dev->priv; |
1314 | ||
52c368dc SM |
1315 | mlx5_pagealloc_cleanup(dev); |
1316 | mlx5_health_cleanup(dev); | |
11f3b84d | 1317 | debugfs_remove_recursive(dev->priv.dbg_root); |
810cbb25 PP |
1318 | mutex_destroy(&priv->pgdir_mutex); |
1319 | mutex_destroy(&priv->alloc_mutex); | |
1320 | mutex_destroy(&priv->bfregs.wc_head.lock); | |
1321 | mutex_destroy(&priv->bfregs.reg_head.lock); | |
1322 | mutex_destroy(&dev->intf_state_mutex); | |
11f3b84d SM |
1323 | } |
1324 | ||
59211bd3 | 1325 | #define MLX5_IB_MOD "mlx5_ib" |
11f3b84d | 1326 | static int init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
9603b61d JM |
1327 | { |
1328 | struct mlx5_core_dev *dev; | |
feae9087 | 1329 | struct devlink *devlink; |
9603b61d JM |
1330 | int err; |
1331 | ||
1f28d776 | 1332 | devlink = mlx5_devlink_alloc(); |
feae9087 | 1333 | if (!devlink) { |
1f28d776 | 1334 | dev_err(&pdev->dev, "devlink alloc failed\n"); |
9603b61d JM |
1335 | return -ENOMEM; |
1336 | } | |
feae9087 OG |
1337 | |
1338 | dev = devlink_priv(devlink); | |
27b942fb PP |
1339 | dev->device = &pdev->dev; |
1340 | dev->pdev = pdev; | |
9603b61d | 1341 | |
386e75af HN |
1342 | dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? |
1343 | MLX5_COREDEV_VF : MLX5_COREDEV_PF; | |
1344 | ||
27b942fb | 1345 | err = mlx5_mdev_init(dev, prof_sel); |
11f3b84d SM |
1346 | if (err) |
1347 | goto mdev_init_err; | |
01187175 | 1348 | |
11f3b84d | 1349 | err = mlx5_pci_init(dev, pdev, id); |
9603b61d | 1350 | if (err) { |
98a8e6fc HN |
1351 | mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", |
1352 | err); | |
11f3b84d | 1353 | goto pci_init_err; |
9603b61d JM |
1354 | } |
1355 | ||
868bc06b | 1356 | err = mlx5_load_one(dev, true); |
9603b61d | 1357 | if (err) { |
98a8e6fc HN |
1358 | mlx5_core_err(dev, "mlx5_load_one failed with error code %d\n", |
1359 | err); | |
0cf53c12 | 1360 | goto err_load_one; |
9603b61d | 1361 | } |
59211bd3 | 1362 | |
f82eed45 | 1363 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1364 | |
8b9d8baa AV |
1365 | err = mlx5_crdump_enable(dev); |
1366 | if (err) | |
1367 | dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); | |
1368 | ||
5d47f6c8 | 1369 | pci_save_state(pdev); |
9603b61d JM |
1370 | return 0; |
1371 | ||
0cf53c12 | 1372 | err_load_one: |
868bc06b | 1373 | mlx5_pci_close(dev); |
11f3b84d SM |
1374 | pci_init_err: |
1375 | mlx5_mdev_uninit(dev); | |
1376 | mdev_init_err: | |
1f28d776 | 1377 | mlx5_devlink_free(devlink); |
a31208b1 | 1378 | |
9603b61d JM |
1379 | return err; |
1380 | } | |
a31208b1 | 1381 | |
9603b61d JM |
1382 | static void remove_one(struct pci_dev *pdev) |
1383 | { | |
1384 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1385 | struct devlink *devlink = priv_to_devlink(dev); |
9603b61d | 1386 | |
8b9d8baa | 1387 | mlx5_crdump_disable(dev); |
1f28d776 | 1388 | mlx5_devlink_unregister(devlink); |
737a234b | 1389 | |
41798df9 | 1390 | mlx5_drain_health_wq(dev); |
f999b706 | 1391 | mlx5_unload_one(dev, true); |
868bc06b | 1392 | mlx5_pci_close(dev); |
11f3b84d | 1393 | mlx5_mdev_uninit(dev); |
1f28d776 | 1394 | mlx5_devlink_free(devlink); |
9603b61d JM |
1395 | } |
1396 | ||
89d44f0a MD |
1397 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1398 | pci_channel_state_t state) | |
1399 | { | |
1400 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a | 1401 | |
98a8e6fc | 1402 | mlx5_core_info(dev, "%s was called\n", __func__); |
04c0c1ab | 1403 | |
8812c24d | 1404 | mlx5_enter_error_state(dev, false); |
3e5b72ac | 1405 | mlx5_error_sw_reset(dev); |
868bc06b | 1406 | mlx5_unload_one(dev, false); |
b3bd076f MS |
1407 | mlx5_drain_health_wq(dev); |
1408 | mlx5_pci_disable_device(dev); | |
05ac2c0b | 1409 | |
89d44f0a MD |
1410 | return state == pci_channel_io_perm_failure ? |
1411 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1412 | } | |
1413 | ||
d57847dc DJ |
1414 | /* wait for the device to show vital signs by waiting |
1415 | * for the health counter to start counting. | |
89d44f0a | 1416 | */ |
d57847dc | 1417 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1418 | { |
1419 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1420 | struct mlx5_core_health *health = &dev->priv.health; | |
1421 | const int niter = 100; | |
d57847dc | 1422 | u32 last_count = 0; |
89d44f0a | 1423 | u32 count; |
89d44f0a MD |
1424 | int i; |
1425 | ||
89d44f0a MD |
1426 | for (i = 0; i < niter; i++) { |
1427 | count = ioread32be(health->health_counter); | |
1428 | if (count && count != 0xffffffff) { | |
d57847dc | 1429 | if (last_count && last_count != count) { |
98a8e6fc HN |
1430 | mlx5_core_info(dev, |
1431 | "wait vital counter value 0x%x after %d iterations\n", | |
1432 | count, i); | |
d57847dc DJ |
1433 | return 0; |
1434 | } | |
1435 | last_count = count; | |
89d44f0a MD |
1436 | } |
1437 | msleep(50); | |
1438 | } | |
1439 | ||
d57847dc | 1440 | return -ETIMEDOUT; |
89d44f0a MD |
1441 | } |
1442 | ||
1061c90f | 1443 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1444 | { |
1445 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1446 | int err; |
1447 | ||
98a8e6fc | 1448 | mlx5_core_info(dev, "%s was called\n", __func__); |
89d44f0a | 1449 | |
1061c90f | 1450 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1451 | if (err) { |
98a8e6fc HN |
1452 | mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", |
1453 | __func__, err); | |
1061c90f MHY |
1454 | return PCI_ERS_RESULT_DISCONNECT; |
1455 | } | |
1456 | ||
1457 | pci_set_master(pdev); | |
1458 | pci_restore_state(pdev); | |
5d47f6c8 | 1459 | pci_save_state(pdev); |
1061c90f MHY |
1460 | |
1461 | if (wait_vital(pdev)) { | |
98a8e6fc | 1462 | mlx5_core_err(dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1463 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1464 | } |
89d44f0a | 1465 | |
1061c90f MHY |
1466 | return PCI_ERS_RESULT_RECOVERED; |
1467 | } | |
1468 | ||
1061c90f MHY |
1469 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1470 | { | |
1471 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1061c90f MHY |
1472 | int err; |
1473 | ||
98a8e6fc | 1474 | mlx5_core_info(dev, "%s was called\n", __func__); |
1061c90f | 1475 | |
868bc06b | 1476 | err = mlx5_load_one(dev, false); |
89d44f0a | 1477 | if (err) |
98a8e6fc HN |
1478 | mlx5_core_err(dev, "%s: mlx5_load_one failed with error code: %d\n", |
1479 | __func__, err); | |
89d44f0a | 1480 | else |
98a8e6fc | 1481 | mlx5_core_info(dev, "%s: device recovered\n", __func__); |
89d44f0a MD |
1482 | } |
1483 | ||
1484 | static const struct pci_error_handlers mlx5_err_handler = { | |
1485 | .error_detected = mlx5_pci_err_detected, | |
1486 | .slot_reset = mlx5_pci_slot_reset, | |
1487 | .resume = mlx5_pci_resume | |
1488 | }; | |
1489 | ||
8812c24d MD |
1490 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1491 | { | |
fcd29ad1 FD |
1492 | bool fast_teardown = false, force_teardown = false; |
1493 | int ret = 1; | |
1494 | ||
1495 | fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); | |
1496 | force_teardown = MLX5_CAP_GEN(dev, force_teardown); | |
1497 | ||
1498 | mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); | |
1499 | mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); | |
8812c24d | 1500 | |
fcd29ad1 | 1501 | if (!fast_teardown && !force_teardown) |
8812c24d | 1502 | return -EOPNOTSUPP; |
8812c24d MD |
1503 | |
1504 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1505 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1506 | return -EAGAIN; | |
1507 | } | |
1508 | ||
d2aa060d HN |
1509 | /* Panic tear down fw command will stop the PCI bus communication |
1510 | * with the HCA, so the health polll is no longer needed. | |
1511 | */ | |
1512 | mlx5_drain_health_wq(dev); | |
76d5581c | 1513 | mlx5_stop_health_poll(dev, false); |
d2aa060d | 1514 | |
fcd29ad1 FD |
1515 | ret = mlx5_cmd_fast_teardown_hca(dev); |
1516 | if (!ret) | |
1517 | goto succeed; | |
1518 | ||
8812c24d | 1519 | ret = mlx5_cmd_force_teardown_hca(dev); |
fcd29ad1 FD |
1520 | if (!ret) |
1521 | goto succeed; | |
1522 | ||
1523 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1524 | mlx5_start_health_poll(dev); | |
1525 | return ret; | |
8812c24d | 1526 | |
fcd29ad1 | 1527 | succeed: |
8812c24d MD |
1528 | mlx5_enter_error_state(dev, true); |
1529 | ||
1ef903bf DJ |
1530 | /* Some platforms requiring freeing the IRQ's in the shutdown |
1531 | * flow. If they aren't freed they can't be allocated after | |
1532 | * kexec. There is no need to cleanup the mlx5_core software | |
1533 | * contexts. | |
1534 | */ | |
1ef903bf DJ |
1535 | mlx5_core_eq_free_irqs(dev); |
1536 | ||
8812c24d MD |
1537 | return 0; |
1538 | } | |
1539 | ||
5fc7197d MD |
1540 | static void shutdown(struct pci_dev *pdev) |
1541 | { | |
1542 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
8812c24d | 1543 | int err; |
5fc7197d | 1544 | |
98a8e6fc | 1545 | mlx5_core_info(dev, "Shutdown was called\n"); |
8812c24d MD |
1546 | err = mlx5_try_fast_unload(dev); |
1547 | if (err) | |
868bc06b | 1548 | mlx5_unload_one(dev, false); |
5fc7197d MD |
1549 | mlx5_pci_disable_device(dev); |
1550 | } | |
1551 | ||
8fc3e29b MB |
1552 | static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) |
1553 | { | |
1554 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1555 | ||
1556 | mlx5_unload_one(dev, false); | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | static int mlx5_resume(struct pci_dev *pdev) | |
1562 | { | |
1563 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1564 | ||
1565 | return mlx5_load_one(dev, false); | |
1566 | } | |
1567 | ||
9603b61d | 1568 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1569 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1570 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1571 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1572 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1573 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1574 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1575 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1576 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1577 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1578 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1579 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1580 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
85327a9c EBE |
1581 | { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ |
1582 | { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ | |
b7eca940 | 1583 | { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ |
505a7f54 | 1584 | { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ |
2e9d3e83 NO |
1585 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1586 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
d19a79ee | 1587 | { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ |
9603b61d JM |
1588 | { 0, } |
1589 | }; | |
1590 | ||
1591 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1592 | ||
04c0c1ab MHY |
1593 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1594 | { | |
b3bd076f MS |
1595 | mlx5_error_sw_reset(dev); |
1596 | mlx5_unload_one(dev, false); | |
04c0c1ab MHY |
1597 | } |
1598 | ||
1599 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1600 | { | |
1601 | mlx5_pci_disable_device(dev); | |
1602 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1603 | mlx5_pci_resume(dev->pdev); | |
1604 | } | |
1605 | ||
9603b61d JM |
1606 | static struct pci_driver mlx5_core_driver = { |
1607 | .name = DRIVER_NAME, | |
1608 | .id_table = mlx5_core_pci_table, | |
1609 | .probe = init_one, | |
89d44f0a | 1610 | .remove = remove_one, |
8fc3e29b MB |
1611 | .suspend = mlx5_suspend, |
1612 | .resume = mlx5_resume, | |
5fc7197d | 1613 | .shutdown = shutdown, |
fc50db98 EC |
1614 | .err_handler = &mlx5_err_handler, |
1615 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1616 | }; |
e126ba97 | 1617 | |
f663ad98 KH |
1618 | static void mlx5_core_verify_params(void) |
1619 | { | |
1620 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1621 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1622 | prof_sel, | |
1623 | ARRAY_SIZE(profile) - 1, | |
1624 | MLX5_DEFAULT_PROF); | |
1625 | prof_sel = MLX5_DEFAULT_PROF; | |
1626 | } | |
1627 | } | |
1628 | ||
e126ba97 EC |
1629 | static int __init init(void) |
1630 | { | |
1631 | int err; | |
1632 | ||
8737f818 DJ |
1633 | get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); |
1634 | ||
f663ad98 | 1635 | mlx5_core_verify_params(); |
c778dd31 | 1636 | mlx5_accel_ipsec_build_fs_cmds(); |
e126ba97 | 1637 | mlx5_register_debugfs(); |
e126ba97 | 1638 | |
9603b61d JM |
1639 | err = pci_register_driver(&mlx5_core_driver); |
1640 | if (err) | |
ac6ea6e8 | 1641 | goto err_debug; |
9603b61d | 1642 | |
f62b8bb8 AV |
1643 | #ifdef CONFIG_MLX5_CORE_EN |
1644 | mlx5e_init(); | |
1645 | #endif | |
1646 | ||
e126ba97 EC |
1647 | return 0; |
1648 | ||
e126ba97 EC |
1649 | err_debug: |
1650 | mlx5_unregister_debugfs(); | |
1651 | return err; | |
1652 | } | |
1653 | ||
1654 | static void __exit cleanup(void) | |
1655 | { | |
f62b8bb8 AV |
1656 | #ifdef CONFIG_MLX5_CORE_EN |
1657 | mlx5e_cleanup(); | |
1658 | #endif | |
9603b61d | 1659 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1660 | mlx5_unregister_debugfs(); |
1661 | } | |
1662 | ||
1663 | module_init(init); | |
1664 | module_exit(cleanup); |