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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
46 | #include <linux/mlx5/srq.h> | |
47 | #include <linux/debugfs.h> | |
f66f049f | 48 | #include <linux/kmod.h> |
b775516b | 49 | #include <linux/mlx5/mlx5_ifc.h> |
c85023e1 | 50 | #include <linux/mlx5/vport.h> |
5a7b27eb MG |
51 | #ifdef CONFIG_RFS_ACCEL |
52 | #include <linux/cpu_rmap.h> | |
53 | #endif | |
feae9087 | 54 | #include <net/devlink.h> |
e126ba97 | 55 | #include "mlx5_core.h" |
86d722ad | 56 | #include "fs_core.h" |
eeb66cdb | 57 | #include "lib/mpfs.h" |
073bb189 | 58 | #include "eswitch.h" |
52ec462e | 59 | #include "lib/mlx5.h" |
e29341fb | 60 | #include "fpga/core.h" |
bebb23e6 | 61 | #include "accel/ipsec.h" |
7c39afb3 | 62 | #include "lib/clock.h" |
e126ba97 | 63 | |
e126ba97 | 64 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
4ae6c18c | 65 | MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver"); |
e126ba97 EC |
66 | MODULE_LICENSE("Dual BSD/GPL"); |
67 | MODULE_VERSION(DRIVER_VERSION); | |
68 | ||
f663ad98 KH |
69 | unsigned int mlx5_core_debug_mask; |
70 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
71 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
72 | ||
9603b61d | 73 | #define MLX5_DEFAULT_PROF 2 |
f663ad98 KH |
74 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
75 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
76 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
77 | ||
f91e6d89 EBE |
78 | enum { |
79 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
80 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
81 | }; | |
82 | ||
9603b61d JM |
83 | static struct mlx5_profile profile[] = { |
84 | [0] = { | |
85 | .mask = 0, | |
86 | }, | |
87 | [1] = { | |
88 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
89 | .log_max_qp = 12, | |
90 | }, | |
91 | [2] = { | |
92 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
93 | MLX5_PROF_MASK_MR_CACHE, | |
5f40b4ed | 94 | .log_max_qp = 18, |
9603b61d JM |
95 | .mr_cache[0] = { |
96 | .size = 500, | |
97 | .limit = 250 | |
98 | }, | |
99 | .mr_cache[1] = { | |
100 | .size = 500, | |
101 | .limit = 250 | |
102 | }, | |
103 | .mr_cache[2] = { | |
104 | .size = 500, | |
105 | .limit = 250 | |
106 | }, | |
107 | .mr_cache[3] = { | |
108 | .size = 500, | |
109 | .limit = 250 | |
110 | }, | |
111 | .mr_cache[4] = { | |
112 | .size = 500, | |
113 | .limit = 250 | |
114 | }, | |
115 | .mr_cache[5] = { | |
116 | .size = 500, | |
117 | .limit = 250 | |
118 | }, | |
119 | .mr_cache[6] = { | |
120 | .size = 500, | |
121 | .limit = 250 | |
122 | }, | |
123 | .mr_cache[7] = { | |
124 | .size = 500, | |
125 | .limit = 250 | |
126 | }, | |
127 | .mr_cache[8] = { | |
128 | .size = 500, | |
129 | .limit = 250 | |
130 | }, | |
131 | .mr_cache[9] = { | |
132 | .size = 500, | |
133 | .limit = 250 | |
134 | }, | |
135 | .mr_cache[10] = { | |
136 | .size = 500, | |
137 | .limit = 250 | |
138 | }, | |
139 | .mr_cache[11] = { | |
140 | .size = 500, | |
141 | .limit = 250 | |
142 | }, | |
143 | .mr_cache[12] = { | |
144 | .size = 64, | |
145 | .limit = 32 | |
146 | }, | |
147 | .mr_cache[13] = { | |
148 | .size = 32, | |
149 | .limit = 16 | |
150 | }, | |
151 | .mr_cache[14] = { | |
152 | .size = 16, | |
153 | .limit = 8 | |
154 | }, | |
155 | .mr_cache[15] = { | |
156 | .size = 8, | |
157 | .limit = 4 | |
158 | }, | |
7d0cc6ed AK |
159 | .mr_cache[16] = { |
160 | .size = 8, | |
161 | .limit = 4 | |
162 | }, | |
163 | .mr_cache[17] = { | |
164 | .size = 8, | |
165 | .limit = 4 | |
166 | }, | |
167 | .mr_cache[18] = { | |
168 | .size = 8, | |
169 | .limit = 4 | |
170 | }, | |
171 | .mr_cache[19] = { | |
172 | .size = 4, | |
173 | .limit = 2 | |
174 | }, | |
175 | .mr_cache[20] = { | |
176 | .size = 4, | |
177 | .limit = 2 | |
178 | }, | |
9603b61d JM |
179 | }, |
180 | }; | |
e126ba97 | 181 | |
6c780a02 EC |
182 | #define FW_INIT_TIMEOUT_MILI 2000 |
183 | #define FW_INIT_WAIT_MS 2 | |
184 | #define FW_PRE_INIT_TIMEOUT_MILI 10000 | |
e3297246 EC |
185 | |
186 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili) | |
187 | { | |
188 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); | |
189 | int err = 0; | |
190 | ||
191 | while (fw_initializing(dev)) { | |
192 | if (time_after(jiffies, end)) { | |
193 | err = -EBUSY; | |
194 | break; | |
195 | } | |
196 | msleep(FW_INIT_WAIT_MS); | |
197 | } | |
198 | ||
199 | return err; | |
200 | } | |
201 | ||
012e50e1 HN |
202 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
203 | { | |
204 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
205 | driver_version); | |
206 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0}; | |
207 | u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0}; | |
208 | int remaining_size = driver_ver_sz; | |
209 | char *string; | |
210 | ||
211 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
212 | return; | |
213 | ||
214 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
215 | ||
216 | strncpy(string, "Linux", remaining_size); | |
217 | ||
218 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
219 | strncat(string, ",", remaining_size); | |
220 | ||
221 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
222 | strncat(string, DRIVER_NAME, remaining_size); | |
223 | ||
224 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
225 | strncat(string, ",", remaining_size); | |
226 | ||
227 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
228 | strncat(string, DRIVER_VERSION, remaining_size); | |
229 | ||
230 | /*Send the command*/ | |
231 | MLX5_SET(set_driver_version_in, in, opcode, | |
232 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
233 | ||
234 | mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); | |
235 | } | |
236 | ||
e126ba97 EC |
237 | static int set_dma_caps(struct pci_dev *pdev) |
238 | { | |
239 | int err; | |
240 | ||
241 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); | |
242 | if (err) { | |
1a91de28 | 243 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
e126ba97 EC |
244 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
245 | if (err) { | |
1a91de28 | 246 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
247 | return err; |
248 | } | |
249 | } | |
250 | ||
251 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); | |
252 | if (err) { | |
253 | dev_warn(&pdev->dev, | |
1a91de28 | 254 | "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
e126ba97 EC |
255 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
256 | if (err) { | |
257 | dev_err(&pdev->dev, | |
1a91de28 | 258 | "Can't set consistent PCI DMA mask, aborting\n"); |
e126ba97 EC |
259 | return err; |
260 | } | |
261 | } | |
262 | ||
263 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); | |
264 | return err; | |
265 | } | |
266 | ||
89d44f0a MD |
267 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
268 | { | |
269 | struct pci_dev *pdev = dev->pdev; | |
270 | int err = 0; | |
271 | ||
272 | mutex_lock(&dev->pci_status_mutex); | |
273 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
274 | err = pci_enable_device(pdev); | |
275 | if (!err) | |
276 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
277 | } | |
278 | mutex_unlock(&dev->pci_status_mutex); | |
279 | ||
280 | return err; | |
281 | } | |
282 | ||
283 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
284 | { | |
285 | struct pci_dev *pdev = dev->pdev; | |
286 | ||
287 | mutex_lock(&dev->pci_status_mutex); | |
288 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
289 | pci_disable_device(pdev); | |
290 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
291 | } | |
292 | mutex_unlock(&dev->pci_status_mutex); | |
293 | } | |
294 | ||
e126ba97 EC |
295 | static int request_bar(struct pci_dev *pdev) |
296 | { | |
297 | int err = 0; | |
298 | ||
299 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 300 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
301 | return -ENODEV; |
302 | } | |
303 | ||
304 | err = pci_request_regions(pdev, DRIVER_NAME); | |
305 | if (err) | |
306 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
307 | ||
308 | return err; | |
309 | } | |
310 | ||
311 | static void release_bar(struct pci_dev *pdev) | |
312 | { | |
313 | pci_release_regions(pdev); | |
314 | } | |
315 | ||
78249c42 | 316 | static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev) |
e126ba97 | 317 | { |
db058a18 SM |
318 | struct mlx5_priv *priv = &dev->priv; |
319 | struct mlx5_eq_table *table = &priv->eq_table; | |
938fe83c | 320 | int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); |
e126ba97 | 321 | int nvec; |
b6908c29 | 322 | int err; |
e126ba97 | 323 | |
938fe83c SM |
324 | nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() + |
325 | MLX5_EQ_VEC_COMP_BASE; | |
e126ba97 EC |
326 | nvec = min_t(int, nvec, num_eqs); |
327 | if (nvec <= MLX5_EQ_VEC_COMP_BASE) | |
328 | return -ENOMEM; | |
329 | ||
db058a18 | 330 | priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL); |
78249c42 | 331 | if (!priv->irq_info) |
b6908c29 | 332 | return -ENOMEM; |
e126ba97 | 333 | |
231243c8 | 334 | nvec = pci_alloc_irq_vectors(dev->pdev, |
78249c42 | 335 | MLX5_EQ_VEC_COMP_BASE + 1, nvec, |
231243c8 | 336 | PCI_IRQ_MSIX); |
b6908c29 AH |
337 | if (nvec < 0) { |
338 | err = nvec; | |
339 | goto err_free_irq_info; | |
340 | } | |
e126ba97 | 341 | |
f3c9407b | 342 | table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; |
e126ba97 EC |
343 | |
344 | return 0; | |
db058a18 | 345 | |
b6908c29 | 346 | err_free_irq_info: |
db058a18 | 347 | kfree(priv->irq_info); |
b6908c29 | 348 | return err; |
e126ba97 EC |
349 | } |
350 | ||
78249c42 | 351 | static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev) |
e126ba97 | 352 | { |
db058a18 | 353 | struct mlx5_priv *priv = &dev->priv; |
e126ba97 | 354 | |
78249c42 | 355 | pci_free_irq_vectors(dev->pdev); |
db058a18 | 356 | kfree(priv->irq_info); |
e126ba97 EC |
357 | } |
358 | ||
bd10838a | 359 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
360 | u8 he; |
361 | u8 rsvd[15]; | |
362 | }; | |
363 | ||
87b8de49 EC |
364 | #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) |
365 | ||
366 | enum { | |
c7a08ac7 EC |
367 | MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | |
368 | MLX5_DEV_CAP_FLAG_DCT, | |
87b8de49 EC |
369 | }; |
370 | ||
2974ab6e | 371 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
372 | { |
373 | switch (size) { | |
374 | case 128: | |
375 | return 0; | |
376 | case 256: | |
377 | return 1; | |
378 | case 512: | |
379 | return 2; | |
380 | case 1024: | |
381 | return 3; | |
382 | case 2048: | |
383 | return 4; | |
384 | case 4096: | |
385 | return 5; | |
386 | default: | |
2974ab6e | 387 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
388 | return 0; |
389 | } | |
390 | } | |
391 | ||
b06e7de8 LR |
392 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
393 | enum mlx5_cap_type cap_type, | |
394 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 395 | { |
b775516b EC |
396 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
397 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
398 | void *out, *hca_caps; |
399 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
400 | int err; |
401 | ||
b775516b EC |
402 | memset(in, 0, sizeof(in)); |
403 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 404 | if (!out) |
e126ba97 | 405 | return -ENOMEM; |
938fe83c | 406 | |
b775516b EC |
407 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
408 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
409 | err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); | |
c7a08ac7 | 410 | if (err) { |
938fe83c SM |
411 | mlx5_core_warn(dev, |
412 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
413 | cap_type, cap_mode, err); | |
e126ba97 EC |
414 | goto query_ex; |
415 | } | |
c7a08ac7 | 416 | |
938fe83c SM |
417 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
418 | ||
419 | switch (cap_mode) { | |
420 | case HCA_CAP_OPMOD_GET_MAX: | |
701052c5 | 421 | memcpy(dev->caps.hca_max[cap_type], hca_caps, |
938fe83c SM |
422 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
423 | break; | |
424 | case HCA_CAP_OPMOD_GET_CUR: | |
701052c5 | 425 | memcpy(dev->caps.hca_cur[cap_type], hca_caps, |
938fe83c SM |
426 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
427 | break; | |
428 | default: | |
429 | mlx5_core_warn(dev, | |
430 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
431 | cap_type, cap_mode); | |
432 | err = -EINVAL; | |
433 | break; | |
434 | } | |
c7a08ac7 EC |
435 | query_ex: |
436 | kfree(out); | |
437 | return err; | |
438 | } | |
439 | ||
b06e7de8 LR |
440 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
441 | { | |
442 | int ret; | |
443 | ||
444 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
445 | if (ret) | |
446 | return ret; | |
447 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
448 | } | |
449 | ||
f91e6d89 | 450 | static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod) |
c7a08ac7 | 451 | { |
c4f287c4 | 452 | u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; |
e126ba97 | 453 | |
b775516b | 454 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 455 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
c4f287c4 | 456 | return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); |
c7a08ac7 EC |
457 | } |
458 | ||
f91e6d89 EBE |
459 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) |
460 | { | |
461 | void *set_ctx; | |
462 | void *set_hca_cap; | |
463 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); | |
464 | int req_endianness; | |
465 | int err; | |
466 | ||
467 | if (MLX5_CAP_GEN(dev, atomic)) { | |
b06e7de8 | 468 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); |
f91e6d89 EBE |
469 | if (err) |
470 | return err; | |
471 | } else { | |
472 | return 0; | |
473 | } | |
474 | ||
475 | req_endianness = | |
476 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 477 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
478 | |
479 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
480 | return 0; | |
481 | ||
482 | set_ctx = kzalloc(set_sz, GFP_KERNEL); | |
483 | if (!set_ctx) | |
484 | return -ENOMEM; | |
485 | ||
486 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
487 | ||
488 | /* Set requestor to host endianness */ | |
bd10838a | 489 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
490 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
491 | ||
492 | err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); | |
493 | ||
494 | kfree(set_ctx); | |
495 | return err; | |
496 | } | |
497 | ||
c7a08ac7 EC |
498 | static int handle_hca_cap(struct mlx5_core_dev *dev) |
499 | { | |
b775516b | 500 | void *set_ctx = NULL; |
c7a08ac7 | 501 | struct mlx5_profile *prof = dev->profile; |
c7a08ac7 | 502 | int err = -ENOMEM; |
b775516b | 503 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
938fe83c | 504 | void *set_hca_cap; |
c7a08ac7 | 505 | |
b775516b | 506 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
c7a08ac7 | 507 | if (!set_ctx) |
e126ba97 | 508 | goto query_ex; |
e126ba97 | 509 | |
b06e7de8 | 510 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 EC |
511 | if (err) |
512 | goto query_ex; | |
513 | ||
938fe83c SM |
514 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
515 | capability); | |
701052c5 | 516 | memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL], |
938fe83c SM |
517 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
518 | ||
519 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 520 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 521 | 128); |
c7a08ac7 | 522 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 523 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 524 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 525 | |
883371c4 NO |
526 | /* Check log_max_qp from HCA caps to set in current profile */ |
527 | if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) { | |
528 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", | |
529 | profile[prof_sel].log_max_qp, | |
530 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); | |
531 | profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); | |
532 | } | |
c7a08ac7 | 533 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
534 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
535 | prof->log_max_qp); | |
c7a08ac7 | 536 | |
938fe83c SM |
537 | /* disable cmdif checksum */ |
538 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 539 | |
91828bd8 MD |
540 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
541 | * than 4K. | |
542 | */ | |
543 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
544 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
545 | ||
fe1e1876 CS |
546 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
547 | ||
f32f5bd2 DJ |
548 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
549 | MLX5_SET(cmd_hca_cap, | |
550 | set_hca_cap, | |
551 | cache_line_128byte, | |
552 | cache_line_size() == 128 ? 1 : 0); | |
553 | ||
f91e6d89 EBE |
554 | err = set_caps(dev, set_ctx, set_sz, |
555 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); | |
c7a08ac7 | 556 | |
e126ba97 | 557 | query_ex: |
e126ba97 | 558 | kfree(set_ctx); |
e126ba97 EC |
559 | return err; |
560 | } | |
561 | ||
562 | static int set_hca_ctrl(struct mlx5_core_dev *dev) | |
563 | { | |
bd10838a OG |
564 | struct mlx5_reg_host_endianness he_in; |
565 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
566 | int err; |
567 | ||
fc50db98 EC |
568 | if (!mlx5_core_is_pf(dev)) |
569 | return 0; | |
570 | ||
e126ba97 EC |
571 | memset(&he_in, 0, sizeof(he_in)); |
572 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
573 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
574 | &he_out, sizeof(he_out), | |
575 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
576 | return err; | |
577 | } | |
578 | ||
c85023e1 HN |
579 | static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) |
580 | { | |
581 | int ret = 0; | |
582 | ||
583 | /* Disable local_lb by default */ | |
8978cc92 | 584 | if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) |
c85023e1 HN |
585 | ret = mlx5_nic_vport_update_local_lb(dev, false); |
586 | ||
587 | return ret; | |
588 | } | |
589 | ||
0b107106 | 590 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 591 | { |
c4f287c4 SM |
592 | u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; |
593 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; | |
cd23b14b | 594 | |
0b107106 EC |
595 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
596 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
c4f287c4 | 597 | return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); |
cd23b14b EC |
598 | } |
599 | ||
0b107106 | 600 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 601 | { |
c4f287c4 SM |
602 | u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; |
603 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; | |
cd23b14b | 604 | |
0b107106 EC |
605 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
606 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
c4f287c4 | 607 | return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
cd23b14b EC |
608 | } |
609 | ||
a5a1d1c2 | 610 | u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev) |
b0844444 EBE |
611 | { |
612 | u32 timer_h, timer_h1, timer_l; | |
613 | ||
614 | timer_h = ioread32be(&dev->iseg->internal_timer_h); | |
615 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
616 | timer_h1 = ioread32be(&dev->iseg->internal_timer_h); | |
617 | if (timer_h != timer_h1) /* wrap around */ | |
618 | timer_l = ioread32be(&dev->iseg->internal_timer_l); | |
619 | ||
a5a1d1c2 | 620 | return (u64)timer_l | (u64)timer_h1 << 32; |
b0844444 EBE |
621 | } |
622 | ||
231243c8 SM |
623 | static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i) |
624 | { | |
625 | struct mlx5_priv *priv = &mdev->priv; | |
626 | int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i); | |
627 | ||
628 | if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) { | |
629 | mlx5_core_warn(mdev, "zalloc_cpumask_var failed"); | |
630 | return -ENOMEM; | |
631 | } | |
632 | ||
633 | cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node), | |
634 | priv->irq_info[i].mask); | |
635 | ||
636 | if (IS_ENABLED(CONFIG_SMP) && | |
637 | irq_set_affinity_hint(irq, priv->irq_info[i].mask)) | |
638 | mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq); | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i) | |
644 | { | |
645 | struct mlx5_priv *priv = &mdev->priv; | |
646 | int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i); | |
647 | ||
648 | irq_set_affinity_hint(irq, NULL); | |
649 | free_cpumask_var(priv->irq_info[i].mask); | |
650 | } | |
651 | ||
652 | static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev) | |
653 | { | |
654 | int err; | |
655 | int i; | |
656 | ||
657 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) { | |
658 | err = mlx5_irq_set_affinity_hint(mdev, i); | |
659 | if (err) | |
660 | goto err_out; | |
661 | } | |
662 | ||
663 | return 0; | |
664 | ||
665 | err_out: | |
666 | for (i--; i >= 0; i--) | |
667 | mlx5_irq_clear_affinity_hint(mdev, i); | |
668 | ||
669 | return err; | |
670 | } | |
671 | ||
672 | static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev) | |
673 | { | |
674 | int i; | |
675 | ||
676 | for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) | |
677 | mlx5_irq_clear_affinity_hint(mdev, i); | |
678 | } | |
679 | ||
0b6e26ce DT |
680 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
681 | unsigned int *irqn) | |
233d05d2 SM |
682 | { |
683 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
684 | struct mlx5_eq *eq, *n; | |
685 | int err = -ENOENT; | |
686 | ||
687 | spin_lock(&table->lock); | |
688 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
689 | if (eq->index == vector) { | |
690 | *eqn = eq->eqn; | |
691 | *irqn = eq->irqn; | |
692 | err = 0; | |
693 | break; | |
694 | } | |
695 | } | |
696 | spin_unlock(&table->lock); | |
697 | ||
698 | return err; | |
699 | } | |
700 | EXPORT_SYMBOL(mlx5_vector2eqn); | |
701 | ||
94c6825e MB |
702 | struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn) |
703 | { | |
704 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
705 | struct mlx5_eq *eq; | |
706 | ||
707 | spin_lock(&table->lock); | |
708 | list_for_each_entry(eq, &table->comp_eqs_list, list) | |
709 | if (eq->eqn == eqn) { | |
710 | spin_unlock(&table->lock); | |
711 | return eq; | |
712 | } | |
713 | ||
714 | spin_unlock(&table->lock); | |
715 | ||
716 | return ERR_PTR(-ENOENT); | |
717 | } | |
718 | ||
233d05d2 SM |
719 | static void free_comp_eqs(struct mlx5_core_dev *dev) |
720 | { | |
721 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
722 | struct mlx5_eq *eq, *n; | |
723 | ||
5a7b27eb MG |
724 | #ifdef CONFIG_RFS_ACCEL |
725 | if (dev->rmap) { | |
726 | free_irq_cpu_rmap(dev->rmap); | |
727 | dev->rmap = NULL; | |
728 | } | |
729 | #endif | |
233d05d2 SM |
730 | spin_lock(&table->lock); |
731 | list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { | |
732 | list_del(&eq->list); | |
733 | spin_unlock(&table->lock); | |
734 | if (mlx5_destroy_unmap_eq(dev, eq)) | |
735 | mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", | |
736 | eq->eqn); | |
737 | kfree(eq); | |
738 | spin_lock(&table->lock); | |
739 | } | |
740 | spin_unlock(&table->lock); | |
741 | } | |
742 | ||
743 | static int alloc_comp_eqs(struct mlx5_core_dev *dev) | |
744 | { | |
745 | struct mlx5_eq_table *table = &dev->priv.eq_table; | |
db058a18 | 746 | char name[MLX5_MAX_IRQ_NAME]; |
233d05d2 SM |
747 | struct mlx5_eq *eq; |
748 | int ncomp_vec; | |
749 | int nent; | |
750 | int err; | |
751 | int i; | |
752 | ||
753 | INIT_LIST_HEAD(&table->comp_eqs_list); | |
754 | ncomp_vec = table->num_comp_vectors; | |
755 | nent = MLX5_COMP_EQ_SIZE; | |
5a7b27eb MG |
756 | #ifdef CONFIG_RFS_ACCEL |
757 | dev->rmap = alloc_irq_cpu_rmap(ncomp_vec); | |
758 | if (!dev->rmap) | |
759 | return -ENOMEM; | |
760 | #endif | |
233d05d2 SM |
761 | for (i = 0; i < ncomp_vec; i++) { |
762 | eq = kzalloc(sizeof(*eq), GFP_KERNEL); | |
763 | if (!eq) { | |
764 | err = -ENOMEM; | |
765 | goto clean; | |
766 | } | |
767 | ||
5a7b27eb | 768 | #ifdef CONFIG_RFS_ACCEL |
78249c42 SG |
769 | irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev, |
770 | MLX5_EQ_VEC_COMP_BASE + i)); | |
5a7b27eb | 771 | #endif |
db058a18 | 772 | snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i); |
233d05d2 SM |
773 | err = mlx5_create_map_eq(dev, eq, |
774 | i + MLX5_EQ_VEC_COMP_BASE, nent, 0, | |
01187175 | 775 | name, MLX5_EQ_TYPE_COMP); |
233d05d2 SM |
776 | if (err) { |
777 | kfree(eq); | |
778 | goto clean; | |
779 | } | |
780 | mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); | |
781 | eq->index = i; | |
782 | spin_lock(&table->lock); | |
783 | list_add_tail(&eq->list, &table->comp_eqs_list); | |
784 | spin_unlock(&table->lock); | |
785 | } | |
786 | ||
787 | return 0; | |
788 | ||
789 | clean: | |
790 | free_comp_eqs(dev); | |
791 | return err; | |
792 | } | |
793 | ||
f62b8bb8 AV |
794 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
795 | { | |
c4f287c4 SM |
796 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; |
797 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; | |
f62b8bb8 | 798 | u32 sup_issi; |
c4f287c4 | 799 | int err; |
f62b8bb8 AV |
800 | |
801 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
c4f287c4 SM |
802 | err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), |
803 | query_out, sizeof(query_out)); | |
f62b8bb8 | 804 | if (err) { |
c4f287c4 SM |
805 | u32 syndrome; |
806 | u8 status; | |
807 | ||
808 | mlx5_cmd_mbox_status(query_out, &status, &syndrome); | |
f9c14e46 KH |
809 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
810 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
811 | err, status, syndrome); | |
812 | return err; | |
f62b8bb8 AV |
813 | } |
814 | ||
f9c14e46 KH |
815 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
816 | dev->issi = 0; | |
817 | return 0; | |
f62b8bb8 AV |
818 | } |
819 | ||
820 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
821 | ||
822 | if (sup_issi & (1 << 1)) { | |
c4f287c4 SM |
823 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; |
824 | u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; | |
f62b8bb8 AV |
825 | |
826 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
827 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
c4f287c4 SM |
828 | err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), |
829 | set_out, sizeof(set_out)); | |
f62b8bb8 | 830 | if (err) { |
f9c14e46 KH |
831 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
832 | err); | |
f62b8bb8 AV |
833 | return err; |
834 | } | |
835 | ||
836 | dev->issi = 1; | |
837 | ||
838 | return 0; | |
e74a1db0 | 839 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
840 | return 0; |
841 | } | |
842 | ||
9eb78923 | 843 | return -EOPNOTSUPP; |
f62b8bb8 | 844 | } |
f62b8bb8 | 845 | |
a31208b1 MD |
846 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
847 | { | |
848 | struct pci_dev *pdev = dev->pdev; | |
849 | int err = 0; | |
e126ba97 | 850 | |
e126ba97 EC |
851 | pci_set_drvdata(dev->pdev, dev); |
852 | strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); | |
853 | priv->name[MLX5_MAX_NAME_LEN - 1] = 0; | |
854 | ||
855 | mutex_init(&priv->pgdir_mutex); | |
856 | INIT_LIST_HEAD(&priv->pgdir_list); | |
857 | spin_lock_init(&priv->mkey_lock); | |
858 | ||
311c7c71 SM |
859 | mutex_init(&priv->alloc_mutex); |
860 | ||
861 | priv->numa_node = dev_to_node(&dev->pdev->dev); | |
862 | ||
e126ba97 EC |
863 | priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root); |
864 | if (!priv->dbg_root) | |
865 | return -ENOMEM; | |
866 | ||
89d44f0a | 867 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 868 | if (err) { |
1a91de28 | 869 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
e126ba97 EC |
870 | goto err_dbg; |
871 | } | |
872 | ||
873 | err = request_bar(pdev); | |
874 | if (err) { | |
1a91de28 | 875 | dev_err(&pdev->dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
876 | goto err_disable; |
877 | } | |
878 | ||
879 | pci_set_master(pdev); | |
880 | ||
881 | err = set_dma_caps(pdev); | |
882 | if (err) { | |
883 | dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n"); | |
884 | goto err_clr_master; | |
885 | } | |
886 | ||
887 | dev->iseg_base = pci_resource_start(dev->pdev, 0); | |
888 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); | |
889 | if (!dev->iseg) { | |
890 | err = -ENOMEM; | |
891 | dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n"); | |
892 | goto err_clr_master; | |
893 | } | |
a31208b1 MD |
894 | |
895 | return 0; | |
896 | ||
897 | err_clr_master: | |
898 | pci_clear_master(dev->pdev); | |
899 | release_bar(dev->pdev); | |
900 | err_disable: | |
89d44f0a | 901 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
902 | |
903 | err_dbg: | |
904 | debugfs_remove(priv->dbg_root); | |
905 | return err; | |
906 | } | |
907 | ||
908 | static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) | |
909 | { | |
910 | iounmap(dev->iseg); | |
911 | pci_clear_master(dev->pdev); | |
912 | release_bar(dev->pdev); | |
89d44f0a | 913 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
914 | debugfs_remove(priv->dbg_root); |
915 | } | |
916 | ||
59211bd3 MHY |
917 | static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) |
918 | { | |
919 | struct pci_dev *pdev = dev->pdev; | |
920 | int err; | |
921 | ||
59211bd3 MHY |
922 | err = mlx5_query_board_id(dev); |
923 | if (err) { | |
924 | dev_err(&pdev->dev, "query board id failed\n"); | |
925 | goto out; | |
926 | } | |
927 | ||
928 | err = mlx5_eq_init(dev); | |
929 | if (err) { | |
930 | dev_err(&pdev->dev, "failed to initialize eq\n"); | |
931 | goto out; | |
932 | } | |
933 | ||
59211bd3 MHY |
934 | err = mlx5_init_cq_table(dev); |
935 | if (err) { | |
936 | dev_err(&pdev->dev, "failed to initialize cq table\n"); | |
937 | goto err_eq_cleanup; | |
938 | } | |
939 | ||
940 | mlx5_init_qp_table(dev); | |
941 | ||
942 | mlx5_init_srq_table(dev); | |
943 | ||
944 | mlx5_init_mkey_table(dev); | |
945 | ||
52ec462e IT |
946 | mlx5_init_reserved_gids(dev); |
947 | ||
7c39afb3 FD |
948 | mlx5_init_clock(dev); |
949 | ||
59211bd3 MHY |
950 | err = mlx5_init_rl_table(dev); |
951 | if (err) { | |
952 | dev_err(&pdev->dev, "Failed to init rate limiting\n"); | |
953 | goto err_tables_cleanup; | |
954 | } | |
955 | ||
eeb66cdb SM |
956 | err = mlx5_mpfs_init(dev); |
957 | if (err) { | |
958 | dev_err(&pdev->dev, "Failed to init l2 table %d\n", err); | |
959 | goto err_rl_cleanup; | |
960 | } | |
961 | ||
c2d6e31a MHY |
962 | err = mlx5_eswitch_init(dev); |
963 | if (err) { | |
964 | dev_err(&pdev->dev, "Failed to init eswitch %d\n", err); | |
eeb66cdb | 965 | goto err_mpfs_cleanup; |
c2d6e31a | 966 | } |
c2d6e31a MHY |
967 | |
968 | err = mlx5_sriov_init(dev); | |
969 | if (err) { | |
970 | dev_err(&pdev->dev, "Failed to init sriov %d\n", err); | |
971 | goto err_eswitch_cleanup; | |
972 | } | |
973 | ||
9410733c IT |
974 | err = mlx5_fpga_init(dev); |
975 | if (err) { | |
976 | dev_err(&pdev->dev, "Failed to init fpga device %d\n", err); | |
977 | goto err_sriov_cleanup; | |
978 | } | |
979 | ||
59211bd3 MHY |
980 | return 0; |
981 | ||
9410733c IT |
982 | err_sriov_cleanup: |
983 | mlx5_sriov_cleanup(dev); | |
c2d6e31a | 984 | err_eswitch_cleanup: |
c2d6e31a | 985 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
eeb66cdb | 986 | err_mpfs_cleanup: |
eeb66cdb | 987 | mlx5_mpfs_cleanup(dev); |
c2d6e31a | 988 | err_rl_cleanup: |
c2d6e31a | 989 | mlx5_cleanup_rl_table(dev); |
59211bd3 MHY |
990 | err_tables_cleanup: |
991 | mlx5_cleanup_mkey_table(dev); | |
992 | mlx5_cleanup_srq_table(dev); | |
993 | mlx5_cleanup_qp_table(dev); | |
994 | mlx5_cleanup_cq_table(dev); | |
995 | ||
996 | err_eq_cleanup: | |
997 | mlx5_eq_cleanup(dev); | |
998 | ||
999 | out: | |
1000 | return err; | |
1001 | } | |
1002 | ||
1003 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
1004 | { | |
9410733c | 1005 | mlx5_fpga_cleanup(dev); |
c2d6e31a | 1006 | mlx5_sriov_cleanup(dev); |
c2d6e31a | 1007 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
eeb66cdb | 1008 | mlx5_mpfs_cleanup(dev); |
59211bd3 | 1009 | mlx5_cleanup_rl_table(dev); |
7c39afb3 | 1010 | mlx5_cleanup_clock(dev); |
52ec462e | 1011 | mlx5_cleanup_reserved_gids(dev); |
59211bd3 MHY |
1012 | mlx5_cleanup_mkey_table(dev); |
1013 | mlx5_cleanup_srq_table(dev); | |
1014 | mlx5_cleanup_qp_table(dev); | |
1015 | mlx5_cleanup_cq_table(dev); | |
1016 | mlx5_eq_cleanup(dev); | |
1017 | } | |
1018 | ||
1019 | static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, | |
1020 | bool boot) | |
a31208b1 MD |
1021 | { |
1022 | struct pci_dev *pdev = dev->pdev; | |
1023 | int err; | |
1024 | ||
89d44f0a | 1025 | mutex_lock(&dev->intf_state_mutex); |
5fc7197d | 1026 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
1027 | dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n", |
1028 | __func__); | |
1029 | goto out; | |
1030 | } | |
1031 | ||
e126ba97 EC |
1032 | dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
1033 | fw_rev_min(dev), fw_rev_sub(dev)); | |
1034 | ||
89d44f0a MD |
1035 | /* on load removing any previous indication of internal error, device is |
1036 | * up | |
1037 | */ | |
1038 | dev->state = MLX5_DEVICE_STATE_UP; | |
1039 | ||
6c780a02 EC |
1040 | /* wait for firmware to accept initialization segments configurations |
1041 | */ | |
1042 | err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI); | |
1043 | if (err) { | |
1044 | dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n", | |
1045 | FW_PRE_INIT_TIMEOUT_MILI); | |
8ce59b16 | 1046 | goto out_err; |
6c780a02 EC |
1047 | } |
1048 | ||
e126ba97 EC |
1049 | err = mlx5_cmd_init(dev); |
1050 | if (err) { | |
1051 | dev_err(&pdev->dev, "Failed initializing command interface, aborting\n"); | |
89d44f0a | 1052 | goto out_err; |
e126ba97 EC |
1053 | } |
1054 | ||
e3297246 EC |
1055 | err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI); |
1056 | if (err) { | |
1057 | dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n", | |
1058 | FW_INIT_TIMEOUT_MILI); | |
55378a23 | 1059 | goto err_cmd_cleanup; |
e3297246 EC |
1060 | } |
1061 | ||
0b107106 | 1062 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b EC |
1063 | if (err) { |
1064 | dev_err(&pdev->dev, "enable hca failed\n"); | |
59211bd3 | 1065 | goto err_cmd_cleanup; |
cd23b14b EC |
1066 | } |
1067 | ||
f62b8bb8 AV |
1068 | err = mlx5_core_set_issi(dev); |
1069 | if (err) { | |
1070 | dev_err(&pdev->dev, "failed to set issi\n"); | |
1071 | goto err_disable_hca; | |
1072 | } | |
f62b8bb8 | 1073 | |
cd23b14b EC |
1074 | err = mlx5_satisfy_startup_pages(dev, 1); |
1075 | if (err) { | |
1076 | dev_err(&pdev->dev, "failed to allocate boot pages\n"); | |
1077 | goto err_disable_hca; | |
1078 | } | |
1079 | ||
e126ba97 EC |
1080 | err = set_hca_ctrl(dev); |
1081 | if (err) { | |
1082 | dev_err(&pdev->dev, "set_hca_ctrl failed\n"); | |
cd23b14b | 1083 | goto reclaim_boot_pages; |
e126ba97 EC |
1084 | } |
1085 | ||
1086 | err = handle_hca_cap(dev); | |
1087 | if (err) { | |
1088 | dev_err(&pdev->dev, "handle_hca_cap failed\n"); | |
cd23b14b | 1089 | goto reclaim_boot_pages; |
e126ba97 EC |
1090 | } |
1091 | ||
f91e6d89 EBE |
1092 | err = handle_hca_cap_atomic(dev); |
1093 | if (err) { | |
1094 | dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n"); | |
1095 | goto reclaim_boot_pages; | |
e126ba97 EC |
1096 | } |
1097 | ||
cd23b14b | 1098 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1099 | if (err) { |
cd23b14b EC |
1100 | dev_err(&pdev->dev, "failed to allocate init pages\n"); |
1101 | goto reclaim_boot_pages; | |
e126ba97 EC |
1102 | } |
1103 | ||
1104 | err = mlx5_pagealloc_start(dev); | |
1105 | if (err) { | |
1106 | dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n"); | |
cd23b14b | 1107 | goto reclaim_boot_pages; |
e126ba97 EC |
1108 | } |
1109 | ||
1110 | err = mlx5_cmd_init_hca(dev); | |
1111 | if (err) { | |
1112 | dev_err(&pdev->dev, "init hca failed\n"); | |
1113 | goto err_pagealloc_stop; | |
1114 | } | |
1115 | ||
012e50e1 HN |
1116 | mlx5_set_driver_version(dev); |
1117 | ||
e126ba97 EC |
1118 | mlx5_start_health_poll(dev); |
1119 | ||
bba1574c DJ |
1120 | err = mlx5_query_hca_caps(dev); |
1121 | if (err) { | |
1122 | dev_err(&pdev->dev, "query hca failed\n"); | |
1123 | goto err_stop_poll; | |
1124 | } | |
1125 | ||
259bbc57 MG |
1126 | if (boot) { |
1127 | err = mlx5_init_once(dev, priv); | |
1128 | if (err) { | |
1129 | dev_err(&pdev->dev, "sw objs init failed\n"); | |
1130 | goto err_stop_poll; | |
1131 | } | |
e126ba97 EC |
1132 | } |
1133 | ||
78249c42 | 1134 | err = mlx5_alloc_irq_vectors(dev); |
e126ba97 | 1135 | if (err) { |
78249c42 | 1136 | dev_err(&pdev->dev, "alloc irq vectors failed\n"); |
59211bd3 | 1137 | goto err_cleanup_once; |
e126ba97 EC |
1138 | } |
1139 | ||
01187175 | 1140 | dev->priv.uar = mlx5_get_uars_page(dev); |
72f36be0 | 1141 | if (IS_ERR(dev->priv.uar)) { |
e126ba97 | 1142 | dev_err(&pdev->dev, "Failed allocating uar, aborting\n"); |
72f36be0 | 1143 | err = PTR_ERR(dev->priv.uar); |
59211bd3 | 1144 | goto err_disable_msix; |
e126ba97 EC |
1145 | } |
1146 | ||
1147 | err = mlx5_start_eqs(dev); | |
1148 | if (err) { | |
1149 | dev_err(&pdev->dev, "Failed to start pages and async EQs\n"); | |
9410733c | 1150 | goto err_put_uars; |
e126ba97 EC |
1151 | } |
1152 | ||
233d05d2 SM |
1153 | err = alloc_comp_eqs(dev); |
1154 | if (err) { | |
1155 | dev_err(&pdev->dev, "Failed to alloc completion EQs\n"); | |
1156 | goto err_stop_eqs; | |
1157 | } | |
1158 | ||
231243c8 SM |
1159 | err = mlx5_irq_set_affinity_hints(dev); |
1160 | if (err) { | |
1161 | dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n"); | |
1162 | goto err_affinity_hints; | |
1163 | } | |
1164 | ||
86d722ad | 1165 | err = mlx5_init_fs(dev); |
59211bd3 | 1166 | if (err) { |
86d722ad | 1167 | dev_err(&pdev->dev, "Failed to init flow steering\n"); |
c85023e1 | 1168 | goto err_fs; |
59211bd3 | 1169 | } |
e126ba97 | 1170 | |
c85023e1 | 1171 | err = mlx5_core_set_hca_defaults(dev); |
86d722ad | 1172 | if (err) { |
c85023e1 | 1173 | dev_err(&pdev->dev, "Failed to set hca defaults\n"); |
86d722ad MG |
1174 | goto err_fs; |
1175 | } | |
1466cc5b | 1176 | |
c2d6e31a | 1177 | err = mlx5_sriov_attach(dev); |
fc50db98 EC |
1178 | if (err) { |
1179 | dev_err(&pdev->dev, "sriov init failed %d\n", err); | |
1180 | goto err_sriov; | |
1181 | } | |
1182 | ||
e29341fb IT |
1183 | err = mlx5_fpga_device_start(dev); |
1184 | if (err) { | |
1185 | dev_err(&pdev->dev, "fpga device start failed %d\n", err); | |
52ec462e | 1186 | goto err_fpga_start; |
e29341fb | 1187 | } |
bebb23e6 IT |
1188 | err = mlx5_accel_ipsec_init(dev); |
1189 | if (err) { | |
1190 | dev_err(&pdev->dev, "IPSec device start failed %d\n", err); | |
1191 | goto err_ipsec_start; | |
1192 | } | |
e29341fb | 1193 | |
737a234b MHY |
1194 | if (mlx5_device_registered(dev)) { |
1195 | mlx5_attach_device(dev); | |
1196 | } else { | |
1197 | err = mlx5_register_device(dev); | |
1198 | if (err) { | |
1199 | dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err); | |
1200 | goto err_reg_dev; | |
1201 | } | |
a31208b1 MD |
1202 | } |
1203 | ||
5fc7197d | 1204 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
89d44f0a MD |
1205 | out: |
1206 | mutex_unlock(&dev->intf_state_mutex); | |
1207 | ||
e126ba97 EC |
1208 | return 0; |
1209 | ||
59211bd3 | 1210 | err_reg_dev: |
bebb23e6 IT |
1211 | mlx5_accel_ipsec_cleanup(dev); |
1212 | err_ipsec_start: | |
52ec462e IT |
1213 | mlx5_fpga_device_stop(dev); |
1214 | ||
1215 | err_fpga_start: | |
c2d6e31a | 1216 | mlx5_sriov_detach(dev); |
fc50db98 | 1217 | |
59211bd3 | 1218 | err_sriov: |
86d722ad | 1219 | mlx5_cleanup_fs(dev); |
59211bd3 | 1220 | |
86d722ad | 1221 | err_fs: |
231243c8 SM |
1222 | mlx5_irq_clear_affinity_hints(dev); |
1223 | ||
1224 | err_affinity_hints: | |
db058a18 SM |
1225 | free_comp_eqs(dev); |
1226 | ||
233d05d2 SM |
1227 | err_stop_eqs: |
1228 | mlx5_stop_eqs(dev); | |
1229 | ||
5fe9dec0 | 1230 | err_put_uars: |
01187175 | 1231 | mlx5_put_uars_page(dev, priv->uar); |
e126ba97 | 1232 | |
59211bd3 | 1233 | err_disable_msix: |
78249c42 | 1234 | mlx5_free_irq_vectors(dev); |
e126ba97 | 1235 | |
59211bd3 MHY |
1236 | err_cleanup_once: |
1237 | if (boot) | |
1238 | mlx5_cleanup_once(dev); | |
1239 | ||
e126ba97 EC |
1240 | err_stop_poll: |
1241 | mlx5_stop_health_poll(dev); | |
1bde6e30 EC |
1242 | if (mlx5_cmd_teardown_hca(dev)) { |
1243 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); | |
89d44f0a | 1244 | goto out_err; |
1bde6e30 | 1245 | } |
e126ba97 EC |
1246 | |
1247 | err_pagealloc_stop: | |
1248 | mlx5_pagealloc_stop(dev); | |
1249 | ||
cd23b14b | 1250 | reclaim_boot_pages: |
e126ba97 EC |
1251 | mlx5_reclaim_startup_pages(dev); |
1252 | ||
cd23b14b | 1253 | err_disable_hca: |
0b107106 | 1254 | mlx5_core_disable_hca(dev, 0); |
cd23b14b | 1255 | |
59211bd3 | 1256 | err_cmd_cleanup: |
e126ba97 EC |
1257 | mlx5_cmd_cleanup(dev); |
1258 | ||
89d44f0a MD |
1259 | out_err: |
1260 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1261 | mutex_unlock(&dev->intf_state_mutex); | |
1262 | ||
e126ba97 EC |
1263 | return err; |
1264 | } | |
e126ba97 | 1265 | |
59211bd3 MHY |
1266 | static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, |
1267 | bool cleanup) | |
e126ba97 | 1268 | { |
89d44f0a | 1269 | int err = 0; |
e126ba97 | 1270 | |
5e44fca5 | 1271 | if (cleanup) |
2a0165a0 | 1272 | mlx5_drain_health_recovery(dev); |
689a248d | 1273 | |
89d44f0a | 1274 | mutex_lock(&dev->intf_state_mutex); |
b3cb5388 | 1275 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
89d44f0a MD |
1276 | dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", |
1277 | __func__); | |
59211bd3 MHY |
1278 | if (cleanup) |
1279 | mlx5_cleanup_once(dev); | |
89d44f0a MD |
1280 | goto out; |
1281 | } | |
6b6adee3 | 1282 | |
9ade8c7c | 1283 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
9ade8c7c | 1284 | |
737a234b MHY |
1285 | if (mlx5_device_registered(dev)) |
1286 | mlx5_detach_device(dev); | |
1287 | ||
bebb23e6 | 1288 | mlx5_accel_ipsec_cleanup(dev); |
52ec462e IT |
1289 | mlx5_fpga_device_stop(dev); |
1290 | ||
c2d6e31a | 1291 | mlx5_sriov_detach(dev); |
86d722ad | 1292 | mlx5_cleanup_fs(dev); |
231243c8 | 1293 | mlx5_irq_clear_affinity_hints(dev); |
233d05d2 | 1294 | free_comp_eqs(dev); |
e126ba97 | 1295 | mlx5_stop_eqs(dev); |
01187175 | 1296 | mlx5_put_uars_page(dev, priv->uar); |
78249c42 | 1297 | mlx5_free_irq_vectors(dev); |
59211bd3 MHY |
1298 | if (cleanup) |
1299 | mlx5_cleanup_once(dev); | |
e126ba97 | 1300 | mlx5_stop_health_poll(dev); |
ac6ea6e8 EC |
1301 | err = mlx5_cmd_teardown_hca(dev); |
1302 | if (err) { | |
1bde6e30 | 1303 | dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n"); |
ac6ea6e8 | 1304 | goto out; |
1bde6e30 | 1305 | } |
e126ba97 EC |
1306 | mlx5_pagealloc_stop(dev); |
1307 | mlx5_reclaim_startup_pages(dev); | |
0b107106 | 1308 | mlx5_core_disable_hca(dev, 0); |
e126ba97 | 1309 | mlx5_cmd_cleanup(dev); |
9603b61d | 1310 | |
ac6ea6e8 | 1311 | out: |
89d44f0a | 1312 | mutex_unlock(&dev->intf_state_mutex); |
ac6ea6e8 | 1313 | return err; |
9603b61d | 1314 | } |
64613d94 | 1315 | |
9603b61d JM |
1316 | struct mlx5_core_event_handler { |
1317 | void (*event)(struct mlx5_core_dev *dev, | |
1318 | enum mlx5_dev_event event, | |
1319 | void *data); | |
1320 | }; | |
1321 | ||
feae9087 | 1322 | static const struct devlink_ops mlx5_devlink_ops = { |
e80541ec | 1323 | #ifdef CONFIG_MLX5_ESWITCH |
feae9087 OG |
1324 | .eswitch_mode_set = mlx5_devlink_eswitch_mode_set, |
1325 | .eswitch_mode_get = mlx5_devlink_eswitch_mode_get, | |
bffaa916 RD |
1326 | .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set, |
1327 | .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get, | |
7768d197 RD |
1328 | .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set, |
1329 | .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, | |
feae9087 OG |
1330 | #endif |
1331 | }; | |
f66f049f | 1332 | |
59211bd3 | 1333 | #define MLX5_IB_MOD "mlx5_ib" |
9603b61d JM |
1334 | static int init_one(struct pci_dev *pdev, |
1335 | const struct pci_device_id *id) | |
1336 | { | |
1337 | struct mlx5_core_dev *dev; | |
feae9087 | 1338 | struct devlink *devlink; |
9603b61d JM |
1339 | struct mlx5_priv *priv; |
1340 | int err; | |
1341 | ||
feae9087 OG |
1342 | devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev)); |
1343 | if (!devlink) { | |
9603b61d JM |
1344 | dev_err(&pdev->dev, "kzalloc failed\n"); |
1345 | return -ENOMEM; | |
1346 | } | |
feae9087 OG |
1347 | |
1348 | dev = devlink_priv(devlink); | |
9603b61d | 1349 | priv = &dev->priv; |
fc50db98 | 1350 | priv->pci_dev_data = id->driver_data; |
9603b61d JM |
1351 | |
1352 | pci_set_drvdata(pdev, dev); | |
1353 | ||
0e97a340 HN |
1354 | dev->pdev = pdev; |
1355 | dev->event = mlx5_core_event; | |
9603b61d | 1356 | dev->profile = &profile[prof_sel]; |
9603b61d | 1357 | |
364d1798 EC |
1358 | INIT_LIST_HEAD(&priv->ctx_list); |
1359 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a MD |
1360 | mutex_init(&dev->pci_status_mutex); |
1361 | mutex_init(&dev->intf_state_mutex); | |
d9aaed83 | 1362 | |
97834eba ES |
1363 | INIT_LIST_HEAD(&priv->waiting_events_list); |
1364 | priv->is_accum_events = false; | |
1365 | ||
d9aaed83 AK |
1366 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1367 | err = init_srcu_struct(&priv->pfault_srcu); | |
1368 | if (err) { | |
1369 | dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n", | |
1370 | err); | |
1371 | goto clean_dev; | |
1372 | } | |
1373 | #endif | |
01187175 EC |
1374 | mutex_init(&priv->bfregs.reg_head.lock); |
1375 | mutex_init(&priv->bfregs.wc_head.lock); | |
1376 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1377 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1378 | ||
a31208b1 | 1379 | err = mlx5_pci_init(dev, priv); |
9603b61d | 1380 | if (err) { |
a31208b1 | 1381 | dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err); |
d9aaed83 | 1382 | goto clean_srcu; |
9603b61d JM |
1383 | } |
1384 | ||
ac6ea6e8 EC |
1385 | err = mlx5_health_init(dev); |
1386 | if (err) { | |
1387 | dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err); | |
1388 | goto close_pci; | |
1389 | } | |
1390 | ||
59211bd3 MHY |
1391 | mlx5_pagealloc_init(dev); |
1392 | ||
1393 | err = mlx5_load_one(dev, priv, true); | |
9603b61d | 1394 | if (err) { |
a31208b1 | 1395 | dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err); |
ac6ea6e8 | 1396 | goto clean_health; |
9603b61d | 1397 | } |
59211bd3 | 1398 | |
f82eed45 | 1399 | request_module_nowait(MLX5_IB_MOD); |
9603b61d | 1400 | |
feae9087 OG |
1401 | err = devlink_register(devlink, &pdev->dev); |
1402 | if (err) | |
1403 | goto clean_load; | |
1404 | ||
5d47f6c8 | 1405 | pci_save_state(pdev); |
9603b61d JM |
1406 | return 0; |
1407 | ||
feae9087 | 1408 | clean_load: |
59211bd3 | 1409 | mlx5_unload_one(dev, priv, true); |
ac6ea6e8 | 1410 | clean_health: |
59211bd3 | 1411 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1412 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1413 | close_pci: |
1414 | mlx5_pci_close(dev, priv); | |
d9aaed83 AK |
1415 | clean_srcu: |
1416 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING | |
1417 | cleanup_srcu_struct(&priv->pfault_srcu); | |
a31208b1 | 1418 | clean_dev: |
d9aaed83 | 1419 | #endif |
feae9087 | 1420 | devlink_free(devlink); |
a31208b1 | 1421 | |
9603b61d JM |
1422 | return err; |
1423 | } | |
a31208b1 | 1424 | |
9603b61d JM |
1425 | static void remove_one(struct pci_dev *pdev) |
1426 | { | |
1427 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1428 | struct devlink *devlink = priv_to_devlink(dev); |
a31208b1 | 1429 | struct mlx5_priv *priv = &dev->priv; |
9603b61d | 1430 | |
feae9087 | 1431 | devlink_unregister(devlink); |
737a234b MHY |
1432 | mlx5_unregister_device(dev); |
1433 | ||
59211bd3 | 1434 | if (mlx5_unload_one(dev, priv, true)) { |
a31208b1 | 1435 | dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n"); |
ac6ea6e8 | 1436 | mlx5_health_cleanup(dev); |
a31208b1 MD |
1437 | return; |
1438 | } | |
737a234b | 1439 | |
59211bd3 | 1440 | mlx5_pagealloc_cleanup(dev); |
ac6ea6e8 | 1441 | mlx5_health_cleanup(dev); |
a31208b1 | 1442 | mlx5_pci_close(dev, priv); |
d9aaed83 AK |
1443 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
1444 | cleanup_srcu_struct(&priv->pfault_srcu); | |
1445 | #endif | |
feae9087 | 1446 | devlink_free(devlink); |
9603b61d JM |
1447 | } |
1448 | ||
89d44f0a MD |
1449 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1450 | pci_channel_state_t state) | |
1451 | { | |
1452 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1453 | struct mlx5_priv *priv = &dev->priv; | |
1454 | ||
1455 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
04c0c1ab | 1456 | |
8812c24d | 1457 | mlx5_enter_error_state(dev, false); |
59211bd3 | 1458 | mlx5_unload_one(dev, priv, false); |
5d47f6c8 | 1459 | /* In case of kernel call drain the health wq */ |
05ac2c0b | 1460 | if (state) { |
5e44fca5 | 1461 | mlx5_drain_health_wq(dev); |
05ac2c0b MHY |
1462 | mlx5_pci_disable_device(dev); |
1463 | } | |
1464 | ||
89d44f0a MD |
1465 | return state == pci_channel_io_perm_failure ? |
1466 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
1467 | } | |
1468 | ||
d57847dc DJ |
1469 | /* wait for the device to show vital signs by waiting |
1470 | * for the health counter to start counting. | |
89d44f0a | 1471 | */ |
d57847dc | 1472 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1473 | { |
1474 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1475 | struct mlx5_core_health *health = &dev->priv.health; | |
1476 | const int niter = 100; | |
d57847dc | 1477 | u32 last_count = 0; |
89d44f0a | 1478 | u32 count; |
89d44f0a MD |
1479 | int i; |
1480 | ||
89d44f0a MD |
1481 | for (i = 0; i < niter; i++) { |
1482 | count = ioread32be(health->health_counter); | |
1483 | if (count && count != 0xffffffff) { | |
d57847dc DJ |
1484 | if (last_count && last_count != count) { |
1485 | dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i); | |
1486 | return 0; | |
1487 | } | |
1488 | last_count = count; | |
89d44f0a MD |
1489 | } |
1490 | msleep(50); | |
1491 | } | |
1492 | ||
d57847dc | 1493 | return -ETIMEDOUT; |
89d44f0a MD |
1494 | } |
1495 | ||
1061c90f | 1496 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a MD |
1497 | { |
1498 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
89d44f0a MD |
1499 | int err; |
1500 | ||
1501 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1502 | ||
1061c90f | 1503 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1504 | if (err) { |
1061c90f MHY |
1505 | dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n" |
1506 | , __func__, err); | |
1507 | return PCI_ERS_RESULT_DISCONNECT; | |
1508 | } | |
1509 | ||
1510 | pci_set_master(pdev); | |
1511 | pci_restore_state(pdev); | |
5d47f6c8 | 1512 | pci_save_state(pdev); |
1061c90f MHY |
1513 | |
1514 | if (wait_vital(pdev)) { | |
d57847dc | 1515 | dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__); |
1061c90f | 1516 | return PCI_ERS_RESULT_DISCONNECT; |
d57847dc | 1517 | } |
89d44f0a | 1518 | |
1061c90f MHY |
1519 | return PCI_ERS_RESULT_RECOVERED; |
1520 | } | |
1521 | ||
1061c90f MHY |
1522 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1523 | { | |
1524 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1525 | struct mlx5_priv *priv = &dev->priv; | |
1526 | int err; | |
1527 | ||
1528 | dev_info(&pdev->dev, "%s was called\n", __func__); | |
1529 | ||
59211bd3 | 1530 | err = mlx5_load_one(dev, priv, false); |
89d44f0a MD |
1531 | if (err) |
1532 | dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n" | |
1533 | , __func__, err); | |
1534 | else | |
1535 | dev_info(&pdev->dev, "%s: device recovered\n", __func__); | |
1536 | } | |
1537 | ||
1538 | static const struct pci_error_handlers mlx5_err_handler = { | |
1539 | .error_detected = mlx5_pci_err_detected, | |
1540 | .slot_reset = mlx5_pci_slot_reset, | |
1541 | .resume = mlx5_pci_resume | |
1542 | }; | |
1543 | ||
8812c24d MD |
1544 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1545 | { | |
1546 | int ret; | |
1547 | ||
1548 | if (!MLX5_CAP_GEN(dev, force_teardown)) { | |
1549 | mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); | |
1550 | return -EOPNOTSUPP; | |
1551 | } | |
1552 | ||
1553 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1554 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1555 | return -EAGAIN; | |
1556 | } | |
1557 | ||
d2aa060d HN |
1558 | /* Panic tear down fw command will stop the PCI bus communication |
1559 | * with the HCA, so the health polll is no longer needed. | |
1560 | */ | |
1561 | mlx5_drain_health_wq(dev); | |
1562 | mlx5_stop_health_poll(dev); | |
1563 | ||
8812c24d MD |
1564 | ret = mlx5_cmd_force_teardown_hca(dev); |
1565 | if (ret) { | |
1566 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
d2aa060d | 1567 | mlx5_start_health_poll(dev); |
8812c24d MD |
1568 | return ret; |
1569 | } | |
1570 | ||
1571 | mlx5_enter_error_state(dev, true); | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
5fc7197d MD |
1576 | static void shutdown(struct pci_dev *pdev) |
1577 | { | |
1578 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1579 | struct mlx5_priv *priv = &dev->priv; | |
8812c24d | 1580 | int err; |
5fc7197d MD |
1581 | |
1582 | dev_info(&pdev->dev, "Shutdown was called\n"); | |
8812c24d MD |
1583 | err = mlx5_try_fast_unload(dev); |
1584 | if (err) | |
1585 | mlx5_unload_one(dev, priv, false); | |
5fc7197d MD |
1586 | mlx5_pci_disable_device(dev); |
1587 | } | |
1588 | ||
9603b61d | 1589 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1590 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1591 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1592 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1593 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1594 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1595 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1596 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1597 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1598 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1599 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1600 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1601 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
2e9d3e83 NO |
1602 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1603 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
9603b61d JM |
1604 | { 0, } |
1605 | }; | |
1606 | ||
1607 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1608 | ||
04c0c1ab MHY |
1609 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1610 | { | |
1611 | mlx5_pci_err_detected(dev->pdev, 0); | |
1612 | } | |
1613 | ||
1614 | void mlx5_recover_device(struct mlx5_core_dev *dev) | |
1615 | { | |
1616 | mlx5_pci_disable_device(dev); | |
1617 | if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) | |
1618 | mlx5_pci_resume(dev->pdev); | |
1619 | } | |
1620 | ||
9603b61d JM |
1621 | static struct pci_driver mlx5_core_driver = { |
1622 | .name = DRIVER_NAME, | |
1623 | .id_table = mlx5_core_pci_table, | |
1624 | .probe = init_one, | |
89d44f0a | 1625 | .remove = remove_one, |
5fc7197d | 1626 | .shutdown = shutdown, |
fc50db98 EC |
1627 | .err_handler = &mlx5_err_handler, |
1628 | .sriov_configure = mlx5_core_sriov_configure, | |
9603b61d | 1629 | }; |
e126ba97 | 1630 | |
f663ad98 KH |
1631 | static void mlx5_core_verify_params(void) |
1632 | { | |
1633 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
1634 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
1635 | prof_sel, | |
1636 | ARRAY_SIZE(profile) - 1, | |
1637 | MLX5_DEFAULT_PROF); | |
1638 | prof_sel = MLX5_DEFAULT_PROF; | |
1639 | } | |
1640 | } | |
1641 | ||
e126ba97 EC |
1642 | static int __init init(void) |
1643 | { | |
1644 | int err; | |
1645 | ||
f663ad98 | 1646 | mlx5_core_verify_params(); |
e126ba97 | 1647 | mlx5_register_debugfs(); |
e126ba97 | 1648 | |
9603b61d JM |
1649 | err = pci_register_driver(&mlx5_core_driver); |
1650 | if (err) | |
ac6ea6e8 | 1651 | goto err_debug; |
9603b61d | 1652 | |
f62b8bb8 AV |
1653 | #ifdef CONFIG_MLX5_CORE_EN |
1654 | mlx5e_init(); | |
1655 | #endif | |
1656 | ||
e126ba97 EC |
1657 | return 0; |
1658 | ||
e126ba97 EC |
1659 | err_debug: |
1660 | mlx5_unregister_debugfs(); | |
1661 | return err; | |
1662 | } | |
1663 | ||
1664 | static void __exit cleanup(void) | |
1665 | { | |
f62b8bb8 AV |
1666 | #ifdef CONFIG_MLX5_CORE_EN |
1667 | mlx5e_cleanup(); | |
1668 | #endif | |
9603b61d | 1669 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
1670 | mlx5_unregister_debugfs(); |
1671 | } | |
1672 | ||
1673 | module_init(init); | |
1674 | module_exit(cleanup); |