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net/mlx5e: Removed not need synchronize_rcu
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / main.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
adec640e 33#include <linux/highmem.h>
e126ba97
EC		 34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
db058a18 41#include <linux/interrupt.h>
e3297246 42#include <linux/delay.h>
e126ba97
EC		 43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
f66f049f 48#include <linux/kmod.h>
b775516b 49#include <linux/mlx5/mlx5_ifc.h>
c85023e1 50#include <linux/mlx5/vport.h>
5a7b27eb
MG		 51#ifdef CONFIG_RFS_ACCEL
52#include <linux/cpu_rmap.h>
53#endif
feae9087 54#include <net/devlink.h>
e126ba97 55#include "mlx5_core.h"
86d722ad 56#include "fs_core.h"
eeb66cdb 57#include "lib/mpfs.h"
073bb189 58#include "eswitch.h"
52ec462e 59#include "lib/mlx5.h"
e29341fb 60#include "fpga/core.h"
bebb23e6 61#include "accel/ipsec.h"
7c39afb3 62#include "lib/clock.h"
e126ba97 63
e126ba97 64MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
4ae6c18c 65MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
e126ba97
EC		 66MODULE_LICENSE("Dual BSD/GPL");
67MODULE_VERSION(DRIVER_VERSION);
68
f663ad98
KH		 69unsigned int mlx5_core_debug_mask;
70module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
e126ba97
EC		 71MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
72
9603b61d 73#define MLX5_DEFAULT_PROF 2
f663ad98
KH		 74static unsigned int prof_sel = MLX5_DEFAULT_PROF;
75module_param_named(prof_sel, prof_sel, uint, 0444);
9603b61d
JM		 76MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
77
8737f818
DJ		 78static u32 sw_owner_id[4];
79
f91e6d89
EBE		 80enum {
81 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
82 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
83};
84
9603b61d
JM		 85static struct mlx5_profile profile[] = {
86 [0] = {
87 .mask = 0,
88 },
89 [1] = {
90 .mask = MLX5_PROF_MASK_QP_SIZE,
91 .log_max_qp = 12,
92 },
93 [2] = {
94 .mask = MLX5_PROF_MASK_QP_SIZE |
95 MLX5_PROF_MASK_MR_CACHE,
5f40b4ed 96 .log_max_qp = 18,
9603b61d
JM		 97 .mr_cache[0] = {
98 .size = 500,
99 .limit = 250
100 },
101 .mr_cache[1] = {
102 .size = 500,
103 .limit = 250
104 },
105 .mr_cache[2] = {
106 .size = 500,
107 .limit = 250
108 },
109 .mr_cache[3] = {
110 .size = 500,
111 .limit = 250
112 },
113 .mr_cache[4] = {
114 .size = 500,
115 .limit = 250
116 },
117 .mr_cache[5] = {
118 .size = 500,
119 .limit = 250
120 },
121 .mr_cache[6] = {
122 .size = 500,
123 .limit = 250
124 },
125 .mr_cache[7] = {
126 .size = 500,
127 .limit = 250
128 },
129 .mr_cache[8] = {
130 .size = 500,
131 .limit = 250
132 },
133 .mr_cache[9] = {
134 .size = 500,
135 .limit = 250
136 },
137 .mr_cache[10] = {
138 .size = 500,
139 .limit = 250
140 },
141 .mr_cache[11] = {
142 .size = 500,
143 .limit = 250
144 },
145 .mr_cache[12] = {
146 .size = 64,
147 .limit = 32
148 },
149 .mr_cache[13] = {
150 .size = 32,
151 .limit = 16
152 },
153 .mr_cache[14] = {
154 .size = 16,
155 .limit = 8
156 },
157 .mr_cache[15] = {
158 .size = 8,
159 .limit = 4
160 },
7d0cc6ed
AK		 161 .mr_cache[16] = {
162 .size = 8,
163 .limit = 4
164 },
165 .mr_cache[17] = {
166 .size = 8,
167 .limit = 4
168 },
169 .mr_cache[18] = {
170 .size = 8,
171 .limit = 4
172 },
173 .mr_cache[19] = {
174 .size = 4,
175 .limit = 2
176 },
177 .mr_cache[20] = {
178 .size = 4,
179 .limit = 2
180 },
9603b61d
JM		 181 },
182};
e126ba97 183
6c780a02
EC		 184#define FW_INIT_TIMEOUT_MILI 2000
185#define FW_INIT_WAIT_MS 2
186#define FW_PRE_INIT_TIMEOUT_MILI 10000
e3297246
EC		 187
188static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
189{
190 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
191 int err = 0;
192
193 while (fw_initializing(dev)) {
194 if (time_after(jiffies, end)) {
195 err = -EBUSY;
196 break;
197 }
198 msleep(FW_INIT_WAIT_MS);
199 }
200
201 return err;
202}
203
012e50e1
HN		 204static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
205{
206 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
207 driver_version);
208 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
209 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
210 int remaining_size = driver_ver_sz;
211 char *string;
212
213 if (!MLX5_CAP_GEN(dev, driver_version))
214 return;
215
216 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
217
218 strncpy(string, "Linux", remaining_size);
219
220 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
221 strncat(string, ",", remaining_size);
222
223 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
224 strncat(string, DRIVER_NAME, remaining_size);
225
226 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
227 strncat(string, ",", remaining_size);
228
229 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
230 strncat(string, DRIVER_VERSION, remaining_size);
231
232 /*Send the command*/
233 MLX5_SET(set_driver_version_in, in, opcode,
234 MLX5_CMD_OP_SET_DRIVER_VERSION);
235
236 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
237}
238
e126ba97
EC		 239static int set_dma_caps(struct pci_dev *pdev)
240{
241 int err;
242
243 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
244 if (err) {
1a91de28 245 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
e126ba97
EC		 246 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
247 if (err) {
1a91de28 248 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
e126ba97
EC		 249 return err;
250 }
251 }
252
253 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
254 if (err) {
255 dev_warn(&pdev->dev,
1a91de28 256 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
e126ba97
EC		 257 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
258 if (err) {
259 dev_err(&pdev->dev,
1a91de28 260 "Can't set consistent PCI DMA mask, aborting\n");
e126ba97
EC		 261 return err;
262 }
263 }
264
265 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
266 return err;
267}
268
89d44f0a
MD		 269static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
270{
271 struct pci_dev *pdev = dev->pdev;
272 int err = 0;
273
274 mutex_lock(&dev->pci_status_mutex);
275 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
276 err = pci_enable_device(pdev);
277 if (!err)
278 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
279 }
280 mutex_unlock(&dev->pci_status_mutex);
281
282 return err;
283}
284
285static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
286{
287 struct pci_dev *pdev = dev->pdev;
288
289 mutex_lock(&dev->pci_status_mutex);
290 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
291 pci_disable_device(pdev);
292 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
293 }
294 mutex_unlock(&dev->pci_status_mutex);
295}
296
e126ba97
EC		 297static int request_bar(struct pci_dev *pdev)
298{
299 int err = 0;
300
301 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1a91de28 302 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
e126ba97
EC		 303 return -ENODEV;
304 }
305
306 err = pci_request_regions(pdev, DRIVER_NAME);
307 if (err)
308 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
309
310 return err;
311}
312
313static void release_bar(struct pci_dev *pdev)
314{
315 pci_release_regions(pdev);
316}
317
78249c42 318static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
e126ba97 319{
db058a18
SM		 320 struct mlx5_priv *priv = &dev->priv;
321 struct mlx5_eq_table *table = &priv->eq_table;
938fe83c 322 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
e126ba97 323 int nvec;
b6908c29 324 int err;
e126ba97 325
938fe83c
SM		 326 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
327 MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 328 nvec = min_t(int, nvec, num_eqs);
329 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
330 return -ENOMEM;
331
db058a18 332 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
78249c42 333 if (!priv->irq_info)
b6908c29 334 return -ENOMEM;
e126ba97 335
231243c8 336 nvec = pci_alloc_irq_vectors(dev->pdev,
78249c42 337 MLX5_EQ_VEC_COMP_BASE + 1, nvec,
231243c8 338 PCI_IRQ_MSIX);
b6908c29
AH		 339 if (nvec < 0) {
340 err = nvec;
341 goto err_free_irq_info;
342 }
e126ba97 343
f3c9407b 344 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
e126ba97
EC		 345
346 return 0;
db058a18 347
b6908c29 348err_free_irq_info:
db058a18 349 kfree(priv->irq_info);
b6908c29 350 return err;
e126ba97
EC		 351}
352
78249c42 353static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
e126ba97 354{
db058a18 355 struct mlx5_priv *priv = &dev->priv;
e126ba97 356
78249c42 357 pci_free_irq_vectors(dev->pdev);
db058a18 358 kfree(priv->irq_info);
e126ba97
EC		 359}
360
bd10838a 361struct mlx5_reg_host_endianness {
e126ba97
EC		 362 u8 he;
363 u8 rsvd[15];
364};
365
87b8de49
EC		 366#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
367
368enum {
c7a08ac7
EC		 369 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
370 MLX5_DEV_CAP_FLAG_DCT,
87b8de49
EC		 371};
372
2974ab6e 373static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
c7a08ac7
EC		 374{
375 switch (size) {
376 case 128:
377 return 0;
378 case 256:
379 return 1;
380 case 512:
381 return 2;
382 case 1024:
383 return 3;
384 case 2048:
385 return 4;
386 case 4096:
387 return 5;
388 default:
2974ab6e 389 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
c7a08ac7
EC		 390 return 0;
391 }
392}
393
b06e7de8
LR		 394static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
395 enum mlx5_cap_type cap_type,
396 enum mlx5_cap_mode cap_mode)
c7a08ac7 397{
b775516b
EC		 398 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
399 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
938fe83c
SM		 400 void *out, *hca_caps;
401 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
e126ba97
EC		 402 int err;
403
b775516b
EC		 404 memset(in, 0, sizeof(in));
405 out = kzalloc(out_sz, GFP_KERNEL);
c7a08ac7 406 if (!out)
e126ba97 407 return -ENOMEM;
938fe83c 408
b775516b
EC		 409 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
410 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
411 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
c7a08ac7 412 if (err) {
938fe83c
SM		 413 mlx5_core_warn(dev,
414 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
415 cap_type, cap_mode, err);
e126ba97
EC		 416 goto query_ex;
417 }
c7a08ac7 418
938fe83c
SM		 419 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
420
421 switch (cap_mode) {
422 case HCA_CAP_OPMOD_GET_MAX:
701052c5 423 memcpy(dev->caps.hca_max[cap_type], hca_caps,
938fe83c
SM		 424 MLX5_UN_SZ_BYTES(hca_cap_union));
425 break;
426 case HCA_CAP_OPMOD_GET_CUR:
701052c5 427 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
938fe83c
SM		 428 MLX5_UN_SZ_BYTES(hca_cap_union));
429 break;
430 default:
431 mlx5_core_warn(dev,
432 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
433 cap_type, cap_mode);
434 err = -EINVAL;
435 break;
436 }
c7a08ac7
EC		 437query_ex:
438 kfree(out);
439 return err;
440}
441
b06e7de8
LR		 442int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
443{
444 int ret;
445
446 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
447 if (ret)
448 return ret;
449 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
450}
451
f91e6d89 452static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
c7a08ac7 453{
c4f287c4 454 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
e126ba97 455
b775516b 456 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
f91e6d89 457 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
c4f287c4 458 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
c7a08ac7
EC		 459}
460
f91e6d89
EBE		 461static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
462{
463 void *set_ctx;
464 void *set_hca_cap;
465 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
466 int req_endianness;
467 int err;
468
469 if (MLX5_CAP_GEN(dev, atomic)) {
b06e7de8 470 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
f91e6d89
EBE		 471 if (err)
472 return err;
473 } else {
474 return 0;
475 }
476
477 req_endianness =
478 MLX5_CAP_ATOMIC(dev,
bd10838a 479 supported_atomic_req_8B_endianness_mode_1);
f91e6d89
EBE		 480
481 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
482 return 0;
483
484 set_ctx = kzalloc(set_sz, GFP_KERNEL);
485 if (!set_ctx)
486 return -ENOMEM;
487
488 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
489
490 /* Set requestor to host endianness */
bd10838a 491 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
f91e6d89
EBE		 492 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
493
494 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
495
496 kfree(set_ctx);
497 return err;
498}
499
c7a08ac7
EC		 500static int handle_hca_cap(struct mlx5_core_dev *dev)
501{
b775516b 502 void *set_ctx = NULL;
c7a08ac7 503 struct mlx5_profile *prof = dev->profile;
c7a08ac7 504 int err = -ENOMEM;
b775516b 505 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
938fe83c 506 void *set_hca_cap;
c7a08ac7 507
b775516b 508 set_ctx = kzalloc(set_sz, GFP_KERNEL);
c7a08ac7 509 if (!set_ctx)
e126ba97 510 goto query_ex;
e126ba97 511
b06e7de8 512 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
e126ba97
EC		 513 if (err)
514 goto query_ex;
515
938fe83c
SM		 516 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
517 capability);
701052c5 518 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
938fe83c
SM		 519 MLX5_ST_SZ_BYTES(cmd_hca_cap));
520
521 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
707c4602 522 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
938fe83c 523 128);
c7a08ac7 524 /* we limit the size of the pkey table to 128 entries for now */
938fe83c 525 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
2974ab6e 526 to_fw_pkey_sz(dev, 128));
c7a08ac7 527
883371c4
NO		 528 /* Check log_max_qp from HCA caps to set in current profile */
529 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
530 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
531 profile[prof_sel].log_max_qp,
532 MLX5_CAP_GEN_MAX(dev, log_max_qp));
533 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
534 }
c7a08ac7 535 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
938fe83c
SM		 536 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
537 prof->log_max_qp);
c7a08ac7 538
938fe83c
SM		 539 /* disable cmdif checksum */
540 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
c7a08ac7 541
91828bd8
MD		 542 /* Enable 4K UAR only when HCA supports it and page size is bigger
543 * than 4K.
544 */
545 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
f502d834
EC		 546 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
547
fe1e1876
CS		 548 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
549
f32f5bd2
DJ		 550 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
551 MLX5_SET(cmd_hca_cap,
552 set_hca_cap,
553 cache_line_128byte,
554 cache_line_size() == 128 ? 1 : 0);
555
dd44572a
MS		 556 if (MLX5_CAP_GEN_MAX(dev, dct))
557 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
558
c4b76d8d
DJ		 559 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
560 MLX5_SET(cmd_hca_cap,
561 set_hca_cap,
562 num_vhca_ports,
563 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
564
f91e6d89
EBE		 565 err = set_caps(dev, set_ctx, set_sz,
566 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
c7a08ac7 567
e126ba97 568query_ex:
e126ba97 569 kfree(set_ctx);
e126ba97
EC		 570 return err;
571}
572
573static int set_hca_ctrl(struct mlx5_core_dev *dev)
574{
bd10838a
OG		 575 struct mlx5_reg_host_endianness he_in;
576 struct mlx5_reg_host_endianness he_out;
e126ba97
EC		 577 int err;
578
fc50db98
EC		 579 if (!mlx5_core_is_pf(dev))
580 return 0;
581
e126ba97
EC		 582 memset(&he_in, 0, sizeof(he_in));
583 he_in.he = MLX5_SET_HOST_ENDIANNESS;
584 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
585 &he_out, sizeof(he_out),
586 MLX5_REG_HOST_ENDIANNESS, 0, 1);
587 return err;
588}
589
c85023e1
HN		 590static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
591{
592 int ret = 0;
593
594 /* Disable local_lb by default */
8978cc92 595 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
c85023e1
HN		 596 ret = mlx5_nic_vport_update_local_lb(dev, false);
597
598 return ret;
599}
600
0b107106 601int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 602{
c4f287c4
SM		 603 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
604 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
cd23b14b 605
0b107106
EC		 606 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
607 MLX5_SET(enable_hca_in, in, function_id, func_id);
c4f287c4 608 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
cd23b14b
EC		 609}
610
0b107106 611int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
cd23b14b 612{
c4f287c4
SM		 613 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
614 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
cd23b14b 615
0b107106
EC		 616 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
617 MLX5_SET(disable_hca_in, in, function_id, func_id);
c4f287c4 618 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
cd23b14b
EC		 619}
620
a5a1d1c2 621u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
b0844444
EBE		 622{
623 u32 timer_h, timer_h1, timer_l;
624
625 timer_h = ioread32be(&dev->iseg->internal_timer_h);
626 timer_l = ioread32be(&dev->iseg->internal_timer_l);
627 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
628 if (timer_h != timer_h1) /* wrap around */
629 timer_l = ioread32be(&dev->iseg->internal_timer_l);
630
a5a1d1c2 631 return (u64)timer_l | (u64)timer_h1 << 32;
b0844444
EBE		 632}
633
231243c8
SM		 634static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
635{
636 struct mlx5_priv *priv = &mdev->priv;
637 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
638
639 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
640 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
641 return -ENOMEM;
642 }
643
644 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
645 priv->irq_info[i].mask);
646
647 if (IS_ENABLED(CONFIG_SMP) &&
648 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
649 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
650
651 return 0;
652}
653
654static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
655{
656 struct mlx5_priv *priv = &mdev->priv;
657 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
658
659 irq_set_affinity_hint(irq, NULL);
660 free_cpumask_var(priv->irq_info[i].mask);
661}
662
663static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
664{
665 int err;
666 int i;
667
668 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
669 err = mlx5_irq_set_affinity_hint(mdev, i);
670 if (err)
671 goto err_out;
672 }
673
674 return 0;
675
676err_out:
677 for (i--; i >= 0; i--)
678 mlx5_irq_clear_affinity_hint(mdev, i);
679
680 return err;
681}
682
683static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
684{
685 int i;
686
687 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
688 mlx5_irq_clear_affinity_hint(mdev, i);
689}
690
0b6e26ce
DT		 691int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
692 unsigned int *irqn)
233d05d2
SM		 693{
694 struct mlx5_eq_table *table = &dev->priv.eq_table;
695 struct mlx5_eq *eq, *n;
696 int err = -ENOENT;
697
698 spin_lock(&table->lock);
699 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
700 if (eq->index == vector) {
701 *eqn = eq->eqn;
702 *irqn = eq->irqn;
703 err = 0;
704 break;
705 }
706 }
707 spin_unlock(&table->lock);
708
709 return err;
710}
711EXPORT_SYMBOL(mlx5_vector2eqn);
712
94c6825e
MB		 713struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
714{
715 struct mlx5_eq_table *table = &dev->priv.eq_table;
716 struct mlx5_eq *eq;
717
718 spin_lock(&table->lock);
719 list_for_each_entry(eq, &table->comp_eqs_list, list)
720 if (eq->eqn == eqn) {
721 spin_unlock(&table->lock);
722 return eq;
723 }
724
725 spin_unlock(&table->lock);
726
727 return ERR_PTR(-ENOENT);
728}
729
233d05d2
SM		 730static void free_comp_eqs(struct mlx5_core_dev *dev)
731{
732 struct mlx5_eq_table *table = &dev->priv.eq_table;
733 struct mlx5_eq *eq, *n;
734
5a7b27eb
MG		 735#ifdef CONFIG_RFS_ACCEL
736 if (dev->rmap) {
737 free_irq_cpu_rmap(dev->rmap);
738 dev->rmap = NULL;
739 }
740#endif
233d05d2
SM		 741 spin_lock(&table->lock);
742 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
743 list_del(&eq->list);
744 spin_unlock(&table->lock);
745 if (mlx5_destroy_unmap_eq(dev, eq))
746 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
747 eq->eqn);
748 kfree(eq);
749 spin_lock(&table->lock);
750 }
751 spin_unlock(&table->lock);
752}
753
754static int alloc_comp_eqs(struct mlx5_core_dev *dev)
755{
756 struct mlx5_eq_table *table = &dev->priv.eq_table;
db058a18 757 char name[MLX5_MAX_IRQ_NAME];
233d05d2
SM		 758 struct mlx5_eq *eq;
759 int ncomp_vec;
760 int nent;
761 int err;
762 int i;
763
764 INIT_LIST_HEAD(&table->comp_eqs_list);
765 ncomp_vec = table->num_comp_vectors;
766 nent = MLX5_COMP_EQ_SIZE;
5a7b27eb
MG		 767#ifdef CONFIG_RFS_ACCEL
768 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
769 if (!dev->rmap)
770 return -ENOMEM;
771#endif
233d05d2
SM		 772 for (i = 0; i < ncomp_vec; i++) {
773 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
774 if (!eq) {
775 err = -ENOMEM;
776 goto clean;
777 }
778
5a7b27eb 779#ifdef CONFIG_RFS_ACCEL
78249c42
SG		 780 irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
781 MLX5_EQ_VEC_COMP_BASE + i));
5a7b27eb 782#endif
db058a18 783 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
233d05d2
SM		 784 err = mlx5_create_map_eq(dev, eq,
785 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
01187175 786 name, MLX5_EQ_TYPE_COMP);
233d05d2
SM		 787 if (err) {
788 kfree(eq);
789 goto clean;
790 }
791 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
792 eq->index = i;
793 spin_lock(&table->lock);
794 list_add_tail(&eq->list, &table->comp_eqs_list);
795 spin_unlock(&table->lock);
796 }
797
798 return 0;
799
800clean:
801 free_comp_eqs(dev);
802 return err;
803}
804
f62b8bb8
AV		 805static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
806{
c4f287c4
SM		 807 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
808 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
f62b8bb8 809 u32 sup_issi;
c4f287c4 810 int err;
f62b8bb8
AV		 811
812 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
c4f287c4
SM		 813 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
814 query_out, sizeof(query_out));
f62b8bb8 815 if (err) {
c4f287c4
SM		 816 u32 syndrome;
817 u8 status;
818
819 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
f9c14e46
KH		 820 if (!status || syndrome == MLX5_DRIVER_SYND) {
821 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
822 err, status, syndrome);
823 return err;
f62b8bb8
AV		 824 }
825
f9c14e46
KH		 826 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
827 dev->issi = 0;
828 return 0;
f62b8bb8
AV		 829 }
830
831 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
832
833 if (sup_issi & (1 << 1)) {
c4f287c4
SM		 834 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
835 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
f62b8bb8
AV		 836
837 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
838 MLX5_SET(set_issi_in, set_in, current_issi, 1);
c4f287c4
SM		 839 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
840 set_out, sizeof(set_out));
f62b8bb8 841 if (err) {
f9c14e46
KH		 842 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
843 err);
f62b8bb8
AV		 844 return err;
845 }
846
847 dev->issi = 1;
848
849 return 0;
e74a1db0 850 } else if (sup_issi & (1 << 0) || !sup_issi) {
f62b8bb8
AV		 851 return 0;
852 }
853
9eb78923 854 return -EOPNOTSUPP;
f62b8bb8 855}
f62b8bb8 856
a31208b1
MD		 857static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
858{
859 struct pci_dev *pdev = dev->pdev;
860 int err = 0;
e126ba97 861
e126ba97
EC		 862 pci_set_drvdata(dev->pdev, dev);
863 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
864 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
865
866 mutex_init(&priv->pgdir_mutex);
867 INIT_LIST_HEAD(&priv->pgdir_list);
868 spin_lock_init(&priv->mkey_lock);
869
311c7c71
SM		 870 mutex_init(&priv->alloc_mutex);
871
872 priv->numa_node = dev_to_node(&dev->pdev->dev);
873
e126ba97
EC		 874 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
875 if (!priv->dbg_root)
876 return -ENOMEM;
877
89d44f0a 878 err = mlx5_pci_enable_device(dev);
e126ba97 879 if (err) {
1a91de28 880 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
e126ba97
EC		 881 goto err_dbg;
882 }
883
884 err = request_bar(pdev);
885 if (err) {
1a91de28 886 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
e126ba97
EC		 887 goto err_disable;
888 }
889
890 pci_set_master(pdev);
891
892 err = set_dma_caps(pdev);
893 if (err) {
894 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
895 goto err_clr_master;
896 }
897
898 dev->iseg_base = pci_resource_start(dev->pdev, 0);
899 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
900 if (!dev->iseg) {
901 err = -ENOMEM;
902 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
903 goto err_clr_master;
904 }
a31208b1
MD		 905
906 return 0;
907
908err_clr_master:
909 pci_clear_master(dev->pdev);
910 release_bar(dev->pdev);
911err_disable:
89d44f0a 912 mlx5_pci_disable_device(dev);
a31208b1
MD		 913
914err_dbg:
915 debugfs_remove(priv->dbg_root);
916 return err;
917}
918
919static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
920{
921 iounmap(dev->iseg);
922 pci_clear_master(dev->pdev);
923 release_bar(dev->pdev);
89d44f0a 924 mlx5_pci_disable_device(dev);
a31208b1
MD		 925 debugfs_remove(priv->dbg_root);
926}
927
59211bd3
MHY		 928static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
929{
930 struct pci_dev *pdev = dev->pdev;
931 int err;
932
59211bd3
MHY		 933 err = mlx5_query_board_id(dev);
934 if (err) {
935 dev_err(&pdev->dev, "query board id failed\n");
936 goto out;
937 }
938
939 err = mlx5_eq_init(dev);
940 if (err) {
941 dev_err(&pdev->dev, "failed to initialize eq\n");
942 goto out;
943 }
944
02d92f79 945 err = mlx5_cq_debugfs_init(dev);
59211bd3 946 if (err) {
02d92f79 947 dev_err(&pdev->dev, "failed to initialize cq debugfs\n");
59211bd3
MHY		 948 goto err_eq_cleanup;
949 }
950
951 mlx5_init_qp_table(dev);
952
953 mlx5_init_srq_table(dev);
954
955 mlx5_init_mkey_table(dev);
956
52ec462e
IT		 957 mlx5_init_reserved_gids(dev);
958
7c39afb3
FD		 959 mlx5_init_clock(dev);
960
59211bd3
MHY		 961 err = mlx5_init_rl_table(dev);
962 if (err) {
963 dev_err(&pdev->dev, "Failed to init rate limiting\n");
964 goto err_tables_cleanup;
965 }
966
eeb66cdb
SM		 967 err = mlx5_mpfs_init(dev);
968 if (err) {
969 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
970 goto err_rl_cleanup;
971 }
972
c2d6e31a
MHY		 973 err = mlx5_eswitch_init(dev);
974 if (err) {
975 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
eeb66cdb 976 goto err_mpfs_cleanup;
c2d6e31a 977 }
c2d6e31a
MHY		 978
979 err = mlx5_sriov_init(dev);
980 if (err) {
981 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
982 goto err_eswitch_cleanup;
983 }
984
9410733c
IT		 985 err = mlx5_fpga_init(dev);
986 if (err) {
987 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
988 goto err_sriov_cleanup;
989 }
990
59211bd3
MHY		 991 return 0;
992
9410733c
IT		 993err_sriov_cleanup:
994 mlx5_sriov_cleanup(dev);
c2d6e31a 995err_eswitch_cleanup:
c2d6e31a 996 mlx5_eswitch_cleanup(dev->priv.eswitch);
eeb66cdb 997err_mpfs_cleanup:
eeb66cdb 998 mlx5_mpfs_cleanup(dev);
c2d6e31a 999err_rl_cleanup:
c2d6e31a 1000 mlx5_cleanup_rl_table(dev);
59211bd3
MHY		 1001err_tables_cleanup:
1002 mlx5_cleanup_mkey_table(dev);
1003 mlx5_cleanup_srq_table(dev);
1004 mlx5_cleanup_qp_table(dev);
02d92f79 1005 mlx5_cq_debugfs_cleanup(dev);
59211bd3
MHY		 1006
1007err_eq_cleanup:
1008 mlx5_eq_cleanup(dev);
1009
1010out:
1011 return err;
1012}
1013
1014static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1015{
9410733c 1016 mlx5_fpga_cleanup(dev);
c2d6e31a 1017 mlx5_sriov_cleanup(dev);
c2d6e31a 1018 mlx5_eswitch_cleanup(dev->priv.eswitch);
eeb66cdb 1019 mlx5_mpfs_cleanup(dev);
59211bd3 1020 mlx5_cleanup_rl_table(dev);
7c39afb3 1021 mlx5_cleanup_clock(dev);
52ec462e 1022 mlx5_cleanup_reserved_gids(dev);
59211bd3
MHY		 1023 mlx5_cleanup_mkey_table(dev);
1024 mlx5_cleanup_srq_table(dev);
1025 mlx5_cleanup_qp_table(dev);
02d92f79 1026 mlx5_cq_debugfs_cleanup(dev);
59211bd3
MHY		 1027 mlx5_eq_cleanup(dev);
1028}
1029
1030static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1031 bool boot)
a31208b1
MD		 1032{
1033 struct pci_dev *pdev = dev->pdev;
1034 int err;
1035
89d44f0a 1036 mutex_lock(&dev->intf_state_mutex);
5fc7197d 1037 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 1038 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1039 __func__);
1040 goto out;
1041 }
1042
e126ba97
EC		 1043 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1044 fw_rev_min(dev), fw_rev_sub(dev));
1045
89d44f0a
MD		 1046 /* on load removing any previous indication of internal error, device is
1047 * up
1048 */
1049 dev->state = MLX5_DEVICE_STATE_UP;
1050
6c780a02
EC		 1051 /* wait for firmware to accept initialization segments configurations
1052 */
1053 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
1054 if (err) {
1055 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
1056 FW_PRE_INIT_TIMEOUT_MILI);
8ce59b16 1057 goto out_err;
6c780a02
EC		 1058 }
1059
e126ba97
EC		 1060 err = mlx5_cmd_init(dev);
1061 if (err) {
1062 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
89d44f0a 1063 goto out_err;
e126ba97
EC		 1064 }
1065
e3297246
EC		 1066 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1067 if (err) {
1068 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1069 FW_INIT_TIMEOUT_MILI);
55378a23 1070 goto err_cmd_cleanup;
e3297246
EC		 1071 }
1072
0b107106 1073 err = mlx5_core_enable_hca(dev, 0);
cd23b14b
EC		 1074 if (err) {
1075 dev_err(&pdev->dev, "enable hca failed\n");
59211bd3 1076 goto err_cmd_cleanup;
cd23b14b
EC		 1077 }
1078
f62b8bb8
AV		 1079 err = mlx5_core_set_issi(dev);
1080 if (err) {
1081 dev_err(&pdev->dev, "failed to set issi\n");
1082 goto err_disable_hca;
1083 }
f62b8bb8 1084
cd23b14b
EC		 1085 err = mlx5_satisfy_startup_pages(dev, 1);
1086 if (err) {
1087 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1088 goto err_disable_hca;
1089 }
1090
e126ba97
EC		 1091 err = set_hca_ctrl(dev);
1092 if (err) {
1093 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
cd23b14b 1094 goto reclaim_boot_pages;
e126ba97
EC		 1095 }
1096
1097 err = handle_hca_cap(dev);
1098 if (err) {
1099 dev_err(&pdev->dev, "handle_hca_cap failed\n");
cd23b14b 1100 goto reclaim_boot_pages;
e126ba97
EC		 1101 }
1102
f91e6d89
EBE		 1103 err = handle_hca_cap_atomic(dev);
1104 if (err) {
1105 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1106 goto reclaim_boot_pages;
e126ba97
EC		 1107 }
1108
cd23b14b 1109 err = mlx5_satisfy_startup_pages(dev, 0);
e126ba97 1110 if (err) {
cd23b14b
EC		 1111 dev_err(&pdev->dev, "failed to allocate init pages\n");
1112 goto reclaim_boot_pages;
e126ba97
EC		 1113 }
1114
1115 err = mlx5_pagealloc_start(dev);
1116 if (err) {
1117 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
cd23b14b 1118 goto reclaim_boot_pages;
e126ba97
EC		 1119 }
1120
8737f818 1121 err = mlx5_cmd_init_hca(dev, sw_owner_id);
e126ba97
EC		 1122 if (err) {
1123 dev_err(&pdev->dev, "init hca failed\n");
1124 goto err_pagealloc_stop;
1125 }
1126
012e50e1
HN		 1127 mlx5_set_driver_version(dev);
1128
e126ba97
EC		 1129 mlx5_start_health_poll(dev);
1130
bba1574c
DJ		 1131 err = mlx5_query_hca_caps(dev);
1132 if (err) {
1133 dev_err(&pdev->dev, "query hca failed\n");
1134 goto err_stop_poll;
1135 }
1136
259bbc57
MG		 1137 if (boot) {
1138 err = mlx5_init_once(dev, priv);
1139 if (err) {
1140 dev_err(&pdev->dev, "sw objs init failed\n");
1141 goto err_stop_poll;
1142 }
e126ba97
EC		 1143 }
1144
78249c42 1145 err = mlx5_alloc_irq_vectors(dev);
e126ba97 1146 if (err) {
78249c42 1147 dev_err(&pdev->dev, "alloc irq vectors failed\n");
59211bd3 1148 goto err_cleanup_once;
e126ba97
EC		 1149 }
1150
01187175 1151 dev->priv.uar = mlx5_get_uars_page(dev);
72f36be0 1152 if (IS_ERR(dev->priv.uar)) {
e126ba97 1153 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
72f36be0 1154 err = PTR_ERR(dev->priv.uar);
59211bd3 1155 goto err_disable_msix;
e126ba97
EC		 1156 }
1157
1158 err = mlx5_start_eqs(dev);
1159 if (err) {
1160 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
9410733c 1161 goto err_put_uars;
e126ba97
EC		 1162 }
1163
233d05d2
SM		 1164 err = alloc_comp_eqs(dev);
1165 if (err) {
1166 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1167 goto err_stop_eqs;
1168 }
1169
231243c8
SM		 1170 err = mlx5_irq_set_affinity_hints(dev);
1171 if (err) {
1172 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1173 goto err_affinity_hints;
1174 }
1175
86d722ad 1176 err = mlx5_init_fs(dev);
59211bd3 1177 if (err) {
86d722ad 1178 dev_err(&pdev->dev, "Failed to init flow steering\n");
c85023e1 1179 goto err_fs;
59211bd3 1180 }
e126ba97 1181
c85023e1 1182 err = mlx5_core_set_hca_defaults(dev);
86d722ad 1183 if (err) {
c85023e1 1184 dev_err(&pdev->dev, "Failed to set hca defaults\n");
86d722ad
MG		 1185 goto err_fs;
1186 }
1466cc5b 1187
c2d6e31a 1188 err = mlx5_sriov_attach(dev);
fc50db98
EC		 1189 if (err) {
1190 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1191 goto err_sriov;
1192 }
1193
e29341fb
IT		 1194 err = mlx5_fpga_device_start(dev);
1195 if (err) {
1196 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
52ec462e 1197 goto err_fpga_start;
e29341fb 1198 }
bebb23e6
IT		 1199 err = mlx5_accel_ipsec_init(dev);
1200 if (err) {
1201 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1202 goto err_ipsec_start;
1203 }
e29341fb 1204
737a234b
MHY		 1205 if (mlx5_device_registered(dev)) {
1206 mlx5_attach_device(dev);
1207 } else {
1208 err = mlx5_register_device(dev);
1209 if (err) {
1210 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1211 goto err_reg_dev;
1212 }
a31208b1
MD		 1213 }
1214
5fc7197d 1215 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
89d44f0a
MD		 1216out:
1217 mutex_unlock(&dev->intf_state_mutex);
1218
e126ba97
EC		 1219 return 0;
1220
59211bd3 1221err_reg_dev:
bebb23e6
IT		 1222 mlx5_accel_ipsec_cleanup(dev);
1223err_ipsec_start:
52ec462e
IT		 1224 mlx5_fpga_device_stop(dev);
1225
1226err_fpga_start:
c2d6e31a 1227 mlx5_sriov_detach(dev);
fc50db98 1228
59211bd3 1229err_sriov:
86d722ad 1230 mlx5_cleanup_fs(dev);
59211bd3 1231
86d722ad 1232err_fs:
231243c8
SM		 1233 mlx5_irq_clear_affinity_hints(dev);
1234
1235err_affinity_hints:
db058a18
SM		 1236 free_comp_eqs(dev);
1237
233d05d2
SM		 1238err_stop_eqs:
1239 mlx5_stop_eqs(dev);
1240
5fe9dec0 1241err_put_uars:
01187175 1242 mlx5_put_uars_page(dev, priv->uar);
e126ba97 1243
59211bd3 1244err_disable_msix:
78249c42 1245 mlx5_free_irq_vectors(dev);
e126ba97 1246
59211bd3
MHY		 1247err_cleanup_once:
1248 if (boot)
1249 mlx5_cleanup_once(dev);
1250
e126ba97
EC		 1251err_stop_poll:
1252 mlx5_stop_health_poll(dev);
1bde6e30
EC		 1253 if (mlx5_cmd_teardown_hca(dev)) {
1254 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
89d44f0a 1255 goto out_err;
1bde6e30 1256 }
e126ba97
EC		 1257
1258err_pagealloc_stop:
1259 mlx5_pagealloc_stop(dev);
1260
cd23b14b 1261reclaim_boot_pages:
e126ba97
EC		 1262 mlx5_reclaim_startup_pages(dev);
1263
cd23b14b 1264err_disable_hca:
0b107106 1265 mlx5_core_disable_hca(dev, 0);
cd23b14b 1266
59211bd3 1267err_cmd_cleanup:
e126ba97
EC		 1268 mlx5_cmd_cleanup(dev);
1269
89d44f0a
MD		 1270out_err:
1271 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1272 mutex_unlock(&dev->intf_state_mutex);
1273
e126ba97
EC		 1274 return err;
1275}
e126ba97 1276
59211bd3
MHY		 1277static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1278 bool cleanup)
e126ba97 1279{
89d44f0a 1280 int err = 0;
e126ba97 1281
5e44fca5 1282 if (cleanup)
2a0165a0 1283 mlx5_drain_health_recovery(dev);
689a248d 1284
89d44f0a 1285 mutex_lock(&dev->intf_state_mutex);
b3cb5388 1286 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
89d44f0a
MD		 1287 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1288 __func__);
59211bd3
MHY		 1289 if (cleanup)
1290 mlx5_cleanup_once(dev);
89d44f0a
MD		 1291 goto out;
1292 }
6b6adee3 1293
9ade8c7c 1294 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
9ade8c7c 1295
737a234b
MHY		 1296 if (mlx5_device_registered(dev))
1297 mlx5_detach_device(dev);
1298
bebb23e6 1299 mlx5_accel_ipsec_cleanup(dev);
52ec462e
IT		 1300 mlx5_fpga_device_stop(dev);
1301
c2d6e31a 1302 mlx5_sriov_detach(dev);
86d722ad 1303 mlx5_cleanup_fs(dev);
231243c8 1304 mlx5_irq_clear_affinity_hints(dev);
233d05d2 1305 free_comp_eqs(dev);
e126ba97 1306 mlx5_stop_eqs(dev);
01187175 1307 mlx5_put_uars_page(dev, priv->uar);
78249c42 1308 mlx5_free_irq_vectors(dev);
59211bd3
MHY		 1309 if (cleanup)
1310 mlx5_cleanup_once(dev);
e126ba97 1311 mlx5_stop_health_poll(dev);
ac6ea6e8
EC		 1312 err = mlx5_cmd_teardown_hca(dev);
1313 if (err) {
1bde6e30 1314 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
ac6ea6e8 1315 goto out;
1bde6e30 1316 }
e126ba97
EC		 1317 mlx5_pagealloc_stop(dev);
1318 mlx5_reclaim_startup_pages(dev);
0b107106 1319 mlx5_core_disable_hca(dev, 0);
e126ba97 1320 mlx5_cmd_cleanup(dev);
9603b61d 1321
ac6ea6e8 1322out:
89d44f0a 1323 mutex_unlock(&dev->intf_state_mutex);
ac6ea6e8 1324 return err;
9603b61d 1325}
64613d94 1326
9603b61d
JM		 1327struct mlx5_core_event_handler {
1328 void (*event)(struct mlx5_core_dev *dev,
1329 enum mlx5_dev_event event,
1330 void *data);
1331};
1332
feae9087 1333static const struct devlink_ops mlx5_devlink_ops = {
e80541ec 1334#ifdef CONFIG_MLX5_ESWITCH
feae9087
OG		 1335 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1336 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
bffaa916
RD		 1337 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1338 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
7768d197
RD		 1339 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1340 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
feae9087
OG		 1341#endif
1342};
f66f049f 1343
59211bd3 1344#define MLX5_IB_MOD "mlx5_ib"
9603b61d
JM		 1345static int init_one(struct pci_dev *pdev,
1346 const struct pci_device_id *id)
1347{
1348 struct mlx5_core_dev *dev;
feae9087 1349 struct devlink *devlink;
9603b61d
JM		 1350 struct mlx5_priv *priv;
1351 int err;
1352
feae9087
OG		 1353 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1354 if (!devlink) {
9603b61d
JM		 1355 dev_err(&pdev->dev, "kzalloc failed\n");
1356 return -ENOMEM;
1357 }
feae9087
OG		 1358
1359 dev = devlink_priv(devlink);
9603b61d 1360 priv = &dev->priv;
fc50db98 1361 priv->pci_dev_data = id->driver_data;
9603b61d
JM		 1362
1363 pci_set_drvdata(pdev, dev);
1364
0e97a340
HN		 1365 dev->pdev = pdev;
1366 dev->event = mlx5_core_event;
9603b61d 1367 dev->profile = &profile[prof_sel];
9603b61d 1368
364d1798
EC		 1369 INIT_LIST_HEAD(&priv->ctx_list);
1370 spin_lock_init(&priv->ctx_lock);
89d44f0a
MD		 1371 mutex_init(&dev->pci_status_mutex);
1372 mutex_init(&dev->intf_state_mutex);
d9aaed83 1373
97834eba
ES		 1374 INIT_LIST_HEAD(&priv->waiting_events_list);
1375 priv->is_accum_events = false;
1376
d9aaed83
AK		 1377#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1378 err = init_srcu_struct(&priv->pfault_srcu);
1379 if (err) {
1380 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1381 err);
1382 goto clean_dev;
1383 }
1384#endif
01187175
EC		 1385 mutex_init(&priv->bfregs.reg_head.lock);
1386 mutex_init(&priv->bfregs.wc_head.lock);
1387 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1388 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1389
a31208b1 1390 err = mlx5_pci_init(dev, priv);
9603b61d 1391 if (err) {
a31208b1 1392 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
d9aaed83 1393 goto clean_srcu;
9603b61d
JM		 1394 }
1395
ac6ea6e8
EC		 1396 err = mlx5_health_init(dev);
1397 if (err) {
1398 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1399 goto close_pci;
1400 }
1401
59211bd3
MHY		 1402 mlx5_pagealloc_init(dev);
1403
1404 err = mlx5_load_one(dev, priv, true);
9603b61d 1405 if (err) {
a31208b1 1406 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
ac6ea6e8 1407 goto clean_health;
9603b61d 1408 }
59211bd3 1409
f82eed45 1410 request_module_nowait(MLX5_IB_MOD);
9603b61d 1411
feae9087
OG		 1412 err = devlink_register(devlink, &pdev->dev);
1413 if (err)
1414 goto clean_load;
1415
5d47f6c8 1416 pci_save_state(pdev);
9603b61d
JM		 1417 return 0;
1418
feae9087 1419clean_load:
59211bd3 1420 mlx5_unload_one(dev, priv, true);
ac6ea6e8 1421clean_health:
59211bd3 1422 mlx5_pagealloc_cleanup(dev);
ac6ea6e8 1423 mlx5_health_cleanup(dev);
a31208b1
MD		 1424close_pci:
1425 mlx5_pci_close(dev, priv);
d9aaed83
AK		 1426clean_srcu:
1427#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1428 cleanup_srcu_struct(&priv->pfault_srcu);
a31208b1 1429clean_dev:
d9aaed83 1430#endif
feae9087 1431 devlink_free(devlink);
a31208b1 1432
9603b61d
JM		 1433 return err;
1434}
a31208b1 1435
9603b61d
JM		 1436static void remove_one(struct pci_dev *pdev)
1437{
1438 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
feae9087 1439 struct devlink *devlink = priv_to_devlink(dev);
a31208b1 1440 struct mlx5_priv *priv = &dev->priv;
9603b61d 1441
feae9087 1442 devlink_unregister(devlink);
737a234b
MHY		 1443 mlx5_unregister_device(dev);
1444
59211bd3 1445 if (mlx5_unload_one(dev, priv, true)) {
a31208b1 1446 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
ac6ea6e8 1447 mlx5_health_cleanup(dev);
a31208b1
MD		 1448 return;
1449 }
737a234b 1450
59211bd3 1451 mlx5_pagealloc_cleanup(dev);
ac6ea6e8 1452 mlx5_health_cleanup(dev);
a31208b1 1453 mlx5_pci_close(dev, priv);
d9aaed83
AK		 1454#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1455 cleanup_srcu_struct(&priv->pfault_srcu);
1456#endif
feae9087 1457 devlink_free(devlink);
9603b61d
JM		 1458}
1459
89d44f0a
MD		 1460static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1461 pci_channel_state_t state)
1462{
1463 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1464 struct mlx5_priv *priv = &dev->priv;
1465
1466 dev_info(&pdev->dev, "%s was called\n", __func__);
04c0c1ab 1467
8812c24d 1468 mlx5_enter_error_state(dev, false);
59211bd3 1469 mlx5_unload_one(dev, priv, false);
5d47f6c8 1470 /* In case of kernel call drain the health wq */
05ac2c0b 1471 if (state) {
5e44fca5 1472 mlx5_drain_health_wq(dev);
05ac2c0b
MHY		 1473 mlx5_pci_disable_device(dev);
1474 }
1475
89d44f0a
MD		 1476 return state == pci_channel_io_perm_failure ?
1477 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1478}
1479
d57847dc
DJ		 1480/* wait for the device to show vital signs by waiting
1481 * for the health counter to start counting.
89d44f0a 1482 */
d57847dc 1483static int wait_vital(struct pci_dev *pdev)
89d44f0a
MD		 1484{
1485 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1486 struct mlx5_core_health *health = &dev->priv.health;
1487 const int niter = 100;
d57847dc 1488 u32 last_count = 0;
89d44f0a 1489 u32 count;
89d44f0a
MD		 1490 int i;
1491
89d44f0a
MD		 1492 for (i = 0; i < niter; i++) {
1493 count = ioread32be(health->health_counter);
1494 if (count && count != 0xffffffff) {
d57847dc
DJ		 1495 if (last_count && last_count != count) {
1496 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1497 return 0;
1498 }
1499 last_count = count;
89d44f0a
MD		 1500 }
1501 msleep(50);
1502 }
1503
d57847dc 1504 return -ETIMEDOUT;
89d44f0a
MD		 1505}
1506
1061c90f 1507static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
89d44f0a
MD		 1508{
1509 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
89d44f0a
MD		 1510 int err;
1511
1512 dev_info(&pdev->dev, "%s was called\n", __func__);
1513
1061c90f 1514 err = mlx5_pci_enable_device(dev);
d57847dc 1515 if (err) {
1061c90f
MHY		 1516 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1517 , __func__, err);
1518 return PCI_ERS_RESULT_DISCONNECT;
1519 }
1520
1521 pci_set_master(pdev);
1522 pci_restore_state(pdev);
5d47f6c8 1523 pci_save_state(pdev);
1061c90f
MHY		 1524
1525 if (wait_vital(pdev)) {
d57847dc 1526 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1061c90f 1527 return PCI_ERS_RESULT_DISCONNECT;
d57847dc 1528 }
89d44f0a 1529
1061c90f
MHY		 1530 return PCI_ERS_RESULT_RECOVERED;
1531}
1532
1061c90f
MHY		 1533static void mlx5_pci_resume(struct pci_dev *pdev)
1534{
1535 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1536 struct mlx5_priv *priv = &dev->priv;
1537 int err;
1538
1539 dev_info(&pdev->dev, "%s was called\n", __func__);
1540
59211bd3 1541 err = mlx5_load_one(dev, priv, false);
89d44f0a
MD		 1542 if (err)
1543 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1544 , __func__, err);
1545 else
1546 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1547}
1548
1549static const struct pci_error_handlers mlx5_err_handler = {
1550 .error_detected = mlx5_pci_err_detected,
1551 .slot_reset = mlx5_pci_slot_reset,
1552 .resume = mlx5_pci_resume
1553};
1554
8812c24d
MD		 1555static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1556{
1557 int ret;
1558
1559 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1560 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1561 return -EOPNOTSUPP;
1562 }
1563
1564 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1565 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1566 return -EAGAIN;
1567 }
1568
d2aa060d
HN		 1569 /* Panic tear down fw command will stop the PCI bus communication
1570 * with the HCA, so the health polll is no longer needed.
1571 */
1572 mlx5_drain_health_wq(dev);
1573 mlx5_stop_health_poll(dev);
1574
8812c24d
MD		 1575 ret = mlx5_cmd_force_teardown_hca(dev);
1576 if (ret) {
1577 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
d2aa060d 1578 mlx5_start_health_poll(dev);
8812c24d
MD		 1579 return ret;
1580 }
1581
1582 mlx5_enter_error_state(dev, true);
1583
1584 return 0;
1585}
1586
5fc7197d
MD		 1587static void shutdown(struct pci_dev *pdev)
1588{
1589 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1590 struct mlx5_priv *priv = &dev->priv;
8812c24d 1591 int err;
5fc7197d
MD		 1592
1593 dev_info(&pdev->dev, "Shutdown was called\n");
8812c24d
MD		 1594 err = mlx5_try_fast_unload(dev);
1595 if (err)
1596 mlx5_unload_one(dev, priv, false);
5fc7197d
MD		 1597 mlx5_pci_disable_device(dev);
1598}
1599
9603b61d 1600static const struct pci_device_id mlx5_core_pci_table[] = {
bbad7c21 1601 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
fc50db98 1602 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
bbad7c21 1603 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
fc50db98 1604 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
bbad7c21 1605 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
fc50db98 1606 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
7092fe86 1607 { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */
64dbbdfe 1608 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
d0dd989f
MD		 1609 { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */
1610 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
1611 { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */
1612 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2e9d3e83
NO		 1613 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
1614 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */
9603b61d
JM		 1615 { 0, }
1616};
1617
1618MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1619
04c0c1ab
MHY		 1620void mlx5_disable_device(struct mlx5_core_dev *dev)
1621{
1622 mlx5_pci_err_detected(dev->pdev, 0);
1623}
1624
1625void mlx5_recover_device(struct mlx5_core_dev *dev)
1626{
1627 mlx5_pci_disable_device(dev);
1628 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1629 mlx5_pci_resume(dev->pdev);
1630}
1631
9603b61d
JM		 1632static struct pci_driver mlx5_core_driver = {
1633 .name = DRIVER_NAME,
1634 .id_table = mlx5_core_pci_table,
1635 .probe = init_one,
89d44f0a 1636 .remove = remove_one,
5fc7197d 1637 .shutdown = shutdown,
fc50db98
EC		 1638 .err_handler = &mlx5_err_handler,
1639 .sriov_configure = mlx5_core_sriov_configure,
9603b61d 1640};
e126ba97 1641
f663ad98
KH		 1642static void mlx5_core_verify_params(void)
1643{
1644 if (prof_sel >= ARRAY_SIZE(profile)) {
1645 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1646 prof_sel,
1647 ARRAY_SIZE(profile) - 1,
1648 MLX5_DEFAULT_PROF);
1649 prof_sel = MLX5_DEFAULT_PROF;
1650 }
1651}
1652
e126ba97
EC		 1653static int __init init(void)
1654{
1655 int err;
1656
8737f818
DJ		 1657 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1658
f663ad98 1659 mlx5_core_verify_params();
e126ba97 1660 mlx5_register_debugfs();
e126ba97 1661
9603b61d
JM		 1662 err = pci_register_driver(&mlx5_core_driver);
1663 if (err)
ac6ea6e8 1664 goto err_debug;
9603b61d 1665
f62b8bb8
AV		 1666#ifdef CONFIG_MLX5_CORE_EN
1667 mlx5e_init();
1668#endif
1669
e126ba97
EC		 1670 return 0;
1671
e126ba97
EC		 1672err_debug:
1673 mlx5_unregister_debugfs();
1674 return err;
1675}
1676
1677static void __exit cleanup(void)
1678{
f62b8bb8
AV		 1679#ifdef CONFIG_MLX5_CORE_EN
1680 mlx5e_cleanup();
1681#endif
9603b61d 1682 pci_unregister_driver(&mlx5_core_driver);
e126ba97
EC		 1683 mlx5_unregister_debugfs();
1684}
1685
1686module_init(init);
1687module_exit(cleanup);
Linux 6.x block layer and io_uring tree(s)