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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
adec640e | 33 | #include <linux/highmem.h> |
e126ba97 EC |
34 | #include <linux/module.h> |
35 | #include <linux/init.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/slab.h> | |
40 | #include <linux/io-mapping.h> | |
db058a18 | 41 | #include <linux/interrupt.h> |
e3297246 | 42 | #include <linux/delay.h> |
e126ba97 EC |
43 | #include <linux/mlx5/driver.h> |
44 | #include <linux/mlx5/cq.h> | |
45 | #include <linux/mlx5/qp.h> | |
e126ba97 | 46 | #include <linux/debugfs.h> |
f66f049f | 47 | #include <linux/kmod.h> |
b775516b | 48 | #include <linux/mlx5/mlx5_ifc.h> |
c85023e1 | 49 | #include <linux/mlx5/vport.h> |
5a7b27eb MG |
50 | #ifdef CONFIG_RFS_ACCEL |
51 | #include <linux/cpu_rmap.h> | |
52 | #endif | |
907af0f0 | 53 | #include <linux/version.h> |
feae9087 | 54 | #include <net/devlink.h> |
e126ba97 | 55 | #include "mlx5_core.h" |
f2f3df55 | 56 | #include "lib/eq.h" |
16d76083 | 57 | #include "fs_core.h" |
eeb66cdb | 58 | #include "lib/mpfs.h" |
073bb189 | 59 | #include "eswitch.h" |
1f28d776 | 60 | #include "devlink.h" |
38b9f903 | 61 | #include "fw_reset.h" |
52ec462e | 62 | #include "lib/mlx5.h" |
5945e1ad | 63 | #include "lib/tout.h" |
e29341fb | 64 | #include "fpga/core.h" |
c6e3b421 | 65 | #include "en_accel/ipsec.h" |
7c39afb3 | 66 | #include "lib/clock.h" |
358aa5ce | 67 | #include "lib/vxlan.h" |
0ccc171e | 68 | #include "lib/geneve.h" |
fadd59fc | 69 | #include "lib/devcom.h" |
b25bbc2f | 70 | #include "lib/pci_vsc.h" |
24406953 | 71 | #include "diag/fw_tracer.h" |
591905ba | 72 | #include "ecpf.h" |
87175120 | 73 | #include "lib/hv_vhca.h" |
12206b17 | 74 | #include "diag/rsc_dump.h" |
f3196bb0 | 75 | #include "sf/vhca_event.h" |
90d010b8 | 76 | #include "sf/dev/dev.h" |
6a327321 | 77 | #include "sf/sf.h" |
3b43190b | 78 | #include "mlx5_irq.h" |
e126ba97 | 79 | |
e126ba97 | 80 | MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); |
048f3143 | 81 | MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) core driver"); |
e126ba97 | 82 | MODULE_LICENSE("Dual BSD/GPL"); |
e126ba97 | 83 | |
f663ad98 KH |
84 | unsigned int mlx5_core_debug_mask; |
85 | module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644); | |
e126ba97 EC |
86 | MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); |
87 | ||
f663ad98 KH |
88 | static unsigned int prof_sel = MLX5_DEFAULT_PROF; |
89 | module_param_named(prof_sel, prof_sel, uint, 0444); | |
9603b61d JM |
90 | MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2"); |
91 | ||
8737f818 | 92 | static u32 sw_owner_id[4]; |
dc402ccc YH |
93 | #define MAX_SW_VHCA_ID (BIT(__mlx5_bit_sz(cmd_hca_cap_2, sw_vhca_id)) - 1) |
94 | static DEFINE_IDA(sw_vhca_ida); | |
8737f818 | 95 | |
f91e6d89 EBE |
96 | enum { |
97 | MLX5_ATOMIC_REQ_MODE_BE = 0x0, | |
98 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, | |
99 | }; | |
100 | ||
f79a609e MS |
101 | #define LOG_MAX_SUPPORTED_QPS 0xff |
102 | ||
9603b61d JM |
103 | static struct mlx5_profile profile[] = { |
104 | [0] = { | |
105 | .mask = 0, | |
106 | }, | |
107 | [1] = { | |
108 | .mask = MLX5_PROF_MASK_QP_SIZE, | |
109 | .log_max_qp = 12, | |
110 | }, | |
111 | [2] = { | |
112 | .mask = MLX5_PROF_MASK_QP_SIZE | | |
113 | MLX5_PROF_MASK_MR_CACHE, | |
f79a609e | 114 | .log_max_qp = LOG_MAX_SUPPORTED_QPS, |
9603b61d JM |
115 | .mr_cache[0] = { |
116 | .size = 500, | |
117 | .limit = 250 | |
118 | }, | |
119 | .mr_cache[1] = { | |
120 | .size = 500, | |
121 | .limit = 250 | |
122 | }, | |
123 | .mr_cache[2] = { | |
124 | .size = 500, | |
125 | .limit = 250 | |
126 | }, | |
127 | .mr_cache[3] = { | |
128 | .size = 500, | |
129 | .limit = 250 | |
130 | }, | |
131 | .mr_cache[4] = { | |
132 | .size = 500, | |
133 | .limit = 250 | |
134 | }, | |
135 | .mr_cache[5] = { | |
136 | .size = 500, | |
137 | .limit = 250 | |
138 | }, | |
139 | .mr_cache[6] = { | |
140 | .size = 500, | |
141 | .limit = 250 | |
142 | }, | |
143 | .mr_cache[7] = { | |
144 | .size = 500, | |
145 | .limit = 250 | |
146 | }, | |
147 | .mr_cache[8] = { | |
148 | .size = 500, | |
149 | .limit = 250 | |
150 | }, | |
151 | .mr_cache[9] = { | |
152 | .size = 500, | |
153 | .limit = 250 | |
154 | }, | |
155 | .mr_cache[10] = { | |
156 | .size = 500, | |
157 | .limit = 250 | |
158 | }, | |
159 | .mr_cache[11] = { | |
160 | .size = 500, | |
161 | .limit = 250 | |
162 | }, | |
163 | .mr_cache[12] = { | |
164 | .size = 64, | |
165 | .limit = 32 | |
166 | }, | |
167 | .mr_cache[13] = { | |
168 | .size = 32, | |
169 | .limit = 16 | |
170 | }, | |
171 | .mr_cache[14] = { | |
172 | .size = 16, | |
173 | .limit = 8 | |
174 | }, | |
175 | .mr_cache[15] = { | |
176 | .size = 8, | |
177 | .limit = 4 | |
178 | }, | |
179 | }, | |
180 | }; | |
e126ba97 | 181 | |
b8a92577 DJ |
182 | static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, |
183 | u32 warn_time_mili) | |
e3297246 | 184 | { |
b8a92577 | 185 | unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili); |
e3297246 | 186 | unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili); |
cdfc6ffb | 187 | u32 fw_initializing; |
e3297246 EC |
188 | int err = 0; |
189 | ||
cdfc6ffb SD |
190 | do { |
191 | fw_initializing = ioread32be(&dev->iseg->initializing); | |
192 | if (!(fw_initializing >> 31)) | |
193 | break; | |
8324a02c GL |
194 | if (time_after(jiffies, end) || |
195 | test_and_clear_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state)) { | |
e3297246 EC |
196 | err = -EBUSY; |
197 | break; | |
198 | } | |
b8a92577 | 199 | if (warn_time_mili && time_after(jiffies, warn)) { |
cdfc6ffb SD |
200 | mlx5_core_warn(dev, "Waiting for FW initialization, timeout abort in %ds (0x%x)\n", |
201 | jiffies_to_msecs(end - warn) / 1000, fw_initializing); | |
b8a92577 DJ |
202 | warn = jiffies + msecs_to_jiffies(warn_time_mili); |
203 | } | |
5945e1ad | 204 | msleep(mlx5_tout_ms(dev, FW_PRE_INIT_WAIT)); |
cdfc6ffb | 205 | } while (true); |
e3297246 EC |
206 | |
207 | return err; | |
208 | } | |
209 | ||
012e50e1 HN |
210 | static void mlx5_set_driver_version(struct mlx5_core_dev *dev) |
211 | { | |
212 | int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in, | |
213 | driver_version); | |
3ac0e69e | 214 | u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; |
012e50e1 HN |
215 | int remaining_size = driver_ver_sz; |
216 | char *string; | |
217 | ||
218 | if (!MLX5_CAP_GEN(dev, driver_version)) | |
219 | return; | |
220 | ||
221 | string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); | |
222 | ||
223 | strncpy(string, "Linux", remaining_size); | |
224 | ||
225 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
226 | strncat(string, ",", remaining_size); | |
227 | ||
228 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
17a7612b | 229 | strncat(string, KBUILD_MODNAME, remaining_size); |
012e50e1 HN |
230 | |
231 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
232 | strncat(string, ",", remaining_size); | |
233 | ||
234 | remaining_size = max_t(int, 0, driver_ver_sz - strlen(string)); | |
907af0f0 LR |
235 | |
236 | snprintf(string + strlen(string), remaining_size, "%u.%u.%u", | |
88a68672 SL |
237 | LINUX_VERSION_MAJOR, LINUX_VERSION_PATCHLEVEL, |
238 | LINUX_VERSION_SUBLEVEL); | |
012e50e1 HN |
239 | |
240 | /*Send the command*/ | |
241 | MLX5_SET(set_driver_version_in, in, opcode, | |
242 | MLX5_CMD_OP_SET_DRIVER_VERSION); | |
243 | ||
3ac0e69e | 244 | mlx5_cmd_exec_in(dev, set_driver_version, in); |
012e50e1 HN |
245 | } |
246 | ||
e126ba97 EC |
247 | static int set_dma_caps(struct pci_dev *pdev) |
248 | { | |
249 | int err; | |
250 | ||
eb9c5c0d | 251 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
e126ba97 | 252 | if (err) { |
1a91de28 | 253 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
eb9c5c0d | 254 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
e126ba97 | 255 | if (err) { |
1a91de28 | 256 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
e126ba97 EC |
257 | return err; |
258 | } | |
259 | } | |
260 | ||
e126ba97 EC |
261 | dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); |
262 | return err; | |
263 | } | |
264 | ||
89d44f0a MD |
265 | static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) |
266 | { | |
267 | struct pci_dev *pdev = dev->pdev; | |
268 | int err = 0; | |
269 | ||
270 | mutex_lock(&dev->pci_status_mutex); | |
271 | if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { | |
272 | err = pci_enable_device(pdev); | |
273 | if (!err) | |
274 | dev->pci_status = MLX5_PCI_STATUS_ENABLED; | |
275 | } | |
276 | mutex_unlock(&dev->pci_status_mutex); | |
277 | ||
278 | return err; | |
279 | } | |
280 | ||
281 | static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) | |
282 | { | |
283 | struct pci_dev *pdev = dev->pdev; | |
284 | ||
285 | mutex_lock(&dev->pci_status_mutex); | |
286 | if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { | |
287 | pci_disable_device(pdev); | |
288 | dev->pci_status = MLX5_PCI_STATUS_DISABLED; | |
289 | } | |
290 | mutex_unlock(&dev->pci_status_mutex); | |
291 | } | |
292 | ||
e126ba97 EC |
293 | static int request_bar(struct pci_dev *pdev) |
294 | { | |
295 | int err = 0; | |
296 | ||
297 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1a91de28 | 298 | dev_err(&pdev->dev, "Missing registers BAR, aborting\n"); |
e126ba97 EC |
299 | return -ENODEV; |
300 | } | |
301 | ||
17a7612b | 302 | err = pci_request_regions(pdev, KBUILD_MODNAME); |
e126ba97 EC |
303 | if (err) |
304 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); | |
305 | ||
306 | return err; | |
307 | } | |
308 | ||
309 | static void release_bar(struct pci_dev *pdev) | |
310 | { | |
311 | pci_release_regions(pdev); | |
312 | } | |
313 | ||
bd10838a | 314 | struct mlx5_reg_host_endianness { |
e126ba97 EC |
315 | u8 he; |
316 | u8 rsvd[15]; | |
317 | }; | |
318 | ||
2974ab6e | 319 | static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) |
c7a08ac7 EC |
320 | { |
321 | switch (size) { | |
322 | case 128: | |
323 | return 0; | |
324 | case 256: | |
325 | return 1; | |
326 | case 512: | |
327 | return 2; | |
328 | case 1024: | |
329 | return 3; | |
330 | case 2048: | |
331 | return 4; | |
332 | case 4096: | |
333 | return 5; | |
334 | default: | |
2974ab6e | 335 | mlx5_core_warn(dev, "invalid pkey table size %d\n", size); |
c7a08ac7 EC |
336 | return 0; |
337 | } | |
338 | } | |
339 | ||
b06e7de8 LR |
340 | static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, |
341 | enum mlx5_cap_type cap_type, | |
342 | enum mlx5_cap_mode cap_mode) | |
c7a08ac7 | 343 | { |
b775516b EC |
344 | u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; |
345 | int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
938fe83c SM |
346 | void *out, *hca_caps; |
347 | u16 opmod = (cap_type << 1) | (cap_mode & 0x01); | |
e126ba97 EC |
348 | int err; |
349 | ||
b775516b EC |
350 | memset(in, 0, sizeof(in)); |
351 | out = kzalloc(out_sz, GFP_KERNEL); | |
c7a08ac7 | 352 | if (!out) |
e126ba97 | 353 | return -ENOMEM; |
938fe83c | 354 | |
b775516b EC |
355 | MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); |
356 | MLX5_SET(query_hca_cap_in, in, op_mod, opmod); | |
3ac0e69e | 357 | err = mlx5_cmd_exec_inout(dev, query_hca_cap, in, out); |
c7a08ac7 | 358 | if (err) { |
938fe83c SM |
359 | mlx5_core_warn(dev, |
360 | "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", | |
361 | cap_type, cap_mode, err); | |
e126ba97 EC |
362 | goto query_ex; |
363 | } | |
c7a08ac7 | 364 | |
938fe83c SM |
365 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); |
366 | ||
367 | switch (cap_mode) { | |
368 | case HCA_CAP_OPMOD_GET_MAX: | |
48f02eef | 369 | memcpy(dev->caps.hca[cap_type]->max, hca_caps, |
938fe83c SM |
370 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
371 | break; | |
372 | case HCA_CAP_OPMOD_GET_CUR: | |
48f02eef | 373 | memcpy(dev->caps.hca[cap_type]->cur, hca_caps, |
938fe83c SM |
374 | MLX5_UN_SZ_BYTES(hca_cap_union)); |
375 | break; | |
376 | default: | |
377 | mlx5_core_warn(dev, | |
378 | "Tried to query dev cap type(%x) with wrong opmode(%x)\n", | |
379 | cap_type, cap_mode); | |
380 | err = -EINVAL; | |
381 | break; | |
382 | } | |
c7a08ac7 EC |
383 | query_ex: |
384 | kfree(out); | |
385 | return err; | |
386 | } | |
387 | ||
b06e7de8 LR |
388 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) |
389 | { | |
390 | int ret; | |
391 | ||
392 | ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); | |
393 | if (ret) | |
394 | return ret; | |
395 | return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); | |
396 | } | |
397 | ||
a2a322f4 | 398 | static int set_caps(struct mlx5_core_dev *dev, void *in, int opmod) |
c7a08ac7 | 399 | { |
b775516b | 400 | MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); |
f91e6d89 | 401 | MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1); |
3ac0e69e | 402 | return mlx5_cmd_exec_in(dev, set_hca_cap, in); |
c7a08ac7 EC |
403 | } |
404 | ||
a2a322f4 | 405 | static int handle_hca_cap_atomic(struct mlx5_core_dev *dev, void *set_ctx) |
f91e6d89 | 406 | { |
f91e6d89 | 407 | void *set_hca_cap; |
f91e6d89 EBE |
408 | int req_endianness; |
409 | int err; | |
410 | ||
a2a322f4 | 411 | if (!MLX5_CAP_GEN(dev, atomic)) |
f91e6d89 | 412 | return 0; |
a2a322f4 LR |
413 | |
414 | err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); | |
415 | if (err) | |
416 | return err; | |
f91e6d89 EBE |
417 | |
418 | req_endianness = | |
419 | MLX5_CAP_ATOMIC(dev, | |
bd10838a | 420 | supported_atomic_req_8B_endianness_mode_1); |
f91e6d89 EBE |
421 | |
422 | if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) | |
423 | return 0; | |
424 | ||
f91e6d89 EBE |
425 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); |
426 | ||
427 | /* Set requestor to host endianness */ | |
bd10838a | 428 | MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode, |
f91e6d89 EBE |
429 | MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); |
430 | ||
a2a322f4 | 431 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC); |
f91e6d89 EBE |
432 | } |
433 | ||
a2a322f4 | 434 | static int handle_hca_cap_odp(struct mlx5_core_dev *dev, void *set_ctx) |
46861e3e | 435 | { |
46861e3e | 436 | void *set_hca_cap; |
fca22e7e | 437 | bool do_set = false; |
46861e3e MS |
438 | int err; |
439 | ||
37b6bb77 LR |
440 | if (!IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) || |
441 | !MLX5_CAP_GEN(dev, pg)) | |
46861e3e MS |
442 | return 0; |
443 | ||
444 | err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); | |
445 | if (err) | |
446 | return err; | |
447 | ||
46861e3e | 448 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); |
48f02eef | 449 | memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ODP]->cur, |
46861e3e MS |
450 | MLX5_ST_SZ_BYTES(odp_cap)); |
451 | ||
fca22e7e MS |
452 | #define ODP_CAP_SET_MAX(dev, field) \ |
453 | do { \ | |
454 | u32 _res = MLX5_CAP_ODP_MAX(dev, field); \ | |
455 | if (_res) { \ | |
456 | do_set = true; \ | |
457 | MLX5_SET(odp_cap, set_hca_cap, field, _res); \ | |
458 | } \ | |
459 | } while (0) | |
460 | ||
461 | ODP_CAP_SET_MAX(dev, ud_odp_caps.srq_receive); | |
462 | ODP_CAP_SET_MAX(dev, rc_odp_caps.srq_receive); | |
463 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.srq_receive); | |
464 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.send); | |
465 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.receive); | |
466 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.write); | |
467 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.read); | |
468 | ODP_CAP_SET_MAX(dev, xrc_odp_caps.atomic); | |
00679b63 MG |
469 | ODP_CAP_SET_MAX(dev, dc_odp_caps.srq_receive); |
470 | ODP_CAP_SET_MAX(dev, dc_odp_caps.send); | |
471 | ODP_CAP_SET_MAX(dev, dc_odp_caps.receive); | |
472 | ODP_CAP_SET_MAX(dev, dc_odp_caps.write); | |
473 | ODP_CAP_SET_MAX(dev, dc_odp_caps.read); | |
474 | ODP_CAP_SET_MAX(dev, dc_odp_caps.atomic); | |
fca22e7e | 475 | |
a2a322f4 LR |
476 | if (!do_set) |
477 | return 0; | |
fca22e7e | 478 | |
a2a322f4 | 479 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ODP); |
46861e3e MS |
480 | } |
481 | ||
8680a60f SD |
482 | static int max_uc_list_get_devlink_param(struct mlx5_core_dev *dev) |
483 | { | |
484 | struct devlink *devlink = priv_to_devlink(dev); | |
485 | union devlink_param_value val; | |
486 | int err; | |
487 | ||
488 | err = devlink_param_driverinit_value_get(devlink, | |
489 | DEVLINK_PARAM_GENERIC_ID_MAX_MACS, | |
490 | &val); | |
491 | if (!err) | |
492 | return val.vu32; | |
493 | mlx5_core_dbg(dev, "Failed to get param. err = %d\n", err); | |
494 | return err; | |
495 | } | |
496 | ||
dc402ccc YH |
497 | static int handle_hca_cap_2(struct mlx5_core_dev *dev, void *set_ctx) |
498 | { | |
499 | void *set_hca_cap; | |
500 | int err; | |
501 | ||
502 | if (!MLX5_CAP_GEN_MAX(dev, hca_cap_2)) | |
503 | return 0; | |
504 | ||
505 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2); | |
506 | if (err) | |
507 | return err; | |
508 | ||
509 | if (!MLX5_CAP_GEN_2_MAX(dev, sw_vhca_id_valid) || | |
510 | !(dev->priv.sw_vhca_id > 0)) | |
511 | return 0; | |
512 | ||
513 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, | |
514 | capability); | |
515 | memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL_2]->cur, | |
516 | MLX5_ST_SZ_BYTES(cmd_hca_cap_2)); | |
517 | MLX5_SET(cmd_hca_cap_2, set_hca_cap, sw_vhca_id_valid, 1); | |
518 | ||
519 | return set_caps(dev, set_ctx, MLX5_CAP_GENERAL_2); | |
520 | } | |
521 | ||
a2a322f4 | 522 | static int handle_hca_cap(struct mlx5_core_dev *dev, void *set_ctx) |
c7a08ac7 | 523 | { |
3410fbcd | 524 | struct mlx5_profile *prof = &dev->profile; |
938fe83c | 525 | void *set_hca_cap; |
8680a60f | 526 | int max_uc_list; |
a2a322f4 | 527 | int err; |
e126ba97 | 528 | |
b06e7de8 | 529 | err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); |
e126ba97 | 530 | if (err) |
a2a322f4 | 531 | return err; |
e126ba97 | 532 | |
938fe83c SM |
533 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, |
534 | capability); | |
48f02eef | 535 | memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_GENERAL]->cur, |
938fe83c SM |
536 | MLX5_ST_SZ_BYTES(cmd_hca_cap)); |
537 | ||
538 | mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", | |
707c4602 | 539 | mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), |
938fe83c | 540 | 128); |
c7a08ac7 | 541 | /* we limit the size of the pkey table to 128 entries for now */ |
938fe83c | 542 | MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, |
2974ab6e | 543 | to_fw_pkey_sz(dev, 128)); |
c7a08ac7 | 544 | |
883371c4 | 545 | /* Check log_max_qp from HCA caps to set in current profile */ |
f79a609e | 546 | if (prof->log_max_qp == LOG_MAX_SUPPORTED_QPS) { |
a6e9085d | 547 | prof->log_max_qp = min_t(u8, 18, MLX5_CAP_GEN_MAX(dev, log_max_qp)); |
f79a609e | 548 | } else if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < prof->log_max_qp) { |
883371c4 | 549 | mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n", |
3410fbcd | 550 | prof->log_max_qp, |
883371c4 | 551 | MLX5_CAP_GEN_MAX(dev, log_max_qp)); |
3410fbcd | 552 | prof->log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp); |
883371c4 | 553 | } |
c7a08ac7 | 554 | if (prof->mask & MLX5_PROF_MASK_QP_SIZE) |
938fe83c SM |
555 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, |
556 | prof->log_max_qp); | |
c7a08ac7 | 557 | |
938fe83c SM |
558 | /* disable cmdif checksum */ |
559 | MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); | |
c7a08ac7 | 560 | |
91828bd8 MD |
561 | /* Enable 4K UAR only when HCA supports it and page size is bigger |
562 | * than 4K. | |
563 | */ | |
564 | if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) | |
f502d834 EC |
565 | MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); |
566 | ||
fe1e1876 CS |
567 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); |
568 | ||
f32f5bd2 DJ |
569 | if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte)) |
570 | MLX5_SET(cmd_hca_cap, | |
571 | set_hca_cap, | |
572 | cache_line_128byte, | |
c67f100e | 573 | cache_line_size() >= 128 ? 1 : 0); |
f32f5bd2 | 574 | |
dd44572a MS |
575 | if (MLX5_CAP_GEN_MAX(dev, dct)) |
576 | MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1); | |
577 | ||
e7f4d0bc MS |
578 | if (MLX5_CAP_GEN_MAX(dev, pci_sync_for_fw_update_event)) |
579 | MLX5_SET(cmd_hca_cap, set_hca_cap, pci_sync_for_fw_update_event, 1); | |
580 | ||
c4b76d8d DJ |
581 | if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports)) |
582 | MLX5_SET(cmd_hca_cap, | |
583 | set_hca_cap, | |
584 | num_vhca_ports, | |
585 | MLX5_CAP_GEN_MAX(dev, num_vhca_ports)); | |
586 | ||
c6168161 EBE |
587 | if (MLX5_CAP_GEN_MAX(dev, release_all_pages)) |
588 | MLX5_SET(cmd_hca_cap, set_hca_cap, release_all_pages, 1); | |
589 | ||
4dca6509 MG |
590 | if (MLX5_CAP_GEN_MAX(dev, mkey_by_name)) |
591 | MLX5_SET(cmd_hca_cap, set_hca_cap, mkey_by_name, 1); | |
592 | ||
f3196bb0 PP |
593 | mlx5_vhca_state_cap_handle(dev, set_hca_cap); |
594 | ||
604774ad LR |
595 | if (MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)) |
596 | MLX5_SET(cmd_hca_cap, set_hca_cap, num_total_dynamic_vf_msix, | |
597 | MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix)); | |
598 | ||
fbfa97b4 SD |
599 | if (MLX5_CAP_GEN(dev, roce_rw_supported)) |
600 | MLX5_SET(cmd_hca_cap, set_hca_cap, roce, mlx5_is_roce_init_enabled(dev)); | |
601 | ||
8680a60f SD |
602 | max_uc_list = max_uc_list_get_devlink_param(dev); |
603 | if (max_uc_list > 0) | |
604 | MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_current_uc_list, | |
605 | ilog2(max_uc_list)); | |
606 | ||
a2a322f4 | 607 | return set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE); |
e126ba97 | 608 | } |
c7a08ac7 | 609 | |
fbfa97b4 SD |
610 | /* Cached MLX5_CAP_GEN(dev, roce) can be out of sync this early in the |
611 | * boot process. | |
612 | * In case RoCE cap is writable in FW and user/devlink requested to change the | |
613 | * cap, we are yet to query the final state of the above cap. | |
614 | * Hence, the need for this function. | |
615 | * | |
616 | * Returns | |
617 | * True: | |
618 | * 1) RoCE cap is read only in FW and already disabled | |
619 | * OR: | |
620 | * 2) RoCE cap is writable in FW and user/devlink requested it off. | |
621 | * | |
622 | * In any other case, return False. | |
623 | */ | |
624 | static bool is_roce_fw_disabled(struct mlx5_core_dev *dev) | |
625 | { | |
626 | return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_init_enabled(dev)) || | |
627 | (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); | |
628 | } | |
629 | ||
59e9e8e4 MZ |
630 | static int handle_hca_cap_roce(struct mlx5_core_dev *dev, void *set_ctx) |
631 | { | |
632 | void *set_hca_cap; | |
633 | int err; | |
634 | ||
fbfa97b4 | 635 | if (is_roce_fw_disabled(dev)) |
59e9e8e4 MZ |
636 | return 0; |
637 | ||
638 | err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); | |
639 | if (err) | |
640 | return err; | |
641 | ||
642 | if (MLX5_CAP_ROCE(dev, sw_r_roce_src_udp_port) || | |
643 | !MLX5_CAP_ROCE_MAX(dev, sw_r_roce_src_udp_port)) | |
644 | return 0; | |
645 | ||
646 | set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); | |
48f02eef | 647 | memcpy(set_hca_cap, dev->caps.hca[MLX5_CAP_ROCE]->cur, |
59e9e8e4 MZ |
648 | MLX5_ST_SZ_BYTES(roce_cap)); |
649 | MLX5_SET(roce_cap, set_hca_cap, sw_r_roce_src_udp_port, 1); | |
650 | ||
651 | err = set_caps(dev, set_ctx, MLX5_SET_HCA_CAP_OP_MOD_ROCE); | |
e126ba97 EC |
652 | return err; |
653 | } | |
654 | ||
37b6bb77 LR |
655 | static int set_hca_cap(struct mlx5_core_dev *dev) |
656 | { | |
a2a322f4 LR |
657 | int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); |
658 | void *set_ctx; | |
37b6bb77 LR |
659 | int err; |
660 | ||
a2a322f4 LR |
661 | set_ctx = kzalloc(set_sz, GFP_KERNEL); |
662 | if (!set_ctx) | |
663 | return -ENOMEM; | |
664 | ||
665 | err = handle_hca_cap(dev, set_ctx); | |
37b6bb77 | 666 | if (err) { |
98a8e6fc | 667 | mlx5_core_err(dev, "handle_hca_cap failed\n"); |
37b6bb77 LR |
668 | goto out; |
669 | } | |
670 | ||
a2a322f4 LR |
671 | memset(set_ctx, 0, set_sz); |
672 | err = handle_hca_cap_atomic(dev, set_ctx); | |
37b6bb77 | 673 | if (err) { |
98a8e6fc | 674 | mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); |
37b6bb77 LR |
675 | goto out; |
676 | } | |
677 | ||
a2a322f4 LR |
678 | memset(set_ctx, 0, set_sz); |
679 | err = handle_hca_cap_odp(dev, set_ctx); | |
37b6bb77 | 680 | if (err) { |
98a8e6fc | 681 | mlx5_core_err(dev, "handle_hca_cap_odp failed\n"); |
37b6bb77 LR |
682 | goto out; |
683 | } | |
684 | ||
59e9e8e4 MZ |
685 | memset(set_ctx, 0, set_sz); |
686 | err = handle_hca_cap_roce(dev, set_ctx); | |
687 | if (err) { | |
688 | mlx5_core_err(dev, "handle_hca_cap_roce failed\n"); | |
689 | goto out; | |
690 | } | |
691 | ||
dc402ccc YH |
692 | memset(set_ctx, 0, set_sz); |
693 | err = handle_hca_cap_2(dev, set_ctx); | |
694 | if (err) { | |
695 | mlx5_core_err(dev, "handle_hca_cap_2 failed\n"); | |
696 | goto out; | |
697 | } | |
698 | ||
37b6bb77 | 699 | out: |
a2a322f4 | 700 | kfree(set_ctx); |
37b6bb77 LR |
701 | return err; |
702 | } | |
703 | ||
e126ba97 EC |
704 | static int set_hca_ctrl(struct mlx5_core_dev *dev) |
705 | { | |
bd10838a OG |
706 | struct mlx5_reg_host_endianness he_in; |
707 | struct mlx5_reg_host_endianness he_out; | |
e126ba97 EC |
708 | int err; |
709 | ||
fc50db98 EC |
710 | if (!mlx5_core_is_pf(dev)) |
711 | return 0; | |
712 | ||
e126ba97 EC |
713 | memset(&he_in, 0, sizeof(he_in)); |
714 | he_in.he = MLX5_SET_HOST_ENDIANNESS; | |
715 | err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), | |
716 | &he_out, sizeof(he_out), | |
717 | MLX5_REG_HOST_ENDIANNESS, 0, 1); | |
718 | return err; | |
719 | } | |
720 | ||
c85023e1 HN |
721 | static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) |
722 | { | |
723 | int ret = 0; | |
724 | ||
725 | /* Disable local_lb by default */ | |
8978cc92 | 726 | if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) |
c85023e1 HN |
727 | ret = mlx5_nic_vport_update_local_lb(dev, false); |
728 | ||
729 | return ret; | |
730 | } | |
731 | ||
0b107106 | 732 | int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 733 | { |
3ac0e69e | 734 | u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; |
cd23b14b | 735 | |
0b107106 EC |
736 | MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); |
737 | MLX5_SET(enable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
738 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
739 | dev->caps.embedded_cpu); | |
3ac0e69e | 740 | return mlx5_cmd_exec_in(dev, enable_hca, in); |
cd23b14b EC |
741 | } |
742 | ||
0b107106 | 743 | int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id) |
cd23b14b | 744 | { |
3ac0e69e | 745 | u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; |
cd23b14b | 746 | |
0b107106 EC |
747 | MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); |
748 | MLX5_SET(disable_hca_in, in, function_id, func_id); | |
22e939a9 BW |
749 | MLX5_SET(enable_hca_in, in, embedded_cpu_function, |
750 | dev->caps.embedded_cpu); | |
3ac0e69e | 751 | return mlx5_cmd_exec_in(dev, disable_hca, in); |
cd23b14b EC |
752 | } |
753 | ||
f62b8bb8 AV |
754 | static int mlx5_core_set_issi(struct mlx5_core_dev *dev) |
755 | { | |
3ac0e69e LR |
756 | u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {}; |
757 | u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {}; | |
f62b8bb8 | 758 | u32 sup_issi; |
c4f287c4 | 759 | int err; |
f62b8bb8 AV |
760 | |
761 | MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); | |
3ac0e69e | 762 | err = mlx5_cmd_exec_inout(dev, query_issi, query_in, query_out); |
f62b8bb8 | 763 | if (err) { |
605bef00 SM |
764 | u32 syndrome = MLX5_GET(query_issi_out, query_out, syndrome); |
765 | u8 status = MLX5_GET(query_issi_out, query_out, status); | |
c4f287c4 | 766 | |
f9c14e46 KH |
767 | if (!status || syndrome == MLX5_DRIVER_SYND) { |
768 | mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n", | |
769 | err, status, syndrome); | |
770 | return err; | |
f62b8bb8 AV |
771 | } |
772 | ||
f9c14e46 KH |
773 | mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n"); |
774 | dev->issi = 0; | |
775 | return 0; | |
f62b8bb8 AV |
776 | } |
777 | ||
778 | sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); | |
779 | ||
780 | if (sup_issi & (1 << 1)) { | |
3ac0e69e | 781 | u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {}; |
f62b8bb8 AV |
782 | |
783 | MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); | |
784 | MLX5_SET(set_issi_in, set_in, current_issi, 1); | |
3ac0e69e | 785 | err = mlx5_cmd_exec_in(dev, set_issi, set_in); |
f62b8bb8 | 786 | if (err) { |
f9c14e46 KH |
787 | mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n", |
788 | err); | |
f62b8bb8 AV |
789 | return err; |
790 | } | |
791 | ||
792 | dev->issi = 1; | |
793 | ||
794 | return 0; | |
e74a1db0 | 795 | } else if (sup_issi & (1 << 0) || !sup_issi) { |
f62b8bb8 AV |
796 | return 0; |
797 | } | |
798 | ||
9eb78923 | 799 | return -EOPNOTSUPP; |
f62b8bb8 | 800 | } |
f62b8bb8 | 801 | |
11f3b84d SM |
802 | static int mlx5_pci_init(struct mlx5_core_dev *dev, struct pci_dev *pdev, |
803 | const struct pci_device_id *id) | |
a31208b1 | 804 | { |
a31208b1 | 805 | int err = 0; |
e126ba97 | 806 | |
d22663ed | 807 | mutex_init(&dev->pci_status_mutex); |
11f3b84d | 808 | pci_set_drvdata(dev->pdev, dev); |
311c7c71 | 809 | |
aa8106f1 | 810 | dev->bar_addr = pci_resource_start(pdev, 0); |
311c7c71 | 811 | |
89d44f0a | 812 | err = mlx5_pci_enable_device(dev); |
e126ba97 | 813 | if (err) { |
98a8e6fc | 814 | mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); |
11f3b84d | 815 | return err; |
e126ba97 EC |
816 | } |
817 | ||
818 | err = request_bar(pdev); | |
819 | if (err) { | |
98a8e6fc | 820 | mlx5_core_err(dev, "error requesting BARs, aborting\n"); |
e126ba97 EC |
821 | goto err_disable; |
822 | } | |
823 | ||
824 | pci_set_master(pdev); | |
825 | ||
826 | err = set_dma_caps(pdev); | |
827 | if (err) { | |
98a8e6fc | 828 | mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); |
e126ba97 EC |
829 | goto err_clr_master; |
830 | } | |
831 | ||
ce4eee53 MG |
832 | if (pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP32) && |
833 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP64) && | |
834 | pci_enable_atomic_ops_to_root(pdev, PCI_EXP_DEVCAP2_ATOMIC_COMP128)) | |
835 | mlx5_core_dbg(dev, "Enabling pci atomics failed\n"); | |
836 | ||
aa8106f1 | 837 | dev->iseg_base = dev->bar_addr; |
e126ba97 EC |
838 | dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); |
839 | if (!dev->iseg) { | |
840 | err = -ENOMEM; | |
98a8e6fc | 841 | mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); |
e126ba97 EC |
842 | goto err_clr_master; |
843 | } | |
a31208b1 | 844 | |
b25bbc2f | 845 | mlx5_pci_vsc_init(dev); |
c89da067 | 846 | dev->caps.embedded_cpu = mlx5_read_embedded_cpu(dev); |
a31208b1 MD |
847 | return 0; |
848 | ||
849 | err_clr_master: | |
850 | pci_clear_master(dev->pdev); | |
851 | release_bar(dev->pdev); | |
852 | err_disable: | |
89d44f0a | 853 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
854 | return err; |
855 | } | |
856 | ||
868bc06b | 857 | static void mlx5_pci_close(struct mlx5_core_dev *dev) |
a31208b1 | 858 | { |
42ea9f1b SD |
859 | /* health work might still be active, and it needs pci bar in |
860 | * order to know the NIC state. Therefore, drain the health WQ | |
861 | * before removing the pci bars | |
862 | */ | |
863 | mlx5_drain_health_wq(dev); | |
a31208b1 MD |
864 | iounmap(dev->iseg); |
865 | pci_clear_master(dev->pdev); | |
866 | release_bar(dev->pdev); | |
89d44f0a | 867 | mlx5_pci_disable_device(dev); |
a31208b1 MD |
868 | } |
869 | ||
868bc06b | 870 | static int mlx5_init_once(struct mlx5_core_dev *dev) |
59211bd3 | 871 | { |
59211bd3 MHY |
872 | int err; |
873 | ||
868bc06b SM |
874 | dev->priv.devcom = mlx5_devcom_register_device(dev); |
875 | if (IS_ERR(dev->priv.devcom)) | |
98a8e6fc HN |
876 | mlx5_core_err(dev, "failed to register with devcom (0x%p)\n", |
877 | dev->priv.devcom); | |
fadd59fc | 878 | |
59211bd3 MHY |
879 | err = mlx5_query_board_id(dev); |
880 | if (err) { | |
98a8e6fc | 881 | mlx5_core_err(dev, "query board id failed\n"); |
fadd59fc | 882 | goto err_devcom; |
59211bd3 MHY |
883 | } |
884 | ||
561aa15a YA |
885 | err = mlx5_irq_table_init(dev); |
886 | if (err) { | |
887 | mlx5_core_err(dev, "failed to initialize irq table\n"); | |
888 | goto err_devcom; | |
889 | } | |
890 | ||
f2f3df55 | 891 | err = mlx5_eq_table_init(dev); |
59211bd3 | 892 | if (err) { |
98a8e6fc | 893 | mlx5_core_err(dev, "failed to initialize eq\n"); |
561aa15a | 894 | goto err_irq_cleanup; |
59211bd3 MHY |
895 | } |
896 | ||
69c1280b SM |
897 | err = mlx5_events_init(dev); |
898 | if (err) { | |
98a8e6fc | 899 | mlx5_core_err(dev, "failed to initialize events\n"); |
69c1280b SM |
900 | goto err_eq_cleanup; |
901 | } | |
902 | ||
38b9f903 MS |
903 | err = mlx5_fw_reset_init(dev); |
904 | if (err) { | |
905 | mlx5_core_err(dev, "failed to initialize fw reset events\n"); | |
906 | goto err_events_cleanup; | |
907 | } | |
908 | ||
9f818c8a | 909 | mlx5_cq_debugfs_init(dev); |
59211bd3 | 910 | |
52ec462e IT |
911 | mlx5_init_reserved_gids(dev); |
912 | ||
7c39afb3 FD |
913 | mlx5_init_clock(dev); |
914 | ||
358aa5ce | 915 | dev->vxlan = mlx5_vxlan_create(dev); |
0ccc171e | 916 | dev->geneve = mlx5_geneve_create(dev); |
358aa5ce | 917 | |
59211bd3 MHY |
918 | err = mlx5_init_rl_table(dev); |
919 | if (err) { | |
98a8e6fc | 920 | mlx5_core_err(dev, "Failed to init rate limiting\n"); |
59211bd3 MHY |
921 | goto err_tables_cleanup; |
922 | } | |
923 | ||
eeb66cdb SM |
924 | err = mlx5_mpfs_init(dev); |
925 | if (err) { | |
98a8e6fc | 926 | mlx5_core_err(dev, "Failed to init l2 table %d\n", err); |
eeb66cdb SM |
927 | goto err_rl_cleanup; |
928 | } | |
929 | ||
86eec50b | 930 | err = mlx5_sriov_init(dev); |
c2d6e31a | 931 | if (err) { |
86eec50b | 932 | mlx5_core_err(dev, "Failed to init sriov %d\n", err); |
eeb66cdb | 933 | goto err_mpfs_cleanup; |
c2d6e31a | 934 | } |
c2d6e31a | 935 | |
86eec50b | 936 | err = mlx5_eswitch_init(dev); |
c2d6e31a | 937 | if (err) { |
86eec50b BW |
938 | mlx5_core_err(dev, "Failed to init eswitch %d\n", err); |
939 | goto err_sriov_cleanup; | |
c2d6e31a MHY |
940 | } |
941 | ||
9410733c IT |
942 | err = mlx5_fpga_init(dev); |
943 | if (err) { | |
98a8e6fc | 944 | mlx5_core_err(dev, "Failed to init fpga device %d\n", err); |
86eec50b | 945 | goto err_eswitch_cleanup; |
9410733c IT |
946 | } |
947 | ||
f3196bb0 PP |
948 | err = mlx5_vhca_event_init(dev); |
949 | if (err) { | |
950 | mlx5_core_err(dev, "Failed to init vhca event notifier %d\n", err); | |
951 | goto err_fpga_cleanup; | |
952 | } | |
953 | ||
8f010541 PP |
954 | err = mlx5_sf_hw_table_init(dev); |
955 | if (err) { | |
956 | mlx5_core_err(dev, "Failed to init SF HW table %d\n", err); | |
957 | goto err_sf_hw_table_cleanup; | |
958 | } | |
959 | ||
960 | err = mlx5_sf_table_init(dev); | |
961 | if (err) { | |
962 | mlx5_core_err(dev, "Failed to init SF table %d\n", err); | |
963 | goto err_sf_table_cleanup; | |
964 | } | |
965 | ||
b3388697 SD |
966 | err = mlx5_fs_core_alloc(dev); |
967 | if (err) { | |
968 | mlx5_core_err(dev, "Failed to alloc flow steering\n"); | |
969 | goto err_fs; | |
970 | } | |
971 | ||
c9b9dcb4 AL |
972 | dev->dm = mlx5_dm_create(dev); |
973 | if (IS_ERR(dev->dm)) | |
974 | mlx5_core_warn(dev, "Failed to init device memory%d\n", err); | |
975 | ||
24406953 | 976 | dev->tracer = mlx5_fw_tracer_create(dev); |
87175120 | 977 | dev->hv_vhca = mlx5_hv_vhca_create(dev); |
12206b17 | 978 | dev->rsc_dump = mlx5_rsc_dump_create(dev); |
24406953 | 979 | |
59211bd3 MHY |
980 | return 0; |
981 | ||
b3388697 SD |
982 | err_fs: |
983 | mlx5_sf_table_cleanup(dev); | |
8f010541 PP |
984 | err_sf_table_cleanup: |
985 | mlx5_sf_hw_table_cleanup(dev); | |
986 | err_sf_hw_table_cleanup: | |
987 | mlx5_vhca_event_cleanup(dev); | |
f3196bb0 PP |
988 | err_fpga_cleanup: |
989 | mlx5_fpga_cleanup(dev); | |
c2d6e31a | 990 | err_eswitch_cleanup: |
c2d6e31a | 991 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
86eec50b BW |
992 | err_sriov_cleanup: |
993 | mlx5_sriov_cleanup(dev); | |
eeb66cdb | 994 | err_mpfs_cleanup: |
eeb66cdb | 995 | mlx5_mpfs_cleanup(dev); |
c2d6e31a | 996 | err_rl_cleanup: |
c2d6e31a | 997 | mlx5_cleanup_rl_table(dev); |
59211bd3 | 998 | err_tables_cleanup: |
0ccc171e | 999 | mlx5_geneve_destroy(dev->geneve); |
358aa5ce | 1000 | mlx5_vxlan_destroy(dev->vxlan); |
02d92f79 | 1001 | mlx5_cq_debugfs_cleanup(dev); |
38b9f903 MS |
1002 | mlx5_fw_reset_cleanup(dev); |
1003 | err_events_cleanup: | |
69c1280b | 1004 | mlx5_events_cleanup(dev); |
59211bd3 | 1005 | err_eq_cleanup: |
f2f3df55 | 1006 | mlx5_eq_table_cleanup(dev); |
561aa15a YA |
1007 | err_irq_cleanup: |
1008 | mlx5_irq_table_cleanup(dev); | |
fadd59fc AH |
1009 | err_devcom: |
1010 | mlx5_devcom_unregister_device(dev->priv.devcom); | |
59211bd3 | 1011 | |
59211bd3 MHY |
1012 | return err; |
1013 | } | |
1014 | ||
1015 | static void mlx5_cleanup_once(struct mlx5_core_dev *dev) | |
1016 | { | |
12206b17 | 1017 | mlx5_rsc_dump_destroy(dev); |
87175120 | 1018 | mlx5_hv_vhca_destroy(dev->hv_vhca); |
24406953 | 1019 | mlx5_fw_tracer_destroy(dev->tracer); |
c9b9dcb4 | 1020 | mlx5_dm_cleanup(dev); |
b3388697 | 1021 | mlx5_fs_core_free(dev); |
8f010541 PP |
1022 | mlx5_sf_table_cleanup(dev); |
1023 | mlx5_sf_hw_table_cleanup(dev); | |
f3196bb0 | 1024 | mlx5_vhca_event_cleanup(dev); |
9410733c | 1025 | mlx5_fpga_cleanup(dev); |
c2d6e31a | 1026 | mlx5_eswitch_cleanup(dev->priv.eswitch); |
86eec50b | 1027 | mlx5_sriov_cleanup(dev); |
eeb66cdb | 1028 | mlx5_mpfs_cleanup(dev); |
59211bd3 | 1029 | mlx5_cleanup_rl_table(dev); |
0ccc171e | 1030 | mlx5_geneve_destroy(dev->geneve); |
358aa5ce | 1031 | mlx5_vxlan_destroy(dev->vxlan); |
7c39afb3 | 1032 | mlx5_cleanup_clock(dev); |
52ec462e | 1033 | mlx5_cleanup_reserved_gids(dev); |
02d92f79 | 1034 | mlx5_cq_debugfs_cleanup(dev); |
38b9f903 | 1035 | mlx5_fw_reset_cleanup(dev); |
69c1280b | 1036 | mlx5_events_cleanup(dev); |
f2f3df55 | 1037 | mlx5_eq_table_cleanup(dev); |
561aa15a | 1038 | mlx5_irq_table_cleanup(dev); |
fadd59fc | 1039 | mlx5_devcom_unregister_device(dev->priv.devcom); |
59211bd3 MHY |
1040 | } |
1041 | ||
37ca95e6 | 1042 | static int mlx5_function_setup(struct mlx5_core_dev *dev, u64 timeout) |
a31208b1 | 1043 | { |
a31208b1 MD |
1044 | int err; |
1045 | ||
98a8e6fc HN |
1046 | mlx5_core_info(dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev), |
1047 | fw_rev_min(dev), fw_rev_sub(dev)); | |
e126ba97 | 1048 | |
00c6bcb0 TG |
1049 | /* Only PFs hold the relevant PCIe information for this query */ |
1050 | if (mlx5_core_is_pf(dev)) | |
1051 | pcie_print_link_status(dev->pdev); | |
1052 | ||
6c780a02 EC |
1053 | /* wait for firmware to accept initialization segments configurations |
1054 | */ | |
37ca95e6 | 1055 | err = wait_fw_init(dev, timeout, |
5945e1ad | 1056 | mlx5_tout_ms(dev, FW_PRE_INIT_WARN_MESSAGE_INTERVAL)); |
6c780a02 | 1057 | if (err) { |
5945e1ad | 1058 | mlx5_core_err(dev, "Firmware over %llu MS in pre-initializing state, aborting\n", |
37ca95e6 | 1059 | timeout); |
76091b0f | 1060 | return err; |
6c780a02 EC |
1061 | } |
1062 | ||
e126ba97 EC |
1063 | err = mlx5_cmd_init(dev); |
1064 | if (err) { | |
98a8e6fc | 1065 | mlx5_core_err(dev, "Failed initializing command interface, aborting\n"); |
76091b0f | 1066 | return err; |
e126ba97 EC |
1067 | } |
1068 | ||
5945e1ad AT |
1069 | mlx5_tout_query_iseg(dev); |
1070 | ||
1071 | err = wait_fw_init(dev, mlx5_tout_ms(dev, FW_INIT), 0); | |
e3297246 | 1072 | if (err) { |
5945e1ad AT |
1073 | mlx5_core_err(dev, "Firmware over %llu MS in initializing state, aborting\n", |
1074 | mlx5_tout_ms(dev, FW_INIT)); | |
55378a23 | 1075 | goto err_cmd_cleanup; |
e3297246 EC |
1076 | } |
1077 | ||
f7936ddd EBE |
1078 | mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_UP); |
1079 | ||
0b107106 | 1080 | err = mlx5_core_enable_hca(dev, 0); |
cd23b14b | 1081 | if (err) { |
98a8e6fc | 1082 | mlx5_core_err(dev, "enable hca failed\n"); |
59211bd3 | 1083 | goto err_cmd_cleanup; |
cd23b14b EC |
1084 | } |
1085 | ||
f62b8bb8 AV |
1086 | err = mlx5_core_set_issi(dev); |
1087 | if (err) { | |
98a8e6fc | 1088 | mlx5_core_err(dev, "failed to set issi\n"); |
f62b8bb8 AV |
1089 | goto err_disable_hca; |
1090 | } | |
f62b8bb8 | 1091 | |
cd23b14b EC |
1092 | err = mlx5_satisfy_startup_pages(dev, 1); |
1093 | if (err) { | |
98a8e6fc | 1094 | mlx5_core_err(dev, "failed to allocate boot pages\n"); |
cd23b14b EC |
1095 | goto err_disable_hca; |
1096 | } | |
1097 | ||
32def412 AT |
1098 | err = mlx5_tout_query_dtor(dev); |
1099 | if (err) { | |
1100 | mlx5_core_err(dev, "failed to read dtor\n"); | |
1101 | goto reclaim_boot_pages; | |
1102 | } | |
1103 | ||
e126ba97 EC |
1104 | err = set_hca_ctrl(dev); |
1105 | if (err) { | |
98a8e6fc | 1106 | mlx5_core_err(dev, "set_hca_ctrl failed\n"); |
cd23b14b | 1107 | goto reclaim_boot_pages; |
e126ba97 EC |
1108 | } |
1109 | ||
37b6bb77 | 1110 | err = set_hca_cap(dev); |
f91e6d89 | 1111 | if (err) { |
98a8e6fc | 1112 | mlx5_core_err(dev, "set_hca_cap failed\n"); |
46861e3e MS |
1113 | goto reclaim_boot_pages; |
1114 | } | |
1115 | ||
cd23b14b | 1116 | err = mlx5_satisfy_startup_pages(dev, 0); |
e126ba97 | 1117 | if (err) { |
98a8e6fc | 1118 | mlx5_core_err(dev, "failed to allocate init pages\n"); |
cd23b14b | 1119 | goto reclaim_boot_pages; |
e126ba97 EC |
1120 | } |
1121 | ||
8737f818 | 1122 | err = mlx5_cmd_init_hca(dev, sw_owner_id); |
e126ba97 | 1123 | if (err) { |
98a8e6fc | 1124 | mlx5_core_err(dev, "init hca failed\n"); |
0cf53c12 | 1125 | goto reclaim_boot_pages; |
e126ba97 EC |
1126 | } |
1127 | ||
012e50e1 HN |
1128 | mlx5_set_driver_version(dev); |
1129 | ||
bba1574c DJ |
1130 | err = mlx5_query_hca_caps(dev); |
1131 | if (err) { | |
98a8e6fc | 1132 | mlx5_core_err(dev, "query hca failed\n"); |
502e82b9 | 1133 | goto reclaim_boot_pages; |
bba1574c DJ |
1134 | } |
1135 | ||
502e82b9 AL |
1136 | mlx5_start_health_poll(dev); |
1137 | ||
e161105e SM |
1138 | return 0; |
1139 | ||
e161105e SM |
1140 | reclaim_boot_pages: |
1141 | mlx5_reclaim_startup_pages(dev); | |
1142 | err_disable_hca: | |
1143 | mlx5_core_disable_hca(dev, 0); | |
1144 | err_cmd_cleanup: | |
f7936ddd | 1145 | mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); |
e161105e SM |
1146 | mlx5_cmd_cleanup(dev); |
1147 | ||
1148 | return err; | |
1149 | } | |
1150 | ||
1151 | static int mlx5_function_teardown(struct mlx5_core_dev *dev, bool boot) | |
1152 | { | |
1153 | int err; | |
1154 | ||
1155 | mlx5_stop_health_poll(dev, boot); | |
1156 | err = mlx5_cmd_teardown_hca(dev); | |
1157 | if (err) { | |
98a8e6fc | 1158 | mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); |
e161105e | 1159 | return err; |
e126ba97 | 1160 | } |
e161105e SM |
1161 | mlx5_reclaim_startup_pages(dev); |
1162 | mlx5_core_disable_hca(dev, 0); | |
f7936ddd | 1163 | mlx5_cmd_set_state(dev, MLX5_CMDIF_STATE_DOWN); |
e161105e SM |
1164 | mlx5_cmd_cleanup(dev); |
1165 | ||
1166 | return 0; | |
1167 | } | |
1168 | ||
a80d1b68 | 1169 | static int mlx5_load(struct mlx5_core_dev *dev) |
e161105e | 1170 | { |
e161105e | 1171 | int err; |
e126ba97 | 1172 | |
01187175 | 1173 | dev->priv.uar = mlx5_get_uars_page(dev); |
72f36be0 | 1174 | if (IS_ERR(dev->priv.uar)) { |
98a8e6fc | 1175 | mlx5_core_err(dev, "Failed allocating uar, aborting\n"); |
72f36be0 | 1176 | err = PTR_ERR(dev->priv.uar); |
a80d1b68 | 1177 | return err; |
e126ba97 EC |
1178 | } |
1179 | ||
69c1280b | 1180 | mlx5_events_start(dev); |
0cf53c12 SM |
1181 | mlx5_pagealloc_start(dev); |
1182 | ||
e1706e62 YA |
1183 | err = mlx5_irq_table_create(dev); |
1184 | if (err) { | |
1185 | mlx5_core_err(dev, "Failed to alloc IRQs\n"); | |
1186 | goto err_irq_table; | |
1187 | } | |
1188 | ||
c8e21b3b | 1189 | err = mlx5_eq_table_create(dev); |
e126ba97 | 1190 | if (err) { |
98a8e6fc | 1191 | mlx5_core_err(dev, "Failed to create EQs\n"); |
c8e21b3b | 1192 | goto err_eq_table; |
e126ba97 EC |
1193 | } |
1194 | ||
24406953 FD |
1195 | err = mlx5_fw_tracer_init(dev->tracer); |
1196 | if (err) { | |
f62eb932 AL |
1197 | mlx5_core_err(dev, "Failed to init FW tracer %d\n", err); |
1198 | mlx5_fw_tracer_destroy(dev->tracer); | |
1199 | dev->tracer = NULL; | |
24406953 FD |
1200 | } |
1201 | ||
38b9f903 | 1202 | mlx5_fw_reset_events_start(dev); |
87175120 EBE |
1203 | mlx5_hv_vhca_init(dev->hv_vhca); |
1204 | ||
12206b17 AL |
1205 | err = mlx5_rsc_dump_init(dev); |
1206 | if (err) { | |
f62eb932 AL |
1207 | mlx5_core_err(dev, "Failed to init Resource dump %d\n", err); |
1208 | mlx5_rsc_dump_destroy(dev); | |
1209 | dev->rsc_dump = NULL; | |
12206b17 AL |
1210 | } |
1211 | ||
04e87170 MB |
1212 | err = mlx5_fpga_device_start(dev); |
1213 | if (err) { | |
98a8e6fc | 1214 | mlx5_core_err(dev, "fpga device start failed %d\n", err); |
04e87170 MB |
1215 | goto err_fpga_start; |
1216 | } | |
1217 | ||
b3388697 | 1218 | err = mlx5_fs_core_init(dev); |
59211bd3 | 1219 | if (err) { |
98a8e6fc | 1220 | mlx5_core_err(dev, "Failed to init flow steering\n"); |
c85023e1 | 1221 | goto err_fs; |
59211bd3 | 1222 | } |
e126ba97 | 1223 | |
c85023e1 | 1224 | err = mlx5_core_set_hca_defaults(dev); |
86d722ad | 1225 | if (err) { |
98a8e6fc | 1226 | mlx5_core_err(dev, "Failed to set hca defaults\n"); |
94a4b841 | 1227 | goto err_set_hca; |
86d722ad | 1228 | } |
1466cc5b | 1229 | |
f3196bb0 PP |
1230 | mlx5_vhca_event_start(dev); |
1231 | ||
6a327321 PP |
1232 | err = mlx5_sf_hw_table_create(dev); |
1233 | if (err) { | |
1234 | mlx5_core_err(dev, "sf table create failed %d\n", err); | |
1235 | goto err_vhca; | |
1236 | } | |
1237 | ||
22e939a9 BW |
1238 | err = mlx5_ec_init(dev); |
1239 | if (err) { | |
98a8e6fc | 1240 | mlx5_core_err(dev, "Failed to init embedded CPU\n"); |
22e939a9 BW |
1241 | goto err_ec; |
1242 | } | |
1243 | ||
cac1eb2c | 1244 | mlx5_lag_add_mdev(dev); |
5bef709d PP |
1245 | err = mlx5_sriov_attach(dev); |
1246 | if (err) { | |
1247 | mlx5_core_err(dev, "sriov init failed %d\n", err); | |
1248 | goto err_sriov; | |
1249 | } | |
1250 | ||
90d010b8 PP |
1251 | mlx5_sf_dev_table_create(dev); |
1252 | ||
e126ba97 EC |
1253 | return 0; |
1254 | ||
59211bd3 | 1255 | err_sriov: |
cac1eb2c | 1256 | mlx5_lag_remove_mdev(dev); |
5bef709d PP |
1257 | mlx5_ec_cleanup(dev); |
1258 | err_ec: | |
6a327321 PP |
1259 | mlx5_sf_hw_table_destroy(dev); |
1260 | err_vhca: | |
f3196bb0 | 1261 | mlx5_vhca_event_stop(dev); |
94a4b841 | 1262 | err_set_hca: |
b3388697 | 1263 | mlx5_fs_core_cleanup(dev); |
86d722ad | 1264 | err_fs: |
04e87170 | 1265 | mlx5_fpga_device_stop(dev); |
04e87170 | 1266 | err_fpga_start: |
12206b17 | 1267 | mlx5_rsc_dump_cleanup(dev); |
87175120 | 1268 | mlx5_hv_vhca_cleanup(dev->hv_vhca); |
38b9f903 | 1269 | mlx5_fw_reset_events_stop(dev); |
24406953 | 1270 | mlx5_fw_tracer_cleanup(dev->tracer); |
c8e21b3b | 1271 | mlx5_eq_table_destroy(dev); |
c8e21b3b | 1272 | err_eq_table: |
e1706e62 YA |
1273 | mlx5_irq_table_destroy(dev); |
1274 | err_irq_table: | |
0cf53c12 | 1275 | mlx5_pagealloc_stop(dev); |
69c1280b | 1276 | mlx5_events_stop(dev); |
868bc06b | 1277 | mlx5_put_uars_page(dev, dev->priv.uar); |
a80d1b68 SM |
1278 | return err; |
1279 | } | |
e126ba97 | 1280 | |
a80d1b68 SM |
1281 | static void mlx5_unload(struct mlx5_core_dev *dev) |
1282 | { | |
90d010b8 | 1283 | mlx5_sf_dev_table_destroy(dev); |
a80d1b68 | 1284 | mlx5_sriov_detach(dev); |
f019679e | 1285 | mlx5_eswitch_disable(dev->priv.eswitch); |
cac1eb2c | 1286 | mlx5_lag_remove_mdev(dev); |
5bef709d | 1287 | mlx5_ec_cleanup(dev); |
6a327321 | 1288 | mlx5_sf_hw_table_destroy(dev); |
f3196bb0 | 1289 | mlx5_vhca_event_stop(dev); |
b3388697 | 1290 | mlx5_fs_core_cleanup(dev); |
a80d1b68 | 1291 | mlx5_fpga_device_stop(dev); |
12206b17 | 1292 | mlx5_rsc_dump_cleanup(dev); |
87175120 | 1293 | mlx5_hv_vhca_cleanup(dev->hv_vhca); |
38b9f903 | 1294 | mlx5_fw_reset_events_stop(dev); |
a80d1b68 SM |
1295 | mlx5_fw_tracer_cleanup(dev->tracer); |
1296 | mlx5_eq_table_destroy(dev); | |
e1706e62 | 1297 | mlx5_irq_table_destroy(dev); |
a80d1b68 SM |
1298 | mlx5_pagealloc_stop(dev); |
1299 | mlx5_events_stop(dev); | |
1300 | mlx5_put_uars_page(dev, dev->priv.uar); | |
1301 | } | |
59211bd3 | 1302 | |
6dea2f7e | 1303 | int mlx5_init_one(struct mlx5_core_dev *dev) |
a80d1b68 | 1304 | { |
84a433a4 | 1305 | struct devlink *devlink = priv_to_devlink(dev); |
a80d1b68 SM |
1306 | int err = 0; |
1307 | ||
84a433a4 | 1308 | devl_lock(devlink); |
a80d1b68 | 1309 | mutex_lock(&dev->intf_state_mutex); |
a80d1b68 | 1310 | dev->state = MLX5_DEVICE_STATE_UP; |
e126ba97 | 1311 | |
37ca95e6 | 1312 | err = mlx5_function_setup(dev, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); |
a80d1b68 | 1313 | if (err) |
4f7400d5 | 1314 | goto err_function; |
e126ba97 | 1315 | |
6dea2f7e LR |
1316 | err = mlx5_init_once(dev); |
1317 | if (err) { | |
1318 | mlx5_core_err(dev, "sw objs init failed\n"); | |
1319 | goto function_teardown; | |
a80d1b68 | 1320 | } |
cd23b14b | 1321 | |
a80d1b68 SM |
1322 | err = mlx5_load(dev); |
1323 | if (err) | |
1324 | goto err_load; | |
e126ba97 | 1325 | |
98f91c45 PP |
1326 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
1327 | ||
919d13a7 | 1328 | err = mlx5_devlink_register(priv_to_devlink(dev)); |
6dea2f7e LR |
1329 | if (err) |
1330 | goto err_devlink_reg; | |
e126ba97 | 1331 | |
6dea2f7e | 1332 | err = mlx5_register_device(dev); |
a925b5e3 LR |
1333 | if (err) |
1334 | goto err_register; | |
1335 | ||
4162f58b | 1336 | mutex_unlock(&dev->intf_state_mutex); |
84a433a4 | 1337 | devl_unlock(devlink); |
4162f58b | 1338 | return 0; |
a80d1b68 | 1339 | |
a925b5e3 | 1340 | err_register: |
6dea2f7e | 1341 | mlx5_devlink_unregister(priv_to_devlink(dev)); |
a6f3b623 | 1342 | err_devlink_reg: |
98f91c45 | 1343 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
a80d1b68 SM |
1344 | mlx5_unload(dev); |
1345 | err_load: | |
6dea2f7e | 1346 | mlx5_cleanup_once(dev); |
e161105e | 1347 | function_teardown: |
6dea2f7e | 1348 | mlx5_function_teardown(dev, true); |
4f7400d5 | 1349 | err_function: |
89d44f0a MD |
1350 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; |
1351 | mutex_unlock(&dev->intf_state_mutex); | |
84a433a4 | 1352 | devl_unlock(devlink); |
e126ba97 EC |
1353 | return err; |
1354 | } | |
e126ba97 | 1355 | |
6dea2f7e | 1356 | void mlx5_uninit_one(struct mlx5_core_dev *dev) |
e126ba97 | 1357 | { |
84a433a4 MS |
1358 | struct devlink *devlink = priv_to_devlink(dev); |
1359 | ||
1360 | devl_lock(devlink); | |
98f91c45 PP |
1361 | mutex_lock(&dev->intf_state_mutex); |
1362 | ||
6dea2f7e LR |
1363 | mlx5_unregister_device(dev); |
1364 | mlx5_devlink_unregister(priv_to_devlink(dev)); | |
689a248d | 1365 | |
b3cb5388 | 1366 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { |
98a8e6fc HN |
1367 | mlx5_core_warn(dev, "%s: interface is down, NOP\n", |
1368 | __func__); | |
6dea2f7e | 1369 | mlx5_cleanup_once(dev); |
89d44f0a MD |
1370 | goto out; |
1371 | } | |
6b6adee3 | 1372 | |
9ade8c7c | 1373 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
6dea2f7e LR |
1374 | mlx5_unload(dev); |
1375 | mlx5_cleanup_once(dev); | |
1376 | mlx5_function_teardown(dev, true); | |
1377 | out: | |
1378 | mutex_unlock(&dev->intf_state_mutex); | |
84a433a4 | 1379 | devl_unlock(devlink); |
6dea2f7e LR |
1380 | } |
1381 | ||
84a433a4 | 1382 | int mlx5_load_one_devl_locked(struct mlx5_core_dev *dev, bool recovery) |
6dea2f7e LR |
1383 | { |
1384 | int err = 0; | |
37ca95e6 | 1385 | u64 timeout; |
6dea2f7e | 1386 | |
84a433a4 | 1387 | devl_assert_locked(priv_to_devlink(dev)); |
6dea2f7e LR |
1388 | mutex_lock(&dev->intf_state_mutex); |
1389 | if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { | |
1390 | mlx5_core_warn(dev, "interface is up, NOP\n"); | |
1391 | goto out; | |
1392 | } | |
1393 | /* remove any previous indication of internal error */ | |
1394 | dev->state = MLX5_DEVICE_STATE_UP; | |
1395 | ||
37ca95e6 GL |
1396 | if (recovery) |
1397 | timeout = mlx5_tout_ms(dev, FW_PRE_INIT_ON_RECOVERY_TIMEOUT); | |
1398 | else | |
1399 | timeout = mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT); | |
1400 | err = mlx5_function_setup(dev, timeout); | |
6dea2f7e LR |
1401 | if (err) |
1402 | goto err_function; | |
1403 | ||
1404 | err = mlx5_load(dev); | |
1405 | if (err) | |
1406 | goto err_load; | |
1407 | ||
1408 | set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
9ade8c7c | 1409 | |
6dea2f7e LR |
1410 | err = mlx5_attach_device(dev); |
1411 | if (err) | |
1412 | goto err_attach; | |
1413 | ||
1414 | mutex_unlock(&dev->intf_state_mutex); | |
1415 | return 0; | |
1416 | ||
1417 | err_attach: | |
1418 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); | |
a80d1b68 | 1419 | mlx5_unload(dev); |
6dea2f7e LR |
1420 | err_load: |
1421 | mlx5_function_teardown(dev, false); | |
1422 | err_function: | |
1423 | dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; | |
1424 | out: | |
1425 | mutex_unlock(&dev->intf_state_mutex); | |
1426 | return err; | |
1427 | } | |
a80d1b68 | 1428 | |
84a433a4 | 1429 | int mlx5_load_one(struct mlx5_core_dev *dev, bool recovery) |
6dea2f7e | 1430 | { |
84a433a4 MS |
1431 | struct devlink *devlink = priv_to_devlink(dev); |
1432 | int ret; | |
1433 | ||
1434 | devl_lock(devlink); | |
1435 | ret = mlx5_load_one_devl_locked(dev, recovery); | |
1436 | devl_unlock(devlink); | |
1437 | return ret; | |
1438 | } | |
1439 | ||
1440 | void mlx5_unload_one_devl_locked(struct mlx5_core_dev *dev) | |
1441 | { | |
1442 | devl_assert_locked(priv_to_devlink(dev)); | |
6dea2f7e LR |
1443 | mutex_lock(&dev->intf_state_mutex); |
1444 | ||
1445 | mlx5_detach_device(dev); | |
1446 | ||
1447 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { | |
1448 | mlx5_core_warn(dev, "%s: interface is down, NOP\n", | |
1449 | __func__); | |
1450 | goto out; | |
1451 | } | |
9603b61d | 1452 | |
6dea2f7e LR |
1453 | clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); |
1454 | mlx5_unload(dev); | |
1455 | mlx5_function_teardown(dev, false); | |
ac6ea6e8 | 1456 | out: |
89d44f0a | 1457 | mutex_unlock(&dev->intf_state_mutex); |
9603b61d | 1458 | } |
64613d94 | 1459 | |
84a433a4 MS |
1460 | void mlx5_unload_one(struct mlx5_core_dev *dev) |
1461 | { | |
1462 | struct devlink *devlink = priv_to_devlink(dev); | |
1463 | ||
1464 | devl_lock(devlink); | |
1465 | mlx5_unload_one_devl_locked(dev); | |
1466 | devl_unlock(devlink); | |
1467 | } | |
1468 | ||
48f02eef PP |
1469 | static const int types[] = { |
1470 | MLX5_CAP_GENERAL, | |
1471 | MLX5_CAP_GENERAL_2, | |
1472 | MLX5_CAP_ETHERNET_OFFLOADS, | |
1473 | MLX5_CAP_IPOIB_ENHANCED_OFFLOADS, | |
1474 | MLX5_CAP_ODP, | |
1475 | MLX5_CAP_ATOMIC, | |
1476 | MLX5_CAP_ROCE, | |
1477 | MLX5_CAP_IPOIB_OFFLOADS, | |
1478 | MLX5_CAP_FLOW_TABLE, | |
1479 | MLX5_CAP_ESWITCH_FLOW_TABLE, | |
1480 | MLX5_CAP_ESWITCH, | |
1481 | MLX5_CAP_VECTOR_CALC, | |
1482 | MLX5_CAP_QOS, | |
1483 | MLX5_CAP_DEBUG, | |
1484 | MLX5_CAP_DEV_MEM, | |
1485 | MLX5_CAP_DEV_EVENT, | |
1486 | MLX5_CAP_TLS, | |
1487 | MLX5_CAP_VDPA_EMULATION, | |
1488 | MLX5_CAP_IPSEC, | |
425a563a | 1489 | MLX5_CAP_PORT_SELECTION, |
7025329d | 1490 | MLX5_CAP_DEV_SHAMPO, |
48f02eef PP |
1491 | }; |
1492 | ||
1493 | static void mlx5_hca_caps_free(struct mlx5_core_dev *dev) | |
1494 | { | |
1495 | int type; | |
1496 | int i; | |
1497 | ||
1498 | for (i = 0; i < ARRAY_SIZE(types); i++) { | |
1499 | type = types[i]; | |
1500 | kfree(dev->caps.hca[type]); | |
1501 | } | |
1502 | } | |
1503 | ||
1504 | static int mlx5_hca_caps_alloc(struct mlx5_core_dev *dev) | |
1505 | { | |
1506 | struct mlx5_hca_cap *cap; | |
1507 | int type; | |
1508 | int i; | |
1509 | ||
1510 | for (i = 0; i < ARRAY_SIZE(types); i++) { | |
1511 | cap = kzalloc(sizeof(*cap), GFP_KERNEL); | |
1512 | if (!cap) | |
1513 | goto err; | |
1514 | type = types[i]; | |
1515 | dev->caps.hca[type] = cap; | |
1516 | } | |
1517 | ||
1518 | return 0; | |
1519 | ||
1520 | err: | |
1521 | mlx5_hca_caps_free(dev); | |
1522 | return -ENOMEM; | |
1523 | } | |
1524 | ||
1958fc2f | 1525 | int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) |
9603b61d | 1526 | { |
11f3b84d | 1527 | struct mlx5_priv *priv = &dev->priv; |
9603b61d JM |
1528 | int err; |
1529 | ||
3410fbcd | 1530 | memcpy(&dev->profile, &profile[profile_idx], sizeof(dev->profile)); |
364d1798 EC |
1531 | INIT_LIST_HEAD(&priv->ctx_list); |
1532 | spin_lock_init(&priv->ctx_lock); | |
89d44f0a | 1533 | mutex_init(&dev->intf_state_mutex); |
d9aaed83 | 1534 | |
01187175 EC |
1535 | mutex_init(&priv->bfregs.reg_head.lock); |
1536 | mutex_init(&priv->bfregs.wc_head.lock); | |
1537 | INIT_LIST_HEAD(&priv->bfregs.reg_head.list); | |
1538 | INIT_LIST_HEAD(&priv->bfregs.wc_head.list); | |
1539 | ||
11f3b84d SM |
1540 | mutex_init(&priv->alloc_mutex); |
1541 | mutex_init(&priv->pgdir_mutex); | |
1542 | INIT_LIST_HEAD(&priv->pgdir_list); | |
11f3b84d | 1543 | |
44f66ac9 | 1544 | priv->numa_node = dev_to_node(mlx5_core_dma_dev(dev)); |
66771a1c MS |
1545 | priv->dbg.dbg_root = debugfs_create_dir(dev_name(dev->device), |
1546 | mlx5_debugfs_root); | |
3d347b1b AL |
1547 | INIT_LIST_HEAD(&priv->traps); |
1548 | ||
76091b0f AT |
1549 | err = mlx5_tout_init(dev); |
1550 | if (err) { | |
1551 | mlx5_core_err(dev, "Failed initializing timeouts, aborting\n"); | |
1552 | goto err_timeout_init; | |
1553 | } | |
1554 | ||
ac6ea6e8 | 1555 | err = mlx5_health_init(dev); |
52c368dc SM |
1556 | if (err) |
1557 | goto err_health_init; | |
ac6ea6e8 | 1558 | |
0cf53c12 SM |
1559 | err = mlx5_pagealloc_init(dev); |
1560 | if (err) | |
1561 | goto err_pagealloc_init; | |
59211bd3 | 1562 | |
a925b5e3 LR |
1563 | err = mlx5_adev_init(dev); |
1564 | if (err) | |
1565 | goto err_adev_init; | |
1566 | ||
48f02eef PP |
1567 | err = mlx5_hca_caps_alloc(dev); |
1568 | if (err) | |
1569 | goto err_hca_caps; | |
1570 | ||
dc402ccc YH |
1571 | /* The conjunction of sw_vhca_id with sw_owner_id will be a global |
1572 | * unique id per function which uses mlx5_core. | |
1573 | * Those values are supplied to FW as part of the init HCA command to | |
1574 | * be used by both driver and FW when it's applicable. | |
1575 | */ | |
1576 | dev->priv.sw_vhca_id = ida_alloc_range(&sw_vhca_ida, 1, | |
1577 | MAX_SW_VHCA_ID, | |
1578 | GFP_KERNEL); | |
1579 | if (dev->priv.sw_vhca_id < 0) | |
1580 | mlx5_core_err(dev, "failed to allocate sw_vhca_id, err=%d\n", | |
1581 | dev->priv.sw_vhca_id); | |
1582 | ||
11f3b84d | 1583 | return 0; |
52c368dc | 1584 | |
48f02eef PP |
1585 | err_hca_caps: |
1586 | mlx5_adev_cleanup(dev); | |
a925b5e3 LR |
1587 | err_adev_init: |
1588 | mlx5_pagealloc_cleanup(dev); | |
52c368dc SM |
1589 | err_pagealloc_init: |
1590 | mlx5_health_cleanup(dev); | |
1591 | err_health_init: | |
76091b0f AT |
1592 | mlx5_tout_cleanup(dev); |
1593 | err_timeout_init: | |
66771a1c | 1594 | debugfs_remove(dev->priv.dbg.dbg_root); |
810cbb25 PP |
1595 | mutex_destroy(&priv->pgdir_mutex); |
1596 | mutex_destroy(&priv->alloc_mutex); | |
1597 | mutex_destroy(&priv->bfregs.wc_head.lock); | |
1598 | mutex_destroy(&priv->bfregs.reg_head.lock); | |
1599 | mutex_destroy(&dev->intf_state_mutex); | |
52c368dc | 1600 | return err; |
11f3b84d SM |
1601 | } |
1602 | ||
1958fc2f | 1603 | void mlx5_mdev_uninit(struct mlx5_core_dev *dev) |
11f3b84d | 1604 | { |
810cbb25 PP |
1605 | struct mlx5_priv *priv = &dev->priv; |
1606 | ||
dc402ccc YH |
1607 | if (priv->sw_vhca_id > 0) |
1608 | ida_free(&sw_vhca_ida, dev->priv.sw_vhca_id); | |
1609 | ||
48f02eef | 1610 | mlx5_hca_caps_free(dev); |
a925b5e3 | 1611 | mlx5_adev_cleanup(dev); |
52c368dc SM |
1612 | mlx5_pagealloc_cleanup(dev); |
1613 | mlx5_health_cleanup(dev); | |
76091b0f | 1614 | mlx5_tout_cleanup(dev); |
66771a1c | 1615 | debugfs_remove_recursive(dev->priv.dbg.dbg_root); |
810cbb25 PP |
1616 | mutex_destroy(&priv->pgdir_mutex); |
1617 | mutex_destroy(&priv->alloc_mutex); | |
1618 | mutex_destroy(&priv->bfregs.wc_head.lock); | |
1619 | mutex_destroy(&priv->bfregs.reg_head.lock); | |
1620 | mutex_destroy(&dev->intf_state_mutex); | |
11f3b84d SM |
1621 | } |
1622 | ||
6dea2f7e | 1623 | static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) |
9603b61d JM |
1624 | { |
1625 | struct mlx5_core_dev *dev; | |
feae9087 | 1626 | struct devlink *devlink; |
9603b61d JM |
1627 | int err; |
1628 | ||
919d13a7 | 1629 | devlink = mlx5_devlink_alloc(&pdev->dev); |
feae9087 | 1630 | if (!devlink) { |
1f28d776 | 1631 | dev_err(&pdev->dev, "devlink alloc failed\n"); |
9603b61d JM |
1632 | return -ENOMEM; |
1633 | } | |
feae9087 OG |
1634 | |
1635 | dev = devlink_priv(devlink); | |
27b942fb PP |
1636 | dev->device = &pdev->dev; |
1637 | dev->pdev = pdev; | |
9603b61d | 1638 | |
386e75af HN |
1639 | dev->coredev_type = id->driver_data & MLX5_PCI_DEV_IS_VF ? |
1640 | MLX5_COREDEV_VF : MLX5_COREDEV_PF; | |
1641 | ||
a925b5e3 | 1642 | dev->priv.adev_idx = mlx5_adev_idx_alloc(); |
4d8be211 LR |
1643 | if (dev->priv.adev_idx < 0) { |
1644 | err = dev->priv.adev_idx; | |
1645 | goto adev_init_err; | |
1646 | } | |
a925b5e3 | 1647 | |
27b942fb | 1648 | err = mlx5_mdev_init(dev, prof_sel); |
11f3b84d SM |
1649 | if (err) |
1650 | goto mdev_init_err; | |
01187175 | 1651 | |
11f3b84d | 1652 | err = mlx5_pci_init(dev, pdev, id); |
9603b61d | 1653 | if (err) { |
98a8e6fc HN |
1654 | mlx5_core_err(dev, "mlx5_pci_init failed with error code %d\n", |
1655 | err); | |
11f3b84d | 1656 | goto pci_init_err; |
9603b61d JM |
1657 | } |
1658 | ||
6dea2f7e | 1659 | err = mlx5_init_one(dev); |
9603b61d | 1660 | if (err) { |
6dea2f7e | 1661 | mlx5_core_err(dev, "mlx5_init_one failed with error code %d\n", |
98a8e6fc | 1662 | err); |
6dea2f7e | 1663 | goto err_init_one; |
9603b61d | 1664 | } |
59211bd3 | 1665 | |
8b9d8baa AV |
1666 | err = mlx5_crdump_enable(dev); |
1667 | if (err) | |
1668 | dev_err(&pdev->dev, "mlx5_crdump_enable failed with error code %d\n", err); | |
1669 | ||
5d47f6c8 | 1670 | pci_save_state(pdev); |
64ea2d0e | 1671 | devlink_register(devlink); |
9603b61d JM |
1672 | return 0; |
1673 | ||
6dea2f7e | 1674 | err_init_one: |
868bc06b | 1675 | mlx5_pci_close(dev); |
11f3b84d SM |
1676 | pci_init_err: |
1677 | mlx5_mdev_uninit(dev); | |
1678 | mdev_init_err: | |
a925b5e3 | 1679 | mlx5_adev_idx_free(dev->priv.adev_idx); |
4d8be211 | 1680 | adev_init_err: |
1f28d776 | 1681 | mlx5_devlink_free(devlink); |
a31208b1 | 1682 | |
9603b61d JM |
1683 | return err; |
1684 | } | |
a31208b1 | 1685 | |
9603b61d JM |
1686 | static void remove_one(struct pci_dev *pdev) |
1687 | { | |
1688 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
feae9087 | 1689 | struct devlink *devlink = priv_to_devlink(dev); |
9603b61d | 1690 | |
16d42d31 SD |
1691 | /* mlx5_drain_fw_reset() is using devlink APIs. Hence, we must drain |
1692 | * fw_reset before unregistering the devlink. | |
1693 | */ | |
1694 | mlx5_drain_fw_reset(dev); | |
8324a02c | 1695 | set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); |
64ea2d0e | 1696 | devlink_unregister(devlink); |
143a41d7 | 1697 | mlx5_sriov_disable(pdev); |
8b9d8baa | 1698 | mlx5_crdump_disable(dev); |
41798df9 | 1699 | mlx5_drain_health_wq(dev); |
6dea2f7e | 1700 | mlx5_uninit_one(dev); |
868bc06b | 1701 | mlx5_pci_close(dev); |
11f3b84d | 1702 | mlx5_mdev_uninit(dev); |
a925b5e3 | 1703 | mlx5_adev_idx_free(dev->priv.adev_idx); |
1f28d776 | 1704 | mlx5_devlink_free(devlink); |
9603b61d JM |
1705 | } |
1706 | ||
fad1783a SM |
1707 | #define mlx5_pci_trace(dev, fmt, ...) ({ \ |
1708 | struct mlx5_core_dev *__dev = (dev); \ | |
1709 | mlx5_core_info(__dev, "%s Device state = %d health sensors: %d pci_status: %d. " fmt, \ | |
1710 | __func__, __dev->state, mlx5_health_check_fatal_sensors(__dev), \ | |
1711 | __dev->pci_status, ##__VA_ARGS__); \ | |
1712 | }) | |
1713 | ||
1714 | static const char *result2str(enum pci_ers_result result) | |
1715 | { | |
1716 | return result == PCI_ERS_RESULT_NEED_RESET ? "need reset" : | |
1717 | result == PCI_ERS_RESULT_DISCONNECT ? "disconnect" : | |
1718 | result == PCI_ERS_RESULT_RECOVERED ? "recovered" : | |
1719 | "unknown"; | |
1720 | } | |
1721 | ||
89d44f0a MD |
1722 | static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, |
1723 | pci_channel_state_t state) | |
1724 | { | |
1725 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
fad1783a | 1726 | enum pci_ers_result res; |
89d44f0a | 1727 | |
fad1783a | 1728 | mlx5_pci_trace(dev, "Enter, pci channel state = %d\n", state); |
04c0c1ab | 1729 | |
8812c24d | 1730 | mlx5_enter_error_state(dev, false); |
3e5b72ac | 1731 | mlx5_error_sw_reset(dev); |
6dea2f7e | 1732 | mlx5_unload_one(dev); |
b3bd076f MS |
1733 | mlx5_drain_health_wq(dev); |
1734 | mlx5_pci_disable_device(dev); | |
05ac2c0b | 1735 | |
fad1783a | 1736 | res = state == pci_channel_io_perm_failure ? |
89d44f0a | 1737 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; |
fad1783a SM |
1738 | |
1739 | mlx5_pci_trace(dev, "Exit, result = %d, %s\n", res, result2str(res)); | |
1740 | return res; | |
89d44f0a MD |
1741 | } |
1742 | ||
d57847dc DJ |
1743 | /* wait for the device to show vital signs by waiting |
1744 | * for the health counter to start counting. | |
89d44f0a | 1745 | */ |
d57847dc | 1746 | static int wait_vital(struct pci_dev *pdev) |
89d44f0a MD |
1747 | { |
1748 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1749 | struct mlx5_core_health *health = &dev->priv.health; | |
1750 | const int niter = 100; | |
d57847dc | 1751 | u32 last_count = 0; |
89d44f0a | 1752 | u32 count; |
89d44f0a MD |
1753 | int i; |
1754 | ||
89d44f0a MD |
1755 | for (i = 0; i < niter; i++) { |
1756 | count = ioread32be(health->health_counter); | |
1757 | if (count && count != 0xffffffff) { | |
d57847dc | 1758 | if (last_count && last_count != count) { |
98a8e6fc HN |
1759 | mlx5_core_info(dev, |
1760 | "wait vital counter value 0x%x after %d iterations\n", | |
1761 | count, i); | |
d57847dc DJ |
1762 | return 0; |
1763 | } | |
1764 | last_count = count; | |
89d44f0a MD |
1765 | } |
1766 | msleep(50); | |
1767 | } | |
1768 | ||
d57847dc | 1769 | return -ETIMEDOUT; |
89d44f0a MD |
1770 | } |
1771 | ||
1061c90f | 1772 | static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) |
89d44f0a | 1773 | { |
fad1783a | 1774 | enum pci_ers_result res = PCI_ERS_RESULT_DISCONNECT; |
89d44f0a | 1775 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); |
89d44f0a MD |
1776 | int err; |
1777 | ||
fad1783a | 1778 | mlx5_pci_trace(dev, "Enter\n"); |
89d44f0a | 1779 | |
1061c90f | 1780 | err = mlx5_pci_enable_device(dev); |
d57847dc | 1781 | if (err) { |
98a8e6fc HN |
1782 | mlx5_core_err(dev, "%s: mlx5_pci_enable_device failed with error code: %d\n", |
1783 | __func__, err); | |
fad1783a | 1784 | goto out; |
1061c90f MHY |
1785 | } |
1786 | ||
1787 | pci_set_master(pdev); | |
1788 | pci_restore_state(pdev); | |
5d47f6c8 | 1789 | pci_save_state(pdev); |
1061c90f | 1790 | |
fad1783a SM |
1791 | err = wait_vital(pdev); |
1792 | if (err) { | |
1793 | mlx5_core_err(dev, "%s: wait vital failed with error code: %d\n", | |
1794 | __func__, err); | |
1795 | goto out; | |
d57847dc | 1796 | } |
89d44f0a | 1797 | |
fad1783a SM |
1798 | res = PCI_ERS_RESULT_RECOVERED; |
1799 | out: | |
1800 | mlx5_pci_trace(dev, "Exit, err = %d, result = %d, %s\n", err, res, result2str(res)); | |
1801 | return res; | |
1061c90f MHY |
1802 | } |
1803 | ||
1061c90f MHY |
1804 | static void mlx5_pci_resume(struct pci_dev *pdev) |
1805 | { | |
1806 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1061c90f MHY |
1807 | int err; |
1808 | ||
fad1783a | 1809 | mlx5_pci_trace(dev, "Enter, loading driver..\n"); |
1061c90f | 1810 | |
37ca95e6 | 1811 | err = mlx5_load_one(dev, false); |
fad1783a SM |
1812 | |
1813 | mlx5_pci_trace(dev, "Done, err = %d, device %s\n", err, | |
1814 | !err ? "recovered" : "Failed"); | |
89d44f0a MD |
1815 | } |
1816 | ||
1817 | static const struct pci_error_handlers mlx5_err_handler = { | |
1818 | .error_detected = mlx5_pci_err_detected, | |
1819 | .slot_reset = mlx5_pci_slot_reset, | |
1820 | .resume = mlx5_pci_resume | |
1821 | }; | |
1822 | ||
8812c24d MD |
1823 | static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) |
1824 | { | |
fcd29ad1 FD |
1825 | bool fast_teardown = false, force_teardown = false; |
1826 | int ret = 1; | |
1827 | ||
1828 | fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); | |
1829 | force_teardown = MLX5_CAP_GEN(dev, force_teardown); | |
1830 | ||
1831 | mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); | |
1832 | mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); | |
8812c24d | 1833 | |
fcd29ad1 | 1834 | if (!fast_teardown && !force_teardown) |
8812c24d | 1835 | return -EOPNOTSUPP; |
8812c24d MD |
1836 | |
1837 | if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { | |
1838 | mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); | |
1839 | return -EAGAIN; | |
1840 | } | |
1841 | ||
d2aa060d | 1842 | /* Panic tear down fw command will stop the PCI bus communication |
b0ea505b | 1843 | * with the HCA, so the health poll is no longer needed. |
d2aa060d HN |
1844 | */ |
1845 | mlx5_drain_health_wq(dev); | |
76d5581c | 1846 | mlx5_stop_health_poll(dev, false); |
d2aa060d | 1847 | |
fcd29ad1 FD |
1848 | ret = mlx5_cmd_fast_teardown_hca(dev); |
1849 | if (!ret) | |
1850 | goto succeed; | |
1851 | ||
8812c24d | 1852 | ret = mlx5_cmd_force_teardown_hca(dev); |
fcd29ad1 FD |
1853 | if (!ret) |
1854 | goto succeed; | |
1855 | ||
1856 | mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret); | |
1857 | mlx5_start_health_poll(dev); | |
1858 | return ret; | |
8812c24d | 1859 | |
fcd29ad1 | 1860 | succeed: |
8812c24d MD |
1861 | mlx5_enter_error_state(dev, true); |
1862 | ||
1ef903bf DJ |
1863 | /* Some platforms requiring freeing the IRQ's in the shutdown |
1864 | * flow. If they aren't freed they can't be allocated after | |
1865 | * kexec. There is no need to cleanup the mlx5_core software | |
1866 | * contexts. | |
1867 | */ | |
1ef903bf DJ |
1868 | mlx5_core_eq_free_irqs(dev); |
1869 | ||
8812c24d MD |
1870 | return 0; |
1871 | } | |
1872 | ||
5fc7197d MD |
1873 | static void shutdown(struct pci_dev *pdev) |
1874 | { | |
1875 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
8812c24d | 1876 | int err; |
5fc7197d | 1877 | |
98a8e6fc | 1878 | mlx5_core_info(dev, "Shutdown was called\n"); |
8324a02c | 1879 | set_bit(MLX5_BREAK_FW_WAIT, &dev->intf_state); |
8812c24d MD |
1880 | err = mlx5_try_fast_unload(dev); |
1881 | if (err) | |
6dea2f7e | 1882 | mlx5_unload_one(dev); |
5fc7197d MD |
1883 | mlx5_pci_disable_device(dev); |
1884 | } | |
1885 | ||
8fc3e29b MB |
1886 | static int mlx5_suspend(struct pci_dev *pdev, pm_message_t state) |
1887 | { | |
1888 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1889 | ||
6dea2f7e | 1890 | mlx5_unload_one(dev); |
8fc3e29b MB |
1891 | |
1892 | return 0; | |
1893 | } | |
1894 | ||
1895 | static int mlx5_resume(struct pci_dev *pdev) | |
1896 | { | |
1897 | struct mlx5_core_dev *dev = pci_get_drvdata(pdev); | |
1898 | ||
37ca95e6 | 1899 | return mlx5_load_one(dev, false); |
8fc3e29b MB |
1900 | } |
1901 | ||
9603b61d | 1902 | static const struct pci_device_id mlx5_core_pci_table[] = { |
bbad7c21 | 1903 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) }, |
fc50db98 | 1904 | { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */ |
bbad7c21 | 1905 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) }, |
fc50db98 | 1906 | { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */ |
bbad7c21 | 1907 | { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) }, |
fc50db98 | 1908 | { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */ |
7092fe86 | 1909 | { PCI_VDEVICE(MELLANOX, 0x1017) }, /* ConnectX-5, PCIe 3.0 */ |
64dbbdfe | 1910 | { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */ |
d0dd989f MD |
1911 | { PCI_VDEVICE(MELLANOX, 0x1019) }, /* ConnectX-5 Ex */ |
1912 | { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */ | |
1913 | { PCI_VDEVICE(MELLANOX, 0x101b) }, /* ConnectX-6 */ | |
1914 | { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */ | |
85327a9c EBE |
1915 | { PCI_VDEVICE(MELLANOX, 0x101d) }, /* ConnectX-6 Dx */ |
1916 | { PCI_VDEVICE(MELLANOX, 0x101e), MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */ | |
b7eca940 | 1917 | { PCI_VDEVICE(MELLANOX, 0x101f) }, /* ConnectX-6 LX */ |
505a7f54 | 1918 | { PCI_VDEVICE(MELLANOX, 0x1021) }, /* ConnectX-7 */ |
f908a35b | 1919 | { PCI_VDEVICE(MELLANOX, 0x1023) }, /* ConnectX-8 */ |
2e9d3e83 NO |
1920 | { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ |
1921 | { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF}, /* BlueField integrated ConnectX-5 network controller VF */ | |
d19a79ee | 1922 | { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ |
dd8595ea | 1923 | { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ |
f908a35b | 1924 | { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ |
9603b61d JM |
1925 | { 0, } |
1926 | }; | |
1927 | ||
1928 | MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); | |
1929 | ||
04c0c1ab MHY |
1930 | void mlx5_disable_device(struct mlx5_core_dev *dev) |
1931 | { | |
b3bd076f | 1932 | mlx5_error_sw_reset(dev); |
d3dbdc9f | 1933 | mlx5_unload_one_devl_locked(dev); |
04c0c1ab MHY |
1934 | } |
1935 | ||
fe06992b | 1936 | int mlx5_recover_device(struct mlx5_core_dev *dev) |
04c0c1ab | 1937 | { |
33de865f MS |
1938 | if (!mlx5_core_is_sf(dev)) { |
1939 | mlx5_pci_disable_device(dev); | |
1940 | if (mlx5_pci_slot_reset(dev->pdev) != PCI_ERS_RESULT_RECOVERED) | |
1941 | return -EIO; | |
1942 | } | |
fe06992b | 1943 | |
d3dbdc9f | 1944 | return mlx5_load_one_devl_locked(dev, true); |
04c0c1ab MHY |
1945 | } |
1946 | ||
9603b61d | 1947 | static struct pci_driver mlx5_core_driver = { |
17a7612b | 1948 | .name = KBUILD_MODNAME, |
9603b61d | 1949 | .id_table = mlx5_core_pci_table, |
6dea2f7e | 1950 | .probe = probe_one, |
89d44f0a | 1951 | .remove = remove_one, |
8fc3e29b MB |
1952 | .suspend = mlx5_suspend, |
1953 | .resume = mlx5_resume, | |
5fc7197d | 1954 | .shutdown = shutdown, |
fc50db98 EC |
1955 | .err_handler = &mlx5_err_handler, |
1956 | .sriov_configure = mlx5_core_sriov_configure, | |
e71b75f7 LR |
1957 | .sriov_get_vf_total_msix = mlx5_sriov_get_vf_total_msix, |
1958 | .sriov_set_msix_vec_count = mlx5_core_sriov_set_msix_vec_count, | |
9603b61d | 1959 | }; |
e126ba97 | 1960 | |
1695b97b YH |
1961 | /** |
1962 | * mlx5_vf_get_core_dev - Get the mlx5 core device from a given VF PCI device if | |
1963 | * mlx5_core is its driver. | |
1964 | * @pdev: The associated PCI device. | |
1965 | * | |
1966 | * Upon return the interface state lock stay held to let caller uses it safely. | |
1967 | * Caller must ensure to use the returned mlx5 device for a narrow window | |
1968 | * and put it back with mlx5_vf_put_core_dev() immediately once usage was over. | |
1969 | * | |
1970 | * Return: Pointer to the associated mlx5_core_dev or NULL. | |
1971 | */ | |
1972 | struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev) | |
1695b97b YH |
1973 | { |
1974 | struct mlx5_core_dev *mdev; | |
1975 | ||
1976 | mdev = pci_iov_get_pf_drvdata(pdev, &mlx5_core_driver); | |
1977 | if (IS_ERR(mdev)) | |
1978 | return NULL; | |
1979 | ||
1980 | mutex_lock(&mdev->intf_state_mutex); | |
1981 | if (!test_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state)) { | |
1982 | mutex_unlock(&mdev->intf_state_mutex); | |
1983 | return NULL; | |
1984 | } | |
1985 | ||
1986 | return mdev; | |
1987 | } | |
1988 | EXPORT_SYMBOL(mlx5_vf_get_core_dev); | |
1989 | ||
1990 | /** | |
1991 | * mlx5_vf_put_core_dev - Put the mlx5 core device back. | |
1992 | * @mdev: The mlx5 core device. | |
1993 | * | |
1994 | * Upon return the interface state lock is unlocked and caller should not | |
1995 | * access the mdev any more. | |
1996 | */ | |
1997 | void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev) | |
1695b97b YH |
1998 | { |
1999 | mutex_unlock(&mdev->intf_state_mutex); | |
2000 | } | |
2001 | EXPORT_SYMBOL(mlx5_vf_put_core_dev); | |
2002 | ||
f663ad98 KH |
2003 | static void mlx5_core_verify_params(void) |
2004 | { | |
2005 | if (prof_sel >= ARRAY_SIZE(profile)) { | |
2006 | pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n", | |
2007 | prof_sel, | |
2008 | ARRAY_SIZE(profile) - 1, | |
2009 | MLX5_DEFAULT_PROF); | |
2010 | prof_sel = MLX5_DEFAULT_PROF; | |
2011 | } | |
2012 | } | |
2013 | ||
e126ba97 EC |
2014 | static int __init init(void) |
2015 | { | |
2016 | int err; | |
2017 | ||
17a7612b LR |
2018 | WARN_ONCE(strcmp(MLX5_ADEV_NAME, KBUILD_MODNAME), |
2019 | "mlx5_core name not in sync with kernel module name"); | |
2020 | ||
8737f818 DJ |
2021 | get_random_bytes(&sw_owner_id, sizeof(sw_owner_id)); |
2022 | ||
f663ad98 | 2023 | mlx5_core_verify_params(); |
e126ba97 | 2024 | mlx5_register_debugfs(); |
e126ba97 | 2025 | |
9603b61d JM |
2026 | err = pci_register_driver(&mlx5_core_driver); |
2027 | if (err) | |
ac6ea6e8 | 2028 | goto err_debug; |
9603b61d | 2029 | |
1958fc2f PP |
2030 | err = mlx5_sf_driver_register(); |
2031 | if (err) | |
2032 | goto err_sf; | |
2033 | ||
912cebf4 | 2034 | err = mlx5e_init(); |
c633e799 LR |
2035 | if (err) |
2036 | goto err_en; | |
f62b8bb8 | 2037 | |
e126ba97 EC |
2038 | return 0; |
2039 | ||
c633e799 LR |
2040 | err_en: |
2041 | mlx5_sf_driver_unregister(); | |
1958fc2f PP |
2042 | err_sf: |
2043 | pci_unregister_driver(&mlx5_core_driver); | |
e126ba97 EC |
2044 | err_debug: |
2045 | mlx5_unregister_debugfs(); | |
2046 | return err; | |
2047 | } | |
2048 | ||
2049 | static void __exit cleanup(void) | |
2050 | { | |
f62b8bb8 | 2051 | mlx5e_cleanup(); |
1958fc2f | 2052 | mlx5_sf_driver_unregister(); |
9603b61d | 2053 | pci_unregister_driver(&mlx5_core_driver); |
e126ba97 EC |
2054 | mlx5_unregister_debugfs(); |
2055 | } | |
2056 | ||
2057 | module_init(init); | |
2058 | module_exit(cleanup); |