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Merge tag 'mlx5-updates-2021-05-26' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / lag.c
CommitLineData
7907f23a
AH		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/netdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/vport.h>
36#include "mlx5_core.h"
3b5ff59f 37#include "eswitch.h"
10a193ed 38#include "lag.h"
544fe7c2 39#include "lag_mp.h"
7907f23a
AH		 40
41/* General purpose, use for short periods of time.
42 * Beware of lock dependencies (preferably, no locks should be acquired
43 * under it).
44 */
64363e61 45static DEFINE_SPINLOCK(lag_lock);
7907f23a
AH		 46
47static int mlx5_cmd_create_lag(struct mlx5_core_dev *dev, u8 remap_port1,
48 u8 remap_port2)
49{
5d19395f 50 u32 in[MLX5_ST_SZ_DW(create_lag_in)] = {};
7907f23a
AH		 51 void *lag_ctx = MLX5_ADDR_OF(create_lag_in, in, ctx);
52
53 MLX5_SET(create_lag_in, in, opcode, MLX5_CMD_OP_CREATE_LAG);
54
55 MLX5_SET(lagc, lag_ctx, tx_remap_affinity_1, remap_port1);
56 MLX5_SET(lagc, lag_ctx, tx_remap_affinity_2, remap_port2);
57
5d19395f 58 return mlx5_cmd_exec_in(dev, create_lag, in);
7907f23a
AH		 59}
60
61static int mlx5_cmd_modify_lag(struct mlx5_core_dev *dev, u8 remap_port1,
62 u8 remap_port2)
63{
5d19395f 64 u32 in[MLX5_ST_SZ_DW(modify_lag_in)] = {};
7907f23a
AH		 65 void *lag_ctx = MLX5_ADDR_OF(modify_lag_in, in, ctx);
66
67 MLX5_SET(modify_lag_in, in, opcode, MLX5_CMD_OP_MODIFY_LAG);
68 MLX5_SET(modify_lag_in, in, field_select, 0x1);
69
70 MLX5_SET(lagc, lag_ctx, tx_remap_affinity_1, remap_port1);
71 MLX5_SET(lagc, lag_ctx, tx_remap_affinity_2, remap_port2);
72
5d19395f 73 return mlx5_cmd_exec_in(dev, modify_lag, in);
7907f23a
AH		 74}
75
3bc34f3b
AH		 76int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev)
77{
5d19395f 78 u32 in[MLX5_ST_SZ_DW(create_vport_lag_in)] = {};
3bc34f3b
AH		 79
80 MLX5_SET(create_vport_lag_in, in, opcode, MLX5_CMD_OP_CREATE_VPORT_LAG);
81
5d19395f 82 return mlx5_cmd_exec_in(dev, create_vport_lag, in);
3bc34f3b
AH		 83}
84EXPORT_SYMBOL(mlx5_cmd_create_vport_lag);
85
86int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev)
87{
5d19395f 88 u32 in[MLX5_ST_SZ_DW(destroy_vport_lag_in)] = {};
3bc34f3b
AH		 89
90 MLX5_SET(destroy_vport_lag_in, in, opcode, MLX5_CMD_OP_DESTROY_VPORT_LAG);
91
5d19395f 92 return mlx5_cmd_exec_in(dev, destroy_vport_lag, in);
3bc34f3b
AH		 93}
94EXPORT_SYMBOL(mlx5_cmd_destroy_vport_lag);
95
10a193ed
RD		 96int mlx5_lag_dev_get_netdev_idx(struct mlx5_lag *ldev,
97 struct net_device *ndev)
7907f23a
AH		 98{
99 int i;
100
101 for (i = 0; i < MLX5_MAX_PORTS; i++)
102 if (ldev->pf[i].netdev == ndev)
103 return i;
104
f552be54 105 return -ENOENT;
7907f23a
AH		 106}
107
7c34ec19
AH		 108static bool __mlx5_lag_is_roce(struct mlx5_lag *ldev)
109{
110 return !!(ldev->flags & MLX5_LAG_FLAG_ROCE);
111}
112
113static bool __mlx5_lag_is_sriov(struct mlx5_lag *ldev)
114{
115 return !!(ldev->flags & MLX5_LAG_FLAG_SRIOV);
116}
117
7907f23a
AH		 118static void mlx5_infer_tx_affinity_mapping(struct lag_tracker *tracker,
119 u8 *port1, u8 *port2)
120{
86136410
EC		 121 bool p1en;
122 bool p2en;
123
124 p1en = tracker->netdev_state[MLX5_LAG_P1].tx_enabled &&
125 tracker->netdev_state[MLX5_LAG_P1].link_up;
126
127 p2en = tracker->netdev_state[MLX5_LAG_P2].tx_enabled &&
128 tracker->netdev_state[MLX5_LAG_P2].link_up;
129
dc798b4c
AH		 130 *port1 = 1;
131 *port2 = 2;
86136410 132 if ((!p1en && !p2en) || (p1en && p2en))
dc798b4c 133 return;
dc798b4c 134
86136410 135 if (p1en)
dc798b4c 136 *port2 = 1;
86136410
EC		 137 else
138 *port1 = 2;
7907f23a
AH		 139}
140
10a193ed
RD		 141void mlx5_modify_lag(struct mlx5_lag *ldev,
142 struct lag_tracker *tracker)
4c283e61 143{
84d2dbb0 144 struct mlx5_core_dev *dev0 = ldev->pf[MLX5_LAG_P1].dev;
4c283e61
SK		 145 u8 v2p_port1, v2p_port2;
146 int err;
147
148 mlx5_infer_tx_affinity_mapping(tracker, &v2p_port1,
149 &v2p_port2);
150
84d2dbb0
EA		 151 if (v2p_port1 != ldev->v2p_map[MLX5_LAG_P1] ||
152 v2p_port2 != ldev->v2p_map[MLX5_LAG_P2]) {
153 ldev->v2p_map[MLX5_LAG_P1] = v2p_port1;
154 ldev->v2p_map[MLX5_LAG_P2] = v2p_port2;
4c283e61
SK		 155
156 mlx5_core_info(dev0, "modify lag map port 1:%d port 2:%d",
84d2dbb0
EA		 157 ldev->v2p_map[MLX5_LAG_P1],
158 ldev->v2p_map[MLX5_LAG_P2]);
4c283e61
SK		 159
160 err = mlx5_cmd_modify_lag(dev0, v2p_port1, v2p_port2);
161 if (err)
162 mlx5_core_err(dev0,
163 "Failed to modify LAG (%d)\n",
164 err);
165 }
166}
167
8252cf72
RD		 168static int mlx5_create_lag(struct mlx5_lag *ldev,
169 struct lag_tracker *tracker)
7907f23a 170{
84d2dbb0 171 struct mlx5_core_dev *dev0 = ldev->pf[MLX5_LAG_P1].dev;
7907f23a
AH		 172 int err;
173
84d2dbb0
EA		 174 mlx5_infer_tx_affinity_mapping(tracker, &ldev->v2p_map[MLX5_LAG_P1],
175 &ldev->v2p_map[MLX5_LAG_P2]);
7907f23a 176
3cfe432e 177 mlx5_core_info(dev0, "lag map port 1:%d port 2:%d",
84d2dbb0 178 ldev->v2p_map[MLX5_LAG_P1], ldev->v2p_map[MLX5_LAG_P2]);
3cfe432e 179
84d2dbb0
EA		 180 err = mlx5_cmd_create_lag(dev0, ldev->v2p_map[MLX5_LAG_P1],
181 ldev->v2p_map[MLX5_LAG_P2]);
7907f23a
AH		 182 if (err)
183 mlx5_core_err(dev0,
184 "Failed to create LAG (%d)\n",
185 err);
8252cf72
RD		 186 return err;
187}
188
10a193ed
RD		 189int mlx5_activate_lag(struct mlx5_lag *ldev,
190 struct lag_tracker *tracker,
191 u8 flags)
8252cf72 192{
95824666 193 bool roce_lag = !!(flags & MLX5_LAG_FLAG_ROCE);
84d2dbb0 194 struct mlx5_core_dev *dev0 = ldev->pf[MLX5_LAG_P1].dev;
95824666
AH		 195 int err;
196
197 err = mlx5_create_lag(ldev, tracker);
198 if (err) {
199 if (roce_lag) {
200 mlx5_core_err(dev0,
201 "Failed to activate RoCE LAG\n");
202 } else {
203 mlx5_core_err(dev0,
204 "Failed to activate VF LAG\n"
205 "Make sure all VFs are unbound prior to VF LAG activation or deactivation\n");
206 }
207 return err;
208 }
209
7c34ec19 210 ldev->flags |= flags;
95824666 211 return 0;
7907f23a
AH		 212}
213
95824666 214static int mlx5_deactivate_lag(struct mlx5_lag *ldev)
7907f23a 215{
84d2dbb0 216 struct mlx5_core_dev *dev0 = ldev->pf[MLX5_LAG_P1].dev;
5d19395f 217 u32 in[MLX5_ST_SZ_DW(destroy_lag_in)] = {};
95824666 218 bool roce_lag = __mlx5_lag_is_roce(ldev);
7907f23a
AH		 219 int err;
220
7c34ec19 221 ldev->flags &= ~MLX5_LAG_MODE_FLAGS;
7907f23a 222
5d19395f
LR		 223 MLX5_SET(destroy_lag_in, in, opcode, MLX5_CMD_OP_DESTROY_LAG);
224 err = mlx5_cmd_exec_in(dev0, destroy_lag, in);
95824666
AH		 225 if (err) {
226 if (roce_lag) {
227 mlx5_core_err(dev0,
228 "Failed to deactivate RoCE LAG; driver restart required\n");
229 } else {
230 mlx5_core_err(dev0,
231 "Failed to deactivate VF LAG; driver restart required\n"
232 "Make sure all VFs are unbound prior to VF LAG activation or deactivation\n");
233 }
234 }
235
236 return err;
7907f23a
AH		 237}
238
eff849b2
RL		 239static bool mlx5_lag_check_prereq(struct mlx5_lag *ldev)
240{
84d2dbb0 241 if (!ldev->pf[MLX5_LAG_P1].dev || !ldev->pf[MLX5_LAG_P2].dev)
eff849b2 242 return false;
a6491744
AH		 243
244#ifdef CONFIG_MLX5_ESWITCH
84d2dbb0
EA		 245 return mlx5_esw_lag_prereq(ldev->pf[MLX5_LAG_P1].dev,
246 ldev->pf[MLX5_LAG_P2].dev);
a6491744 247#else
84d2dbb0
EA		 248 return (!mlx5_sriov_is_enabled(ldev->pf[MLX5_LAG_P1].dev) &&
249 !mlx5_sriov_is_enabled(ldev->pf[MLX5_LAG_P2].dev));
a6491744 250#endif
eff849b2
RL		 251}
252
93f82444 253static void mlx5_lag_add_devices(struct mlx5_lag *ldev)
95824666
AH		 254{
255 int i;
256
93f82444
LR		 257 for (i = 0; i < MLX5_MAX_PORTS; i++) {
258 if (!ldev->pf[i].dev)
259 continue;
260
261 ldev->pf[i].dev->priv.flags &= ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
262 mlx5_rescan_drivers_locked(ldev->pf[i].dev);
263 }
95824666
AH		 264}
265
93f82444 266static void mlx5_lag_remove_devices(struct mlx5_lag *ldev)
95824666
AH		 267{
268 int i;
269
93f82444
LR		 270 for (i = 0; i < MLX5_MAX_PORTS; i++) {
271 if (!ldev->pf[i].dev)
272 continue;
273
274 ldev->pf[i].dev->priv.flags |= MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
275 mlx5_rescan_drivers_locked(ldev->pf[i].dev);
276 }
95824666
AH		 277}
278
7907f23a
AH		 279static void mlx5_do_bond(struct mlx5_lag *ldev)
280{
84d2dbb0
EA		 281 struct mlx5_core_dev *dev0 = ldev->pf[MLX5_LAG_P1].dev;
282 struct mlx5_core_dev *dev1 = ldev->pf[MLX5_LAG_P2].dev;
7907f23a 283 struct lag_tracker tracker;
7c34ec19 284 bool do_bond, roce_lag;
95824666 285 int err;
7907f23a 286
9b412cc3 287 if (!mlx5_lag_is_ready(ldev))
7907f23a
AH		 288 return;
289
7907f23a 290 tracker = ldev->tracker;
7907f23a 291
eff849b2 292 do_bond = tracker.is_bonded && mlx5_lag_check_prereq(ldev);
edb31b16 293
292612d6 294 if (do_bond && !__mlx5_lag_is_active(ldev)) {
7c34ec19
AH		 295 roce_lag = !mlx5_sriov_is_enabled(dev0) &&
296 !mlx5_sriov_is_enabled(dev1);
297
86b39a66 298#ifdef CONFIG_MLX5_ESWITCH
2b147675
EC		 299 roce_lag = roce_lag &&
300 dev0->priv.eswitch->mode == MLX5_ESWITCH_NONE &&
301 dev1->priv.eswitch->mode == MLX5_ESWITCH_NONE;
86b39a66
BW		 302#endif
303
7c34ec19 304 if (roce_lag)
93f82444 305 mlx5_lag_remove_devices(ldev);
95824666
AH		 306
307 err = mlx5_activate_lag(ldev, &tracker,
308 roce_lag ? MLX5_LAG_FLAG_ROCE :
309 MLX5_LAG_FLAG_SRIOV);
310 if (err) {
311 if (roce_lag)
93f82444 312 mlx5_lag_add_devices(ldev);
7907f23a 313
95824666
AH		 314 return;
315 }
7907f23a 316
7c34ec19 317 if (roce_lag) {
93f82444
LR		 318 dev0->priv.flags &= ~MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
319 mlx5_rescan_drivers_locked(dev0);
3b5ff59f
RL		 320 mlx5_nic_vport_enable_roce(dev1);
321 }
292612d6 322 } else if (do_bond && __mlx5_lag_is_active(ldev)) {
4c283e61 323 mlx5_modify_lag(ldev, &tracker);
292612d6 324 } else if (!do_bond && __mlx5_lag_is_active(ldev)) {
7c34ec19
AH		 325 roce_lag = __mlx5_lag_is_roce(ldev);
326
327 if (roce_lag) {
93f82444
LR		 328 dev0->priv.flags |= MLX5_PRIV_FLAGS_DISABLE_IB_ADEV;
329 mlx5_rescan_drivers_locked(dev0);
3b5ff59f
RL		 330 mlx5_nic_vport_disable_roce(dev1);
331 }
7907f23a 332
95824666
AH		 333 err = mlx5_deactivate_lag(ldev);
334 if (err)
335 return;
7907f23a 336
7c34ec19 337 if (roce_lag)
93f82444 338 mlx5_lag_add_devices(ldev);
7907f23a
AH		 339 }
340}
341
342static void mlx5_queue_bond_work(struct mlx5_lag *ldev, unsigned long delay)
343{
e6ee5e71 344 queue_delayed_work(ldev->wq, &ldev->bond_work, delay);
7907f23a
AH		 345}
346
347static void mlx5_do_bond_work(struct work_struct *work)
348{
349 struct delayed_work *delayed_work = to_delayed_work(work);
350 struct mlx5_lag *ldev = container_of(delayed_work, struct mlx5_lag,
351 bond_work);
352 int status;
353
f1ee87fe 354 status = mlx5_dev_list_trylock();
7907f23a
AH		 355 if (!status) {
356 /* 1 sec delay. */
357 mlx5_queue_bond_work(ldev, HZ);
358 return;
359 }
360
361 mlx5_do_bond(ldev);
f1ee87fe 362 mlx5_dev_list_unlock();
7907f23a
AH		 363}
364
365static int mlx5_handle_changeupper_event(struct mlx5_lag *ldev,
366 struct lag_tracker *tracker,
367 struct net_device *ndev,
368 struct netdev_notifier_changeupper_info *info)
369{
370 struct net_device *upper = info->upper_dev, *ndev_tmp;
e497ec68 371 struct netdev_lag_upper_info *lag_upper_info = NULL;
1a3c9114 372 bool is_bonded, is_in_lag, mode_supported;
7907f23a
AH		 373 int bond_status = 0;
374 int num_slaves = 0;
375 int idx;
376
377 if (!netif_is_lag_master(upper))
378 return 0;
379
e497ec68
TB		 380 if (info->linking)
381 lag_upper_info = info->upper_info;
7907f23a
AH		 382
383 /* The event may still be of interest if the slave does not belong to
384 * us, but is enslaved to a master which has one or more of our netdevs
385 * as slaves (e.g., if a new slave is added to a master that bonds two
386 * of our netdevs, we should unbond).
387 */
388 rcu_read_lock();
389 for_each_netdev_in_bond_rcu(upper, ndev_tmp) {
390 idx = mlx5_lag_dev_get_netdev_idx(ldev, ndev_tmp);
f552be54 391 if (idx >= 0)
7907f23a
AH		 392 bond_status |= (1 << idx);
393
394 num_slaves++;
395 }
396 rcu_read_unlock();
397
398 /* None of this lagdev's netdevs are slaves of this master. */
399 if (!(bond_status & 0x3))
400 return 0;
401
402 if (lag_upper_info)
403 tracker->tx_type = lag_upper_info->tx_type;
404
405 /* Determine bonding status:
406 * A device is considered bonded if both its physical ports are slaves
407 * of the same lag master, and only them.
7907f23a 408 */
1a3c9114 409 is_in_lag = num_slaves == MLX5_MAX_PORTS && bond_status == 0x3;
7907f23a 410
9b412cc3
JL		 411 if (!mlx5_lag_is_ready(ldev) && is_in_lag) {
412 NL_SET_ERR_MSG_MOD(info->info.extack,
413 "Can't activate LAG offload, PF is configured with more than 64 VFs");
414 return 0;
415 }
416
1a3c9114
JL		 417 /* Lag mode must be activebackup or hash. */
418 mode_supported = tracker->tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP ||
419 tracker->tx_type == NETDEV_LAG_TX_TYPE_HASH;
420
421 if (is_in_lag && !mode_supported)
422 NL_SET_ERR_MSG_MOD(info->info.extack,
423 "Can't activate LAG offload, TX type isn't supported");
424
425 is_bonded = is_in_lag && mode_supported;
7907f23a
AH		 426 if (tracker->is_bonded != is_bonded) {
427 tracker->is_bonded = is_bonded;
428 return 1;
429 }
430
431 return 0;
432}
433
434static int mlx5_handle_changelowerstate_event(struct mlx5_lag *ldev,
435 struct lag_tracker *tracker,
436 struct net_device *ndev,
437 struct netdev_notifier_changelowerstate_info *info)
438{
439 struct netdev_lag_lower_state_info *lag_lower_info;
440 int idx;
441
442 if (!netif_is_lag_port(ndev))
443 return 0;
444
445 idx = mlx5_lag_dev_get_netdev_idx(ldev, ndev);
f552be54 446 if (idx < 0)
7907f23a
AH		 447 return 0;
448
449 /* This information is used to determine virtual to physical
450 * port mapping.
451 */
452 lag_lower_info = info->lower_state_info;
453 if (!lag_lower_info)
454 return 0;
455
456 tracker->netdev_state[idx] = *lag_lower_info;
457
458 return 1;
459}
460
461static int mlx5_lag_netdev_event(struct notifier_block *this,
462 unsigned long event, void *ptr)
463{
464 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
465 struct lag_tracker tracker;
466 struct mlx5_lag *ldev;
467 int changed = 0;
468
7907f23a
AH		 469 if ((event != NETDEV_CHANGEUPPER) && (event != NETDEV_CHANGELOWERSTATE))
470 return NOTIFY_DONE;
471
472 ldev = container_of(this, struct mlx5_lag, nb);
9b412cc3
JL		 473
474 if (!mlx5_lag_is_ready(ldev) && event == NETDEV_CHANGELOWERSTATE)
475 return NOTIFY_DONE;
476
7907f23a
AH		 477 tracker = ldev->tracker;
478
479 switch (event) {
480 case NETDEV_CHANGEUPPER:
481 changed = mlx5_handle_changeupper_event(ldev, &tracker, ndev,
482 ptr);
483 break;
484 case NETDEV_CHANGELOWERSTATE:
485 changed = mlx5_handle_changelowerstate_event(ldev, &tracker,
486 ndev, ptr);
487 break;
488 }
489
7907f23a 490 ldev->tracker = tracker;
7907f23a
AH		 491
492 if (changed)
493 mlx5_queue_bond_work(ldev, 0);
494
495 return NOTIFY_DONE;
496}
497
498static struct mlx5_lag *mlx5_lag_dev_alloc(void)
499{
500 struct mlx5_lag *ldev;
501
502 ldev = kzalloc(sizeof(*ldev), GFP_KERNEL);
503 if (!ldev)
504 return NULL;
505
e6ee5e71
RD		 506 ldev->wq = create_singlethread_workqueue("mlx5_lag");
507 if (!ldev->wq) {
508 kfree(ldev);
509 return NULL;
510 }
511
7907f23a
AH		 512 INIT_DELAYED_WORK(&ldev->bond_work, mlx5_do_bond_work);
513
514 return ldev;
515}
516
517static void mlx5_lag_dev_free(struct mlx5_lag *ldev)
518{
e6ee5e71 519 destroy_workqueue(ldev->wq);
7907f23a
AH		 520 kfree(ldev);
521}
522
9b412cc3
JL		 523static int mlx5_lag_dev_add_pf(struct mlx5_lag *ldev,
524 struct mlx5_core_dev *dev,
525 struct net_device *netdev)
7907f23a
AH		 526{
527 unsigned int fn = PCI_FUNC(dev->pdev->devfn);
528
529 if (fn >= MLX5_MAX_PORTS)
9b412cc3 530 return -EPERM;
7907f23a 531
64363e61 532 spin_lock(&lag_lock);
7907f23a
AH		 533 ldev->pf[fn].dev = dev;
534 ldev->pf[fn].netdev = netdev;
535 ldev->tracker.netdev_state[fn].link_up = 0;
536 ldev->tracker.netdev_state[fn].tx_enabled = 0;
537
538 dev->priv.lag = ldev;
552db7bc 539
64363e61 540 spin_unlock(&lag_lock);
9b412cc3
JL		 541
542 return fn;
7907f23a
AH		 543}
544
545static void mlx5_lag_dev_remove_pf(struct mlx5_lag *ldev,
546 struct mlx5_core_dev *dev)
547{
548 int i;
549
550 for (i = 0; i < MLX5_MAX_PORTS; i++)
551 if (ldev->pf[i].dev == dev)
552 break;
553
554 if (i == MLX5_MAX_PORTS)
555 return;
556
64363e61 557 spin_lock(&lag_lock);
7907f23a
AH		 558 memset(&ldev->pf[i], 0, sizeof(*ldev->pf));
559
560 dev->priv.lag = NULL;
64363e61 561 spin_unlock(&lag_lock);
7907f23a
AH		 562}
563
7907f23a
AH		 564/* Must be called with intf_mutex held */
565void mlx5_lag_add(struct mlx5_core_dev *dev, struct net_device *netdev)
566{
567 struct mlx5_lag *ldev = NULL;
568 struct mlx5_core_dev *tmp_dev;
9b412cc3 569 int i, err;
7907f23a 570
abf8ef95
MZ		 571 if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
572 !MLX5_CAP_GEN(dev, lag_master) ||
573 MLX5_CAP_GEN(dev, num_lag_ports) != MLX5_MAX_PORTS)
7907f23a
AH		 574 return;
575
f1ee87fe
MHY		 576 tmp_dev = mlx5_get_next_phys_dev(dev);
577 if (tmp_dev)
578 ldev = tmp_dev->priv.lag;
7907f23a
AH		 579
580 if (!ldev) {
581 ldev = mlx5_lag_dev_alloc();
582 if (!ldev) {
583 mlx5_core_err(dev, "Failed to alloc lag dev\n");
584 return;
585 }
586 }
587
9b412cc3
JL		 588 if (mlx5_lag_dev_add_pf(ldev, dev, netdev) < 0)
589 return;
590
abf8ef95
MZ		 591 for (i = 0; i < MLX5_MAX_PORTS; i++)
592 if (!ldev->pf[i].dev)
9b412cc3 593 break;
9b412cc3
JL		 594
595 if (i >= MLX5_MAX_PORTS)
596 ldev->flags |= MLX5_LAG_FLAG_READY;
7907f23a
AH		 597
598 if (!ldev->nb.notifier_call) {
599 ldev->nb.notifier_call = mlx5_lag_netdev_event;
e387f7d5 600 if (register_netdevice_notifier_net(&init_net, &ldev->nb)) {
7907f23a
AH		 601 ldev->nb.notifier_call = NULL;
602 mlx5_core_err(dev, "Failed to register LAG netdev notifier\n");
603 }
604 }
544fe7c2
RD		 605
606 err = mlx5_lag_mp_init(ldev);
607 if (err)
608 mlx5_core_err(dev, "Failed to init multipath lag err=%d\n",
609 err);
7907f23a
AH		 610}
611
612/* Must be called with intf_mutex held */
e387f7d5 613void mlx5_lag_remove(struct mlx5_core_dev *dev)
7907f23a
AH		 614{
615 struct mlx5_lag *ldev;
616 int i;
617
618 ldev = mlx5_lag_dev_get(dev);
619 if (!ldev)
620 return;
621
292612d6 622 if (__mlx5_lag_is_active(ldev))
7907f23a
AH		 623 mlx5_deactivate_lag(ldev);
624
625 mlx5_lag_dev_remove_pf(ldev, dev);
626
9b412cc3
JL		 627 ldev->flags &= ~MLX5_LAG_FLAG_READY;
628
7907f23a
AH		 629 for (i = 0; i < MLX5_MAX_PORTS; i++)
630 if (ldev->pf[i].dev)
631 break;
632
633 if (i == MLX5_MAX_PORTS) {
0b136454 634 if (ldev->nb.notifier_call) {
e387f7d5 635 unregister_netdevice_notifier_net(&init_net, &ldev->nb);
0b136454
EC		 636 ldev->nb.notifier_call = NULL;
637 }
544fe7c2 638 mlx5_lag_mp_cleanup(ldev);
7907f23a
AH		 639 cancel_delayed_work_sync(&ldev->bond_work);
640 mlx5_lag_dev_free(ldev);
641 }
642}
643
7c34ec19
AH		 644bool mlx5_lag_is_roce(struct mlx5_core_dev *dev)
645{
646 struct mlx5_lag *ldev;
647 bool res;
648
64363e61 649 spin_lock(&lag_lock);
7c34ec19
AH		 650 ldev = mlx5_lag_dev_get(dev);
651 res = ldev && __mlx5_lag_is_roce(ldev);
64363e61 652 spin_unlock(&lag_lock);
7c34ec19
AH		 653
654 return res;
655}
656EXPORT_SYMBOL(mlx5_lag_is_roce);
657
7907f23a
AH		 658bool mlx5_lag_is_active(struct mlx5_core_dev *dev)
659{
660 struct mlx5_lag *ldev;
661 bool res;
662
64363e61 663 spin_lock(&lag_lock);
7907f23a 664 ldev = mlx5_lag_dev_get(dev);
292612d6 665 res = ldev && __mlx5_lag_is_active(ldev);
64363e61 666 spin_unlock(&lag_lock);
7907f23a
AH		 667
668 return res;
669}
670EXPORT_SYMBOL(mlx5_lag_is_active);
671
7c34ec19
AH		 672bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev)
673{
674 struct mlx5_lag *ldev;
675 bool res;
676
64363e61 677 spin_lock(&lag_lock);
7c34ec19
AH		 678 ldev = mlx5_lag_dev_get(dev);
679 res = ldev && __mlx5_lag_is_sriov(ldev);
64363e61 680 spin_unlock(&lag_lock);
7c34ec19
AH		 681
682 return res;
683}
684EXPORT_SYMBOL(mlx5_lag_is_sriov);
685
eff849b2 686void mlx5_lag_update(struct mlx5_core_dev *dev)
552db7bc
MS		 687{
688 struct mlx5_lag *ldev;
552db7bc
MS		 689
690 mlx5_dev_list_lock();
552db7bc 691 ldev = mlx5_lag_dev_get(dev);
eff849b2 692 if (!ldev)
552db7bc 693 goto unlock;
552db7bc 694
eff849b2 695 mlx5_do_bond(ldev);
552db7bc 696
eff849b2
RL		 697unlock:
698 mlx5_dev_list_unlock();
552db7bc
MS		 699}
700
6a32047a
AH		 701struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev)
702{
703 struct net_device *ndev = NULL;
704 struct mlx5_lag *ldev;
705
64363e61 706 spin_lock(&lag_lock);
6a32047a
AH		 707 ldev = mlx5_lag_dev_get(dev);
708
7c34ec19 709 if (!(ldev && __mlx5_lag_is_roce(ldev)))
6a32047a
AH		 710 goto unlock;
711
712 if (ldev->tracker.tx_type == NETDEV_LAG_TX_TYPE_ACTIVEBACKUP) {
84d2dbb0
EA		 713 ndev = ldev->tracker.netdev_state[MLX5_LAG_P1].tx_enabled ?
714 ldev->pf[MLX5_LAG_P1].netdev :
715 ldev->pf[MLX5_LAG_P2].netdev;
6a32047a 716 } else {
84d2dbb0 717 ndev = ldev->pf[MLX5_LAG_P1].netdev;
6a32047a
AH		 718 }
719 if (ndev)
720 dev_hold(ndev);
721
722unlock:
64363e61 723 spin_unlock(&lag_lock);
6a32047a
AH		 724
725 return ndev;
726}
727EXPORT_SYMBOL(mlx5_lag_get_roce_netdev);
728
c6bc6041
MG		 729u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
730 struct net_device *slave)
731{
732 struct mlx5_lag *ldev;
733 u8 port = 0;
734
735 spin_lock(&lag_lock);
736 ldev = mlx5_lag_dev_get(dev);
737 if (!(ldev && __mlx5_lag_is_roce(ldev)))
738 goto unlock;
739
740 if (ldev->pf[MLX5_LAG_P1].netdev == slave)
741 port = MLX5_LAG_P1;
742 else
743 port = MLX5_LAG_P2;
744
745 port = ldev->v2p_map[port];
746
747unlock:
748 spin_unlock(&lag_lock);
749 return port;
750}
751EXPORT_SYMBOL(mlx5_lag_get_slave_port);
752
71a0ff65
MD		 753int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
754 u64 *values,
755 int num_counters,
756 size_t *offsets)
757{
758 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
759 struct mlx5_core_dev *mdev[MLX5_MAX_PORTS];
760 struct mlx5_lag *ldev;
761 int num_ports;
762 int ret, i, j;
763 void *out;
764
765 out = kvzalloc(outlen, GFP_KERNEL);
766 if (!out)
767 return -ENOMEM;
768
769 memset(values, 0, sizeof(*values) * num_counters);
770
64363e61 771 spin_lock(&lag_lock);
71a0ff65 772 ldev = mlx5_lag_dev_get(dev);
093bd764 773 if (ldev && __mlx5_lag_is_active(ldev)) {
71a0ff65 774 num_ports = MLX5_MAX_PORTS;
84d2dbb0
EA		 775 mdev[MLX5_LAG_P1] = ldev->pf[MLX5_LAG_P1].dev;
776 mdev[MLX5_LAG_P2] = ldev->pf[MLX5_LAG_P2].dev;
71a0ff65
MD		 777 } else {
778 num_ports = 1;
84d2dbb0 779 mdev[MLX5_LAG_P1] = dev;
71a0ff65 780 }
64363e61 781 spin_unlock(&lag_lock);
71a0ff65
MD		 782
783 for (i = 0; i < num_ports; ++i) {
5d19395f
LR		 784 u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = {};
785
786 MLX5_SET(query_cong_statistics_in, in, opcode,
787 MLX5_CMD_OP_QUERY_CONG_STATISTICS);
788 ret = mlx5_cmd_exec_inout(mdev[i], query_cong_statistics, in,
789 out);
71a0ff65 790 if (ret)
64363e61 791 goto free;
71a0ff65
MD		 792
793 for (j = 0; j < num_counters; ++j)
794 values[j] += be64_to_cpup((__be64 *)(out + offsets[j]));
795 }
796
64363e61 797free:
71a0ff65
MD		 798 kvfree(out);
799 return ret;
800}
801EXPORT_SYMBOL(mlx5_lag_query_cong_counters);
Linux 6.x block layer and io_uring tree(s)