projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: dsa: dsa_loop: Make dynamic debugging helpful
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
37#include <linux/mlx5/fs.h>
38#include "mlx5_core.h"
39#include "eswitch.h"
40
1033665e
OG		 41enum {
42 FDB_FAST_PATH = 0,
43 FDB_SLOW_PATH
44};
45
74491de9 46struct mlx5_flow_handle *
3d80d1a2
OG		 47mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
48 struct mlx5_flow_spec *spec,
776b12b6 49 struct mlx5_esw_flow_attr *attr)
3d80d1a2 50{
e37a79e5 51 struct mlx5_flow_destination dest[2] = {};
66958ed9 52 struct mlx5_flow_act flow_act = {0};
3d80d1a2 53 struct mlx5_fc *counter = NULL;
74491de9 54 struct mlx5_flow_handle *rule;
3d80d1a2 55 void *misc;
e37a79e5 56 int i = 0;
3d80d1a2
OG		 57
58 if (esw->mode != SRIOV_OFFLOADS)
59 return ERR_PTR(-EOPNOTSUPP);
60
6acfbf38
OG		 61 flow_act.action = attr->action;
62 /* if per flow vlan pop/push is emulated, don't set that into the firmware */
63 if (!mlx5_eswitch_vlan_actions_supported(esw->dev))
64 flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
65 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
66 else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
67 flow_act.vlan.ethtype = ntohs(attr->vlan_proto);
68 flow_act.vlan.vid = attr->vlan_vid;
69 flow_act.vlan.prio = attr->vlan_prio;
70 }
776b12b6 71
66958ed9 72 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
e37a79e5 73 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
b17f7fc1 74 dest[i].vport.num = attr->out_rep->vport;
56e858df
RL		 75 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
76 dest[i].vport.vhca_id =
77 MLX5_CAP_GEN(attr->out_mdev, vhca_id);
78 dest[i].vport.vhca_id_valid = 1;
79 }
e37a79e5
MB		 80 i++;
81 }
66958ed9 82 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3d80d1a2 83 counter = mlx5_fc_create(esw->dev, true);
aa0cbbae
OG		 84 if (IS_ERR(counter)) {
85 rule = ERR_CAST(counter);
86 goto err_counter_alloc;
87 }
e37a79e5
MB		 88 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
89 dest[i].counter = counter;
90 i++;
3d80d1a2
OG		 91 }
92
93 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
776b12b6 94 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport);
3d80d1a2 95
10ff5359
SK		 96 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
97 MLX5_SET(fte_match_set_misc, misc,
98 source_eswitch_owner_vhca_id,
99 MLX5_CAP_GEN(attr->in_mdev, vhca_id));
100
3d80d1a2
OG		 101 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
102 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
10ff5359
SK		 103 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
104 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
105 source_eswitch_owner_vhca_id);
3d80d1a2 106
38aa51c1
OG		 107 if (attr->match_level == MLX5_MATCH_NONE)
108 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
109 else
110 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS |
111 MLX5_MATCH_MISC_PARAMETERS;
112
bbd00f7e
HHZ		 113 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
114 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 115
aa24670e 116 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
d7e75a32
OG		 117 flow_act.modify_id = attr->mod_hdr_id;
118
aa24670e 119 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
45247bf2 120 flow_act.encap_id = attr->encap_id;
a54e20b4 121
74491de9 122 rule = mlx5_add_flow_rules((struct mlx5_flow_table *)esw->fdb_table.fdb,
66958ed9 123 spec, &flow_act, dest, i);
3d80d1a2 124 if (IS_ERR(rule))
aa0cbbae 125 goto err_add_rule;
375f51e2
RD		 126 else
127 esw->offloads.num_flows++;
3d80d1a2
OG		 128
129 return rule;
aa0cbbae
OG		 130
131err_add_rule:
132 mlx5_fc_destroy(esw->dev, counter);
133err_counter_alloc:
134 return rule;
3d80d1a2
OG		 135}
136
d85cdccb
OG		 137void
138mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
139 struct mlx5_flow_handle *rule,
140 struct mlx5_esw_flow_attr *attr)
141{
142 struct mlx5_fc *counter = NULL;
143
aa0cbbae
OG		 144 counter = mlx5_flow_rule_counter(rule);
145 mlx5_del_flow_rules(rule);
146 mlx5_fc_destroy(esw->dev, counter);
147 esw->offloads.num_flows--;
d85cdccb
OG		 148}
149
f5f82476
OG		 150static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val)
151{
152 struct mlx5_eswitch_rep *rep;
153 int vf_vport, err = 0;
154
155 esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none");
156 for (vf_vport = 1; vf_vport < esw->enabled_vports; vf_vport++) {
157 rep = &esw->offloads.vport_reps[vf_vport];
a4b97ab4 158 if (!rep->rep_if[REP_ETH].valid)
f5f82476
OG		 159 continue;
160
161 err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val);
162 if (err)
163 goto out;
164 }
165
166out:
167 return err;
168}
169
170static struct mlx5_eswitch_rep *
171esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop)
172{
173 struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL;
174
175 in_rep = attr->in_rep;
176 out_rep = attr->out_rep;
177
178 if (push)
179 vport = in_rep;
180 else if (pop)
181 vport = out_rep;
182 else
183 vport = in_rep;
184
185 return vport;
186}
187
188static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr,
189 bool push, bool pop, bool fwd)
190{
191 struct mlx5_eswitch_rep *in_rep, *out_rep;
192
193 if ((push || pop) && !fwd)
194 goto out_notsupp;
195
196 in_rep = attr->in_rep;
197 out_rep = attr->out_rep;
198
199 if (push && in_rep->vport == FDB_UPLINK_VPORT)
200 goto out_notsupp;
201
202 if (pop && out_rep->vport == FDB_UPLINK_VPORT)
203 goto out_notsupp;
204
205 /* vport has vlan push configured, can't offload VF --> wire rules w.o it */
206 if (!push && !pop && fwd)
207 if (in_rep->vlan && out_rep->vport == FDB_UPLINK_VPORT)
208 goto out_notsupp;
209
210 /* protects against (1) setting rules with different vlans to push and
211 * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0)
212 */
6acfbf38 213 if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid))
f5f82476
OG		 214 goto out_notsupp;
215
216 return 0;
217
218out_notsupp:
9eb78923 219 return -EOPNOTSUPP;
f5f82476
OG		 220}
221
222int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
223 struct mlx5_esw_flow_attr *attr)
224{
225 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
226 struct mlx5_eswitch_rep *vport = NULL;
227 bool push, pop, fwd;
228 int err = 0;
229
6acfbf38
OG		 230 /* nop if we're on the vlan push/pop non emulation mode */
231 if (mlx5_eswitch_vlan_actions_supported(esw->dev))
232 return 0;
233
f5f82476
OG		 234 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
235 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
236 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
237
238 err = esw_add_vlan_action_check(attr, push, pop, fwd);
239 if (err)
240 return err;
241
242 attr->vlan_handled = false;
243
244 vport = esw_vlan_action_get_vport(attr, push, pop);
245
246 if (!push && !pop && fwd) {
247 /* tracks VF --> wire rules without vlan push action */
248 if (attr->out_rep->vport == FDB_UPLINK_VPORT) {
249 vport->vlan_refcount++;
250 attr->vlan_handled = true;
251 }
252
253 return 0;
254 }
255
256 if (!push && !pop)
257 return 0;
258
259 if (!(offloads->vlan_push_pop_refcount)) {
260 /* it's the 1st vlan rule, apply global vlan pop policy */
261 err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP);
262 if (err)
263 goto out;
264 }
265 offloads->vlan_push_pop_refcount++;
266
267 if (push) {
268 if (vport->vlan_refcount)
269 goto skip_set_push;
270
6acfbf38 271 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, attr->vlan_vid, 0,
f5f82476
OG		 272 SET_VLAN_INSERT | SET_VLAN_STRIP);
273 if (err)
274 goto out;
6acfbf38 275 vport->vlan = attr->vlan_vid;
f5f82476
OG		 276skip_set_push:
277 vport->vlan_refcount++;
278 }
279out:
280 if (!err)
281 attr->vlan_handled = true;
282 return err;
283}
284
285int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
286 struct mlx5_esw_flow_attr *attr)
287{
288 struct offloads_fdb *offloads = &esw->fdb_table.offloads;
289 struct mlx5_eswitch_rep *vport = NULL;
290 bool push, pop, fwd;
291 int err = 0;
292
6acfbf38
OG		 293 /* nop if we're on the vlan push/pop non emulation mode */
294 if (mlx5_eswitch_vlan_actions_supported(esw->dev))
295 return 0;
296
f5f82476
OG		 297 if (!attr->vlan_handled)
298 return 0;
299
300 push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH);
301 pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
302 fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
303
304 vport = esw_vlan_action_get_vport(attr, push, pop);
305
306 if (!push && !pop && fwd) {
307 /* tracks VF --> wire rules without vlan push action */
308 if (attr->out_rep->vport == FDB_UPLINK_VPORT)
309 vport->vlan_refcount--;
310
311 return 0;
312 }
313
314 if (push) {
315 vport->vlan_refcount--;
316 if (vport->vlan_refcount)
317 goto skip_unset_push;
318
319 vport->vlan = 0;
320 err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport,
321 0, 0, SET_VLAN_STRIP);
322 if (err)
323 goto out;
324 }
325
326skip_unset_push:
327 offloads->vlan_push_pop_refcount--;
328 if (offloads->vlan_push_pop_refcount)
329 return 0;
330
331 /* no more vlan rules, stop global vlan pop policy */
332 err = esw_set_global_vlan_pop(esw, 0);
333
334out:
335 return err;
336}
337
f7a68945 338struct mlx5_flow_handle *
ab22be9b
OG		 339mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *esw, int vport, u32 sqn)
340{
66958ed9 341 struct mlx5_flow_act flow_act = {0};
4c5009c5 342 struct mlx5_flow_destination dest = {};
74491de9 343 struct mlx5_flow_handle *flow_rule;
c5bb1730 344 struct mlx5_flow_spec *spec;
ab22be9b
OG		 345 void *misc;
346
1b9a07ee 347 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 348 if (!spec) {
ab22be9b
OG		 349 flow_rule = ERR_PTR(-ENOMEM);
350 goto out;
351 }
352
c5bb1730 353 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b
OG		 354 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
355 MLX5_SET(fte_match_set_misc, misc, source_port, 0x0); /* source vport is 0 */
356
c5bb1730 357 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b
OG		 358 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
359 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
360
c5bb1730 361 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
ab22be9b 362 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
b17f7fc1 363 dest.vport.num = vport;
66958ed9 364 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 365
74491de9 366 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.fdb, spec,
66958ed9 367 &flow_act, &dest, 1);
ab22be9b
OG		 368 if (IS_ERR(flow_rule))
369 esw_warn(esw->dev, "FDB: Failed to add send to vport rule err %ld\n", PTR_ERR(flow_rule));
370out:
c5bb1730 371 kvfree(spec);
ab22be9b
OG		 372 return flow_rule;
373}
57cbd893 374EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 375
159fe639
MB		 376void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
377{
378 mlx5_del_flow_rules(rule);
379}
380
3aa33572
OG		 381static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
382{
66958ed9 383 struct mlx5_flow_act flow_act = {0};
4c5009c5 384 struct mlx5_flow_destination dest = {};
74491de9 385 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 386 struct mlx5_flow_spec *spec;
f80be543
MB		 387 void *headers_c;
388 void *headers_v;
3aa33572 389 int err = 0;
f80be543
MB		 390 u8 *dmac_c;
391 u8 *dmac_v;
3aa33572 392
1b9a07ee 393 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 394 if (!spec) {
3aa33572
OG		 395 err = -ENOMEM;
396 goto out;
397 }
398
f80be543
MB		 399 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
400 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
401 outer_headers);
402 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
403 outer_headers.dmac_47_16);
404 dmac_c[0] = 0x01;
405
3aa33572 406 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
b17f7fc1 407 dest.vport.num = 0;
66958ed9 408 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 409
74491de9 410 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.fdb, spec,
66958ed9 411 &flow_act, &dest, 1);
3aa33572
OG		 412 if (IS_ERR(flow_rule)) {
413 err = PTR_ERR(flow_rule);
f80be543 414 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 415 goto out;
416 }
417
f80be543
MB		 418 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
419
420 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
421 outer_headers);
422 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
423 outer_headers.dmac_47_16);
424 dmac_v[0] = 0x01;
425 flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.fdb, spec,
426 &flow_act, &dest, 1);
427 if (IS_ERR(flow_rule)) {
428 err = PTR_ERR(flow_rule);
429 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
430 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
431 goto out;
432 }
433
434 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
435
3aa33572 436out:
c5bb1730 437 kvfree(spec);
3aa33572
OG		 438 return err;
439}
440
1033665e 441#define ESW_OFFLOADS_NUM_GROUPS 4
69697b6e 442
1967ce6e 443static int esw_create_offloads_fast_fdb_table(struct mlx5_eswitch *esw)
69697b6e 444{
69697b6e
OG		 445 struct mlx5_core_dev *dev = esw->dev;
446 struct mlx5_flow_namespace *root_ns;
447 struct mlx5_flow_table *fdb = NULL;
1967ce6e 448 int esw_size, err = 0;
bbd00f7e 449 u32 flags = 0;
a8ffcc74
RL		 450 u32 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
451 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
69697b6e 452
69697b6e
OG		 453 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
454 if (!root_ns) {
455 esw_warn(dev, "Failed to get FDB flow namespace\n");
5403dc70 456 err = -EOPNOTSUPP;
1967ce6e 457 goto out;
69697b6e
OG		 458 }
459
264d7bf3
OG		 460 esw_debug(dev, "Create offloads FDB table, min (max esw size(2^%d), max counters(%d)*groups(%d))\n",
461 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size),
a8ffcc74 462 max_flow_counter, ESW_OFFLOADS_NUM_GROUPS);
264d7bf3 463
a8ffcc74 464 esw_size = min_t(int, max_flow_counter * ESW_OFFLOADS_NUM_GROUPS,
264d7bf3 465 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
69697b6e 466
7768d197 467 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
bbd00f7e
HHZ		 468 flags |= MLX5_FLOW_TABLE_TUNNEL_EN;
469
1033665e 470 fdb = mlx5_create_auto_grouped_flow_table(root_ns, FDB_FAST_PATH,
264d7bf3 471 esw_size,
c9f1b073 472 ESW_OFFLOADS_NUM_GROUPS, 0,
bbd00f7e 473 flags);
69697b6e
OG		 474 if (IS_ERR(fdb)) {
475 err = PTR_ERR(fdb);
1033665e 476 esw_warn(dev, "Failed to create Fast path FDB Table err %d\n", err);
1967ce6e 477 goto out;
69697b6e
OG		 478 }
479 esw->fdb_table.fdb = fdb;
480
1967ce6e
OG		 481out:
482 return err;
483}
484
485static void esw_destroy_offloads_fast_fdb_table(struct mlx5_eswitch *esw)
486{
487 mlx5_destroy_flow_table(esw->fdb_table.fdb);
488}
489
490#define MAX_PF_SQ 256
cd3d07e7 491#define MAX_SQ_NVPORTS 32
1967ce6e
OG		 492
493static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw, int nvports)
494{
495 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
496 struct mlx5_flow_table_attr ft_attr = {};
497 struct mlx5_core_dev *dev = esw->dev;
498 struct mlx5_flow_namespace *root_ns;
499 struct mlx5_flow_table *fdb = NULL;
500 int table_size, ix, err = 0;
501 struct mlx5_flow_group *g;
502 void *match_criteria;
503 u32 *flow_group_in;
f80be543 504 u8 *dmac;
1967ce6e
OG		 505
506 esw_debug(esw->dev, "Create offloads FDB Tables\n");
1b9a07ee 507 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 508 if (!flow_group_in)
509 return -ENOMEM;
510
511 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
512 if (!root_ns) {
513 esw_warn(dev, "Failed to get FDB flow namespace\n");
514 err = -EOPNOTSUPP;
515 goto ns_err;
516 }
517
518 err = esw_create_offloads_fast_fdb_table(esw);
519 if (err)
520 goto fast_fdb_err;
521
f80be543 522 table_size = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ + 2;
b3ba5149
ES		 523
524 ft_attr.max_fte = table_size;
525 ft_attr.prio = FDB_SLOW_PATH;
526
527 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 528 if (IS_ERR(fdb)) {
529 err = PTR_ERR(fdb);
530 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
531 goto slow_fdb_err;
532 }
533 esw->fdb_table.offloads.fdb = fdb;
534
69697b6e
OG		 535 /* create send-to-vport group */
536 memset(flow_group_in, 0, inlen);
537 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
538 MLX5_MATCH_MISC_PARAMETERS);
539
540 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
541
542 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
543 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
544
cd3d07e7 545 ix = nvports * MAX_SQ_NVPORTS + MAX_PF_SQ;
69697b6e
OG		 546 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
547 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1);
548
549 g = mlx5_create_flow_group(fdb, flow_group_in);
550 if (IS_ERR(g)) {
551 err = PTR_ERR(g);
552 esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err);
553 goto send_vport_err;
554 }
555 esw->fdb_table.offloads.send_to_vport_grp = g;
556
557 /* create miss group */
558 memset(flow_group_in, 0, inlen);
f80be543
MB		 559 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
560 MLX5_MATCH_OUTER_HEADERS);
561 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
562 match_criteria);
563 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
564 outer_headers.dmac_47_16);
565 dmac[0] = 0x01;
69697b6e
OG		 566
567 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix);
f80be543 568 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix + 2);
69697b6e
OG		 569
570 g = mlx5_create_flow_group(fdb, flow_group_in);
571 if (IS_ERR(g)) {
572 err = PTR_ERR(g);
573 esw_warn(dev, "Failed to create miss flow group err(%d)\n", err);
574 goto miss_err;
575 }
576 esw->fdb_table.offloads.miss_grp = g;
577
3aa33572
OG		 578 err = esw_add_fdb_miss_rule(esw);
579 if (err)
580 goto miss_rule_err;
581
69697b6e
OG		 582 return 0;
583
3aa33572
OG		 584miss_rule_err:
585 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
69697b6e
OG		 586miss_err:
587 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
588send_vport_err:
1033665e
OG		 589 mlx5_destroy_flow_table(esw->fdb_table.offloads.fdb);
590slow_fdb_err:
591 mlx5_destroy_flow_table(esw->fdb_table.fdb);
592fast_fdb_err:
69697b6e
OG		 593ns_err:
594 kvfree(flow_group_in);
595 return err;
596}
597
1967ce6e 598static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e
OG		 599{
600 if (!esw->fdb_table.fdb)
601 return;
602
1967ce6e 603 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 604 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
605 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e
OG		 606 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
607 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
608
1033665e 609 mlx5_destroy_flow_table(esw->fdb_table.offloads.fdb);
1967ce6e 610 esw_destroy_offloads_fast_fdb_table(esw);
69697b6e 611}
c116c6ee
OG		 612
613static int esw_create_offloads_table(struct mlx5_eswitch *esw)
614{
b3ba5149 615 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 616 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 617 struct mlx5_flow_table *ft_offloads;
618 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 619 int err = 0;
620
621 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
622 if (!ns) {
623 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 624 return -EOPNOTSUPP;
c116c6ee
OG		 625 }
626
b3ba5149
ES		 627 ft_attr.max_fte = dev->priv.sriov.num_vfs + 2;
628
629 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 630 if (IS_ERR(ft_offloads)) {
631 err = PTR_ERR(ft_offloads);
632 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
633 return err;
634 }
635
636 esw->offloads.ft_offloads = ft_offloads;
637 return 0;
638}
639
640static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
641{
642 struct mlx5_esw_offload *offloads = &esw->offloads;
643
644 mlx5_destroy_flow_table(offloads->ft_offloads);
645}
fed9ce22
OG		 646
647static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
648{
649 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
650 struct mlx5_flow_group *g;
651 struct mlx5_priv *priv = &esw->dev->priv;
652 u32 *flow_group_in;
653 void *match_criteria, *misc;
654 int err = 0;
655 int nvports = priv->sriov.num_vfs + 2;
656
1b9a07ee 657 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 658 if (!flow_group_in)
659 return -ENOMEM;
660
661 /* create vport rx group */
662 memset(flow_group_in, 0, inlen);
663 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
664 MLX5_MATCH_MISC_PARAMETERS);
665
666 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
667 misc = MLX5_ADDR_OF(fte_match_param, match_criteria, misc_parameters);
668 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
669
670 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
671 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
672
673 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
674
675 if (IS_ERR(g)) {
676 err = PTR_ERR(g);
677 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
678 goto out;
679 }
680
681 esw->offloads.vport_rx_group = g;
682out:
e574978a 683 kvfree(flow_group_in);
fed9ce22
OG		 684 return err;
685}
686
687static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
688{
689 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
690}
691
74491de9 692struct mlx5_flow_handle *
fed9ce22
OG		 693mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn)
694{
66958ed9 695 struct mlx5_flow_act flow_act = {0};
4c5009c5 696 struct mlx5_flow_destination dest = {};
74491de9 697 struct mlx5_flow_handle *flow_rule;
c5bb1730 698 struct mlx5_flow_spec *spec;
fed9ce22
OG		 699 void *misc;
700
1b9a07ee 701 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 702 if (!spec) {
fed9ce22
OG		 703 flow_rule = ERR_PTR(-ENOMEM);
704 goto out;
705 }
706
c5bb1730 707 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
fed9ce22
OG		 708 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
709
c5bb1730 710 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
fed9ce22
OG		 711 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
712
c5bb1730 713 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
fed9ce22
OG		 714 dest.type = MLX5_FLOW_DESTINATION_TYPE_TIR;
715 dest.tir_num = tirn;
716
66958ed9 717 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 718 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
e53eef63 719 &flow_act, &dest, 1);
fed9ce22
OG		 720 if (IS_ERR(flow_rule)) {
721 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
722 goto out;
723 }
724
725out:
c5bb1730 726 kvfree(spec);
fed9ce22
OG		 727 return flow_rule;
728}
feae9087 729
c930a3ad
OG		 730static int esw_offloads_start(struct mlx5_eswitch *esw)
731{
6c419ba8 732 int err, err1, num_vfs = esw->dev->priv.sriov.num_vfs;
c930a3ad
OG		 733
734 if (esw->mode != SRIOV_LEGACY) {
735 esw_warn(esw->dev, "Can't set offloads mode, SRIOV legacy not enabled\n");
736 return -EINVAL;
737 }
738
739 mlx5_eswitch_disable_sriov(esw);
740 err = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_OFFLOADS);
6c419ba8
OG		 741 if (err) {
742 esw_warn(esw->dev, "Failed setting eswitch to offloads, err %d\n", err);
743 err1 = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_LEGACY);
744 if (err1)
5403dc70 745 esw_warn(esw->dev, "Failed setting eswitch back to legacy, err %d\n", err1);
6c419ba8 746 }
bffaa916
RD		 747 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
748 if (mlx5_eswitch_inline_mode_get(esw,
749 num_vfs,
750 &esw->offloads.inline_mode)) {
751 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
752 esw_warn(esw->dev, "Inline mode is different between vports\n");
753 }
754 }
c930a3ad
OG		 755 return err;
756}
757
e8d31c4d
MB		 758void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
759{
760 kfree(esw->offloads.vport_reps);
761}
762
763int esw_offloads_init_reps(struct mlx5_eswitch *esw)
764{
765 int total_vfs = MLX5_TOTAL_VPORTS(esw->dev);
766 struct mlx5_core_dev *dev = esw->dev;
767 struct mlx5_esw_offload *offloads;
768 struct mlx5_eswitch_rep *rep;
769 u8 hw_id[ETH_ALEN];
770 int vport;
771
772 esw->offloads.vport_reps = kcalloc(total_vfs,
773 sizeof(struct mlx5_eswitch_rep),
774 GFP_KERNEL);
775 if (!esw->offloads.vport_reps)
776 return -ENOMEM;
777
778 offloads = &esw->offloads;
779 mlx5_query_nic_vport_mac_address(dev, 0, hw_id);
780
781 for (vport = 0; vport < total_vfs; vport++) {
782 rep = &offloads->vport_reps[vport];
783
784 rep->vport = vport;
785 ether_addr_copy(rep->hw_id, hw_id);
786 }
787
788 offloads->vport_reps[0].vport = FDB_UPLINK_VPORT;
789
790 return 0;
791}
792
a4b97ab4
MB		 793static void esw_offloads_unload_reps_type(struct mlx5_eswitch *esw, int nvports,
794 u8 rep_type)
6ed1803a
MB		 795{
796 struct mlx5_eswitch_rep *rep;
797 int vport;
798
799 for (vport = nvports - 1; vport >= 0; vport--) {
800 rep = &esw->offloads.vport_reps[vport];
a4b97ab4 801 if (!rep->rep_if[rep_type].valid)
6ed1803a
MB		 802 continue;
803
a4b97ab4 804 rep->rep_if[rep_type].unload(rep);
6ed1803a
MB		 805 }
806}
807
a4b97ab4
MB		 808static void esw_offloads_unload_reps(struct mlx5_eswitch *esw, int nvports)
809{
810 u8 rep_type = NUM_REP_TYPES;
811
812 while (rep_type-- > 0)
813 esw_offloads_unload_reps_type(esw, nvports, rep_type);
814}
815
816static int esw_offloads_load_reps_type(struct mlx5_eswitch *esw, int nvports,
817 u8 rep_type)
c930a3ad 818{
cb67b832
HHZ		 819 struct mlx5_eswitch_rep *rep;
820 int vport;
c930a3ad
OG		 821 int err;
822
6ed1803a
MB		 823 for (vport = 0; vport < nvports; vport++) {
824 rep = &esw->offloads.vport_reps[vport];
a4b97ab4 825 if (!rep->rep_if[rep_type].valid)
6ed1803a
MB		 826 continue;
827
a4b97ab4 828 err = rep->rep_if[rep_type].load(esw->dev, rep);
6ed1803a
MB		 829 if (err)
830 goto err_reps;
831 }
832
833 return 0;
834
835err_reps:
a4b97ab4
MB		 836 esw_offloads_unload_reps_type(esw, vport, rep_type);
837 return err;
838}
839
840static int esw_offloads_load_reps(struct mlx5_eswitch *esw, int nvports)
841{
842 u8 rep_type = 0;
843 int err;
844
845 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
846 err = esw_offloads_load_reps_type(esw, nvports, rep_type);
847 if (err)
848 goto err_reps;
849 }
850
851 return err;
852
853err_reps:
854 while (rep_type-- > 0)
855 esw_offloads_unload_reps_type(esw, nvports, rep_type);
6ed1803a
MB		 856 return err;
857}
858
859int esw_offloads_init(struct mlx5_eswitch *esw, int nvports)
860{
861 int err;
862
1967ce6e 863 err = esw_create_offloads_fdb_tables(esw, nvports);
c930a3ad 864 if (err)
c5447c70 865 return err;
c930a3ad
OG		 866
867 err = esw_create_offloads_table(esw);
868 if (err)
869 goto create_ft_err;
870
871 err = esw_create_vport_rx_group(esw);
872 if (err)
873 goto create_fg_err;
874
6ed1803a
MB		 875 err = esw_offloads_load_reps(esw, nvports);
876 if (err)
877 goto err_reps;
9da34cd3 878
c930a3ad
OG		 879 return 0;
880
cb67b832 881err_reps:
cb67b832
HHZ		 882 esw_destroy_vport_rx_group(esw);
883
c930a3ad
OG		 884create_fg_err:
885 esw_destroy_offloads_table(esw);
886
887create_ft_err:
1967ce6e 888 esw_destroy_offloads_fdb_tables(esw);
5bae8c03 889
c930a3ad
OG		 890 return err;
891}
892
893static int esw_offloads_stop(struct mlx5_eswitch *esw)
894{
6c419ba8 895 int err, err1, num_vfs = esw->dev->priv.sriov.num_vfs;
c930a3ad
OG		 896
897 mlx5_eswitch_disable_sriov(esw);
898 err = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_LEGACY);
6c419ba8
OG		 899 if (err) {
900 esw_warn(esw->dev, "Failed setting eswitch to legacy, err %d\n", err);
901 err1 = mlx5_eswitch_enable_sriov(esw, num_vfs, SRIOV_OFFLOADS);
902 if (err1)
903 esw_warn(esw->dev, "Failed setting eswitch back to offloads, err %d\n", err);
904 }
c930a3ad 905
5bae8c03 906 /* enable back PF RoCE */
c5447c70 907 mlx5_reload_interface(esw->dev, MLX5_INTERFACE_PROTOCOL_IB);
5bae8c03 908
c930a3ad
OG		 909 return err;
910}
911
912void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports)
913{
6ed1803a 914 esw_offloads_unload_reps(esw, nvports);
c930a3ad
OG		 915 esw_destroy_vport_rx_group(esw);
916 esw_destroy_offloads_table(esw);
1967ce6e 917 esw_destroy_offloads_fdb_tables(esw);
c930a3ad
OG		 918}
919
ef78618b 920static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 921{
922 switch (mode) {
923 case DEVLINK_ESWITCH_MODE_LEGACY:
924 *mlx5_mode = SRIOV_LEGACY;
925 break;
926 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
927 *mlx5_mode = SRIOV_OFFLOADS;
928 break;
929 default:
930 return -EINVAL;
931 }
932
933 return 0;
934}
935
ef78618b
OG		 936static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
937{
938 switch (mlx5_mode) {
939 case SRIOV_LEGACY:
940 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
941 break;
942 case SRIOV_OFFLOADS:
943 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
944 break;
945 default:
946 return -EINVAL;
947 }
948
949 return 0;
950}
951
bffaa916
RD		 952static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
953{
954 switch (mode) {
955 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
956 *mlx5_mode = MLX5_INLINE_MODE_NONE;
957 break;
958 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
959 *mlx5_mode = MLX5_INLINE_MODE_L2;
960 break;
961 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
962 *mlx5_mode = MLX5_INLINE_MODE_IP;
963 break;
964 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
965 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
966 break;
967 default:
968 return -EINVAL;
969 }
970
971 return 0;
972}
973
974static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
975{
976 switch (mlx5_mode) {
977 case MLX5_INLINE_MODE_NONE:
978 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
979 break;
980 case MLX5_INLINE_MODE_L2:
981 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
982 break;
983 case MLX5_INLINE_MODE_IP:
984 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
985 break;
986 case MLX5_INLINE_MODE_TCP_UDP:
987 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
988 break;
989 default:
990 return -EINVAL;
991 }
992
993 return 0;
994}
995
9d1cef19 996static int mlx5_devlink_eswitch_check(struct devlink *devlink)
feae9087 997{
9d1cef19 998 struct mlx5_core_dev *dev = devlink_priv(devlink);
c930a3ad 999
9d1cef19
OG		 1000 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1001 return -EOPNOTSUPP;
c930a3ad
OG		 1002
1003 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1004 return -EOPNOTSUPP;
1005
9d1cef19 1006 if (dev->priv.eswitch->mode == SRIOV_NONE)
c930a3ad
OG		 1007 return -EOPNOTSUPP;
1008
9d1cef19
OG		 1009 return 0;
1010}
1011
1012int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode)
1013{
1014 struct mlx5_core_dev *dev = devlink_priv(devlink);
1015 u16 cur_mlx5_mode, mlx5_mode = 0;
1016 int err;
1017
1018 err = mlx5_devlink_eswitch_check(devlink);
1019 if (err)
1020 return err;
1021
1022 cur_mlx5_mode = dev->priv.eswitch->mode;
1023
ef78618b 1024 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 1025 return -EINVAL;
1026
1027 if (cur_mlx5_mode == mlx5_mode)
1028 return 0;
1029
1030 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV)
1031 return esw_offloads_start(dev->priv.eswitch);
1032 else if (mode == DEVLINK_ESWITCH_MODE_LEGACY)
1033 return esw_offloads_stop(dev->priv.eswitch);
1034 else
1035 return -EINVAL;
feae9087
OG		 1036}
1037
1038int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
1039{
9d1cef19
OG		 1040 struct mlx5_core_dev *dev = devlink_priv(devlink);
1041 int err;
c930a3ad 1042
9d1cef19
OG		 1043 err = mlx5_devlink_eswitch_check(devlink);
1044 if (err)
1045 return err;
c930a3ad 1046
ef78618b 1047 return esw_mode_to_devlink(dev->priv.eswitch->mode, mode);
feae9087 1048}
127ea380 1049
bffaa916
RD		 1050int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode)
1051{
1052 struct mlx5_core_dev *dev = devlink_priv(devlink);
1053 struct mlx5_eswitch *esw = dev->priv.eswitch;
c415f704 1054 int err, vport;
bffaa916
RD		 1055 u8 mlx5_mode;
1056
9d1cef19
OG		 1057 err = mlx5_devlink_eswitch_check(devlink);
1058 if (err)
1059 return err;
bffaa916 1060
c415f704
OG		 1061 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1062 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1063 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE)
1064 return 0;
1065 /* fall through */
1066 case MLX5_CAP_INLINE_MODE_L2:
1067 esw_warn(dev, "Inline mode can't be set\n");
bffaa916 1068 return -EOPNOTSUPP;
c415f704
OG		 1069 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1070 break;
1071 }
bffaa916 1072
375f51e2
RD		 1073 if (esw->offloads.num_flows > 0) {
1074 esw_warn(dev, "Can't set inline mode when flows are configured\n");
1075 return -EOPNOTSUPP;
1076 }
1077
bffaa916
RD		 1078 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
1079 if (err)
1080 goto out;
1081
9d1cef19 1082 for (vport = 1; vport < esw->enabled_vports; vport++) {
bffaa916
RD		 1083 err = mlx5_modify_nic_vport_min_inline(dev, vport, mlx5_mode);
1084 if (err) {
1085 esw_warn(dev, "Failed to set min inline on vport %d\n",
1086 vport);
1087 goto revert_inline_mode;
1088 }
1089 }
1090
1091 esw->offloads.inline_mode = mlx5_mode;
1092 return 0;
1093
1094revert_inline_mode:
1095 while (--vport > 0)
1096 mlx5_modify_nic_vport_min_inline(dev,
1097 vport,
1098 esw->offloads.inline_mode);
1099out:
1100 return err;
1101}
1102
1103int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
1104{
1105 struct mlx5_core_dev *dev = devlink_priv(devlink);
1106 struct mlx5_eswitch *esw = dev->priv.eswitch;
9d1cef19 1107 int err;
bffaa916 1108
9d1cef19
OG		 1109 err = mlx5_devlink_eswitch_check(devlink);
1110 if (err)
1111 return err;
bffaa916 1112
bffaa916
RD		 1113 return esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
1114}
1115
1116int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode)
1117{
c415f704 1118 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
bffaa916
RD		 1119 struct mlx5_core_dev *dev = esw->dev;
1120 int vport;
bffaa916
RD		 1121
1122 if (!MLX5_CAP_GEN(dev, vport_group_manager))
1123 return -EOPNOTSUPP;
1124
1125 if (esw->mode == SRIOV_NONE)
1126 return -EOPNOTSUPP;
1127
c415f704
OG		 1128 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
1129 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1130 mlx5_mode = MLX5_INLINE_MODE_NONE;
1131 goto out;
1132 case MLX5_CAP_INLINE_MODE_L2:
1133 mlx5_mode = MLX5_INLINE_MODE_L2;
1134 goto out;
1135 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1136 goto query_vports;
1137 }
bffaa916 1138
c415f704 1139query_vports:
bffaa916
RD		 1140 for (vport = 1; vport <= nvfs; vport++) {
1141 mlx5_query_nic_vport_min_inline(dev, vport, &mlx5_mode);
1142 if (vport > 1 && prev_mlx5_mode != mlx5_mode)
1143 return -EINVAL;
1144 prev_mlx5_mode = mlx5_mode;
1145 }
1146
c415f704 1147out:
bffaa916
RD		 1148 *mode = mlx5_mode;
1149 return 0;
1150}
1151
7768d197
RD		 1152int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap)
1153{
1154 struct mlx5_core_dev *dev = devlink_priv(devlink);
1155 struct mlx5_eswitch *esw = dev->priv.eswitch;
1156 int err;
1157
9d1cef19
OG		 1158 err = mlx5_devlink_eswitch_check(devlink);
1159 if (err)
1160 return err;
7768d197
RD		 1161
1162 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
1163 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, encap) ||
1164 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap)))
1165 return -EOPNOTSUPP;
1166
1167 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC)
1168 return -EOPNOTSUPP;
1169
1170 if (esw->mode == SRIOV_LEGACY) {
1171 esw->offloads.encap = encap;
1172 return 0;
1173 }
1174
1175 if (esw->offloads.encap == encap)
1176 return 0;
1177
1178 if (esw->offloads.num_flows > 0) {
1179 esw_warn(dev, "Can't set encapsulation when flows are configured\n");
1180 return -EOPNOTSUPP;
1181 }
1182
1183 esw_destroy_offloads_fast_fdb_table(esw);
1184
1185 esw->offloads.encap = encap;
1186 err = esw_create_offloads_fast_fdb_table(esw);
1187 if (err) {
1188 esw_warn(esw->dev, "Failed re-creating fast FDB table, err %d\n", err);
1189 esw->offloads.encap = !encap;
2fe30e23 1190 (void)esw_create_offloads_fast_fdb_table(esw);
7768d197
RD		 1191 }
1192 return err;
1193}
1194
1195int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap)
1196{
1197 struct mlx5_core_dev *dev = devlink_priv(devlink);
1198 struct mlx5_eswitch *esw = dev->priv.eswitch;
9d1cef19 1199 int err;
7768d197 1200
9d1cef19
OG		 1201 err = mlx5_devlink_eswitch_check(devlink);
1202 if (err)
1203 return err;
7768d197
RD		 1204
1205 *encap = esw->offloads.encap;
1206 return 0;
1207}
1208
127ea380 1209void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw,
9deb2241 1210 int vport_index,
a4b97ab4
MB		 1211 struct mlx5_eswitch_rep_if *__rep_if,
1212 u8 rep_type)
127ea380
HHZ		 1213{
1214 struct mlx5_esw_offload *offloads = &esw->offloads;
a4b97ab4 1215 struct mlx5_eswitch_rep_if *rep_if;
9deb2241 1216
a4b97ab4 1217 rep_if = &offloads->vport_reps[vport_index].rep_if[rep_type];
127ea380 1218
a4b97ab4
MB		 1219 rep_if->load = __rep_if->load;
1220 rep_if->unload = __rep_if->unload;
22215908 1221 rep_if->get_proto_dev = __rep_if->get_proto_dev;
a4b97ab4 1222 rep_if->priv = __rep_if->priv;
127ea380 1223
a4b97ab4 1224 rep_if->valid = true;
127ea380 1225}
57cbd893 1226EXPORT_SYMBOL(mlx5_eswitch_register_vport_rep);
127ea380
HHZ		 1227
1228void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw,
a4b97ab4 1229 int vport_index, u8 rep_type)
127ea380
HHZ		 1230{
1231 struct mlx5_esw_offload *offloads = &esw->offloads;
cb67b832
HHZ		 1232 struct mlx5_eswitch_rep *rep;
1233
9deb2241 1234 rep = &offloads->vport_reps[vport_index];
cb67b832 1235
9deb2241 1236 if (esw->mode == SRIOV_OFFLOADS && esw->vports[vport_index].enabled)
a4b97ab4 1237 rep->rep_if[rep_type].unload(rep);
127ea380 1238
a4b97ab4 1239 rep->rep_if[rep_type].valid = false;
127ea380 1240}
57cbd893 1241EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_rep);
726293f1 1242
a4b97ab4 1243void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1
HHZ		 1244{
1245#define UPLINK_REP_INDEX 0
1246 struct mlx5_esw_offload *offloads = &esw->offloads;
1247 struct mlx5_eswitch_rep *rep;
1248
1249 rep = &offloads->vport_reps[UPLINK_REP_INDEX];
a4b97ab4 1250 return rep->rep_if[rep_type].priv;
726293f1 1251}
22215908
MB		 1252
1253void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
1254 int vport,
1255 u8 rep_type)
1256{
1257 struct mlx5_esw_offload *offloads = &esw->offloads;
1258 struct mlx5_eswitch_rep *rep;
1259
1260 if (vport == FDB_UPLINK_VPORT)
1261 vport = UPLINK_REP_INDEX;
1262
1263 rep = &offloads->vport_reps[vport];
1264
1265 if (rep->rep_if[rep_type].valid &&
1266 rep->rep_if[rep_type].get_proto_dev)
1267 return rep->rep_if[rep_type].get_proto_dev(rep);
1268 return NULL;
1269}
57cbd893 1270EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 1271
1272void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
1273{
1274 return mlx5_eswitch_get_proto_dev(esw, UPLINK_REP_INDEX, rep_type);
1275}
57cbd893
MB		 1276EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
1277
1278struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
1279 int vport)
1280{
1281 return &esw->offloads.vport_reps[vport];
1282}
1283EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
Linux 6.x block layer and io_uring tree(s)