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69697b6e OG |
1 | /* |
2 | * Copyright (c) 2016, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/etherdevice.h> | |
133dcfc5 | 34 | #include <linux/idr.h> |
69697b6e OG |
35 | #include <linux/mlx5/driver.h> |
36 | #include <linux/mlx5/mlx5_ifc.h> | |
37 | #include <linux/mlx5/vport.h> | |
38 | #include <linux/mlx5/fs.h> | |
39 | #include "mlx5_core.h" | |
40 | #include "eswitch.h" | |
34ca6535 | 41 | #include "esw/indir_table.h" |
ea651a86 | 42 | #include "esw/acl/ofld.h" |
80f09dfc | 43 | #include "rdma.h" |
e52c2802 PB |
44 | #include "en.h" |
45 | #include "fs_core.h" | |
ac004b83 | 46 | #include "lib/devcom.h" |
a3888f33 | 47 | #include "lib/eq.h" |
ae430332 | 48 | #include "lib/fs_chains.h" |
c620b772 | 49 | #include "en_tc.h" |
c9355682 | 50 | #include "en/mapping.h" |
69697b6e | 51 | |
47dd7e60 PP |
52 | #define mlx5_esw_for_each_rep(esw, i, rep) \ |
53 | xa_for_each(&((esw)->offloads.vport_reps), i, rep) | |
54 | ||
55 | #define mlx5_esw_for_each_sf_rep(esw, i, rep) \ | |
56 | xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF) | |
57 | ||
58 | #define mlx5_esw_for_each_vf_rep(esw, index, rep) \ | |
59 | mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \ | |
60 | rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF) | |
61 | ||
cd7e4186 BW |
62 | /* There are two match-all miss flows, one for unicast dst mac and |
63 | * one for multicast. | |
64 | */ | |
65 | #define MLX5_ESW_MISS_FLOWS (2) | |
c9b99abc BW |
66 | #define UPLINK_REP_INDEX 0 |
67 | ||
c796bb7c CM |
68 | #define MLX5_ESW_VPORT_TBL_SIZE 128 |
69 | #define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4 | |
70 | ||
71 | static const struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = { | |
72 | .max_fte = MLX5_ESW_VPORT_TBL_SIZE, | |
73 | .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS, | |
74 | .flags = 0, | |
75 | }; | |
76 | ||
879c8f84 BW |
77 | static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw, |
78 | u16 vport_num) | |
79 | { | |
47dd7e60 | 80 | return xa_load(&esw->offloads.vport_reps, vport_num); |
879c8f84 BW |
81 | } |
82 | ||
6f7bbad1 JL |
83 | static void |
84 | mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw, | |
85 | struct mlx5_flow_spec *spec, | |
86 | struct mlx5_esw_flow_attr *attr) | |
87 | { | |
88 | if (MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) && | |
036e19b9 HI |
89 | attr && attr->in_rep) |
90 | spec->flow_context.flow_source = | |
91 | attr->in_rep->vport == MLX5_VPORT_UPLINK ? | |
92 | MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK : | |
93 | MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT; | |
6f7bbad1 | 94 | } |
b7826076 | 95 | |
f94d6389 CM |
96 | /* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits |
97 | * are not needed as well in the following process. So clear them all for simplicity. | |
98 | */ | |
99 | void | |
100 | mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec) | |
101 | { | |
102 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { | |
103 | void *misc2; | |
104 | ||
105 | misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); | |
106 | MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0); | |
107 | ||
108 | misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2); | |
109 | MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0); | |
110 | ||
111 | if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2))) | |
112 | spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2; | |
113 | } | |
114 | } | |
115 | ||
c01cfd0f JL |
116 | static void |
117 | mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw, | |
118 | struct mlx5_flow_spec *spec, | |
a508728a | 119 | struct mlx5_flow_attr *attr, |
b055ecf5 MB |
120 | struct mlx5_eswitch *src_esw, |
121 | u16 vport) | |
c01cfd0f JL |
122 | { |
123 | void *misc2; | |
124 | void *misc; | |
125 | ||
126 | /* Use metadata matching because vport is not represented by single | |
127 | * VHCA in dual-port RoCE mode, and matching on source vport may fail. | |
128 | */ | |
129 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { | |
a508728a VB |
130 | if (mlx5_esw_indir_table_decap_vport(attr)) |
131 | vport = mlx5_esw_indir_table_decap_vport(attr); | |
c01cfd0f JL |
132 | misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); |
133 | MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, | |
b055ecf5 MB |
134 | mlx5_eswitch_get_vport_metadata_for_match(src_esw, |
135 | vport)); | |
c01cfd0f JL |
136 | |
137 | misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2); | |
0f0d3827 PB |
138 | MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, |
139 | mlx5_eswitch_get_vport_metadata_mask()); | |
c01cfd0f JL |
140 | |
141 | spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; | |
c01cfd0f JL |
142 | } else { |
143 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); | |
b055ecf5 | 144 | MLX5_SET(fte_match_set_misc, misc, source_port, vport); |
c01cfd0f JL |
145 | |
146 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) | |
147 | MLX5_SET(fte_match_set_misc, misc, | |
148 | source_eswitch_owner_vhca_id, | |
b055ecf5 | 149 | MLX5_CAP_GEN(src_esw->dev, vhca_id)); |
c01cfd0f JL |
150 | |
151 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters); | |
152 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
153 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) | |
154 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, | |
155 | source_eswitch_owner_vhca_id); | |
156 | ||
157 | spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS; | |
158 | } | |
c01cfd0f JL |
159 | } |
160 | ||
a508728a VB |
161 | static int |
162 | esw_setup_decap_indir(struct mlx5_eswitch *esw, | |
163 | struct mlx5_flow_attr *attr, | |
164 | struct mlx5_flow_spec *spec) | |
165 | { | |
166 | struct mlx5_flow_table *ft; | |
167 | ||
168 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE)) | |
169 | return -EOPNOTSUPP; | |
170 | ||
171 | ft = mlx5_esw_indir_table_get(esw, attr, spec, | |
172 | mlx5_esw_indir_table_decap_vport(attr), true); | |
173 | return PTR_ERR_OR_ZERO(ft); | |
174 | } | |
175 | ||
9e51c0a6 | 176 | static void |
a508728a VB |
177 | esw_cleanup_decap_indir(struct mlx5_eswitch *esw, |
178 | struct mlx5_flow_attr *attr) | |
179 | { | |
180 | if (mlx5_esw_indir_table_decap_vport(attr)) | |
181 | mlx5_esw_indir_table_put(esw, attr, | |
182 | mlx5_esw_indir_table_decap_vport(attr), | |
183 | true); | |
184 | } | |
185 | ||
f94d6389 CM |
186 | static int |
187 | esw_setup_sampler_dest(struct mlx5_flow_destination *dest, | |
188 | struct mlx5_flow_act *flow_act, | |
189 | struct mlx5_esw_flow_attr *esw_attr, | |
190 | int i) | |
191 | { | |
192 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
193 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER; | |
194 | dest[i].sampler_id = esw_attr->sample->sampler_id; | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
a508728a | 199 | static int |
9e51c0a6 VB |
200 | esw_setup_ft_dest(struct mlx5_flow_destination *dest, |
201 | struct mlx5_flow_act *flow_act, | |
a508728a | 202 | struct mlx5_eswitch *esw, |
9e51c0a6 | 203 | struct mlx5_flow_attr *attr, |
a508728a | 204 | struct mlx5_flow_spec *spec, |
9e51c0a6 VB |
205 | int i) |
206 | { | |
207 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
208 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
209 | dest[i].ft = attr->dest_ft; | |
a508728a VB |
210 | |
211 | if (mlx5_esw_indir_table_decap_vport(attr)) | |
212 | return esw_setup_decap_indir(esw, attr, spec); | |
213 | return 0; | |
9e51c0a6 VB |
214 | } |
215 | ||
216 | static void | |
217 | esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, | |
218 | struct mlx5_flow_act *flow_act, | |
219 | struct mlx5_fs_chains *chains, | |
220 | int i) | |
221 | { | |
2a2c84fa RD |
222 | if (mlx5_chains_ignore_flow_level_supported(chains)) |
223 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
9e51c0a6 VB |
224 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; |
225 | dest[i].ft = mlx5_chains_get_tc_end_ft(chains); | |
226 | } | |
227 | ||
228 | static int | |
229 | esw_setup_chain_dest(struct mlx5_flow_destination *dest, | |
230 | struct mlx5_flow_act *flow_act, | |
231 | struct mlx5_fs_chains *chains, | |
232 | u32 chain, u32 prio, u32 level, | |
233 | int i) | |
234 | { | |
235 | struct mlx5_flow_table *ft; | |
236 | ||
237 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
238 | ft = mlx5_chains_get_table(chains, chain, prio, level); | |
239 | if (IS_ERR(ft)) | |
240 | return PTR_ERR(ft); | |
241 | ||
242 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
243 | dest[i].ft = ft; | |
244 | return 0; | |
245 | } | |
246 | ||
10742efc VB |
247 | static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr, |
248 | int from, int to) | |
249 | { | |
250 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
251 | struct mlx5_fs_chains *chains = esw_chains(esw); | |
252 | int i; | |
253 | ||
254 | for (i = from; i < to; i++) | |
255 | if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE) | |
256 | mlx5_chains_put_table(chains, 0, 1, 0); | |
a508728a VB |
257 | else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport, |
258 | esw_attr->dests[i].mdev)) | |
259 | mlx5_esw_indir_table_put(esw, attr, esw_attr->dests[i].rep->vport, | |
260 | false); | |
10742efc VB |
261 | } |
262 | ||
263 | static bool | |
264 | esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr) | |
265 | { | |
266 | int i; | |
267 | ||
268 | for (i = esw_attr->split_count; i < esw_attr->out_count; i++) | |
269 | if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE) | |
270 | return true; | |
271 | return false; | |
272 | } | |
273 | ||
274 | static int | |
275 | esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest, | |
276 | struct mlx5_flow_act *flow_act, | |
277 | struct mlx5_eswitch *esw, | |
278 | struct mlx5_fs_chains *chains, | |
279 | struct mlx5_flow_attr *attr, | |
280 | int *i) | |
281 | { | |
282 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
283 | int j, err; | |
284 | ||
285 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE)) | |
286 | return -EOPNOTSUPP; | |
287 | ||
288 | for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) { | |
289 | err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i); | |
290 | if (err) | |
291 | goto err_setup_chain; | |
292 | flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; | |
293 | flow_act->pkt_reformat = esw_attr->dests[j].pkt_reformat; | |
294 | } | |
295 | return 0; | |
296 | ||
297 | err_setup_chain: | |
298 | esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j); | |
299 | return err; | |
300 | } | |
301 | ||
302 | static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw, | |
303 | struct mlx5_flow_attr *attr) | |
304 | { | |
305 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
306 | ||
307 | esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count); | |
308 | } | |
309 | ||
a508728a VB |
310 | static bool |
311 | esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr) | |
312 | { | |
313 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
314 | int i; | |
315 | ||
316 | for (i = esw_attr->split_count; i < esw_attr->out_count; i++) | |
317 | if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport, | |
318 | esw_attr->dests[i].mdev)) | |
319 | return true; | |
320 | return false; | |
321 | } | |
322 | ||
323 | static int | |
324 | esw_setup_indir_table(struct mlx5_flow_destination *dest, | |
325 | struct mlx5_flow_act *flow_act, | |
326 | struct mlx5_eswitch *esw, | |
327 | struct mlx5_flow_attr *attr, | |
328 | struct mlx5_flow_spec *spec, | |
329 | bool ignore_flow_lvl, | |
330 | int *i) | |
331 | { | |
332 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
333 | int j, err; | |
334 | ||
335 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SRC_REWRITE)) | |
336 | return -EOPNOTSUPP; | |
337 | ||
338 | for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) { | |
339 | if (ignore_flow_lvl) | |
340 | flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; | |
341 | dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
342 | ||
343 | dest[*i].ft = mlx5_esw_indir_table_get(esw, attr, spec, | |
344 | esw_attr->dests[j].rep->vport, false); | |
345 | if (IS_ERR(dest[*i].ft)) { | |
346 | err = PTR_ERR(dest[*i].ft); | |
347 | goto err_indir_tbl_get; | |
348 | } | |
349 | } | |
350 | ||
351 | if (mlx5_esw_indir_table_decap_vport(attr)) { | |
352 | err = esw_setup_decap_indir(esw, attr, spec); | |
353 | if (err) | |
354 | goto err_indir_tbl_get; | |
355 | } | |
356 | ||
357 | return 0; | |
358 | ||
359 | err_indir_tbl_get: | |
360 | esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j); | |
361 | return err; | |
362 | } | |
363 | ||
364 | static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr) | |
365 | { | |
366 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
367 | ||
368 | esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count); | |
369 | esw_cleanup_decap_indir(esw, attr); | |
370 | } | |
371 | ||
9e51c0a6 VB |
372 | static void |
373 | esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level) | |
374 | { | |
375 | mlx5_chains_put_table(chains, chain, prio, level); | |
376 | } | |
377 | ||
378 | static void | |
379 | esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act, | |
380 | struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr, | |
381 | int attr_idx, int dest_idx, bool pkt_reformat) | |
382 | { | |
383 | dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
384 | dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport; | |
385 | dest[dest_idx].vport.vhca_id = | |
386 | MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id); | |
387 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) | |
388 | dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID; | |
389 | if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP) { | |
390 | if (pkt_reformat) { | |
391 | flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; | |
392 | flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat; | |
393 | } | |
394 | dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID; | |
395 | dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat; | |
396 | } | |
397 | } | |
398 | ||
399 | static int | |
400 | esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act, | |
401 | struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr, | |
402 | int i) | |
403 | { | |
404 | int j; | |
405 | ||
406 | for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++) | |
407 | esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true); | |
408 | return i; | |
409 | } | |
410 | ||
e929e3da MD |
411 | static bool |
412 | esw_src_port_rewrite_supported(struct mlx5_eswitch *esw) | |
413 | { | |
414 | return MLX5_CAP_GEN(esw->dev, reg_c_preserve) && | |
415 | mlx5_eswitch_vport_match_metadata_enabled(esw) && | |
416 | MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level); | |
417 | } | |
418 | ||
9e51c0a6 VB |
419 | static int |
420 | esw_setup_dests(struct mlx5_flow_destination *dest, | |
421 | struct mlx5_flow_act *flow_act, | |
422 | struct mlx5_eswitch *esw, | |
423 | struct mlx5_flow_attr *attr, | |
10742efc | 424 | struct mlx5_flow_spec *spec, |
9e51c0a6 VB |
425 | int *i) |
426 | { | |
427 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; | |
428 | struct mlx5_fs_chains *chains = esw_chains(esw); | |
429 | int err = 0; | |
430 | ||
10742efc | 431 | if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) && |
e929e3da | 432 | esw_src_port_rewrite_supported(esw)) |
10742efc VB |
433 | attr->flags |= MLX5_ESW_ATTR_FLAG_SRC_REWRITE; |
434 | ||
f94d6389 CM |
435 | if (attr->flags & MLX5_ESW_ATTR_FLAG_SAMPLE) { |
436 | esw_setup_sampler_dest(dest, flow_act, esw_attr, *i); | |
437 | (*i)++; | |
438 | } else if (attr->dest_ft) { | |
a508728a | 439 | esw_setup_ft_dest(dest, flow_act, esw, attr, spec, *i); |
9e51c0a6 VB |
440 | (*i)++; |
441 | } else if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH) { | |
442 | esw_setup_slow_path_dest(dest, flow_act, chains, *i); | |
443 | (*i)++; | |
444 | } else if (attr->dest_chain) { | |
445 | err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, | |
446 | 1, 0, *i); | |
447 | (*i)++; | |
a508728a VB |
448 | } else if (esw_is_indir_table(esw, attr)) { |
449 | err = esw_setup_indir_table(dest, flow_act, esw, attr, spec, true, i); | |
10742efc VB |
450 | } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) { |
451 | err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i); | |
9e51c0a6 VB |
452 | } else { |
453 | *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i); | |
454 | } | |
455 | ||
456 | return err; | |
457 | } | |
458 | ||
459 | static void | |
460 | esw_cleanup_dests(struct mlx5_eswitch *esw, | |
461 | struct mlx5_flow_attr *attr) | |
462 | { | |
10742efc | 463 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
9e51c0a6 VB |
464 | struct mlx5_fs_chains *chains = esw_chains(esw); |
465 | ||
a508728a VB |
466 | if (attr->dest_ft) { |
467 | esw_cleanup_decap_indir(esw, attr); | |
468 | } else if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) { | |
10742efc VB |
469 | if (attr->dest_chain) |
470 | esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0); | |
a508728a VB |
471 | else if (esw_is_indir_table(esw, attr)) |
472 | esw_cleanup_indir_table(esw, attr); | |
10742efc VB |
473 | else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) |
474 | esw_cleanup_chain_src_port_rewrite(esw, attr); | |
475 | } | |
9e51c0a6 VB |
476 | } |
477 | ||
74491de9 | 478 | struct mlx5_flow_handle * |
3d80d1a2 OG |
479 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
480 | struct mlx5_flow_spec *spec, | |
c620b772 | 481 | struct mlx5_flow_attr *attr) |
3d80d1a2 | 482 | { |
592d3651 | 483 | struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {}; |
42f7ad67 | 484 | struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, }; |
c620b772 | 485 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
ae430332 | 486 | struct mlx5_fs_chains *chains = esw_chains(esw); |
c620b772 AL |
487 | bool split = !!(esw_attr->split_count); |
488 | struct mlx5_vport_tbl_attr fwd_attr; | |
74491de9 | 489 | struct mlx5_flow_handle *rule; |
e52c2802 | 490 | struct mlx5_flow_table *fdb; |
9e51c0a6 | 491 | int i = 0; |
3d80d1a2 | 492 | |
f6455de0 | 493 | if (esw->mode != MLX5_ESWITCH_OFFLOADS) |
3d80d1a2 OG |
494 | return ERR_PTR(-EOPNOTSUPP); |
495 | ||
6acfbf38 OG |
496 | flow_act.action = attr->action; |
497 | /* if per flow vlan pop/push is emulated, don't set that into the firmware */ | |
cc495188 | 498 | if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1)) |
6acfbf38 OG |
499 | flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH | |
500 | MLX5_FLOW_CONTEXT_ACTION_VLAN_POP); | |
501 | else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) { | |
c620b772 AL |
502 | flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]); |
503 | flow_act.vlan[0].vid = esw_attr->vlan_vid[0]; | |
504 | flow_act.vlan[0].prio = esw_attr->vlan_prio[0]; | |
cc495188 | 505 | if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) { |
c620b772 AL |
506 | flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]); |
507 | flow_act.vlan[1].vid = esw_attr->vlan_vid[1]; | |
508 | flow_act.vlan[1].prio = esw_attr->vlan_prio[1]; | |
cc495188 | 509 | } |
6acfbf38 | 510 | } |
776b12b6 | 511 | |
10742efc VB |
512 | mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr); |
513 | ||
66958ed9 | 514 | if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { |
9e51c0a6 VB |
515 | int err; |
516 | ||
10742efc | 517 | err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i); |
9e51c0a6 VB |
518 | if (err) { |
519 | rule = ERR_PTR(err); | |
520 | goto err_create_goto_table; | |
56e858df | 521 | } |
e37a79e5 | 522 | } |
14e6b038 | 523 | |
c620b772 AL |
524 | if (esw_attr->decap_pkt_reformat) |
525 | flow_act.pkt_reformat = esw_attr->decap_pkt_reformat; | |
14e6b038 | 526 | |
66958ed9 | 527 | if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { |
e37a79e5 | 528 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; |
171c7625 | 529 | dest[i].counter_id = mlx5_fc_id(attr->counter); |
e37a79e5 | 530 | i++; |
3d80d1a2 OG |
531 | } |
532 | ||
93b3586e | 533 | if (attr->outer_match_level != MLX5_MATCH_NONE) |
6363651d | 534 | spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS; |
93b3586e HN |
535 | if (attr->inner_match_level != MLX5_MATCH_NONE) |
536 | spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS; | |
3d80d1a2 | 537 | |
aa24670e | 538 | if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
2b688ea5 | 539 | flow_act.modify_hdr = attr->modify_hdr; |
d7e75a32 | 540 | |
f94d6389 CM |
541 | /* esw_attr->sample is allocated only when there is a sample action */ |
542 | if (esw_attr->sample && esw_attr->sample->sample_default_tbl) { | |
543 | fdb = esw_attr->sample->sample_default_tbl; | |
544 | } else if (split) { | |
c620b772 AL |
545 | fwd_attr.chain = attr->chain; |
546 | fwd_attr.prio = attr->prio; | |
547 | fwd_attr.vport = esw_attr->in_rep->vport; | |
c796bb7c | 548 | fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
c620b772 | 549 | |
0a9e2307 | 550 | fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr); |
96e32687 | 551 | } else { |
d18296ff | 552 | if (attr->chain || attr->prio) |
ae430332 AL |
553 | fdb = mlx5_chains_get_table(chains, attr->chain, |
554 | attr->prio, 0); | |
d18296ff | 555 | else |
c620b772 | 556 | fdb = attr->ft; |
6fb0701a PB |
557 | |
558 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_NO_IN_PORT)) | |
a508728a | 559 | mlx5_eswitch_set_rule_source_port(esw, spec, attr, |
b055ecf5 MB |
560 | esw_attr->in_mdev->priv.eswitch, |
561 | esw_attr->in_rep->vport); | |
96e32687 | 562 | } |
e52c2802 PB |
563 | if (IS_ERR(fdb)) { |
564 | rule = ERR_CAST(fdb); | |
565 | goto err_esw_get; | |
566 | } | |
567 | ||
84be2fda | 568 | if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec)) |
c620b772 | 569 | rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr, |
10caabda | 570 | &flow_act, dest, i); |
84be2fda | 571 | else |
10caabda | 572 | rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i); |
3d80d1a2 | 573 | if (IS_ERR(rule)) |
e52c2802 | 574 | goto err_add_rule; |
375f51e2 | 575 | else |
525e84be | 576 | atomic64_inc(&esw->offloads.num_flows); |
3d80d1a2 | 577 | |
e52c2802 PB |
578 | return rule; |
579 | ||
580 | err_add_rule: | |
96e32687 | 581 | if (split) |
0a9e2307 | 582 | mlx5_esw_vporttbl_put(esw, &fwd_attr); |
d18296ff | 583 | else if (attr->chain || attr->prio) |
ae430332 | 584 | mlx5_chains_put_table(chains, attr->chain, attr->prio, 0); |
e52c2802 | 585 | err_esw_get: |
9e51c0a6 | 586 | esw_cleanup_dests(esw, attr); |
e52c2802 | 587 | err_create_goto_table: |
aa0cbbae | 588 | return rule; |
3d80d1a2 OG |
589 | } |
590 | ||
e4ad91f2 CM |
591 | struct mlx5_flow_handle * |
592 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
593 | struct mlx5_flow_spec *spec, | |
c620b772 | 594 | struct mlx5_flow_attr *attr) |
e4ad91f2 CM |
595 | { |
596 | struct mlx5_flow_destination dest[MLX5_MAX_FLOW_FWD_VPORTS + 1] = {}; | |
42f7ad67 | 597 | struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, }; |
c620b772 | 598 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
ae430332 | 599 | struct mlx5_fs_chains *chains = esw_chains(esw); |
c620b772 | 600 | struct mlx5_vport_tbl_attr fwd_attr; |
e52c2802 PB |
601 | struct mlx5_flow_table *fast_fdb; |
602 | struct mlx5_flow_table *fwd_fdb; | |
e4ad91f2 | 603 | struct mlx5_flow_handle *rule; |
10742efc | 604 | int i, err = 0; |
e4ad91f2 | 605 | |
ae430332 | 606 | fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0); |
e52c2802 PB |
607 | if (IS_ERR(fast_fdb)) { |
608 | rule = ERR_CAST(fast_fdb); | |
609 | goto err_get_fast; | |
610 | } | |
611 | ||
c620b772 AL |
612 | fwd_attr.chain = attr->chain; |
613 | fwd_attr.prio = attr->prio; | |
614 | fwd_attr.vport = esw_attr->in_rep->vport; | |
c796bb7c | 615 | fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
0a9e2307 | 616 | fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr); |
e52c2802 PB |
617 | if (IS_ERR(fwd_fdb)) { |
618 | rule = ERR_CAST(fwd_fdb); | |
619 | goto err_get_fwd; | |
620 | } | |
621 | ||
e4ad91f2 | 622 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
10742efc | 623 | for (i = 0; i < esw_attr->split_count; i++) { |
a508728a VB |
624 | if (esw_is_indir_table(esw, attr)) |
625 | err = esw_setup_indir_table(dest, &flow_act, esw, attr, spec, false, &i); | |
626 | else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) | |
10742efc VB |
627 | err = esw_setup_chain_src_port_rewrite(dest, &flow_act, esw, chains, attr, |
628 | &i); | |
629 | else | |
630 | esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false); | |
631 | ||
632 | if (err) { | |
633 | rule = ERR_PTR(err); | |
634 | goto err_chain_src_rewrite; | |
635 | } | |
636 | } | |
e4ad91f2 | 637 | dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; |
873d2f12 | 638 | dest[i].ft = fwd_fdb; |
e4ad91f2 CM |
639 | i++; |
640 | ||
a508728a | 641 | mlx5_eswitch_set_rule_source_port(esw, spec, attr, |
b055ecf5 MB |
642 | esw_attr->in_mdev->priv.eswitch, |
643 | esw_attr->in_rep->vport); | |
e4ad91f2 | 644 | |
93b3586e | 645 | if (attr->outer_match_level != MLX5_MATCH_NONE) |
c01cfd0f | 646 | spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS; |
e4ad91f2 | 647 | |
278d51f2 | 648 | flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL; |
e52c2802 | 649 | rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i); |
e4ad91f2 | 650 | |
10742efc VB |
651 | if (IS_ERR(rule)) { |
652 | i = esw_attr->split_count; | |
653 | goto err_chain_src_rewrite; | |
654 | } | |
e4ad91f2 | 655 | |
525e84be | 656 | atomic64_inc(&esw->offloads.num_flows); |
e52c2802 PB |
657 | |
658 | return rule; | |
10742efc VB |
659 | err_chain_src_rewrite: |
660 | esw_put_dest_tables_loop(esw, attr, 0, i); | |
0a9e2307 | 661 | mlx5_esw_vporttbl_put(esw, &fwd_attr); |
e52c2802 | 662 | err_get_fwd: |
ae430332 | 663 | mlx5_chains_put_table(chains, attr->chain, attr->prio, 0); |
e52c2802 | 664 | err_get_fast: |
e4ad91f2 CM |
665 | return rule; |
666 | } | |
667 | ||
e52c2802 PB |
668 | static void |
669 | __mlx5_eswitch_del_rule(struct mlx5_eswitch *esw, | |
670 | struct mlx5_flow_handle *rule, | |
c620b772 | 671 | struct mlx5_flow_attr *attr, |
e52c2802 PB |
672 | bool fwd_rule) |
673 | { | |
c620b772 | 674 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
ae430332 | 675 | struct mlx5_fs_chains *chains = esw_chains(esw); |
c620b772 AL |
676 | bool split = (esw_attr->split_count > 0); |
677 | struct mlx5_vport_tbl_attr fwd_attr; | |
10caabda | 678 | int i; |
e52c2802 PB |
679 | |
680 | mlx5_del_flow_rules(rule); | |
10caabda | 681 | |
84be2fda | 682 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)) { |
d8a2034f EC |
683 | /* unref the term table */ |
684 | for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) { | |
c620b772 AL |
685 | if (esw_attr->dests[i].termtbl) |
686 | mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl); | |
d8a2034f | 687 | } |
10caabda OS |
688 | } |
689 | ||
525e84be | 690 | atomic64_dec(&esw->offloads.num_flows); |
e52c2802 | 691 | |
c620b772 AL |
692 | if (fwd_rule || split) { |
693 | fwd_attr.chain = attr->chain; | |
694 | fwd_attr.prio = attr->prio; | |
695 | fwd_attr.vport = esw_attr->in_rep->vport; | |
c796bb7c | 696 | fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
c620b772 AL |
697 | } |
698 | ||
e52c2802 | 699 | if (fwd_rule) { |
0a9e2307 | 700 | mlx5_esw_vporttbl_put(esw, &fwd_attr); |
ae430332 | 701 | mlx5_chains_put_table(chains, attr->chain, attr->prio, 0); |
10742efc | 702 | esw_put_dest_tables_loop(esw, attr, 0, esw_attr->split_count); |
e52c2802 | 703 | } else { |
96e32687 | 704 | if (split) |
0a9e2307 | 705 | mlx5_esw_vporttbl_put(esw, &fwd_attr); |
d18296ff | 706 | else if (attr->chain || attr->prio) |
ae430332 | 707 | mlx5_chains_put_table(chains, attr->chain, attr->prio, 0); |
9e51c0a6 | 708 | esw_cleanup_dests(esw, attr); |
e52c2802 PB |
709 | } |
710 | } | |
711 | ||
d85cdccb OG |
712 | void |
713 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
714 | struct mlx5_flow_handle *rule, | |
c620b772 | 715 | struct mlx5_flow_attr *attr) |
d85cdccb | 716 | { |
e52c2802 | 717 | __mlx5_eswitch_del_rule(esw, rule, attr, false); |
d85cdccb OG |
718 | } |
719 | ||
48265006 OG |
720 | void |
721 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
722 | struct mlx5_flow_handle *rule, | |
c620b772 | 723 | struct mlx5_flow_attr *attr) |
48265006 | 724 | { |
e52c2802 | 725 | __mlx5_eswitch_del_rule(esw, rule, attr, true); |
48265006 OG |
726 | } |
727 | ||
f5f82476 OG |
728 | static int esw_set_global_vlan_pop(struct mlx5_eswitch *esw, u8 val) |
729 | { | |
730 | struct mlx5_eswitch_rep *rep; | |
47dd7e60 PP |
731 | unsigned long i; |
732 | int err = 0; | |
f5f82476 OG |
733 | |
734 | esw_debug(esw->dev, "%s applying global %s policy\n", __func__, val ? "pop" : "none"); | |
47dd7e60 | 735 | mlx5_esw_for_each_host_func_vport(esw, i, rep, esw->esw_funcs.num_vfs) { |
8693115a | 736 | if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED) |
f5f82476 OG |
737 | continue; |
738 | ||
739 | err = __mlx5_eswitch_set_vport_vlan(esw, rep->vport, 0, 0, val); | |
740 | if (err) | |
741 | goto out; | |
742 | } | |
743 | ||
744 | out: | |
745 | return err; | |
746 | } | |
747 | ||
748 | static struct mlx5_eswitch_rep * | |
749 | esw_vlan_action_get_vport(struct mlx5_esw_flow_attr *attr, bool push, bool pop) | |
750 | { | |
751 | struct mlx5_eswitch_rep *in_rep, *out_rep, *vport = NULL; | |
752 | ||
753 | in_rep = attr->in_rep; | |
df65a573 | 754 | out_rep = attr->dests[0].rep; |
f5f82476 OG |
755 | |
756 | if (push) | |
757 | vport = in_rep; | |
758 | else if (pop) | |
759 | vport = out_rep; | |
760 | else | |
761 | vport = in_rep; | |
762 | ||
763 | return vport; | |
764 | } | |
765 | ||
766 | static int esw_add_vlan_action_check(struct mlx5_esw_flow_attr *attr, | |
767 | bool push, bool pop, bool fwd) | |
768 | { | |
769 | struct mlx5_eswitch_rep *in_rep, *out_rep; | |
770 | ||
771 | if ((push || pop) && !fwd) | |
772 | goto out_notsupp; | |
773 | ||
774 | in_rep = attr->in_rep; | |
df65a573 | 775 | out_rep = attr->dests[0].rep; |
f5f82476 | 776 | |
b05af6aa | 777 | if (push && in_rep->vport == MLX5_VPORT_UPLINK) |
f5f82476 OG |
778 | goto out_notsupp; |
779 | ||
b05af6aa | 780 | if (pop && out_rep->vport == MLX5_VPORT_UPLINK) |
f5f82476 OG |
781 | goto out_notsupp; |
782 | ||
783 | /* vport has vlan push configured, can't offload VF --> wire rules w.o it */ | |
784 | if (!push && !pop && fwd) | |
b05af6aa | 785 | if (in_rep->vlan && out_rep->vport == MLX5_VPORT_UPLINK) |
f5f82476 OG |
786 | goto out_notsupp; |
787 | ||
788 | /* protects against (1) setting rules with different vlans to push and | |
789 | * (2) setting rules w.o vlans (attr->vlan = 0) && w. vlans to push (!= 0) | |
790 | */ | |
1482bd3d | 791 | if (push && in_rep->vlan_refcount && (in_rep->vlan != attr->vlan_vid[0])) |
f5f82476 OG |
792 | goto out_notsupp; |
793 | ||
794 | return 0; | |
795 | ||
796 | out_notsupp: | |
9eb78923 | 797 | return -EOPNOTSUPP; |
f5f82476 OG |
798 | } |
799 | ||
800 | int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw, | |
c620b772 | 801 | struct mlx5_flow_attr *attr) |
f5f82476 OG |
802 | { |
803 | struct offloads_fdb *offloads = &esw->fdb_table.offloads; | |
c620b772 | 804 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
f5f82476 OG |
805 | struct mlx5_eswitch_rep *vport = NULL; |
806 | bool push, pop, fwd; | |
807 | int err = 0; | |
808 | ||
6acfbf38 | 809 | /* nop if we're on the vlan push/pop non emulation mode */ |
cc495188 | 810 | if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1)) |
6acfbf38 OG |
811 | return 0; |
812 | ||
f5f82476 OG |
813 | push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH); |
814 | pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP); | |
e52c2802 PB |
815 | fwd = !!((attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) && |
816 | !attr->dest_chain); | |
f5f82476 | 817 | |
0e18134f VB |
818 | mutex_lock(&esw->state_lock); |
819 | ||
c620b772 | 820 | err = esw_add_vlan_action_check(esw_attr, push, pop, fwd); |
f5f82476 | 821 | if (err) |
0e18134f | 822 | goto unlock; |
f5f82476 | 823 | |
39ac237c | 824 | attr->flags &= ~MLX5_ESW_ATTR_FLAG_VLAN_HANDLED; |
f5f82476 | 825 | |
c620b772 | 826 | vport = esw_vlan_action_get_vport(esw_attr, push, pop); |
f5f82476 OG |
827 | |
828 | if (!push && !pop && fwd) { | |
829 | /* tracks VF --> wire rules without vlan push action */ | |
c620b772 | 830 | if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) { |
f5f82476 | 831 | vport->vlan_refcount++; |
39ac237c | 832 | attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED; |
f5f82476 OG |
833 | } |
834 | ||
0e18134f | 835 | goto unlock; |
f5f82476 OG |
836 | } |
837 | ||
838 | if (!push && !pop) | |
0e18134f | 839 | goto unlock; |
f5f82476 OG |
840 | |
841 | if (!(offloads->vlan_push_pop_refcount)) { | |
842 | /* it's the 1st vlan rule, apply global vlan pop policy */ | |
843 | err = esw_set_global_vlan_pop(esw, SET_VLAN_STRIP); | |
844 | if (err) | |
845 | goto out; | |
846 | } | |
847 | offloads->vlan_push_pop_refcount++; | |
848 | ||
849 | if (push) { | |
850 | if (vport->vlan_refcount) | |
851 | goto skip_set_push; | |
852 | ||
c620b772 AL |
853 | err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, esw_attr->vlan_vid[0], |
854 | 0, SET_VLAN_INSERT | SET_VLAN_STRIP); | |
f5f82476 OG |
855 | if (err) |
856 | goto out; | |
c620b772 | 857 | vport->vlan = esw_attr->vlan_vid[0]; |
f5f82476 OG |
858 | skip_set_push: |
859 | vport->vlan_refcount++; | |
860 | } | |
861 | out: | |
862 | if (!err) | |
39ac237c | 863 | attr->flags |= MLX5_ESW_ATTR_FLAG_VLAN_HANDLED; |
0e18134f VB |
864 | unlock: |
865 | mutex_unlock(&esw->state_lock); | |
f5f82476 OG |
866 | return err; |
867 | } | |
868 | ||
869 | int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw, | |
c620b772 | 870 | struct mlx5_flow_attr *attr) |
f5f82476 OG |
871 | { |
872 | struct offloads_fdb *offloads = &esw->fdb_table.offloads; | |
c620b772 | 873 | struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr; |
f5f82476 OG |
874 | struct mlx5_eswitch_rep *vport = NULL; |
875 | bool push, pop, fwd; | |
876 | int err = 0; | |
877 | ||
6acfbf38 | 878 | /* nop if we're on the vlan push/pop non emulation mode */ |
cc495188 | 879 | if (mlx5_eswitch_vlan_actions_supported(esw->dev, 1)) |
6acfbf38 OG |
880 | return 0; |
881 | ||
39ac237c | 882 | if (!(attr->flags & MLX5_ESW_ATTR_FLAG_VLAN_HANDLED)) |
f5f82476 OG |
883 | return 0; |
884 | ||
885 | push = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH); | |
886 | pop = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP); | |
887 | fwd = !!(attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST); | |
888 | ||
0e18134f VB |
889 | mutex_lock(&esw->state_lock); |
890 | ||
c620b772 | 891 | vport = esw_vlan_action_get_vport(esw_attr, push, pop); |
f5f82476 OG |
892 | |
893 | if (!push && !pop && fwd) { | |
894 | /* tracks VF --> wire rules without vlan push action */ | |
c620b772 | 895 | if (esw_attr->dests[0].rep->vport == MLX5_VPORT_UPLINK) |
f5f82476 OG |
896 | vport->vlan_refcount--; |
897 | ||
0e18134f | 898 | goto out; |
f5f82476 OG |
899 | } |
900 | ||
901 | if (push) { | |
902 | vport->vlan_refcount--; | |
903 | if (vport->vlan_refcount) | |
904 | goto skip_unset_push; | |
905 | ||
906 | vport->vlan = 0; | |
907 | err = __mlx5_eswitch_set_vport_vlan(esw, vport->vport, | |
908 | 0, 0, SET_VLAN_STRIP); | |
909 | if (err) | |
910 | goto out; | |
911 | } | |
912 | ||
913 | skip_unset_push: | |
914 | offloads->vlan_push_pop_refcount--; | |
915 | if (offloads->vlan_push_pop_refcount) | |
0e18134f | 916 | goto out; |
f5f82476 OG |
917 | |
918 | /* no more vlan rules, stop global vlan pop policy */ | |
919 | err = esw_set_global_vlan_pop(esw, 0); | |
920 | ||
921 | out: | |
0e18134f | 922 | mutex_unlock(&esw->state_lock); |
f5f82476 OG |
923 | return err; |
924 | } | |
925 | ||
f7a68945 | 926 | struct mlx5_flow_handle * |
3a46f4fb | 927 | mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw, |
979bf468 | 928 | struct mlx5_eswitch *from_esw, |
3a46f4fb | 929 | struct mlx5_eswitch_rep *rep, |
02f3afd9 | 930 | u32 sqn) |
ab22be9b | 931 | { |
66958ed9 | 932 | struct mlx5_flow_act flow_act = {0}; |
4c5009c5 | 933 | struct mlx5_flow_destination dest = {}; |
74491de9 | 934 | struct mlx5_flow_handle *flow_rule; |
c5bb1730 | 935 | struct mlx5_flow_spec *spec; |
ab22be9b OG |
936 | void *misc; |
937 | ||
1b9a07ee | 938 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
c5bb1730 | 939 | if (!spec) { |
ab22be9b OG |
940 | flow_rule = ERR_PTR(-ENOMEM); |
941 | goto out; | |
942 | } | |
943 | ||
c5bb1730 | 944 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); |
ab22be9b | 945 | MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn); |
a1b3839a | 946 | /* source vport is the esw manager */ |
979bf468 | 947 | MLX5_SET(fte_match_set_misc, misc, source_port, from_esw->manager_vport); |
3a46f4fb | 948 | if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch)) |
7d97822a | 949 | MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, |
979bf468 | 950 | MLX5_CAP_GEN(from_esw->dev, vhca_id)); |
ab22be9b | 951 | |
c5bb1730 | 952 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters); |
ab22be9b OG |
953 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn); |
954 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
3a46f4fb | 955 | if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch)) |
7d97822a MB |
956 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, |
957 | source_eswitch_owner_vhca_id); | |
ab22be9b | 958 | |
c5bb1730 | 959 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS; |
ab22be9b | 960 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; |
3a46f4fb MB |
961 | dest.vport.num = rep->vport; |
962 | dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id); | |
963 | dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID; | |
66958ed9 | 964 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
ab22be9b | 965 | |
3a46f4fb | 966 | flow_rule = mlx5_add_flow_rules(on_esw->fdb_table.offloads.slow_fdb, |
39ac237c | 967 | spec, &flow_act, &dest, 1); |
ab22be9b | 968 | if (IS_ERR(flow_rule)) |
3a46f4fb MB |
969 | esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n", |
970 | PTR_ERR(flow_rule)); | |
ab22be9b | 971 | out: |
c5bb1730 | 972 | kvfree(spec); |
ab22be9b OG |
973 | return flow_rule; |
974 | } | |
57cbd893 | 975 | EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule); |
ab22be9b | 976 | |
159fe639 MB |
977 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule) |
978 | { | |
979 | mlx5_del_flow_rules(rule); | |
980 | } | |
981 | ||
8e404fef VB |
982 | static void mlx5_eswitch_del_send_to_vport_meta_rules(struct mlx5_eswitch *esw) |
983 | { | |
984 | struct mlx5_flow_handle **flows = esw->fdb_table.offloads.send_to_vport_meta_rules; | |
47dd7e60 | 985 | int i = 0, num_vfs = esw->esw_funcs.num_vfs; |
8e404fef VB |
986 | |
987 | if (!num_vfs || !flows) | |
988 | return; | |
989 | ||
47dd7e60 PP |
990 | for (i = 0; i < num_vfs; i++) |
991 | mlx5_del_flow_rules(flows[i]); | |
8e404fef VB |
992 | |
993 | kvfree(flows); | |
994 | } | |
995 | ||
996 | static int | |
997 | mlx5_eswitch_add_send_to_vport_meta_rules(struct mlx5_eswitch *esw) | |
998 | { | |
8e404fef VB |
999 | struct mlx5_flow_destination dest = {}; |
1000 | struct mlx5_flow_act flow_act = {0}; | |
6308a5f0 | 1001 | int num_vfs, rule_idx = 0, err = 0; |
8e404fef VB |
1002 | struct mlx5_flow_handle *flow_rule; |
1003 | struct mlx5_flow_handle **flows; | |
1004 | struct mlx5_flow_spec *spec; | |
47dd7e60 PP |
1005 | struct mlx5_vport *vport; |
1006 | unsigned long i; | |
6308a5f0 | 1007 | u16 vport_num; |
8e404fef VB |
1008 | |
1009 | num_vfs = esw->esw_funcs.num_vfs; | |
1010 | flows = kvzalloc(num_vfs * sizeof(*flows), GFP_KERNEL); | |
1011 | if (!flows) | |
1012 | return -ENOMEM; | |
1013 | ||
1014 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); | |
1015 | if (!spec) { | |
1016 | err = -ENOMEM; | |
1017 | goto alloc_err; | |
1018 | } | |
1019 | ||
1020 | MLX5_SET(fte_match_param, spec->match_criteria, | |
1021 | misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask()); | |
1022 | MLX5_SET(fte_match_param, spec->match_criteria, | |
1023 | misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK); | |
1024 | MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1, | |
1025 | ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK); | |
1026 | ||
1027 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; | |
1028 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
1029 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
1030 | ||
47dd7e60 PP |
1031 | mlx5_esw_for_each_vf_vport(esw, i, vport, num_vfs) { |
1032 | vport_num = vport->vport; | |
8e404fef VB |
1033 | MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0, |
1034 | mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num)); | |
1035 | dest.vport.num = vport_num; | |
1036 | ||
1037 | flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, | |
1038 | spec, &flow_act, &dest, 1); | |
1039 | if (IS_ERR(flow_rule)) { | |
1040 | err = PTR_ERR(flow_rule); | |
1041 | esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule idx %d, err %ld\n", | |
1042 | rule_idx, PTR_ERR(flow_rule)); | |
1043 | goto rule_err; | |
1044 | } | |
1045 | flows[rule_idx++] = flow_rule; | |
1046 | } | |
1047 | ||
1048 | esw->fdb_table.offloads.send_to_vport_meta_rules = flows; | |
1049 | kvfree(spec); | |
1050 | return 0; | |
1051 | ||
1052 | rule_err: | |
1053 | while (--rule_idx >= 0) | |
1054 | mlx5_del_flow_rules(flows[rule_idx]); | |
1055 | kvfree(spec); | |
1056 | alloc_err: | |
1057 | kvfree(flows); | |
1058 | return err; | |
1059 | } | |
1060 | ||
5b7cb745 PB |
1061 | static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw) |
1062 | { | |
1063 | return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) & | |
1064 | MLX5_FDB_TO_VPORT_REG_C_1; | |
1065 | } | |
1066 | ||
332bd3a5 | 1067 | static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable) |
c1286050 JL |
1068 | { |
1069 | u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {}; | |
e08a6832 LR |
1070 | u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {}; |
1071 | u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {}; | |
5b7cb745 | 1072 | u8 curr, wanted; |
c1286050 JL |
1073 | int err; |
1074 | ||
5b7cb745 PB |
1075 | if (!mlx5_eswitch_reg_c1_loopback_supported(esw) && |
1076 | !mlx5_eswitch_vport_match_metadata_enabled(esw)) | |
332bd3a5 | 1077 | return 0; |
c1286050 | 1078 | |
e08a6832 LR |
1079 | MLX5_SET(query_esw_vport_context_in, in, opcode, |
1080 | MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT); | |
1081 | err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out); | |
c1286050 JL |
1082 | if (err) |
1083 | return err; | |
1084 | ||
5b7cb745 PB |
1085 | curr = MLX5_GET(query_esw_vport_context_out, out, |
1086 | esw_vport_context.fdb_to_vport_reg_c_id); | |
1087 | wanted = MLX5_FDB_TO_VPORT_REG_C_0; | |
1088 | if (mlx5_eswitch_reg_c1_loopback_supported(esw)) | |
1089 | wanted |= MLX5_FDB_TO_VPORT_REG_C_1; | |
c1286050 | 1090 | |
332bd3a5 | 1091 | if (enable) |
5b7cb745 | 1092 | curr |= wanted; |
332bd3a5 | 1093 | else |
5b7cb745 | 1094 | curr &= ~wanted; |
c1286050 | 1095 | |
e08a6832 | 1096 | MLX5_SET(modify_esw_vport_context_in, min, |
5b7cb745 | 1097 | esw_vport_context.fdb_to_vport_reg_c_id, curr); |
e08a6832 | 1098 | MLX5_SET(modify_esw_vport_context_in, min, |
c1286050 JL |
1099 | field_select.fdb_to_vport_reg_c_id, 1); |
1100 | ||
e08a6832 | 1101 | err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min); |
5b7cb745 PB |
1102 | if (!err) { |
1103 | if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1)) | |
1104 | esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED; | |
1105 | else | |
1106 | esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED; | |
1107 | } | |
1108 | ||
1109 | return err; | |
c1286050 JL |
1110 | } |
1111 | ||
a5641cb5 JL |
1112 | static void peer_miss_rules_setup(struct mlx5_eswitch *esw, |
1113 | struct mlx5_core_dev *peer_dev, | |
ac004b83 RD |
1114 | struct mlx5_flow_spec *spec, |
1115 | struct mlx5_flow_destination *dest) | |
1116 | { | |
a5641cb5 | 1117 | void *misc; |
ac004b83 | 1118 | |
a5641cb5 JL |
1119 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { |
1120 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1121 | misc_parameters_2); | |
0f0d3827 PB |
1122 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, |
1123 | mlx5_eswitch_get_vport_metadata_mask()); | |
ac004b83 | 1124 | |
a5641cb5 JL |
1125 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; |
1126 | } else { | |
1127 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1128 | misc_parameters); | |
ac004b83 | 1129 | |
a5641cb5 JL |
1130 | MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, |
1131 | MLX5_CAP_GEN(peer_dev, vhca_id)); | |
1132 | ||
1133 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS; | |
1134 | ||
1135 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1136 | misc_parameters); | |
1137 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
1138 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, | |
1139 | source_eswitch_owner_vhca_id); | |
1140 | } | |
ac004b83 RD |
1141 | |
1142 | dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT; | |
a1b3839a | 1143 | dest->vport.num = peer_dev->priv.eswitch->manager_vport; |
ac004b83 | 1144 | dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id); |
04de7dda | 1145 | dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID; |
ac004b83 RD |
1146 | } |
1147 | ||
a5641cb5 JL |
1148 | static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw, |
1149 | struct mlx5_eswitch *peer_esw, | |
1150 | struct mlx5_flow_spec *spec, | |
1151 | u16 vport) | |
1152 | { | |
1153 | void *misc; | |
1154 | ||
1155 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { | |
1156 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1157 | misc_parameters_2); | |
1158 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, | |
1159 | mlx5_eswitch_get_vport_metadata_for_match(peer_esw, | |
1160 | vport)); | |
1161 | } else { | |
1162 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1163 | misc_parameters); | |
1164 | MLX5_SET(fte_match_set_misc, misc, source_port, vport); | |
1165 | } | |
1166 | } | |
1167 | ||
ac004b83 RD |
1168 | static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw, |
1169 | struct mlx5_core_dev *peer_dev) | |
1170 | { | |
1171 | struct mlx5_flow_destination dest = {}; | |
1172 | struct mlx5_flow_act flow_act = {0}; | |
1173 | struct mlx5_flow_handle **flows; | |
ac004b83 RD |
1174 | /* total vports is the same for both e-switches */ |
1175 | int nvports = esw->total_vports; | |
47dd7e60 PP |
1176 | struct mlx5_flow_handle *flow; |
1177 | struct mlx5_flow_spec *spec; | |
1178 | struct mlx5_vport *vport; | |
1179 | unsigned long i; | |
ac004b83 | 1180 | void *misc; |
47dd7e60 | 1181 | int err; |
ac004b83 RD |
1182 | |
1183 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); | |
1184 | if (!spec) | |
1185 | return -ENOMEM; | |
1186 | ||
a5641cb5 | 1187 | peer_miss_rules_setup(esw, peer_dev, spec, &dest); |
ac004b83 RD |
1188 | |
1189 | flows = kvzalloc(nvports * sizeof(*flows), GFP_KERNEL); | |
1190 | if (!flows) { | |
1191 | err = -ENOMEM; | |
1192 | goto alloc_flows_err; | |
1193 | } | |
1194 | ||
1195 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
1196 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1197 | misc_parameters); | |
1198 | ||
81cd229c | 1199 | if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { |
47dd7e60 | 1200 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); |
a5641cb5 JL |
1201 | esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch, |
1202 | spec, MLX5_VPORT_PF); | |
1203 | ||
81cd229c BW |
1204 | flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, |
1205 | spec, &flow_act, &dest, 1); | |
1206 | if (IS_ERR(flow)) { | |
1207 | err = PTR_ERR(flow); | |
1208 | goto add_pf_flow_err; | |
1209 | } | |
47dd7e60 | 1210 | flows[vport->index] = flow; |
81cd229c BW |
1211 | } |
1212 | ||
1213 | if (mlx5_ecpf_vport_exists(esw->dev)) { | |
47dd7e60 | 1214 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); |
81cd229c BW |
1215 | MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF); |
1216 | flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, | |
1217 | spec, &flow_act, &dest, 1); | |
1218 | if (IS_ERR(flow)) { | |
1219 | err = PTR_ERR(flow); | |
1220 | goto add_ecpf_flow_err; | |
1221 | } | |
47dd7e60 | 1222 | flows[vport->index] = flow; |
81cd229c BW |
1223 | } |
1224 | ||
47dd7e60 | 1225 | mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) { |
a5641cb5 JL |
1226 | esw_set_peer_miss_rule_source_port(esw, |
1227 | peer_dev->priv.eswitch, | |
47dd7e60 | 1228 | spec, vport->vport); |
a5641cb5 | 1229 | |
ac004b83 RD |
1230 | flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, |
1231 | spec, &flow_act, &dest, 1); | |
1232 | if (IS_ERR(flow)) { | |
1233 | err = PTR_ERR(flow); | |
81cd229c | 1234 | goto add_vf_flow_err; |
ac004b83 | 1235 | } |
47dd7e60 | 1236 | flows[vport->index] = flow; |
ac004b83 RD |
1237 | } |
1238 | ||
1239 | esw->fdb_table.offloads.peer_miss_rules = flows; | |
1240 | ||
1241 | kvfree(spec); | |
1242 | return 0; | |
1243 | ||
81cd229c | 1244 | add_vf_flow_err: |
47dd7e60 PP |
1245 | mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) { |
1246 | if (!flows[vport->index]) | |
1247 | continue; | |
1248 | mlx5_del_flow_rules(flows[vport->index]); | |
1249 | } | |
1250 | if (mlx5_ecpf_vport_exists(esw->dev)) { | |
1251 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); | |
1252 | mlx5_del_flow_rules(flows[vport->index]); | |
1253 | } | |
81cd229c | 1254 | add_ecpf_flow_err: |
47dd7e60 PP |
1255 | if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { |
1256 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); | |
1257 | mlx5_del_flow_rules(flows[vport->index]); | |
1258 | } | |
81cd229c BW |
1259 | add_pf_flow_err: |
1260 | esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err); | |
ac004b83 RD |
1261 | kvfree(flows); |
1262 | alloc_flows_err: | |
1263 | kvfree(spec); | |
1264 | return err; | |
1265 | } | |
1266 | ||
1267 | static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw) | |
1268 | { | |
1269 | struct mlx5_flow_handle **flows; | |
47dd7e60 PP |
1270 | struct mlx5_vport *vport; |
1271 | unsigned long i; | |
ac004b83 RD |
1272 | |
1273 | flows = esw->fdb_table.offloads.peer_miss_rules; | |
1274 | ||
47dd7e60 PP |
1275 | mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) |
1276 | mlx5_del_flow_rules(flows[vport->index]); | |
ac004b83 | 1277 | |
47dd7e60 PP |
1278 | if (mlx5_ecpf_vport_exists(esw->dev)) { |
1279 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF); | |
1280 | mlx5_del_flow_rules(flows[vport->index]); | |
1281 | } | |
81cd229c | 1282 | |
47dd7e60 PP |
1283 | if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { |
1284 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF); | |
1285 | mlx5_del_flow_rules(flows[vport->index]); | |
1286 | } | |
ac004b83 RD |
1287 | kvfree(flows); |
1288 | } | |
1289 | ||
3aa33572 OG |
1290 | static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw) |
1291 | { | |
66958ed9 | 1292 | struct mlx5_flow_act flow_act = {0}; |
4c5009c5 | 1293 | struct mlx5_flow_destination dest = {}; |
74491de9 | 1294 | struct mlx5_flow_handle *flow_rule = NULL; |
c5bb1730 | 1295 | struct mlx5_flow_spec *spec; |
f80be543 MB |
1296 | void *headers_c; |
1297 | void *headers_v; | |
3aa33572 | 1298 | int err = 0; |
f80be543 MB |
1299 | u8 *dmac_c; |
1300 | u8 *dmac_v; | |
3aa33572 | 1301 | |
1b9a07ee | 1302 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
c5bb1730 | 1303 | if (!spec) { |
3aa33572 OG |
1304 | err = -ENOMEM; |
1305 | goto out; | |
1306 | } | |
1307 | ||
f80be543 MB |
1308 | spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS; |
1309 | headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1310 | outer_headers); | |
1311 | dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c, | |
1312 | outer_headers.dmac_47_16); | |
1313 | dmac_c[0] = 0x01; | |
1314 | ||
3aa33572 | 1315 | dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT; |
a1b3839a | 1316 | dest.vport.num = esw->manager_vport; |
66958ed9 | 1317 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
3aa33572 | 1318 | |
39ac237c PB |
1319 | flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, |
1320 | spec, &flow_act, &dest, 1); | |
3aa33572 OG |
1321 | if (IS_ERR(flow_rule)) { |
1322 | err = PTR_ERR(flow_rule); | |
f80be543 | 1323 | esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err); |
3aa33572 OG |
1324 | goto out; |
1325 | } | |
1326 | ||
f80be543 MB |
1327 | esw->fdb_table.offloads.miss_rule_uni = flow_rule; |
1328 | ||
1329 | headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1330 | outer_headers); | |
1331 | dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v, | |
1332 | outer_headers.dmac_47_16); | |
1333 | dmac_v[0] = 0x01; | |
39ac237c PB |
1334 | flow_rule = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb, |
1335 | spec, &flow_act, &dest, 1); | |
f80be543 MB |
1336 | if (IS_ERR(flow_rule)) { |
1337 | err = PTR_ERR(flow_rule); | |
1338 | esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err); | |
1339 | mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni); | |
1340 | goto out; | |
1341 | } | |
1342 | ||
1343 | esw->fdb_table.offloads.miss_rule_multi = flow_rule; | |
1344 | ||
3aa33572 | 1345 | out: |
c5bb1730 | 1346 | kvfree(spec); |
3aa33572 OG |
1347 | return err; |
1348 | } | |
1349 | ||
11b717d6 PB |
1350 | struct mlx5_flow_handle * |
1351 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) | |
1352 | { | |
1353 | struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, }; | |
1354 | struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore; | |
1355 | struct mlx5_flow_context *flow_context; | |
1356 | struct mlx5_flow_handle *flow_rule; | |
1357 | struct mlx5_flow_destination dest; | |
1358 | struct mlx5_flow_spec *spec; | |
1359 | void *misc; | |
1360 | ||
60acc105 PB |
1361 | if (!mlx5_eswitch_reg_c1_loopback_supported(esw)) |
1362 | return ERR_PTR(-EOPNOTSUPP); | |
1363 | ||
9f4d9283 | 1364 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
11b717d6 PB |
1365 | if (!spec) |
1366 | return ERR_PTR(-ENOMEM); | |
1367 | ||
1368 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1369 | misc_parameters_2); | |
1370 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, | |
a91d98a0 | 1371 | ESW_REG_C0_USER_DATA_METADATA_MASK); |
11b717d6 PB |
1372 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, |
1373 | misc_parameters_2); | |
1374 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag); | |
1375 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; | |
6724e66b PB |
1376 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | |
1377 | MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; | |
1378 | flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id; | |
11b717d6 PB |
1379 | |
1380 | flow_context = &spec->flow_context; | |
1381 | flow_context->flags |= FLOW_CONTEXT_HAS_TAG; | |
1382 | flow_context->flow_tag = tag; | |
1383 | dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
1384 | dest.ft = esw->offloads.ft_offloads; | |
1385 | ||
1386 | flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1); | |
9f4d9283 | 1387 | kvfree(spec); |
11b717d6 PB |
1388 | |
1389 | if (IS_ERR(flow_rule)) | |
1390 | esw_warn(esw->dev, | |
1391 | "Failed to create restore rule for tag: %d, err(%d)\n", | |
1392 | tag, (int)PTR_ERR(flow_rule)); | |
1393 | ||
1394 | return flow_rule; | |
1395 | } | |
1396 | ||
1967ce6e | 1397 | #define MAX_PF_SQ 256 |
cd3d07e7 | 1398 | #define MAX_SQ_NVPORTS 32 |
1967ce6e | 1399 | |
a5641cb5 JL |
1400 | static void esw_set_flow_group_source_port(struct mlx5_eswitch *esw, |
1401 | u32 *flow_group_in) | |
1402 | { | |
1403 | void *match_criteria = MLX5_ADDR_OF(create_flow_group_in, | |
1404 | flow_group_in, | |
1405 | match_criteria); | |
1406 | ||
1407 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { | |
1408 | MLX5_SET(create_flow_group_in, flow_group_in, | |
1409 | match_criteria_enable, | |
1410 | MLX5_MATCH_MISC_PARAMETERS_2); | |
1411 | ||
0f0d3827 PB |
1412 | MLX5_SET(fte_match_param, match_criteria, |
1413 | misc_parameters_2.metadata_reg_c_0, | |
1414 | mlx5_eswitch_get_vport_metadata_mask()); | |
a5641cb5 JL |
1415 | } else { |
1416 | MLX5_SET(create_flow_group_in, flow_group_in, | |
1417 | match_criteria_enable, | |
1418 | MLX5_MATCH_MISC_PARAMETERS); | |
1419 | ||
1420 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, | |
1421 | misc_parameters.source_port); | |
1422 | } | |
1423 | } | |
1424 | ||
ae430332 | 1425 | #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) |
0a9e2307 | 1426 | static void esw_vport_tbl_put(struct mlx5_eswitch *esw) |
4c7f4028 CM |
1427 | { |
1428 | struct mlx5_vport_tbl_attr attr; | |
1429 | struct mlx5_vport *vport; | |
47dd7e60 | 1430 | unsigned long i; |
4c7f4028 CM |
1431 | |
1432 | attr.chain = 0; | |
1433 | attr.prio = 1; | |
47dd7e60 | 1434 | mlx5_esw_for_each_vport(esw, i, vport) { |
4c7f4028 | 1435 | attr.vport = vport->vport; |
c796bb7c | 1436 | attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
0a9e2307 | 1437 | mlx5_esw_vporttbl_put(esw, &attr); |
4c7f4028 CM |
1438 | } |
1439 | } | |
1440 | ||
0a9e2307 | 1441 | static int esw_vport_tbl_get(struct mlx5_eswitch *esw) |
4c7f4028 CM |
1442 | { |
1443 | struct mlx5_vport_tbl_attr attr; | |
1444 | struct mlx5_flow_table *fdb; | |
1445 | struct mlx5_vport *vport; | |
47dd7e60 | 1446 | unsigned long i; |
4c7f4028 CM |
1447 | |
1448 | attr.chain = 0; | |
1449 | attr.prio = 1; | |
47dd7e60 | 1450 | mlx5_esw_for_each_vport(esw, i, vport) { |
4c7f4028 | 1451 | attr.vport = vport->vport; |
c796bb7c | 1452 | attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns; |
0a9e2307 | 1453 | fdb = mlx5_esw_vporttbl_get(esw, &attr); |
4c7f4028 CM |
1454 | if (IS_ERR(fdb)) |
1455 | goto out; | |
1456 | } | |
1457 | return 0; | |
1458 | ||
1459 | out: | |
0a9e2307 | 1460 | esw_vport_tbl_put(esw); |
4c7f4028 CM |
1461 | return PTR_ERR(fdb); |
1462 | } | |
1463 | ||
ae430332 AL |
1464 | #define fdb_modify_header_fwd_to_table_supported(esw) \ |
1465 | (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table)) | |
1466 | static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags) | |
1467 | { | |
1468 | struct mlx5_core_dev *dev = esw->dev; | |
1469 | ||
1470 | if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level)) | |
1471 | *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED; | |
1472 | ||
1473 | if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) && | |
1474 | esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) { | |
1475 | *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED; | |
1476 | esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n"); | |
1477 | } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) { | |
1478 | *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED; | |
1479 | esw_warn(dev, "Tc chains and priorities offload aren't supported\n"); | |
1480 | } else if (!fdb_modify_header_fwd_to_table_supported(esw)) { | |
1481 | /* Disabled when ttl workaround is needed, e.g | |
1482 | * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig | |
1483 | */ | |
1484 | esw_warn(dev, | |
1485 | "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n"); | |
1486 | *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED; | |
1487 | } else { | |
1488 | *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED; | |
1489 | esw_info(dev, "Supported tc chains and prios offload\n"); | |
1490 | } | |
1491 | ||
1492 | if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) | |
1493 | *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED; | |
1494 | } | |
1495 | ||
1496 | static int | |
1497 | esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb) | |
1498 | { | |
1499 | struct mlx5_core_dev *dev = esw->dev; | |
1500 | struct mlx5_flow_table *nf_ft, *ft; | |
1501 | struct mlx5_chains_attr attr = {}; | |
1502 | struct mlx5_fs_chains *chains; | |
1503 | u32 fdb_max; | |
1504 | int err; | |
1505 | ||
1506 | fdb_max = 1 << MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size); | |
1507 | ||
1508 | esw_init_chains_offload_flags(esw, &attr.flags); | |
1509 | attr.ns = MLX5_FLOW_NAMESPACE_FDB; | |
1510 | attr.max_ft_sz = fdb_max; | |
1511 | attr.max_grp_num = esw->params.large_group_num; | |
1512 | attr.default_ft = miss_fdb; | |
c9355682 | 1513 | attr.mapping = esw->offloads.reg_c0_obj_pool; |
ae430332 AL |
1514 | |
1515 | chains = mlx5_chains_create(dev, &attr); | |
1516 | if (IS_ERR(chains)) { | |
1517 | err = PTR_ERR(chains); | |
1518 | esw_warn(dev, "Failed to create fdb chains err(%d)\n", err); | |
1519 | return err; | |
1520 | } | |
1521 | ||
1522 | esw->fdb_table.offloads.esw_chains_priv = chains; | |
1523 | ||
1524 | /* Create tc_end_ft which is the always created ft chain */ | |
1525 | nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains), | |
1526 | 1, 0); | |
1527 | if (IS_ERR(nf_ft)) { | |
1528 | err = PTR_ERR(nf_ft); | |
1529 | goto nf_ft_err; | |
1530 | } | |
1531 | ||
1532 | /* Always open the root for fast path */ | |
1533 | ft = mlx5_chains_get_table(chains, 0, 1, 0); | |
1534 | if (IS_ERR(ft)) { | |
1535 | err = PTR_ERR(ft); | |
1536 | goto level_0_err; | |
1537 | } | |
1538 | ||
1539 | /* Open level 1 for split fdb rules now if prios isn't supported */ | |
1540 | if (!mlx5_chains_prios_supported(chains)) { | |
0a9e2307 | 1541 | err = esw_vport_tbl_get(esw); |
ae430332 AL |
1542 | if (err) |
1543 | goto level_1_err; | |
1544 | } | |
1545 | ||
1546 | mlx5_chains_set_end_ft(chains, nf_ft); | |
1547 | ||
1548 | return 0; | |
1549 | ||
1550 | level_1_err: | |
1551 | mlx5_chains_put_table(chains, 0, 1, 0); | |
1552 | level_0_err: | |
1553 | mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0); | |
1554 | nf_ft_err: | |
1555 | mlx5_chains_destroy(chains); | |
1556 | esw->fdb_table.offloads.esw_chains_priv = NULL; | |
1557 | ||
1558 | return err; | |
1559 | } | |
1560 | ||
1561 | static void | |
1562 | esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains) | |
1563 | { | |
1564 | if (!mlx5_chains_prios_supported(chains)) | |
0a9e2307 | 1565 | esw_vport_tbl_put(esw); |
ae430332 AL |
1566 | mlx5_chains_put_table(chains, 0, 1, 0); |
1567 | mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0); | |
1568 | mlx5_chains_destroy(chains); | |
1569 | } | |
1570 | ||
1571 | #else /* CONFIG_MLX5_CLS_ACT */ | |
1572 | ||
1573 | static int | |
1574 | esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb) | |
1575 | { return 0; } | |
1576 | ||
1577 | static void | |
1578 | esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains) | |
1579 | {} | |
1580 | ||
1581 | #endif | |
1582 | ||
0da3c12d | 1583 | static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw) |
1967ce6e OG |
1584 | { |
1585 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); | |
1586 | struct mlx5_flow_table_attr ft_attr = {}; | |
8e404fef | 1587 | int num_vfs, table_size, ix, err = 0; |
1967ce6e OG |
1588 | struct mlx5_core_dev *dev = esw->dev; |
1589 | struct mlx5_flow_namespace *root_ns; | |
1590 | struct mlx5_flow_table *fdb = NULL; | |
39ac237c | 1591 | u32 flags = 0, *flow_group_in; |
1967ce6e OG |
1592 | struct mlx5_flow_group *g; |
1593 | void *match_criteria; | |
f80be543 | 1594 | u8 *dmac; |
1967ce6e OG |
1595 | |
1596 | esw_debug(esw->dev, "Create offloads FDB Tables\n"); | |
39ac237c | 1597 | |
1b9a07ee | 1598 | flow_group_in = kvzalloc(inlen, GFP_KERNEL); |
1967ce6e OG |
1599 | if (!flow_group_in) |
1600 | return -ENOMEM; | |
1601 | ||
1602 | root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB); | |
1603 | if (!root_ns) { | |
1604 | esw_warn(dev, "Failed to get FDB flow namespace\n"); | |
1605 | err = -EOPNOTSUPP; | |
1606 | goto ns_err; | |
1607 | } | |
8463daf1 MG |
1608 | esw->fdb_table.offloads.ns = root_ns; |
1609 | err = mlx5_flow_namespace_set_mode(root_ns, | |
1610 | esw->dev->priv.steering->mode); | |
1611 | if (err) { | |
1612 | esw_warn(dev, "Failed to set FDB namespace steering mode\n"); | |
1613 | goto ns_err; | |
1614 | } | |
1967ce6e | 1615 | |
0da3c12d | 1616 | table_size = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ + |
8e404fef | 1617 | MLX5_ESW_MISS_FLOWS + esw->total_vports + esw->esw_funcs.num_vfs; |
b3ba5149 | 1618 | |
e52c2802 PB |
1619 | /* create the slow path fdb with encap set, so further table instances |
1620 | * can be created at run time while VFs are probed if the FW allows that. | |
1621 | */ | |
1622 | if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) | |
1623 | flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT | | |
1624 | MLX5_FLOW_TABLE_TUNNEL_EN_DECAP); | |
1625 | ||
1626 | ft_attr.flags = flags; | |
b3ba5149 ES |
1627 | ft_attr.max_fte = table_size; |
1628 | ft_attr.prio = FDB_SLOW_PATH; | |
1629 | ||
1630 | fdb = mlx5_create_flow_table(root_ns, &ft_attr); | |
1033665e OG |
1631 | if (IS_ERR(fdb)) { |
1632 | err = PTR_ERR(fdb); | |
1633 | esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err); | |
1634 | goto slow_fdb_err; | |
1635 | } | |
52fff327 | 1636 | esw->fdb_table.offloads.slow_fdb = fdb; |
1033665e | 1637 | |
ec3be887 VB |
1638 | /* Create empty TC-miss managed table. This allows plugging in following |
1639 | * priorities without directly exposing their level 0 table to | |
1640 | * eswitch_offloads and passing it as miss_fdb to following call to | |
1641 | * esw_chains_create(). | |
1642 | */ | |
1643 | memset(&ft_attr, 0, sizeof(ft_attr)); | |
1644 | ft_attr.prio = FDB_TC_MISS; | |
1645 | esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr); | |
1646 | if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) { | |
1647 | err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table); | |
1648 | esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err); | |
1649 | goto tc_miss_table_err; | |
1650 | } | |
1651 | ||
1652 | err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table); | |
39ac237c | 1653 | if (err) { |
ae430332 | 1654 | esw_warn(dev, "Failed to open fdb chains err(%d)\n", err); |
39ac237c | 1655 | goto fdb_chains_err; |
e52c2802 PB |
1656 | } |
1657 | ||
69697b6e | 1658 | /* create send-to-vport group */ |
69697b6e OG |
1659 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, |
1660 | MLX5_MATCH_MISC_PARAMETERS); | |
1661 | ||
1662 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria); | |
1663 | ||
1664 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn); | |
1665 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port); | |
7d97822a MB |
1666 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) { |
1667 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, | |
1668 | misc_parameters.source_eswitch_owner_vhca_id); | |
1669 | MLX5_SET(create_flow_group_in, flow_group_in, | |
1670 | source_eswitch_owner_vhca_id_valid, 1); | |
1671 | } | |
69697b6e | 1672 | |
0da3c12d | 1673 | ix = esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ; |
69697b6e OG |
1674 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); |
1675 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, ix - 1); | |
1676 | ||
1677 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
1678 | if (IS_ERR(g)) { | |
1679 | err = PTR_ERR(g); | |
1680 | esw_warn(dev, "Failed to create send-to-vport flow group err(%d)\n", err); | |
1681 | goto send_vport_err; | |
1682 | } | |
1683 | esw->fdb_table.offloads.send_to_vport_grp = g; | |
1684 | ||
e929e3da MD |
1685 | if (esw_src_port_rewrite_supported(esw)) { |
1686 | /* meta send to vport */ | |
1687 | memset(flow_group_in, 0, inlen); | |
1688 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, | |
1689 | MLX5_MATCH_MISC_PARAMETERS_2); | |
8e404fef | 1690 | |
e929e3da | 1691 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria); |
8e404fef | 1692 | |
e929e3da MD |
1693 | MLX5_SET(fte_match_param, match_criteria, |
1694 | misc_parameters_2.metadata_reg_c_0, | |
1695 | mlx5_eswitch_get_vport_metadata_mask()); | |
1696 | MLX5_SET(fte_match_param, match_criteria, | |
1697 | misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK); | |
1698 | ||
1699 | num_vfs = esw->esw_funcs.num_vfs; | |
1700 | if (num_vfs) { | |
1701 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix); | |
1702 | MLX5_SET(create_flow_group_in, flow_group_in, | |
1703 | end_flow_index, ix + num_vfs - 1); | |
1704 | ix += num_vfs; | |
1705 | ||
1706 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
1707 | if (IS_ERR(g)) { | |
1708 | err = PTR_ERR(g); | |
1709 | esw_warn(dev, "Failed to create send-to-vport meta flow group err(%d)\n", | |
1710 | err); | |
1711 | goto send_vport_meta_err; | |
1712 | } | |
1713 | esw->fdb_table.offloads.send_to_vport_meta_grp = g; | |
1714 | ||
1715 | err = mlx5_eswitch_add_send_to_vport_meta_rules(esw); | |
1716 | if (err) | |
1717 | goto meta_rule_err; | |
8e404fef | 1718 | } |
8e404fef VB |
1719 | } |
1720 | ||
6cec0229 MD |
1721 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) { |
1722 | /* create peer esw miss group */ | |
1723 | memset(flow_group_in, 0, inlen); | |
ac004b83 | 1724 | |
6cec0229 | 1725 | esw_set_flow_group_source_port(esw, flow_group_in); |
a5641cb5 | 1726 | |
6cec0229 MD |
1727 | if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) { |
1728 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, | |
1729 | flow_group_in, | |
1730 | match_criteria); | |
ac004b83 | 1731 | |
6cec0229 MD |
1732 | MLX5_SET_TO_ONES(fte_match_param, match_criteria, |
1733 | misc_parameters.source_eswitch_owner_vhca_id); | |
a5641cb5 | 1734 | |
6cec0229 MD |
1735 | MLX5_SET(create_flow_group_in, flow_group_in, |
1736 | source_eswitch_owner_vhca_id_valid, 1); | |
1737 | } | |
ac004b83 | 1738 | |
6cec0229 MD |
1739 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix); |
1740 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, | |
1741 | ix + esw->total_vports - 1); | |
1742 | ix += esw->total_vports; | |
ac004b83 | 1743 | |
6cec0229 MD |
1744 | g = mlx5_create_flow_group(fdb, flow_group_in); |
1745 | if (IS_ERR(g)) { | |
1746 | err = PTR_ERR(g); | |
1747 | esw_warn(dev, "Failed to create peer miss flow group err(%d)\n", err); | |
1748 | goto peer_miss_err; | |
1749 | } | |
1750 | esw->fdb_table.offloads.peer_miss_grp = g; | |
ac004b83 | 1751 | } |
ac004b83 | 1752 | |
69697b6e OG |
1753 | /* create miss group */ |
1754 | memset(flow_group_in, 0, inlen); | |
f80be543 MB |
1755 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, |
1756 | MLX5_MATCH_OUTER_HEADERS); | |
1757 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, | |
1758 | match_criteria); | |
1759 | dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, | |
1760 | outer_headers.dmac_47_16); | |
1761 | dmac[0] = 0x01; | |
69697b6e OG |
1762 | |
1763 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, ix); | |
cd7e4186 BW |
1764 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, |
1765 | ix + MLX5_ESW_MISS_FLOWS); | |
69697b6e OG |
1766 | |
1767 | g = mlx5_create_flow_group(fdb, flow_group_in); | |
1768 | if (IS_ERR(g)) { | |
1769 | err = PTR_ERR(g); | |
1770 | esw_warn(dev, "Failed to create miss flow group err(%d)\n", err); | |
1771 | goto miss_err; | |
1772 | } | |
1773 | esw->fdb_table.offloads.miss_grp = g; | |
1774 | ||
3aa33572 OG |
1775 | err = esw_add_fdb_miss_rule(esw); |
1776 | if (err) | |
1777 | goto miss_rule_err; | |
1778 | ||
c88a026e | 1779 | kvfree(flow_group_in); |
69697b6e OG |
1780 | return 0; |
1781 | ||
3aa33572 OG |
1782 | miss_rule_err: |
1783 | mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp); | |
69697b6e | 1784 | miss_err: |
6cec0229 MD |
1785 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) |
1786 | mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp); | |
ac004b83 | 1787 | peer_miss_err: |
8e404fef VB |
1788 | mlx5_eswitch_del_send_to_vport_meta_rules(esw); |
1789 | meta_rule_err: | |
1790 | if (esw->fdb_table.offloads.send_to_vport_meta_grp) | |
1791 | mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp); | |
1792 | send_vport_meta_err: | |
69697b6e OG |
1793 | mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp); |
1794 | send_vport_err: | |
ae430332 | 1795 | esw_chains_destroy(esw, esw_chains(esw)); |
39ac237c | 1796 | fdb_chains_err: |
ec3be887 VB |
1797 | mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table); |
1798 | tc_miss_table_err: | |
52fff327 | 1799 | mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb); |
1033665e | 1800 | slow_fdb_err: |
8463daf1 MG |
1801 | /* Holds true only as long as DMFS is the default */ |
1802 | mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS); | |
69697b6e OG |
1803 | ns_err: |
1804 | kvfree(flow_group_in); | |
1805 | return err; | |
1806 | } | |
1807 | ||
1967ce6e | 1808 | static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw) |
69697b6e | 1809 | { |
e52c2802 | 1810 | if (!esw->fdb_table.offloads.slow_fdb) |
69697b6e OG |
1811 | return; |
1812 | ||
1967ce6e | 1813 | esw_debug(esw->dev, "Destroy offloads FDB Tables\n"); |
f80be543 MB |
1814 | mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi); |
1815 | mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni); | |
8e404fef | 1816 | mlx5_eswitch_del_send_to_vport_meta_rules(esw); |
69697b6e | 1817 | mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp); |
8e404fef VB |
1818 | if (esw->fdb_table.offloads.send_to_vport_meta_grp) |
1819 | mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp); | |
6cec0229 MD |
1820 | if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) |
1821 | mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp); | |
69697b6e OG |
1822 | mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp); |
1823 | ||
ae430332 AL |
1824 | esw_chains_destroy(esw, esw_chains(esw)); |
1825 | ||
ec3be887 | 1826 | mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table); |
52fff327 | 1827 | mlx5_destroy_flow_table(esw->fdb_table.offloads.slow_fdb); |
8463daf1 MG |
1828 | /* Holds true only as long as DMFS is the default */ |
1829 | mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns, | |
1830 | MLX5_FLOW_STEERING_MODE_DMFS); | |
7dc84de9 | 1831 | atomic64_set(&esw->user_count, 0); |
69697b6e | 1832 | } |
c116c6ee | 1833 | |
8d6bd3c3 | 1834 | static int esw_create_offloads_table(struct mlx5_eswitch *esw) |
c116c6ee | 1835 | { |
b3ba5149 | 1836 | struct mlx5_flow_table_attr ft_attr = {}; |
c116c6ee | 1837 | struct mlx5_core_dev *dev = esw->dev; |
b3ba5149 ES |
1838 | struct mlx5_flow_table *ft_offloads; |
1839 | struct mlx5_flow_namespace *ns; | |
c116c6ee OG |
1840 | int err = 0; |
1841 | ||
1842 | ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS); | |
1843 | if (!ns) { | |
1844 | esw_warn(esw->dev, "Failed to get offloads flow namespace\n"); | |
eff596da | 1845 | return -EOPNOTSUPP; |
c116c6ee OG |
1846 | } |
1847 | ||
8d6bd3c3 | 1848 | ft_attr.max_fte = esw->total_vports + MLX5_ESW_MISS_FLOWS; |
11b717d6 | 1849 | ft_attr.prio = 1; |
b3ba5149 ES |
1850 | |
1851 | ft_offloads = mlx5_create_flow_table(ns, &ft_attr); | |
c116c6ee OG |
1852 | if (IS_ERR(ft_offloads)) { |
1853 | err = PTR_ERR(ft_offloads); | |
1854 | esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err); | |
1855 | return err; | |
1856 | } | |
1857 | ||
1858 | esw->offloads.ft_offloads = ft_offloads; | |
1859 | return 0; | |
1860 | } | |
1861 | ||
1862 | static void esw_destroy_offloads_table(struct mlx5_eswitch *esw) | |
1863 | { | |
1864 | struct mlx5_esw_offload *offloads = &esw->offloads; | |
1865 | ||
1866 | mlx5_destroy_flow_table(offloads->ft_offloads); | |
1867 | } | |
fed9ce22 | 1868 | |
8d6bd3c3 | 1869 | static int esw_create_vport_rx_group(struct mlx5_eswitch *esw) |
fed9ce22 OG |
1870 | { |
1871 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); | |
1872 | struct mlx5_flow_group *g; | |
fed9ce22 | 1873 | u32 *flow_group_in; |
8d6bd3c3 | 1874 | int nvports; |
fed9ce22 | 1875 | int err = 0; |
fed9ce22 | 1876 | |
8d6bd3c3 | 1877 | nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS; |
1b9a07ee | 1878 | flow_group_in = kvzalloc(inlen, GFP_KERNEL); |
fed9ce22 OG |
1879 | if (!flow_group_in) |
1880 | return -ENOMEM; | |
1881 | ||
1882 | /* create vport rx group */ | |
a5641cb5 | 1883 | esw_set_flow_group_source_port(esw, flow_group_in); |
fed9ce22 OG |
1884 | |
1885 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); | |
1886 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1); | |
1887 | ||
1888 | g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in); | |
1889 | ||
1890 | if (IS_ERR(g)) { | |
1891 | err = PTR_ERR(g); | |
1892 | mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err); | |
1893 | goto out; | |
1894 | } | |
1895 | ||
1896 | esw->offloads.vport_rx_group = g; | |
1897 | out: | |
e574978a | 1898 | kvfree(flow_group_in); |
fed9ce22 OG |
1899 | return err; |
1900 | } | |
1901 | ||
1902 | static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw) | |
1903 | { | |
1904 | mlx5_destroy_flow_group(esw->offloads.vport_rx_group); | |
1905 | } | |
1906 | ||
74491de9 | 1907 | struct mlx5_flow_handle * |
02f3afd9 | 1908 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 1909 | struct mlx5_flow_destination *dest) |
fed9ce22 | 1910 | { |
66958ed9 | 1911 | struct mlx5_flow_act flow_act = {0}; |
74491de9 | 1912 | struct mlx5_flow_handle *flow_rule; |
c5bb1730 | 1913 | struct mlx5_flow_spec *spec; |
fed9ce22 OG |
1914 | void *misc; |
1915 | ||
1b9a07ee | 1916 | spec = kvzalloc(sizeof(*spec), GFP_KERNEL); |
c5bb1730 | 1917 | if (!spec) { |
fed9ce22 OG |
1918 | flow_rule = ERR_PTR(-ENOMEM); |
1919 | goto out; | |
1920 | } | |
1921 | ||
a5641cb5 JL |
1922 | if (mlx5_eswitch_vport_match_metadata_enabled(esw)) { |
1923 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); | |
1924 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, | |
1925 | mlx5_eswitch_get_vport_metadata_for_match(esw, vport)); | |
fed9ce22 | 1926 | |
a5641cb5 | 1927 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2); |
0f0d3827 PB |
1928 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, |
1929 | mlx5_eswitch_get_vport_metadata_mask()); | |
fed9ce22 | 1930 | |
a5641cb5 JL |
1931 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2; |
1932 | } else { | |
1933 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); | |
1934 | MLX5_SET(fte_match_set_misc, misc, source_port, vport); | |
1935 | ||
1936 | misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters); | |
1937 | MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); | |
1938 | ||
1939 | spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS; | |
1940 | } | |
fed9ce22 | 1941 | |
66958ed9 | 1942 | flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
74491de9 | 1943 | flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec, |
c966f7d5 | 1944 | &flow_act, dest, 1); |
fed9ce22 OG |
1945 | if (IS_ERR(flow_rule)) { |
1946 | esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule)); | |
1947 | goto out; | |
1948 | } | |
1949 | ||
1950 | out: | |
c5bb1730 | 1951 | kvfree(spec); |
fed9ce22 OG |
1952 | return flow_rule; |
1953 | } | |
feae9087 | 1954 | |
47dd7e60 | 1955 | static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode) |
cc617ced PP |
1956 | { |
1957 | u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2; | |
1958 | struct mlx5_core_dev *dev = esw->dev; | |
47dd7e60 PP |
1959 | struct mlx5_vport *vport; |
1960 | unsigned long i; | |
cc617ced PP |
1961 | |
1962 | if (!MLX5_CAP_GEN(dev, vport_group_manager)) | |
1963 | return -EOPNOTSUPP; | |
1964 | ||
1965 | if (esw->mode == MLX5_ESWITCH_NONE) | |
1966 | return -EOPNOTSUPP; | |
1967 | ||
1968 | switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) { | |
1969 | case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: | |
1970 | mlx5_mode = MLX5_INLINE_MODE_NONE; | |
1971 | goto out; | |
1972 | case MLX5_CAP_INLINE_MODE_L2: | |
1973 | mlx5_mode = MLX5_INLINE_MODE_L2; | |
1974 | goto out; | |
1975 | case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: | |
1976 | goto query_vports; | |
1977 | } | |
1978 | ||
1979 | query_vports: | |
1980 | mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode); | |
47dd7e60 PP |
1981 | mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) { |
1982 | mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode); | |
cc617ced PP |
1983 | if (prev_mlx5_mode != mlx5_mode) |
1984 | return -EINVAL; | |
1985 | prev_mlx5_mode = mlx5_mode; | |
1986 | } | |
1987 | ||
1988 | out: | |
1989 | *mode = mlx5_mode; | |
1990 | return 0; | |
e08a6832 | 1991 | } |
bf3347c4 | 1992 | |
11b717d6 PB |
1993 | static void esw_destroy_restore_table(struct mlx5_eswitch *esw) |
1994 | { | |
1995 | struct mlx5_esw_offload *offloads = &esw->offloads; | |
1996 | ||
60acc105 PB |
1997 | if (!mlx5_eswitch_reg_c1_loopback_supported(esw)) |
1998 | return; | |
1999 | ||
6724e66b | 2000 | mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id); |
11b717d6 PB |
2001 | mlx5_destroy_flow_group(offloads->restore_group); |
2002 | mlx5_destroy_flow_table(offloads->ft_offloads_restore); | |
2003 | } | |
2004 | ||
2005 | static int esw_create_restore_table(struct mlx5_eswitch *esw) | |
2006 | { | |
d65dbedf | 2007 | u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {}; |
11b717d6 PB |
2008 | int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in); |
2009 | struct mlx5_flow_table_attr ft_attr = {}; | |
2010 | struct mlx5_core_dev *dev = esw->dev; | |
2011 | struct mlx5_flow_namespace *ns; | |
6724e66b | 2012 | struct mlx5_modify_hdr *mod_hdr; |
11b717d6 PB |
2013 | void *match_criteria, *misc; |
2014 | struct mlx5_flow_table *ft; | |
2015 | struct mlx5_flow_group *g; | |
2016 | u32 *flow_group_in; | |
2017 | int err = 0; | |
2018 | ||
60acc105 PB |
2019 | if (!mlx5_eswitch_reg_c1_loopback_supported(esw)) |
2020 | return 0; | |
2021 | ||
11b717d6 PB |
2022 | ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS); |
2023 | if (!ns) { | |
2024 | esw_warn(esw->dev, "Failed to get offloads flow namespace\n"); | |
2025 | return -EOPNOTSUPP; | |
2026 | } | |
2027 | ||
2028 | flow_group_in = kvzalloc(inlen, GFP_KERNEL); | |
2029 | if (!flow_group_in) { | |
2030 | err = -ENOMEM; | |
2031 | goto out_free; | |
2032 | } | |
2033 | ||
a91d98a0 | 2034 | ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS; |
11b717d6 PB |
2035 | ft = mlx5_create_flow_table(ns, &ft_attr); |
2036 | if (IS_ERR(ft)) { | |
2037 | err = PTR_ERR(ft); | |
2038 | esw_warn(esw->dev, "Failed to create restore table, err %d\n", | |
2039 | err); | |
2040 | goto out_free; | |
2041 | } | |
2042 | ||
11b717d6 PB |
2043 | match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, |
2044 | match_criteria); | |
2045 | misc = MLX5_ADDR_OF(fte_match_param, match_criteria, | |
2046 | misc_parameters_2); | |
2047 | ||
2048 | MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, | |
a91d98a0 | 2049 | ESW_REG_C0_USER_DATA_METADATA_MASK); |
11b717d6 PB |
2050 | MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0); |
2051 | MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, | |
2052 | ft_attr.max_fte - 1); | |
2053 | MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, | |
2054 | MLX5_MATCH_MISC_PARAMETERS_2); | |
2055 | g = mlx5_create_flow_group(ft, flow_group_in); | |
2056 | if (IS_ERR(g)) { | |
2057 | err = PTR_ERR(g); | |
2058 | esw_warn(dev, "Failed to create restore flow group, err: %d\n", | |
2059 | err); | |
2060 | goto err_group; | |
2061 | } | |
2062 | ||
6724e66b PB |
2063 | MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY); |
2064 | MLX5_SET(copy_action_in, modact, src_field, | |
2065 | MLX5_ACTION_IN_FIELD_METADATA_REG_C_1); | |
2066 | MLX5_SET(copy_action_in, modact, dst_field, | |
2067 | MLX5_ACTION_IN_FIELD_METADATA_REG_B); | |
2068 | mod_hdr = mlx5_modify_header_alloc(esw->dev, | |
2069 | MLX5_FLOW_NAMESPACE_KERNEL, 1, | |
2070 | modact); | |
2071 | if (IS_ERR(mod_hdr)) { | |
e9864539 | 2072 | err = PTR_ERR(mod_hdr); |
6724e66b PB |
2073 | esw_warn(dev, "Failed to create restore mod header, err: %d\n", |
2074 | err); | |
6724e66b PB |
2075 | goto err_mod_hdr; |
2076 | } | |
2077 | ||
11b717d6 PB |
2078 | esw->offloads.ft_offloads_restore = ft; |
2079 | esw->offloads.restore_group = g; | |
6724e66b | 2080 | esw->offloads.restore_copy_hdr_id = mod_hdr; |
11b717d6 | 2081 | |
c8508713 RD |
2082 | kvfree(flow_group_in); |
2083 | ||
11b717d6 PB |
2084 | return 0; |
2085 | ||
6724e66b PB |
2086 | err_mod_hdr: |
2087 | mlx5_destroy_flow_group(g); | |
11b717d6 PB |
2088 | err_group: |
2089 | mlx5_destroy_flow_table(ft); | |
2090 | out_free: | |
2091 | kvfree(flow_group_in); | |
2092 | ||
2093 | return err; | |
cc617ced PP |
2094 | } |
2095 | ||
db7ff19e EB |
2096 | static int esw_offloads_start(struct mlx5_eswitch *esw, |
2097 | struct netlink_ext_ack *extack) | |
c930a3ad | 2098 | { |
062f4bf4 | 2099 | int err, err1; |
c930a3ad | 2100 | |
8e0aa4bc PP |
2101 | mlx5_eswitch_disable_locked(esw, false); |
2102 | err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS, | |
2103 | esw->dev->priv.sriov.num_vfs); | |
6c419ba8 | 2104 | if (err) { |
8c98ee77 EB |
2105 | NL_SET_ERR_MSG_MOD(extack, |
2106 | "Failed setting eswitch to offloads"); | |
8e0aa4bc PP |
2107 | err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY, |
2108 | MLX5_ESWITCH_IGNORE_NUM_VFS); | |
8c98ee77 EB |
2109 | if (err1) { |
2110 | NL_SET_ERR_MSG_MOD(extack, | |
2111 | "Failed setting eswitch back to legacy"); | |
2112 | } | |
6c419ba8 | 2113 | } |
bffaa916 RD |
2114 | if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) { |
2115 | if (mlx5_eswitch_inline_mode_get(esw, | |
bffaa916 RD |
2116 | &esw->offloads.inline_mode)) { |
2117 | esw->offloads.inline_mode = MLX5_INLINE_MODE_L2; | |
8c98ee77 EB |
2118 | NL_SET_ERR_MSG_MOD(extack, |
2119 | "Inline mode is different between vports"); | |
bffaa916 RD |
2120 | } |
2121 | } | |
c930a3ad OG |
2122 | return err; |
2123 | } | |
2124 | ||
47dd7e60 PP |
2125 | static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw, |
2126 | struct mlx5_eswitch_rep *rep, | |
2127 | xa_mark_t mark) | |
e8d31c4d | 2128 | { |
47dd7e60 PP |
2129 | bool mark_set; |
2130 | ||
2131 | /* Copy the mark from vport to its rep */ | |
2132 | mark_set = xa_get_mark(&esw->vports, rep->vport, mark); | |
2133 | if (mark_set) | |
2134 | xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark); | |
e8d31c4d MB |
2135 | } |
2136 | ||
47dd7e60 | 2137 | static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport) |
e8d31c4d | 2138 | { |
e8d31c4d | 2139 | struct mlx5_eswitch_rep *rep; |
47dd7e60 PP |
2140 | int rep_type; |
2141 | int err; | |
e8d31c4d | 2142 | |
47dd7e60 PP |
2143 | rep = kzalloc(sizeof(*rep), GFP_KERNEL); |
2144 | if (!rep) | |
e8d31c4d MB |
2145 | return -ENOMEM; |
2146 | ||
47dd7e60 PP |
2147 | rep->vport = vport->vport; |
2148 | rep->vport_index = vport->index; | |
2149 | for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) | |
2150 | atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED); | |
f121e0ea | 2151 | |
47dd7e60 PP |
2152 | err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL); |
2153 | if (err) | |
2154 | goto insert_err; | |
2155 | ||
2156 | mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN); | |
2157 | mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF); | |
2158 | mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF); | |
2159 | return 0; | |
2160 | ||
2161 | insert_err: | |
2162 | kfree(rep); | |
2163 | return err; | |
2164 | } | |
2165 | ||
2166 | static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw, | |
2167 | struct mlx5_eswitch_rep *rep) | |
2168 | { | |
2169 | xa_erase(&esw->offloads.vport_reps, rep->vport); | |
2170 | kfree(rep); | |
2171 | } | |
2172 | ||
2173 | void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw) | |
2174 | { | |
2175 | struct mlx5_eswitch_rep *rep; | |
2176 | unsigned long i; | |
e8d31c4d | 2177 | |
47dd7e60 PP |
2178 | mlx5_esw_for_each_rep(esw, i, rep) |
2179 | mlx5_esw_offloads_rep_cleanup(esw, rep); | |
2180 | xa_destroy(&esw->offloads.vport_reps); | |
2181 | } | |
2182 | ||
2183 | int esw_offloads_init_reps(struct mlx5_eswitch *esw) | |
2184 | { | |
2185 | struct mlx5_vport *vport; | |
2186 | unsigned long i; | |
2187 | int err; | |
2188 | ||
2189 | xa_init(&esw->offloads.vport_reps); | |
2190 | ||
2191 | mlx5_esw_for_each_vport(esw, i, vport) { | |
2192 | err = mlx5_esw_offloads_rep_init(esw, vport); | |
2193 | if (err) | |
2194 | goto err; | |
2195 | } | |
e8d31c4d | 2196 | return 0; |
47dd7e60 PP |
2197 | |
2198 | err: | |
2199 | esw_offloads_cleanup_reps(esw); | |
2200 | return err; | |
e8d31c4d MB |
2201 | } |
2202 | ||
c9b99abc BW |
2203 | static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw, |
2204 | struct mlx5_eswitch_rep *rep, u8 rep_type) | |
2205 | { | |
8693115a | 2206 | if (atomic_cmpxchg(&rep->rep_data[rep_type].state, |
6f4e0219 | 2207 | REP_LOADED, REP_REGISTERED) == REP_LOADED) |
8693115a | 2208 | esw->offloads.rep_ops[rep_type]->unload(rep); |
c9b99abc BW |
2209 | } |
2210 | ||
d7f33a45 VP |
2211 | static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type) |
2212 | { | |
2213 | struct mlx5_eswitch_rep *rep; | |
47dd7e60 | 2214 | unsigned long i; |
d7f33a45 VP |
2215 | |
2216 | mlx5_esw_for_each_sf_rep(esw, i, rep) | |
2217 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
2218 | } | |
2219 | ||
4110fc59 | 2220 | static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type) |
6ed1803a MB |
2221 | { |
2222 | struct mlx5_eswitch_rep *rep; | |
47dd7e60 | 2223 | unsigned long i; |
4110fc59 | 2224 | |
d7f33a45 VP |
2225 | __unload_reps_sf_vport(esw, rep_type); |
2226 | ||
47dd7e60 | 2227 | mlx5_esw_for_each_vf_rep(esw, i, rep) |
4110fc59 | 2228 | __esw_offloads_unload_rep(esw, rep, rep_type); |
c9b99abc | 2229 | |
81cd229c BW |
2230 | if (mlx5_ecpf_vport_exists(esw->dev)) { |
2231 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF); | |
2232 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
2233 | } | |
2234 | ||
2235 | if (mlx5_core_is_ecpf_esw_manager(esw->dev)) { | |
2236 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF); | |
2237 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
2238 | } | |
2239 | ||
879c8f84 | 2240 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK); |
c9b99abc | 2241 | __esw_offloads_unload_rep(esw, rep, rep_type); |
6ed1803a MB |
2242 | } |
2243 | ||
d970812b | 2244 | int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num) |
a4b97ab4 | 2245 | { |
c2d7712c BW |
2246 | struct mlx5_eswitch_rep *rep; |
2247 | int rep_type; | |
a4b97ab4 MB |
2248 | int err; |
2249 | ||
c2d7712c BW |
2250 | rep = mlx5_eswitch_get_rep(esw, vport_num); |
2251 | for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) | |
2252 | if (atomic_cmpxchg(&rep->rep_data[rep_type].state, | |
2253 | REP_REGISTERED, REP_LOADED) == REP_REGISTERED) { | |
2254 | err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep); | |
2255 | if (err) | |
2256 | goto err_reps; | |
2257 | } | |
2258 | ||
2259 | return 0; | |
a4b97ab4 MB |
2260 | |
2261 | err_reps: | |
c2d7712c BW |
2262 | atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED); |
2263 | for (--rep_type; rep_type >= 0; rep_type--) | |
2264 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
6ed1803a MB |
2265 | return err; |
2266 | } | |
2267 | ||
d970812b | 2268 | void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num) |
c2d7712c BW |
2269 | { |
2270 | struct mlx5_eswitch_rep *rep; | |
2271 | int rep_type; | |
2272 | ||
c2d7712c BW |
2273 | rep = mlx5_eswitch_get_rep(esw, vport_num); |
2274 | for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--) | |
2275 | __esw_offloads_unload_rep(esw, rep, rep_type); | |
2276 | } | |
2277 | ||
38679b5a PP |
2278 | int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num) |
2279 | { | |
2280 | int err; | |
2281 | ||
2282 | if (esw->mode != MLX5_ESWITCH_OFFLOADS) | |
2283 | return 0; | |
2284 | ||
865d6d1c RD |
2285 | if (vport_num != MLX5_VPORT_UPLINK) { |
2286 | err = mlx5_esw_offloads_devlink_port_register(esw, vport_num); | |
2287 | if (err) | |
2288 | return err; | |
2289 | } | |
c7eddc60 | 2290 | |
38679b5a | 2291 | err = mlx5_esw_offloads_rep_load(esw, vport_num); |
c7eddc60 PP |
2292 | if (err) |
2293 | goto load_err; | |
2294 | return err; | |
2295 | ||
2296 | load_err: | |
865d6d1c RD |
2297 | if (vport_num != MLX5_VPORT_UPLINK) |
2298 | mlx5_esw_offloads_devlink_port_unregister(esw, vport_num); | |
38679b5a PP |
2299 | return err; |
2300 | } | |
2301 | ||
2302 | void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num) | |
2303 | { | |
2304 | if (esw->mode != MLX5_ESWITCH_OFFLOADS) | |
2305 | return; | |
2306 | ||
2307 | mlx5_esw_offloads_rep_unload(esw, vport_num); | |
865d6d1c RD |
2308 | |
2309 | if (vport_num != MLX5_VPORT_UPLINK) | |
2310 | mlx5_esw_offloads_devlink_port_unregister(esw, vport_num); | |
38679b5a PP |
2311 | } |
2312 | ||
ac004b83 RD |
2313 | #define ESW_OFFLOADS_DEVCOM_PAIR (0) |
2314 | #define ESW_OFFLOADS_DEVCOM_UNPAIR (1) | |
2315 | ||
2316 | static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw, | |
2317 | struct mlx5_eswitch *peer_esw) | |
2318 | { | |
ac004b83 | 2319 | |
027d7166 | 2320 | return esw_add_fdb_peer_miss_rules(esw, peer_esw->dev); |
ac004b83 RD |
2321 | } |
2322 | ||
2323 | static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw) | |
2324 | { | |
d956873f | 2325 | #if IS_ENABLED(CONFIG_MLX5_CLS_ACT) |
04de7dda | 2326 | mlx5e_tc_clean_fdb_peer_flows(esw); |
d956873f | 2327 | #endif |
ac004b83 RD |
2328 | esw_del_fdb_peer_miss_rules(esw); |
2329 | } | |
2330 | ||
8463daf1 MG |
2331 | static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw, |
2332 | struct mlx5_eswitch *peer_esw, | |
2333 | bool pair) | |
2334 | { | |
2335 | struct mlx5_flow_root_namespace *peer_ns; | |
2336 | struct mlx5_flow_root_namespace *ns; | |
2337 | int err; | |
2338 | ||
2339 | peer_ns = peer_esw->dev->priv.steering->fdb_root_ns; | |
2340 | ns = esw->dev->priv.steering->fdb_root_ns; | |
2341 | ||
2342 | if (pair) { | |
2343 | err = mlx5_flow_namespace_set_peer(ns, peer_ns); | |
2344 | if (err) | |
2345 | return err; | |
2346 | ||
e53e6655 | 2347 | err = mlx5_flow_namespace_set_peer(peer_ns, ns); |
8463daf1 MG |
2348 | if (err) { |
2349 | mlx5_flow_namespace_set_peer(ns, NULL); | |
2350 | return err; | |
2351 | } | |
2352 | } else { | |
2353 | mlx5_flow_namespace_set_peer(ns, NULL); | |
2354 | mlx5_flow_namespace_set_peer(peer_ns, NULL); | |
2355 | } | |
2356 | ||
2357 | return 0; | |
2358 | } | |
2359 | ||
ac004b83 RD |
2360 | static int mlx5_esw_offloads_devcom_event(int event, |
2361 | void *my_data, | |
2362 | void *event_data) | |
2363 | { | |
2364 | struct mlx5_eswitch *esw = my_data; | |
ac004b83 | 2365 | struct mlx5_devcom *devcom = esw->dev->priv.devcom; |
8463daf1 | 2366 | struct mlx5_eswitch *peer_esw = event_data; |
ac004b83 RD |
2367 | int err; |
2368 | ||
2369 | switch (event) { | |
2370 | case ESW_OFFLOADS_DEVCOM_PAIR: | |
a5641cb5 JL |
2371 | if (mlx5_eswitch_vport_match_metadata_enabled(esw) != |
2372 | mlx5_eswitch_vport_match_metadata_enabled(peer_esw)) | |
2373 | break; | |
2374 | ||
8463daf1 | 2375 | err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true); |
ac004b83 RD |
2376 | if (err) |
2377 | goto err_out; | |
8463daf1 MG |
2378 | err = mlx5_esw_offloads_pair(esw, peer_esw); |
2379 | if (err) | |
2380 | goto err_peer; | |
ac004b83 RD |
2381 | |
2382 | err = mlx5_esw_offloads_pair(peer_esw, esw); | |
2383 | if (err) | |
2384 | goto err_pair; | |
2385 | ||
2386 | mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true); | |
2387 | break; | |
2388 | ||
2389 | case ESW_OFFLOADS_DEVCOM_UNPAIR: | |
2390 | if (!mlx5_devcom_is_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS)) | |
2391 | break; | |
2392 | ||
2393 | mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false); | |
2394 | mlx5_esw_offloads_unpair(peer_esw); | |
2395 | mlx5_esw_offloads_unpair(esw); | |
8463daf1 | 2396 | mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false); |
ac004b83 RD |
2397 | break; |
2398 | } | |
2399 | ||
2400 | return 0; | |
2401 | ||
2402 | err_pair: | |
2403 | mlx5_esw_offloads_unpair(esw); | |
8463daf1 MG |
2404 | err_peer: |
2405 | mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false); | |
ac004b83 RD |
2406 | err_out: |
2407 | mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d", | |
2408 | event, err); | |
2409 | return err; | |
2410 | } | |
2411 | ||
2412 | static void esw_offloads_devcom_init(struct mlx5_eswitch *esw) | |
2413 | { | |
2414 | struct mlx5_devcom *devcom = esw->dev->priv.devcom; | |
2415 | ||
04de7dda RD |
2416 | INIT_LIST_HEAD(&esw->offloads.peer_flows); |
2417 | mutex_init(&esw->offloads.peer_mutex); | |
2418 | ||
ac004b83 RD |
2419 | if (!MLX5_CAP_ESW(esw->dev, merged_eswitch)) |
2420 | return; | |
2421 | ||
2422 | mlx5_devcom_register_component(devcom, | |
2423 | MLX5_DEVCOM_ESW_OFFLOADS, | |
2424 | mlx5_esw_offloads_devcom_event, | |
2425 | esw); | |
2426 | ||
2427 | mlx5_devcom_send_event(devcom, | |
2428 | MLX5_DEVCOM_ESW_OFFLOADS, | |
2429 | ESW_OFFLOADS_DEVCOM_PAIR, esw); | |
2430 | } | |
2431 | ||
2432 | static void esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw) | |
2433 | { | |
2434 | struct mlx5_devcom *devcom = esw->dev->priv.devcom; | |
2435 | ||
2436 | if (!MLX5_CAP_ESW(esw->dev, merged_eswitch)) | |
2437 | return; | |
2438 | ||
2439 | mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS, | |
2440 | ESW_OFFLOADS_DEVCOM_UNPAIR, esw); | |
2441 | ||
2442 | mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
2443 | } | |
2444 | ||
7bf481d7 | 2445 | bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw) |
92ab1eb3 JL |
2446 | { |
2447 | if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl)) | |
2448 | return false; | |
2449 | ||
2450 | if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) & | |
2451 | MLX5_FDB_TO_VPORT_REG_C_0)) | |
2452 | return false; | |
2453 | ||
2454 | if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source)) | |
2455 | return false; | |
2456 | ||
2457 | if (mlx5_core_is_ecpf_esw_manager(esw->dev) || | |
2458 | mlx5_ecpf_vport_exists(esw->dev)) | |
2459 | return false; | |
2460 | ||
2461 | return true; | |
2462 | } | |
2463 | ||
133dcfc5 VP |
2464 | u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw) |
2465 | { | |
7cd7becd | 2466 | u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1; |
2467 | u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 1; | |
2468 | u32 pf_num; | |
133dcfc5 VP |
2469 | int id; |
2470 | ||
7cd7becd | 2471 | /* Only 4 bits of pf_num */ |
2472 | pf_num = PCI_FUNC(esw->dev->pdev->devfn); | |
2473 | if (pf_num > max_pf_num) | |
2474 | return 0; | |
133dcfc5 | 2475 | |
7cd7becd | 2476 | /* Metadata is 4 bits of PFNUM and 12 bits of unique id */ |
2477 | /* Use only non-zero vport_id (1-4095) for all PF's */ | |
2478 | id = ida_alloc_range(&esw->offloads.vport_metadata_ida, 1, vport_end_ida, GFP_KERNEL); | |
2479 | if (id < 0) | |
2480 | return 0; | |
2481 | id = (pf_num << ESW_VPORT_BITS) | id; | |
2482 | return id; | |
133dcfc5 VP |
2483 | } |
2484 | ||
2485 | void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata) | |
2486 | { | |
7cd7becd | 2487 | u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1; |
2488 | ||
2489 | /* Metadata contains only 12 bits of actual ida id */ | |
2490 | ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask); | |
133dcfc5 VP |
2491 | } |
2492 | ||
2493 | static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw, | |
2494 | struct mlx5_vport *vport) | |
2495 | { | |
133dcfc5 VP |
2496 | vport->default_metadata = mlx5_esw_match_metadata_alloc(esw); |
2497 | vport->metadata = vport->default_metadata; | |
2498 | return vport->metadata ? 0 : -ENOSPC; | |
2499 | } | |
2500 | ||
2501 | static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw, | |
2502 | struct mlx5_vport *vport) | |
2503 | { | |
406493a5 | 2504 | if (!vport->default_metadata) |
133dcfc5 VP |
2505 | return; |
2506 | ||
2507 | WARN_ON(vport->metadata != vport->default_metadata); | |
2508 | mlx5_esw_match_metadata_free(esw, vport->default_metadata); | |
2509 | } | |
2510 | ||
fc99c3d6 VP |
2511 | static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw) |
2512 | { | |
2513 | struct mlx5_vport *vport; | |
47dd7e60 | 2514 | unsigned long i; |
fc99c3d6 VP |
2515 | |
2516 | if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) | |
2517 | return; | |
2518 | ||
47dd7e60 | 2519 | mlx5_esw_for_each_vport(esw, i, vport) |
fc99c3d6 VP |
2520 | esw_offloads_vport_metadata_cleanup(esw, vport); |
2521 | } | |
2522 | ||
2523 | static int esw_offloads_metadata_init(struct mlx5_eswitch *esw) | |
2524 | { | |
2525 | struct mlx5_vport *vport; | |
47dd7e60 | 2526 | unsigned long i; |
fc99c3d6 | 2527 | int err; |
fc99c3d6 VP |
2528 | |
2529 | if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) | |
2530 | return 0; | |
2531 | ||
47dd7e60 | 2532 | mlx5_esw_for_each_vport(esw, i, vport) { |
fc99c3d6 VP |
2533 | err = esw_offloads_vport_metadata_setup(esw, vport); |
2534 | if (err) | |
2535 | goto metadata_err; | |
2536 | } | |
2537 | ||
2538 | return 0; | |
2539 | ||
2540 | metadata_err: | |
2541 | esw_offloads_metadata_uninit(esw); | |
2542 | return err; | |
2543 | } | |
2544 | ||
7bf481d7 PP |
2545 | int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable) |
2546 | { | |
2547 | int err = 0; | |
2548 | ||
2549 | down_write(&esw->mode_lock); | |
2550 | if (esw->mode != MLX5_ESWITCH_NONE) { | |
2551 | err = -EBUSY; | |
2552 | goto done; | |
2553 | } | |
2554 | if (!mlx5_esw_vport_match_metadata_supported(esw)) { | |
2555 | err = -EOPNOTSUPP; | |
2556 | goto done; | |
2557 | } | |
2558 | if (enable) | |
2559 | esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA; | |
2560 | else | |
2561 | esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA; | |
2562 | done: | |
2563 | up_write(&esw->mode_lock); | |
2564 | return err; | |
2565 | } | |
2566 | ||
748da30b | 2567 | int |
89a0f1fb PP |
2568 | esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, |
2569 | struct mlx5_vport *vport) | |
7445cfb1 | 2570 | { |
7445cfb1 JL |
2571 | int err; |
2572 | ||
07bab950 | 2573 | err = esw_acl_ingress_ofld_setup(esw, vport); |
89a0f1fb | 2574 | if (err) |
fc99c3d6 | 2575 | return err; |
7445cfb1 | 2576 | |
2c40db2f PP |
2577 | err = esw_acl_egress_ofld_setup(esw, vport); |
2578 | if (err) | |
2579 | goto egress_err; | |
07bab950 VP |
2580 | |
2581 | return 0; | |
2582 | ||
2583 | egress_err: | |
2584 | esw_acl_ingress_ofld_cleanup(esw, vport); | |
89a0f1fb PP |
2585 | return err; |
2586 | } | |
18486737 | 2587 | |
748da30b | 2588 | void |
89a0f1fb PP |
2589 | esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, |
2590 | struct mlx5_vport *vport) | |
2591 | { | |
ea651a86 | 2592 | esw_acl_egress_ofld_cleanup(vport); |
07bab950 | 2593 | esw_acl_ingress_ofld_cleanup(esw, vport); |
89a0f1fb | 2594 | } |
7445cfb1 | 2595 | |
748da30b | 2596 | static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw) |
7445cfb1 JL |
2597 | { |
2598 | struct mlx5_vport *vport; | |
18486737 | 2599 | |
748da30b | 2600 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK); |
7bef147a SM |
2601 | if (IS_ERR(vport)) |
2602 | return PTR_ERR(vport); | |
2603 | ||
4e9a9ef7 | 2604 | return esw_vport_create_offloads_acl_tables(esw, vport); |
18486737 EB |
2605 | } |
2606 | ||
748da30b | 2607 | static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw) |
18486737 | 2608 | { |
786ef904 | 2609 | struct mlx5_vport *vport; |
7445cfb1 | 2610 | |
748da30b | 2611 | vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK); |
7bef147a SM |
2612 | if (IS_ERR(vport)) |
2613 | return; | |
2614 | ||
748da30b | 2615 | esw_vport_destroy_offloads_acl_tables(esw, vport); |
18486737 EB |
2616 | } |
2617 | ||
062f4bf4 | 2618 | static int esw_offloads_steering_init(struct mlx5_eswitch *esw) |
6ed1803a | 2619 | { |
34ca6535 | 2620 | struct mlx5_esw_indir_table *indir; |
6ed1803a MB |
2621 | int err; |
2622 | ||
5c1d260e | 2623 | memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb)); |
f8d1edda PP |
2624 | mutex_init(&esw->fdb_table.offloads.vports.lock); |
2625 | hash_init(esw->fdb_table.offloads.vports.table); | |
7dc84de9 | 2626 | atomic64_set(&esw->user_count, 0); |
e52c2802 | 2627 | |
34ca6535 VB |
2628 | indir = mlx5_esw_indir_table_init(); |
2629 | if (IS_ERR(indir)) { | |
2630 | err = PTR_ERR(indir); | |
2631 | goto create_indir_err; | |
2632 | } | |
2633 | esw->fdb_table.offloads.indir = indir; | |
2634 | ||
748da30b | 2635 | err = esw_create_uplink_offloads_acl_tables(esw); |
7445cfb1 | 2636 | if (err) |
f8d1edda | 2637 | goto create_acl_err; |
18486737 | 2638 | |
8d6bd3c3 | 2639 | err = esw_create_offloads_table(esw); |
c930a3ad | 2640 | if (err) |
11b717d6 | 2641 | goto create_offloads_err; |
c930a3ad | 2642 | |
11b717d6 | 2643 | err = esw_create_restore_table(esw); |
c930a3ad | 2644 | if (err) |
11b717d6 PB |
2645 | goto create_restore_err; |
2646 | ||
0da3c12d | 2647 | err = esw_create_offloads_fdb_tables(esw); |
11b717d6 PB |
2648 | if (err) |
2649 | goto create_fdb_err; | |
c930a3ad | 2650 | |
8d6bd3c3 | 2651 | err = esw_create_vport_rx_group(esw); |
c930a3ad OG |
2652 | if (err) |
2653 | goto create_fg_err; | |
2654 | ||
2655 | return 0; | |
2656 | ||
2657 | create_fg_err: | |
1967ce6e | 2658 | esw_destroy_offloads_fdb_tables(esw); |
7445cfb1 | 2659 | create_fdb_err: |
11b717d6 PB |
2660 | esw_destroy_restore_table(esw); |
2661 | create_restore_err: | |
2662 | esw_destroy_offloads_table(esw); | |
2663 | create_offloads_err: | |
748da30b | 2664 | esw_destroy_uplink_offloads_acl_tables(esw); |
f8d1edda | 2665 | create_acl_err: |
34ca6535 VB |
2666 | mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir); |
2667 | create_indir_err: | |
f8d1edda | 2668 | mutex_destroy(&esw->fdb_table.offloads.vports.lock); |
c930a3ad OG |
2669 | return err; |
2670 | } | |
2671 | ||
eca8cc38 BW |
2672 | static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw) |
2673 | { | |
2674 | esw_destroy_vport_rx_group(esw); | |
eca8cc38 | 2675 | esw_destroy_offloads_fdb_tables(esw); |
11b717d6 PB |
2676 | esw_destroy_restore_table(esw); |
2677 | esw_destroy_offloads_table(esw); | |
748da30b | 2678 | esw_destroy_uplink_offloads_acl_tables(esw); |
34ca6535 | 2679 | mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir); |
f8d1edda | 2680 | mutex_destroy(&esw->fdb_table.offloads.vports.lock); |
eca8cc38 BW |
2681 | } |
2682 | ||
7e736f9a PP |
2683 | static void |
2684 | esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out) | |
a3888f33 | 2685 | { |
5ccf2770 | 2686 | bool host_pf_disabled; |
7e736f9a | 2687 | u16 new_num_vfs; |
a3888f33 | 2688 | |
7e736f9a PP |
2689 | new_num_vfs = MLX5_GET(query_esw_functions_out, out, |
2690 | host_params_context.host_num_of_vfs); | |
5ccf2770 BW |
2691 | host_pf_disabled = MLX5_GET(query_esw_functions_out, out, |
2692 | host_params_context.host_pf_disabled); | |
a3888f33 | 2693 | |
7e736f9a PP |
2694 | if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled) |
2695 | return; | |
a3888f33 BW |
2696 | |
2697 | /* Number of VFs can only change from "0 to x" or "x to 0". */ | |
cd56f929 | 2698 | if (esw->esw_funcs.num_vfs > 0) { |
23bb50cf | 2699 | mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs); |
a3888f33 | 2700 | } else { |
7e736f9a | 2701 | int err; |
a3888f33 | 2702 | |
23bb50cf BW |
2703 | err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs, |
2704 | MLX5_VPORT_UC_ADDR_CHANGE); | |
a3888f33 | 2705 | if (err) |
7e736f9a | 2706 | return; |
a3888f33 | 2707 | } |
7e736f9a | 2708 | esw->esw_funcs.num_vfs = new_num_vfs; |
a3888f33 BW |
2709 | } |
2710 | ||
7e736f9a | 2711 | static void esw_functions_changed_event_handler(struct work_struct *work) |
ac35dcd6 | 2712 | { |
7e736f9a PP |
2713 | struct mlx5_host_work *host_work; |
2714 | struct mlx5_eswitch *esw; | |
dd28087c | 2715 | const u32 *out; |
ac35dcd6 | 2716 | |
7e736f9a PP |
2717 | host_work = container_of(work, struct mlx5_host_work, work); |
2718 | esw = host_work->esw; | |
a3888f33 | 2719 | |
dd28087c PP |
2720 | out = mlx5_esw_query_functions(esw->dev); |
2721 | if (IS_ERR(out)) | |
7e736f9a | 2722 | goto out; |
a3888f33 | 2723 | |
7e736f9a | 2724 | esw_vfs_changed_event_handler(esw, out); |
dd28087c | 2725 | kvfree(out); |
a3888f33 | 2726 | out: |
ac35dcd6 VP |
2727 | kfree(host_work); |
2728 | } | |
2729 | ||
16fff98a | 2730 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data) |
a3888f33 | 2731 | { |
cd56f929 | 2732 | struct mlx5_esw_functions *esw_funcs; |
a3888f33 | 2733 | struct mlx5_host_work *host_work; |
a3888f33 BW |
2734 | struct mlx5_eswitch *esw; |
2735 | ||
2736 | host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC); | |
2737 | if (!host_work) | |
2738 | return NOTIFY_DONE; | |
2739 | ||
cd56f929 VP |
2740 | esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb); |
2741 | esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs); | |
a3888f33 BW |
2742 | |
2743 | host_work->esw = esw; | |
2744 | ||
062f4bf4 | 2745 | INIT_WORK(&host_work->work, esw_functions_changed_event_handler); |
a3888f33 BW |
2746 | queue_work(esw->work_queue, &host_work->work); |
2747 | ||
2748 | return NOTIFY_OK; | |
2749 | } | |
2750 | ||
a53cf949 PP |
2751 | static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw) |
2752 | { | |
2753 | const u32 *query_host_out; | |
2754 | ||
2755 | if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) | |
2756 | return 0; | |
2757 | ||
2758 | query_host_out = mlx5_esw_query_functions(esw->dev); | |
2759 | if (IS_ERR(query_host_out)) | |
2760 | return PTR_ERR(query_host_out); | |
2761 | ||
2762 | /* Mark non local controller with non zero controller number. */ | |
2763 | esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out, | |
2764 | host_params_context.host_number); | |
2765 | kvfree(query_host_out); | |
2766 | return 0; | |
2767 | } | |
2768 | ||
f1b9acd3 PP |
2769 | bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller) |
2770 | { | |
2771 | /* Local controller is always valid */ | |
2772 | if (controller == 0) | |
2773 | return true; | |
2774 | ||
2775 | if (!mlx5_core_is_ecpf_esw_manager(esw->dev)) | |
2776 | return false; | |
2777 | ||
2778 | /* External host number starts with zero in device */ | |
2779 | return (controller == esw->offloads.host_number + 1); | |
2780 | } | |
2781 | ||
5896b972 | 2782 | int esw_offloads_enable(struct mlx5_eswitch *esw) |
eca8cc38 | 2783 | { |
c9355682 | 2784 | struct mapping_ctx *reg_c0_obj_pool; |
3b83b6c2 | 2785 | struct mlx5_vport *vport; |
47dd7e60 PP |
2786 | unsigned long i; |
2787 | int err; | |
eca8cc38 | 2788 | |
9a64144d MG |
2789 | if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat) && |
2790 | MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, decap)) | |
2791 | esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_BASIC; | |
2792 | else | |
2793 | esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE; | |
2794 | ||
2bb72e7e | 2795 | mutex_init(&esw->offloads.termtbl_mutex); |
8463daf1 | 2796 | mlx5_rdma_enable_roce(esw->dev); |
eca8cc38 | 2797 | |
a53cf949 PP |
2798 | err = mlx5_esw_host_number_init(esw); |
2799 | if (err) | |
cd1ef966 | 2800 | goto err_metadata; |
a53cf949 | 2801 | |
fc99c3d6 VP |
2802 | err = esw_offloads_metadata_init(esw); |
2803 | if (err) | |
2804 | goto err_metadata; | |
2805 | ||
332bd3a5 PP |
2806 | err = esw_set_passing_vport_metadata(esw, true); |
2807 | if (err) | |
2808 | goto err_vport_metadata; | |
c1286050 | 2809 | |
c9355682 CM |
2810 | reg_c0_obj_pool = mapping_create(sizeof(struct mlx5_mapped_obj), |
2811 | ESW_REG_C0_USER_DATA_METADATA_MASK, | |
2812 | true); | |
2813 | if (IS_ERR(reg_c0_obj_pool)) { | |
2814 | err = PTR_ERR(reg_c0_obj_pool); | |
2815 | goto err_pool; | |
2816 | } | |
2817 | esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool; | |
2818 | ||
7983a675 PB |
2819 | err = esw_offloads_steering_init(esw); |
2820 | if (err) | |
2821 | goto err_steering_init; | |
2822 | ||
3b83b6c2 DL |
2823 | /* Representor will control the vport link state */ |
2824 | mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs) | |
2825 | vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN; | |
2826 | ||
c2d7712c BW |
2827 | /* Uplink vport rep must load first. */ |
2828 | err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK); | |
925a6acc | 2829 | if (err) |
c2d7712c | 2830 | goto err_uplink; |
c1286050 | 2831 | |
c2d7712c | 2832 | err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE); |
eca8cc38 | 2833 | if (err) |
c2d7712c | 2834 | goto err_vports; |
eca8cc38 BW |
2835 | |
2836 | esw_offloads_devcom_init(esw); | |
a3888f33 | 2837 | |
eca8cc38 BW |
2838 | return 0; |
2839 | ||
925a6acc | 2840 | err_vports: |
c2d7712c BW |
2841 | esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK); |
2842 | err_uplink: | |
7983a675 | 2843 | esw_offloads_steering_cleanup(esw); |
79949985 | 2844 | err_steering_init: |
c9355682 CM |
2845 | mapping_destroy(reg_c0_obj_pool); |
2846 | err_pool: | |
79949985 | 2847 | esw_set_passing_vport_metadata(esw, false); |
7983a675 | 2848 | err_vport_metadata: |
fc99c3d6 VP |
2849 | esw_offloads_metadata_uninit(esw); |
2850 | err_metadata: | |
8463daf1 | 2851 | mlx5_rdma_disable_roce(esw->dev); |
2bb72e7e | 2852 | mutex_destroy(&esw->offloads.termtbl_mutex); |
eca8cc38 BW |
2853 | return err; |
2854 | } | |
2855 | ||
db7ff19e EB |
2856 | static int esw_offloads_stop(struct mlx5_eswitch *esw, |
2857 | struct netlink_ext_ack *extack) | |
c930a3ad | 2858 | { |
062f4bf4 | 2859 | int err, err1; |
c930a3ad | 2860 | |
8e0aa4bc PP |
2861 | mlx5_eswitch_disable_locked(esw, false); |
2862 | err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_LEGACY, | |
2863 | MLX5_ESWITCH_IGNORE_NUM_VFS); | |
6c419ba8 | 2864 | if (err) { |
8c98ee77 | 2865 | NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy"); |
8e0aa4bc PP |
2866 | err1 = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_OFFLOADS, |
2867 | MLX5_ESWITCH_IGNORE_NUM_VFS); | |
8c98ee77 EB |
2868 | if (err1) { |
2869 | NL_SET_ERR_MSG_MOD(extack, | |
2870 | "Failed setting eswitch back to offloads"); | |
2871 | } | |
6c419ba8 | 2872 | } |
c930a3ad OG |
2873 | |
2874 | return err; | |
2875 | } | |
2876 | ||
5896b972 | 2877 | void esw_offloads_disable(struct mlx5_eswitch *esw) |
c930a3ad | 2878 | { |
ac004b83 | 2879 | esw_offloads_devcom_cleanup(esw); |
5896b972 | 2880 | mlx5_eswitch_disable_pf_vf_vports(esw); |
c2d7712c | 2881 | esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK); |
332bd3a5 | 2882 | esw_set_passing_vport_metadata(esw, false); |
eca8cc38 | 2883 | esw_offloads_steering_cleanup(esw); |
c9355682 | 2884 | mapping_destroy(esw->offloads.reg_c0_obj_pool); |
fc99c3d6 | 2885 | esw_offloads_metadata_uninit(esw); |
8463daf1 | 2886 | mlx5_rdma_disable_roce(esw->dev); |
2bb72e7e | 2887 | mutex_destroy(&esw->offloads.termtbl_mutex); |
9a64144d | 2888 | esw->offloads.encap = DEVLINK_ESWITCH_ENCAP_MODE_NONE; |
c930a3ad OG |
2889 | } |
2890 | ||
ef78618b | 2891 | static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode) |
c930a3ad OG |
2892 | { |
2893 | switch (mode) { | |
2894 | case DEVLINK_ESWITCH_MODE_LEGACY: | |
f6455de0 | 2895 | *mlx5_mode = MLX5_ESWITCH_LEGACY; |
c930a3ad OG |
2896 | break; |
2897 | case DEVLINK_ESWITCH_MODE_SWITCHDEV: | |
f6455de0 | 2898 | *mlx5_mode = MLX5_ESWITCH_OFFLOADS; |
c930a3ad OG |
2899 | break; |
2900 | default: | |
2901 | return -EINVAL; | |
2902 | } | |
2903 | ||
2904 | return 0; | |
2905 | } | |
2906 | ||
ef78618b OG |
2907 | static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode) |
2908 | { | |
2909 | switch (mlx5_mode) { | |
f6455de0 | 2910 | case MLX5_ESWITCH_LEGACY: |
ef78618b OG |
2911 | *mode = DEVLINK_ESWITCH_MODE_LEGACY; |
2912 | break; | |
f6455de0 | 2913 | case MLX5_ESWITCH_OFFLOADS: |
ef78618b OG |
2914 | *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV; |
2915 | break; | |
2916 | default: | |
2917 | return -EINVAL; | |
2918 | } | |
2919 | ||
2920 | return 0; | |
2921 | } | |
2922 | ||
bffaa916 RD |
2923 | static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode) |
2924 | { | |
2925 | switch (mode) { | |
2926 | case DEVLINK_ESWITCH_INLINE_MODE_NONE: | |
2927 | *mlx5_mode = MLX5_INLINE_MODE_NONE; | |
2928 | break; | |
2929 | case DEVLINK_ESWITCH_INLINE_MODE_LINK: | |
2930 | *mlx5_mode = MLX5_INLINE_MODE_L2; | |
2931 | break; | |
2932 | case DEVLINK_ESWITCH_INLINE_MODE_NETWORK: | |
2933 | *mlx5_mode = MLX5_INLINE_MODE_IP; | |
2934 | break; | |
2935 | case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT: | |
2936 | *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP; | |
2937 | break; | |
2938 | default: | |
2939 | return -EINVAL; | |
2940 | } | |
2941 | ||
2942 | return 0; | |
2943 | } | |
2944 | ||
2945 | static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode) | |
2946 | { | |
2947 | switch (mlx5_mode) { | |
2948 | case MLX5_INLINE_MODE_NONE: | |
2949 | *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE; | |
2950 | break; | |
2951 | case MLX5_INLINE_MODE_L2: | |
2952 | *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK; | |
2953 | break; | |
2954 | case MLX5_INLINE_MODE_IP: | |
2955 | *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK; | |
2956 | break; | |
2957 | case MLX5_INLINE_MODE_TCP_UDP: | |
2958 | *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT; | |
2959 | break; | |
2960 | default: | |
2961 | return -EINVAL; | |
2962 | } | |
2963 | ||
2964 | return 0; | |
2965 | } | |
2966 | ||
ae24432c PP |
2967 | static int eswitch_devlink_esw_mode_check(const struct mlx5_eswitch *esw) |
2968 | { | |
2969 | /* devlink commands in NONE eswitch mode are currently supported only | |
2970 | * on ECPF. | |
2971 | */ | |
2972 | return (esw->mode == MLX5_ESWITCH_NONE && | |
2973 | !mlx5_core_is_ecpf_esw_manager(esw->dev)) ? -EOPNOTSUPP : 0; | |
2974 | } | |
2975 | ||
db7ff19e EB |
2976 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
2977 | struct netlink_ext_ack *extack) | |
9d1cef19 | 2978 | { |
9d1cef19 | 2979 | u16 cur_mlx5_mode, mlx5_mode = 0; |
bd939753 | 2980 | struct mlx5_eswitch *esw; |
ea2128fd | 2981 | int err = 0; |
9d1cef19 | 2982 | |
bd939753 PP |
2983 | esw = mlx5_devlink_eswitch_get(devlink); |
2984 | if (IS_ERR(esw)) | |
2985 | return PTR_ERR(esw); | |
9d1cef19 | 2986 | |
ef78618b | 2987 | if (esw_mode_from_devlink(mode, &mlx5_mode)) |
c930a3ad OG |
2988 | return -EINVAL; |
2989 | ||
7dc84de9 RD |
2990 | err = mlx5_esw_try_lock(esw); |
2991 | if (err < 0) { | |
2992 | NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy"); | |
2993 | return err; | |
2994 | } | |
2995 | cur_mlx5_mode = err; | |
2996 | err = 0; | |
2997 | ||
c930a3ad | 2998 | if (cur_mlx5_mode == mlx5_mode) |
8e0aa4bc | 2999 | goto unlock; |
c930a3ad OG |
3000 | |
3001 | if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) | |
8e0aa4bc | 3002 | err = esw_offloads_start(esw, extack); |
c930a3ad | 3003 | else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) |
8e0aa4bc | 3004 | err = esw_offloads_stop(esw, extack); |
c930a3ad | 3005 | else |
8e0aa4bc PP |
3006 | err = -EINVAL; |
3007 | ||
3008 | unlock: | |
7dc84de9 | 3009 | mlx5_esw_unlock(esw); |
8e0aa4bc | 3010 | return err; |
feae9087 OG |
3011 | } |
3012 | ||
3013 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode) | |
3014 | { | |
bd939753 | 3015 | struct mlx5_eswitch *esw; |
9d1cef19 | 3016 | int err; |
c930a3ad | 3017 | |
bd939753 PP |
3018 | esw = mlx5_devlink_eswitch_get(devlink); |
3019 | if (IS_ERR(esw)) | |
3020 | return PTR_ERR(esw); | |
c930a3ad | 3021 | |
c55479d0 | 3022 | down_write(&esw->mode_lock); |
bd939753 | 3023 | err = eswitch_devlink_esw_mode_check(esw); |
ae24432c | 3024 | if (err) |
8e0aa4bc | 3025 | goto unlock; |
ae24432c | 3026 | |
8e0aa4bc PP |
3027 | err = esw_mode_to_devlink(esw->mode, mode); |
3028 | unlock: | |
c55479d0 | 3029 | up_write(&esw->mode_lock); |
8e0aa4bc | 3030 | return err; |
feae9087 | 3031 | } |
127ea380 | 3032 | |
47dd7e60 PP |
3033 | static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode, |
3034 | struct netlink_ext_ack *extack) | |
3035 | { | |
3036 | struct mlx5_core_dev *dev = esw->dev; | |
3037 | struct mlx5_vport *vport; | |
3038 | u16 err_vport_num = 0; | |
3039 | unsigned long i; | |
3040 | int err = 0; | |
3041 | ||
3042 | mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) { | |
3043 | err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode); | |
3044 | if (err) { | |
3045 | err_vport_num = vport->vport; | |
3046 | NL_SET_ERR_MSG_MOD(extack, | |
3047 | "Failed to set min inline on vport"); | |
3048 | goto revert_inline_mode; | |
3049 | } | |
3050 | } | |
3051 | return 0; | |
3052 | ||
3053 | revert_inline_mode: | |
3054 | mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) { | |
3055 | if (vport->vport == err_vport_num) | |
3056 | break; | |
3057 | mlx5_modify_nic_vport_min_inline(dev, | |
3058 | vport->vport, | |
3059 | esw->offloads.inline_mode); | |
3060 | } | |
3061 | return err; | |
3062 | } | |
3063 | ||
db7ff19e EB |
3064 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
3065 | struct netlink_ext_ack *extack) | |
bffaa916 RD |
3066 | { |
3067 | struct mlx5_core_dev *dev = devlink_priv(devlink); | |
bd939753 | 3068 | struct mlx5_eswitch *esw; |
bffaa916 | 3069 | u8 mlx5_mode; |
47dd7e60 | 3070 | int err; |
bffaa916 | 3071 | |
bd939753 PP |
3072 | esw = mlx5_devlink_eswitch_get(devlink); |
3073 | if (IS_ERR(esw)) | |
3074 | return PTR_ERR(esw); | |
bffaa916 | 3075 | |
c55479d0 | 3076 | down_write(&esw->mode_lock); |
ae24432c PP |
3077 | err = eswitch_devlink_esw_mode_check(esw); |
3078 | if (err) | |
8e0aa4bc | 3079 | goto out; |
ae24432c | 3080 | |
c415f704 OG |
3081 | switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) { |
3082 | case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: | |
3083 | if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) | |
8e0aa4bc | 3084 | goto out; |
c8b838d1 | 3085 | fallthrough; |
c415f704 | 3086 | case MLX5_CAP_INLINE_MODE_L2: |
8c98ee77 | 3087 | NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set"); |
8e0aa4bc PP |
3088 | err = -EOPNOTSUPP; |
3089 | goto out; | |
c415f704 OG |
3090 | case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: |
3091 | break; | |
3092 | } | |
bffaa916 | 3093 | |
525e84be | 3094 | if (atomic64_read(&esw->offloads.num_flows) > 0) { |
8c98ee77 EB |
3095 | NL_SET_ERR_MSG_MOD(extack, |
3096 | "Can't set inline mode when flows are configured"); | |
8e0aa4bc PP |
3097 | err = -EOPNOTSUPP; |
3098 | goto out; | |
375f51e2 RD |
3099 | } |
3100 | ||
bffaa916 RD |
3101 | err = esw_inline_mode_from_devlink(mode, &mlx5_mode); |
3102 | if (err) | |
3103 | goto out; | |
3104 | ||
47dd7e60 PP |
3105 | err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack); |
3106 | if (err) | |
3107 | goto out; | |
bffaa916 RD |
3108 | |
3109 | esw->offloads.inline_mode = mlx5_mode; | |
c55479d0 | 3110 | up_write(&esw->mode_lock); |
bffaa916 RD |
3111 | return 0; |
3112 | ||
bffaa916 | 3113 | out: |
c55479d0 | 3114 | up_write(&esw->mode_lock); |
bffaa916 RD |
3115 | return err; |
3116 | } | |
3117 | ||
3118 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode) | |
3119 | { | |
bd939753 | 3120 | struct mlx5_eswitch *esw; |
9d1cef19 | 3121 | int err; |
bffaa916 | 3122 | |
bd939753 PP |
3123 | esw = mlx5_devlink_eswitch_get(devlink); |
3124 | if (IS_ERR(esw)) | |
3125 | return PTR_ERR(esw); | |
bffaa916 | 3126 | |
c55479d0 | 3127 | down_write(&esw->mode_lock); |
ae24432c PP |
3128 | err = eswitch_devlink_esw_mode_check(esw); |
3129 | if (err) | |
8e0aa4bc | 3130 | goto unlock; |
ae24432c | 3131 | |
8e0aa4bc PP |
3132 | err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode); |
3133 | unlock: | |
c55479d0 | 3134 | up_write(&esw->mode_lock); |
8e0aa4bc | 3135 | return err; |
bffaa916 RD |
3136 | } |
3137 | ||
98fdbea5 LR |
3138 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
3139 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 3140 | struct netlink_ext_ack *extack) |
7768d197 RD |
3141 | { |
3142 | struct mlx5_core_dev *dev = devlink_priv(devlink); | |
bd939753 | 3143 | struct mlx5_eswitch *esw; |
7768d197 RD |
3144 | int err; |
3145 | ||
bd939753 PP |
3146 | esw = mlx5_devlink_eswitch_get(devlink); |
3147 | if (IS_ERR(esw)) | |
3148 | return PTR_ERR(esw); | |
7768d197 | 3149 | |
c55479d0 | 3150 | down_write(&esw->mode_lock); |
ae24432c PP |
3151 | err = eswitch_devlink_esw_mode_check(esw); |
3152 | if (err) | |
8e0aa4bc | 3153 | goto unlock; |
ae24432c | 3154 | |
7768d197 | 3155 | if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE && |
60786f09 | 3156 | (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) || |
8e0aa4bc PP |
3157 | !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) { |
3158 | err = -EOPNOTSUPP; | |
3159 | goto unlock; | |
3160 | } | |
7768d197 | 3161 | |
8e0aa4bc PP |
3162 | if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) { |
3163 | err = -EOPNOTSUPP; | |
3164 | goto unlock; | |
3165 | } | |
7768d197 | 3166 | |
f6455de0 | 3167 | if (esw->mode == MLX5_ESWITCH_LEGACY) { |
7768d197 | 3168 | esw->offloads.encap = encap; |
8e0aa4bc | 3169 | goto unlock; |
7768d197 RD |
3170 | } |
3171 | ||
3172 | if (esw->offloads.encap == encap) | |
8e0aa4bc | 3173 | goto unlock; |
7768d197 | 3174 | |
525e84be | 3175 | if (atomic64_read(&esw->offloads.num_flows) > 0) { |
8c98ee77 EB |
3176 | NL_SET_ERR_MSG_MOD(extack, |
3177 | "Can't set encapsulation when flows are configured"); | |
8e0aa4bc PP |
3178 | err = -EOPNOTSUPP; |
3179 | goto unlock; | |
7768d197 RD |
3180 | } |
3181 | ||
e52c2802 | 3182 | esw_destroy_offloads_fdb_tables(esw); |
7768d197 RD |
3183 | |
3184 | esw->offloads.encap = encap; | |
e52c2802 | 3185 | |
0da3c12d | 3186 | err = esw_create_offloads_fdb_tables(esw); |
e52c2802 | 3187 | |
7768d197 | 3188 | if (err) { |
8c98ee77 EB |
3189 | NL_SET_ERR_MSG_MOD(extack, |
3190 | "Failed re-creating fast FDB table"); | |
7768d197 | 3191 | esw->offloads.encap = !encap; |
0da3c12d | 3192 | (void)esw_create_offloads_fdb_tables(esw); |
7768d197 | 3193 | } |
e52c2802 | 3194 | |
8e0aa4bc | 3195 | unlock: |
c55479d0 | 3196 | up_write(&esw->mode_lock); |
7768d197 RD |
3197 | return err; |
3198 | } | |
3199 | ||
98fdbea5 LR |
3200 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
3201 | enum devlink_eswitch_encap_mode *encap) | |
7768d197 | 3202 | { |
bd939753 | 3203 | struct mlx5_eswitch *esw; |
9d1cef19 | 3204 | int err; |
7768d197 | 3205 | |
bd939753 PP |
3206 | esw = mlx5_devlink_eswitch_get(devlink); |
3207 | if (IS_ERR(esw)) | |
3208 | return PTR_ERR(esw); | |
3209 | ||
7768d197 | 3210 | |
c55479d0 | 3211 | down_write(&esw->mode_lock); |
ae24432c PP |
3212 | err = eswitch_devlink_esw_mode_check(esw); |
3213 | if (err) | |
8e0aa4bc | 3214 | goto unlock; |
ae24432c | 3215 | |
7768d197 | 3216 | *encap = esw->offloads.encap; |
8e0aa4bc | 3217 | unlock: |
c55479d0 | 3218 | up_write(&esw->mode_lock); |
7768d197 RD |
3219 | return 0; |
3220 | } | |
3221 | ||
c2d7712c BW |
3222 | static bool |
3223 | mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num) | |
3224 | { | |
3225 | /* Currently, only ECPF based device has representor for host PF. */ | |
3226 | if (vport_num == MLX5_VPORT_PF && | |
3227 | !mlx5_core_is_ecpf_esw_manager(esw->dev)) | |
3228 | return false; | |
3229 | ||
3230 | if (vport_num == MLX5_VPORT_ECPF && | |
3231 | !mlx5_ecpf_vport_exists(esw->dev)) | |
3232 | return false; | |
3233 | ||
3234 | return true; | |
3235 | } | |
3236 | ||
f8e8fa02 | 3237 | void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw, |
8693115a | 3238 | const struct mlx5_eswitch_rep_ops *ops, |
f8e8fa02 | 3239 | u8 rep_type) |
127ea380 | 3240 | { |
8693115a | 3241 | struct mlx5_eswitch_rep_data *rep_data; |
f8e8fa02 | 3242 | struct mlx5_eswitch_rep *rep; |
47dd7e60 | 3243 | unsigned long i; |
9deb2241 | 3244 | |
8693115a | 3245 | esw->offloads.rep_ops[rep_type] = ops; |
47dd7e60 PP |
3246 | mlx5_esw_for_each_rep(esw, i, rep) { |
3247 | if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) { | |
59c904c8 | 3248 | rep->esw = esw; |
c2d7712c BW |
3249 | rep_data = &rep->rep_data[rep_type]; |
3250 | atomic_set(&rep_data->state, REP_REGISTERED); | |
3251 | } | |
f8e8fa02 | 3252 | } |
127ea380 | 3253 | } |
f8e8fa02 | 3254 | EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps); |
127ea380 | 3255 | |
f8e8fa02 | 3256 | void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type) |
127ea380 | 3257 | { |
cb67b832 | 3258 | struct mlx5_eswitch_rep *rep; |
47dd7e60 | 3259 | unsigned long i; |
cb67b832 | 3260 | |
f6455de0 | 3261 | if (esw->mode == MLX5_ESWITCH_OFFLOADS) |
062f4bf4 | 3262 | __unload_reps_all_vport(esw, rep_type); |
127ea380 | 3263 | |
47dd7e60 | 3264 | mlx5_esw_for_each_rep(esw, i, rep) |
8693115a | 3265 | atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED); |
127ea380 | 3266 | } |
f8e8fa02 | 3267 | EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps); |
726293f1 | 3268 | |
a4b97ab4 | 3269 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type) |
726293f1 | 3270 | { |
726293f1 HHZ |
3271 | struct mlx5_eswitch_rep *rep; |
3272 | ||
879c8f84 | 3273 | rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK); |
8693115a | 3274 | return rep->rep_data[rep_type].priv; |
726293f1 | 3275 | } |
22215908 MB |
3276 | |
3277 | void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw, | |
02f3afd9 | 3278 | u16 vport, |
22215908 MB |
3279 | u8 rep_type) |
3280 | { | |
22215908 MB |
3281 | struct mlx5_eswitch_rep *rep; |
3282 | ||
879c8f84 | 3283 | rep = mlx5_eswitch_get_rep(esw, vport); |
22215908 | 3284 | |
8693115a PP |
3285 | if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED && |
3286 | esw->offloads.rep_ops[rep_type]->get_proto_dev) | |
3287 | return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep); | |
22215908 MB |
3288 | return NULL; |
3289 | } | |
57cbd893 | 3290 | EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev); |
22215908 MB |
3291 | |
3292 | void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type) | |
3293 | { | |
879c8f84 | 3294 | return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type); |
22215908 | 3295 | } |
57cbd893 MB |
3296 | EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev); |
3297 | ||
3298 | struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw, | |
02f3afd9 | 3299 | u16 vport) |
57cbd893 | 3300 | { |
879c8f84 | 3301 | return mlx5_eswitch_get_rep(esw, vport); |
57cbd893 MB |
3302 | } |
3303 | EXPORT_SYMBOL(mlx5_eswitch_vport_rep); | |
91d6291c | 3304 | |
5b7cb745 PB |
3305 | bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw) |
3306 | { | |
3307 | return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED); | |
3308 | } | |
3309 | EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled); | |
3310 | ||
7445cfb1 JL |
3311 | bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw) |
3312 | { | |
3313 | return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA); | |
3314 | } | |
3315 | EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled); | |
3316 | ||
0f0d3827 | 3317 | u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, |
7445cfb1 JL |
3318 | u16 vport_num) |
3319 | { | |
133dcfc5 | 3320 | struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num); |
0f0d3827 | 3321 | |
133dcfc5 VP |
3322 | if (WARN_ON_ONCE(IS_ERR(vport))) |
3323 | return 0; | |
0f0d3827 | 3324 | |
133dcfc5 | 3325 | return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS); |
7445cfb1 JL |
3326 | } |
3327 | EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match); | |
d970812b PP |
3328 | |
3329 | int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port, | |
f1b9acd3 | 3330 | u16 vport_num, u32 controller, u32 sfnum) |
d970812b PP |
3331 | { |
3332 | int err; | |
3333 | ||
3334 | err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE); | |
3335 | if (err) | |
3336 | return err; | |
3337 | ||
f1b9acd3 | 3338 | err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum); |
d970812b PP |
3339 | if (err) |
3340 | goto devlink_err; | |
3341 | ||
3342 | err = mlx5_esw_offloads_rep_load(esw, vport_num); | |
3343 | if (err) | |
3344 | goto rep_err; | |
3345 | return 0; | |
3346 | ||
3347 | rep_err: | |
3348 | mlx5_esw_devlink_sf_port_unregister(esw, vport_num); | |
3349 | devlink_err: | |
3350 | mlx5_esw_vport_disable(esw, vport_num); | |
3351 | return err; | |
3352 | } | |
3353 | ||
3354 | void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num) | |
3355 | { | |
3356 | mlx5_esw_offloads_rep_unload(esw, vport_num); | |
3357 | mlx5_esw_devlink_sf_port_unregister(esw, vport_num); | |
3358 | mlx5_esw_vport_disable(esw, vport_num); | |
3359 | } | |
84ae9c1f VB |
3360 | |
3361 | static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id) | |
3362 | { | |
3363 | int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); | |
3364 | void *query_ctx; | |
3365 | void *hca_caps; | |
3366 | int err; | |
3367 | ||
3368 | *vhca_id = 0; | |
3369 | if (mlx5_esw_is_manager_vport(esw, vport_num) || | |
3370 | !MLX5_CAP_GEN(esw->dev, vhca_resource_manager)) | |
3371 | return -EPERM; | |
3372 | ||
3373 | query_ctx = kzalloc(query_out_sz, GFP_KERNEL); | |
3374 | if (!query_ctx) | |
3375 | return -ENOMEM; | |
3376 | ||
3377 | err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx); | |
3378 | if (err) | |
3379 | goto out_free; | |
3380 | ||
3381 | hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability); | |
3382 | *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id); | |
3383 | ||
3384 | out_free: | |
3385 | kfree(query_ctx); | |
3386 | return err; | |
3387 | } | |
3388 | ||
3389 | int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num) | |
3390 | { | |
3391 | u16 *old_entry, *vhca_map_entry, vhca_id; | |
3392 | int err; | |
3393 | ||
3394 | err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id); | |
3395 | if (err) { | |
3396 | esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n", | |
3397 | vport_num, err); | |
3398 | return err; | |
3399 | } | |
3400 | ||
3401 | vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL); | |
3402 | if (!vhca_map_entry) | |
3403 | return -ENOMEM; | |
3404 | ||
3405 | *vhca_map_entry = vport_num; | |
3406 | old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL); | |
3407 | if (xa_is_err(old_entry)) { | |
3408 | kfree(vhca_map_entry); | |
3409 | return xa_err(old_entry); | |
3410 | } | |
3411 | kfree(old_entry); | |
3412 | return 0; | |
3413 | } | |
3414 | ||
3415 | void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num) | |
3416 | { | |
3417 | u16 *vhca_map_entry, vhca_id; | |
3418 | int err; | |
3419 | ||
3420 | err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id); | |
3421 | if (err) | |
3422 | esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n", | |
3423 | vport_num, err); | |
3424 | ||
3425 | vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id); | |
3426 | kfree(vhca_map_entry); | |
3427 | } | |
3428 | ||
3429 | int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num) | |
3430 | { | |
3431 | u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id); | |
3432 | ||
3433 | if (!res) | |
3434 | return -ENOENT; | |
3435 | ||
3436 | *vport_num = *res; | |
3437 | return 0; | |
3438 | } | |
10742efc VB |
3439 | |
3440 | u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw, | |
3441 | u16 vport_num) | |
3442 | { | |
3443 | struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num); | |
3444 | ||
3445 | if (WARN_ON_ONCE(IS_ERR(vport))) | |
3446 | return 0; | |
3447 | ||
3448 | return vport->metadata; | |
3449 | } | |
3450 | EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set); |