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net/mlx5: Allow mlx5_esw_offloads_devlink_port_register() to register SFs
[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
34ca6535 41#include "esw/indir_table.h"
ea651a86 42#include "esw/acl/ofld.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
ae430332 48#include "lib/fs_chains.h"
c620b772 49#include "en_tc.h"
c9355682 50#include "en/mapping.h"
c85a6b8f 51#include "devlink.h"
94db3317 52#include "lag/lag.h"
6fda078d 53#include "en/tc/post_meter.h"
69697b6e 54
47dd7e60
PP		 55#define mlx5_esw_for_each_rep(esw, i, rep) \
56 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
57
cd7e4186
BW		 58/* There are two match-all miss flows, one for unicast dst mac and
59 * one for multicast.
60 */
61#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 62#define UPLINK_REP_INDEX 0
63
c796bb7c
CM		 64#define MLX5_ESW_VPORT_TBL_SIZE 128
65#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
66
8ea7bcf6
JL		 67#define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
68
fd745f4c 69static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
c796bb7c
CM		 70 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
71 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
72 .flags = 0,
73};
74
879c8f84
BW		 75static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
76 u16 vport_num)
77{
47dd7e60 78 return xa_load(&esw->offloads.vport_reps, vport_num);
879c8f84
BW		 79}
80
6f7bbad1
JL		 81static void
82mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
83 struct mlx5_flow_spec *spec,
84 struct mlx5_esw_flow_attr *attr)
85{
166f431e
AL		 86 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) || !attr || !attr->in_rep)
87 return;
88
89 if (attr->int_port) {
90 spec->flow_context.flow_source = mlx5e_tc_int_port_get_flow_source(attr->int_port);
91
92 return;
93 }
94
95 spec->flow_context.flow_source = (attr->in_rep->vport == MLX5_VPORT_UPLINK) ?
96 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
97 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 98}
b7826076 99
f94d6389
CM		 100/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
101 * are not needed as well in the following process. So clear them all for simplicity.
102 */
103void
104mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
105{
106 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
107 void *misc2;
108
109 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
110 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
111
112 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
113 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
114
115 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
116 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
117 }
118}
119
c01cfd0f
JL		 120static void
121mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
122 struct mlx5_flow_spec *spec,
a508728a 123 struct mlx5_flow_attr *attr,
b055ecf5
MB		 124 struct mlx5_eswitch *src_esw,
125 u16 vport)
c01cfd0f 126{
166f431e
AL		 127 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
128 u32 metadata;
c01cfd0f
JL		 129 void *misc2;
130 void *misc;
131
132 /* Use metadata matching because vport is not represented by single
133 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
134 */
135 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
a508728a
VB		 136 if (mlx5_esw_indir_table_decap_vport(attr))
137 vport = mlx5_esw_indir_table_decap_vport(attr);
166f431e 138
e0bf81bf 139 if (!attr->chain && esw_attr && esw_attr->int_port)
166f431e
AL		 140 metadata =
141 mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
142 else
143 metadata =
144 mlx5_eswitch_get_vport_metadata_for_match(src_esw, vport);
145
c01cfd0f 146 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
166f431e 147 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata);
c01cfd0f
JL		 148
149 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 150 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
151 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 152
153 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 154 } else {
155 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 156 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 157
158 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
159 MLX5_SET(fte_match_set_misc, misc,
160 source_eswitch_owner_vhca_id,
b055ecf5 161 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 162
163 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
164 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
165 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
166 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
167 source_eswitch_owner_vhca_id);
168
169 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
170 }
c01cfd0f
JL		 171}
172
a508728a
VB		 173static int
174esw_setup_decap_indir(struct mlx5_eswitch *esw,
521933cd 175 struct mlx5_flow_attr *attr)
a508728a
VB		 176{
177 struct mlx5_flow_table *ft;
178
e5d4e1da 179 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
a508728a
VB		 180 return -EOPNOTSUPP;
181
521933cd 182 ft = mlx5_esw_indir_table_get(esw, attr,
a508728a
VB		 183 mlx5_esw_indir_table_decap_vport(attr), true);
184 return PTR_ERR_OR_ZERO(ft);
185}
186
9e51c0a6 187static void
a508728a
VB		 188esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
189 struct mlx5_flow_attr *attr)
190{
191 if (mlx5_esw_indir_table_decap_vport(attr))
521933cd 192 mlx5_esw_indir_table_put(esw,
a508728a
VB		 193 mlx5_esw_indir_table_decap_vport(attr),
194 true);
195}
196
6fda078d
OS		 197static int
198esw_setup_mtu_dest(struct mlx5_flow_destination *dest,
199 struct mlx5e_meter_attr *meter,
200 int i)
201{
202 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_RANGE;
203 dest[i].range.field = MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN;
204 dest[i].range.min = 0;
205 dest[i].range.max = meter->params.mtu;
206 dest[i].range.hit_ft = mlx5e_post_meter_get_mtu_true_ft(meter->post_meter);
207 dest[i].range.miss_ft = mlx5e_post_meter_get_mtu_false_ft(meter->post_meter);
208
209 return 0;
210}
211
f94d6389
CM		 212static int
213esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
214 struct mlx5_flow_act *flow_act,
eeed226e 215 u32 sampler_id,
f94d6389
CM		 216 int i)
217{
218 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
219 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
eeed226e 220 dest[i].sampler_id = sampler_id;
f94d6389
CM		 221
222 return 0;
223}
224
a508728a 225static int
9e51c0a6
VB		 226esw_setup_ft_dest(struct mlx5_flow_destination *dest,
227 struct mlx5_flow_act *flow_act,
a508728a 228 struct mlx5_eswitch *esw,
9e51c0a6
VB		 229 struct mlx5_flow_attr *attr,
230 int i)
231{
232 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
233 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
234 dest[i].ft = attr->dest_ft;
a508728a
VB		 235
236 if (mlx5_esw_indir_table_decap_vport(attr))
521933cd 237 return esw_setup_decap_indir(esw, attr);
a508728a 238 return 0;
9e51c0a6
VB		 239}
240
241static void
c0063a43
VB		 242esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
243 struct mlx5_fs_chains *chains, int i)
9e51c0a6 244{
2a2c84fa
RD		 245 if (mlx5_chains_ignore_flow_level_supported(chains))
246 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
9e51c0a6
VB		 247 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
248 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
249}
250
c0063a43
VB		 251static void
252esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
253 struct mlx5_eswitch *esw, int i)
254{
255 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))
256 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
257 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
dcf19b9c 258 dest[i].ft = mlx5_eswitch_get_slow_fdb(esw);
c0063a43
VB		 259}
260
9e51c0a6
VB		 261static int
262esw_setup_chain_dest(struct mlx5_flow_destination *dest,
263 struct mlx5_flow_act *flow_act,
264 struct mlx5_fs_chains *chains,
265 u32 chain, u32 prio, u32 level,
266 int i)
267{
268 struct mlx5_flow_table *ft;
269
270 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
271 ft = mlx5_chains_get_table(chains, chain, prio, level);
272 if (IS_ERR(ft))
273 return PTR_ERR(ft);
274
275 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
276 dest[i].ft = ft;
277 return 0;
278}
279
10742efc
VB		 280static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
281 int from, int to)
282{
283 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
284 struct mlx5_fs_chains *chains = esw_chains(esw);
285 int i;
286
287 for (i = from; i < to; i++)
288 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
289 mlx5_chains_put_table(chains, 0, 1, 0);
a508728a
VB		 290 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
291 esw_attr->dests[i].mdev))
521933cd 292 mlx5_esw_indir_table_put(esw, esw_attr->dests[i].rep->vport,
a508728a 293 false);
10742efc
VB		 294}
295
296static bool
297esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
298{
299 int i;
300
301 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
302 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
303 return true;
304 return false;
305}
306
307static int
308esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
309 struct mlx5_flow_act *flow_act,
310 struct mlx5_eswitch *esw,
311 struct mlx5_fs_chains *chains,
312 struct mlx5_flow_attr *attr,
313 int *i)
314{
315 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
de31854e 316 int err;
10742efc 317
e5d4e1da 318 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
10742efc
VB		 319 return -EOPNOTSUPP;
320
de31854e
DC		 321 /* flow steering cannot handle more than one dest with the same ft
322 * in a single flow
323 */
324 if (esw_attr->out_count - esw_attr->split_count > 1)
325 return -EOPNOTSUPP;
326
327 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
328 if (err)
329 return err;
27484f71 330
de31854e
DC		 331 if (esw_attr->dests[esw_attr->split_count].pkt_reformat) {
332 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
333 flow_act->pkt_reformat = esw_attr->dests[esw_attr->split_count].pkt_reformat;
10742efc 334 }
de31854e 335 (*i)++;
10742efc 336
de31854e 337 return 0;
10742efc
VB		 338}
339
340static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
341 struct mlx5_flow_attr *attr)
342{
343 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
344
345 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
346}
347
a508728a
VB		 348static bool
349esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
350{
351 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
e219440d 352 bool result = false;
a508728a
VB		 353 int i;
354
e219440d
MD		 355 /* Indirect table is supported only for flows with in_port uplink
356 * and the destination is vport on the same eswitch as the uplink,
357 * return false in case at least one of destinations doesn't meet
358 * this criteria.
359 */
360 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
27484f71
AL		 361 if (esw_attr->dests[i].rep &&
362 mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
e219440d
MD		 363 esw_attr->dests[i].mdev)) {
364 result = true;
365 } else {
366 result = false;
367 break;
368 }
369 }
370 return result;
a508728a
VB		 371}
372
373static int
374esw_setup_indir_table(struct mlx5_flow_destination *dest,
375 struct mlx5_flow_act *flow_act,
376 struct mlx5_eswitch *esw,
377 struct mlx5_flow_attr *attr,
a508728a
VB		 378 int *i)
379{
380 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
381 int j, err;
382
e5d4e1da 383 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
a508728a
VB		 384 return -EOPNOTSUPP;
385
386 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
d602be22 387 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
a508728a
VB		 388 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
389
521933cd 390 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,
a508728a
VB		 391 esw_attr->dests[j].rep->vport, false);
392 if (IS_ERR(dest[*i].ft)) {
393 err = PTR_ERR(dest[*i].ft);
394 goto err_indir_tbl_get;
395 }
396 }
397
398 if (mlx5_esw_indir_table_decap_vport(attr)) {
521933cd 399 err = esw_setup_decap_indir(esw, attr);
a508728a
VB		 400 if (err)
401 goto err_indir_tbl_get;
402 }
403
404 return 0;
405
406err_indir_tbl_get:
407 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
408 return err;
409}
410
411static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
412{
413 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
414
415 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
416 esw_cleanup_decap_indir(esw, attr);
417}
418
9e51c0a6
VB		 419static void
420esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
421{
422 mlx5_chains_put_table(chains, chain, prio, level);
423}
424
d1569537
JL		 425static bool esw_same_vhca_id(struct mlx5_core_dev *mdev1, struct mlx5_core_dev *mdev2)
426{
427 return MLX5_CAP_GEN(mdev1, vhca_id) == MLX5_CAP_GEN(mdev2, vhca_id);
428}
429
430static bool esw_setup_uplink_fwd_ipsec_needed(struct mlx5_eswitch *esw,
431 struct mlx5_esw_flow_attr *esw_attr,
432 int attr_idx)
433{
434 if (esw->offloads.ft_ipsec_tx_pol &&
435 esw_attr->dests[attr_idx].rep &&
436 esw_attr->dests[attr_idx].rep->vport == MLX5_VPORT_UPLINK &&
437 /* To be aligned with software, encryption is needed only for tunnel device */
438 (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) &&
439 esw_attr->dests[attr_idx].rep != esw_attr->in_rep &&
440 esw_same_vhca_id(esw_attr->dests[attr_idx].mdev, esw->dev))
441 return true;
442
443 return false;
444}
445
446static bool esw_flow_dests_fwd_ipsec_check(struct mlx5_eswitch *esw,
447 struct mlx5_esw_flow_attr *esw_attr)
448{
449 int i;
450
451 if (!esw->offloads.ft_ipsec_tx_pol)
452 return true;
453
454 for (i = 0; i < esw_attr->split_count; i++)
455 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i))
456 return false;
457
458 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
459 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, i) &&
460 (esw_attr->out_count - esw_attr->split_count > 1))
461 return false;
462
463 return true;
464}
465
9e51c0a6 466static void
d1569537
JL		 467esw_setup_dest_fwd_vport(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
468 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
469 int attr_idx, int dest_idx, bool pkt_reformat)
9e51c0a6
VB		 470{
471 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
472 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
c6719725
MD		 473 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
474 dest[dest_idx].vport.vhca_id =
475 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
9e51c0a6 476 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
942fca7e 477 if (dest[dest_idx].vport.num == MLX5_VPORT_UPLINK &&
8ce81fc0 478 mlx5_lag_is_mpesw(esw->dev))
94db3317 479 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_UPLINK;
c6719725 480 }
6d942e40 481 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
9e51c0a6
VB		 482 if (pkt_reformat) {
483 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
484 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
485 }
486 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
487 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
488 }
489}
490
d1569537
JL		 491static void
492esw_setup_dest_fwd_ipsec(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
493 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
494 int attr_idx, int dest_idx, bool pkt_reformat)
495{
496 dest[dest_idx].ft = esw->offloads.ft_ipsec_tx_pol;
497 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
498 if (pkt_reformat &&
499 esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
500 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
501 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
502 }
503}
504
505static void
506esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
507 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
508 int attr_idx, int dest_idx, bool pkt_reformat)
509{
510 if (esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
511 esw_setup_dest_fwd_ipsec(dest, flow_act, esw, esw_attr,
512 attr_idx, dest_idx, pkt_reformat);
513 else
514 esw_setup_dest_fwd_vport(dest, flow_act, esw, esw_attr,
515 attr_idx, dest_idx, pkt_reformat);
516}
517
9e51c0a6
VB		 518static int
519esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
520 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
521 int i)
522{
523 int j;
524
525 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
526 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
527 return i;
528}
529
e929e3da
MD		 530static bool
531esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
532{
533 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
534 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
535 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
536}
537
e0e22d59
JL		 538static bool
539esw_dests_to_vf_pf_vports(struct mlx5_flow_destination *dests, int max_dest)
540{
541 bool vf_dest = false, pf_dest = false;
542 int i;
543
544 for (i = 0; i < max_dest; i++) {
545 if (dests[i].type != MLX5_FLOW_DESTINATION_TYPE_VPORT)
546 continue;
547
548 if (dests[i].vport.num == MLX5_VPORT_UPLINK)
549 pf_dest = true;
550 else
551 vf_dest = true;
552
553 if (vf_dest && pf_dest)
554 return true;
555 }
556
557 return false;
558}
559
9e51c0a6
VB		 560static int
561esw_setup_dests(struct mlx5_flow_destination *dest,
562 struct mlx5_flow_act *flow_act,
563 struct mlx5_eswitch *esw,
564 struct mlx5_flow_attr *attr,
10742efc 565 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 566 int *i)
567{
568 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
569 struct mlx5_fs_chains *chains = esw_chains(esw);
570 int err = 0;
571
10742efc 572 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
e929e3da 573 esw_src_port_rewrite_supported(esw))
e5d4e1da 574 attr->flags |= MLX5_ATTR_FLAG_SRC_REWRITE;
10742efc 575
42760d95 576 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {
c0063a43
VB		 577 esw_setup_slow_path_dest(dest, flow_act, esw, *i);
578 (*i)++;
42760d95
RD		 579 goto out;
580 }
581
582 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
583 esw_setup_sampler_dest(dest, flow_act, attr->sample_attr.sampler_id, *i);
584 (*i)++;
c0063a43
VB		 585 } else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {
586 esw_setup_accept_dest(dest, flow_act, chains, *i);
9e51c0a6 587 (*i)++;
6fda078d
OS		 588 } else if (attr->flags & MLX5_ATTR_FLAG_MTU) {
589 err = esw_setup_mtu_dest(dest, &attr->meter_attr, *i);
590 (*i)++;
a508728a 591 } else if (esw_is_indir_table(esw, attr)) {
d602be22 592 err = esw_setup_indir_table(dest, flow_act, esw, attr, i);
10742efc
VB		 593 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
594 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
9e51c0a6
VB		 595 } else {
596 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
8c9cc1eb
RD		 597
598 if (attr->dest_ft) {
521933cd 599 err = esw_setup_ft_dest(dest, flow_act, esw, attr, *i);
8c9cc1eb
RD		 600 (*i)++;
601 } else if (attr->dest_chain) {
602 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
603 1, 0, *i);
604 (*i)++;
605 }
9e51c0a6
VB		 606 }
607
42760d95 608out:
9e51c0a6
VB		 609 return err;
610}
611
612static void
613esw_cleanup_dests(struct mlx5_eswitch *esw,
614 struct mlx5_flow_attr *attr)
615{
10742efc 616 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
9e51c0a6
VB		 617 struct mlx5_fs_chains *chains = esw_chains(esw);
618
a508728a
VB		 619 if (attr->dest_ft) {
620 esw_cleanup_decap_indir(esw, attr);
e5d4e1da 621 } else if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
10742efc
VB		 622 if (attr->dest_chain)
623 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
a508728a
VB		 624 else if (esw_is_indir_table(esw, attr))
625 esw_cleanup_indir_table(esw, attr);
10742efc
VB		 626 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
627 esw_cleanup_chain_src_port_rewrite(esw, attr);
628 }
9e51c0a6
VB		 629}
630
9153da46
JL		 631static void
632esw_setup_meter(struct mlx5_flow_attr *attr, struct mlx5_flow_act *flow_act)
633{
634 struct mlx5e_flow_meter_handle *meter;
635
636 meter = attr->meter_attr.meter;
637 flow_act->exe_aso.type = attr->exe_aso_type;
638 flow_act->exe_aso.object_id = meter->obj_id;
639 flow_act->exe_aso.flow_meter.meter_idx = meter->idx;
640 flow_act->exe_aso.flow_meter.init_color = MLX5_FLOW_METER_COLOR_GREEN;
641 /* use metadata reg 5 for packet color */
642 flow_act->exe_aso.return_reg_id = 5;
643}
644
74491de9 645struct mlx5_flow_handle *
3d80d1a2
OG		 646mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
647 struct mlx5_flow_spec *spec,
c620b772 648 struct mlx5_flow_attr *attr)
3d80d1a2 649{
42f7ad67 650 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 651 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 652 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 653 bool split = !!(esw_attr->split_count);
654 struct mlx5_vport_tbl_attr fwd_attr;
40888162 655 struct mlx5_flow_destination *dest;
74491de9 656 struct mlx5_flow_handle *rule;
e52c2802 657 struct mlx5_flow_table *fdb;
9e51c0a6 658 int i = 0;
3d80d1a2 659
f6455de0 660 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 661 return ERR_PTR(-EOPNOTSUPP);
662
633ad4b2
RD		 663 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
664 return ERR_PTR(-EOPNOTSUPP);
665
d1569537
JL		 666 if (!esw_flow_dests_fwd_ipsec_check(esw, esw_attr))
667 return ERR_PTR(-EOPNOTSUPP);
668
40888162
MD		 669 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
670 if (!dest)
671 return ERR_PTR(-ENOMEM);
672
6acfbf38 673 flow_act.action = attr->action;
633ad4b2
RD		 674
675 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 676 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
677 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
678 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 679 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 680 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
681 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
682 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 683 }
6acfbf38 684 }
776b12b6 685
10742efc
VB		 686 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
687
66958ed9 688 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
9e51c0a6
VB		 689 int err;
690
10742efc 691 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
9e51c0a6
VB		 692 if (err) {
693 rule = ERR_PTR(err);
694 goto err_create_goto_table;
56e858df 695 }
e0e22d59
JL		 696
697 /* Header rewrite with combined wire+loopback in FDB is not allowed */
698 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) &&
699 esw_dests_to_vf_pf_vports(dest, i)) {
700 esw_warn(esw->dev,
701 "FDB: Header rewrite with forwarding to both PF and VF is not allowed\n");
702 rule = ERR_PTR(-EINVAL);
703 goto err_esw_get;
704 }
e37a79e5 705 }
14e6b038 706
c620b772
AL		 707 if (esw_attr->decap_pkt_reformat)
708 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 709
66958ed9 710 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 711 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 712 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 713 i++;
3d80d1a2
OG		 714 }
715
93b3586e 716 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 717 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 718 if (attr->inner_match_level != MLX5_MATCH_NONE)
719 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 720
aa24670e 721 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 722 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 723
9153da46
JL		 724 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
725 attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)
726 esw_setup_meter(attr, &flow_act);
727
2741f223 728 if (split) {
c620b772
AL		 729 fwd_attr.chain = attr->chain;
730 fwd_attr.prio = attr->prio;
731 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 732 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772 733
0a9e2307 734 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
96e32687 735 } else {
d18296ff 736 if (attr->chain || attr->prio)
ae430332
AL		 737 fdb = mlx5_chains_get_table(chains, attr->chain,
738 attr->prio, 0);
d18296ff 739 else
c620b772 740 fdb = attr->ft;
6fb0701a 741
e5d4e1da 742 if (!(attr->flags & MLX5_ATTR_FLAG_NO_IN_PORT))
a508728a 743 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 744 esw_attr->in_mdev->priv.eswitch,
745 esw_attr->in_rep->vport);
96e32687 746 }
e52c2802
PB		 747 if (IS_ERR(fdb)) {
748 rule = ERR_CAST(fdb);
749 goto err_esw_get;
750 }
751
5a5624d1
OS		 752 if (!i) {
753 kfree(dest);
754 dest = NULL;
755 }
756
84be2fda 757 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 758 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 759 &flow_act, dest, i);
84be2fda 760 else
10caabda 761 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 762 if (IS_ERR(rule))
e52c2802 763 goto err_add_rule;
375f51e2 764 else
525e84be 765 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 766
40888162 767 kfree(dest);
e52c2802
PB		 768 return rule;
769
770err_add_rule:
96e32687 771 if (split)
0a9e2307 772 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 773 else if (attr->chain || attr->prio)
ae430332 774 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 775err_esw_get:
9e51c0a6 776 esw_cleanup_dests(esw, attr);
e52c2802 777err_create_goto_table:
40888162 778 kfree(dest);
aa0cbbae 779 return rule;
3d80d1a2
OG		 780}
781
e4ad91f2
CM		 782struct mlx5_flow_handle *
783mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
784 struct mlx5_flow_spec *spec,
c620b772 785 struct mlx5_flow_attr *attr)
e4ad91f2 786{
42f7ad67 787 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 788 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 789 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 790 struct mlx5_vport_tbl_attr fwd_attr;
40888162 791 struct mlx5_flow_destination *dest;
e52c2802
PB		 792 struct mlx5_flow_table *fast_fdb;
793 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 794 struct mlx5_flow_handle *rule;
10742efc 795 int i, err = 0;
e4ad91f2 796
40888162
MD		 797 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
798 if (!dest)
799 return ERR_PTR(-ENOMEM);
800
ae430332 801 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 802 if (IS_ERR(fast_fdb)) {
803 rule = ERR_CAST(fast_fdb);
804 goto err_get_fast;
805 }
806
c620b772
AL		 807 fwd_attr.chain = attr->chain;
808 fwd_attr.prio = attr->prio;
809 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 810 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 811 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
e52c2802
PB		 812 if (IS_ERR(fwd_fdb)) {
813 rule = ERR_CAST(fwd_fdb);
814 goto err_get_fwd;
815 }
816
e4ad91f2 817 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
10742efc 818 for (i = 0; i < esw_attr->split_count; i++) {
1313d78a
MD		 819 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
820 /* Source port rewrite (forward to ovs internal port or statck device) isn't
821 * supported in the rule of split action.
822 */
823 err = -EOPNOTSUPP;
10742efc
VB		 824 else
825 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
826
827 if (err) {
828 rule = ERR_PTR(err);
829 goto err_chain_src_rewrite;
830 }
831 }
e4ad91f2 832 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 833 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 834 i++;
835
a508728a 836 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 837 esw_attr->in_mdev->priv.eswitch,
838 esw_attr->in_rep->vport);
e4ad91f2 839
93b3586e 840 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 841 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 842
278d51f2 843 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 844 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 845
10742efc
VB		 846 if (IS_ERR(rule)) {
847 i = esw_attr->split_count;
848 goto err_chain_src_rewrite;
849 }
e4ad91f2 850
525e84be 851 atomic64_inc(&esw->offloads.num_flows);
e52c2802 852
40888162 853 kfree(dest);
e52c2802 854 return rule;
10742efc 855err_chain_src_rewrite:
0a9e2307 856 mlx5_esw_vporttbl_put(esw, &fwd_attr);
e52c2802 857err_get_fwd:
ae430332 858 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 859err_get_fast:
40888162 860 kfree(dest);
e4ad91f2
CM		 861 return rule;
862}
863
e52c2802
PB		 864static void
865__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
866 struct mlx5_flow_handle *rule,
c620b772 867 struct mlx5_flow_attr *attr,
e52c2802
PB		 868 bool fwd_rule)
869{
c620b772 870 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 871 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 872 bool split = (esw_attr->split_count > 0);
873 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 874 int i;
e52c2802
PB		 875
876 mlx5_del_flow_rules(rule);
10caabda 877
e5d4e1da 878 if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
d8a2034f
EC		 879 /* unref the term table */
880 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 881 if (esw_attr->dests[i].termtbl)
882 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 883 }
10caabda
OS		 884 }
885
525e84be 886 atomic64_dec(&esw->offloads.num_flows);
e52c2802 887
c620b772
AL		 888 if (fwd_rule || split) {
889 fwd_attr.chain = attr->chain;
890 fwd_attr.prio = attr->prio;
891 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 892 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772
AL		 893 }
894
e52c2802 895 if (fwd_rule) {
0a9e2307 896 mlx5_esw_vporttbl_put(esw, &fwd_attr);
ae430332 897 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 898 } else {
96e32687 899 if (split)
0a9e2307 900 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 901 else if (attr->chain || attr->prio)
ae430332 902 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
9e51c0a6 903 esw_cleanup_dests(esw, attr);
e52c2802
PB		 904 }
905}
906
d85cdccb
OG		 907void
908mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
909 struct mlx5_flow_handle *rule,
c620b772 910 struct mlx5_flow_attr *attr)
d85cdccb 911{
e52c2802 912 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 913}
914
48265006
OG		 915void
916mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
917 struct mlx5_flow_handle *rule,
c620b772 918 struct mlx5_flow_attr *attr)
48265006 919{
e52c2802 920 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 921}
922
f7a68945 923struct mlx5_flow_handle *
3a46f4fb 924mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
979bf468 925 struct mlx5_eswitch *from_esw,
3a46f4fb 926 struct mlx5_eswitch_rep *rep,
02f3afd9 927 u32 sqn)
ab22be9b 928{
66958ed9 929 struct mlx5_flow_act flow_act = {0};
4c5009c5 930 struct mlx5_flow_destination dest = {};
74491de9 931 struct mlx5_flow_handle *flow_rule;
c5bb1730 932 struct mlx5_flow_spec *spec;
ab22be9b 933 void *misc;
29bcb6e4 934 u16 vport;
ab22be9b 935
1b9a07ee 936 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 937 if (!spec) {
ab22be9b
OG		 938 flow_rule = ERR_PTR(-ENOMEM);
939 goto out;
940 }
941
c5bb1730 942 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 943 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
ab22be9b 944
c5bb1730 945 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b 946 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
ab22be9b 947
c5bb1730 948 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
29bcb6e4
RD		 949
950 /* source vport is the esw manager */
951 vport = from_esw->manager_vport;
952
953 if (mlx5_eswitch_vport_match_metadata_enabled(on_esw)) {
954 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
955 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
956 mlx5_eswitch_get_vport_metadata_for_match(from_esw, vport));
957
958 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
959 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
960 mlx5_eswitch_get_vport_metadata_mask());
961
962 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
963 } else {
964 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
965 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
966
967 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
968 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
969 MLX5_CAP_GEN(from_esw->dev, vhca_id));
970
971 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
972 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
973
974 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
975 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
976 source_eswitch_owner_vhca_id);
977
978 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
979 }
980
ab22be9b 981 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
3a46f4fb
MB		 982 dest.vport.num = rep->vport;
983 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
984 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
66958ed9 985 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 986
c6c2bf5d
JL		 987 if (rep->vport == MLX5_VPORT_UPLINK && on_esw->offloads.ft_ipsec_tx_pol) {
988 dest.ft = on_esw->offloads.ft_ipsec_tx_pol;
989 flow_act.flags = FLOW_ACT_IGNORE_FLOW_LEVEL;
990 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
991 } else {
992 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
993 dest.vport.num = rep->vport;
994 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
995 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
996 }
997
1bf8b0da
RD		 998 if (MLX5_CAP_ESW_FLOWTABLE(on_esw->dev, flow_source) &&
999 rep->vport == MLX5_VPORT_UPLINK)
d0444254
AL		 1000 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
1001
dcf19b9c 1002 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(on_esw),
39ac237c 1003 spec, &flow_act, &dest, 1);
ab22be9b 1004 if (IS_ERR(flow_rule))
3a46f4fb
MB		 1005 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
1006 PTR_ERR(flow_rule));
ab22be9b 1007out:
c5bb1730 1008 kvfree(spec);
ab22be9b
OG		 1009 return flow_rule;
1010}
57cbd893 1011EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 1012
159fe639
MB		 1013void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
1014{
1015 mlx5_del_flow_rules(rule);
1016}
1017
430e2d5e 1018void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule)
8e404fef 1019{
430e2d5e
RD		 1020 if (rule)
1021 mlx5_del_flow_rules(rule);
f019679e
CM		 1022}
1023
430e2d5e
RD		 1024struct mlx5_flow_handle *
1025mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num)
8e404fef 1026{
8e404fef
VB		 1027 struct mlx5_flow_destination dest = {};
1028 struct mlx5_flow_act flow_act = {0};
1029 struct mlx5_flow_handle *flow_rule;
8e404fef 1030 struct mlx5_flow_spec *spec;
8e404fef
VB		 1031
1032 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
430e2d5e
RD		 1033 if (!spec)
1034 return ERR_PTR(-ENOMEM);
8e404fef
VB		 1035
1036 MLX5_SET(fte_match_param, spec->match_criteria,
1037 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
1038 MLX5_SET(fte_match_param, spec->match_criteria,
1039 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1040 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
1041 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
1042
1043 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1044 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
1045 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1046
430e2d5e
RD		 1047 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
1048 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
1049 dest.vport.num = vport_num;
8e404fef 1050
dcf19b9c 1051 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
430e2d5e
RD		 1052 spec, &flow_act, &dest, 1);
1053 if (IS_ERR(flow_rule))
1054 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule vport %d, err %ld\n",
1055 vport_num, PTR_ERR(flow_rule));
8e404fef 1056
8e404fef 1057 kvfree(spec);
430e2d5e 1058 return flow_rule;
8e404fef
VB		 1059}
1060
5b7cb745
PB		 1061static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
1062{
1063 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
1064 MLX5_FDB_TO_VPORT_REG_C_1;
1065}
1066
332bd3a5 1067static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 1068{
1069 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 1070 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
1071 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 1072 u8 curr, wanted;
c1286050
JL		 1073 int err;
1074
5b7cb745
PB		 1075 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
1076 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 1077 return 0;
c1286050 1078
e08a6832
LR		 1079 MLX5_SET(query_esw_vport_context_in, in, opcode,
1080 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
1081 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 1082 if (err)
1083 return err;
1084
5b7cb745
PB		 1085 curr = MLX5_GET(query_esw_vport_context_out, out,
1086 esw_vport_context.fdb_to_vport_reg_c_id);
1087 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
1088 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
1089 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 1090
332bd3a5 1091 if (enable)
5b7cb745 1092 curr |= wanted;
332bd3a5 1093 else
5b7cb745 1094 curr &= ~wanted;
c1286050 1095
e08a6832 1096 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 1097 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 1098 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 1099 field_select.fdb_to_vport_reg_c_id, 1);
1100
e08a6832 1101 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 1102 if (!err) {
1103 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1104 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1105 else
1106 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1107 }
1108
1109 return err;
c1286050
JL		 1110}
1111
a5641cb5
JL		 1112static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1113 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 1114 struct mlx5_flow_spec *spec,
1115 struct mlx5_flow_destination *dest)
1116{
a5641cb5 1117 void *misc;
ac004b83 1118
a5641cb5
JL		 1119 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1120 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1121 misc_parameters_2);
0f0d3827
PB		 1122 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1123 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 1124
a5641cb5
JL		 1125 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1126 } else {
1127 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1128 misc_parameters);
ac004b83 1129
a5641cb5
JL		 1130 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1131 MLX5_CAP_GEN(peer_dev, vhca_id));
1132
1133 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1134
1135 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1136 misc_parameters);
1137 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1138 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1139 source_eswitch_owner_vhca_id);
1140 }
ac004b83
RD		 1141
1142 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1143 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 1144 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 1145 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 1146}
1147
a5641cb5
JL		 1148static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1149 struct mlx5_eswitch *peer_esw,
1150 struct mlx5_flow_spec *spec,
1151 u16 vport)
1152{
1153 void *misc;
1154
1155 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1156 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1157 misc_parameters_2);
1158 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1159 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1160 vport));
1161 } else {
1162 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1163 misc_parameters);
1164 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1165 }
1166}
1167
ac004b83
RD		 1168static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1169 struct mlx5_core_dev *peer_dev)
1170{
1171 struct mlx5_flow_destination dest = {};
1172 struct mlx5_flow_act flow_act = {0};
1173 struct mlx5_flow_handle **flows;
ac004b83
RD		 1174 /* total vports is the same for both e-switches */
1175 int nvports = esw->total_vports;
47dd7e60
PP		 1176 struct mlx5_flow_handle *flow;
1177 struct mlx5_flow_spec *spec;
1178 struct mlx5_vport *vport;
1179 unsigned long i;
ac004b83 1180 void *misc;
47dd7e60 1181 int err;
ac004b83 1182
1552e9b5
RD		 1183 if (!MLX5_VPORT_MANAGER(esw->dev) && !mlx5_core_is_ecpf_esw_manager(esw->dev))
1184 return 0;
1185
ac004b83
RD		 1186 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1187 if (!spec)
1188 return -ENOMEM;
1189
a5641cb5 1190 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83 1191
806bf340 1192 flows = kvcalloc(nvports, sizeof(*flows), GFP_KERNEL);
ac004b83
RD		 1193 if (!flows) {
1194 err = -ENOMEM;
1195 goto alloc_flows_err;
1196 }
1197
1198 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1199 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1200 misc_parameters);
1201
81cd229c 1202 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
47dd7e60 1203 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
a5641cb5
JL		 1204 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1205 spec, MLX5_VPORT_PF);
1206
dcf19b9c 1207 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
81cd229c
BW		 1208 spec, &flow_act, &dest, 1);
1209 if (IS_ERR(flow)) {
1210 err = PTR_ERR(flow);
1211 goto add_pf_flow_err;
1212 }
47dd7e60 1213 flows[vport->index] = flow;
81cd229c
BW		 1214 }
1215
1216 if (mlx5_ecpf_vport_exists(esw->dev)) {
47dd7e60 1217 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
81cd229c 1218 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
dcf19b9c 1219 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
81cd229c
BW		 1220 spec, &flow_act, &dest, 1);
1221 if (IS_ERR(flow)) {
1222 err = PTR_ERR(flow);
1223 goto add_ecpf_flow_err;
1224 }
47dd7e60 1225 flows[vport->index] = flow;
81cd229c
BW		 1226 }
1227
47dd7e60 1228 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 1229 esw_set_peer_miss_rule_source_port(esw,
1230 peer_dev->priv.eswitch,
47dd7e60 1231 spec, vport->vport);
a5641cb5 1232
dcf19b9c 1233 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
ac004b83
RD		 1234 spec, &flow_act, &dest, 1);
1235 if (IS_ERR(flow)) {
1236 err = PTR_ERR(flow);
81cd229c 1237 goto add_vf_flow_err;
ac004b83 1238 }
47dd7e60 1239 flows[vport->index] = flow;
ac004b83
RD		 1240 }
1241
fa3c73ee
DJ		 1242 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
1243 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1244 if (i >= mlx5_core_max_ec_vfs(peer_dev))
1245 break;
1246 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1247 spec, vport->vport);
1248 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1249 spec, &flow_act, &dest, 1);
1250 if (IS_ERR(flow)) {
1251 err = PTR_ERR(flow);
1252 goto add_ec_vf_flow_err;
1253 }
1254 flows[vport->index] = flow;
1255 }
1256 }
9bee385a 1257 esw->fdb_table.offloads.peer_miss_rules[mlx5_get_dev_index(peer_dev)] = flows;
ac004b83
RD		 1258
1259 kvfree(spec);
1260 return 0;
1261
fa3c73ee
DJ		 1262add_ec_vf_flow_err:
1263 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1264 if (!flows[vport->index])
1265 continue;
1266 mlx5_del_flow_rules(flows[vport->index]);
1267 }
81cd229c 1268add_vf_flow_err:
47dd7e60
PP		 1269 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1270 if (!flows[vport->index])
1271 continue;
1272 mlx5_del_flow_rules(flows[vport->index]);
1273 }
1274 if (mlx5_ecpf_vport_exists(esw->dev)) {
1275 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1276 mlx5_del_flow_rules(flows[vport->index]);
1277 }
81cd229c 1278add_ecpf_flow_err:
47dd7e60
PP		 1279 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1280 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1281 mlx5_del_flow_rules(flows[vport->index]);
1282 }
81cd229c
BW		 1283add_pf_flow_err:
1284 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1285 kvfree(flows);
1286alloc_flows_err:
1287 kvfree(spec);
1288 return err;
1289}
1290
9bee385a
SD		 1291static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1292 struct mlx5_core_dev *peer_dev)
ac004b83 1293{
1552e9b5 1294 u16 peer_index = mlx5_get_dev_index(peer_dev);
ac004b83 1295 struct mlx5_flow_handle **flows;
47dd7e60
PP		 1296 struct mlx5_vport *vport;
1297 unsigned long i;
ac004b83 1298
1552e9b5
RD		 1299 flows = esw->fdb_table.offloads.peer_miss_rules[peer_index];
1300 if (!flows)
1301 return;
ac004b83 1302
fa3c73ee
DJ		 1303 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
1304 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1305 /* The flow for a particular vport could be NULL if the other ECPF
1306 * has fewer or no VFs enabled
1307 */
1308 if (!flows[vport->index])
1309 continue;
1310 mlx5_del_flow_rules(flows[vport->index]);
1311 }
1312 }
1313
47dd7e60
PP		 1314 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1315 mlx5_del_flow_rules(flows[vport->index]);
ac004b83 1316
47dd7e60
PP		 1317 if (mlx5_ecpf_vport_exists(esw->dev)) {
1318 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1319 mlx5_del_flow_rules(flows[vport->index]);
1320 }
81cd229c 1321
47dd7e60
PP		 1322 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1323 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1324 mlx5_del_flow_rules(flows[vport->index]);
1325 }
1552e9b5 1326
ac004b83 1327 kvfree(flows);
1552e9b5 1328 esw->fdb_table.offloads.peer_miss_rules[peer_index] = NULL;
ac004b83
RD		 1329}
1330
3aa33572
OG		 1331static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1332{
66958ed9 1333 struct mlx5_flow_act flow_act = {0};
4c5009c5 1334 struct mlx5_flow_destination dest = {};
74491de9 1335 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1336 struct mlx5_flow_spec *spec;
f80be543
MB		 1337 void *headers_c;
1338 void *headers_v;
3aa33572 1339 int err = 0;
f80be543
MB		 1340 u8 *dmac_c;
1341 u8 *dmac_v;
3aa33572 1342
1b9a07ee 1343 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1344 if (!spec) {
3aa33572
OG		 1345 err = -ENOMEM;
1346 goto out;
1347 }
1348
f80be543
MB		 1349 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1350 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1351 outer_headers);
1352 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1353 outer_headers.dmac_47_16);
1354 dmac_c[0] = 0x01;
1355
3aa33572 1356 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1357 dest.vport.num = esw->manager_vport;
66958ed9 1358 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1359
dcf19b9c 1360 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
39ac237c 1361 spec, &flow_act, &dest, 1);
3aa33572
OG		 1362 if (IS_ERR(flow_rule)) {
1363 err = PTR_ERR(flow_rule);
f80be543 1364 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1365 goto out;
1366 }
1367
f80be543
MB		 1368 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1369
1370 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1371 outer_headers);
1372 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1373 outer_headers.dmac_47_16);
1374 dmac_v[0] = 0x01;
dcf19b9c 1375 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
39ac237c 1376 spec, &flow_act, &dest, 1);
f80be543
MB		 1377 if (IS_ERR(flow_rule)) {
1378 err = PTR_ERR(flow_rule);
1379 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1380 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1381 goto out;
1382 }
1383
1384 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1385
3aa33572 1386out:
c5bb1730 1387 kvfree(spec);
3aa33572
OG		 1388 return err;
1389}
1390
11b717d6
PB		 1391struct mlx5_flow_handle *
1392esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1393{
1394 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1395 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1396 struct mlx5_flow_context *flow_context;
1397 struct mlx5_flow_handle *flow_rule;
1398 struct mlx5_flow_destination dest;
1399 struct mlx5_flow_spec *spec;
1400 void *misc;
1401
60acc105
PB		 1402 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1403 return ERR_PTR(-EOPNOTSUPP);
1404
9f4d9283 1405 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
11b717d6
PB		 1406 if (!spec)
1407 return ERR_PTR(-ENOMEM);
1408
1409 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1410 misc_parameters_2);
1411 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 1412 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 1413 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1414 misc_parameters_2);
1415 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1416 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1417 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1418 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1419 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1420
1421 flow_context = &spec->flow_context;
1422 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1423 flow_context->flow_tag = tag;
1424 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1425 dest.ft = esw->offloads.ft_offloads;
1426
1427 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
9f4d9283 1428 kvfree(spec);
11b717d6
PB		 1429
1430 if (IS_ERR(flow_rule))
1431 esw_warn(esw->dev,
1432 "Failed to create restore rule for tag: %d, err(%d)\n",
1433 tag, (int)PTR_ERR(flow_rule));
1434
1435 return flow_rule;
1436}
1437
1967ce6e 1438#define MAX_PF_SQ 256
cd3d07e7 1439#define MAX_SQ_NVPORTS 32
1967ce6e 1440
7eb197fd
RD		 1441void
1442mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1443 u32 *flow_group_in,
1444 int match_params)
a5641cb5
JL		 1445{
1446 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1447 flow_group_in,
1448 match_criteria);
1449
1450 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1451 MLX5_SET(create_flow_group_in, flow_group_in,
1452 match_criteria_enable,
29bcb6e4 1453 MLX5_MATCH_MISC_PARAMETERS_2 | match_params);
a5641cb5 1454
0f0d3827
PB		 1455 MLX5_SET(fte_match_param, match_criteria,
1456 misc_parameters_2.metadata_reg_c_0,
1457 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1458 } else {
1459 MLX5_SET(create_flow_group_in, flow_group_in,
1460 match_criteria_enable,
29bcb6e4 1461 MLX5_MATCH_MISC_PARAMETERS | match_params);
a5641cb5
JL		 1462
1463 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1464 misc_parameters.source_port);
1465 }
1466}
1467
ae430332 1468#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0a9e2307 1469static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
4c7f4028
CM		 1470{
1471 struct mlx5_vport_tbl_attr attr;
1472 struct mlx5_vport *vport;
47dd7e60 1473 unsigned long i;
4c7f4028
CM		 1474
1475 attr.chain = 0;
1476 attr.prio = 1;
47dd7e60 1477 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1478 attr.vport = vport->vport;
c796bb7c 1479 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1480 mlx5_esw_vporttbl_put(esw, &attr);
4c7f4028
CM		 1481 }
1482}
1483
0a9e2307 1484static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
4c7f4028
CM		 1485{
1486 struct mlx5_vport_tbl_attr attr;
1487 struct mlx5_flow_table *fdb;
1488 struct mlx5_vport *vport;
47dd7e60 1489 unsigned long i;
4c7f4028
CM		 1490
1491 attr.chain = 0;
1492 attr.prio = 1;
47dd7e60 1493 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1494 attr.vport = vport->vport;
c796bb7c 1495 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1496 fdb = mlx5_esw_vporttbl_get(esw, &attr);
4c7f4028
CM		 1497 if (IS_ERR(fdb))
1498 goto out;
1499 }
1500 return 0;
1501
1502out:
0a9e2307 1503 esw_vport_tbl_put(esw);
4c7f4028
CM		 1504 return PTR_ERR(fdb);
1505}
1506
ae430332
AL		 1507#define fdb_modify_header_fwd_to_table_supported(esw) \
1508 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1509static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1510{
1511 struct mlx5_core_dev *dev = esw->dev;
1512
1513 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1514 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1515
1516 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1517 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1518 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1519 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1520 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1521 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1522 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1523 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1524 /* Disabled when ttl workaround is needed, e.g
1525 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1526 */
1527 esw_warn(dev,
1528 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1529 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1530 } else {
1531 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1532 esw_info(dev, "Supported tc chains and prios offload\n");
1533 }
1534
1535 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1536 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1537}
1538
1539static int
1540esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1541{
1542 struct mlx5_core_dev *dev = esw->dev;
1543 struct mlx5_flow_table *nf_ft, *ft;
1544 struct mlx5_chains_attr attr = {};
1545 struct mlx5_fs_chains *chains;
ae430332
AL		 1546 int err;
1547
ae430332
AL		 1548 esw_init_chains_offload_flags(esw, &attr.flags);
1549 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
ae430332
AL		 1550 attr.max_grp_num = esw->params.large_group_num;
1551 attr.default_ft = miss_fdb;
c9355682 1552 attr.mapping = esw->offloads.reg_c0_obj_pool;
ae430332
AL		 1553
1554 chains = mlx5_chains_create(dev, &attr);
1555 if (IS_ERR(chains)) {
1556 err = PTR_ERR(chains);
1557 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1558 return err;
1559 }
8e80e564 1560 mlx5_chains_print_info(chains);
ae430332
AL		 1561
1562 esw->fdb_table.offloads.esw_chains_priv = chains;
1563
1564 /* Create tc_end_ft which is the always created ft chain */
1565 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1566 1, 0);
1567 if (IS_ERR(nf_ft)) {
1568 err = PTR_ERR(nf_ft);
1569 goto nf_ft_err;
1570 }
1571
1572 /* Always open the root for fast path */
1573 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1574 if (IS_ERR(ft)) {
1575 err = PTR_ERR(ft);
1576 goto level_0_err;
1577 }
1578
1579 /* Open level 1 for split fdb rules now if prios isn't supported */
1580 if (!mlx5_chains_prios_supported(chains)) {
0a9e2307 1581 err = esw_vport_tbl_get(esw);
ae430332
AL		 1582 if (err)
1583 goto level_1_err;
1584 }
1585
1586 mlx5_chains_set_end_ft(chains, nf_ft);
1587
1588 return 0;
1589
1590level_1_err:
1591 mlx5_chains_put_table(chains, 0, 1, 0);
1592level_0_err:
1593 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1594nf_ft_err:
1595 mlx5_chains_destroy(chains);
1596 esw->fdb_table.offloads.esw_chains_priv = NULL;
1597
1598 return err;
1599}
1600
1601static void
1602esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1603{
1604 if (!mlx5_chains_prios_supported(chains))
0a9e2307 1605 esw_vport_tbl_put(esw);
ae430332
AL		 1606 mlx5_chains_put_table(chains, 0, 1, 0);
1607 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1608 mlx5_chains_destroy(chains);
1609}
1610
1611#else /* CONFIG_MLX5_CLS_ACT */
1612
1613static int
1614esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1615{ return 0; }
1616
1617static void
1618esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1619{}
1620
1621#endif
1622
4a561817
RD		 1623static int
1624esw_create_send_to_vport_group(struct mlx5_eswitch *esw,
1625 struct mlx5_flow_table *fdb,
1626 u32 *flow_group_in,
1627 int *ix)
1628{
1629 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1630 struct mlx5_flow_group *g;
1631 void *match_criteria;
1632 int count, err = 0;
1633
1634 memset(flow_group_in, 0, inlen);
1635
7eb197fd 1636 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, MLX5_MATCH_MISC_PARAMETERS);
4a561817
RD		 1637
1638 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
4a561817 1639 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
29bcb6e4
RD		 1640
1641 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1642 MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
4a561817
RD		 1643 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1644 misc_parameters.source_eswitch_owner_vhca_id);
1645 MLX5_SET(create_flow_group_in, flow_group_in,
1646 source_eswitch_owner_vhca_id_valid, 1);
1647 }
1648
1649 /* See comment at table_size calculation */
1650 count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1651 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1652 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, *ix + count - 1);
1653 *ix += count;
1654
1655 g = mlx5_create_flow_group(fdb, flow_group_in);
1656 if (IS_ERR(g)) {
1657 err = PTR_ERR(g);
1658 esw_warn(esw->dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1659 goto out;
1660 }
1661 esw->fdb_table.offloads.send_to_vport_grp = g;
1662
1663out:
1664 return err;
1665}
1666
1667static int
1668esw_create_meta_send_to_vport_group(struct mlx5_eswitch *esw,
1669 struct mlx5_flow_table *fdb,
1670 u32 *flow_group_in,
1671 int *ix)
1672{
1673 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
4a561817
RD		 1674 struct mlx5_flow_group *g;
1675 void *match_criteria;
1676 int err = 0;
1677
1678 if (!esw_src_port_rewrite_supported(esw))
1679 return 0;
1680
1681 memset(flow_group_in, 0, inlen);
1682
1683 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1684 MLX5_MATCH_MISC_PARAMETERS_2);
1685
1686 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1687
1688 MLX5_SET(fte_match_param, match_criteria,
1689 misc_parameters_2.metadata_reg_c_0,
1690 mlx5_eswitch_get_vport_metadata_mask());
1691 MLX5_SET(fte_match_param, match_criteria,
1692 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1693
430e2d5e
RD		 1694 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1695 MLX5_SET(create_flow_group_in, flow_group_in,
1696 end_flow_index, *ix + esw->total_vports - 1);
1697 *ix += esw->total_vports;
4a561817 1698
430e2d5e
RD		 1699 g = mlx5_create_flow_group(fdb, flow_group_in);
1700 if (IS_ERR(g)) {
1701 err = PTR_ERR(g);
1702 esw_warn(esw->dev,
1703 "Failed to create send-to-vport meta flow group err(%d)\n", err);
1704 goto send_vport_meta_err;
4a561817 1705 }
430e2d5e 1706 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
4a561817
RD		 1707
1708 return 0;
1709
4a561817
RD		 1710send_vport_meta_err:
1711 return err;
1712}
1713
1714static int
1715esw_create_peer_esw_miss_group(struct mlx5_eswitch *esw,
1716 struct mlx5_flow_table *fdb,
1717 u32 *flow_group_in,
1718 int *ix)
1719{
18e31d42 1720 int max_peer_ports = (esw->total_vports - 1) * (MLX5_MAX_PORTS - 1);
4a561817
RD		 1721 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1722 struct mlx5_flow_group *g;
1723 void *match_criteria;
1724 int err = 0;
1725
1726 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1727 return 0;
1728
1729 memset(flow_group_in, 0, inlen);
1730
7eb197fd 1731 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
4a561817
RD		 1732
1733 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1734 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1735 flow_group_in,
1736 match_criteria);
1737
1738 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1739 misc_parameters.source_eswitch_owner_vhca_id);
1740
1741 MLX5_SET(create_flow_group_in, flow_group_in,
1742 source_eswitch_owner_vhca_id_valid, 1);
1743 }
1744
1745 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1746 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
18e31d42
SD		 1747 *ix + max_peer_ports);
1748 *ix += max_peer_ports + 1;
4a561817
RD		 1749
1750 g = mlx5_create_flow_group(fdb, flow_group_in);
1751 if (IS_ERR(g)) {
1752 err = PTR_ERR(g);
1753 esw_warn(esw->dev, "Failed to create peer miss flow group err(%d)\n", err);
1754 goto out;
1755 }
1756 esw->fdb_table.offloads.peer_miss_grp = g;
1757
1758out:
1759 return err;
1760}
1761
1762static int
1763esw_create_miss_group(struct mlx5_eswitch *esw,
1764 struct mlx5_flow_table *fdb,
1765 u32 *flow_group_in,
1766 int *ix)
1767{
1768 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1769 struct mlx5_flow_group *g;
1770 void *match_criteria;
1771 int err = 0;
1772 u8 *dmac;
1773
1774 memset(flow_group_in, 0, inlen);
1775
1776 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1777 MLX5_MATCH_OUTER_HEADERS);
1778 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1779 match_criteria);
1780 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1781 outer_headers.dmac_47_16);
1782 dmac[0] = 0x01;
1783
1784 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1785 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1786 *ix + MLX5_ESW_MISS_FLOWS);
1787
1788 g = mlx5_create_flow_group(fdb, flow_group_in);
1789 if (IS_ERR(g)) {
1790 err = PTR_ERR(g);
1791 esw_warn(esw->dev, "Failed to create miss flow group err(%d)\n", err);
1792 goto miss_err;
1793 }
1794 esw->fdb_table.offloads.miss_grp = g;
1795
1796 err = esw_add_fdb_miss_rule(esw);
1797 if (err)
1798 goto miss_rule_err;
1799
1800 return 0;
1801
1802miss_rule_err:
1803 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1804miss_err:
1805 return err;
1806}
1807
0da3c12d 1808static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1809{
1810 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1811 struct mlx5_flow_table_attr ft_attr = {};
1812 struct mlx5_core_dev *dev = esw->dev;
1813 struct mlx5_flow_namespace *root_ns;
1814 struct mlx5_flow_table *fdb = NULL;
4a561817 1815 int table_size, ix = 0, err = 0;
39ac237c 1816 u32 flags = 0, *flow_group_in;
1967ce6e
OG		 1817
1818 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1819
1b9a07ee 1820 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1821 if (!flow_group_in)
1822 return -ENOMEM;
1823
1824 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1825 if (!root_ns) {
1826 esw_warn(dev, "Failed to get FDB flow namespace\n");
1827 err = -EOPNOTSUPP;
1828 goto ns_err;
1829 }
8463daf1
MG		 1830 esw->fdb_table.offloads.ns = root_ns;
1831 err = mlx5_flow_namespace_set_mode(root_ns,
1832 esw->dev->priv.steering->mode);
1833 if (err) {
1834 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1835 goto ns_err;
1836 }
1967ce6e 1837
898b0786
MB		 1838 /* To be strictly correct:
1839 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1840 * should be:
1841 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1842 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1843 * but as the peer device might not be in switchdev mode it's not
1844 * possible. We use the fact that by default FW sets max vfs and max sfs
1845 * to the same value on both devices. If it needs to be changed in the future note
1846 * the peer miss group should also be created based on the number of
1847 * total vports of the peer (currently is also uses esw->total_vports).
1848 */
1849 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
18e31d42 1850 esw->total_vports * MLX5_MAX_PORTS + MLX5_ESW_MISS_FLOWS;
b3ba5149 1851
e52c2802
PB		 1852 /* create the slow path fdb with encap set, so further table instances
1853 * can be created at run time while VFs are probed if the FW allows that.
1854 */
1855 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1856 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1857 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1858
1859 ft_attr.flags = flags;
b3ba5149
ES		 1860 ft_attr.max_fte = table_size;
1861 ft_attr.prio = FDB_SLOW_PATH;
1862
1863 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1864 if (IS_ERR(fdb)) {
1865 err = PTR_ERR(fdb);
1866 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1867 goto slow_fdb_err;
1868 }
52fff327 1869 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1870
ec3be887
VB		 1871 /* Create empty TC-miss managed table. This allows plugging in following
1872 * priorities without directly exposing their level 0 table to
1873 * eswitch_offloads and passing it as miss_fdb to following call to
1874 * esw_chains_create().
1875 */
1876 memset(&ft_attr, 0, sizeof(ft_attr));
1877 ft_attr.prio = FDB_TC_MISS;
1878 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1879 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1880 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1881 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1882 goto tc_miss_table_err;
1883 }
1884
1885 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
39ac237c 1886 if (err) {
ae430332 1887 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1888 goto fdb_chains_err;
e52c2802
PB		 1889 }
1890
4a561817
RD		 1891 err = esw_create_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1892 if (err)
69697b6e 1893 goto send_vport_err;
8e404fef 1894
4a561817
RD		 1895 err = esw_create_meta_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1896 if (err)
1897 goto send_vport_meta_err;
69697b6e 1898
4a561817
RD		 1899 err = esw_create_peer_esw_miss_group(esw, fdb, flow_group_in, &ix);
1900 if (err)
1901 goto peer_miss_err;
69697b6e 1902
4a561817 1903 err = esw_create_miss_group(esw, fdb, flow_group_in, &ix);
3aa33572 1904 if (err)
4a561817 1905 goto miss_err;
3aa33572 1906
c88a026e 1907 kvfree(flow_group_in);
69697b6e
OG		 1908 return 0;
1909
1910miss_err:
6cec0229
MD		 1911 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1912 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1913peer_miss_err:
8e404fef
VB		 1914 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1915 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1916send_vport_meta_err:
69697b6e
OG		 1917 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1918send_vport_err:
ae430332 1919 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1920fdb_chains_err:
ec3be887
VB		 1921 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1922tc_miss_table_err:
dcf19b9c 1923 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1033665e 1924slow_fdb_err:
8463daf1
MG		 1925 /* Holds true only as long as DMFS is the default */
1926 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1927ns_err:
1928 kvfree(flow_group_in);
1929 return err;
1930}
1931
1967ce6e 1932static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1933{
dcf19b9c 1934 if (!mlx5_eswitch_get_slow_fdb(esw))
69697b6e
OG		 1935 return;
1936
1967ce6e 1937 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1938 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1939 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e 1940 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
8e404fef
VB		 1941 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1942 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
6cec0229
MD		 1943 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1944 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1945 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1946
ae430332
AL		 1947 esw_chains_destroy(esw, esw_chains(esw));
1948
ec3be887 1949 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
dcf19b9c 1950 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
8463daf1
MG		 1951 /* Holds true only as long as DMFS is the default */
1952 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1953 MLX5_FLOW_STEERING_MODE_DMFS);
7dc84de9 1954 atomic64_set(&esw->user_count, 0);
69697b6e 1955}
c116c6ee 1956
8ea7bcf6 1957static int esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch *esw)
4f4edcc2
AL		 1958{
1959 int nvports;
1960
1961 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1962 if (mlx5e_tc_int_port_supported(esw))
1963 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1964
1965 return nvports;
1966}
1967
8d6bd3c3 1968static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1969{
b3ba5149 1970 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1971 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1972 struct mlx5_flow_table *ft_offloads;
1973 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1974 int err = 0;
1975
1976 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1977 if (!ns) {
1978 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1979 return -EOPNOTSUPP;
c116c6ee
OG		 1980 }
1981
8ea7bcf6
JL		 1982 ft_attr.max_fte = esw_get_nr_ft_offloads_steering_src_ports(esw) +
1983 MLX5_ESW_FT_OFFLOADS_DROP_RULE;
11b717d6 1984 ft_attr.prio = 1;
b3ba5149
ES		 1985
1986 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1987 if (IS_ERR(ft_offloads)) {
1988 err = PTR_ERR(ft_offloads);
1989 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1990 return err;
1991 }
1992
1993 esw->offloads.ft_offloads = ft_offloads;
1994 return 0;
1995}
1996
1997static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1998{
1999 struct mlx5_esw_offload *offloads = &esw->offloads;
2000
2001 mlx5_destroy_flow_table(offloads->ft_offloads);
2002}
fed9ce22 2003
8d6bd3c3 2004static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 2005{
2006 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2007 struct mlx5_flow_group *g;
fed9ce22 2008 u32 *flow_group_in;
8d6bd3c3 2009 int nvports;
fed9ce22 2010 int err = 0;
fed9ce22 2011
8ea7bcf6 2012 nvports = esw_get_nr_ft_offloads_steering_src_ports(esw);
1b9a07ee 2013 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 2014 if (!flow_group_in)
2015 return -ENOMEM;
2016
7eb197fd 2017 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
fed9ce22
OG		 2018
2019 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2020 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
2021
2022 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2023
2024 if (IS_ERR(g)) {
2025 err = PTR_ERR(g);
2026 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
2027 goto out;
2028 }
2029
2030 esw->offloads.vport_rx_group = g;
2031out:
e574978a 2032 kvfree(flow_group_in);
fed9ce22
OG		 2033 return err;
2034}
2035
2036static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
2037{
2038 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
2039}
2040
8ea7bcf6
JL		 2041static int esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch *esw)
2042{
2043 /* ft_offloads table is enlarged by MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
2044 * for the drop rule, which is placed at the end of the table.
2045 * So return the total of vport and int_port as rule index.
2046 */
2047 return esw_get_nr_ft_offloads_steering_src_ports(esw);
2048}
2049
2050static int esw_create_vport_rx_drop_group(struct mlx5_eswitch *esw)
2051{
2052 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2053 struct mlx5_flow_group *g;
2054 u32 *flow_group_in;
2055 int flow_index;
2056 int err = 0;
2057
2058 flow_index = esw_create_vport_rx_drop_rule_index(esw);
2059
2060 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2061 if (!flow_group_in)
2062 return -ENOMEM;
2063
2064 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
2065 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
2066
2067 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
2068
2069 if (IS_ERR(g)) {
2070 err = PTR_ERR(g);
2071 mlx5_core_warn(esw->dev, "Failed to create vport rx drop group err %d\n", err);
2072 goto out;
2073 }
2074
2075 esw->offloads.vport_rx_drop_group = g;
2076out:
2077 kvfree(flow_group_in);
2078 return err;
2079}
2080
2081static void esw_destroy_vport_rx_drop_group(struct mlx5_eswitch *esw)
2082{
2083 if (esw->offloads.vport_rx_drop_group)
2084 mlx5_destroy_flow_group(esw->offloads.vport_rx_drop_group);
2085}
2086
7eb197fd
RD		 2087void
2088mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
2089 u16 vport,
2090 struct mlx5_flow_spec *spec)
fed9ce22 2091{
fed9ce22
OG		 2092 void *misc;
2093
a5641cb5
JL		 2094 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
2095 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
2096 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2097 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 2098
a5641cb5 2099 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 2100 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
2101 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 2102
a5641cb5
JL		 2103 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
2104 } else {
2105 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
2106 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
2107
2108 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2109 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2110
2111 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2112 }
7eb197fd
RD		 2113}
2114
2115struct mlx5_flow_handle *
2116mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
2117 struct mlx5_flow_destination *dest)
2118{
2119 struct mlx5_flow_act flow_act = {0};
2120 struct mlx5_flow_handle *flow_rule;
2121 struct mlx5_flow_spec *spec;
2122
2123 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2124 if (!spec) {
2125 flow_rule = ERR_PTR(-ENOMEM);
2126 goto out;
2127 }
2128
2129 mlx5_esw_set_spec_source_port(esw, vport, spec);
fed9ce22 2130
66958ed9 2131 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 2132 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 2133 &flow_act, dest, 1);
fed9ce22
OG		 2134 if (IS_ERR(flow_rule)) {
2135 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
2136 goto out;
2137 }
2138
2139out:
c5bb1730 2140 kvfree(spec);
fed9ce22
OG		 2141 return flow_rule;
2142}
feae9087 2143
8ea7bcf6
JL		 2144static int esw_create_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2145{
2146 struct mlx5_flow_act flow_act = {};
2147 struct mlx5_flow_handle *flow_rule;
2148
2149 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2150 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, NULL,
2151 &flow_act, NULL, 0);
2152 if (IS_ERR(flow_rule)) {
2153 esw_warn(esw->dev,
2154 "fs offloads: Failed to add vport rx drop rule err %ld\n",
2155 PTR_ERR(flow_rule));
2156 return PTR_ERR(flow_rule);
2157 }
2158
2159 esw->offloads.vport_rx_drop_rule = flow_rule;
2160
2161 return 0;
2162}
2163
2164static void esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2165{
2166 if (esw->offloads.vport_rx_drop_rule)
2167 mlx5_del_flow_rules(esw->offloads.vport_rx_drop_rule);
2168}
2169
47dd7e60 2170static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
cc617ced
PP		 2171{
2172 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2173 struct mlx5_core_dev *dev = esw->dev;
47dd7e60
PP		 2174 struct mlx5_vport *vport;
2175 unsigned long i;
cc617ced
PP		 2176
2177 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2178 return -EOPNOTSUPP;
2179
f019679e 2180 if (!mlx5_esw_is_fdb_created(esw))
cc617ced
PP		 2181 return -EOPNOTSUPP;
2182
2183 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2184 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2185 mlx5_mode = MLX5_INLINE_MODE_NONE;
2186 goto out;
2187 case MLX5_CAP_INLINE_MODE_L2:
2188 mlx5_mode = MLX5_INLINE_MODE_L2;
2189 goto out;
2190 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2191 goto query_vports;
2192 }
2193
2194query_vports:
2195 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
47dd7e60
PP		 2196 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2197 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
cc617ced
PP		 2198 if (prev_mlx5_mode != mlx5_mode)
2199 return -EINVAL;
2200 prev_mlx5_mode = mlx5_mode;
2201 }
2202
2203out:
2204 *mode = mlx5_mode;
2205 return 0;
e08a6832 2206}
bf3347c4 2207
11b717d6
PB		 2208static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2209{
2210 struct mlx5_esw_offload *offloads = &esw->offloads;
2211
60acc105
PB		 2212 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2213 return;
2214
6724e66b 2215 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 2216 mlx5_destroy_flow_group(offloads->restore_group);
2217 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2218}
2219
2220static int esw_create_restore_table(struct mlx5_eswitch *esw)
2221{
d65dbedf 2222 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 2223 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2224 struct mlx5_flow_table_attr ft_attr = {};
2225 struct mlx5_core_dev *dev = esw->dev;
2226 struct mlx5_flow_namespace *ns;
6724e66b 2227 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 2228 void *match_criteria, *misc;
2229 struct mlx5_flow_table *ft;
2230 struct mlx5_flow_group *g;
2231 u32 *flow_group_in;
2232 int err = 0;
2233
60acc105
PB		 2234 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2235 return 0;
2236
11b717d6
PB		 2237 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2238 if (!ns) {
2239 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2240 return -EOPNOTSUPP;
2241 }
2242
2243 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2244 if (!flow_group_in) {
2245 err = -ENOMEM;
2246 goto out_free;
2247 }
2248
a91d98a0 2249 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
11b717d6
PB		 2250 ft = mlx5_create_flow_table(ns, &ft_attr);
2251 if (IS_ERR(ft)) {
2252 err = PTR_ERR(ft);
2253 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2254 err);
2255 goto out_free;
2256 }
2257
11b717d6
PB		 2258 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2259 match_criteria);
2260 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2261 misc_parameters_2);
2262
2263 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 2264 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 2265 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2266 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2267 ft_attr.max_fte - 1);
2268 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2269 MLX5_MATCH_MISC_PARAMETERS_2);
2270 g = mlx5_create_flow_group(ft, flow_group_in);
2271 if (IS_ERR(g)) {
2272 err = PTR_ERR(g);
2273 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2274 err);
2275 goto err_group;
2276 }
2277
6724e66b
PB		 2278 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2279 MLX5_SET(copy_action_in, modact, src_field,
2280 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2281 MLX5_SET(copy_action_in, modact, dst_field,
2282 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2283 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2284 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2285 modact);
2286 if (IS_ERR(mod_hdr)) {
e9864539 2287 err = PTR_ERR(mod_hdr);
6724e66b
PB		 2288 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2289 err);
6724e66b
PB		 2290 goto err_mod_hdr;
2291 }
2292
11b717d6
PB		 2293 esw->offloads.ft_offloads_restore = ft;
2294 esw->offloads.restore_group = g;
6724e66b 2295 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 2296
c8508713
RD		 2297 kvfree(flow_group_in);
2298
11b717d6
PB		 2299 return 0;
2300
6724e66b
PB		 2301err_mod_hdr:
2302 mlx5_destroy_flow_group(g);
11b717d6
PB		 2303err_group:
2304 mlx5_destroy_flow_table(ft);
2305out_free:
2306 kvfree(flow_group_in);
2307
2308 return err;
cc617ced
PP		 2309}
2310
db7ff19e
EB		 2311static int esw_offloads_start(struct mlx5_eswitch *esw,
2312 struct netlink_ext_ack *extack)
c930a3ad 2313{
e12de39c 2314 int err;
c930a3ad 2315
b6f2846a
CM		 2316 esw->mode = MLX5_ESWITCH_OFFLOADS;
2317 err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
6c419ba8 2318 if (err) {
8c98ee77
EB		 2319 NL_SET_ERR_MSG_MOD(extack,
2320 "Failed setting eswitch to offloads");
b6f2846a 2321 esw->mode = MLX5_ESWITCH_LEGACY;
b6f2846a 2322 mlx5_rescan_drivers(esw->dev);
97bd788e 2323 return err;
6c419ba8 2324 }
bffaa916
RD		 2325 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2326 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 2327 &esw->offloads.inline_mode)) {
2328 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 2329 NL_SET_ERR_MSG_MOD(extack,
2330 "Inline mode is different between vports");
bffaa916
RD		 2331 }
2332 }
97bd788e 2333 return 0;
c930a3ad
OG		 2334}
2335
47dd7e60 2336static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
e8d31c4d 2337{
e8d31c4d 2338 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 2339 int rep_type;
2340 int err;
e8d31c4d 2341
47dd7e60
PP		 2342 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2343 if (!rep)
e8d31c4d
MB		 2344 return -ENOMEM;
2345
47dd7e60
PP		 2346 rep->vport = vport->vport;
2347 rep->vport_index = vport->index;
2348 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2349 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
f121e0ea 2350
47dd7e60
PP		 2351 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2352 if (err)
2353 goto insert_err;
2354
47dd7e60
PP		 2355 return 0;
2356
2357insert_err:
2358 kfree(rep);
2359 return err;
2360}
2361
2362static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2363 struct mlx5_eswitch_rep *rep)
2364{
2365 xa_erase(&esw->offloads.vport_reps, rep->vport);
2366 kfree(rep);
2367}
2368
d2a651ef 2369static void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
47dd7e60
PP		 2370{
2371 struct mlx5_eswitch_rep *rep;
2372 unsigned long i;
e8d31c4d 2373
47dd7e60
PP		 2374 mlx5_esw_for_each_rep(esw, i, rep)
2375 mlx5_esw_offloads_rep_cleanup(esw, rep);
2376 xa_destroy(&esw->offloads.vport_reps);
2377}
2378
d2a651ef 2379static int esw_offloads_init_reps(struct mlx5_eswitch *esw)
47dd7e60
PP		 2380{
2381 struct mlx5_vport *vport;
2382 unsigned long i;
2383 int err;
2384
2385 xa_init(&esw->offloads.vport_reps);
2386
2387 mlx5_esw_for_each_vport(esw, i, vport) {
2388 err = mlx5_esw_offloads_rep_init(esw, vport);
2389 if (err)
2390 goto err;
2391 }
e8d31c4d 2392 return 0;
47dd7e60
PP		 2393
2394err:
2395 esw_offloads_cleanup_reps(esw);
2396 return err;
e8d31c4d
MB		 2397}
2398
d2a651ef
JP		 2399static int esw_port_metadata_set(struct devlink *devlink, u32 id,
2400 struct devlink_param_gset_ctx *ctx)
2401{
2402 struct mlx5_core_dev *dev = devlink_priv(devlink);
2403 struct mlx5_eswitch *esw = dev->priv.eswitch;
2404 int err = 0;
2405
2406 down_write(&esw->mode_lock);
2407 if (mlx5_esw_is_fdb_created(esw)) {
2408 err = -EBUSY;
2409 goto done;
2410 }
2411 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2412 err = -EOPNOTSUPP;
2413 goto done;
2414 }
2415 if (ctx->val.vbool)
2416 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2417 else
2418 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2419done:
2420 up_write(&esw->mode_lock);
2421 return err;
2422}
2423
2424static int esw_port_metadata_get(struct devlink *devlink, u32 id,
2425 struct devlink_param_gset_ctx *ctx)
2426{
2427 struct mlx5_core_dev *dev = devlink_priv(devlink);
2428
2429 ctx->val.vbool = mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch);
2430 return 0;
2431}
2432
2433static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
2434 union devlink_param_value val,
2435 struct netlink_ext_ack *extack)
2436{
2437 struct mlx5_core_dev *dev = devlink_priv(devlink);
2438 u8 esw_mode;
2439
2440 esw_mode = mlx5_eswitch_mode(dev);
2441 if (esw_mode == MLX5_ESWITCH_OFFLOADS) {
2442 NL_SET_ERR_MSG_MOD(extack,
2443 "E-Switch must either disabled or non switchdev mode");
2444 return -EBUSY;
2445 }
2446 return 0;
2447}
2448
2449static const struct devlink_param esw_devlink_params[] = {
2450 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
2451 "esw_port_metadata", DEVLINK_PARAM_TYPE_BOOL,
2452 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2453 esw_port_metadata_get,
2454 esw_port_metadata_set,
2455 esw_port_metadata_validate),
2456};
2457
2458int esw_offloads_init(struct mlx5_eswitch *esw)
2459{
2460 int err;
2461
2462 err = esw_offloads_init_reps(esw);
2463 if (err)
2464 return err;
2465
2466 err = devl_params_register(priv_to_devlink(esw->dev),
2467 esw_devlink_params,
2468 ARRAY_SIZE(esw_devlink_params));
2469 if (err)
2470 goto err_params;
2471
2472 return 0;
2473
2474err_params:
2475 esw_offloads_cleanup_reps(esw);
2476 return err;
2477}
2478
2479void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2480{
2481 devl_params_unregister(priv_to_devlink(esw->dev),
2482 esw_devlink_params,
2483 ARRAY_SIZE(esw_devlink_params));
2484 esw_offloads_cleanup_reps(esw);
2485}
2486
c9b99abc
BW		 2487static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2488 struct mlx5_eswitch_rep *rep, u8 rep_type)
2489{
8693115a 2490 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 2491 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 2492 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 2493}
2494
4110fc59 2495static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 2496{
2497 struct mlx5_eswitch_rep *rep;
47dd7e60 2498 unsigned long i;
4110fc59 2499
18a92b05 2500 mlx5_esw_for_each_rep(esw, i, rep)
81cd229c 2501 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2502}
2503
b7186387 2504static int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 2505{
c2d7712c
BW		 2506 struct mlx5_eswitch_rep *rep;
2507 int rep_type;
a4b97ab4
MB		 2508 int err;
2509
c2d7712c
BW		 2510 rep = mlx5_eswitch_get_rep(esw, vport_num);
2511 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2512 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2513 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2514 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2515 if (err)
2516 goto err_reps;
2517 }
2518
2519 return 0;
a4b97ab4
MB		 2520
2521err_reps:
c2d7712c
BW		 2522 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2523 for (--rep_type; rep_type >= 0; rep_type--)
2524 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2525 return err;
2526}
2527
b7186387 2528static void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 2529{
2530 struct mlx5_eswitch_rep *rep;
2531 int rep_type;
2532
c2d7712c
BW		 2533 rep = mlx5_eswitch_get_rep(esw, vport_num);
2534 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2535 __esw_offloads_unload_rep(esw, rep, rep_type);
2536}
2537
d9833bcf
JP		 2538int mlx5_esw_offloads_init_pf_vf_rep(struct mlx5_eswitch *esw, u16 vport_num)
2539{
2540 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2541 return 0;
2542
2543 return mlx5_esw_offloads_pf_vf_devlink_port_init(esw, vport_num);
2544}
2545
2546void mlx5_esw_offloads_cleanup_pf_vf_rep(struct mlx5_eswitch *esw, u16 vport_num)
2547{
2548 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2549 return;
2550
2551 mlx5_esw_offloads_pf_vf_devlink_port_cleanup(esw, vport_num);
2552}
2553
9eca8bb8 2554int mlx5_esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
38679b5a
PP		 2555{
2556 int err;
2557
2558 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2559 return 0;
2560
ba3d85f0
JP		 2561 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2562 if (err)
2563 return err;
c7eddc60 2564
38679b5a 2565 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 2566 if (err)
2567 goto load_err;
2568 return err;
2569
2570load_err:
ba3d85f0 2571 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2572 return err;
2573}
2574
9eca8bb8 2575void mlx5_esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
38679b5a
PP		 2576{
2577 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2578 return;
2579
2580 mlx5_esw_offloads_rep_unload(esw, vport_num);
865d6d1c 2581
ba3d85f0 2582 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2583}
2584
db202995
MB		 2585static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2586 struct mlx5_core_dev *slave)
2587{
2588 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2589 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2590 struct mlx5_flow_root_namespace *root;
2591 struct mlx5_flow_namespace *ns;
2592 int err;
2593
2594 MLX5_SET(set_flow_table_root_in, in, opcode,
2595 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2596 MLX5_SET(set_flow_table_root_in, in, table_type,
2597 FS_FT_FDB);
2598
2599 if (master) {
2600 ns = mlx5_get_flow_namespace(master,
2601 MLX5_FLOW_NAMESPACE_FDB);
2602 root = find_root(&ns->node);
2603 mutex_lock(&root->chain_lock);
2604 MLX5_SET(set_flow_table_root_in, in,
2605 table_eswitch_owner_vhca_id_valid, 1);
2606 MLX5_SET(set_flow_table_root_in, in,
2607 table_eswitch_owner_vhca_id,
2608 MLX5_CAP_GEN(master, vhca_id));
2609 MLX5_SET(set_flow_table_root_in, in, table_id,
2610 root->root_ft->id);
2611 } else {
2612 ns = mlx5_get_flow_namespace(slave,
2613 MLX5_FLOW_NAMESPACE_FDB);
2614 root = find_root(&ns->node);
2615 mutex_lock(&root->chain_lock);
2616 MLX5_SET(set_flow_table_root_in, in, table_id,
2617 root->root_ft->id);
2618 }
2619
2620 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2621 mutex_unlock(&root->chain_lock);
2622
2623 return err;
2624}
2625
2626static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2627 struct mlx5_core_dev *slave,
2628 struct mlx5_vport *vport,
2629 struct mlx5_flow_table *acl)
2630{
5e0202eb 2631 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
db202995
MB		 2632 struct mlx5_flow_handle *flow_rule = NULL;
2633 struct mlx5_flow_destination dest = {};
2634 struct mlx5_flow_act flow_act = {};
2635 struct mlx5_flow_spec *spec;
2636 int err = 0;
2637 void *misc;
2638
2639 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2640 if (!spec)
2641 return -ENOMEM;
2642
2643 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2644 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2645 misc_parameters);
2646 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
5e0202eb 2647 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, slave_index);
db202995
MB		 2648
2649 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2650 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2651 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2652 source_eswitch_owner_vhca_id);
2653
2654 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2655 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2656 dest.vport.num = slave->priv.eswitch->manager_vport;
2657 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2658 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2659
2660 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2661 &dest, 1);
5e0202eb 2662 if (IS_ERR(flow_rule)) {
db202995 2663 err = PTR_ERR(flow_rule);
5e0202eb
SD		 2664 } else {
2665 err = xa_insert(&vport->egress.offloads.bounce_rules,
2666 slave_index, flow_rule, GFP_KERNEL);
2667 if (err)
2668 mlx5_del_flow_rules(flow_rule);
2669 }
db202995
MB		 2670
2671 kvfree(spec);
2672 return err;
2673}
2674
4575ab3b
RD		 2675static int esw_master_egress_create_resources(struct mlx5_eswitch *esw,
2676 struct mlx5_flow_namespace *egress_ns,
014e4d48 2677 struct mlx5_vport *vport, size_t count)
db202995
MB		 2678{
2679 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
db202995 2680 struct mlx5_flow_table_attr ft_attr = {
014e4d48 2681 .max_fte = count, .prio = 0, .level = 0,
db202995 2682 };
db202995
MB		 2683 struct mlx5_flow_table *acl;
2684 struct mlx5_flow_group *g;
db202995
MB		 2685 void *match_criteria;
2686 u32 *flow_group_in;
2687 int err;
2688
db202995 2689 if (vport->egress.acl)
5e0202eb 2690 return 0;
db202995
MB		 2691
2692 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2693 if (!flow_group_in)
2694 return -ENOMEM;
2695
4575ab3b
RD		 2696 if (vport->vport || mlx5_core_is_ecpf(esw->dev))
2697 ft_attr.flags = MLX5_FLOW_TABLE_OTHER_VPORT;
2698
db202995
MB		 2699 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2700 if (IS_ERR(acl)) {
2701 err = PTR_ERR(acl);
2702 goto out;
2703 }
2704
2705 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2706 match_criteria);
2707 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2708 misc_parameters.source_port);
2709 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2710 misc_parameters.source_eswitch_owner_vhca_id);
2711 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2712 MLX5_MATCH_MISC_PARAMETERS);
2713
2714 MLX5_SET(create_flow_group_in, flow_group_in,
2715 source_eswitch_owner_vhca_id_valid, 1);
2716 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
014e4d48 2717 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, count);
db202995
MB		 2718
2719 g = mlx5_create_flow_group(acl, flow_group_in);
2720 if (IS_ERR(g)) {
2721 err = PTR_ERR(g);
2722 goto err_group;
2723 }
2724
db202995
MB		 2725 vport->egress.acl = acl;
2726 vport->egress.offloads.bounce_grp = g;
5e0202eb
SD		 2727 vport->egress.type = VPORT_EGRESS_ACL_TYPE_SHARED_FDB;
2728 xa_init_flags(&vport->egress.offloads.bounce_rules, XA_FLAGS_ALLOC);
db202995
MB		 2729
2730 kvfree(flow_group_in);
2731
2732 return 0;
2733
db202995
MB		 2734err_group:
2735 mlx5_destroy_flow_table(acl);
2736out:
2737 kvfree(flow_group_in);
2738 return err;
2739}
2740
5e0202eb
SD		 2741static void esw_master_egress_destroy_resources(struct mlx5_vport *vport)
2742{
15ddd72e
RD		 2743 if (!xa_empty(&vport->egress.offloads.bounce_rules))
2744 return;
5e0202eb 2745 mlx5_destroy_flow_group(vport->egress.offloads.bounce_grp);
15ddd72e 2746 vport->egress.offloads.bounce_grp = NULL;
5e0202eb 2747 mlx5_destroy_flow_table(vport->egress.acl);
15ddd72e 2748 vport->egress.acl = NULL;
5e0202eb
SD		 2749}
2750
2751static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
014e4d48 2752 struct mlx5_core_dev *slave, size_t count)
5e0202eb
SD		 2753{
2754 struct mlx5_eswitch *esw = master->priv.eswitch;
2755 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2756 struct mlx5_flow_namespace *egress_ns;
2757 struct mlx5_vport *vport;
2758 int err;
2759
2760 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2761 if (IS_ERR(vport))
2762 return PTR_ERR(vport);
2763
2764 egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2765 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2766 vport->index);
2767 if (!egress_ns)
2768 return -EINVAL;
2769
2770 if (vport->egress.acl && vport->egress.type != VPORT_EGRESS_ACL_TYPE_SHARED_FDB)
2771 return 0;
2772
4575ab3b 2773 err = esw_master_egress_create_resources(esw, egress_ns, vport, count);
5e0202eb
SD		 2774 if (err)
2775 return err;
2776
2777 if (xa_load(&vport->egress.offloads.bounce_rules, slave_index))
2778 return -EINVAL;
2779
2780 err = __esw_set_master_egress_rule(master, slave, vport, vport->egress.acl);
2781 if (err)
2782 goto err_rule;
2783
2784 return 0;
2785
2786err_rule:
2787 esw_master_egress_destroy_resources(vport);
2788 return err;
2789}
2790
014e4d48
SD		 2791static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev,
2792 struct mlx5_core_dev *slave_dev)
db202995
MB		 2793{
2794 struct mlx5_vport *vport;
2795
2796 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2797 dev->priv.eswitch->manager_vport);
2798
014e4d48
SD		 2799 esw_acl_egress_ofld_bounce_rule_destroy(vport, MLX5_CAP_GEN(slave_dev, vhca_id));
2800
2801 if (xa_empty(&vport->egress.offloads.bounce_rules)) {
2802 esw_acl_egress_ofld_cleanup(vport);
2803 xa_destroy(&vport->egress.offloads.bounce_rules);
2804 }
db202995
MB		 2805}
2806
014e4d48
SD		 2807int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
2808 struct mlx5_eswitch *slave_esw, int max_slaves)
db202995
MB		 2809{
2810 int err;
2811
db202995
MB		 2812 err = esw_set_slave_root_fdb(master_esw->dev,
2813 slave_esw->dev);
2814 if (err)
82e86a6c 2815 return err;
db202995
MB		 2816
2817 err = esw_set_master_egress_rule(master_esw->dev,
014e4d48 2818 slave_esw->dev, max_slaves);
db202995
MB		 2819 if (err)
2820 goto err_acl;
2821
2822 return err;
2823
2824err_acl:
2825 esw_set_slave_root_fdb(NULL, slave_esw->dev);
db202995
MB		 2826 return err;
2827}
2828
014e4d48 2829void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
db202995
MB		 2830 struct mlx5_eswitch *slave_esw)
2831{
db202995 2832 esw_set_slave_root_fdb(NULL, slave_esw->dev);
014e4d48 2833 esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev);
db202995
MB		 2834}
2835
ac004b83
RD		 2836#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2837#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2838
ed7a8fe7
MB		 2839static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw,
2840 struct mlx5_eswitch *peer_esw)
ac004b83 2841{
c8e6a9e6
MB		 2842 const struct mlx5_eswitch_rep_ops *ops;
2843 struct mlx5_eswitch_rep *rep;
2844 unsigned long i;
2845 u8 rep_type;
2846
2847 mlx5_esw_for_each_rep(esw, i, rep) {
2848 rep_type = NUM_REP_TYPES;
2849 while (rep_type--) {
2850 ops = esw->offloads.rep_ops[rep_type];
2851 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2852 ops->event)
ed7a8fe7 2853 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, peer_esw);
c8e6a9e6
MB		 2854 }
2855 }
ac004b83
RD		 2856}
2857
ed7a8fe7
MB		 2858static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,
2859 struct mlx5_eswitch *peer_esw)
ac004b83 2860{
d956873f 2861#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 2862 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 2863#endif
ed7a8fe7 2864 mlx5_esw_offloads_rep_event_unpair(esw, peer_esw);
9bee385a 2865 esw_del_fdb_peer_miss_rules(esw, peer_esw->dev);
ac004b83
RD		 2866}
2867
c8e6a9e6
MB		 2868static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2869 struct mlx5_eswitch *peer_esw)
2870{
2871 const struct mlx5_eswitch_rep_ops *ops;
2872 struct mlx5_eswitch_rep *rep;
2873 unsigned long i;
2874 u8 rep_type;
2875 int err;
2876
2877 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2878 if (err)
2879 return err;
2880
2881 mlx5_esw_for_each_rep(esw, i, rep) {
2882 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2883 ops = esw->offloads.rep_ops[rep_type];
2884 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2885 ops->event) {
2886 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2887 if (err)
2888 goto err_out;
2889 }
2890 }
2891 }
2892
2893 return 0;
2894
2895err_out:
ed7a8fe7 2896 mlx5_esw_offloads_unpair(esw, peer_esw);
c8e6a9e6
MB		 2897 return err;
2898}
2899
8463daf1
MG		 2900static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2901 struct mlx5_eswitch *peer_esw,
2902 bool pair)
2903{
62752c0b
SD		 2904 u16 peer_vhca_id = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
2905 u16 vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id);
8463daf1
MG		 2906 struct mlx5_flow_root_namespace *peer_ns;
2907 struct mlx5_flow_root_namespace *ns;
2908 int err;
2909
2910 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2911 ns = esw->dev->priv.steering->fdb_root_ns;
2912
2913 if (pair) {
62752c0b 2914 err = mlx5_flow_namespace_set_peer(ns, peer_ns, peer_vhca_id);
8463daf1
MG		 2915 if (err)
2916 return err;
2917
62752c0b 2918 err = mlx5_flow_namespace_set_peer(peer_ns, ns, vhca_id);
8463daf1 2919 if (err) {
62752c0b 2920 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
8463daf1
MG		 2921 return err;
2922 }
2923 } else {
62752c0b
SD		 2924 mlx5_flow_namespace_set_peer(ns, NULL, peer_vhca_id);
2925 mlx5_flow_namespace_set_peer(peer_ns, NULL, vhca_id);
8463daf1
MG		 2926 }
2927
2928 return 0;
2929}
2930
ac004b83
RD		 2931static int mlx5_esw_offloads_devcom_event(int event,
2932 void *my_data,
2933 void *event_data)
2934{
2935 struct mlx5_eswitch *esw = my_data;
8463daf1 2936 struct mlx5_eswitch *peer_esw = event_data;
70c36438
RD		 2937 u16 esw_i, peer_esw_i;
2938 bool esw_paired;
ac004b83
RD		 2939 int err;
2940
70c36438
RD		 2941 peer_esw_i = MLX5_CAP_GEN(peer_esw->dev, vhca_id);
2942 esw_i = MLX5_CAP_GEN(esw->dev, vhca_id);
2943 esw_paired = !!xa_load(&esw->paired, peer_esw_i);
2944
ac004b83
RD		 2945 switch (event) {
2946 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 2947 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2948 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2949 break;
2950
70c36438 2951 if (esw_paired)
8c253dfc
SD		 2952 break;
2953
8463daf1 2954 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 2955 if (err)
2956 goto err_out;
88d162b4 2957
8463daf1
MG		 2958 err = mlx5_esw_offloads_pair(esw, peer_esw);
2959 if (err)
2960 goto err_peer;
ac004b83
RD		 2961
2962 err = mlx5_esw_offloads_pair(peer_esw, esw);
2963 if (err)
2964 goto err_pair;
2965
70c36438
RD		 2966 err = xa_insert(&esw->paired, peer_esw_i, peer_esw, GFP_KERNEL);
2967 if (err)
2968 goto err_xa;
2969
2970 err = xa_insert(&peer_esw->paired, esw_i, esw, GFP_KERNEL);
2971 if (err)
2972 goto err_peer_xa;
2973
8611df72
SD		 2974 esw->num_peers++;
2975 peer_esw->num_peers++;
88d162b4 2976 mlx5_devcom_comp_set_ready(esw->devcom, true);
ac004b83
RD		 2977 break;
2978
2979 case ESW_OFFLOADS_DEVCOM_UNPAIR:
70c36438 2980 if (!esw_paired)
ac004b83
RD		 2981 break;
2982
8611df72
SD		 2983 peer_esw->num_peers--;
2984 esw->num_peers--;
2985 if (!esw->num_peers && !peer_esw->num_peers)
88d162b4 2986 mlx5_devcom_comp_set_ready(esw->devcom, false);
70c36438
RD		 2987 xa_erase(&peer_esw->paired, esw_i);
2988 xa_erase(&esw->paired, peer_esw_i);
ed7a8fe7
MB		 2989 mlx5_esw_offloads_unpair(peer_esw, esw);
2990 mlx5_esw_offloads_unpair(esw, peer_esw);
8463daf1 2991 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2992 break;
2993 }
2994
2995 return 0;
2996
70c36438
RD		 2997err_peer_xa:
2998 xa_erase(&esw->paired, peer_esw_i);
2999err_xa:
3000 mlx5_esw_offloads_unpair(peer_esw, esw);
ac004b83 3001err_pair:
ed7a8fe7 3002 mlx5_esw_offloads_unpair(esw, peer_esw);
8463daf1
MG		 3003err_peer:
3004 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 3005err_out:
3006 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
3007 event, err);
3008 return err;
3009}
3010
1161d22d 3011void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw, u64 key)
ac004b83 3012{
9be6c21f 3013 int i;
ac004b83 3014
9be6c21f
SD		 3015 for (i = 0; i < MLX5_MAX_PORTS; i++)
3016 INIT_LIST_HEAD(&esw->offloads.peer_flows[i]);
04de7dda
RD		 3017 mutex_init(&esw->offloads.peer_mutex);
3018
ac004b83
RD		 3019 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
3020 return;
3021
e2bb7984
RD		 3022 if ((MLX5_VPORT_MANAGER(esw->dev) || mlx5_core_is_ecpf_esw_manager(esw->dev)) &&
3023 !mlx5_lag_is_supported(esw->dev))
3008e6a0
MB		 3024 return;
3025
70c36438 3026 xa_init(&esw->paired);
8611df72 3027 esw->num_peers = 0;
88d162b4
RD		 3028 esw->devcom = mlx5_devcom_register_component(esw->dev->priv.devc,
3029 MLX5_DEVCOM_ESW_OFFLOADS,
1161d22d 3030 key,
88d162b4
RD		 3031 mlx5_esw_offloads_devcom_event,
3032 esw);
3033 if (IS_ERR_OR_NULL(esw->devcom))
3034 return;
3035
3036 mlx5_devcom_send_event(esw->devcom,
e2a82bf8 3037 ESW_OFFLOADS_DEVCOM_PAIR,
88d162b4
RD		 3038 ESW_OFFLOADS_DEVCOM_UNPAIR,
3039 esw);
ac004b83
RD		 3040}
3041
2be5bd42 3042void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
ac004b83 3043{
88d162b4 3044 if (IS_ERR_OR_NULL(esw->devcom))
ac004b83
RD		 3045 return;
3046
88d162b4
RD		 3047 mlx5_devcom_send_event(esw->devcom,
3048 ESW_OFFLOADS_DEVCOM_UNPAIR,
e2a82bf8 3049 ESW_OFFLOADS_DEVCOM_UNPAIR,
88d162b4 3050 esw);
ac004b83 3051
88d162b4 3052 mlx5_devcom_unregister_component(esw->devcom);
70c36438 3053 xa_destroy(&esw->paired);
88d162b4
RD		 3054 esw->devcom = NULL;
3055}
3056
3057bool mlx5_esw_offloads_devcom_is_ready(struct mlx5_eswitch *esw)
3058{
3059 return mlx5_devcom_comp_is_ready(esw->devcom);
ac004b83
RD		 3060}
3061
7bf481d7 3062bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
92ab1eb3
JL		 3063{
3064 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
3065 return false;
3066
3067 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
3068 MLX5_FDB_TO_VPORT_REG_C_0))
3069 return false;
3070
92ab1eb3
JL		 3071 return true;
3072}
3073
0b0ea3c5
SR		 3074#define MLX5_ESW_METADATA_RSVD_UPLINK 1
3075
3076/* Share the same metadata for uplink's. This is fine because:
3077 * (a) In shared FDB mode (LAG) both uplink's are treated the
3078 * same and tagged with the same metadata.
3079 * (b) In non shared FDB mode, packets from physical port0
3080 * cannot hit eswitch of PF1 and vice versa.
3081 */
3082static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw)
3083{
3084 return MLX5_ESW_METADATA_RSVD_UPLINK;
3085}
3086
133dcfc5
VP		 3087u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
3088{
7cd7becd 3089 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
4f4edcc2
AL		 3090 /* Reserve 0xf for internal port offload */
3091 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
7cd7becd 3092 u32 pf_num;
133dcfc5
VP		 3093 int id;
3094
7cd7becd 3095 /* Only 4 bits of pf_num */
2ec16ddd 3096 pf_num = mlx5_get_dev_index(esw->dev);
7cd7becd 3097 if (pf_num > max_pf_num)
3098 return 0;
133dcfc5 3099
7cd7becd 3100 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
0b0ea3c5
SR		 3101 /* Use only non-zero vport_id (2-4095) for all PF's */
3102 id = ida_alloc_range(&esw->offloads.vport_metadata_ida,
3103 MLX5_ESW_METADATA_RSVD_UPLINK + 1,
3104 vport_end_ida, GFP_KERNEL);
7cd7becd 3105 if (id < 0)
3106 return 0;
3107 id = (pf_num << ESW_VPORT_BITS) | id;
3108 return id;
133dcfc5
VP		 3109}
3110
3111void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
3112{
7cd7becd 3113 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
3114
3115 /* Metadata contains only 12 bits of actual ida id */
3116 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 3117}
3118
3119static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
3120 struct mlx5_vport *vport)
3121{
0b0ea3c5
SR		 3122 if (vport->vport == MLX5_VPORT_UPLINK)
3123 vport->default_metadata = mlx5_esw_match_metadata_reserved(esw);
3124 else
3125 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
3126
133dcfc5
VP		 3127 vport->metadata = vport->default_metadata;
3128 return vport->metadata ? 0 : -ENOSPC;
3129}
3130
3131static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
3132 struct mlx5_vport *vport)
3133{
406493a5 3134 if (!vport->default_metadata)
133dcfc5
VP		 3135 return;
3136
0b0ea3c5
SR		 3137 if (vport->vport == MLX5_VPORT_UPLINK)
3138 return;
3139
133dcfc5
VP		 3140 WARN_ON(vport->metadata != vport->default_metadata);
3141 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
3142}
3143
fc99c3d6
VP		 3144static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
3145{
3146 struct mlx5_vport *vport;
47dd7e60 3147 unsigned long i;
fc99c3d6
VP		 3148
3149 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3150 return;
3151
47dd7e60 3152 mlx5_esw_for_each_vport(esw, i, vport)
fc99c3d6
VP		 3153 esw_offloads_vport_metadata_cleanup(esw, vport);
3154}
3155
3156static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
3157{
3158 struct mlx5_vport *vport;
47dd7e60 3159 unsigned long i;
fc99c3d6 3160 int err;
fc99c3d6
VP		 3161
3162 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3163 return 0;
3164
47dd7e60 3165 mlx5_esw_for_each_vport(esw, i, vport) {
fc99c3d6
VP		 3166 err = esw_offloads_vport_metadata_setup(esw, vport);
3167 if (err)
3168 goto metadata_err;
3169 }
3170
3171 return 0;
3172
3173metadata_err:
3174 esw_offloads_metadata_uninit(esw);
3175 return err;
3176}
3177
748da30b 3178int
89a0f1fb
PP		 3179esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
3180 struct mlx5_vport *vport)
7445cfb1 3181{
7445cfb1
JL		 3182 int err;
3183
07bab950 3184 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 3185 if (err)
fc99c3d6 3186 return err;
7445cfb1 3187
2c40db2f
PP		 3188 err = esw_acl_egress_ofld_setup(esw, vport);
3189 if (err)
3190 goto egress_err;
07bab950
VP		 3191
3192 return 0;
3193
3194egress_err:
3195 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 3196 return err;
3197}
18486737 3198
748da30b 3199void
89a0f1fb
PP		 3200esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
3201 struct mlx5_vport *vport)
3202{
ea651a86 3203 esw_acl_egress_ofld_cleanup(vport);
07bab950 3204 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 3205}
7445cfb1 3206
748da30b 3207static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 3208{
3209 struct mlx5_vport *vport;
18486737 3210
748da30b 3211 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 3212 if (IS_ERR(vport))
3213 return PTR_ERR(vport);
3214
4e9a9ef7 3215 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 3216}
3217
748da30b 3218static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 3219{
786ef904 3220 struct mlx5_vport *vport;
7445cfb1 3221
748da30b 3222 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 3223 if (IS_ERR(vport))
3224 return;
3225
748da30b 3226 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 3227}
3228
db202995
MB		 3229int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw)
3230{
3231 struct mlx5_eswitch_rep *rep;
3232 unsigned long i;
3233 int ret;
3234
3235 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
3236 return 0;
3237
3238 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3239 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
3240 return 0;
3241
3242 ret = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3243 if (ret)
3244 return ret;
3245
3246 mlx5_esw_for_each_rep(esw, i, rep) {
3247 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
3248 mlx5_esw_offloads_rep_load(esw, rep->vport);
3249 }
3250
3251 return 0;
3252}
3253
062f4bf4 3254static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 3255{
34ca6535 3256 struct mlx5_esw_indir_table *indir;
6ed1803a
MB		 3257 int err;
3258
5c1d260e 3259 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 3260 mutex_init(&esw->fdb_table.offloads.vports.lock);
3261 hash_init(esw->fdb_table.offloads.vports.table);
7dc84de9 3262 atomic64_set(&esw->user_count, 0);
e52c2802 3263
34ca6535
VB		 3264 indir = mlx5_esw_indir_table_init();
3265 if (IS_ERR(indir)) {
3266 err = PTR_ERR(indir);
3267 goto create_indir_err;
3268 }
3269 esw->fdb_table.offloads.indir = indir;
3270
748da30b 3271 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 3272 if (err)
f8d1edda 3273 goto create_acl_err;
18486737 3274
8d6bd3c3 3275 err = esw_create_offloads_table(esw);
c930a3ad 3276 if (err)
11b717d6 3277 goto create_offloads_err;
c930a3ad 3278
11b717d6 3279 err = esw_create_restore_table(esw);
c930a3ad 3280 if (err)
11b717d6
PB		 3281 goto create_restore_err;
3282
0da3c12d 3283 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 3284 if (err)
3285 goto create_fdb_err;
c930a3ad 3286
8d6bd3c3 3287 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 3288 if (err)
3289 goto create_fg_err;
3290
8ea7bcf6
JL		 3291 err = esw_create_vport_rx_drop_group(esw);
3292 if (err)
3293 goto create_rx_drop_fg_err;
3294
3295 err = esw_create_vport_rx_drop_rule(esw);
3296 if (err)
3297 goto create_rx_drop_rule_err;
3298
c930a3ad
OG		 3299 return 0;
3300
8ea7bcf6
JL		 3301create_rx_drop_rule_err:
3302 esw_destroy_vport_rx_drop_group(esw);
3303create_rx_drop_fg_err:
3304 esw_destroy_vport_rx_group(esw);
c930a3ad 3305create_fg_err:
1967ce6e 3306 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 3307create_fdb_err:
11b717d6
PB		 3308 esw_destroy_restore_table(esw);
3309create_restore_err:
3310 esw_destroy_offloads_table(esw);
3311create_offloads_err:
748da30b 3312 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 3313create_acl_err:
34ca6535
VB		 3314 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3315create_indir_err:
f8d1edda 3316 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 3317 return err;
3318}
3319
eca8cc38
BW		 3320static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3321{
8ea7bcf6
JL		 3322 esw_destroy_vport_rx_drop_rule(esw);
3323 esw_destroy_vport_rx_drop_group(esw);
eca8cc38 3324 esw_destroy_vport_rx_group(esw);
eca8cc38 3325 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 3326 esw_destroy_restore_table(esw);
3327 esw_destroy_offloads_table(esw);
748da30b 3328 esw_destroy_uplink_offloads_acl_tables(esw);
34ca6535 3329 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
f8d1edda 3330 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 3331}
3332
7e736f9a
PP		 3333static void
3334esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 3335{
f1bc646c 3336 struct devlink *devlink;
5ccf2770 3337 bool host_pf_disabled;
7e736f9a 3338 u16 new_num_vfs;
a3888f33 3339
7e736f9a
PP		 3340 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3341 host_params_context.host_num_of_vfs);
5ccf2770
BW		 3342 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3343 host_params_context.host_pf_disabled);
a3888f33 3344
7e736f9a
PP		 3345 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3346 return;
a3888f33 3347
f1bc646c
MS		 3348 devlink = priv_to_devlink(esw->dev);
3349 devl_lock(devlink);
a3888f33 3350 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 3351 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 3352 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 3353 } else {
7e736f9a 3354 int err;
a3888f33 3355
23bb50cf
BW		 3356 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3357 MLX5_VPORT_UC_ADDR_CHANGE);
b868c8fe
DC		 3358 if (err) {
3359 devl_unlock(devlink);
7e736f9a 3360 return;
b868c8fe 3361 }
a3888f33 3362 }
7e736f9a 3363 esw->esw_funcs.num_vfs = new_num_vfs;
f1bc646c 3364 devl_unlock(devlink);
a3888f33
BW		 3365}
3366
7e736f9a 3367static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 3368{
7e736f9a
PP		 3369 struct mlx5_host_work *host_work;
3370 struct mlx5_eswitch *esw;
dd28087c 3371 const u32 *out;
ac35dcd6 3372
7e736f9a
PP		 3373 host_work = container_of(work, struct mlx5_host_work, work);
3374 esw = host_work->esw;
a3888f33 3375
dd28087c
PP		 3376 out = mlx5_esw_query_functions(esw->dev);
3377 if (IS_ERR(out))
7e736f9a 3378 goto out;
a3888f33 3379
7e736f9a 3380 esw_vfs_changed_event_handler(esw, out);
dd28087c 3381 kvfree(out);
a3888f33 3382out:
ac35dcd6
VP		 3383 kfree(host_work);
3384}
3385
16fff98a 3386int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 3387{
cd56f929 3388 struct mlx5_esw_functions *esw_funcs;
a3888f33 3389 struct mlx5_host_work *host_work;
a3888f33
BW		 3390 struct mlx5_eswitch *esw;
3391
3392 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3393 if (!host_work)
3394 return NOTIFY_DONE;
3395
cd56f929
VP		 3396 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3397 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 3398
3399 host_work->esw = esw;
3400
062f4bf4 3401 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 3402 queue_work(esw->work_queue, &host_work->work);
3403
3404 return NOTIFY_OK;
3405}
3406
a53cf949
PP		 3407static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3408{
3409 const u32 *query_host_out;
3410
3411 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3412 return 0;
3413
3414 query_host_out = mlx5_esw_query_functions(esw->dev);
3415 if (IS_ERR(query_host_out))
3416 return PTR_ERR(query_host_out);
3417
3418 /* Mark non local controller with non zero controller number. */
3419 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3420 host_params_context.host_number);
3421 kvfree(query_host_out);
3422 return 0;
3423}
3424
f1b9acd3
PP		 3425bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3426{
3427 /* Local controller is always valid */
3428 if (controller == 0)
3429 return true;
3430
3431 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3432 return false;
3433
3434 /* External host number starts with zero in device */
3435 return (controller == esw->offloads.host_number + 1);
3436}
3437
5896b972 3438int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 3439{
c9355682 3440 struct mapping_ctx *reg_c0_obj_pool;
3b83b6c2 3441 struct mlx5_vport *vport;
47dd7e60 3442 unsigned long i;
2198b932 3443 u64 mapping_id;
47dd7e60 3444 int err;
eca8cc38 3445
2bb72e7e 3446 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 3447 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 3448
a53cf949
PP		 3449 err = mlx5_esw_host_number_init(esw);
3450 if (err)
cd1ef966 3451 goto err_metadata;
a53cf949 3452
fc99c3d6
VP		 3453 err = esw_offloads_metadata_init(esw);
3454 if (err)
3455 goto err_metadata;
3456
332bd3a5
PP		 3457 err = esw_set_passing_vport_metadata(esw, true);
3458 if (err)
3459 goto err_vport_metadata;
c1286050 3460
2198b932
RD		 3461 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3462
3463 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3464 sizeof(struct mlx5_mapped_obj),
3465 ESW_REG_C0_USER_DATA_METADATA_MASK,
3466 true);
3467
c9355682
CM		 3468 if (IS_ERR(reg_c0_obj_pool)) {
3469 err = PTR_ERR(reg_c0_obj_pool);
3470 goto err_pool;
3471 }
3472 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3473
7983a675
PB		 3474 err = esw_offloads_steering_init(esw);
3475 if (err)
3476 goto err_steering_init;
3477
3b83b6c2
DL		 3478 /* Representor will control the vport link state */
3479 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3480 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
a7719b29
DJ		 3481 if (mlx5_core_ec_sriov_enabled(esw->dev))
3482 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs)
3483 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3b83b6c2 3484
c2d7712c 3485 /* Uplink vport rep must load first. */
ba3d85f0 3486 err = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
925a6acc 3487 if (err)
c2d7712c 3488 goto err_uplink;
c1286050 3489
c2d7712c 3490 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 3491 if (err)
c2d7712c 3492 goto err_vports;
eca8cc38 3493
eca8cc38
BW		 3494 return 0;
3495
925a6acc 3496err_vports:
ba3d85f0 3497 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
c2d7712c 3498err_uplink:
7983a675 3499 esw_offloads_steering_cleanup(esw);
79949985 3500err_steering_init:
c9355682
CM		 3501 mapping_destroy(reg_c0_obj_pool);
3502err_pool:
79949985 3503 esw_set_passing_vport_metadata(esw, false);
7983a675 3504err_vport_metadata:
fc99c3d6
VP		 3505 esw_offloads_metadata_uninit(esw);
3506err_metadata:
8463daf1 3507 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 3508 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 3509 return err;
3510}
3511
db7ff19e
EB		 3512static int esw_offloads_stop(struct mlx5_eswitch *esw,
3513 struct netlink_ext_ack *extack)
c930a3ad 3514{
e12de39c 3515 int err;
c930a3ad 3516
b6f2846a 3517 esw->mode = MLX5_ESWITCH_LEGACY;
2318b8bb
CM		 3518
3519 /* If changing from switchdev to legacy mode without sriov enabled,
3520 * no need to create legacy fdb.
3521 */
bea416c7 3522 if (!mlx5_core_is_pf(esw->dev) || !mlx5_sriov_is_enabled(esw->dev))
2318b8bb
CM		 3523 return 0;
3524
b6f2846a 3525 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
e12de39c 3526 if (err)
8c98ee77 3527 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
c930a3ad
OG		 3528
3529 return err;
3530}
3531
5896b972 3532void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 3533{
5896b972 3534 mlx5_eswitch_disable_pf_vf_vports(esw);
ba3d85f0 3535 mlx5_esw_offloads_rep_unload(esw, MLX5_VPORT_UPLINK);
332bd3a5 3536 esw_set_passing_vport_metadata(esw, false);
eca8cc38 3537 esw_offloads_steering_cleanup(esw);
c9355682 3538 mapping_destroy(esw->offloads.reg_c0_obj_pool);
fc99c3d6 3539 esw_offloads_metadata_uninit(esw);
8463daf1 3540 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 3541 mutex_destroy(&esw->offloads.termtbl_mutex);
c930a3ad
OG		 3542}
3543
ef78618b 3544static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 3545{
3546 switch (mode) {
3547 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 3548 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 3549 break;
3550 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 3551 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 3552 break;
3553 default:
3554 return -EINVAL;
3555 }
3556
3557 return 0;
3558}
3559
ef78618b
OG		 3560static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3561{
3562 switch (mlx5_mode) {
f6455de0 3563 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 3564 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3565 break;
f6455de0 3566 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 3567 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3568 break;
3569 default:
3570 return -EINVAL;
3571 }
3572
3573 return 0;
3574}
3575
bffaa916
RD		 3576static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3577{
3578 switch (mode) {
3579 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3580 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3581 break;
3582 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3583 *mlx5_mode = MLX5_INLINE_MODE_L2;
3584 break;
3585 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3586 *mlx5_mode = MLX5_INLINE_MODE_IP;
3587 break;
3588 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3589 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3590 break;
3591 default:
3592 return -EINVAL;
3593 }
3594
3595 return 0;
3596}
3597
3598static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3599{
3600 switch (mlx5_mode) {
3601 case MLX5_INLINE_MODE_NONE:
3602 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3603 break;
3604 case MLX5_INLINE_MODE_L2:
3605 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3606 break;
3607 case MLX5_INLINE_MODE_IP:
3608 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3609 break;
3610 case MLX5_INLINE_MODE_TCP_UDP:
3611 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3612 break;
3613 default:
3614 return -EINVAL;
3615 }
3616
3617 return 0;
3618}
3619
662404b2
GL		 3620static bool esw_offloads_devlink_ns_eq_netdev_ns(struct devlink *devlink)
3621{
3622 struct net *devl_net, *netdev_net;
3623 struct mlx5_eswitch *esw;
3624
3625 esw = mlx5_devlink_eswitch_get(devlink);
3626 netdev_net = dev_net(esw->dev->mlx5e_res.uplink_netdev);
3627 devl_net = devlink_net(devlink);
3628
3629 return net_eq(devl_net, netdev_net);
3630}
3631
366e4624
JL		 3632int mlx5_eswitch_block_mode_trylock(struct mlx5_core_dev *dev)
3633{
3634 struct devlink *devlink = priv_to_devlink(dev);
3635 struct mlx5_eswitch *esw;
3636 int err;
3637
3638 devl_lock(devlink);
3639 esw = mlx5_devlink_eswitch_get(devlink);
3640 if (IS_ERR(esw)) {
3641 /* Failure means no eswitch => not possible to change eswitch mode */
3642 devl_unlock(devlink);
3643 return 0;
3644 }
3645
3646 err = mlx5_esw_try_lock(esw);
3647 if (err < 0) {
3648 devl_unlock(devlink);
3649 return err;
3650 }
3651
3652 return 0;
3653}
3654
3655void mlx5_eswitch_block_mode_unlock(struct mlx5_core_dev *dev, int err)
3656{
3657 struct devlink *devlink = priv_to_devlink(dev);
3658 struct mlx5_eswitch *esw;
3659
3660 esw = mlx5_devlink_eswitch_get(devlink);
3661 if (IS_ERR(esw))
3662 return;
3663
3664 if (!err)
3665 esw->offloads.num_block_mode++;
3666 mlx5_esw_unlock(esw);
3667 devl_unlock(devlink);
3668}
3669
3670void mlx5_eswitch_unblock_mode_lock(struct mlx5_core_dev *dev)
3671{
3672 struct devlink *devlink = priv_to_devlink(dev);
3673 struct mlx5_eswitch *esw;
3674
3675 esw = mlx5_devlink_eswitch_get(devlink);
3676 if (IS_ERR(esw))
3677 return;
3678
3679 down_write(&esw->mode_lock);
3680}
3681
3682void mlx5_eswitch_unblock_mode_unlock(struct mlx5_core_dev *dev)
3683{
3684 struct devlink *devlink = priv_to_devlink(dev);
3685 struct mlx5_eswitch *esw;
3686
3687 esw = mlx5_devlink_eswitch_get(devlink);
3688 if (IS_ERR(esw))
3689 return;
3690
3691 esw->offloads.num_block_mode--;
3692 up_write(&esw->mode_lock);
3693}
3694
db7ff19e
EB		 3695int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3696 struct netlink_ext_ack *extack)
9d1cef19 3697{
9d1cef19 3698 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 3699 struct mlx5_eswitch *esw;
ea2128fd 3700 int err = 0;
9d1cef19 3701
bd939753
PP		 3702 esw = mlx5_devlink_eswitch_get(devlink);
3703 if (IS_ERR(esw))
3704 return PTR_ERR(esw);
9d1cef19 3705
ef78618b 3706 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 3707 return -EINVAL;
3708
662404b2
GL		 3709 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV &&
3710 !esw_offloads_devlink_ns_eq_netdev_ns(devlink)) {
3711 NL_SET_ERR_MSG_MOD(extack,
3712 "Can't change E-Switch mode to switchdev when netdev net namespace has diverged from the devlink's.");
3713 return -EPERM;
3714 }
3715
cac1eb2c 3716 mlx5_lag_disable_change(esw->dev);
7dc84de9
RD		 3717 err = mlx5_esw_try_lock(esw);
3718 if (err < 0) {
3719 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
cac1eb2c 3720 goto enable_lag;
7dc84de9
RD		 3721 }
3722 cur_mlx5_mode = err;
3723 err = 0;
3724
c930a3ad 3725 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 3726 goto unlock;
c930a3ad 3727
366e4624
JL		 3728 if (esw->offloads.num_block_mode) {
3729 NL_SET_ERR_MSG_MOD(extack,
3730 "Can't change eswitch mode when IPsec SA and/or policies are configured");
3731 err = -EOPNOTSUPP;
3732 goto unlock;
3733 }
3734
f019679e 3735 mlx5_eswitch_disable_locked(esw);
c85a6b8f
AL		 3736 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3737 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3738 NL_SET_ERR_MSG_MOD(extack,
3739 "Can't change mode while devlink traps are active");
3740 err = -EOPNOTSUPP;
3741 goto unlock;
3742 }
8e0aa4bc 3743 err = esw_offloads_start(esw, extack);
c85a6b8f 3744 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
8e0aa4bc 3745 err = esw_offloads_stop(esw, extack);
f019679e 3746 mlx5_rescan_drivers(esw->dev);
c85a6b8f 3747 } else {
8e0aa4bc 3748 err = -EINVAL;
c85a6b8f 3749 }
8e0aa4bc
PP		 3750
3751unlock:
7dc84de9 3752 mlx5_esw_unlock(esw);
cac1eb2c
MB		 3753enable_lag:
3754 mlx5_lag_enable_change(esw->dev);
8e0aa4bc 3755 return err;
feae9087
OG		 3756}
3757
3758int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3759{
bd939753 3760 struct mlx5_eswitch *esw;
9d1cef19 3761 int err;
c930a3ad 3762
bd939753
PP		 3763 esw = mlx5_devlink_eswitch_get(devlink);
3764 if (IS_ERR(esw))
3765 return PTR_ERR(esw);
c930a3ad 3766
efb4879f 3767 down_read(&esw->mode_lock);
8e0aa4bc 3768 err = esw_mode_to_devlink(esw->mode, mode);
efb4879f 3769 up_read(&esw->mode_lock);
8e0aa4bc 3770 return err;
feae9087 3771}
127ea380 3772
47dd7e60
PP		 3773static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3774 struct netlink_ext_ack *extack)
3775{
3776 struct mlx5_core_dev *dev = esw->dev;
3777 struct mlx5_vport *vport;
3778 u16 err_vport_num = 0;
3779 unsigned long i;
3780 int err = 0;
3781
3782 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3783 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3784 if (err) {
3785 err_vport_num = vport->vport;
3786 NL_SET_ERR_MSG_MOD(extack,
3787 "Failed to set min inline on vport");
3788 goto revert_inline_mode;
3789 }
3790 }
a7719b29
DJ		 3791 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
3792 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3793 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3794 if (err) {
3795 err_vport_num = vport->vport;
3796 NL_SET_ERR_MSG_MOD(extack,
3797 "Failed to set min inline on vport");
3798 goto revert_ec_vf_inline_mode;
3799 }
3800 }
3801 }
47dd7e60
PP		 3802 return 0;
3803
a7719b29
DJ		 3804revert_ec_vf_inline_mode:
3805 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3806 if (vport->vport == err_vport_num)
3807 break;
3808 mlx5_modify_nic_vport_min_inline(dev,
3809 vport->vport,
3810 esw->offloads.inline_mode);
3811 }
47dd7e60
PP		 3812revert_inline_mode:
3813 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3814 if (vport->vport == err_vport_num)
3815 break;
3816 mlx5_modify_nic_vport_min_inline(dev,
3817 vport->vport,
3818 esw->offloads.inline_mode);
3819 }
3820 return err;
3821}
3822
db7ff19e
EB		 3823int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3824 struct netlink_ext_ack *extack)
bffaa916
RD		 3825{
3826 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3827 struct mlx5_eswitch *esw;
bffaa916 3828 u8 mlx5_mode;
47dd7e60 3829 int err;
bffaa916 3830
bd939753
PP		 3831 esw = mlx5_devlink_eswitch_get(devlink);
3832 if (IS_ERR(esw))
3833 return PTR_ERR(esw);
bffaa916 3834
367dfa12 3835 down_write(&esw->mode_lock);
ae24432c 3836
c415f704
OG		 3837 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3838 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
bcd68c04
JC		 3839 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3840 err = 0;
8e0aa4bc 3841 goto out;
bcd68c04
JC		 3842 }
3843
c8b838d1 3844 fallthrough;
c415f704 3845 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 3846 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 3847 err = -EOPNOTSUPP;
3848 goto out;
c415f704
OG		 3849 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3850 break;
3851 }
bffaa916 3852
525e84be 3853 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3854 NL_SET_ERR_MSG_MOD(extack,
3855 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 3856 err = -EOPNOTSUPP;
3857 goto out;
375f51e2
RD		 3858 }
3859
bffaa916
RD		 3860 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3861 if (err)
3862 goto out;
3863
47dd7e60
PP		 3864 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3865 if (err)
3866 goto out;
bffaa916
RD		 3867
3868 esw->offloads.inline_mode = mlx5_mode;
367dfa12 3869 up_write(&esw->mode_lock);
bffaa916
RD		 3870 return 0;
3871
bffaa916 3872out:
367dfa12 3873 up_write(&esw->mode_lock);
bffaa916
RD		 3874 return err;
3875}
3876
3877int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3878{
bd939753 3879 struct mlx5_eswitch *esw;
9d1cef19 3880 int err;
bffaa916 3881
bd939753
PP		 3882 esw = mlx5_devlink_eswitch_get(devlink);
3883 if (IS_ERR(esw))
3884 return PTR_ERR(esw);
bffaa916 3885
efb4879f 3886 down_read(&esw->mode_lock);
8e0aa4bc 3887 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
efb4879f 3888 up_read(&esw->mode_lock);
8e0aa4bc 3889 return err;
bffaa916
RD		 3890}
3891
acc10929
LR		 3892bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev)
3893{
3894 struct devlink *devlink = priv_to_devlink(dev);
3895 struct mlx5_eswitch *esw;
3896
3897 devl_lock(devlink);
3898 esw = mlx5_devlink_eswitch_get(devlink);
3899 if (IS_ERR(esw)) {
3900 devl_unlock(devlink);
3901 /* Failure means no eswitch => not possible to change encap */
3902 return true;
3903 }
3904
3905 down_write(&esw->mode_lock);
3906 if (esw->mode != MLX5_ESWITCH_LEGACY &&
3907 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
3908 up_write(&esw->mode_lock);
3909 devl_unlock(devlink);
3910 return false;
3911 }
3912
3913 esw->offloads.num_block_encap++;
3914 up_write(&esw->mode_lock);
3915 devl_unlock(devlink);
3916 return true;
3917}
3918
3919void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
3920{
3921 struct devlink *devlink = priv_to_devlink(dev);
3922 struct mlx5_eswitch *esw;
3923
3924 esw = mlx5_devlink_eswitch_get(devlink);
3925 if (IS_ERR(esw))
3926 return;
3927
3928 down_write(&esw->mode_lock);
3929 esw->offloads.num_block_encap--;
3930 up_write(&esw->mode_lock);
3931}
3932
98fdbea5
LR		 3933int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3934 enum devlink_eswitch_encap_mode encap,
db7ff19e 3935 struct netlink_ext_ack *extack)
7768d197
RD		 3936{
3937 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3938 struct mlx5_eswitch *esw;
f019679e 3939 int err = 0;
7768d197 3940
bd939753
PP		 3941 esw = mlx5_devlink_eswitch_get(devlink);
3942 if (IS_ERR(esw))
3943 return PTR_ERR(esw);
7768d197 3944
367dfa12 3945 down_write(&esw->mode_lock);
ae24432c 3946
7768d197 3947 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 3948 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 3949 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3950 err = -EOPNOTSUPP;
3951 goto unlock;
3952 }
7768d197 3953
8e0aa4bc
PP		 3954 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3955 err = -EOPNOTSUPP;
3956 goto unlock;
3957 }
7768d197 3958
f6455de0 3959 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 3960 esw->offloads.encap = encap;
8e0aa4bc 3961 goto unlock;
7768d197
RD		 3962 }
3963
3964 if (esw->offloads.encap == encap)
8e0aa4bc 3965 goto unlock;
7768d197 3966
525e84be 3967 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3968 NL_SET_ERR_MSG_MOD(extack,
3969 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 3970 err = -EOPNOTSUPP;
3971 goto unlock;
7768d197
RD		 3972 }
3973
acc10929
LR		 3974 if (esw->offloads.num_block_encap) {
3975 NL_SET_ERR_MSG_MOD(extack,
3976 "Can't set encapsulation when IPsec SA and/or policies are configured");
3977 err = -EOPNOTSUPP;
3978 goto unlock;
3979 }
3980
e52c2802 3981 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 3982
3983 esw->offloads.encap = encap;
e52c2802 3984
0da3c12d 3985 err = esw_create_offloads_fdb_tables(esw);
e52c2802 3986
7768d197 3987 if (err) {
8c98ee77
EB		 3988 NL_SET_ERR_MSG_MOD(extack,
3989 "Failed re-creating fast FDB table");
7768d197 3990 esw->offloads.encap = !encap;
0da3c12d 3991 (void)esw_create_offloads_fdb_tables(esw);
7768d197 3992 }
e52c2802 3993
8e0aa4bc 3994unlock:
367dfa12 3995 up_write(&esw->mode_lock);
7768d197
RD		 3996 return err;
3997}
3998
98fdbea5
LR		 3999int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
4000 enum devlink_eswitch_encap_mode *encap)
7768d197 4001{
bd939753 4002 struct mlx5_eswitch *esw;
7768d197 4003
bd939753
PP		 4004 esw = mlx5_devlink_eswitch_get(devlink);
4005 if (IS_ERR(esw))
4006 return PTR_ERR(esw);
4007
efb4879f 4008 down_read(&esw->mode_lock);
7768d197 4009 *encap = esw->offloads.encap;
efb4879f 4010 up_read(&esw->mode_lock);
f019679e 4011 return 0;
7768d197
RD		 4012}
4013
c2d7712c
BW		 4014static bool
4015mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
4016{
4017 /* Currently, only ECPF based device has representor for host PF. */
4018 if (vport_num == MLX5_VPORT_PF &&
4019 !mlx5_core_is_ecpf_esw_manager(esw->dev))
4020 return false;
4021
4022 if (vport_num == MLX5_VPORT_ECPF &&
4023 !mlx5_ecpf_vport_exists(esw->dev))
4024 return false;
4025
4026 return true;
4027}
4028
f8e8fa02 4029void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 4030 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 4031 u8 rep_type)
127ea380 4032{
8693115a 4033 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02 4034 struct mlx5_eswitch_rep *rep;
47dd7e60 4035 unsigned long i;
9deb2241 4036
8693115a 4037 esw->offloads.rep_ops[rep_type] = ops;
47dd7e60
PP		 4038 mlx5_esw_for_each_rep(esw, i, rep) {
4039 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
59c904c8 4040 rep->esw = esw;
c2d7712c
BW		 4041 rep_data = &rep->rep_data[rep_type];
4042 atomic_set(&rep_data->state, REP_REGISTERED);
4043 }
f8e8fa02 4044 }
127ea380 4045}
f8e8fa02 4046EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 4047
f8e8fa02 4048void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 4049{
cb67b832 4050 struct mlx5_eswitch_rep *rep;
47dd7e60 4051 unsigned long i;
cb67b832 4052
f6455de0 4053 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 4054 __unload_reps_all_vport(esw, rep_type);
127ea380 4055
47dd7e60 4056 mlx5_esw_for_each_rep(esw, i, rep)
8693115a 4057 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 4058}
f8e8fa02 4059EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 4060
a4b97ab4 4061void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 4062{
726293f1
HHZ		 4063 struct mlx5_eswitch_rep *rep;
4064
879c8f84 4065 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 4066 return rep->rep_data[rep_type].priv;
726293f1 4067}
22215908
MB		 4068
4069void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 4070 u16 vport,
22215908
MB		 4071 u8 rep_type)
4072{
22215908
MB		 4073 struct mlx5_eswitch_rep *rep;
4074
879c8f84 4075 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 4076
8693115a
PP		 4077 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
4078 esw->offloads.rep_ops[rep_type]->get_proto_dev)
4079 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 4080 return NULL;
4081}
57cbd893 4082EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 4083
4084void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
4085{
879c8f84 4086 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 4087}
57cbd893
MB		 4088EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
4089
4090struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 4091 u16 vport)
57cbd893 4092{
879c8f84 4093 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 4094}
4095EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c 4096
5b7cb745
PB		 4097bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
4098{
4099 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
4100}
4101EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
4102
7445cfb1
JL		 4103bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
4104{
4105 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
4106}
4107EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
4108
0f0d3827 4109u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 4110 u16 vport_num)
4111{
133dcfc5 4112 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 4113
133dcfc5
VP		 4114 if (WARN_ON_ONCE(IS_ERR(vport)))
4115 return 0;
0f0d3827 4116
133dcfc5 4117 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 4118}
4119EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 4120
4121int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
f1b9acd3 4122 u16 vport_num, u32 controller, u32 sfnum)
d970812b
PP		 4123{
4124 int err;
4125
4126 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
4127 if (err)
4128 return err;
4129
f1b9acd3 4130 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
d970812b
PP		 4131 if (err)
4132 goto devlink_err;
4133
4134 err = mlx5_esw_offloads_rep_load(esw, vport_num);
4135 if (err)
4136 goto rep_err;
4137 return 0;
4138
4139rep_err:
4140 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
4141devlink_err:
4142 mlx5_esw_vport_disable(esw, vport_num);
4143 return err;
4144}
4145
4146void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
4147{
4148 mlx5_esw_offloads_rep_unload(esw, vport_num);
4149 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
4150 mlx5_esw_vport_disable(esw, vport_num);
4151}
84ae9c1f
VB		 4152
4153static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
4154{
4155 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4156 void *query_ctx;
4157 void *hca_caps;
4158 int err;
4159
4160 *vhca_id = 0;
84ae9c1f
VB		 4161
4162 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4163 if (!query_ctx)
4164 return -ENOMEM;
4165
47d0c500 4166 err = mlx5_vport_get_other_func_general_cap(esw->dev, vport_num, query_ctx);
84ae9c1f
VB		 4167 if (err)
4168 goto out_free;
4169
4170 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
4171 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
4172
4173out_free:
4174 kfree(query_ctx);
4175 return err;
4176}
4177
4178int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
4179{
4180 u16 *old_entry, *vhca_map_entry, vhca_id;
4181 int err;
4182
4183 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
4184 if (err) {
4185 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
4186 vport_num, err);
4187 return err;
4188 }
4189
4190 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
4191 if (!vhca_map_entry)
4192 return -ENOMEM;
4193
4194 *vhca_map_entry = vport_num;
4195 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
4196 if (xa_is_err(old_entry)) {
4197 kfree(vhca_map_entry);
4198 return xa_err(old_entry);
4199 }
4200 kfree(old_entry);
4201 return 0;
4202}
4203
4204void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
4205{
4206 u16 *vhca_map_entry, vhca_id;
4207 int err;
4208
4209 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
4210 if (err)
4211 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
4212 vport_num, err);
4213
4214 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
4215 kfree(vhca_map_entry);
4216}
4217
4218int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
4219{
4220 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
4221
4222 if (!res)
4223 return -ENOENT;
4224
4225 *vport_num = *res;
4226 return 0;
4227}
10742efc
VB		 4228
4229u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
4230 u16 vport_num)
4231{
4232 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4233
4234 if (WARN_ON_ONCE(IS_ERR(vport)))
4235 return 0;
4236
4237 return vport->metadata;
4238}
4239EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
e9d491a6
PP		 4240
4241static bool
4242is_port_function_supported(struct mlx5_eswitch *esw, u16 vport_num)
4243{
4244 return vport_num == MLX5_VPORT_PF ||
4245 mlx5_eswitch_is_vf_vport(esw, vport_num) ||
4246 mlx5_esw_is_sf_vport(esw, vport_num);
4247}
4248
71c93e37
JP		 4249int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
4250 u8 *hw_addr, int *hw_addr_len,
4251 struct netlink_ext_ack *extack)
e9d491a6
PP		 4252{
4253 struct mlx5_eswitch *esw;
4254 struct mlx5_vport *vport;
4255 u16 vport_num;
4256
4257 esw = mlx5_devlink_eswitch_get(port->devlink);
4258 if (IS_ERR(esw))
4259 return PTR_ERR(esw);
4260
4261 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4262 if (!is_port_function_supported(esw, vport_num))
4263 return -EOPNOTSUPP;
4264
4265 vport = mlx5_eswitch_get_vport(esw, vport_num);
4266 if (IS_ERR(vport)) {
4267 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4268 return PTR_ERR(vport);
4269 }
4270
4271 mutex_lock(&esw->state_lock);
4272 ether_addr_copy(hw_addr, vport->info.mac);
4273 *hw_addr_len = ETH_ALEN;
4274 mutex_unlock(&esw->state_lock);
4275 return 0;
4276}
4277
71c93e37
JP		 4278int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
4279 const u8 *hw_addr, int hw_addr_len,
4280 struct netlink_ext_ack *extack)
e9d491a6
PP		 4281{
4282 struct mlx5_eswitch *esw;
4283 u16 vport_num;
4284
4285 esw = mlx5_devlink_eswitch_get(port->devlink);
4286 if (IS_ERR(esw)) {
4287 NL_SET_ERR_MSG_MOD(extack, "Eswitch doesn't support set hw_addr");
4288 return PTR_ERR(esw);
4289 }
4290
4291 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4292 if (!is_port_function_supported(esw, vport_num)) {
4293 NL_SET_ERR_MSG_MOD(extack, "Port doesn't support set hw_addr");
4294 return -EINVAL;
4295 }
4296
4297 return mlx5_eswitch_set_vport_mac(esw, vport_num, hw_addr);
4298}
7db98396
YH		 4299
4300static struct mlx5_vport *
4301mlx5_devlink_port_fn_get_vport(struct devlink_port *port, struct mlx5_eswitch *esw)
4302{
4303 u16 vport_num;
4304
4305 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
4306 return ERR_PTR(-EOPNOTSUPP);
4307
4308 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4309 if (!is_port_function_supported(esw, vport_num))
4310 return ERR_PTR(-EOPNOTSUPP);
4311
4312 return mlx5_eswitch_get_vport(esw, vport_num);
4313}
4314
e5b9642a
SD		 4315int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
4316 struct netlink_ext_ack *extack)
4317{
4318 struct mlx5_eswitch *esw;
4319 struct mlx5_vport *vport;
e5b9642a
SD		 4320
4321 esw = mlx5_devlink_eswitch_get(port->devlink);
4322 if (IS_ERR(esw))
4323 return PTR_ERR(esw);
4324
4325 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4326 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
550449d8 4327 return -EOPNOTSUPP;
e5b9642a
SD		 4328 }
4329
4330 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4331 if (IS_ERR(vport)) {
4332 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4333 return PTR_ERR(vport);
4334 }
4335
4336 mutex_lock(&esw->state_lock);
550449d8 4337 *is_enabled = vport->info.mig_enabled;
e5b9642a 4338 mutex_unlock(&esw->state_lock);
550449d8 4339 return 0;
e5b9642a
SD		 4340}
4341
4342int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
4343 struct netlink_ext_ack *extack)
4344{
4345 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4346 struct mlx5_eswitch *esw;
4347 struct mlx5_vport *vport;
4348 void *query_ctx;
4349 void *hca_caps;
4350 int err = -EOPNOTSUPP;
4351
4352 esw = mlx5_devlink_eswitch_get(port->devlink);
4353 if (IS_ERR(esw))
4354 return PTR_ERR(esw);
4355
4356 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4357 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4358 return err;
4359 }
4360
4361 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4362 if (IS_ERR(vport)) {
4363 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4364 return PTR_ERR(vport);
4365 }
4366
4367 mutex_lock(&esw->state_lock);
e5b9642a
SD		 4368
4369 if (vport->info.mig_enabled == enable) {
4370 err = 0;
4371 goto out;
4372 }
4373
4374 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4375 if (!query_ctx) {
4376 err = -ENOMEM;
4377 goto out;
4378 }
4379
4380 err = mlx5_vport_get_other_func_cap(esw->dev, vport->vport, query_ctx,
4381 MLX5_CAP_GENERAL_2);
4382 if (err) {
4383 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4384 goto out_free;
4385 }
4386
4387 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
0507f2c8 4388 MLX5_SET(cmd_hca_cap_2, hca_caps, migratable, enable);
e5b9642a
SD		 4389
4390 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport->vport,
4391 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4392 if (err) {
4393 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA migratable cap");
4394 goto out_free;
4395 }
4396
4397 vport->info.mig_enabled = enable;
4398
4399out_free:
4400 kfree(query_ctx);
4401out:
4402 mutex_unlock(&esw->state_lock);
4403 return err;
4404}
4405
7db98396
YH		 4406int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
4407 struct netlink_ext_ack *extack)
4408{
4409 struct mlx5_eswitch *esw;
4410 struct mlx5_vport *vport;
7db98396
YH		 4411
4412 esw = mlx5_devlink_eswitch_get(port->devlink);
4413 if (IS_ERR(esw))
4414 return PTR_ERR(esw);
4415
4416 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4417 if (IS_ERR(vport)) {
4418 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4419 return PTR_ERR(vport);
4420 }
4421
4422 mutex_lock(&esw->state_lock);
550449d8 4423 *is_enabled = vport->info.roce_enabled;
7db98396 4424 mutex_unlock(&esw->state_lock);
550449d8 4425 return 0;
7db98396
YH		 4426}
4427
4428int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
4429 struct netlink_ext_ack *extack)
4430{
4431 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4432 struct mlx5_eswitch *esw;
4433 struct mlx5_vport *vport;
7db98396
YH		 4434 void *query_ctx;
4435 void *hca_caps;
4436 u16 vport_num;
550449d8 4437 int err;
7db98396
YH		 4438
4439 esw = mlx5_devlink_eswitch_get(port->devlink);
4440 if (IS_ERR(esw))
4441 return PTR_ERR(esw);
4442
4443 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4444 if (IS_ERR(vport)) {
4445 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4446 return PTR_ERR(vport);
4447 }
4448 vport_num = vport->vport;
4449
4450 mutex_lock(&esw->state_lock);
7db98396
YH		 4451
4452 if (vport->info.roce_enabled == enable) {
4453 err = 0;
4454 goto out;
4455 }
4456
4457 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4458 if (!query_ctx) {
4459 err = -ENOMEM;
4460 goto out;
4461 }
4462
4463 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4464 MLX5_CAP_GENERAL);
4465 if (err) {
4466 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4467 goto out_free;
4468 }
4469
4470 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
7db98396
YH		 4471 MLX5_SET(cmd_hca_cap, hca_caps, roce, enable);
4472
4473 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4474 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
4475 if (err) {
4476 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap");
4477 goto out_free;
4478 }
4479
4480 vport->info.roce_enabled = enable;
4481
4482out_free:
4483 kfree(query_ctx);
4484out:
4485 mutex_unlock(&esw->state_lock);
4486 return err;
4487}
d1569537
JL		 4488
4489int
4490mlx5_eswitch_restore_ipsec_rule(struct mlx5_eswitch *esw, struct mlx5_flow_handle *rule,
4491 struct mlx5_esw_flow_attr *esw_attr, int attr_idx)
4492{
4493 struct mlx5_flow_destination new_dest = {};
4494 struct mlx5_flow_destination old_dest = {};
4495
4496 if (!esw_setup_uplink_fwd_ipsec_needed(esw, esw_attr, attr_idx))
4497 return 0;
4498
4499 esw_setup_dest_fwd_ipsec(&old_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4500 esw_setup_dest_fwd_vport(&new_dest, NULL, esw, esw_attr, attr_idx, 0, false);
4501
4502 return mlx5_modify_rule_destination(rule, &new_dest, &old_dest);
4503}
Linux 6.x block layer and io_uring tree(s)