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net/mlx5e: E-Switch, Add peer fdb miss rules for vport manager or ecpf
[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
34ca6535 41#include "esw/indir_table.h"
ea651a86 42#include "esw/acl/ofld.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
ae430332 48#include "lib/fs_chains.h"
c620b772 49#include "en_tc.h"
c9355682 50#include "en/mapping.h"
c85a6b8f 51#include "devlink.h"
94db3317 52#include "lag/lag.h"
6fda078d 53#include "en/tc/post_meter.h"
69697b6e 54
47dd7e60
PP		 55#define mlx5_esw_for_each_rep(esw, i, rep) \
56 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
57
cd7e4186
BW		 58/* There are two match-all miss flows, one for unicast dst mac and
59 * one for multicast.
60 */
61#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 62#define UPLINK_REP_INDEX 0
63
c796bb7c
CM		 64#define MLX5_ESW_VPORT_TBL_SIZE 128
65#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
66
8ea7bcf6
JL		 67#define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
68
fd745f4c 69static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
c796bb7c
CM		 70 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
71 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
72 .flags = 0,
73};
74
879c8f84
BW		 75static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
76 u16 vport_num)
77{
47dd7e60 78 return xa_load(&esw->offloads.vport_reps, vport_num);
879c8f84
BW		 79}
80
6f7bbad1
JL		 81static void
82mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
83 struct mlx5_flow_spec *spec,
84 struct mlx5_esw_flow_attr *attr)
85{
166f431e
AL		 86 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) || !attr || !attr->in_rep)
87 return;
88
89 if (attr->int_port) {
90 spec->flow_context.flow_source = mlx5e_tc_int_port_get_flow_source(attr->int_port);
91
92 return;
93 }
94
95 spec->flow_context.flow_source = (attr->in_rep->vport == MLX5_VPORT_UPLINK) ?
96 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
97 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 98}
b7826076 99
f94d6389
CM		 100/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
101 * are not needed as well in the following process. So clear them all for simplicity.
102 */
103void
104mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
105{
106 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
107 void *misc2;
108
109 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
110 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
111
112 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
113 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
114
115 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
116 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
117 }
118}
119
c01cfd0f
JL		 120static void
121mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
122 struct mlx5_flow_spec *spec,
a508728a 123 struct mlx5_flow_attr *attr,
b055ecf5
MB		 124 struct mlx5_eswitch *src_esw,
125 u16 vport)
c01cfd0f 126{
166f431e
AL		 127 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
128 u32 metadata;
c01cfd0f
JL		 129 void *misc2;
130 void *misc;
131
132 /* Use metadata matching because vport is not represented by single
133 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
134 */
135 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
a508728a
VB		 136 if (mlx5_esw_indir_table_decap_vport(attr))
137 vport = mlx5_esw_indir_table_decap_vport(attr);
166f431e 138
e0bf81bf 139 if (!attr->chain && esw_attr && esw_attr->int_port)
166f431e
AL		 140 metadata =
141 mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
142 else
143 metadata =
144 mlx5_eswitch_get_vport_metadata_for_match(src_esw, vport);
145
c01cfd0f 146 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
166f431e 147 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata);
c01cfd0f
JL		 148
149 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 150 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
151 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 152
153 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 154 } else {
155 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 156 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 157
158 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
159 MLX5_SET(fte_match_set_misc, misc,
160 source_eswitch_owner_vhca_id,
b055ecf5 161 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 162
163 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
164 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
165 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
166 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
167 source_eswitch_owner_vhca_id);
168
169 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
170 }
c01cfd0f
JL		 171}
172
a508728a
VB		 173static int
174esw_setup_decap_indir(struct mlx5_eswitch *esw,
521933cd 175 struct mlx5_flow_attr *attr)
a508728a
VB		 176{
177 struct mlx5_flow_table *ft;
178
e5d4e1da 179 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
a508728a
VB		 180 return -EOPNOTSUPP;
181
521933cd 182 ft = mlx5_esw_indir_table_get(esw, attr,
a508728a
VB		 183 mlx5_esw_indir_table_decap_vport(attr), true);
184 return PTR_ERR_OR_ZERO(ft);
185}
186
9e51c0a6 187static void
a508728a
VB		 188esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
189 struct mlx5_flow_attr *attr)
190{
191 if (mlx5_esw_indir_table_decap_vport(attr))
521933cd 192 mlx5_esw_indir_table_put(esw,
a508728a
VB		 193 mlx5_esw_indir_table_decap_vport(attr),
194 true);
195}
196
6fda078d
OS		 197static int
198esw_setup_mtu_dest(struct mlx5_flow_destination *dest,
199 struct mlx5e_meter_attr *meter,
200 int i)
201{
202 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_RANGE;
203 dest[i].range.field = MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN;
204 dest[i].range.min = 0;
205 dest[i].range.max = meter->params.mtu;
206 dest[i].range.hit_ft = mlx5e_post_meter_get_mtu_true_ft(meter->post_meter);
207 dest[i].range.miss_ft = mlx5e_post_meter_get_mtu_false_ft(meter->post_meter);
208
209 return 0;
210}
211
f94d6389
CM		 212static int
213esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
214 struct mlx5_flow_act *flow_act,
eeed226e 215 u32 sampler_id,
f94d6389
CM		 216 int i)
217{
218 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
219 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
eeed226e 220 dest[i].sampler_id = sampler_id;
f94d6389
CM		 221
222 return 0;
223}
224
a508728a 225static int
9e51c0a6
VB		 226esw_setup_ft_dest(struct mlx5_flow_destination *dest,
227 struct mlx5_flow_act *flow_act,
a508728a 228 struct mlx5_eswitch *esw,
9e51c0a6
VB		 229 struct mlx5_flow_attr *attr,
230 int i)
231{
232 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
233 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
234 dest[i].ft = attr->dest_ft;
a508728a
VB		 235
236 if (mlx5_esw_indir_table_decap_vport(attr))
521933cd 237 return esw_setup_decap_indir(esw, attr);
a508728a 238 return 0;
9e51c0a6
VB		 239}
240
241static void
c0063a43
VB		 242esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
243 struct mlx5_fs_chains *chains, int i)
9e51c0a6 244{
2a2c84fa
RD		 245 if (mlx5_chains_ignore_flow_level_supported(chains))
246 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
9e51c0a6
VB		 247 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
248 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
249}
250
c0063a43
VB		 251static void
252esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
253 struct mlx5_eswitch *esw, int i)
254{
255 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))
256 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
257 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
dcf19b9c 258 dest[i].ft = mlx5_eswitch_get_slow_fdb(esw);
c0063a43
VB		 259}
260
9e51c0a6
VB		 261static int
262esw_setup_chain_dest(struct mlx5_flow_destination *dest,
263 struct mlx5_flow_act *flow_act,
264 struct mlx5_fs_chains *chains,
265 u32 chain, u32 prio, u32 level,
266 int i)
267{
268 struct mlx5_flow_table *ft;
269
270 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
271 ft = mlx5_chains_get_table(chains, chain, prio, level);
272 if (IS_ERR(ft))
273 return PTR_ERR(ft);
274
275 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
276 dest[i].ft = ft;
277 return 0;
278}
279
10742efc
VB		 280static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
281 int from, int to)
282{
283 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
284 struct mlx5_fs_chains *chains = esw_chains(esw);
285 int i;
286
287 for (i = from; i < to; i++)
288 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
289 mlx5_chains_put_table(chains, 0, 1, 0);
a508728a
VB		 290 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
291 esw_attr->dests[i].mdev))
521933cd 292 mlx5_esw_indir_table_put(esw, esw_attr->dests[i].rep->vport,
a508728a 293 false);
10742efc
VB		 294}
295
296static bool
297esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
298{
299 int i;
300
301 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
302 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
303 return true;
304 return false;
305}
306
307static int
308esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
309 struct mlx5_flow_act *flow_act,
310 struct mlx5_eswitch *esw,
311 struct mlx5_fs_chains *chains,
312 struct mlx5_flow_attr *attr,
313 int *i)
314{
315 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
de31854e 316 int err;
10742efc 317
e5d4e1da 318 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
10742efc
VB		 319 return -EOPNOTSUPP;
320
de31854e
DC		 321 /* flow steering cannot handle more than one dest with the same ft
322 * in a single flow
323 */
324 if (esw_attr->out_count - esw_attr->split_count > 1)
325 return -EOPNOTSUPP;
326
327 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
328 if (err)
329 return err;
27484f71 330
de31854e
DC		 331 if (esw_attr->dests[esw_attr->split_count].pkt_reformat) {
332 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
333 flow_act->pkt_reformat = esw_attr->dests[esw_attr->split_count].pkt_reformat;
10742efc 334 }
de31854e 335 (*i)++;
10742efc 336
de31854e 337 return 0;
10742efc
VB		 338}
339
340static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
341 struct mlx5_flow_attr *attr)
342{
343 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
344
345 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
346}
347
a508728a
VB		 348static bool
349esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
350{
351 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
e219440d 352 bool result = false;
a508728a
VB		 353 int i;
354
e219440d
MD		 355 /* Indirect table is supported only for flows with in_port uplink
356 * and the destination is vport on the same eswitch as the uplink,
357 * return false in case at least one of destinations doesn't meet
358 * this criteria.
359 */
360 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
27484f71
AL		 361 if (esw_attr->dests[i].rep &&
362 mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
e219440d
MD		 363 esw_attr->dests[i].mdev)) {
364 result = true;
365 } else {
366 result = false;
367 break;
368 }
369 }
370 return result;
a508728a
VB		 371}
372
373static int
374esw_setup_indir_table(struct mlx5_flow_destination *dest,
375 struct mlx5_flow_act *flow_act,
376 struct mlx5_eswitch *esw,
377 struct mlx5_flow_attr *attr,
a508728a
VB		 378 bool ignore_flow_lvl,
379 int *i)
380{
381 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
382 int j, err;
383
e5d4e1da 384 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
a508728a
VB		 385 return -EOPNOTSUPP;
386
387 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
388 if (ignore_flow_lvl)
389 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
390 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
391
521933cd 392 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,
a508728a
VB		 393 esw_attr->dests[j].rep->vport, false);
394 if (IS_ERR(dest[*i].ft)) {
395 err = PTR_ERR(dest[*i].ft);
396 goto err_indir_tbl_get;
397 }
398 }
399
400 if (mlx5_esw_indir_table_decap_vport(attr)) {
521933cd 401 err = esw_setup_decap_indir(esw, attr);
a508728a
VB		 402 if (err)
403 goto err_indir_tbl_get;
404 }
405
406 return 0;
407
408err_indir_tbl_get:
409 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
410 return err;
411}
412
413static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
414{
415 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
416
417 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
418 esw_cleanup_decap_indir(esw, attr);
419}
420
9e51c0a6
VB		 421static void
422esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
423{
424 mlx5_chains_put_table(chains, chain, prio, level);
425}
426
427static void
428esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
429 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
430 int attr_idx, int dest_idx, bool pkt_reformat)
431{
432 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
433 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
c6719725
MD		 434 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
435 dest[dest_idx].vport.vhca_id =
436 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
9e51c0a6 437 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
942fca7e 438 if (dest[dest_idx].vport.num == MLX5_VPORT_UPLINK &&
8ce81fc0 439 mlx5_lag_is_mpesw(esw->dev))
94db3317 440 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_UPLINK;
c6719725 441 }
6d942e40 442 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
9e51c0a6
VB		 443 if (pkt_reformat) {
444 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
445 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
446 }
447 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
448 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
449 }
450}
451
452static int
453esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
454 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
455 int i)
456{
457 int j;
458
459 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
460 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
461 return i;
462}
463
e929e3da
MD		 464static bool
465esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
466{
467 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
468 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
469 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
470}
471
9e51c0a6
VB		 472static int
473esw_setup_dests(struct mlx5_flow_destination *dest,
474 struct mlx5_flow_act *flow_act,
475 struct mlx5_eswitch *esw,
476 struct mlx5_flow_attr *attr,
10742efc 477 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 478 int *i)
479{
480 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
481 struct mlx5_fs_chains *chains = esw_chains(esw);
482 int err = 0;
483
10742efc 484 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
e929e3da 485 esw_src_port_rewrite_supported(esw))
e5d4e1da 486 attr->flags |= MLX5_ATTR_FLAG_SRC_REWRITE;
10742efc 487
42760d95 488 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {
c0063a43
VB		 489 esw_setup_slow_path_dest(dest, flow_act, esw, *i);
490 (*i)++;
42760d95
RD		 491 goto out;
492 }
493
494 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
495 esw_setup_sampler_dest(dest, flow_act, attr->sample_attr.sampler_id, *i);
496 (*i)++;
c0063a43
VB		 497 } else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {
498 esw_setup_accept_dest(dest, flow_act, chains, *i);
9e51c0a6 499 (*i)++;
6fda078d
OS		 500 } else if (attr->flags & MLX5_ATTR_FLAG_MTU) {
501 err = esw_setup_mtu_dest(dest, &attr->meter_attr, *i);
502 (*i)++;
a508728a 503 } else if (esw_is_indir_table(esw, attr)) {
521933cd 504 err = esw_setup_indir_table(dest, flow_act, esw, attr, true, i);
10742efc
VB		 505 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
506 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
9e51c0a6
VB		 507 } else {
508 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
8c9cc1eb
RD		 509
510 if (attr->dest_ft) {
521933cd 511 err = esw_setup_ft_dest(dest, flow_act, esw, attr, *i);
8c9cc1eb
RD		 512 (*i)++;
513 } else if (attr->dest_chain) {
514 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
515 1, 0, *i);
516 (*i)++;
517 }
9e51c0a6
VB		 518 }
519
42760d95 520out:
9e51c0a6
VB		 521 return err;
522}
523
524static void
525esw_cleanup_dests(struct mlx5_eswitch *esw,
526 struct mlx5_flow_attr *attr)
527{
10742efc 528 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
9e51c0a6
VB		 529 struct mlx5_fs_chains *chains = esw_chains(esw);
530
a508728a
VB		 531 if (attr->dest_ft) {
532 esw_cleanup_decap_indir(esw, attr);
e5d4e1da 533 } else if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
10742efc
VB		 534 if (attr->dest_chain)
535 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
a508728a
VB		 536 else if (esw_is_indir_table(esw, attr))
537 esw_cleanup_indir_table(esw, attr);
10742efc
VB		 538 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
539 esw_cleanup_chain_src_port_rewrite(esw, attr);
540 }
9e51c0a6
VB		 541}
542
9153da46
JL		 543static void
544esw_setup_meter(struct mlx5_flow_attr *attr, struct mlx5_flow_act *flow_act)
545{
546 struct mlx5e_flow_meter_handle *meter;
547
548 meter = attr->meter_attr.meter;
549 flow_act->exe_aso.type = attr->exe_aso_type;
550 flow_act->exe_aso.object_id = meter->obj_id;
551 flow_act->exe_aso.flow_meter.meter_idx = meter->idx;
552 flow_act->exe_aso.flow_meter.init_color = MLX5_FLOW_METER_COLOR_GREEN;
553 /* use metadata reg 5 for packet color */
554 flow_act->exe_aso.return_reg_id = 5;
555}
556
74491de9 557struct mlx5_flow_handle *
3d80d1a2
OG		 558mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
559 struct mlx5_flow_spec *spec,
c620b772 560 struct mlx5_flow_attr *attr)
3d80d1a2 561{
42f7ad67 562 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 563 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 564 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 565 bool split = !!(esw_attr->split_count);
566 struct mlx5_vport_tbl_attr fwd_attr;
40888162 567 struct mlx5_flow_destination *dest;
74491de9 568 struct mlx5_flow_handle *rule;
e52c2802 569 struct mlx5_flow_table *fdb;
9e51c0a6 570 int i = 0;
3d80d1a2 571
f6455de0 572 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 573 return ERR_PTR(-EOPNOTSUPP);
574
633ad4b2
RD		 575 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
576 return ERR_PTR(-EOPNOTSUPP);
577
40888162
MD		 578 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
579 if (!dest)
580 return ERR_PTR(-ENOMEM);
581
6acfbf38 582 flow_act.action = attr->action;
633ad4b2
RD		 583
584 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 585 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
586 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
587 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 588 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 589 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
590 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
591 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 592 }
6acfbf38 593 }
776b12b6 594
10742efc
VB		 595 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
596
66958ed9 597 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
9e51c0a6
VB		 598 int err;
599
10742efc 600 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
9e51c0a6
VB		 601 if (err) {
602 rule = ERR_PTR(err);
603 goto err_create_goto_table;
56e858df 604 }
e37a79e5 605 }
14e6b038 606
c620b772
AL		 607 if (esw_attr->decap_pkt_reformat)
608 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 609
66958ed9 610 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 611 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 612 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 613 i++;
3d80d1a2
OG		 614 }
615
93b3586e 616 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 617 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 618 if (attr->inner_match_level != MLX5_MATCH_NONE)
619 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 620
aa24670e 621 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 622 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 623
9153da46
JL		 624 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
625 attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)
626 esw_setup_meter(attr, &flow_act);
627
2741f223 628 if (split) {
c620b772
AL		 629 fwd_attr.chain = attr->chain;
630 fwd_attr.prio = attr->prio;
631 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 632 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772 633
0a9e2307 634 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
96e32687 635 } else {
d18296ff 636 if (attr->chain || attr->prio)
ae430332
AL		 637 fdb = mlx5_chains_get_table(chains, attr->chain,
638 attr->prio, 0);
d18296ff 639 else
c620b772 640 fdb = attr->ft;
6fb0701a 641
e5d4e1da 642 if (!(attr->flags & MLX5_ATTR_FLAG_NO_IN_PORT))
a508728a 643 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 644 esw_attr->in_mdev->priv.eswitch,
645 esw_attr->in_rep->vport);
96e32687 646 }
e52c2802
PB		 647 if (IS_ERR(fdb)) {
648 rule = ERR_CAST(fdb);
649 goto err_esw_get;
650 }
651
5a5624d1
OS		 652 if (!i) {
653 kfree(dest);
654 dest = NULL;
655 }
656
84be2fda 657 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 658 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 659 &flow_act, dest, i);
84be2fda 660 else
10caabda 661 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 662 if (IS_ERR(rule))
e52c2802 663 goto err_add_rule;
375f51e2 664 else
525e84be 665 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 666
40888162 667 kfree(dest);
e52c2802
PB		 668 return rule;
669
670err_add_rule:
96e32687 671 if (split)
0a9e2307 672 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 673 else if (attr->chain || attr->prio)
ae430332 674 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 675err_esw_get:
9e51c0a6 676 esw_cleanup_dests(esw, attr);
e52c2802 677err_create_goto_table:
40888162 678 kfree(dest);
aa0cbbae 679 return rule;
3d80d1a2
OG		 680}
681
e4ad91f2
CM		 682struct mlx5_flow_handle *
683mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
684 struct mlx5_flow_spec *spec,
c620b772 685 struct mlx5_flow_attr *attr)
e4ad91f2 686{
42f7ad67 687 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 688 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 689 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 690 struct mlx5_vport_tbl_attr fwd_attr;
40888162 691 struct mlx5_flow_destination *dest;
e52c2802
PB		 692 struct mlx5_flow_table *fast_fdb;
693 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 694 struct mlx5_flow_handle *rule;
10742efc 695 int i, err = 0;
e4ad91f2 696
40888162
MD		 697 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
698 if (!dest)
699 return ERR_PTR(-ENOMEM);
700
ae430332 701 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 702 if (IS_ERR(fast_fdb)) {
703 rule = ERR_CAST(fast_fdb);
704 goto err_get_fast;
705 }
706
c620b772
AL		 707 fwd_attr.chain = attr->chain;
708 fwd_attr.prio = attr->prio;
709 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 710 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 711 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
e52c2802
PB		 712 if (IS_ERR(fwd_fdb)) {
713 rule = ERR_CAST(fwd_fdb);
714 goto err_get_fwd;
715 }
716
e4ad91f2 717 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
10742efc 718 for (i = 0; i < esw_attr->split_count; i++) {
1313d78a
MD		 719 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
720 /* Source port rewrite (forward to ovs internal port or statck device) isn't
721 * supported in the rule of split action.
722 */
723 err = -EOPNOTSUPP;
10742efc
VB		 724 else
725 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
726
727 if (err) {
728 rule = ERR_PTR(err);
729 goto err_chain_src_rewrite;
730 }
731 }
e4ad91f2 732 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 733 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 734 i++;
735
a508728a 736 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 737 esw_attr->in_mdev->priv.eswitch,
738 esw_attr->in_rep->vport);
e4ad91f2 739
93b3586e 740 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 741 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 742
278d51f2 743 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 744 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 745
10742efc
VB		 746 if (IS_ERR(rule)) {
747 i = esw_attr->split_count;
748 goto err_chain_src_rewrite;
749 }
e4ad91f2 750
525e84be 751 atomic64_inc(&esw->offloads.num_flows);
e52c2802 752
40888162 753 kfree(dest);
e52c2802 754 return rule;
10742efc 755err_chain_src_rewrite:
0a9e2307 756 mlx5_esw_vporttbl_put(esw, &fwd_attr);
e52c2802 757err_get_fwd:
ae430332 758 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 759err_get_fast:
40888162 760 kfree(dest);
e4ad91f2
CM		 761 return rule;
762}
763
e52c2802
PB		 764static void
765__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
766 struct mlx5_flow_handle *rule,
c620b772 767 struct mlx5_flow_attr *attr,
e52c2802
PB		 768 bool fwd_rule)
769{
c620b772 770 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 771 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 772 bool split = (esw_attr->split_count > 0);
773 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 774 int i;
e52c2802
PB		 775
776 mlx5_del_flow_rules(rule);
10caabda 777
e5d4e1da 778 if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
d8a2034f
EC		 779 /* unref the term table */
780 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 781 if (esw_attr->dests[i].termtbl)
782 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 783 }
10caabda
OS		 784 }
785
525e84be 786 atomic64_dec(&esw->offloads.num_flows);
e52c2802 787
c620b772
AL		 788 if (fwd_rule || split) {
789 fwd_attr.chain = attr->chain;
790 fwd_attr.prio = attr->prio;
791 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 792 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772
AL		 793 }
794
e52c2802 795 if (fwd_rule) {
0a9e2307 796 mlx5_esw_vporttbl_put(esw, &fwd_attr);
ae430332 797 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 798 } else {
96e32687 799 if (split)
0a9e2307 800 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 801 else if (attr->chain || attr->prio)
ae430332 802 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
9e51c0a6 803 esw_cleanup_dests(esw, attr);
e52c2802
PB		 804 }
805}
806
d85cdccb
OG		 807void
808mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
809 struct mlx5_flow_handle *rule,
c620b772 810 struct mlx5_flow_attr *attr)
d85cdccb 811{
e52c2802 812 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 813}
814
48265006
OG		 815void
816mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
817 struct mlx5_flow_handle *rule,
c620b772 818 struct mlx5_flow_attr *attr)
48265006 819{
e52c2802 820 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 821}
822
f7a68945 823struct mlx5_flow_handle *
3a46f4fb 824mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
979bf468 825 struct mlx5_eswitch *from_esw,
3a46f4fb 826 struct mlx5_eswitch_rep *rep,
02f3afd9 827 u32 sqn)
ab22be9b 828{
66958ed9 829 struct mlx5_flow_act flow_act = {0};
4c5009c5 830 struct mlx5_flow_destination dest = {};
74491de9 831 struct mlx5_flow_handle *flow_rule;
c5bb1730 832 struct mlx5_flow_spec *spec;
ab22be9b 833 void *misc;
29bcb6e4 834 u16 vport;
ab22be9b 835
1b9a07ee 836 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 837 if (!spec) {
ab22be9b
OG		 838 flow_rule = ERR_PTR(-ENOMEM);
839 goto out;
840 }
841
c5bb1730 842 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 843 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
ab22be9b 844
c5bb1730 845 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b 846 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
ab22be9b 847
c5bb1730 848 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
29bcb6e4
RD		 849
850 /* source vport is the esw manager */
851 vport = from_esw->manager_vport;
852
853 if (mlx5_eswitch_vport_match_metadata_enabled(on_esw)) {
854 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
855 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
856 mlx5_eswitch_get_vport_metadata_for_match(from_esw, vport));
857
858 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
859 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
860 mlx5_eswitch_get_vport_metadata_mask());
861
862 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
863 } else {
864 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
865 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
866
867 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
868 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
869 MLX5_CAP_GEN(from_esw->dev, vhca_id));
870
871 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
872 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
873
874 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
875 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
876 source_eswitch_owner_vhca_id);
877
878 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
879 }
880
ab22be9b 881 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
3a46f4fb
MB		 882 dest.vport.num = rep->vport;
883 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
884 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
66958ed9 885 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 886
1bf8b0da
RD		 887 if (MLX5_CAP_ESW_FLOWTABLE(on_esw->dev, flow_source) &&
888 rep->vport == MLX5_VPORT_UPLINK)
d0444254
AL		 889 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
890
dcf19b9c 891 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(on_esw),
39ac237c 892 spec, &flow_act, &dest, 1);
ab22be9b 893 if (IS_ERR(flow_rule))
3a46f4fb
MB		 894 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
895 PTR_ERR(flow_rule));
ab22be9b 896out:
c5bb1730 897 kvfree(spec);
ab22be9b
OG		 898 return flow_rule;
899}
57cbd893 900EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 901
159fe639
MB		 902void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
903{
904 mlx5_del_flow_rules(rule);
905}
906
430e2d5e 907void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule)
8e404fef 908{
430e2d5e
RD		 909 if (rule)
910 mlx5_del_flow_rules(rule);
f019679e
CM		 911}
912
430e2d5e
RD		 913struct mlx5_flow_handle *
914mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num)
8e404fef 915{
8e404fef
VB		 916 struct mlx5_flow_destination dest = {};
917 struct mlx5_flow_act flow_act = {0};
918 struct mlx5_flow_handle *flow_rule;
8e404fef 919 struct mlx5_flow_spec *spec;
8e404fef
VB		 920
921 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
430e2d5e
RD		 922 if (!spec)
923 return ERR_PTR(-ENOMEM);
8e404fef
VB		 924
925 MLX5_SET(fte_match_param, spec->match_criteria,
926 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
927 MLX5_SET(fte_match_param, spec->match_criteria,
928 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
929 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
930 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
931
932 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
933 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
934 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
935
430e2d5e
RD		 936 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
937 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
938 dest.vport.num = vport_num;
8e404fef 939
dcf19b9c 940 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
430e2d5e
RD		 941 spec, &flow_act, &dest, 1);
942 if (IS_ERR(flow_rule))
943 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule vport %d, err %ld\n",
944 vport_num, PTR_ERR(flow_rule));
8e404fef 945
8e404fef 946 kvfree(spec);
430e2d5e 947 return flow_rule;
8e404fef
VB		 948}
949
5b7cb745
PB		 950static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
951{
952 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
953 MLX5_FDB_TO_VPORT_REG_C_1;
954}
955
332bd3a5 956static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 957{
958 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 959 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
960 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 961 u8 curr, wanted;
c1286050
JL		 962 int err;
963
5b7cb745
PB		 964 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
965 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 966 return 0;
c1286050 967
e08a6832
LR		 968 MLX5_SET(query_esw_vport_context_in, in, opcode,
969 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
970 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 971 if (err)
972 return err;
973
5b7cb745
PB		 974 curr = MLX5_GET(query_esw_vport_context_out, out,
975 esw_vport_context.fdb_to_vport_reg_c_id);
976 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
977 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
978 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 979
332bd3a5 980 if (enable)
5b7cb745 981 curr |= wanted;
332bd3a5 982 else
5b7cb745 983 curr &= ~wanted;
c1286050 984
e08a6832 985 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 986 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 987 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 988 field_select.fdb_to_vport_reg_c_id, 1);
989
e08a6832 990 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 991 if (!err) {
992 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
993 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
994 else
995 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
996 }
997
998 return err;
c1286050
JL		 999}
1000
a5641cb5
JL		 1001static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1002 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 1003 struct mlx5_flow_spec *spec,
1004 struct mlx5_flow_destination *dest)
1005{
a5641cb5 1006 void *misc;
ac004b83 1007
a5641cb5
JL		 1008 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1009 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1010 misc_parameters_2);
0f0d3827
PB		 1011 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1012 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 1013
a5641cb5
JL		 1014 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1015 } else {
1016 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1017 misc_parameters);
ac004b83 1018
a5641cb5
JL		 1019 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1020 MLX5_CAP_GEN(peer_dev, vhca_id));
1021
1022 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1023
1024 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1025 misc_parameters);
1026 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1027 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1028 source_eswitch_owner_vhca_id);
1029 }
ac004b83
RD		 1030
1031 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1032 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 1033 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 1034 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 1035}
1036
a5641cb5
JL		 1037static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1038 struct mlx5_eswitch *peer_esw,
1039 struct mlx5_flow_spec *spec,
1040 u16 vport)
1041{
1042 void *misc;
1043
1044 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1045 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1046 misc_parameters_2);
1047 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1048 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1049 vport));
1050 } else {
1051 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1052 misc_parameters);
1053 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1054 }
1055}
1056
ac004b83
RD		 1057static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1058 struct mlx5_core_dev *peer_dev)
1059{
1060 struct mlx5_flow_destination dest = {};
1061 struct mlx5_flow_act flow_act = {0};
1062 struct mlx5_flow_handle **flows;
ac004b83
RD		 1063 /* total vports is the same for both e-switches */
1064 int nvports = esw->total_vports;
47dd7e60
PP		 1065 struct mlx5_flow_handle *flow;
1066 struct mlx5_flow_spec *spec;
1067 struct mlx5_vport *vport;
1068 unsigned long i;
ac004b83 1069 void *misc;
47dd7e60 1070 int err;
ac004b83 1071
1552e9b5
RD		 1072 if (!MLX5_VPORT_MANAGER(esw->dev) && !mlx5_core_is_ecpf_esw_manager(esw->dev))
1073 return 0;
1074
ac004b83
RD		 1075 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1076 if (!spec)
1077 return -ENOMEM;
1078
a5641cb5 1079 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83 1080
806bf340 1081 flows = kvcalloc(nvports, sizeof(*flows), GFP_KERNEL);
ac004b83
RD		 1082 if (!flows) {
1083 err = -ENOMEM;
1084 goto alloc_flows_err;
1085 }
1086
1087 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1088 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1089 misc_parameters);
1090
81cd229c 1091 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
47dd7e60 1092 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
a5641cb5
JL		 1093 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1094 spec, MLX5_VPORT_PF);
1095
dcf19b9c 1096 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
81cd229c
BW		 1097 spec, &flow_act, &dest, 1);
1098 if (IS_ERR(flow)) {
1099 err = PTR_ERR(flow);
1100 goto add_pf_flow_err;
1101 }
47dd7e60 1102 flows[vport->index] = flow;
81cd229c
BW		 1103 }
1104
1105 if (mlx5_ecpf_vport_exists(esw->dev)) {
47dd7e60 1106 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
81cd229c 1107 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
dcf19b9c 1108 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
81cd229c
BW		 1109 spec, &flow_act, &dest, 1);
1110 if (IS_ERR(flow)) {
1111 err = PTR_ERR(flow);
1112 goto add_ecpf_flow_err;
1113 }
47dd7e60 1114 flows[vport->index] = flow;
81cd229c
BW		 1115 }
1116
47dd7e60 1117 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 1118 esw_set_peer_miss_rule_source_port(esw,
1119 peer_dev->priv.eswitch,
47dd7e60 1120 spec, vport->vport);
a5641cb5 1121
dcf19b9c 1122 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
ac004b83
RD		 1123 spec, &flow_act, &dest, 1);
1124 if (IS_ERR(flow)) {
1125 err = PTR_ERR(flow);
81cd229c 1126 goto add_vf_flow_err;
ac004b83 1127 }
47dd7e60 1128 flows[vport->index] = flow;
ac004b83
RD		 1129 }
1130
fa3c73ee
DJ		 1131 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
1132 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1133 if (i >= mlx5_core_max_ec_vfs(peer_dev))
1134 break;
1135 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1136 spec, vport->vport);
1137 flow = mlx5_add_flow_rules(esw->fdb_table.offloads.slow_fdb,
1138 spec, &flow_act, &dest, 1);
1139 if (IS_ERR(flow)) {
1140 err = PTR_ERR(flow);
1141 goto add_ec_vf_flow_err;
1142 }
1143 flows[vport->index] = flow;
1144 }
1145 }
9bee385a 1146 esw->fdb_table.offloads.peer_miss_rules[mlx5_get_dev_index(peer_dev)] = flows;
ac004b83
RD		 1147
1148 kvfree(spec);
1149 return 0;
1150
fa3c73ee
DJ		 1151add_ec_vf_flow_err:
1152 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1153 if (!flows[vport->index])
1154 continue;
1155 mlx5_del_flow_rules(flows[vport->index]);
1156 }
81cd229c 1157add_vf_flow_err:
47dd7e60
PP		 1158 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1159 if (!flows[vport->index])
1160 continue;
1161 mlx5_del_flow_rules(flows[vport->index]);
1162 }
1163 if (mlx5_ecpf_vport_exists(esw->dev)) {
1164 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1165 mlx5_del_flow_rules(flows[vport->index]);
1166 }
81cd229c 1167add_ecpf_flow_err:
47dd7e60
PP		 1168 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1169 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1170 mlx5_del_flow_rules(flows[vport->index]);
1171 }
81cd229c
BW		 1172add_pf_flow_err:
1173 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1174 kvfree(flows);
1175alloc_flows_err:
1176 kvfree(spec);
1177 return err;
1178}
1179
9bee385a
SD		 1180static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1181 struct mlx5_core_dev *peer_dev)
ac004b83 1182{
1552e9b5 1183 u16 peer_index = mlx5_get_dev_index(peer_dev);
ac004b83 1184 struct mlx5_flow_handle **flows;
47dd7e60
PP		 1185 struct mlx5_vport *vport;
1186 unsigned long i;
ac004b83 1187
1552e9b5
RD		 1188 flows = esw->fdb_table.offloads.peer_miss_rules[peer_index];
1189 if (!flows)
1190 return;
ac004b83 1191
fa3c73ee
DJ		 1192 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
1193 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, mlx5_core_max_ec_vfs(esw->dev)) {
1194 /* The flow for a particular vport could be NULL if the other ECPF
1195 * has fewer or no VFs enabled
1196 */
1197 if (!flows[vport->index])
1198 continue;
1199 mlx5_del_flow_rules(flows[vport->index]);
1200 }
1201 }
1202
47dd7e60
PP		 1203 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1204 mlx5_del_flow_rules(flows[vport->index]);
ac004b83 1205
47dd7e60
PP		 1206 if (mlx5_ecpf_vport_exists(esw->dev)) {
1207 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1208 mlx5_del_flow_rules(flows[vport->index]);
1209 }
81cd229c 1210
47dd7e60
PP		 1211 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1212 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1213 mlx5_del_flow_rules(flows[vport->index]);
1214 }
1552e9b5 1215
ac004b83 1216 kvfree(flows);
1552e9b5 1217 esw->fdb_table.offloads.peer_miss_rules[peer_index] = NULL;
ac004b83
RD		 1218}
1219
3aa33572
OG		 1220static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1221{
66958ed9 1222 struct mlx5_flow_act flow_act = {0};
4c5009c5 1223 struct mlx5_flow_destination dest = {};
74491de9 1224 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1225 struct mlx5_flow_spec *spec;
f80be543
MB		 1226 void *headers_c;
1227 void *headers_v;
3aa33572 1228 int err = 0;
f80be543
MB		 1229 u8 *dmac_c;
1230 u8 *dmac_v;
3aa33572 1231
1b9a07ee 1232 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1233 if (!spec) {
3aa33572
OG		 1234 err = -ENOMEM;
1235 goto out;
1236 }
1237
f80be543
MB		 1238 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1239 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1240 outer_headers);
1241 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1242 outer_headers.dmac_47_16);
1243 dmac_c[0] = 0x01;
1244
3aa33572 1245 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1246 dest.vport.num = esw->manager_vport;
66958ed9 1247 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1248
dcf19b9c 1249 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
39ac237c 1250 spec, &flow_act, &dest, 1);
3aa33572
OG		 1251 if (IS_ERR(flow_rule)) {
1252 err = PTR_ERR(flow_rule);
f80be543 1253 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1254 goto out;
1255 }
1256
f80be543
MB		 1257 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1258
1259 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1260 outer_headers);
1261 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1262 outer_headers.dmac_47_16);
1263 dmac_v[0] = 0x01;
dcf19b9c 1264 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
39ac237c 1265 spec, &flow_act, &dest, 1);
f80be543
MB		 1266 if (IS_ERR(flow_rule)) {
1267 err = PTR_ERR(flow_rule);
1268 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1269 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1270 goto out;
1271 }
1272
1273 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1274
3aa33572 1275out:
c5bb1730 1276 kvfree(spec);
3aa33572
OG		 1277 return err;
1278}
1279
11b717d6
PB		 1280struct mlx5_flow_handle *
1281esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1282{
1283 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1284 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1285 struct mlx5_flow_context *flow_context;
1286 struct mlx5_flow_handle *flow_rule;
1287 struct mlx5_flow_destination dest;
1288 struct mlx5_flow_spec *spec;
1289 void *misc;
1290
60acc105
PB		 1291 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1292 return ERR_PTR(-EOPNOTSUPP);
1293
9f4d9283 1294 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
11b717d6
PB		 1295 if (!spec)
1296 return ERR_PTR(-ENOMEM);
1297
1298 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1299 misc_parameters_2);
1300 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 1301 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 1302 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1303 misc_parameters_2);
1304 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1305 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1306 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1307 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1308 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1309
1310 flow_context = &spec->flow_context;
1311 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1312 flow_context->flow_tag = tag;
1313 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1314 dest.ft = esw->offloads.ft_offloads;
1315
1316 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
9f4d9283 1317 kvfree(spec);
11b717d6
PB		 1318
1319 if (IS_ERR(flow_rule))
1320 esw_warn(esw->dev,
1321 "Failed to create restore rule for tag: %d, err(%d)\n",
1322 tag, (int)PTR_ERR(flow_rule));
1323
1324 return flow_rule;
1325}
1326
1967ce6e 1327#define MAX_PF_SQ 256
cd3d07e7 1328#define MAX_SQ_NVPORTS 32
1967ce6e 1329
7eb197fd
RD		 1330void
1331mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1332 u32 *flow_group_in,
1333 int match_params)
a5641cb5
JL		 1334{
1335 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1336 flow_group_in,
1337 match_criteria);
1338
1339 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1340 MLX5_SET(create_flow_group_in, flow_group_in,
1341 match_criteria_enable,
29bcb6e4 1342 MLX5_MATCH_MISC_PARAMETERS_2 | match_params);
a5641cb5 1343
0f0d3827
PB		 1344 MLX5_SET(fte_match_param, match_criteria,
1345 misc_parameters_2.metadata_reg_c_0,
1346 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1347 } else {
1348 MLX5_SET(create_flow_group_in, flow_group_in,
1349 match_criteria_enable,
29bcb6e4 1350 MLX5_MATCH_MISC_PARAMETERS | match_params);
a5641cb5
JL		 1351
1352 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1353 misc_parameters.source_port);
1354 }
1355}
1356
ae430332 1357#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0a9e2307 1358static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
4c7f4028
CM		 1359{
1360 struct mlx5_vport_tbl_attr attr;
1361 struct mlx5_vport *vport;
47dd7e60 1362 unsigned long i;
4c7f4028
CM		 1363
1364 attr.chain = 0;
1365 attr.prio = 1;
47dd7e60 1366 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1367 attr.vport = vport->vport;
c796bb7c 1368 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1369 mlx5_esw_vporttbl_put(esw, &attr);
4c7f4028
CM		 1370 }
1371}
1372
0a9e2307 1373static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
4c7f4028
CM		 1374{
1375 struct mlx5_vport_tbl_attr attr;
1376 struct mlx5_flow_table *fdb;
1377 struct mlx5_vport *vport;
47dd7e60 1378 unsigned long i;
4c7f4028
CM		 1379
1380 attr.chain = 0;
1381 attr.prio = 1;
47dd7e60 1382 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1383 attr.vport = vport->vport;
c796bb7c 1384 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1385 fdb = mlx5_esw_vporttbl_get(esw, &attr);
4c7f4028
CM		 1386 if (IS_ERR(fdb))
1387 goto out;
1388 }
1389 return 0;
1390
1391out:
0a9e2307 1392 esw_vport_tbl_put(esw);
4c7f4028
CM		 1393 return PTR_ERR(fdb);
1394}
1395
ae430332
AL		 1396#define fdb_modify_header_fwd_to_table_supported(esw) \
1397 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1398static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1399{
1400 struct mlx5_core_dev *dev = esw->dev;
1401
1402 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1403 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1404
1405 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1406 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1407 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1408 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1409 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1410 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1411 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1412 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1413 /* Disabled when ttl workaround is needed, e.g
1414 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1415 */
1416 esw_warn(dev,
1417 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1418 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1419 } else {
1420 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1421 esw_info(dev, "Supported tc chains and prios offload\n");
1422 }
1423
1424 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1425 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1426}
1427
1428static int
1429esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1430{
1431 struct mlx5_core_dev *dev = esw->dev;
1432 struct mlx5_flow_table *nf_ft, *ft;
1433 struct mlx5_chains_attr attr = {};
1434 struct mlx5_fs_chains *chains;
ae430332
AL		 1435 int err;
1436
ae430332
AL		 1437 esw_init_chains_offload_flags(esw, &attr.flags);
1438 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
8e80e564 1439 attr.fs_base_prio = FDB_TC_OFFLOAD;
ae430332
AL		 1440 attr.max_grp_num = esw->params.large_group_num;
1441 attr.default_ft = miss_fdb;
c9355682 1442 attr.mapping = esw->offloads.reg_c0_obj_pool;
ae430332
AL		 1443
1444 chains = mlx5_chains_create(dev, &attr);
1445 if (IS_ERR(chains)) {
1446 err = PTR_ERR(chains);
1447 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1448 return err;
1449 }
8e80e564 1450 mlx5_chains_print_info(chains);
ae430332
AL		 1451
1452 esw->fdb_table.offloads.esw_chains_priv = chains;
1453
1454 /* Create tc_end_ft which is the always created ft chain */
1455 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1456 1, 0);
1457 if (IS_ERR(nf_ft)) {
1458 err = PTR_ERR(nf_ft);
1459 goto nf_ft_err;
1460 }
1461
1462 /* Always open the root for fast path */
1463 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1464 if (IS_ERR(ft)) {
1465 err = PTR_ERR(ft);
1466 goto level_0_err;
1467 }
1468
1469 /* Open level 1 for split fdb rules now if prios isn't supported */
1470 if (!mlx5_chains_prios_supported(chains)) {
0a9e2307 1471 err = esw_vport_tbl_get(esw);
ae430332
AL		 1472 if (err)
1473 goto level_1_err;
1474 }
1475
1476 mlx5_chains_set_end_ft(chains, nf_ft);
1477
1478 return 0;
1479
1480level_1_err:
1481 mlx5_chains_put_table(chains, 0, 1, 0);
1482level_0_err:
1483 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1484nf_ft_err:
1485 mlx5_chains_destroy(chains);
1486 esw->fdb_table.offloads.esw_chains_priv = NULL;
1487
1488 return err;
1489}
1490
1491static void
1492esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1493{
1494 if (!mlx5_chains_prios_supported(chains))
0a9e2307 1495 esw_vport_tbl_put(esw);
ae430332
AL		 1496 mlx5_chains_put_table(chains, 0, 1, 0);
1497 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1498 mlx5_chains_destroy(chains);
1499}
1500
1501#else /* CONFIG_MLX5_CLS_ACT */
1502
1503static int
1504esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1505{ return 0; }
1506
1507static void
1508esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1509{}
1510
1511#endif
1512
4a561817
RD		 1513static int
1514esw_create_send_to_vport_group(struct mlx5_eswitch *esw,
1515 struct mlx5_flow_table *fdb,
1516 u32 *flow_group_in,
1517 int *ix)
1518{
1519 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1520 struct mlx5_flow_group *g;
1521 void *match_criteria;
1522 int count, err = 0;
1523
1524 memset(flow_group_in, 0, inlen);
1525
7eb197fd 1526 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, MLX5_MATCH_MISC_PARAMETERS);
4a561817
RD		 1527
1528 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
4a561817 1529 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
29bcb6e4
RD		 1530
1531 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1532 MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
4a561817
RD		 1533 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1534 misc_parameters.source_eswitch_owner_vhca_id);
1535 MLX5_SET(create_flow_group_in, flow_group_in,
1536 source_eswitch_owner_vhca_id_valid, 1);
1537 }
1538
1539 /* See comment at table_size calculation */
1540 count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1541 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1542 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, *ix + count - 1);
1543 *ix += count;
1544
1545 g = mlx5_create_flow_group(fdb, flow_group_in);
1546 if (IS_ERR(g)) {
1547 err = PTR_ERR(g);
1548 esw_warn(esw->dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1549 goto out;
1550 }
1551 esw->fdb_table.offloads.send_to_vport_grp = g;
1552
1553out:
1554 return err;
1555}
1556
1557static int
1558esw_create_meta_send_to_vport_group(struct mlx5_eswitch *esw,
1559 struct mlx5_flow_table *fdb,
1560 u32 *flow_group_in,
1561 int *ix)
1562{
1563 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
4a561817
RD		 1564 struct mlx5_flow_group *g;
1565 void *match_criteria;
1566 int err = 0;
1567
1568 if (!esw_src_port_rewrite_supported(esw))
1569 return 0;
1570
1571 memset(flow_group_in, 0, inlen);
1572
1573 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1574 MLX5_MATCH_MISC_PARAMETERS_2);
1575
1576 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1577
1578 MLX5_SET(fte_match_param, match_criteria,
1579 misc_parameters_2.metadata_reg_c_0,
1580 mlx5_eswitch_get_vport_metadata_mask());
1581 MLX5_SET(fte_match_param, match_criteria,
1582 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1583
430e2d5e
RD		 1584 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1585 MLX5_SET(create_flow_group_in, flow_group_in,
1586 end_flow_index, *ix + esw->total_vports - 1);
1587 *ix += esw->total_vports;
4a561817 1588
430e2d5e
RD		 1589 g = mlx5_create_flow_group(fdb, flow_group_in);
1590 if (IS_ERR(g)) {
1591 err = PTR_ERR(g);
1592 esw_warn(esw->dev,
1593 "Failed to create send-to-vport meta flow group err(%d)\n", err);
1594 goto send_vport_meta_err;
4a561817 1595 }
430e2d5e 1596 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
4a561817
RD		 1597
1598 return 0;
1599
4a561817
RD		 1600send_vport_meta_err:
1601 return err;
1602}
1603
1604static int
1605esw_create_peer_esw_miss_group(struct mlx5_eswitch *esw,
1606 struct mlx5_flow_table *fdb,
1607 u32 *flow_group_in,
1608 int *ix)
1609{
18e31d42 1610 int max_peer_ports = (esw->total_vports - 1) * (MLX5_MAX_PORTS - 1);
4a561817
RD		 1611 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1612 struct mlx5_flow_group *g;
1613 void *match_criteria;
1614 int err = 0;
1615
1616 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1617 return 0;
1618
1619 memset(flow_group_in, 0, inlen);
1620
7eb197fd 1621 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
4a561817
RD		 1622
1623 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1624 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1625 flow_group_in,
1626 match_criteria);
1627
1628 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1629 misc_parameters.source_eswitch_owner_vhca_id);
1630
1631 MLX5_SET(create_flow_group_in, flow_group_in,
1632 source_eswitch_owner_vhca_id_valid, 1);
1633 }
1634
1635 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1636 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
18e31d42
SD		 1637 *ix + max_peer_ports);
1638 *ix += max_peer_ports + 1;
4a561817
RD		 1639
1640 g = mlx5_create_flow_group(fdb, flow_group_in);
1641 if (IS_ERR(g)) {
1642 err = PTR_ERR(g);
1643 esw_warn(esw->dev, "Failed to create peer miss flow group err(%d)\n", err);
1644 goto out;
1645 }
1646 esw->fdb_table.offloads.peer_miss_grp = g;
1647
1648out:
1649 return err;
1650}
1651
1652static int
1653esw_create_miss_group(struct mlx5_eswitch *esw,
1654 struct mlx5_flow_table *fdb,
1655 u32 *flow_group_in,
1656 int *ix)
1657{
1658 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1659 struct mlx5_flow_group *g;
1660 void *match_criteria;
1661 int err = 0;
1662 u8 *dmac;
1663
1664 memset(flow_group_in, 0, inlen);
1665
1666 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1667 MLX5_MATCH_OUTER_HEADERS);
1668 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1669 match_criteria);
1670 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1671 outer_headers.dmac_47_16);
1672 dmac[0] = 0x01;
1673
1674 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1675 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1676 *ix + MLX5_ESW_MISS_FLOWS);
1677
1678 g = mlx5_create_flow_group(fdb, flow_group_in);
1679 if (IS_ERR(g)) {
1680 err = PTR_ERR(g);
1681 esw_warn(esw->dev, "Failed to create miss flow group err(%d)\n", err);
1682 goto miss_err;
1683 }
1684 esw->fdb_table.offloads.miss_grp = g;
1685
1686 err = esw_add_fdb_miss_rule(esw);
1687 if (err)
1688 goto miss_rule_err;
1689
1690 return 0;
1691
1692miss_rule_err:
1693 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1694miss_err:
1695 return err;
1696}
1697
0da3c12d 1698static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1699{
1700 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1701 struct mlx5_flow_table_attr ft_attr = {};
1702 struct mlx5_core_dev *dev = esw->dev;
1703 struct mlx5_flow_namespace *root_ns;
1704 struct mlx5_flow_table *fdb = NULL;
4a561817 1705 int table_size, ix = 0, err = 0;
39ac237c 1706 u32 flags = 0, *flow_group_in;
1967ce6e
OG		 1707
1708 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1709
1b9a07ee 1710 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1711 if (!flow_group_in)
1712 return -ENOMEM;
1713
1714 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1715 if (!root_ns) {
1716 esw_warn(dev, "Failed to get FDB flow namespace\n");
1717 err = -EOPNOTSUPP;
1718 goto ns_err;
1719 }
8463daf1
MG		 1720 esw->fdb_table.offloads.ns = root_ns;
1721 err = mlx5_flow_namespace_set_mode(root_ns,
1722 esw->dev->priv.steering->mode);
1723 if (err) {
1724 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1725 goto ns_err;
1726 }
1967ce6e 1727
898b0786
MB		 1728 /* To be strictly correct:
1729 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1730 * should be:
1731 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1732 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1733 * but as the peer device might not be in switchdev mode it's not
1734 * possible. We use the fact that by default FW sets max vfs and max sfs
1735 * to the same value on both devices. If it needs to be changed in the future note
1736 * the peer miss group should also be created based on the number of
1737 * total vports of the peer (currently is also uses esw->total_vports).
1738 */
1739 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
18e31d42 1740 esw->total_vports * MLX5_MAX_PORTS + MLX5_ESW_MISS_FLOWS;
b3ba5149 1741
e52c2802
PB		 1742 /* create the slow path fdb with encap set, so further table instances
1743 * can be created at run time while VFs are probed if the FW allows that.
1744 */
1745 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1746 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1747 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1748
1749 ft_attr.flags = flags;
b3ba5149
ES		 1750 ft_attr.max_fte = table_size;
1751 ft_attr.prio = FDB_SLOW_PATH;
1752
1753 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1754 if (IS_ERR(fdb)) {
1755 err = PTR_ERR(fdb);
1756 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1757 goto slow_fdb_err;
1758 }
52fff327 1759 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1760
ec3be887
VB		 1761 /* Create empty TC-miss managed table. This allows plugging in following
1762 * priorities without directly exposing their level 0 table to
1763 * eswitch_offloads and passing it as miss_fdb to following call to
1764 * esw_chains_create().
1765 */
1766 memset(&ft_attr, 0, sizeof(ft_attr));
1767 ft_attr.prio = FDB_TC_MISS;
1768 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1769 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1770 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1771 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1772 goto tc_miss_table_err;
1773 }
1774
1775 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
39ac237c 1776 if (err) {
ae430332 1777 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1778 goto fdb_chains_err;
e52c2802
PB		 1779 }
1780
4a561817
RD		 1781 err = esw_create_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1782 if (err)
69697b6e 1783 goto send_vport_err;
8e404fef 1784
4a561817
RD		 1785 err = esw_create_meta_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1786 if (err)
1787 goto send_vport_meta_err;
69697b6e 1788
4a561817
RD		 1789 err = esw_create_peer_esw_miss_group(esw, fdb, flow_group_in, &ix);
1790 if (err)
1791 goto peer_miss_err;
69697b6e 1792
4a561817 1793 err = esw_create_miss_group(esw, fdb, flow_group_in, &ix);
3aa33572 1794 if (err)
4a561817 1795 goto miss_err;
3aa33572 1796
c88a026e 1797 kvfree(flow_group_in);
69697b6e
OG		 1798 return 0;
1799
1800miss_err:
6cec0229
MD		 1801 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1802 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1803peer_miss_err:
8e404fef
VB		 1804 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1805 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1806send_vport_meta_err:
69697b6e
OG		 1807 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1808send_vport_err:
ae430332 1809 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1810fdb_chains_err:
ec3be887
VB		 1811 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1812tc_miss_table_err:
dcf19b9c 1813 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1033665e 1814slow_fdb_err:
8463daf1
MG		 1815 /* Holds true only as long as DMFS is the default */
1816 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1817ns_err:
1818 kvfree(flow_group_in);
1819 return err;
1820}
1821
1967ce6e 1822static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1823{
dcf19b9c 1824 if (!mlx5_eswitch_get_slow_fdb(esw))
69697b6e
OG		 1825 return;
1826
1967ce6e 1827 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1828 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1829 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e 1830 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
8e404fef
VB		 1831 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1832 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
6cec0229
MD		 1833 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1834 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1835 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1836
ae430332
AL		 1837 esw_chains_destroy(esw, esw_chains(esw));
1838
ec3be887 1839 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
dcf19b9c 1840 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
8463daf1
MG		 1841 /* Holds true only as long as DMFS is the default */
1842 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1843 MLX5_FLOW_STEERING_MODE_DMFS);
7dc84de9 1844 atomic64_set(&esw->user_count, 0);
69697b6e 1845}
c116c6ee 1846
8ea7bcf6 1847static int esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch *esw)
4f4edcc2
AL		 1848{
1849 int nvports;
1850
1851 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1852 if (mlx5e_tc_int_port_supported(esw))
1853 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1854
1855 return nvports;
1856}
1857
8d6bd3c3 1858static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1859{
b3ba5149 1860 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1861 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1862 struct mlx5_flow_table *ft_offloads;
1863 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1864 int err = 0;
1865
1866 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1867 if (!ns) {
1868 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1869 return -EOPNOTSUPP;
c116c6ee
OG		 1870 }
1871
8ea7bcf6
JL		 1872 ft_attr.max_fte = esw_get_nr_ft_offloads_steering_src_ports(esw) +
1873 MLX5_ESW_FT_OFFLOADS_DROP_RULE;
11b717d6 1874 ft_attr.prio = 1;
b3ba5149
ES		 1875
1876 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1877 if (IS_ERR(ft_offloads)) {
1878 err = PTR_ERR(ft_offloads);
1879 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1880 return err;
1881 }
1882
1883 esw->offloads.ft_offloads = ft_offloads;
1884 return 0;
1885}
1886
1887static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1888{
1889 struct mlx5_esw_offload *offloads = &esw->offloads;
1890
1891 mlx5_destroy_flow_table(offloads->ft_offloads);
1892}
fed9ce22 1893
8d6bd3c3 1894static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1895{
1896 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1897 struct mlx5_flow_group *g;
fed9ce22 1898 u32 *flow_group_in;
8d6bd3c3 1899 int nvports;
fed9ce22 1900 int err = 0;
fed9ce22 1901
8ea7bcf6 1902 nvports = esw_get_nr_ft_offloads_steering_src_ports(esw);
1b9a07ee 1903 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1904 if (!flow_group_in)
1905 return -ENOMEM;
1906
1907 /* create vport rx group */
7eb197fd 1908 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
fed9ce22
OG		 1909
1910 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1911 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1912
1913 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1914
1915 if (IS_ERR(g)) {
1916 err = PTR_ERR(g);
1917 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1918 goto out;
1919 }
1920
1921 esw->offloads.vport_rx_group = g;
1922out:
e574978a 1923 kvfree(flow_group_in);
fed9ce22
OG		 1924 return err;
1925}
1926
1927static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1928{
1929 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1930}
1931
8ea7bcf6
JL		 1932static int esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch *esw)
1933{
1934 /* ft_offloads table is enlarged by MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
1935 * for the drop rule, which is placed at the end of the table.
1936 * So return the total of vport and int_port as rule index.
1937 */
1938 return esw_get_nr_ft_offloads_steering_src_ports(esw);
1939}
1940
1941static int esw_create_vport_rx_drop_group(struct mlx5_eswitch *esw)
1942{
1943 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1944 struct mlx5_flow_group *g;
1945 u32 *flow_group_in;
1946 int flow_index;
1947 int err = 0;
1948
1949 flow_index = esw_create_vport_rx_drop_rule_index(esw);
1950
1951 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1952 if (!flow_group_in)
1953 return -ENOMEM;
1954
1955 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
1956 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
1957
1958 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1959
1960 if (IS_ERR(g)) {
1961 err = PTR_ERR(g);
1962 mlx5_core_warn(esw->dev, "Failed to create vport rx drop group err %d\n", err);
1963 goto out;
1964 }
1965
1966 esw->offloads.vport_rx_drop_group = g;
1967out:
1968 kvfree(flow_group_in);
1969 return err;
1970}
1971
1972static void esw_destroy_vport_rx_drop_group(struct mlx5_eswitch *esw)
1973{
1974 if (esw->offloads.vport_rx_drop_group)
1975 mlx5_destroy_flow_group(esw->offloads.vport_rx_drop_group);
1976}
1977
7eb197fd
RD		 1978void
1979mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
1980 u16 vport,
1981 struct mlx5_flow_spec *spec)
fed9ce22 1982{
fed9ce22
OG		 1983 void *misc;
1984
a5641cb5
JL		 1985 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1986 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1987 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1988 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1989
a5641cb5 1990 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1991 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1992 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1993
a5641cb5
JL		 1994 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1995 } else {
1996 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1997 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1998
1999 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2000 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2001
2002 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2003 }
7eb197fd
RD		 2004}
2005
2006struct mlx5_flow_handle *
2007mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
2008 struct mlx5_flow_destination *dest)
2009{
2010 struct mlx5_flow_act flow_act = {0};
2011 struct mlx5_flow_handle *flow_rule;
2012 struct mlx5_flow_spec *spec;
2013
2014 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2015 if (!spec) {
2016 flow_rule = ERR_PTR(-ENOMEM);
2017 goto out;
2018 }
2019
2020 mlx5_esw_set_spec_source_port(esw, vport, spec);
fed9ce22 2021
66958ed9 2022 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 2023 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 2024 &flow_act, dest, 1);
fed9ce22
OG		 2025 if (IS_ERR(flow_rule)) {
2026 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
2027 goto out;
2028 }
2029
2030out:
c5bb1730 2031 kvfree(spec);
fed9ce22
OG		 2032 return flow_rule;
2033}
feae9087 2034
8ea7bcf6
JL		 2035static int esw_create_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2036{
2037 struct mlx5_flow_act flow_act = {};
2038 struct mlx5_flow_handle *flow_rule;
2039
2040 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2041 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, NULL,
2042 &flow_act, NULL, 0);
2043 if (IS_ERR(flow_rule)) {
2044 esw_warn(esw->dev,
2045 "fs offloads: Failed to add vport rx drop rule err %ld\n",
2046 PTR_ERR(flow_rule));
2047 return PTR_ERR(flow_rule);
2048 }
2049
2050 esw->offloads.vport_rx_drop_rule = flow_rule;
2051
2052 return 0;
2053}
2054
2055static void esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2056{
2057 if (esw->offloads.vport_rx_drop_rule)
2058 mlx5_del_flow_rules(esw->offloads.vport_rx_drop_rule);
2059}
2060
47dd7e60 2061static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
cc617ced
PP		 2062{
2063 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2064 struct mlx5_core_dev *dev = esw->dev;
47dd7e60
PP		 2065 struct mlx5_vport *vport;
2066 unsigned long i;
cc617ced
PP		 2067
2068 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2069 return -EOPNOTSUPP;
2070
f019679e 2071 if (!mlx5_esw_is_fdb_created(esw))
cc617ced
PP		 2072 return -EOPNOTSUPP;
2073
2074 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2075 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2076 mlx5_mode = MLX5_INLINE_MODE_NONE;
2077 goto out;
2078 case MLX5_CAP_INLINE_MODE_L2:
2079 mlx5_mode = MLX5_INLINE_MODE_L2;
2080 goto out;
2081 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2082 goto query_vports;
2083 }
2084
2085query_vports:
2086 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
47dd7e60
PP		 2087 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2088 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
cc617ced
PP		 2089 if (prev_mlx5_mode != mlx5_mode)
2090 return -EINVAL;
2091 prev_mlx5_mode = mlx5_mode;
2092 }
2093
2094out:
2095 *mode = mlx5_mode;
2096 return 0;
e08a6832 2097}
bf3347c4 2098
11b717d6
PB		 2099static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2100{
2101 struct mlx5_esw_offload *offloads = &esw->offloads;
2102
60acc105
PB		 2103 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2104 return;
2105
6724e66b 2106 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 2107 mlx5_destroy_flow_group(offloads->restore_group);
2108 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2109}
2110
2111static int esw_create_restore_table(struct mlx5_eswitch *esw)
2112{
d65dbedf 2113 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 2114 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2115 struct mlx5_flow_table_attr ft_attr = {};
2116 struct mlx5_core_dev *dev = esw->dev;
2117 struct mlx5_flow_namespace *ns;
6724e66b 2118 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 2119 void *match_criteria, *misc;
2120 struct mlx5_flow_table *ft;
2121 struct mlx5_flow_group *g;
2122 u32 *flow_group_in;
2123 int err = 0;
2124
60acc105
PB		 2125 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2126 return 0;
2127
11b717d6
PB		 2128 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2129 if (!ns) {
2130 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2131 return -EOPNOTSUPP;
2132 }
2133
2134 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2135 if (!flow_group_in) {
2136 err = -ENOMEM;
2137 goto out_free;
2138 }
2139
a91d98a0 2140 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
11b717d6
PB		 2141 ft = mlx5_create_flow_table(ns, &ft_attr);
2142 if (IS_ERR(ft)) {
2143 err = PTR_ERR(ft);
2144 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2145 err);
2146 goto out_free;
2147 }
2148
11b717d6
PB		 2149 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2150 match_criteria);
2151 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2152 misc_parameters_2);
2153
2154 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 2155 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 2156 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2157 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2158 ft_attr.max_fte - 1);
2159 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2160 MLX5_MATCH_MISC_PARAMETERS_2);
2161 g = mlx5_create_flow_group(ft, flow_group_in);
2162 if (IS_ERR(g)) {
2163 err = PTR_ERR(g);
2164 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2165 err);
2166 goto err_group;
2167 }
2168
6724e66b
PB		 2169 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2170 MLX5_SET(copy_action_in, modact, src_field,
2171 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2172 MLX5_SET(copy_action_in, modact, dst_field,
2173 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2174 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2175 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2176 modact);
2177 if (IS_ERR(mod_hdr)) {
e9864539 2178 err = PTR_ERR(mod_hdr);
6724e66b
PB		 2179 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2180 err);
6724e66b
PB		 2181 goto err_mod_hdr;
2182 }
2183
11b717d6
PB		 2184 esw->offloads.ft_offloads_restore = ft;
2185 esw->offloads.restore_group = g;
6724e66b 2186 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 2187
c8508713
RD		 2188 kvfree(flow_group_in);
2189
11b717d6
PB		 2190 return 0;
2191
6724e66b
PB		 2192err_mod_hdr:
2193 mlx5_destroy_flow_group(g);
11b717d6
PB		 2194err_group:
2195 mlx5_destroy_flow_table(ft);
2196out_free:
2197 kvfree(flow_group_in);
2198
2199 return err;
cc617ced
PP		 2200}
2201
db7ff19e
EB		 2202static int esw_offloads_start(struct mlx5_eswitch *esw,
2203 struct netlink_ext_ack *extack)
c930a3ad 2204{
e12de39c 2205 int err;
c930a3ad 2206
b6f2846a
CM		 2207 esw->mode = MLX5_ESWITCH_OFFLOADS;
2208 err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
6c419ba8 2209 if (err) {
8c98ee77
EB		 2210 NL_SET_ERR_MSG_MOD(extack,
2211 "Failed setting eswitch to offloads");
b6f2846a 2212 esw->mode = MLX5_ESWITCH_LEGACY;
b6f2846a 2213 mlx5_rescan_drivers(esw->dev);
97bd788e 2214 return err;
6c419ba8 2215 }
bffaa916
RD		 2216 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2217 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 2218 &esw->offloads.inline_mode)) {
2219 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 2220 NL_SET_ERR_MSG_MOD(extack,
2221 "Inline mode is different between vports");
bffaa916
RD		 2222 }
2223 }
97bd788e 2224 return 0;
c930a3ad
OG		 2225}
2226
47dd7e60 2227static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
e8d31c4d 2228{
e8d31c4d 2229 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 2230 int rep_type;
2231 int err;
e8d31c4d 2232
47dd7e60
PP		 2233 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2234 if (!rep)
e8d31c4d
MB		 2235 return -ENOMEM;
2236
47dd7e60
PP		 2237 rep->vport = vport->vport;
2238 rep->vport_index = vport->index;
2239 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2240 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
f121e0ea 2241
47dd7e60
PP		 2242 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2243 if (err)
2244 goto insert_err;
2245
47dd7e60
PP		 2246 return 0;
2247
2248insert_err:
2249 kfree(rep);
2250 return err;
2251}
2252
2253static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2254 struct mlx5_eswitch_rep *rep)
2255{
2256 xa_erase(&esw->offloads.vport_reps, rep->vport);
2257 kfree(rep);
2258}
2259
d2a651ef 2260static void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
47dd7e60
PP		 2261{
2262 struct mlx5_eswitch_rep *rep;
2263 unsigned long i;
e8d31c4d 2264
47dd7e60
PP		 2265 mlx5_esw_for_each_rep(esw, i, rep)
2266 mlx5_esw_offloads_rep_cleanup(esw, rep);
2267 xa_destroy(&esw->offloads.vport_reps);
2268}
2269
d2a651ef 2270static int esw_offloads_init_reps(struct mlx5_eswitch *esw)
47dd7e60
PP		 2271{
2272 struct mlx5_vport *vport;
2273 unsigned long i;
2274 int err;
2275
2276 xa_init(&esw->offloads.vport_reps);
2277
2278 mlx5_esw_for_each_vport(esw, i, vport) {
2279 err = mlx5_esw_offloads_rep_init(esw, vport);
2280 if (err)
2281 goto err;
2282 }
e8d31c4d 2283 return 0;
47dd7e60
PP		 2284
2285err:
2286 esw_offloads_cleanup_reps(esw);
2287 return err;
e8d31c4d
MB		 2288}
2289
d2a651ef
JP		 2290static int esw_port_metadata_set(struct devlink *devlink, u32 id,
2291 struct devlink_param_gset_ctx *ctx)
2292{
2293 struct mlx5_core_dev *dev = devlink_priv(devlink);
2294 struct mlx5_eswitch *esw = dev->priv.eswitch;
2295 int err = 0;
2296
2297 down_write(&esw->mode_lock);
2298 if (mlx5_esw_is_fdb_created(esw)) {
2299 err = -EBUSY;
2300 goto done;
2301 }
2302 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2303 err = -EOPNOTSUPP;
2304 goto done;
2305 }
2306 if (ctx->val.vbool)
2307 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2308 else
2309 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2310done:
2311 up_write(&esw->mode_lock);
2312 return err;
2313}
2314
2315static int esw_port_metadata_get(struct devlink *devlink, u32 id,
2316 struct devlink_param_gset_ctx *ctx)
2317{
2318 struct mlx5_core_dev *dev = devlink_priv(devlink);
2319
2320 ctx->val.vbool = mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch);
2321 return 0;
2322}
2323
2324static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
2325 union devlink_param_value val,
2326 struct netlink_ext_ack *extack)
2327{
2328 struct mlx5_core_dev *dev = devlink_priv(devlink);
2329 u8 esw_mode;
2330
2331 esw_mode = mlx5_eswitch_mode(dev);
2332 if (esw_mode == MLX5_ESWITCH_OFFLOADS) {
2333 NL_SET_ERR_MSG_MOD(extack,
2334 "E-Switch must either disabled or non switchdev mode");
2335 return -EBUSY;
2336 }
2337 return 0;
2338}
2339
2340static const struct devlink_param esw_devlink_params[] = {
2341 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
2342 "esw_port_metadata", DEVLINK_PARAM_TYPE_BOOL,
2343 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2344 esw_port_metadata_get,
2345 esw_port_metadata_set,
2346 esw_port_metadata_validate),
2347};
2348
2349int esw_offloads_init(struct mlx5_eswitch *esw)
2350{
2351 int err;
2352
2353 err = esw_offloads_init_reps(esw);
2354 if (err)
2355 return err;
2356
2357 err = devl_params_register(priv_to_devlink(esw->dev),
2358 esw_devlink_params,
2359 ARRAY_SIZE(esw_devlink_params));
2360 if (err)
2361 goto err_params;
2362
2363 return 0;
2364
2365err_params:
2366 esw_offloads_cleanup_reps(esw);
2367 return err;
2368}
2369
2370void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2371{
2372 devl_params_unregister(priv_to_devlink(esw->dev),
2373 esw_devlink_params,
2374 ARRAY_SIZE(esw_devlink_params));
2375 esw_offloads_cleanup_reps(esw);
2376}
2377
c9b99abc
BW		 2378static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2379 struct mlx5_eswitch_rep *rep, u8 rep_type)
2380{
8693115a 2381 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 2382 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 2383 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 2384}
2385
4110fc59 2386static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 2387{
2388 struct mlx5_eswitch_rep *rep;
47dd7e60 2389 unsigned long i;
4110fc59 2390
18a92b05 2391 mlx5_esw_for_each_rep(esw, i, rep)
81cd229c 2392 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2393}
2394
d970812b 2395int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 2396{
c2d7712c
BW		 2397 struct mlx5_eswitch_rep *rep;
2398 int rep_type;
a4b97ab4
MB		 2399 int err;
2400
c2d7712c
BW		 2401 rep = mlx5_eswitch_get_rep(esw, vport_num);
2402 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2403 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2404 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2405 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2406 if (err)
2407 goto err_reps;
2408 }
2409
2410 return 0;
a4b97ab4
MB		 2411
2412err_reps:
c2d7712c
BW		 2413 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2414 for (--rep_type; rep_type >= 0; rep_type--)
2415 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2416 return err;
2417}
2418
d970812b 2419void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 2420{
2421 struct mlx5_eswitch_rep *rep;
2422 int rep_type;
2423
c2d7712c
BW		 2424 rep = mlx5_eswitch_get_rep(esw, vport_num);
2425 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2426 __esw_offloads_unload_rep(esw, rep, rep_type);
2427}
2428
38679b5a
PP		 2429int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2430{
2431 int err;
2432
2433 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2434 return 0;
2435
865d6d1c
RD		 2436 if (vport_num != MLX5_VPORT_UPLINK) {
2437 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2438 if (err)
2439 return err;
2440 }
c7eddc60 2441
38679b5a 2442 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 2443 if (err)
2444 goto load_err;
2445 return err;
2446
2447load_err:
865d6d1c
RD		 2448 if (vport_num != MLX5_VPORT_UPLINK)
2449 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2450 return err;
2451}
2452
2453void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2454{
2455 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2456 return;
2457
2458 mlx5_esw_offloads_rep_unload(esw, vport_num);
865d6d1c
RD		 2459
2460 if (vport_num != MLX5_VPORT_UPLINK)
2461 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2462}
2463
db202995
MB		 2464static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2465 struct mlx5_core_dev *slave)
2466{
2467 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2468 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2469 struct mlx5_flow_root_namespace *root;
2470 struct mlx5_flow_namespace *ns;
2471 int err;
2472
2473 MLX5_SET(set_flow_table_root_in, in, opcode,
2474 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2475 MLX5_SET(set_flow_table_root_in, in, table_type,
2476 FS_FT_FDB);
2477
2478 if (master) {
2479 ns = mlx5_get_flow_namespace(master,
2480 MLX5_FLOW_NAMESPACE_FDB);
2481 root = find_root(&ns->node);
2482 mutex_lock(&root->chain_lock);
2483 MLX5_SET(set_flow_table_root_in, in,
2484 table_eswitch_owner_vhca_id_valid, 1);
2485 MLX5_SET(set_flow_table_root_in, in,
2486 table_eswitch_owner_vhca_id,
2487 MLX5_CAP_GEN(master, vhca_id));
2488 MLX5_SET(set_flow_table_root_in, in, table_id,
2489 root->root_ft->id);
2490 } else {
2491 ns = mlx5_get_flow_namespace(slave,
2492 MLX5_FLOW_NAMESPACE_FDB);
2493 root = find_root(&ns->node);
2494 mutex_lock(&root->chain_lock);
2495 MLX5_SET(set_flow_table_root_in, in, table_id,
2496 root->root_ft->id);
2497 }
2498
2499 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2500 mutex_unlock(&root->chain_lock);
2501
2502 return err;
2503}
2504
2505static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2506 struct mlx5_core_dev *slave,
2507 struct mlx5_vport *vport,
2508 struct mlx5_flow_table *acl)
2509{
5e0202eb 2510 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
db202995
MB		 2511 struct mlx5_flow_handle *flow_rule = NULL;
2512 struct mlx5_flow_destination dest = {};
2513 struct mlx5_flow_act flow_act = {};
2514 struct mlx5_flow_spec *spec;
2515 int err = 0;
2516 void *misc;
2517
2518 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2519 if (!spec)
2520 return -ENOMEM;
2521
2522 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2523 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2524 misc_parameters);
2525 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
5e0202eb 2526 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id, slave_index);
db202995
MB		 2527
2528 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2529 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2530 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2531 source_eswitch_owner_vhca_id);
2532
2533 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2534 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2535 dest.vport.num = slave->priv.eswitch->manager_vport;
2536 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2537 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2538
2539 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2540 &dest, 1);
5e0202eb 2541 if (IS_ERR(flow_rule)) {
db202995 2542 err = PTR_ERR(flow_rule);
5e0202eb
SD		 2543 } else {
2544 err = xa_insert(&vport->egress.offloads.bounce_rules,
2545 slave_index, flow_rule, GFP_KERNEL);
2546 if (err)
2547 mlx5_del_flow_rules(flow_rule);
2548 }
db202995
MB		 2549
2550 kvfree(spec);
2551 return err;
2552}
2553
5e0202eb 2554static int esw_master_egress_create_resources(struct mlx5_flow_namespace *egress_ns,
014e4d48 2555 struct mlx5_vport *vport, size_t count)
db202995
MB		 2556{
2557 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
db202995 2558 struct mlx5_flow_table_attr ft_attr = {
014e4d48 2559 .max_fte = count, .prio = 0, .level = 0,
43a0696f 2560 .flags = MLX5_FLOW_TABLE_OTHER_VPORT,
db202995 2561 };
db202995
MB		 2562 struct mlx5_flow_table *acl;
2563 struct mlx5_flow_group *g;
db202995
MB		 2564 void *match_criteria;
2565 u32 *flow_group_in;
2566 int err;
2567
db202995 2568 if (vport->egress.acl)
5e0202eb 2569 return 0;
db202995
MB		 2570
2571 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2572 if (!flow_group_in)
2573 return -ENOMEM;
2574
2575 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2576 if (IS_ERR(acl)) {
2577 err = PTR_ERR(acl);
2578 goto out;
2579 }
2580
2581 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2582 match_criteria);
2583 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2584 misc_parameters.source_port);
2585 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2586 misc_parameters.source_eswitch_owner_vhca_id);
2587 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2588 MLX5_MATCH_MISC_PARAMETERS);
2589
2590 MLX5_SET(create_flow_group_in, flow_group_in,
2591 source_eswitch_owner_vhca_id_valid, 1);
2592 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
014e4d48 2593 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, count);
db202995
MB		 2594
2595 g = mlx5_create_flow_group(acl, flow_group_in);
2596 if (IS_ERR(g)) {
2597 err = PTR_ERR(g);
2598 goto err_group;
2599 }
2600
db202995
MB		 2601 vport->egress.acl = acl;
2602 vport->egress.offloads.bounce_grp = g;
5e0202eb
SD		 2603 vport->egress.type = VPORT_EGRESS_ACL_TYPE_SHARED_FDB;
2604 xa_init_flags(&vport->egress.offloads.bounce_rules, XA_FLAGS_ALLOC);
db202995
MB		 2605
2606 kvfree(flow_group_in);
2607
2608 return 0;
2609
db202995
MB		 2610err_group:
2611 mlx5_destroy_flow_table(acl);
2612out:
2613 kvfree(flow_group_in);
2614 return err;
2615}
2616
5e0202eb
SD		 2617static void esw_master_egress_destroy_resources(struct mlx5_vport *vport)
2618{
2619 mlx5_destroy_flow_group(vport->egress.offloads.bounce_grp);
2620 mlx5_destroy_flow_table(vport->egress.acl);
2621}
2622
2623static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
014e4d48 2624 struct mlx5_core_dev *slave, size_t count)
5e0202eb
SD		 2625{
2626 struct mlx5_eswitch *esw = master->priv.eswitch;
2627 u16 slave_index = MLX5_CAP_GEN(slave, vhca_id);
2628 struct mlx5_flow_namespace *egress_ns;
2629 struct mlx5_vport *vport;
2630 int err;
2631
2632 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2633 if (IS_ERR(vport))
2634 return PTR_ERR(vport);
2635
2636 egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2637 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2638 vport->index);
2639 if (!egress_ns)
2640 return -EINVAL;
2641
2642 if (vport->egress.acl && vport->egress.type != VPORT_EGRESS_ACL_TYPE_SHARED_FDB)
2643 return 0;
2644
014e4d48 2645 err = esw_master_egress_create_resources(egress_ns, vport, count);
5e0202eb
SD		 2646 if (err)
2647 return err;
2648
2649 if (xa_load(&vport->egress.offloads.bounce_rules, slave_index))
2650 return -EINVAL;
2651
2652 err = __esw_set_master_egress_rule(master, slave, vport, vport->egress.acl);
2653 if (err)
2654 goto err_rule;
2655
2656 return 0;
2657
2658err_rule:
2659 esw_master_egress_destroy_resources(vport);
2660 return err;
2661}
2662
014e4d48
SD		 2663static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev,
2664 struct mlx5_core_dev *slave_dev)
db202995
MB		 2665{
2666 struct mlx5_vport *vport;
2667
2668 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2669 dev->priv.eswitch->manager_vport);
2670
014e4d48
SD		 2671 esw_acl_egress_ofld_bounce_rule_destroy(vport, MLX5_CAP_GEN(slave_dev, vhca_id));
2672
2673 if (xa_empty(&vport->egress.offloads.bounce_rules)) {
2674 esw_acl_egress_ofld_cleanup(vport);
2675 xa_destroy(&vport->egress.offloads.bounce_rules);
2676 }
db202995
MB		 2677}
2678
014e4d48
SD		 2679int mlx5_eswitch_offloads_single_fdb_add_one(struct mlx5_eswitch *master_esw,
2680 struct mlx5_eswitch *slave_esw, int max_slaves)
db202995
MB		 2681{
2682 int err;
2683
db202995
MB		 2684 err = esw_set_slave_root_fdb(master_esw->dev,
2685 slave_esw->dev);
2686 if (err)
82e86a6c 2687 return err;
db202995
MB		 2688
2689 err = esw_set_master_egress_rule(master_esw->dev,
014e4d48 2690 slave_esw->dev, max_slaves);
db202995
MB		 2691 if (err)
2692 goto err_acl;
2693
2694 return err;
2695
2696err_acl:
2697 esw_set_slave_root_fdb(NULL, slave_esw->dev);
db202995
MB		 2698 return err;
2699}
2700
014e4d48 2701void mlx5_eswitch_offloads_single_fdb_del_one(struct mlx5_eswitch *master_esw,
db202995
MB		 2702 struct mlx5_eswitch *slave_esw)
2703{
db202995 2704 esw_set_slave_root_fdb(NULL, slave_esw->dev);
014e4d48 2705 esw_unset_master_egress_rule(master_esw->dev, slave_esw->dev);
db202995
MB		 2706}
2707
ac004b83
RD		 2708#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2709#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2710
ed7a8fe7
MB		 2711static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw,
2712 struct mlx5_eswitch *peer_esw)
ac004b83 2713{
c8e6a9e6
MB		 2714 const struct mlx5_eswitch_rep_ops *ops;
2715 struct mlx5_eswitch_rep *rep;
2716 unsigned long i;
2717 u8 rep_type;
2718
2719 mlx5_esw_for_each_rep(esw, i, rep) {
2720 rep_type = NUM_REP_TYPES;
2721 while (rep_type--) {
2722 ops = esw->offloads.rep_ops[rep_type];
2723 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2724 ops->event)
ed7a8fe7 2725 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, peer_esw);
c8e6a9e6
MB		 2726 }
2727 }
ac004b83
RD		 2728}
2729
ed7a8fe7
MB		 2730static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,
2731 struct mlx5_eswitch *peer_esw)
ac004b83 2732{
d956873f 2733#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 2734 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 2735#endif
ed7a8fe7 2736 mlx5_esw_offloads_rep_event_unpair(esw, peer_esw);
9bee385a 2737 esw_del_fdb_peer_miss_rules(esw, peer_esw->dev);
ac004b83
RD		 2738}
2739
c8e6a9e6
MB		 2740static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2741 struct mlx5_eswitch *peer_esw)
2742{
2743 const struct mlx5_eswitch_rep_ops *ops;
2744 struct mlx5_eswitch_rep *rep;
2745 unsigned long i;
2746 u8 rep_type;
2747 int err;
2748
2749 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2750 if (err)
2751 return err;
2752
2753 mlx5_esw_for_each_rep(esw, i, rep) {
2754 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2755 ops = esw->offloads.rep_ops[rep_type];
2756 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2757 ops->event) {
2758 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2759 if (err)
2760 goto err_out;
2761 }
2762 }
2763 }
2764
2765 return 0;
2766
2767err_out:
ed7a8fe7 2768 mlx5_esw_offloads_unpair(esw, peer_esw);
c8e6a9e6
MB		 2769 return err;
2770}
2771
8463daf1
MG		 2772static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2773 struct mlx5_eswitch *peer_esw,
2774 bool pair)
2775{
6d5b7321 2776 u8 peer_idx = mlx5_get_dev_index(peer_esw->dev);
8463daf1 2777 struct mlx5_flow_root_namespace *peer_ns;
6d5b7321 2778 u8 idx = mlx5_get_dev_index(esw->dev);
8463daf1
MG		 2779 struct mlx5_flow_root_namespace *ns;
2780 int err;
2781
2782 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2783 ns = esw->dev->priv.steering->fdb_root_ns;
2784
2785 if (pair) {
6d5b7321 2786 err = mlx5_flow_namespace_set_peer(ns, peer_ns, peer_idx);
8463daf1
MG		 2787 if (err)
2788 return err;
2789
6d5b7321 2790 err = mlx5_flow_namespace_set_peer(peer_ns, ns, idx);
8463daf1 2791 if (err) {
6d5b7321 2792 mlx5_flow_namespace_set_peer(ns, NULL, peer_idx);
8463daf1
MG		 2793 return err;
2794 }
2795 } else {
6d5b7321
SD		 2796 mlx5_flow_namespace_set_peer(ns, NULL, peer_idx);
2797 mlx5_flow_namespace_set_peer(peer_ns, NULL, idx);
8463daf1
MG		 2798 }
2799
2800 return 0;
2801}
2802
ac004b83
RD		 2803static int mlx5_esw_offloads_devcom_event(int event,
2804 void *my_data,
2805 void *event_data)
2806{
2807 struct mlx5_eswitch *esw = my_data;
ac004b83 2808 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 2809 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 2810 int err;
2811
2812 switch (event) {
2813 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 2814 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2815 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2816 break;
2817
8c253dfc
SD		 2818 if (esw->paired[mlx5_get_dev_index(peer_esw->dev)])
2819 break;
2820
8463daf1 2821 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 2822 if (err)
2823 goto err_out;
8463daf1
MG		 2824 err = mlx5_esw_offloads_pair(esw, peer_esw);
2825 if (err)
2826 goto err_peer;
ac004b83
RD		 2827
2828 err = mlx5_esw_offloads_pair(peer_esw, esw);
2829 if (err)
2830 goto err_pair;
2831
8c253dfc
SD		 2832 esw->paired[mlx5_get_dev_index(peer_esw->dev)] = true;
2833 peer_esw->paired[mlx5_get_dev_index(esw->dev)] = true;
8611df72
SD		 2834 esw->num_peers++;
2835 peer_esw->num_peers++;
e67f928a 2836 mlx5_devcom_comp_set_ready(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
ac004b83
RD		 2837 break;
2838
2839 case ESW_OFFLOADS_DEVCOM_UNPAIR:
8c253dfc 2840 if (!esw->paired[mlx5_get_dev_index(peer_esw->dev)])
ac004b83
RD		 2841 break;
2842
8611df72
SD		 2843 peer_esw->num_peers--;
2844 esw->num_peers--;
2845 if (!esw->num_peers && !peer_esw->num_peers)
2846 mlx5_devcom_comp_set_ready(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
8c253dfc
SD		 2847 esw->paired[mlx5_get_dev_index(peer_esw->dev)] = false;
2848 peer_esw->paired[mlx5_get_dev_index(esw->dev)] = false;
ed7a8fe7
MB		 2849 mlx5_esw_offloads_unpair(peer_esw, esw);
2850 mlx5_esw_offloads_unpair(esw, peer_esw);
8463daf1 2851 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2852 break;
2853 }
2854
2855 return 0;
2856
2857err_pair:
ed7a8fe7 2858 mlx5_esw_offloads_unpair(esw, peer_esw);
8463daf1
MG		 2859err_peer:
2860 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2861err_out:
2862 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2863 event, err);
2864 return err;
2865}
2866
2be5bd42 2867void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw)
ac004b83
RD		 2868{
2869 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
9be6c21f 2870 int i;
ac004b83 2871
9be6c21f
SD		 2872 for (i = 0; i < MLX5_MAX_PORTS; i++)
2873 INIT_LIST_HEAD(&esw->offloads.peer_flows[i]);
04de7dda
RD		 2874 mutex_init(&esw->offloads.peer_mutex);
2875
ac004b83
RD		 2876 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2877 return;
2878
8ec91f5d 2879 if (!mlx5_lag_is_supported(esw->dev))
3008e6a0
MB		 2880 return;
2881
ac004b83
RD		 2882 mlx5_devcom_register_component(devcom,
2883 MLX5_DEVCOM_ESW_OFFLOADS,
2884 mlx5_esw_offloads_devcom_event,
2885 esw);
2886
8611df72 2887 esw->num_peers = 0;
ac004b83
RD		 2888 mlx5_devcom_send_event(devcom,
2889 MLX5_DEVCOM_ESW_OFFLOADS,
e2a82bf8
SD		 2890 ESW_OFFLOADS_DEVCOM_PAIR,
2891 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
ac004b83
RD		 2892}
2893
2be5bd42 2894void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
ac004b83
RD		 2895{
2896 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2897
2898 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2899 return;
2900
8ec91f5d 2901 if (!mlx5_lag_is_supported(esw->dev))
3008e6a0
MB		 2902 return;
2903
ac004b83 2904 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
e2a82bf8 2905 ESW_OFFLOADS_DEVCOM_UNPAIR,
ac004b83
RD		 2906 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2907
2908 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2909}
2910
7bf481d7 2911bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
92ab1eb3
JL		 2912{
2913 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2914 return false;
2915
2916 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2917 MLX5_FDB_TO_VPORT_REG_C_0))
2918 return false;
2919
92ab1eb3
JL		 2920 return true;
2921}
2922
0b0ea3c5
SR		 2923#define MLX5_ESW_METADATA_RSVD_UPLINK 1
2924
2925/* Share the same metadata for uplink's. This is fine because:
2926 * (a) In shared FDB mode (LAG) both uplink's are treated the
2927 * same and tagged with the same metadata.
2928 * (b) In non shared FDB mode, packets from physical port0
2929 * cannot hit eswitch of PF1 and vice versa.
2930 */
2931static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw)
2932{
2933 return MLX5_ESW_METADATA_RSVD_UPLINK;
2934}
2935
133dcfc5
VP		 2936u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2937{
7cd7becd 2938 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
4f4edcc2
AL		 2939 /* Reserve 0xf for internal port offload */
2940 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
7cd7becd 2941 u32 pf_num;
133dcfc5
VP		 2942 int id;
2943
7cd7becd 2944 /* Only 4 bits of pf_num */
2ec16ddd 2945 pf_num = mlx5_get_dev_index(esw->dev);
7cd7becd 2946 if (pf_num > max_pf_num)
2947 return 0;
133dcfc5 2948
7cd7becd 2949 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
0b0ea3c5
SR		 2950 /* Use only non-zero vport_id (2-4095) for all PF's */
2951 id = ida_alloc_range(&esw->offloads.vport_metadata_ida,
2952 MLX5_ESW_METADATA_RSVD_UPLINK + 1,
2953 vport_end_ida, GFP_KERNEL);
7cd7becd 2954 if (id < 0)
2955 return 0;
2956 id = (pf_num << ESW_VPORT_BITS) | id;
2957 return id;
133dcfc5
VP		 2958}
2959
2960void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2961{
7cd7becd 2962 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2963
2964 /* Metadata contains only 12 bits of actual ida id */
2965 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2966}
2967
2968static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2969 struct mlx5_vport *vport)
2970{
0b0ea3c5
SR		 2971 if (vport->vport == MLX5_VPORT_UPLINK)
2972 vport->default_metadata = mlx5_esw_match_metadata_reserved(esw);
2973 else
2974 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2975
133dcfc5
VP		 2976 vport->metadata = vport->default_metadata;
2977 return vport->metadata ? 0 : -ENOSPC;
2978}
2979
2980static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2981 struct mlx5_vport *vport)
2982{
406493a5 2983 if (!vport->default_metadata)
133dcfc5
VP		 2984 return;
2985
0b0ea3c5
SR		 2986 if (vport->vport == MLX5_VPORT_UPLINK)
2987 return;
2988
133dcfc5
VP		 2989 WARN_ON(vport->metadata != vport->default_metadata);
2990 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2991}
2992
fc99c3d6
VP		 2993static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2994{
2995 struct mlx5_vport *vport;
47dd7e60 2996 unsigned long i;
fc99c3d6
VP		 2997
2998 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2999 return;
3000
47dd7e60 3001 mlx5_esw_for_each_vport(esw, i, vport)
fc99c3d6
VP		 3002 esw_offloads_vport_metadata_cleanup(esw, vport);
3003}
3004
3005static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
3006{
3007 struct mlx5_vport *vport;
47dd7e60 3008 unsigned long i;
fc99c3d6 3009 int err;
fc99c3d6
VP		 3010
3011 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
3012 return 0;
3013
47dd7e60 3014 mlx5_esw_for_each_vport(esw, i, vport) {
fc99c3d6
VP		 3015 err = esw_offloads_vport_metadata_setup(esw, vport);
3016 if (err)
3017 goto metadata_err;
3018 }
3019
3020 return 0;
3021
3022metadata_err:
3023 esw_offloads_metadata_uninit(esw);
3024 return err;
3025}
3026
748da30b 3027int
89a0f1fb
PP		 3028esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
3029 struct mlx5_vport *vport)
7445cfb1 3030{
7445cfb1
JL		 3031 int err;
3032
07bab950 3033 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 3034 if (err)
fc99c3d6 3035 return err;
7445cfb1 3036
2c40db2f
PP		 3037 err = esw_acl_egress_ofld_setup(esw, vport);
3038 if (err)
3039 goto egress_err;
07bab950
VP		 3040
3041 return 0;
3042
3043egress_err:
3044 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 3045 return err;
3046}
18486737 3047
748da30b 3048void
89a0f1fb
PP		 3049esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
3050 struct mlx5_vport *vport)
3051{
ea651a86 3052 esw_acl_egress_ofld_cleanup(vport);
07bab950 3053 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 3054}
7445cfb1 3055
748da30b 3056static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 3057{
3058 struct mlx5_vport *vport;
18486737 3059
748da30b 3060 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 3061 if (IS_ERR(vport))
3062 return PTR_ERR(vport);
3063
4e9a9ef7 3064 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 3065}
3066
748da30b 3067static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 3068{
786ef904 3069 struct mlx5_vport *vport;
7445cfb1 3070
748da30b 3071 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 3072 if (IS_ERR(vport))
3073 return;
3074
748da30b 3075 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 3076}
3077
db202995
MB		 3078int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw)
3079{
3080 struct mlx5_eswitch_rep *rep;
3081 unsigned long i;
3082 int ret;
3083
3084 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
3085 return 0;
3086
3087 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3088 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
3089 return 0;
3090
3091 ret = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3092 if (ret)
3093 return ret;
3094
3095 mlx5_esw_for_each_rep(esw, i, rep) {
3096 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
3097 mlx5_esw_offloads_rep_load(esw, rep->vport);
3098 }
3099
3100 return 0;
3101}
3102
062f4bf4 3103static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 3104{
34ca6535 3105 struct mlx5_esw_indir_table *indir;
6ed1803a
MB		 3106 int err;
3107
5c1d260e 3108 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 3109 mutex_init(&esw->fdb_table.offloads.vports.lock);
3110 hash_init(esw->fdb_table.offloads.vports.table);
7dc84de9 3111 atomic64_set(&esw->user_count, 0);
e52c2802 3112
34ca6535
VB		 3113 indir = mlx5_esw_indir_table_init();
3114 if (IS_ERR(indir)) {
3115 err = PTR_ERR(indir);
3116 goto create_indir_err;
3117 }
3118 esw->fdb_table.offloads.indir = indir;
3119
748da30b 3120 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 3121 if (err)
f8d1edda 3122 goto create_acl_err;
18486737 3123
8d6bd3c3 3124 err = esw_create_offloads_table(esw);
c930a3ad 3125 if (err)
11b717d6 3126 goto create_offloads_err;
c930a3ad 3127
11b717d6 3128 err = esw_create_restore_table(esw);
c930a3ad 3129 if (err)
11b717d6
PB		 3130 goto create_restore_err;
3131
0da3c12d 3132 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 3133 if (err)
3134 goto create_fdb_err;
c930a3ad 3135
8d6bd3c3 3136 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 3137 if (err)
3138 goto create_fg_err;
3139
8ea7bcf6
JL		 3140 err = esw_create_vport_rx_drop_group(esw);
3141 if (err)
3142 goto create_rx_drop_fg_err;
3143
3144 err = esw_create_vport_rx_drop_rule(esw);
3145 if (err)
3146 goto create_rx_drop_rule_err;
3147
c930a3ad
OG		 3148 return 0;
3149
8ea7bcf6
JL		 3150create_rx_drop_rule_err:
3151 esw_destroy_vport_rx_drop_group(esw);
3152create_rx_drop_fg_err:
3153 esw_destroy_vport_rx_group(esw);
c930a3ad 3154create_fg_err:
1967ce6e 3155 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 3156create_fdb_err:
11b717d6
PB		 3157 esw_destroy_restore_table(esw);
3158create_restore_err:
3159 esw_destroy_offloads_table(esw);
3160create_offloads_err:
748da30b 3161 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 3162create_acl_err:
34ca6535
VB		 3163 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3164create_indir_err:
f8d1edda 3165 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 3166 return err;
3167}
3168
eca8cc38
BW		 3169static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3170{
8ea7bcf6
JL		 3171 esw_destroy_vport_rx_drop_rule(esw);
3172 esw_destroy_vport_rx_drop_group(esw);
eca8cc38 3173 esw_destroy_vport_rx_group(esw);
eca8cc38 3174 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 3175 esw_destroy_restore_table(esw);
3176 esw_destroy_offloads_table(esw);
748da30b 3177 esw_destroy_uplink_offloads_acl_tables(esw);
34ca6535 3178 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
f8d1edda 3179 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 3180}
3181
7e736f9a
PP		 3182static void
3183esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 3184{
f1bc646c 3185 struct devlink *devlink;
5ccf2770 3186 bool host_pf_disabled;
7e736f9a 3187 u16 new_num_vfs;
a3888f33 3188
7e736f9a
PP		 3189 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3190 host_params_context.host_num_of_vfs);
5ccf2770
BW		 3191 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3192 host_params_context.host_pf_disabled);
a3888f33 3193
7e736f9a
PP		 3194 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3195 return;
a3888f33 3196
f1bc646c
MS		 3197 devlink = priv_to_devlink(esw->dev);
3198 devl_lock(devlink);
a3888f33 3199 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 3200 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 3201 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 3202 } else {
7e736f9a 3203 int err;
a3888f33 3204
23bb50cf
BW		 3205 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3206 MLX5_VPORT_UC_ADDR_CHANGE);
b868c8fe
DC		 3207 if (err) {
3208 devl_unlock(devlink);
7e736f9a 3209 return;
b868c8fe 3210 }
a3888f33 3211 }
7e736f9a 3212 esw->esw_funcs.num_vfs = new_num_vfs;
f1bc646c 3213 devl_unlock(devlink);
a3888f33
BW		 3214}
3215
7e736f9a 3216static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 3217{
7e736f9a
PP		 3218 struct mlx5_host_work *host_work;
3219 struct mlx5_eswitch *esw;
dd28087c 3220 const u32 *out;
ac35dcd6 3221
7e736f9a
PP		 3222 host_work = container_of(work, struct mlx5_host_work, work);
3223 esw = host_work->esw;
a3888f33 3224
dd28087c
PP		 3225 out = mlx5_esw_query_functions(esw->dev);
3226 if (IS_ERR(out))
7e736f9a 3227 goto out;
a3888f33 3228
7e736f9a 3229 esw_vfs_changed_event_handler(esw, out);
dd28087c 3230 kvfree(out);
a3888f33 3231out:
ac35dcd6
VP		 3232 kfree(host_work);
3233}
3234
16fff98a 3235int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 3236{
cd56f929 3237 struct mlx5_esw_functions *esw_funcs;
a3888f33 3238 struct mlx5_host_work *host_work;
a3888f33
BW		 3239 struct mlx5_eswitch *esw;
3240
3241 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3242 if (!host_work)
3243 return NOTIFY_DONE;
3244
cd56f929
VP		 3245 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3246 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 3247
3248 host_work->esw = esw;
3249
062f4bf4 3250 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 3251 queue_work(esw->work_queue, &host_work->work);
3252
3253 return NOTIFY_OK;
3254}
3255
a53cf949
PP		 3256static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3257{
3258 const u32 *query_host_out;
3259
3260 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3261 return 0;
3262
3263 query_host_out = mlx5_esw_query_functions(esw->dev);
3264 if (IS_ERR(query_host_out))
3265 return PTR_ERR(query_host_out);
3266
3267 /* Mark non local controller with non zero controller number. */
3268 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3269 host_params_context.host_number);
3270 kvfree(query_host_out);
3271 return 0;
3272}
3273
f1b9acd3
PP		 3274bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3275{
3276 /* Local controller is always valid */
3277 if (controller == 0)
3278 return true;
3279
3280 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3281 return false;
3282
3283 /* External host number starts with zero in device */
3284 return (controller == esw->offloads.host_number + 1);
3285}
3286
5896b972 3287int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 3288{
c9355682 3289 struct mapping_ctx *reg_c0_obj_pool;
3b83b6c2 3290 struct mlx5_vport *vport;
47dd7e60 3291 unsigned long i;
2198b932 3292 u64 mapping_id;
47dd7e60 3293 int err;
eca8cc38 3294
2bb72e7e 3295 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 3296 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 3297
a53cf949
PP		 3298 err = mlx5_esw_host_number_init(esw);
3299 if (err)
cd1ef966 3300 goto err_metadata;
a53cf949 3301
fc99c3d6
VP		 3302 err = esw_offloads_metadata_init(esw);
3303 if (err)
3304 goto err_metadata;
3305
332bd3a5
PP		 3306 err = esw_set_passing_vport_metadata(esw, true);
3307 if (err)
3308 goto err_vport_metadata;
c1286050 3309
2198b932
RD		 3310 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3311
3312 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3313 sizeof(struct mlx5_mapped_obj),
3314 ESW_REG_C0_USER_DATA_METADATA_MASK,
3315 true);
3316
c9355682
CM		 3317 if (IS_ERR(reg_c0_obj_pool)) {
3318 err = PTR_ERR(reg_c0_obj_pool);
3319 goto err_pool;
3320 }
3321 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3322
7983a675
PB		 3323 err = esw_offloads_steering_init(esw);
3324 if (err)
3325 goto err_steering_init;
3326
3b83b6c2
DL		 3327 /* Representor will control the vport link state */
3328 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3329 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
a7719b29
DJ		 3330 if (mlx5_core_ec_sriov_enabled(esw->dev))
3331 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs)
3332 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3b83b6c2 3333
c2d7712c
BW		 3334 /* Uplink vport rep must load first. */
3335 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 3336 if (err)
c2d7712c 3337 goto err_uplink;
c1286050 3338
c2d7712c 3339 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 3340 if (err)
c2d7712c 3341 goto err_vports;
eca8cc38 3342
eca8cc38
BW		 3343 return 0;
3344
925a6acc 3345err_vports:
c2d7712c
BW		 3346 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
3347err_uplink:
7983a675 3348 esw_offloads_steering_cleanup(esw);
79949985 3349err_steering_init:
c9355682
CM		 3350 mapping_destroy(reg_c0_obj_pool);
3351err_pool:
79949985 3352 esw_set_passing_vport_metadata(esw, false);
7983a675 3353err_vport_metadata:
fc99c3d6
VP		 3354 esw_offloads_metadata_uninit(esw);
3355err_metadata:
8463daf1 3356 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 3357 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 3358 return err;
3359}
3360
db7ff19e
EB		 3361static int esw_offloads_stop(struct mlx5_eswitch *esw,
3362 struct netlink_ext_ack *extack)
c930a3ad 3363{
e12de39c 3364 int err;
c930a3ad 3365
b6f2846a 3366 esw->mode = MLX5_ESWITCH_LEGACY;
2318b8bb
CM		 3367
3368 /* If changing from switchdev to legacy mode without sriov enabled,
3369 * no need to create legacy fdb.
3370 */
bea416c7 3371 if (!mlx5_core_is_pf(esw->dev) || !mlx5_sriov_is_enabled(esw->dev))
2318b8bb
CM		 3372 return 0;
3373
b6f2846a 3374 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
e12de39c 3375 if (err)
8c98ee77 3376 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
c930a3ad
OG		 3377
3378 return err;
3379}
3380
5896b972 3381void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 3382{
5896b972 3383 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 3384 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 3385 esw_set_passing_vport_metadata(esw, false);
eca8cc38 3386 esw_offloads_steering_cleanup(esw);
c9355682 3387 mapping_destroy(esw->offloads.reg_c0_obj_pool);
fc99c3d6 3388 esw_offloads_metadata_uninit(esw);
8463daf1 3389 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 3390 mutex_destroy(&esw->offloads.termtbl_mutex);
c930a3ad
OG		 3391}
3392
ef78618b 3393static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 3394{
3395 switch (mode) {
3396 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 3397 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 3398 break;
3399 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 3400 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 3401 break;
3402 default:
3403 return -EINVAL;
3404 }
3405
3406 return 0;
3407}
3408
ef78618b
OG		 3409static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3410{
3411 switch (mlx5_mode) {
f6455de0 3412 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 3413 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3414 break;
f6455de0 3415 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 3416 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3417 break;
3418 default:
3419 return -EINVAL;
3420 }
3421
3422 return 0;
3423}
3424
bffaa916
RD		 3425static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3426{
3427 switch (mode) {
3428 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3429 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3430 break;
3431 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3432 *mlx5_mode = MLX5_INLINE_MODE_L2;
3433 break;
3434 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3435 *mlx5_mode = MLX5_INLINE_MODE_IP;
3436 break;
3437 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3438 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3439 break;
3440 default:
3441 return -EINVAL;
3442 }
3443
3444 return 0;
3445}
3446
3447static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3448{
3449 switch (mlx5_mode) {
3450 case MLX5_INLINE_MODE_NONE:
3451 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3452 break;
3453 case MLX5_INLINE_MODE_L2:
3454 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3455 break;
3456 case MLX5_INLINE_MODE_IP:
3457 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3458 break;
3459 case MLX5_INLINE_MODE_TCP_UDP:
3460 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3461 break;
3462 default:
3463 return -EINVAL;
3464 }
3465
3466 return 0;
3467}
3468
662404b2
GL		 3469static bool esw_offloads_devlink_ns_eq_netdev_ns(struct devlink *devlink)
3470{
3471 struct net *devl_net, *netdev_net;
3472 struct mlx5_eswitch *esw;
3473
3474 esw = mlx5_devlink_eswitch_get(devlink);
3475 netdev_net = dev_net(esw->dev->mlx5e_res.uplink_netdev);
3476 devl_net = devlink_net(devlink);
3477
3478 return net_eq(devl_net, netdev_net);
3479}
3480
db7ff19e
EB		 3481int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3482 struct netlink_ext_ack *extack)
9d1cef19 3483{
9d1cef19 3484 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 3485 struct mlx5_eswitch *esw;
ea2128fd 3486 int err = 0;
9d1cef19 3487
bd939753
PP		 3488 esw = mlx5_devlink_eswitch_get(devlink);
3489 if (IS_ERR(esw))
3490 return PTR_ERR(esw);
9d1cef19 3491
ef78618b 3492 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 3493 return -EINVAL;
3494
662404b2
GL		 3495 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV &&
3496 !esw_offloads_devlink_ns_eq_netdev_ns(devlink)) {
3497 NL_SET_ERR_MSG_MOD(extack,
3498 "Can't change E-Switch mode to switchdev when netdev net namespace has diverged from the devlink's.");
3499 return -EPERM;
3500 }
3501
cac1eb2c 3502 mlx5_lag_disable_change(esw->dev);
7dc84de9
RD		 3503 err = mlx5_esw_try_lock(esw);
3504 if (err < 0) {
3505 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
cac1eb2c 3506 goto enable_lag;
7dc84de9
RD		 3507 }
3508 cur_mlx5_mode = err;
3509 err = 0;
3510
c930a3ad 3511 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 3512 goto unlock;
c930a3ad 3513
f019679e 3514 mlx5_eswitch_disable_locked(esw);
c85a6b8f
AL		 3515 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3516 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3517 NL_SET_ERR_MSG_MOD(extack,
3518 "Can't change mode while devlink traps are active");
3519 err = -EOPNOTSUPP;
3520 goto unlock;
3521 }
8e0aa4bc 3522 err = esw_offloads_start(esw, extack);
c85a6b8f 3523 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
8e0aa4bc 3524 err = esw_offloads_stop(esw, extack);
f019679e 3525 mlx5_rescan_drivers(esw->dev);
c85a6b8f 3526 } else {
8e0aa4bc 3527 err = -EINVAL;
c85a6b8f 3528 }
8e0aa4bc
PP		 3529
3530unlock:
7dc84de9 3531 mlx5_esw_unlock(esw);
cac1eb2c
MB		 3532enable_lag:
3533 mlx5_lag_enable_change(esw->dev);
8e0aa4bc 3534 return err;
feae9087
OG		 3535}
3536
3537int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3538{
bd939753 3539 struct mlx5_eswitch *esw;
9d1cef19 3540 int err;
c930a3ad 3541
bd939753
PP		 3542 esw = mlx5_devlink_eswitch_get(devlink);
3543 if (IS_ERR(esw))
3544 return PTR_ERR(esw);
c930a3ad 3545
efb4879f 3546 down_read(&esw->mode_lock);
8e0aa4bc 3547 err = esw_mode_to_devlink(esw->mode, mode);
efb4879f 3548 up_read(&esw->mode_lock);
8e0aa4bc 3549 return err;
feae9087 3550}
127ea380 3551
47dd7e60
PP		 3552static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3553 struct netlink_ext_ack *extack)
3554{
3555 struct mlx5_core_dev *dev = esw->dev;
3556 struct mlx5_vport *vport;
3557 u16 err_vport_num = 0;
3558 unsigned long i;
3559 int err = 0;
3560
3561 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3562 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3563 if (err) {
3564 err_vport_num = vport->vport;
3565 NL_SET_ERR_MSG_MOD(extack,
3566 "Failed to set min inline on vport");
3567 goto revert_inline_mode;
3568 }
3569 }
a7719b29
DJ		 3570 if (mlx5_core_ec_sriov_enabled(esw->dev)) {
3571 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3572 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3573 if (err) {
3574 err_vport_num = vport->vport;
3575 NL_SET_ERR_MSG_MOD(extack,
3576 "Failed to set min inline on vport");
3577 goto revert_ec_vf_inline_mode;
3578 }
3579 }
3580 }
47dd7e60
PP		 3581 return 0;
3582
a7719b29
DJ		 3583revert_ec_vf_inline_mode:
3584 mlx5_esw_for_each_ec_vf_vport(esw, i, vport, esw->esw_funcs.num_ec_vfs) {
3585 if (vport->vport == err_vport_num)
3586 break;
3587 mlx5_modify_nic_vport_min_inline(dev,
3588 vport->vport,
3589 esw->offloads.inline_mode);
3590 }
47dd7e60
PP		 3591revert_inline_mode:
3592 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3593 if (vport->vport == err_vport_num)
3594 break;
3595 mlx5_modify_nic_vport_min_inline(dev,
3596 vport->vport,
3597 esw->offloads.inline_mode);
3598 }
3599 return err;
3600}
3601
db7ff19e
EB		 3602int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3603 struct netlink_ext_ack *extack)
bffaa916
RD		 3604{
3605 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3606 struct mlx5_eswitch *esw;
bffaa916 3607 u8 mlx5_mode;
47dd7e60 3608 int err;
bffaa916 3609
bd939753
PP		 3610 esw = mlx5_devlink_eswitch_get(devlink);
3611 if (IS_ERR(esw))
3612 return PTR_ERR(esw);
bffaa916 3613
367dfa12 3614 down_write(&esw->mode_lock);
ae24432c 3615
c415f704
OG		 3616 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3617 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
bcd68c04
JC		 3618 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3619 err = 0;
8e0aa4bc 3620 goto out;
bcd68c04
JC		 3621 }
3622
c8b838d1 3623 fallthrough;
c415f704 3624 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 3625 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 3626 err = -EOPNOTSUPP;
3627 goto out;
c415f704
OG		 3628 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3629 break;
3630 }
bffaa916 3631
525e84be 3632 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3633 NL_SET_ERR_MSG_MOD(extack,
3634 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 3635 err = -EOPNOTSUPP;
3636 goto out;
375f51e2
RD		 3637 }
3638
bffaa916
RD		 3639 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3640 if (err)
3641 goto out;
3642
47dd7e60
PP		 3643 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3644 if (err)
3645 goto out;
bffaa916
RD		 3646
3647 esw->offloads.inline_mode = mlx5_mode;
367dfa12 3648 up_write(&esw->mode_lock);
bffaa916
RD		 3649 return 0;
3650
bffaa916 3651out:
367dfa12 3652 up_write(&esw->mode_lock);
bffaa916
RD		 3653 return err;
3654}
3655
3656int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3657{
bd939753 3658 struct mlx5_eswitch *esw;
9d1cef19 3659 int err;
bffaa916 3660
bd939753
PP		 3661 esw = mlx5_devlink_eswitch_get(devlink);
3662 if (IS_ERR(esw))
3663 return PTR_ERR(esw);
bffaa916 3664
efb4879f 3665 down_read(&esw->mode_lock);
8e0aa4bc 3666 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
efb4879f 3667 up_read(&esw->mode_lock);
8e0aa4bc 3668 return err;
bffaa916
RD		 3669}
3670
acc10929
LR		 3671bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev)
3672{
3673 struct devlink *devlink = priv_to_devlink(dev);
3674 struct mlx5_eswitch *esw;
3675
3676 devl_lock(devlink);
3677 esw = mlx5_devlink_eswitch_get(devlink);
3678 if (IS_ERR(esw)) {
3679 devl_unlock(devlink);
3680 /* Failure means no eswitch => not possible to change encap */
3681 return true;
3682 }
3683
3684 down_write(&esw->mode_lock);
3685 if (esw->mode != MLX5_ESWITCH_LEGACY &&
3686 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
3687 up_write(&esw->mode_lock);
3688 devl_unlock(devlink);
3689 return false;
3690 }
3691
3692 esw->offloads.num_block_encap++;
3693 up_write(&esw->mode_lock);
3694 devl_unlock(devlink);
3695 return true;
3696}
3697
3698void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
3699{
3700 struct devlink *devlink = priv_to_devlink(dev);
3701 struct mlx5_eswitch *esw;
3702
3703 esw = mlx5_devlink_eswitch_get(devlink);
3704 if (IS_ERR(esw))
3705 return;
3706
3707 down_write(&esw->mode_lock);
3708 esw->offloads.num_block_encap--;
3709 up_write(&esw->mode_lock);
3710}
3711
98fdbea5
LR		 3712int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3713 enum devlink_eswitch_encap_mode encap,
db7ff19e 3714 struct netlink_ext_ack *extack)
7768d197
RD		 3715{
3716 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3717 struct mlx5_eswitch *esw;
f019679e 3718 int err = 0;
7768d197 3719
bd939753
PP		 3720 esw = mlx5_devlink_eswitch_get(devlink);
3721 if (IS_ERR(esw))
3722 return PTR_ERR(esw);
7768d197 3723
367dfa12 3724 down_write(&esw->mode_lock);
ae24432c 3725
7768d197 3726 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 3727 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 3728 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3729 err = -EOPNOTSUPP;
3730 goto unlock;
3731 }
7768d197 3732
8e0aa4bc
PP		 3733 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3734 err = -EOPNOTSUPP;
3735 goto unlock;
3736 }
7768d197 3737
f6455de0 3738 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 3739 esw->offloads.encap = encap;
8e0aa4bc 3740 goto unlock;
7768d197
RD		 3741 }
3742
3743 if (esw->offloads.encap == encap)
8e0aa4bc 3744 goto unlock;
7768d197 3745
525e84be 3746 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3747 NL_SET_ERR_MSG_MOD(extack,
3748 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 3749 err = -EOPNOTSUPP;
3750 goto unlock;
7768d197
RD		 3751 }
3752
acc10929
LR		 3753 if (esw->offloads.num_block_encap) {
3754 NL_SET_ERR_MSG_MOD(extack,
3755 "Can't set encapsulation when IPsec SA and/or policies are configured");
3756 err = -EOPNOTSUPP;
3757 goto unlock;
3758 }
3759
e52c2802 3760 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 3761
3762 esw->offloads.encap = encap;
e52c2802 3763
0da3c12d 3764 err = esw_create_offloads_fdb_tables(esw);
e52c2802 3765
7768d197 3766 if (err) {
8c98ee77
EB		 3767 NL_SET_ERR_MSG_MOD(extack,
3768 "Failed re-creating fast FDB table");
7768d197 3769 esw->offloads.encap = !encap;
0da3c12d 3770 (void)esw_create_offloads_fdb_tables(esw);
7768d197 3771 }
e52c2802 3772
8e0aa4bc 3773unlock:
367dfa12 3774 up_write(&esw->mode_lock);
7768d197
RD		 3775 return err;
3776}
3777
98fdbea5
LR		 3778int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3779 enum devlink_eswitch_encap_mode *encap)
7768d197 3780{
bd939753 3781 struct mlx5_eswitch *esw;
7768d197 3782
bd939753
PP		 3783 esw = mlx5_devlink_eswitch_get(devlink);
3784 if (IS_ERR(esw))
3785 return PTR_ERR(esw);
3786
efb4879f 3787 down_read(&esw->mode_lock);
7768d197 3788 *encap = esw->offloads.encap;
efb4879f 3789 up_read(&esw->mode_lock);
f019679e 3790 return 0;
7768d197
RD		 3791}
3792
c2d7712c
BW		 3793static bool
3794mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3795{
3796 /* Currently, only ECPF based device has representor for host PF. */
3797 if (vport_num == MLX5_VPORT_PF &&
3798 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3799 return false;
3800
3801 if (vport_num == MLX5_VPORT_ECPF &&
3802 !mlx5_ecpf_vport_exists(esw->dev))
3803 return false;
3804
3805 return true;
3806}
3807
f8e8fa02 3808void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 3809 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 3810 u8 rep_type)
127ea380 3811{
8693115a 3812 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02 3813 struct mlx5_eswitch_rep *rep;
47dd7e60 3814 unsigned long i;
9deb2241 3815
8693115a 3816 esw->offloads.rep_ops[rep_type] = ops;
47dd7e60
PP		 3817 mlx5_esw_for_each_rep(esw, i, rep) {
3818 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
59c904c8 3819 rep->esw = esw;
c2d7712c
BW		 3820 rep_data = &rep->rep_data[rep_type];
3821 atomic_set(&rep_data->state, REP_REGISTERED);
3822 }
f8e8fa02 3823 }
127ea380 3824}
f8e8fa02 3825EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 3826
f8e8fa02 3827void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 3828{
cb67b832 3829 struct mlx5_eswitch_rep *rep;
47dd7e60 3830 unsigned long i;
cb67b832 3831
f6455de0 3832 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 3833 __unload_reps_all_vport(esw, rep_type);
127ea380 3834
47dd7e60 3835 mlx5_esw_for_each_rep(esw, i, rep)
8693115a 3836 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 3837}
f8e8fa02 3838EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 3839
a4b97ab4 3840void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 3841{
726293f1
HHZ		 3842 struct mlx5_eswitch_rep *rep;
3843
879c8f84 3844 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 3845 return rep->rep_data[rep_type].priv;
726293f1 3846}
22215908
MB		 3847
3848void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 3849 u16 vport,
22215908
MB		 3850 u8 rep_type)
3851{
22215908
MB		 3852 struct mlx5_eswitch_rep *rep;
3853
879c8f84 3854 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 3855
8693115a
PP		 3856 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3857 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3858 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 3859 return NULL;
3860}
57cbd893 3861EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 3862
3863void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3864{
879c8f84 3865 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 3866}
57cbd893
MB		 3867EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3868
3869struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 3870 u16 vport)
57cbd893 3871{
879c8f84 3872 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 3873}
3874EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c 3875
5b7cb745
PB		 3876bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3877{
3878 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3879}
3880EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3881
7445cfb1
JL		 3882bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3883{
3884 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3885}
3886EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3887
0f0d3827 3888u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 3889 u16 vport_num)
3890{
133dcfc5 3891 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 3892
133dcfc5
VP		 3893 if (WARN_ON_ONCE(IS_ERR(vport)))
3894 return 0;
0f0d3827 3895
133dcfc5 3896 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 3897}
3898EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 3899
3900int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
f1b9acd3 3901 u16 vport_num, u32 controller, u32 sfnum)
d970812b
PP		 3902{
3903 int err;
3904
3905 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3906 if (err)
3907 return err;
3908
f1b9acd3 3909 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
d970812b
PP		 3910 if (err)
3911 goto devlink_err;
3912
3913 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3914 if (err)
3915 goto rep_err;
3916 return 0;
3917
3918rep_err:
3919 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3920devlink_err:
3921 mlx5_esw_vport_disable(esw, vport_num);
3922 return err;
3923}
3924
3925void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3926{
3927 mlx5_esw_offloads_rep_unload(esw, vport_num);
3928 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3929 mlx5_esw_vport_disable(esw, vport_num);
3930}
84ae9c1f
VB		 3931
3932static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3933{
3934 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3935 void *query_ctx;
3936 void *hca_caps;
3937 int err;
3938
3939 *vhca_id = 0;
3940 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3941 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3942 return -EPERM;
3943
3944 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3945 if (!query_ctx)
3946 return -ENOMEM;
3947
47d0c500 3948 err = mlx5_vport_get_other_func_general_cap(esw->dev, vport_num, query_ctx);
84ae9c1f
VB		 3949 if (err)
3950 goto out_free;
3951
3952 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3953 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3954
3955out_free:
3956 kfree(query_ctx);
3957 return err;
3958}
3959
3960int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3961{
3962 u16 *old_entry, *vhca_map_entry, vhca_id;
3963 int err;
3964
3965 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3966 if (err) {
3967 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3968 vport_num, err);
3969 return err;
3970 }
3971
3972 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3973 if (!vhca_map_entry)
3974 return -ENOMEM;
3975
3976 *vhca_map_entry = vport_num;
3977 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3978 if (xa_is_err(old_entry)) {
3979 kfree(vhca_map_entry);
3980 return xa_err(old_entry);
3981 }
3982 kfree(old_entry);
3983 return 0;
3984}
3985
3986void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3987{
3988 u16 *vhca_map_entry, vhca_id;
3989 int err;
3990
3991 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3992 if (err)
3993 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3994 vport_num, err);
3995
3996 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3997 kfree(vhca_map_entry);
3998}
3999
4000int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
4001{
4002 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
4003
4004 if (!res)
4005 return -ENOENT;
4006
4007 *vport_num = *res;
4008 return 0;
4009}
10742efc
VB		 4010
4011u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
4012 u16 vport_num)
4013{
4014 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
4015
4016 if (WARN_ON_ONCE(IS_ERR(vport)))
4017 return 0;
4018
4019 return vport->metadata;
4020}
4021EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
e9d491a6
PP		 4022
4023static bool
4024is_port_function_supported(struct mlx5_eswitch *esw, u16 vport_num)
4025{
4026 return vport_num == MLX5_VPORT_PF ||
4027 mlx5_eswitch_is_vf_vport(esw, vport_num) ||
4028 mlx5_esw_is_sf_vport(esw, vport_num);
4029}
4030
71c93e37
JP		 4031int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
4032 u8 *hw_addr, int *hw_addr_len,
4033 struct netlink_ext_ack *extack)
e9d491a6
PP		 4034{
4035 struct mlx5_eswitch *esw;
4036 struct mlx5_vport *vport;
4037 u16 vport_num;
4038
4039 esw = mlx5_devlink_eswitch_get(port->devlink);
4040 if (IS_ERR(esw))
4041 return PTR_ERR(esw);
4042
4043 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4044 if (!is_port_function_supported(esw, vport_num))
4045 return -EOPNOTSUPP;
4046
4047 vport = mlx5_eswitch_get_vport(esw, vport_num);
4048 if (IS_ERR(vport)) {
4049 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4050 return PTR_ERR(vport);
4051 }
4052
4053 mutex_lock(&esw->state_lock);
4054 ether_addr_copy(hw_addr, vport->info.mac);
4055 *hw_addr_len = ETH_ALEN;
4056 mutex_unlock(&esw->state_lock);
4057 return 0;
4058}
4059
71c93e37
JP		 4060int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
4061 const u8 *hw_addr, int hw_addr_len,
4062 struct netlink_ext_ack *extack)
e9d491a6
PP		 4063{
4064 struct mlx5_eswitch *esw;
4065 u16 vport_num;
4066
4067 esw = mlx5_devlink_eswitch_get(port->devlink);
4068 if (IS_ERR(esw)) {
4069 NL_SET_ERR_MSG_MOD(extack, "Eswitch doesn't support set hw_addr");
4070 return PTR_ERR(esw);
4071 }
4072
4073 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4074 if (!is_port_function_supported(esw, vport_num)) {
4075 NL_SET_ERR_MSG_MOD(extack, "Port doesn't support set hw_addr");
4076 return -EINVAL;
4077 }
4078
4079 return mlx5_eswitch_set_vport_mac(esw, vport_num, hw_addr);
4080}
7db98396
YH		 4081
4082static struct mlx5_vport *
4083mlx5_devlink_port_fn_get_vport(struct devlink_port *port, struct mlx5_eswitch *esw)
4084{
4085 u16 vport_num;
4086
4087 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
4088 return ERR_PTR(-EOPNOTSUPP);
4089
4090 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4091 if (!is_port_function_supported(esw, vport_num))
4092 return ERR_PTR(-EOPNOTSUPP);
4093
4094 return mlx5_eswitch_get_vport(esw, vport_num);
4095}
4096
e5b9642a
SD		 4097int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
4098 struct netlink_ext_ack *extack)
4099{
4100 struct mlx5_eswitch *esw;
4101 struct mlx5_vport *vport;
4102 int err = -EOPNOTSUPP;
4103
4104 esw = mlx5_devlink_eswitch_get(port->devlink);
4105 if (IS_ERR(esw))
4106 return PTR_ERR(esw);
4107
4108 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4109 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4110 return err;
4111 }
4112
4113 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4114 if (IS_ERR(vport)) {
4115 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4116 return PTR_ERR(vport);
4117 }
4118
4119 mutex_lock(&esw->state_lock);
4120 if (vport->enabled) {
4121 *is_enabled = vport->info.mig_enabled;
4122 err = 0;
4123 }
4124 mutex_unlock(&esw->state_lock);
4125 return err;
4126}
4127
4128int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
4129 struct netlink_ext_ack *extack)
4130{
4131 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4132 struct mlx5_eswitch *esw;
4133 struct mlx5_vport *vport;
4134 void *query_ctx;
4135 void *hca_caps;
4136 int err = -EOPNOTSUPP;
4137
4138 esw = mlx5_devlink_eswitch_get(port->devlink);
4139 if (IS_ERR(esw))
4140 return PTR_ERR(esw);
4141
4142 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4143 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4144 return err;
4145 }
4146
4147 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4148 if (IS_ERR(vport)) {
4149 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4150 return PTR_ERR(vport);
4151 }
4152
4153 mutex_lock(&esw->state_lock);
4154 if (!vport->enabled) {
4155 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4156 goto out;
4157 }
4158
4159 if (vport->info.mig_enabled == enable) {
4160 err = 0;
4161 goto out;
4162 }
4163
4164 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4165 if (!query_ctx) {
4166 err = -ENOMEM;
4167 goto out;
4168 }
4169
4170 err = mlx5_vport_get_other_func_cap(esw->dev, vport->vport, query_ctx,
4171 MLX5_CAP_GENERAL_2);
4172 if (err) {
4173 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4174 goto out_free;
4175 }
4176
4177 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
e5b9642a
SD		 4178 MLX5_SET(cmd_hca_cap_2, hca_caps, migratable, 1);
4179
4180 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport->vport,
4181 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4182 if (err) {
4183 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA migratable cap");
4184 goto out_free;
4185 }
4186
4187 vport->info.mig_enabled = enable;
4188
4189out_free:
4190 kfree(query_ctx);
4191out:
4192 mutex_unlock(&esw->state_lock);
4193 return err;
4194}
4195
7db98396
YH		 4196int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
4197 struct netlink_ext_ack *extack)
4198{
4199 struct mlx5_eswitch *esw;
4200 struct mlx5_vport *vport;
4201 int err = -EOPNOTSUPP;
4202
4203 esw = mlx5_devlink_eswitch_get(port->devlink);
4204 if (IS_ERR(esw))
4205 return PTR_ERR(esw);
4206
4207 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4208 if (IS_ERR(vport)) {
4209 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4210 return PTR_ERR(vport);
4211 }
4212
4213 mutex_lock(&esw->state_lock);
4214 if (vport->enabled) {
4215 *is_enabled = vport->info.roce_enabled;
4216 err = 0;
4217 }
4218 mutex_unlock(&esw->state_lock);
4219 return err;
4220}
4221
4222int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
4223 struct netlink_ext_ack *extack)
4224{
4225 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4226 struct mlx5_eswitch *esw;
4227 struct mlx5_vport *vport;
4228 int err = -EOPNOTSUPP;
4229 void *query_ctx;
4230 void *hca_caps;
4231 u16 vport_num;
4232
4233 esw = mlx5_devlink_eswitch_get(port->devlink);
4234 if (IS_ERR(esw))
4235 return PTR_ERR(esw);
4236
4237 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4238 if (IS_ERR(vport)) {
4239 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4240 return PTR_ERR(vport);
4241 }
4242 vport_num = vport->vport;
4243
4244 mutex_lock(&esw->state_lock);
4245 if (!vport->enabled) {
4246 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4247 goto out;
4248 }
4249
4250 if (vport->info.roce_enabled == enable) {
4251 err = 0;
4252 goto out;
4253 }
4254
4255 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4256 if (!query_ctx) {
4257 err = -ENOMEM;
4258 goto out;
4259 }
4260
4261 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4262 MLX5_CAP_GENERAL);
4263 if (err) {
4264 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4265 goto out_free;
4266 }
4267
4268 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
7db98396
YH		 4269 MLX5_SET(cmd_hca_cap, hca_caps, roce, enable);
4270
4271 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4272 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
4273 if (err) {
4274 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap");
4275 goto out_free;
4276 }
4277
4278 vport->info.roce_enabled = enable;
4279
4280out_free:
4281 kfree(query_ctx);
4282out:
4283 mutex_unlock(&esw->state_lock);
4284 return err;
4285}
Linux 6.x block layer and io_uring tree(s)