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net/mlx5e: en_tc, re-factor query route port
[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch_offloads.c
CommitLineData
69697b6e
OG		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
133dcfc5 34#include <linux/idr.h>
69697b6e
OG		 35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/mlx5_ifc.h>
37#include <linux/mlx5/vport.h>
38#include <linux/mlx5/fs.h>
39#include "mlx5_core.h"
40#include "eswitch.h"
34ca6535 41#include "esw/indir_table.h"
ea651a86 42#include "esw/acl/ofld.h"
80f09dfc 43#include "rdma.h"
e52c2802
PB		 44#include "en.h"
45#include "fs_core.h"
ac004b83 46#include "lib/devcom.h"
a3888f33 47#include "lib/eq.h"
ae430332 48#include "lib/fs_chains.h"
c620b772 49#include "en_tc.h"
c9355682 50#include "en/mapping.h"
c85a6b8f 51#include "devlink.h"
94db3317 52#include "lag/lag.h"
6fda078d 53#include "en/tc/post_meter.h"
69697b6e 54
47dd7e60
PP		 55#define mlx5_esw_for_each_rep(esw, i, rep) \
56 xa_for_each(&((esw)->offloads.vport_reps), i, rep)
57
58#define mlx5_esw_for_each_sf_rep(esw, i, rep) \
59 xa_for_each_marked(&((esw)->offloads.vport_reps), i, rep, MLX5_ESW_VPT_SF)
60
61#define mlx5_esw_for_each_vf_rep(esw, index, rep) \
62 mlx5_esw_for_each_entry_marked(&((esw)->offloads.vport_reps), index, \
63 rep, (esw)->esw_funcs.num_vfs, MLX5_ESW_VPT_VF)
64
cd7e4186
BW		 65/* There are two match-all miss flows, one for unicast dst mac and
66 * one for multicast.
67 */
68#define MLX5_ESW_MISS_FLOWS (2)
c9b99abc
BW		 69#define UPLINK_REP_INDEX 0
70
c796bb7c
CM		 71#define MLX5_ESW_VPORT_TBL_SIZE 128
72#define MLX5_ESW_VPORT_TBL_NUM_GROUPS 4
73
8ea7bcf6
JL		 74#define MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
75
fd745f4c 76static struct esw_vport_tbl_namespace mlx5_esw_vport_tbl_mirror_ns = {
c796bb7c
CM		 77 .max_fte = MLX5_ESW_VPORT_TBL_SIZE,
78 .max_num_groups = MLX5_ESW_VPORT_TBL_NUM_GROUPS,
79 .flags = 0,
80};
81
879c8f84
BW		 82static struct mlx5_eswitch_rep *mlx5_eswitch_get_rep(struct mlx5_eswitch *esw,
83 u16 vport_num)
84{
47dd7e60 85 return xa_load(&esw->offloads.vport_reps, vport_num);
879c8f84
BW		 86}
87
6f7bbad1
JL		 88static void
89mlx5_eswitch_set_rule_flow_source(struct mlx5_eswitch *esw,
90 struct mlx5_flow_spec *spec,
91 struct mlx5_esw_flow_attr *attr)
92{
166f431e
AL		 93 if (!MLX5_CAP_ESW_FLOWTABLE(esw->dev, flow_source) || !attr || !attr->in_rep)
94 return;
95
96 if (attr->int_port) {
97 spec->flow_context.flow_source = mlx5e_tc_int_port_get_flow_source(attr->int_port);
98
99 return;
100 }
101
102 spec->flow_context.flow_source = (attr->in_rep->vport == MLX5_VPORT_UPLINK) ?
103 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK :
104 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
6f7bbad1 105}
b7826076 106
f94d6389
CM		 107/* Actually only the upper 16 bits of reg c0 need to be cleared, but the lower 16 bits
108 * are not needed as well in the following process. So clear them all for simplicity.
109 */
110void
111mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec)
112{
113 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
114 void *misc2;
115
116 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
117 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
118
119 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
120 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, 0);
121
122 if (!memchr_inv(misc2, 0, MLX5_ST_SZ_BYTES(fte_match_set_misc2)))
123 spec->match_criteria_enable &= ~MLX5_MATCH_MISC_PARAMETERS_2;
124 }
125}
126
c01cfd0f
JL		 127static void
128mlx5_eswitch_set_rule_source_port(struct mlx5_eswitch *esw,
129 struct mlx5_flow_spec *spec,
a508728a 130 struct mlx5_flow_attr *attr,
b055ecf5
MB		 131 struct mlx5_eswitch *src_esw,
132 u16 vport)
c01cfd0f 133{
166f431e
AL		 134 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
135 u32 metadata;
c01cfd0f
JL		 136 void *misc2;
137 void *misc;
138
139 /* Use metadata matching because vport is not represented by single
140 * VHCA in dual-port RoCE mode, and matching on source vport may fail.
141 */
142 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
a508728a
VB		 143 if (mlx5_esw_indir_table_decap_vport(attr))
144 vport = mlx5_esw_indir_table_decap_vport(attr);
166f431e 145
e0bf81bf 146 if (!attr->chain && esw_attr && esw_attr->int_port)
166f431e
AL		 147 metadata =
148 mlx5e_tc_int_port_get_metadata_for_match(esw_attr->int_port);
149 else
150 metadata =
151 mlx5_eswitch_get_vport_metadata_for_match(src_esw, vport);
152
c01cfd0f 153 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
166f431e 154 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0, metadata);
c01cfd0f
JL		 155
156 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 157 MLX5_SET(fte_match_set_misc2, misc2, metadata_reg_c_0,
158 mlx5_eswitch_get_vport_metadata_mask());
c01cfd0f
JL		 159
160 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
c01cfd0f
JL		 161 } else {
162 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
b055ecf5 163 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
c01cfd0f
JL		 164
165 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
166 MLX5_SET(fte_match_set_misc, misc,
167 source_eswitch_owner_vhca_id,
b055ecf5 168 MLX5_CAP_GEN(src_esw->dev, vhca_id));
c01cfd0f
JL		 169
170 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
171 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
172 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
173 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
174 source_eswitch_owner_vhca_id);
175
176 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
177 }
c01cfd0f
JL		 178}
179
a508728a
VB		 180static int
181esw_setup_decap_indir(struct mlx5_eswitch *esw,
521933cd 182 struct mlx5_flow_attr *attr)
a508728a
VB		 183{
184 struct mlx5_flow_table *ft;
185
e5d4e1da 186 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
a508728a
VB		 187 return -EOPNOTSUPP;
188
521933cd 189 ft = mlx5_esw_indir_table_get(esw, attr,
a508728a
VB		 190 mlx5_esw_indir_table_decap_vport(attr), true);
191 return PTR_ERR_OR_ZERO(ft);
192}
193
9e51c0a6 194static void
a508728a
VB		 195esw_cleanup_decap_indir(struct mlx5_eswitch *esw,
196 struct mlx5_flow_attr *attr)
197{
198 if (mlx5_esw_indir_table_decap_vport(attr))
521933cd 199 mlx5_esw_indir_table_put(esw,
a508728a
VB		 200 mlx5_esw_indir_table_decap_vport(attr),
201 true);
202}
203
6fda078d
OS		 204static int
205esw_setup_mtu_dest(struct mlx5_flow_destination *dest,
206 struct mlx5e_meter_attr *meter,
207 int i)
208{
209 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_RANGE;
210 dest[i].range.field = MLX5_FLOW_DEST_RANGE_FIELD_PKT_LEN;
211 dest[i].range.min = 0;
212 dest[i].range.max = meter->params.mtu;
213 dest[i].range.hit_ft = mlx5e_post_meter_get_mtu_true_ft(meter->post_meter);
214 dest[i].range.miss_ft = mlx5e_post_meter_get_mtu_false_ft(meter->post_meter);
215
216 return 0;
217}
218
f94d6389
CM		 219static int
220esw_setup_sampler_dest(struct mlx5_flow_destination *dest,
221 struct mlx5_flow_act *flow_act,
eeed226e 222 u32 sampler_id,
f94d6389
CM		 223 int i)
224{
225 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
226 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
eeed226e 227 dest[i].sampler_id = sampler_id;
f94d6389
CM		 228
229 return 0;
230}
231
a508728a 232static int
9e51c0a6
VB		 233esw_setup_ft_dest(struct mlx5_flow_destination *dest,
234 struct mlx5_flow_act *flow_act,
a508728a 235 struct mlx5_eswitch *esw,
9e51c0a6
VB		 236 struct mlx5_flow_attr *attr,
237 int i)
238{
239 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
240 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
241 dest[i].ft = attr->dest_ft;
a508728a
VB		 242
243 if (mlx5_esw_indir_table_decap_vport(attr))
521933cd 244 return esw_setup_decap_indir(esw, attr);
a508728a 245 return 0;
9e51c0a6
VB		 246}
247
248static void
c0063a43
VB		 249esw_setup_accept_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
250 struct mlx5_fs_chains *chains, int i)
9e51c0a6 251{
2a2c84fa
RD		 252 if (mlx5_chains_ignore_flow_level_supported(chains))
253 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
9e51c0a6
VB		 254 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
255 dest[i].ft = mlx5_chains_get_tc_end_ft(chains);
256}
257
c0063a43
VB		 258static void
259esw_setup_slow_path_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
260 struct mlx5_eswitch *esw, int i)
261{
262 if (MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level))
263 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
264 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
dcf19b9c 265 dest[i].ft = mlx5_eswitch_get_slow_fdb(esw);
c0063a43
VB		 266}
267
9e51c0a6
VB		 268static int
269esw_setup_chain_dest(struct mlx5_flow_destination *dest,
270 struct mlx5_flow_act *flow_act,
271 struct mlx5_fs_chains *chains,
272 u32 chain, u32 prio, u32 level,
273 int i)
274{
275 struct mlx5_flow_table *ft;
276
277 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
278 ft = mlx5_chains_get_table(chains, chain, prio, level);
279 if (IS_ERR(ft))
280 return PTR_ERR(ft);
281
282 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
283 dest[i].ft = ft;
284 return 0;
285}
286
10742efc
VB		 287static void esw_put_dest_tables_loop(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr,
288 int from, int to)
289{
290 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
291 struct mlx5_fs_chains *chains = esw_chains(esw);
292 int i;
293
294 for (i = from; i < to; i++)
295 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
296 mlx5_chains_put_table(chains, 0, 1, 0);
a508728a
VB		 297 else if (mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
298 esw_attr->dests[i].mdev))
521933cd 299 mlx5_esw_indir_table_put(esw, esw_attr->dests[i].rep->vport,
a508728a 300 false);
10742efc
VB		 301}
302
303static bool
304esw_is_chain_src_port_rewrite(struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr)
305{
306 int i;
307
308 for (i = esw_attr->split_count; i < esw_attr->out_count; i++)
309 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
310 return true;
311 return false;
312}
313
314static int
315esw_setup_chain_src_port_rewrite(struct mlx5_flow_destination *dest,
316 struct mlx5_flow_act *flow_act,
317 struct mlx5_eswitch *esw,
318 struct mlx5_fs_chains *chains,
319 struct mlx5_flow_attr *attr,
320 int *i)
321{
322 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
de31854e 323 int err;
10742efc 324
e5d4e1da 325 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
10742efc
VB		 326 return -EOPNOTSUPP;
327
de31854e
DC		 328 /* flow steering cannot handle more than one dest with the same ft
329 * in a single flow
330 */
331 if (esw_attr->out_count - esw_attr->split_count > 1)
332 return -EOPNOTSUPP;
333
334 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain, 1, 0, *i);
335 if (err)
336 return err;
27484f71 337
de31854e
DC		 338 if (esw_attr->dests[esw_attr->split_count].pkt_reformat) {
339 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
340 flow_act->pkt_reformat = esw_attr->dests[esw_attr->split_count].pkt_reformat;
10742efc 341 }
de31854e 342 (*i)++;
10742efc 343
de31854e 344 return 0;
10742efc
VB		 345}
346
347static void esw_cleanup_chain_src_port_rewrite(struct mlx5_eswitch *esw,
348 struct mlx5_flow_attr *attr)
349{
350 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
351
352 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
353}
354
a508728a
VB		 355static bool
356esw_is_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
357{
358 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
e219440d 359 bool result = false;
a508728a
VB		 360 int i;
361
e219440d
MD		 362 /* Indirect table is supported only for flows with in_port uplink
363 * and the destination is vport on the same eswitch as the uplink,
364 * return false in case at least one of destinations doesn't meet
365 * this criteria.
366 */
367 for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
27484f71
AL		 368 if (esw_attr->dests[i].rep &&
369 mlx5_esw_indir_table_needed(esw, attr, esw_attr->dests[i].rep->vport,
e219440d
MD		 370 esw_attr->dests[i].mdev)) {
371 result = true;
372 } else {
373 result = false;
374 break;
375 }
376 }
377 return result;
a508728a
VB		 378}
379
380static int
381esw_setup_indir_table(struct mlx5_flow_destination *dest,
382 struct mlx5_flow_act *flow_act,
383 struct mlx5_eswitch *esw,
384 struct mlx5_flow_attr *attr,
a508728a
VB		 385 bool ignore_flow_lvl,
386 int *i)
387{
388 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
389 int j, err;
390
e5d4e1da 391 if (!(attr->flags & MLX5_ATTR_FLAG_SRC_REWRITE))
a508728a
VB		 392 return -EOPNOTSUPP;
393
394 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, (*i)++) {
395 if (ignore_flow_lvl)
396 flow_act->flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
397 dest[*i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
398
521933cd 399 dest[*i].ft = mlx5_esw_indir_table_get(esw, attr,
a508728a
VB		 400 esw_attr->dests[j].rep->vport, false);
401 if (IS_ERR(dest[*i].ft)) {
402 err = PTR_ERR(dest[*i].ft);
403 goto err_indir_tbl_get;
404 }
405 }
406
407 if (mlx5_esw_indir_table_decap_vport(attr)) {
521933cd 408 err = esw_setup_decap_indir(esw, attr);
a508728a
VB		 409 if (err)
410 goto err_indir_tbl_get;
411 }
412
413 return 0;
414
415err_indir_tbl_get:
416 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, j);
417 return err;
418}
419
420static void esw_cleanup_indir_table(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
421{
422 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
423
424 esw_put_dest_tables_loop(esw, attr, esw_attr->split_count, esw_attr->out_count);
425 esw_cleanup_decap_indir(esw, attr);
426}
427
9e51c0a6
VB		 428static void
429esw_cleanup_chain_dest(struct mlx5_fs_chains *chains, u32 chain, u32 prio, u32 level)
430{
431 mlx5_chains_put_table(chains, chain, prio, level);
432}
433
434static void
435esw_setup_vport_dest(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
436 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
437 int attr_idx, int dest_idx, bool pkt_reformat)
438{
439 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
440 dest[dest_idx].vport.num = esw_attr->dests[attr_idx].rep->vport;
c6719725
MD		 441 if (MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
442 dest[dest_idx].vport.vhca_id =
443 MLX5_CAP_GEN(esw_attr->dests[attr_idx].mdev, vhca_id);
9e51c0a6 444 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
942fca7e 445 if (dest[dest_idx].vport.num == MLX5_VPORT_UPLINK &&
8ce81fc0 446 mlx5_lag_is_mpesw(esw->dev))
94db3317 447 dest[dest_idx].type = MLX5_FLOW_DESTINATION_TYPE_UPLINK;
c6719725 448 }
6d942e40 449 if (esw_attr->dests[attr_idx].flags & MLX5_ESW_DEST_ENCAP_VALID) {
9e51c0a6
VB		 450 if (pkt_reformat) {
451 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
452 flow_act->pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
453 }
454 dest[dest_idx].vport.flags |= MLX5_FLOW_DEST_VPORT_REFORMAT_ID;
455 dest[dest_idx].vport.pkt_reformat = esw_attr->dests[attr_idx].pkt_reformat;
456 }
457}
458
459static int
460esw_setup_vport_dests(struct mlx5_flow_destination *dest, struct mlx5_flow_act *flow_act,
461 struct mlx5_eswitch *esw, struct mlx5_esw_flow_attr *esw_attr,
462 int i)
463{
464 int j;
465
466 for (j = esw_attr->split_count; j < esw_attr->out_count; j++, i++)
467 esw_setup_vport_dest(dest, flow_act, esw, esw_attr, j, i, true);
468 return i;
469}
470
e929e3da
MD		 471static bool
472esw_src_port_rewrite_supported(struct mlx5_eswitch *esw)
473{
474 return MLX5_CAP_GEN(esw->dev, reg_c_preserve) &&
475 mlx5_eswitch_vport_match_metadata_enabled(esw) &&
476 MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ignore_flow_level);
477}
478
9e51c0a6
VB		 479static int
480esw_setup_dests(struct mlx5_flow_destination *dest,
481 struct mlx5_flow_act *flow_act,
482 struct mlx5_eswitch *esw,
483 struct mlx5_flow_attr *attr,
10742efc 484 struct mlx5_flow_spec *spec,
9e51c0a6
VB		 485 int *i)
486{
487 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
488 struct mlx5_fs_chains *chains = esw_chains(esw);
489 int err = 0;
490
10742efc 491 if (!mlx5_eswitch_termtbl_required(esw, attr, flow_act, spec) &&
e929e3da 492 esw_src_port_rewrite_supported(esw))
e5d4e1da 493 attr->flags |= MLX5_ATTR_FLAG_SRC_REWRITE;
10742efc 494
42760d95 495 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH) {
c0063a43
VB		 496 esw_setup_slow_path_dest(dest, flow_act, esw, *i);
497 (*i)++;
42760d95
RD		 498 goto out;
499 }
500
501 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
502 esw_setup_sampler_dest(dest, flow_act, attr->sample_attr.sampler_id, *i);
503 (*i)++;
c0063a43
VB		 504 } else if (attr->flags & MLX5_ATTR_FLAG_ACCEPT) {
505 esw_setup_accept_dest(dest, flow_act, chains, *i);
9e51c0a6 506 (*i)++;
6fda078d
OS		 507 } else if (attr->flags & MLX5_ATTR_FLAG_MTU) {
508 err = esw_setup_mtu_dest(dest, &attr->meter_attr, *i);
509 (*i)++;
a508728a 510 } else if (esw_is_indir_table(esw, attr)) {
521933cd 511 err = esw_setup_indir_table(dest, flow_act, esw, attr, true, i);
10742efc
VB		 512 } else if (esw_is_chain_src_port_rewrite(esw, esw_attr)) {
513 err = esw_setup_chain_src_port_rewrite(dest, flow_act, esw, chains, attr, i);
9e51c0a6
VB		 514 } else {
515 *i = esw_setup_vport_dests(dest, flow_act, esw, esw_attr, *i);
8c9cc1eb
RD		 516
517 if (attr->dest_ft) {
521933cd 518 err = esw_setup_ft_dest(dest, flow_act, esw, attr, *i);
8c9cc1eb
RD		 519 (*i)++;
520 } else if (attr->dest_chain) {
521 err = esw_setup_chain_dest(dest, flow_act, chains, attr->dest_chain,
522 1, 0, *i);
523 (*i)++;
524 }
9e51c0a6
VB		 525 }
526
42760d95 527out:
9e51c0a6
VB		 528 return err;
529}
530
531static void
532esw_cleanup_dests(struct mlx5_eswitch *esw,
533 struct mlx5_flow_attr *attr)
534{
10742efc 535 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
9e51c0a6
VB		 536 struct mlx5_fs_chains *chains = esw_chains(esw);
537
a508728a
VB		 538 if (attr->dest_ft) {
539 esw_cleanup_decap_indir(esw, attr);
e5d4e1da 540 } else if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
10742efc
VB		 541 if (attr->dest_chain)
542 esw_cleanup_chain_dest(chains, attr->dest_chain, 1, 0);
a508728a
VB		 543 else if (esw_is_indir_table(esw, attr))
544 esw_cleanup_indir_table(esw, attr);
10742efc
VB		 545 else if (esw_is_chain_src_port_rewrite(esw, esw_attr))
546 esw_cleanup_chain_src_port_rewrite(esw, attr);
547 }
9e51c0a6
VB		 548}
549
9153da46
JL		 550static void
551esw_setup_meter(struct mlx5_flow_attr *attr, struct mlx5_flow_act *flow_act)
552{
553 struct mlx5e_flow_meter_handle *meter;
554
555 meter = attr->meter_attr.meter;
556 flow_act->exe_aso.type = attr->exe_aso_type;
557 flow_act->exe_aso.object_id = meter->obj_id;
558 flow_act->exe_aso.flow_meter.meter_idx = meter->idx;
559 flow_act->exe_aso.flow_meter.init_color = MLX5_FLOW_METER_COLOR_GREEN;
560 /* use metadata reg 5 for packet color */
561 flow_act->exe_aso.return_reg_id = 5;
562}
563
74491de9 564struct mlx5_flow_handle *
3d80d1a2
OG		 565mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
566 struct mlx5_flow_spec *spec,
c620b772 567 struct mlx5_flow_attr *attr)
3d80d1a2 568{
42f7ad67 569 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 570 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 571 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 572 bool split = !!(esw_attr->split_count);
573 struct mlx5_vport_tbl_attr fwd_attr;
40888162 574 struct mlx5_flow_destination *dest;
74491de9 575 struct mlx5_flow_handle *rule;
e52c2802 576 struct mlx5_flow_table *fdb;
9e51c0a6 577 int i = 0;
3d80d1a2 578
f6455de0 579 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
3d80d1a2
OG		 580 return ERR_PTR(-EOPNOTSUPP);
581
633ad4b2
RD		 582 if (!mlx5_eswitch_vlan_actions_supported(esw->dev, 1))
583 return ERR_PTR(-EOPNOTSUPP);
584
40888162
MD		 585 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
586 if (!dest)
587 return ERR_PTR(-ENOMEM);
588
6acfbf38 589 flow_act.action = attr->action;
633ad4b2
RD		 590
591 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
c620b772
AL		 592 flow_act.vlan[0].ethtype = ntohs(esw_attr->vlan_proto[0]);
593 flow_act.vlan[0].vid = esw_attr->vlan_vid[0];
594 flow_act.vlan[0].prio = esw_attr->vlan_prio[0];
cc495188 595 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2) {
c620b772
AL		 596 flow_act.vlan[1].ethtype = ntohs(esw_attr->vlan_proto[1]);
597 flow_act.vlan[1].vid = esw_attr->vlan_vid[1];
598 flow_act.vlan[1].prio = esw_attr->vlan_prio[1];
cc495188 599 }
6acfbf38 600 }
776b12b6 601
10742efc
VB		 602 mlx5_eswitch_set_rule_flow_source(esw, spec, esw_attr);
603
66958ed9 604 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
9e51c0a6
VB		 605 int err;
606
10742efc 607 err = esw_setup_dests(dest, &flow_act, esw, attr, spec, &i);
9e51c0a6
VB		 608 if (err) {
609 rule = ERR_PTR(err);
610 goto err_create_goto_table;
56e858df 611 }
e37a79e5 612 }
14e6b038 613
c620b772
AL		 614 if (esw_attr->decap_pkt_reformat)
615 flow_act.pkt_reformat = esw_attr->decap_pkt_reformat;
14e6b038 616
66958ed9 617 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
e37a79e5 618 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 619 dest[i].counter_id = mlx5_fc_id(attr->counter);
e37a79e5 620 i++;
3d80d1a2
OG		 621 }
622
93b3586e 623 if (attr->outer_match_level != MLX5_MATCH_NONE)
6363651d 624 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
93b3586e
HN		 625 if (attr->inner_match_level != MLX5_MATCH_NONE)
626 spec->match_criteria_enable |= MLX5_MATCH_INNER_HEADERS;
3d80d1a2 627
aa24670e 628 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 629 flow_act.modify_hdr = attr->modify_hdr;
d7e75a32 630
9153da46
JL		 631 if ((flow_act.action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
632 attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)
633 esw_setup_meter(attr, &flow_act);
634
2741f223 635 if (split) {
c620b772
AL		 636 fwd_attr.chain = attr->chain;
637 fwd_attr.prio = attr->prio;
638 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 639 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772 640
0a9e2307 641 fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
96e32687 642 } else {
d18296ff 643 if (attr->chain || attr->prio)
ae430332
AL		 644 fdb = mlx5_chains_get_table(chains, attr->chain,
645 attr->prio, 0);
d18296ff 646 else
c620b772 647 fdb = attr->ft;
6fb0701a 648
e5d4e1da 649 if (!(attr->flags & MLX5_ATTR_FLAG_NO_IN_PORT))
a508728a 650 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 651 esw_attr->in_mdev->priv.eswitch,
652 esw_attr->in_rep->vport);
96e32687 653 }
e52c2802
PB		 654 if (IS_ERR(fdb)) {
655 rule = ERR_CAST(fdb);
656 goto err_esw_get;
657 }
658
5a5624d1
OS		 659 if (!i) {
660 kfree(dest);
661 dest = NULL;
662 }
663
84be2fda 664 if (mlx5_eswitch_termtbl_required(esw, attr, &flow_act, spec))
c620b772 665 rule = mlx5_eswitch_add_termtbl_rule(esw, fdb, spec, esw_attr,
10caabda 666 &flow_act, dest, i);
84be2fda 667 else
10caabda 668 rule = mlx5_add_flow_rules(fdb, spec, &flow_act, dest, i);
3d80d1a2 669 if (IS_ERR(rule))
e52c2802 670 goto err_add_rule;
375f51e2 671 else
525e84be 672 atomic64_inc(&esw->offloads.num_flows);
3d80d1a2 673
40888162 674 kfree(dest);
e52c2802
PB		 675 return rule;
676
677err_add_rule:
96e32687 678 if (split)
0a9e2307 679 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 680 else if (attr->chain || attr->prio)
ae430332 681 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 682err_esw_get:
9e51c0a6 683 esw_cleanup_dests(esw, attr);
e52c2802 684err_create_goto_table:
40888162 685 kfree(dest);
aa0cbbae 686 return rule;
3d80d1a2
OG		 687}
688
e4ad91f2
CM		 689struct mlx5_flow_handle *
690mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
691 struct mlx5_flow_spec *spec,
c620b772 692 struct mlx5_flow_attr *attr)
e4ad91f2 693{
42f7ad67 694 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
c620b772 695 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 696 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772 697 struct mlx5_vport_tbl_attr fwd_attr;
40888162 698 struct mlx5_flow_destination *dest;
e52c2802
PB		 699 struct mlx5_flow_table *fast_fdb;
700 struct mlx5_flow_table *fwd_fdb;
e4ad91f2 701 struct mlx5_flow_handle *rule;
10742efc 702 int i, err = 0;
e4ad91f2 703
40888162
MD		 704 dest = kcalloc(MLX5_MAX_FLOW_FWD_VPORTS + 1, sizeof(*dest), GFP_KERNEL);
705 if (!dest)
706 return ERR_PTR(-ENOMEM);
707
ae430332 708 fast_fdb = mlx5_chains_get_table(chains, attr->chain, attr->prio, 0);
e52c2802
PB		 709 if (IS_ERR(fast_fdb)) {
710 rule = ERR_CAST(fast_fdb);
711 goto err_get_fast;
712 }
713
c620b772
AL		 714 fwd_attr.chain = attr->chain;
715 fwd_attr.prio = attr->prio;
716 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 717 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 718 fwd_fdb = mlx5_esw_vporttbl_get(esw, &fwd_attr);
e52c2802
PB		 719 if (IS_ERR(fwd_fdb)) {
720 rule = ERR_CAST(fwd_fdb);
721 goto err_get_fwd;
722 }
723
e4ad91f2 724 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
10742efc 725 for (i = 0; i < esw_attr->split_count; i++) {
1313d78a
MD		 726 if (esw_attr->dests[i].flags & MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
727 /* Source port rewrite (forward to ovs internal port or statck device) isn't
728 * supported in the rule of split action.
729 */
730 err = -EOPNOTSUPP;
10742efc
VB		 731 else
732 esw_setup_vport_dest(dest, &flow_act, esw, esw_attr, i, i, false);
733
734 if (err) {
735 rule = ERR_PTR(err);
736 goto err_chain_src_rewrite;
737 }
738 }
e4ad91f2 739 dest[i].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
873d2f12 740 dest[i].ft = fwd_fdb;
e4ad91f2
CM		 741 i++;
742
a508728a 743 mlx5_eswitch_set_rule_source_port(esw, spec, attr,
b055ecf5
MB		 744 esw_attr->in_mdev->priv.eswitch,
745 esw_attr->in_rep->vport);
e4ad91f2 746
93b3586e 747 if (attr->outer_match_level != MLX5_MATCH_NONE)
c01cfd0f 748 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
e4ad91f2 749
278d51f2 750 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
e52c2802 751 rule = mlx5_add_flow_rules(fast_fdb, spec, &flow_act, dest, i);
e4ad91f2 752
10742efc
VB		 753 if (IS_ERR(rule)) {
754 i = esw_attr->split_count;
755 goto err_chain_src_rewrite;
756 }
e4ad91f2 757
525e84be 758 atomic64_inc(&esw->offloads.num_flows);
e52c2802 759
40888162 760 kfree(dest);
e52c2802 761 return rule;
10742efc 762err_chain_src_rewrite:
0a9e2307 763 mlx5_esw_vporttbl_put(esw, &fwd_attr);
e52c2802 764err_get_fwd:
ae430332 765 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 766err_get_fast:
40888162 767 kfree(dest);
e4ad91f2
CM		 768 return rule;
769}
770
e52c2802
PB		 771static void
772__mlx5_eswitch_del_rule(struct mlx5_eswitch *esw,
773 struct mlx5_flow_handle *rule,
c620b772 774 struct mlx5_flow_attr *attr,
e52c2802
PB		 775 bool fwd_rule)
776{
c620b772 777 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
ae430332 778 struct mlx5_fs_chains *chains = esw_chains(esw);
c620b772
AL		 779 bool split = (esw_attr->split_count > 0);
780 struct mlx5_vport_tbl_attr fwd_attr;
10caabda 781 int i;
e52c2802
PB		 782
783 mlx5_del_flow_rules(rule);
10caabda 784
e5d4e1da 785 if (!mlx5e_tc_attr_flags_skip(attr->flags)) {
d8a2034f
EC		 786 /* unref the term table */
787 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
c620b772
AL		 788 if (esw_attr->dests[i].termtbl)
789 mlx5_eswitch_termtbl_put(esw, esw_attr->dests[i].termtbl);
d8a2034f 790 }
10caabda
OS		 791 }
792
525e84be 793 atomic64_dec(&esw->offloads.num_flows);
e52c2802 794
c620b772
AL		 795 if (fwd_rule || split) {
796 fwd_attr.chain = attr->chain;
797 fwd_attr.prio = attr->prio;
798 fwd_attr.vport = esw_attr->in_rep->vport;
c796bb7c 799 fwd_attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
c620b772
AL		 800 }
801
e52c2802 802 if (fwd_rule) {
0a9e2307 803 mlx5_esw_vporttbl_put(esw, &fwd_attr);
ae430332 804 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
e52c2802 805 } else {
96e32687 806 if (split)
0a9e2307 807 mlx5_esw_vporttbl_put(esw, &fwd_attr);
d18296ff 808 else if (attr->chain || attr->prio)
ae430332 809 mlx5_chains_put_table(chains, attr->chain, attr->prio, 0);
9e51c0a6 810 esw_cleanup_dests(esw, attr);
e52c2802
PB		 811 }
812}
813
d85cdccb
OG		 814void
815mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
816 struct mlx5_flow_handle *rule,
c620b772 817 struct mlx5_flow_attr *attr)
d85cdccb 818{
e52c2802 819 __mlx5_eswitch_del_rule(esw, rule, attr, false);
d85cdccb
OG		 820}
821
48265006
OG		 822void
823mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
824 struct mlx5_flow_handle *rule,
c620b772 825 struct mlx5_flow_attr *attr)
48265006 826{
e52c2802 827 __mlx5_eswitch_del_rule(esw, rule, attr, true);
48265006
OG		 828}
829
f7a68945 830struct mlx5_flow_handle *
3a46f4fb 831mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
979bf468 832 struct mlx5_eswitch *from_esw,
3a46f4fb 833 struct mlx5_eswitch_rep *rep,
02f3afd9 834 u32 sqn)
ab22be9b 835{
66958ed9 836 struct mlx5_flow_act flow_act = {0};
4c5009c5 837 struct mlx5_flow_destination dest = {};
74491de9 838 struct mlx5_flow_handle *flow_rule;
c5bb1730 839 struct mlx5_flow_spec *spec;
ab22be9b 840 void *misc;
29bcb6e4 841 u16 vport;
ab22be9b 842
1b9a07ee 843 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 844 if (!spec) {
ab22be9b
OG		 845 flow_rule = ERR_PTR(-ENOMEM);
846 goto out;
847 }
848
c5bb1730 849 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
ab22be9b 850 MLX5_SET(fte_match_set_misc, misc, source_sqn, sqn);
ab22be9b 851
c5bb1730 852 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
ab22be9b 853 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_sqn);
ab22be9b 854
c5bb1730 855 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
29bcb6e4
RD		 856
857 /* source vport is the esw manager */
858 vport = from_esw->manager_vport;
859
860 if (mlx5_eswitch_vport_match_metadata_enabled(on_esw)) {
861 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
862 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
863 mlx5_eswitch_get_vport_metadata_for_match(from_esw, vport));
864
865 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
866 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
867 mlx5_eswitch_get_vport_metadata_mask());
868
869 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
870 } else {
871 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
872 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
873
874 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
875 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
876 MLX5_CAP_GEN(from_esw->dev, vhca_id));
877
878 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
879 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
880
881 if (MLX5_CAP_ESW(on_esw->dev, merged_eswitch))
882 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
883 source_eswitch_owner_vhca_id);
884
885 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
886 }
887
ab22be9b 888 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
3a46f4fb
MB		 889 dest.vport.num = rep->vport;
890 dest.vport.vhca_id = MLX5_CAP_GEN(rep->esw->dev, vhca_id);
891 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
66958ed9 892 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
ab22be9b 893
1bf8b0da
RD		 894 if (MLX5_CAP_ESW_FLOWTABLE(on_esw->dev, flow_source) &&
895 rep->vport == MLX5_VPORT_UPLINK)
d0444254
AL		 896 spec->flow_context.flow_source = MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT;
897
dcf19b9c 898 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(on_esw),
39ac237c 899 spec, &flow_act, &dest, 1);
ab22be9b 900 if (IS_ERR(flow_rule))
3a46f4fb
MB		 901 esw_warn(on_esw->dev, "FDB: Failed to add send to vport rule err %ld\n",
902 PTR_ERR(flow_rule));
ab22be9b 903out:
c5bb1730 904 kvfree(spec);
ab22be9b
OG		 905 return flow_rule;
906}
57cbd893 907EXPORT_SYMBOL(mlx5_eswitch_add_send_to_vport_rule);
ab22be9b 908
159fe639
MB		 909void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule)
910{
911 mlx5_del_flow_rules(rule);
912}
913
430e2d5e 914void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule)
8e404fef 915{
430e2d5e
RD		 916 if (rule)
917 mlx5_del_flow_rules(rule);
f019679e
CM		 918}
919
430e2d5e
RD		 920struct mlx5_flow_handle *
921mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num)
8e404fef 922{
8e404fef
VB		 923 struct mlx5_flow_destination dest = {};
924 struct mlx5_flow_act flow_act = {0};
925 struct mlx5_flow_handle *flow_rule;
8e404fef 926 struct mlx5_flow_spec *spec;
8e404fef
VB		 927
928 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
430e2d5e
RD		 929 if (!spec)
930 return ERR_PTR(-ENOMEM);
8e404fef
VB		 931
932 MLX5_SET(fte_match_param, spec->match_criteria,
933 misc_parameters_2.metadata_reg_c_0, mlx5_eswitch_get_vport_metadata_mask());
934 MLX5_SET(fte_match_param, spec->match_criteria,
935 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
936 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1,
937 ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK);
938
939 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
940 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
941 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
942
430e2d5e
RD		 943 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0,
944 mlx5_eswitch_get_vport_metadata_for_match(esw, vport_num));
945 dest.vport.num = vport_num;
8e404fef 946
dcf19b9c 947 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
430e2d5e
RD		 948 spec, &flow_act, &dest, 1);
949 if (IS_ERR(flow_rule))
950 esw_warn(esw->dev, "FDB: Failed to add send to vport meta rule vport %d, err %ld\n",
951 vport_num, PTR_ERR(flow_rule));
8e404fef 952
8e404fef 953 kvfree(spec);
430e2d5e 954 return flow_rule;
8e404fef
VB		 955}
956
5b7cb745
PB		 957static bool mlx5_eswitch_reg_c1_loopback_supported(struct mlx5_eswitch *esw)
958{
959 return MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
960 MLX5_FDB_TO_VPORT_REG_C_1;
961}
962
332bd3a5 963static int esw_set_passing_vport_metadata(struct mlx5_eswitch *esw, bool enable)
c1286050
JL		 964{
965 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {};
e08a6832
LR		 966 u32 min[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {};
967 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {};
5b7cb745 968 u8 curr, wanted;
c1286050
JL		 969 int err;
970
5b7cb745
PB		 971 if (!mlx5_eswitch_reg_c1_loopback_supported(esw) &&
972 !mlx5_eswitch_vport_match_metadata_enabled(esw))
332bd3a5 973 return 0;
c1286050 974
e08a6832
LR		 975 MLX5_SET(query_esw_vport_context_in, in, opcode,
976 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
977 err = mlx5_cmd_exec_inout(esw->dev, query_esw_vport_context, in, out);
c1286050
JL		 978 if (err)
979 return err;
980
5b7cb745
PB		 981 curr = MLX5_GET(query_esw_vport_context_out, out,
982 esw_vport_context.fdb_to_vport_reg_c_id);
983 wanted = MLX5_FDB_TO_VPORT_REG_C_0;
984 if (mlx5_eswitch_reg_c1_loopback_supported(esw))
985 wanted |= MLX5_FDB_TO_VPORT_REG_C_1;
c1286050 986
332bd3a5 987 if (enable)
5b7cb745 988 curr |= wanted;
332bd3a5 989 else
5b7cb745 990 curr &= ~wanted;
c1286050 991
e08a6832 992 MLX5_SET(modify_esw_vport_context_in, min,
5b7cb745 993 esw_vport_context.fdb_to_vport_reg_c_id, curr);
e08a6832 994 MLX5_SET(modify_esw_vport_context_in, min,
c1286050
JL		 995 field_select.fdb_to_vport_reg_c_id, 1);
996
e08a6832 997 err = mlx5_eswitch_modify_esw_vport_context(esw->dev, 0, false, min);
5b7cb745
PB		 998 if (!err) {
999 if (enable && (curr & MLX5_FDB_TO_VPORT_REG_C_1))
1000 esw->flags |= MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1001 else
1002 esw->flags &= ~MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED;
1003 }
1004
1005 return err;
c1286050
JL		 1006}
1007
a5641cb5
JL		 1008static void peer_miss_rules_setup(struct mlx5_eswitch *esw,
1009 struct mlx5_core_dev *peer_dev,
ac004b83
RD		 1010 struct mlx5_flow_spec *spec,
1011 struct mlx5_flow_destination *dest)
1012{
a5641cb5 1013 void *misc;
ac004b83 1014
a5641cb5
JL		 1015 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1016 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1017 misc_parameters_2);
0f0d3827
PB		 1018 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1019 mlx5_eswitch_get_vport_metadata_mask());
ac004b83 1020
a5641cb5
JL		 1021 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1022 } else {
1023 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1024 misc_parameters);
ac004b83 1025
a5641cb5
JL		 1026 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
1027 MLX5_CAP_GEN(peer_dev, vhca_id));
1028
1029 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1030
1031 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1032 misc_parameters);
1033 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1034 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
1035 source_eswitch_owner_vhca_id);
1036 }
ac004b83
RD		 1037
1038 dest->type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1039 dest->vport.num = peer_dev->priv.eswitch->manager_vport;
ac004b83 1040 dest->vport.vhca_id = MLX5_CAP_GEN(peer_dev, vhca_id);
04de7dda 1041 dest->vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
ac004b83
RD		 1042}
1043
a5641cb5
JL		 1044static void esw_set_peer_miss_rule_source_port(struct mlx5_eswitch *esw,
1045 struct mlx5_eswitch *peer_esw,
1046 struct mlx5_flow_spec *spec,
1047 u16 vport)
1048{
1049 void *misc;
1050
1051 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1052 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1053 misc_parameters_2);
1054 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1055 mlx5_eswitch_get_vport_metadata_for_match(peer_esw,
1056 vport));
1057 } else {
1058 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1059 misc_parameters);
1060 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1061 }
1062}
1063
ac004b83
RD		 1064static int esw_add_fdb_peer_miss_rules(struct mlx5_eswitch *esw,
1065 struct mlx5_core_dev *peer_dev)
1066{
1067 struct mlx5_flow_destination dest = {};
1068 struct mlx5_flow_act flow_act = {0};
1069 struct mlx5_flow_handle **flows;
ac004b83
RD		 1070 /* total vports is the same for both e-switches */
1071 int nvports = esw->total_vports;
47dd7e60
PP		 1072 struct mlx5_flow_handle *flow;
1073 struct mlx5_flow_spec *spec;
1074 struct mlx5_vport *vport;
1075 unsigned long i;
ac004b83 1076 void *misc;
47dd7e60 1077 int err;
ac004b83
RD		 1078
1079 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1080 if (!spec)
1081 return -ENOMEM;
1082
a5641cb5 1083 peer_miss_rules_setup(esw, peer_dev, spec, &dest);
ac004b83 1084
806bf340 1085 flows = kvcalloc(nvports, sizeof(*flows), GFP_KERNEL);
ac004b83
RD		 1086 if (!flows) {
1087 err = -ENOMEM;
1088 goto alloc_flows_err;
1089 }
1090
1091 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1092 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1093 misc_parameters);
1094
81cd229c 1095 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
47dd7e60 1096 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
a5641cb5
JL		 1097 esw_set_peer_miss_rule_source_port(esw, peer_dev->priv.eswitch,
1098 spec, MLX5_VPORT_PF);
1099
dcf19b9c 1100 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
81cd229c
BW		 1101 spec, &flow_act, &dest, 1);
1102 if (IS_ERR(flow)) {
1103 err = PTR_ERR(flow);
1104 goto add_pf_flow_err;
1105 }
47dd7e60 1106 flows[vport->index] = flow;
81cd229c
BW		 1107 }
1108
1109 if (mlx5_ecpf_vport_exists(esw->dev)) {
47dd7e60 1110 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
81cd229c 1111 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF);
dcf19b9c 1112 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
81cd229c
BW		 1113 spec, &flow_act, &dest, 1);
1114 if (IS_ERR(flow)) {
1115 err = PTR_ERR(flow);
1116 goto add_ecpf_flow_err;
1117 }
47dd7e60 1118 flows[vport->index] = flow;
81cd229c
BW		 1119 }
1120
47dd7e60 1121 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
a5641cb5
JL		 1122 esw_set_peer_miss_rule_source_port(esw,
1123 peer_dev->priv.eswitch,
47dd7e60 1124 spec, vport->vport);
a5641cb5 1125
dcf19b9c 1126 flow = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
ac004b83
RD		 1127 spec, &flow_act, &dest, 1);
1128 if (IS_ERR(flow)) {
1129 err = PTR_ERR(flow);
81cd229c 1130 goto add_vf_flow_err;
ac004b83 1131 }
47dd7e60 1132 flows[vport->index] = flow;
ac004b83
RD		 1133 }
1134
1135 esw->fdb_table.offloads.peer_miss_rules = flows;
1136
1137 kvfree(spec);
1138 return 0;
1139
81cd229c 1140add_vf_flow_err:
47dd7e60
PP		 1141 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev)) {
1142 if (!flows[vport->index])
1143 continue;
1144 mlx5_del_flow_rules(flows[vport->index]);
1145 }
1146 if (mlx5_ecpf_vport_exists(esw->dev)) {
1147 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1148 mlx5_del_flow_rules(flows[vport->index]);
1149 }
81cd229c 1150add_ecpf_flow_err:
47dd7e60
PP		 1151 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1152 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1153 mlx5_del_flow_rules(flows[vport->index]);
1154 }
81cd229c
BW		 1155add_pf_flow_err:
1156 esw_warn(esw->dev, "FDB: Failed to add peer miss flow rule err %d\n", err);
ac004b83
RD		 1157 kvfree(flows);
1158alloc_flows_err:
1159 kvfree(spec);
1160 return err;
1161}
1162
1163static void esw_del_fdb_peer_miss_rules(struct mlx5_eswitch *esw)
1164{
1165 struct mlx5_flow_handle **flows;
47dd7e60
PP		 1166 struct mlx5_vport *vport;
1167 unsigned long i;
ac004b83
RD		 1168
1169 flows = esw->fdb_table.offloads.peer_miss_rules;
1170
47dd7e60
PP		 1171 mlx5_esw_for_each_vf_vport(esw, i, vport, mlx5_core_max_vfs(esw->dev))
1172 mlx5_del_flow_rules(flows[vport->index]);
ac004b83 1173
47dd7e60
PP		 1174 if (mlx5_ecpf_vport_exists(esw->dev)) {
1175 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_ECPF);
1176 mlx5_del_flow_rules(flows[vport->index]);
1177 }
81cd229c 1178
47dd7e60
PP		 1179 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
1180 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_PF);
1181 mlx5_del_flow_rules(flows[vport->index]);
1182 }
ac004b83
RD		 1183 kvfree(flows);
1184}
1185
3aa33572
OG		 1186static int esw_add_fdb_miss_rule(struct mlx5_eswitch *esw)
1187{
66958ed9 1188 struct mlx5_flow_act flow_act = {0};
4c5009c5 1189 struct mlx5_flow_destination dest = {};
74491de9 1190 struct mlx5_flow_handle *flow_rule = NULL;
c5bb1730 1191 struct mlx5_flow_spec *spec;
f80be543
MB		 1192 void *headers_c;
1193 void *headers_v;
3aa33572 1194 int err = 0;
f80be543
MB		 1195 u8 *dmac_c;
1196 u8 *dmac_v;
3aa33572 1197
1b9a07ee 1198 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
c5bb1730 1199 if (!spec) {
3aa33572
OG		 1200 err = -ENOMEM;
1201 goto out;
1202 }
1203
f80be543
MB		 1204 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
1205 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1206 outer_headers);
1207 dmac_c = MLX5_ADDR_OF(fte_match_param, headers_c,
1208 outer_headers.dmac_47_16);
1209 dmac_c[0] = 0x01;
1210
3aa33572 1211 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
a1b3839a 1212 dest.vport.num = esw->manager_vport;
66958ed9 1213 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3aa33572 1214
dcf19b9c 1215 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
39ac237c 1216 spec, &flow_act, &dest, 1);
3aa33572
OG		 1217 if (IS_ERR(flow_rule)) {
1218 err = PTR_ERR(flow_rule);
f80be543 1219 esw_warn(esw->dev, "FDB: Failed to add unicast miss flow rule err %d\n", err);
3aa33572
OG		 1220 goto out;
1221 }
1222
f80be543
MB		 1223 esw->fdb_table.offloads.miss_rule_uni = flow_rule;
1224
1225 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1226 outer_headers);
1227 dmac_v = MLX5_ADDR_OF(fte_match_param, headers_v,
1228 outer_headers.dmac_47_16);
1229 dmac_v[0] = 0x01;
dcf19b9c 1230 flow_rule = mlx5_add_flow_rules(mlx5_eswitch_get_slow_fdb(esw),
39ac237c 1231 spec, &flow_act, &dest, 1);
f80be543
MB		 1232 if (IS_ERR(flow_rule)) {
1233 err = PTR_ERR(flow_rule);
1234 esw_warn(esw->dev, "FDB: Failed to add multicast miss flow rule err %d\n", err);
1235 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
1236 goto out;
1237 }
1238
1239 esw->fdb_table.offloads.miss_rule_multi = flow_rule;
1240
3aa33572 1241out:
c5bb1730 1242 kvfree(spec);
3aa33572
OG		 1243 return err;
1244}
1245
11b717d6
PB		 1246struct mlx5_flow_handle *
1247esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag)
1248{
1249 struct mlx5_flow_act flow_act = { .flags = FLOW_ACT_NO_APPEND, };
1250 struct mlx5_flow_table *ft = esw->offloads.ft_offloads_restore;
1251 struct mlx5_flow_context *flow_context;
1252 struct mlx5_flow_handle *flow_rule;
1253 struct mlx5_flow_destination dest;
1254 struct mlx5_flow_spec *spec;
1255 void *misc;
1256
60acc105
PB		 1257 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
1258 return ERR_PTR(-EOPNOTSUPP);
1259
9f4d9283 1260 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
11b717d6
PB		 1261 if (!spec)
1262 return ERR_PTR(-ENOMEM);
1263
1264 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1265 misc_parameters_2);
1266 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 1267 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 1268 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1269 misc_parameters_2);
1270 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0, tag);
1271 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
6724e66b
PB		 1272 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1273 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1274 flow_act.modify_hdr = esw->offloads.restore_copy_hdr_id;
11b717d6
PB		 1275
1276 flow_context = &spec->flow_context;
1277 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1278 flow_context->flow_tag = tag;
1279 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1280 dest.ft = esw->offloads.ft_offloads;
1281
1282 flow_rule = mlx5_add_flow_rules(ft, spec, &flow_act, &dest, 1);
9f4d9283 1283 kvfree(spec);
11b717d6
PB		 1284
1285 if (IS_ERR(flow_rule))
1286 esw_warn(esw->dev,
1287 "Failed to create restore rule for tag: %d, err(%d)\n",
1288 tag, (int)PTR_ERR(flow_rule));
1289
1290 return flow_rule;
1291}
1292
1967ce6e 1293#define MAX_PF_SQ 256
cd3d07e7 1294#define MAX_SQ_NVPORTS 32
1967ce6e 1295
7eb197fd
RD		 1296void
1297mlx5_esw_set_flow_group_source_port(struct mlx5_eswitch *esw,
1298 u32 *flow_group_in,
1299 int match_params)
a5641cb5
JL		 1300{
1301 void *match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1302 flow_group_in,
1303 match_criteria);
1304
1305 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1306 MLX5_SET(create_flow_group_in, flow_group_in,
1307 match_criteria_enable,
29bcb6e4 1308 MLX5_MATCH_MISC_PARAMETERS_2 | match_params);
a5641cb5 1309
0f0d3827
PB		 1310 MLX5_SET(fte_match_param, match_criteria,
1311 misc_parameters_2.metadata_reg_c_0,
1312 mlx5_eswitch_get_vport_metadata_mask());
a5641cb5
JL		 1313 } else {
1314 MLX5_SET(create_flow_group_in, flow_group_in,
1315 match_criteria_enable,
29bcb6e4 1316 MLX5_MATCH_MISC_PARAMETERS | match_params);
a5641cb5
JL		 1317
1318 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1319 misc_parameters.source_port);
1320 }
1321}
1322
ae430332 1323#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
0a9e2307 1324static void esw_vport_tbl_put(struct mlx5_eswitch *esw)
4c7f4028
CM		 1325{
1326 struct mlx5_vport_tbl_attr attr;
1327 struct mlx5_vport *vport;
47dd7e60 1328 unsigned long i;
4c7f4028
CM		 1329
1330 attr.chain = 0;
1331 attr.prio = 1;
47dd7e60 1332 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1333 attr.vport = vport->vport;
c796bb7c 1334 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1335 mlx5_esw_vporttbl_put(esw, &attr);
4c7f4028
CM		 1336 }
1337}
1338
0a9e2307 1339static int esw_vport_tbl_get(struct mlx5_eswitch *esw)
4c7f4028
CM		 1340{
1341 struct mlx5_vport_tbl_attr attr;
1342 struct mlx5_flow_table *fdb;
1343 struct mlx5_vport *vport;
47dd7e60 1344 unsigned long i;
4c7f4028
CM		 1345
1346 attr.chain = 0;
1347 attr.prio = 1;
47dd7e60 1348 mlx5_esw_for_each_vport(esw, i, vport) {
4c7f4028 1349 attr.vport = vport->vport;
c796bb7c 1350 attr.vport_ns = &mlx5_esw_vport_tbl_mirror_ns;
0a9e2307 1351 fdb = mlx5_esw_vporttbl_get(esw, &attr);
4c7f4028
CM		 1352 if (IS_ERR(fdb))
1353 goto out;
1354 }
1355 return 0;
1356
1357out:
0a9e2307 1358 esw_vport_tbl_put(esw);
4c7f4028
CM		 1359 return PTR_ERR(fdb);
1360}
1361
ae430332
AL		 1362#define fdb_modify_header_fwd_to_table_supported(esw) \
1363 (MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table))
1364static void esw_init_chains_offload_flags(struct mlx5_eswitch *esw, u32 *flags)
1365{
1366 struct mlx5_core_dev *dev = esw->dev;
1367
1368 if (MLX5_CAP_ESW_FLOWTABLE_FDB(dev, ignore_flow_level))
1369 *flags |= MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
1370
1371 if (!MLX5_CAP_ESW_FLOWTABLE(dev, multi_fdb_encap) &&
1372 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
1373 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1374 esw_warn(dev, "Tc chains and priorities offload aren't supported, update firmware if needed\n");
1375 } else if (!mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
1376 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1377 esw_warn(dev, "Tc chains and priorities offload aren't supported\n");
1378 } else if (!fdb_modify_header_fwd_to_table_supported(esw)) {
1379 /* Disabled when ttl workaround is needed, e.g
1380 * when ESWITCH_IPV4_TTL_MODIFY_ENABLE = true in mlxconfig
1381 */
1382 esw_warn(dev,
1383 "Tc chains and priorities offload aren't supported, check firmware version, or mlxconfig settings\n");
1384 *flags &= ~MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1385 } else {
1386 *flags |= MLX5_CHAINS_AND_PRIOS_SUPPORTED;
1387 esw_info(dev, "Supported tc chains and prios offload\n");
1388 }
1389
1390 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1391 *flags |= MLX5_CHAINS_FT_TUNNEL_SUPPORTED;
1392}
1393
1394static int
1395esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1396{
1397 struct mlx5_core_dev *dev = esw->dev;
1398 struct mlx5_flow_table *nf_ft, *ft;
1399 struct mlx5_chains_attr attr = {};
1400 struct mlx5_fs_chains *chains;
ae430332
AL		 1401 int err;
1402
ae430332
AL		 1403 esw_init_chains_offload_flags(esw, &attr.flags);
1404 attr.ns = MLX5_FLOW_NAMESPACE_FDB;
8e80e564 1405 attr.fs_base_prio = FDB_TC_OFFLOAD;
ae430332
AL		 1406 attr.max_grp_num = esw->params.large_group_num;
1407 attr.default_ft = miss_fdb;
c9355682 1408 attr.mapping = esw->offloads.reg_c0_obj_pool;
ae430332
AL		 1409
1410 chains = mlx5_chains_create(dev, &attr);
1411 if (IS_ERR(chains)) {
1412 err = PTR_ERR(chains);
1413 esw_warn(dev, "Failed to create fdb chains err(%d)\n", err);
1414 return err;
1415 }
8e80e564 1416 mlx5_chains_print_info(chains);
ae430332
AL		 1417
1418 esw->fdb_table.offloads.esw_chains_priv = chains;
1419
1420 /* Create tc_end_ft which is the always created ft chain */
1421 nf_ft = mlx5_chains_get_table(chains, mlx5_chains_get_nf_ft_chain(chains),
1422 1, 0);
1423 if (IS_ERR(nf_ft)) {
1424 err = PTR_ERR(nf_ft);
1425 goto nf_ft_err;
1426 }
1427
1428 /* Always open the root for fast path */
1429 ft = mlx5_chains_get_table(chains, 0, 1, 0);
1430 if (IS_ERR(ft)) {
1431 err = PTR_ERR(ft);
1432 goto level_0_err;
1433 }
1434
1435 /* Open level 1 for split fdb rules now if prios isn't supported */
1436 if (!mlx5_chains_prios_supported(chains)) {
0a9e2307 1437 err = esw_vport_tbl_get(esw);
ae430332
AL		 1438 if (err)
1439 goto level_1_err;
1440 }
1441
1442 mlx5_chains_set_end_ft(chains, nf_ft);
1443
1444 return 0;
1445
1446level_1_err:
1447 mlx5_chains_put_table(chains, 0, 1, 0);
1448level_0_err:
1449 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1450nf_ft_err:
1451 mlx5_chains_destroy(chains);
1452 esw->fdb_table.offloads.esw_chains_priv = NULL;
1453
1454 return err;
1455}
1456
1457static void
1458esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1459{
1460 if (!mlx5_chains_prios_supported(chains))
0a9e2307 1461 esw_vport_tbl_put(esw);
ae430332
AL		 1462 mlx5_chains_put_table(chains, 0, 1, 0);
1463 mlx5_chains_put_table(chains, mlx5_chains_get_nf_ft_chain(chains), 1, 0);
1464 mlx5_chains_destroy(chains);
1465}
1466
1467#else /* CONFIG_MLX5_CLS_ACT */
1468
1469static int
1470esw_chains_create(struct mlx5_eswitch *esw, struct mlx5_flow_table *miss_fdb)
1471{ return 0; }
1472
1473static void
1474esw_chains_destroy(struct mlx5_eswitch *esw, struct mlx5_fs_chains *chains)
1475{}
1476
1477#endif
1478
4a561817
RD		 1479static int
1480esw_create_send_to_vport_group(struct mlx5_eswitch *esw,
1481 struct mlx5_flow_table *fdb,
1482 u32 *flow_group_in,
1483 int *ix)
1484{
1485 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1486 struct mlx5_flow_group *g;
1487 void *match_criteria;
1488 int count, err = 0;
1489
1490 memset(flow_group_in, 0, inlen);
1491
7eb197fd 1492 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, MLX5_MATCH_MISC_PARAMETERS);
4a561817
RD		 1493
1494 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
4a561817 1495 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_sqn);
29bcb6e4
RD		 1496
1497 if (!mlx5_eswitch_vport_match_metadata_enabled(esw) &&
1498 MLX5_CAP_ESW(esw->dev, merged_eswitch)) {
4a561817
RD		 1499 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1500 misc_parameters.source_eswitch_owner_vhca_id);
1501 MLX5_SET(create_flow_group_in, flow_group_in,
1502 source_eswitch_owner_vhca_id_valid, 1);
1503 }
1504
1505 /* See comment at table_size calculation */
1506 count = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ);
1507 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1508 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, *ix + count - 1);
1509 *ix += count;
1510
1511 g = mlx5_create_flow_group(fdb, flow_group_in);
1512 if (IS_ERR(g)) {
1513 err = PTR_ERR(g);
1514 esw_warn(esw->dev, "Failed to create send-to-vport flow group err(%d)\n", err);
1515 goto out;
1516 }
1517 esw->fdb_table.offloads.send_to_vport_grp = g;
1518
1519out:
1520 return err;
1521}
1522
1523static int
1524esw_create_meta_send_to_vport_group(struct mlx5_eswitch *esw,
1525 struct mlx5_flow_table *fdb,
1526 u32 *flow_group_in,
1527 int *ix)
1528{
1529 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
4a561817
RD		 1530 struct mlx5_flow_group *g;
1531 void *match_criteria;
1532 int err = 0;
1533
1534 if (!esw_src_port_rewrite_supported(esw))
1535 return 0;
1536
1537 memset(flow_group_in, 0, inlen);
1538
1539 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1540 MLX5_MATCH_MISC_PARAMETERS_2);
1541
1542 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1543
1544 MLX5_SET(fte_match_param, match_criteria,
1545 misc_parameters_2.metadata_reg_c_0,
1546 mlx5_eswitch_get_vport_metadata_mask());
1547 MLX5_SET(fte_match_param, match_criteria,
1548 misc_parameters_2.metadata_reg_c_1, ESW_TUN_MASK);
1549
430e2d5e
RD		 1550 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1551 MLX5_SET(create_flow_group_in, flow_group_in,
1552 end_flow_index, *ix + esw->total_vports - 1);
1553 *ix += esw->total_vports;
4a561817 1554
430e2d5e
RD		 1555 g = mlx5_create_flow_group(fdb, flow_group_in);
1556 if (IS_ERR(g)) {
1557 err = PTR_ERR(g);
1558 esw_warn(esw->dev,
1559 "Failed to create send-to-vport meta flow group err(%d)\n", err);
1560 goto send_vport_meta_err;
4a561817 1561 }
430e2d5e 1562 esw->fdb_table.offloads.send_to_vport_meta_grp = g;
4a561817
RD		 1563
1564 return 0;
1565
4a561817
RD		 1566send_vport_meta_err:
1567 return err;
1568}
1569
1570static int
1571esw_create_peer_esw_miss_group(struct mlx5_eswitch *esw,
1572 struct mlx5_flow_table *fdb,
1573 u32 *flow_group_in,
1574 int *ix)
1575{
1576 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1577 struct mlx5_flow_group *g;
1578 void *match_criteria;
1579 int err = 0;
1580
1581 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
1582 return 0;
1583
1584 memset(flow_group_in, 0, inlen);
1585
7eb197fd 1586 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
4a561817
RD		 1587
1588 if (!mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1589 match_criteria = MLX5_ADDR_OF(create_flow_group_in,
1590 flow_group_in,
1591 match_criteria);
1592
1593 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
1594 misc_parameters.source_eswitch_owner_vhca_id);
1595
1596 MLX5_SET(create_flow_group_in, flow_group_in,
1597 source_eswitch_owner_vhca_id_valid, 1);
1598 }
1599
1600 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1601 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1602 *ix + esw->total_vports - 1);
1603 *ix += esw->total_vports;
1604
1605 g = mlx5_create_flow_group(fdb, flow_group_in);
1606 if (IS_ERR(g)) {
1607 err = PTR_ERR(g);
1608 esw_warn(esw->dev, "Failed to create peer miss flow group err(%d)\n", err);
1609 goto out;
1610 }
1611 esw->fdb_table.offloads.peer_miss_grp = g;
1612
1613out:
1614 return err;
1615}
1616
1617static int
1618esw_create_miss_group(struct mlx5_eswitch *esw,
1619 struct mlx5_flow_table *fdb,
1620 u32 *flow_group_in,
1621 int *ix)
1622{
1623 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1624 struct mlx5_flow_group *g;
1625 void *match_criteria;
1626 int err = 0;
1627 u8 *dmac;
1628
1629 memset(flow_group_in, 0, inlen);
1630
1631 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
1632 MLX5_MATCH_OUTER_HEADERS);
1633 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
1634 match_criteria);
1635 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
1636 outer_headers.dmac_47_16);
1637 dmac[0] = 0x01;
1638
1639 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, *ix);
1640 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
1641 *ix + MLX5_ESW_MISS_FLOWS);
1642
1643 g = mlx5_create_flow_group(fdb, flow_group_in);
1644 if (IS_ERR(g)) {
1645 err = PTR_ERR(g);
1646 esw_warn(esw->dev, "Failed to create miss flow group err(%d)\n", err);
1647 goto miss_err;
1648 }
1649 esw->fdb_table.offloads.miss_grp = g;
1650
1651 err = esw_add_fdb_miss_rule(esw);
1652 if (err)
1653 goto miss_rule_err;
1654
1655 return 0;
1656
1657miss_rule_err:
1658 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1659miss_err:
1660 return err;
1661}
1662
0da3c12d 1663static int esw_create_offloads_fdb_tables(struct mlx5_eswitch *esw)
1967ce6e
OG		 1664{
1665 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1666 struct mlx5_flow_table_attr ft_attr = {};
1667 struct mlx5_core_dev *dev = esw->dev;
1668 struct mlx5_flow_namespace *root_ns;
1669 struct mlx5_flow_table *fdb = NULL;
4a561817 1670 int table_size, ix = 0, err = 0;
39ac237c 1671 u32 flags = 0, *flow_group_in;
1967ce6e
OG		 1672
1673 esw_debug(esw->dev, "Create offloads FDB Tables\n");
39ac237c 1674
1b9a07ee 1675 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1967ce6e
OG		 1676 if (!flow_group_in)
1677 return -ENOMEM;
1678
1679 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
1680 if (!root_ns) {
1681 esw_warn(dev, "Failed to get FDB flow namespace\n");
1682 err = -EOPNOTSUPP;
1683 goto ns_err;
1684 }
8463daf1
MG		 1685 esw->fdb_table.offloads.ns = root_ns;
1686 err = mlx5_flow_namespace_set_mode(root_ns,
1687 esw->dev->priv.steering->mode);
1688 if (err) {
1689 esw_warn(dev, "Failed to set FDB namespace steering mode\n");
1690 goto ns_err;
1691 }
1967ce6e 1692
898b0786
MB		 1693 /* To be strictly correct:
1694 * MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ)
1695 * should be:
1696 * esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ +
1697 * peer_esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ
1698 * but as the peer device might not be in switchdev mode it's not
1699 * possible. We use the fact that by default FW sets max vfs and max sfs
1700 * to the same value on both devices. If it needs to be changed in the future note
1701 * the peer miss group should also be created based on the number of
1702 * total vports of the peer (currently is also uses esw->total_vports).
1703 */
1704 table_size = MLX5_MAX_PORTS * (esw->total_vports * MAX_SQ_NVPORTS + MAX_PF_SQ) +
430e2d5e 1705 esw->total_vports * 2 + MLX5_ESW_MISS_FLOWS;
b3ba5149 1706
e52c2802
PB		 1707 /* create the slow path fdb with encap set, so further table instances
1708 * can be created at run time while VFs are probed if the FW allows that.
1709 */
1710 if (esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE)
1711 flags |= (MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT |
1712 MLX5_FLOW_TABLE_TUNNEL_EN_DECAP);
1713
1714 ft_attr.flags = flags;
b3ba5149
ES		 1715 ft_attr.max_fte = table_size;
1716 ft_attr.prio = FDB_SLOW_PATH;
1717
1718 fdb = mlx5_create_flow_table(root_ns, &ft_attr);
1033665e
OG		 1719 if (IS_ERR(fdb)) {
1720 err = PTR_ERR(fdb);
1721 esw_warn(dev, "Failed to create slow path FDB Table err %d\n", err);
1722 goto slow_fdb_err;
1723 }
52fff327 1724 esw->fdb_table.offloads.slow_fdb = fdb;
1033665e 1725
ec3be887
VB		 1726 /* Create empty TC-miss managed table. This allows plugging in following
1727 * priorities without directly exposing their level 0 table to
1728 * eswitch_offloads and passing it as miss_fdb to following call to
1729 * esw_chains_create().
1730 */
1731 memset(&ft_attr, 0, sizeof(ft_attr));
1732 ft_attr.prio = FDB_TC_MISS;
1733 esw->fdb_table.offloads.tc_miss_table = mlx5_create_flow_table(root_ns, &ft_attr);
1734 if (IS_ERR(esw->fdb_table.offloads.tc_miss_table)) {
1735 err = PTR_ERR(esw->fdb_table.offloads.tc_miss_table);
1736 esw_warn(dev, "Failed to create TC miss FDB Table err %d\n", err);
1737 goto tc_miss_table_err;
1738 }
1739
1740 err = esw_chains_create(esw, esw->fdb_table.offloads.tc_miss_table);
39ac237c 1741 if (err) {
ae430332 1742 esw_warn(dev, "Failed to open fdb chains err(%d)\n", err);
39ac237c 1743 goto fdb_chains_err;
e52c2802
PB		 1744 }
1745
4a561817
RD		 1746 err = esw_create_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1747 if (err)
69697b6e 1748 goto send_vport_err;
8e404fef 1749
4a561817
RD		 1750 err = esw_create_meta_send_to_vport_group(esw, fdb, flow_group_in, &ix);
1751 if (err)
1752 goto send_vport_meta_err;
69697b6e 1753
4a561817
RD		 1754 err = esw_create_peer_esw_miss_group(esw, fdb, flow_group_in, &ix);
1755 if (err)
1756 goto peer_miss_err;
69697b6e 1757
4a561817 1758 err = esw_create_miss_group(esw, fdb, flow_group_in, &ix);
3aa33572 1759 if (err)
4a561817 1760 goto miss_err;
3aa33572 1761
c88a026e 1762 kvfree(flow_group_in);
69697b6e
OG		 1763 return 0;
1764
1765miss_err:
6cec0229
MD		 1766 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1767 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
ac004b83 1768peer_miss_err:
8e404fef
VB		 1769 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1770 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
1771send_vport_meta_err:
69697b6e
OG		 1772 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
1773send_vport_err:
ae430332 1774 esw_chains_destroy(esw, esw_chains(esw));
39ac237c 1775fdb_chains_err:
ec3be887
VB		 1776 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
1777tc_miss_table_err:
dcf19b9c 1778 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
1033665e 1779slow_fdb_err:
8463daf1
MG		 1780 /* Holds true only as long as DMFS is the default */
1781 mlx5_flow_namespace_set_mode(root_ns, MLX5_FLOW_STEERING_MODE_DMFS);
69697b6e
OG		 1782ns_err:
1783 kvfree(flow_group_in);
1784 return err;
1785}
1786
1967ce6e 1787static void esw_destroy_offloads_fdb_tables(struct mlx5_eswitch *esw)
69697b6e 1788{
dcf19b9c 1789 if (!mlx5_eswitch_get_slow_fdb(esw))
69697b6e
OG		 1790 return;
1791
1967ce6e 1792 esw_debug(esw->dev, "Destroy offloads FDB Tables\n");
f80be543
MB		 1793 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_multi);
1794 mlx5_del_flow_rules(esw->fdb_table.offloads.miss_rule_uni);
69697b6e 1795 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_grp);
8e404fef
VB		 1796 if (esw->fdb_table.offloads.send_to_vport_meta_grp)
1797 mlx5_destroy_flow_group(esw->fdb_table.offloads.send_to_vport_meta_grp);
6cec0229
MD		 1798 if (MLX5_CAP_ESW(esw->dev, merged_eswitch))
1799 mlx5_destroy_flow_group(esw->fdb_table.offloads.peer_miss_grp);
69697b6e
OG		 1800 mlx5_destroy_flow_group(esw->fdb_table.offloads.miss_grp);
1801
ae430332
AL		 1802 esw_chains_destroy(esw, esw_chains(esw));
1803
ec3be887 1804 mlx5_destroy_flow_table(esw->fdb_table.offloads.tc_miss_table);
dcf19b9c 1805 mlx5_destroy_flow_table(mlx5_eswitch_get_slow_fdb(esw));
8463daf1
MG		 1806 /* Holds true only as long as DMFS is the default */
1807 mlx5_flow_namespace_set_mode(esw->fdb_table.offloads.ns,
1808 MLX5_FLOW_STEERING_MODE_DMFS);
7dc84de9 1809 atomic64_set(&esw->user_count, 0);
69697b6e 1810}
c116c6ee 1811
8ea7bcf6 1812static int esw_get_nr_ft_offloads_steering_src_ports(struct mlx5_eswitch *esw)
4f4edcc2
AL		 1813{
1814 int nvports;
1815
1816 nvports = esw->total_vports + MLX5_ESW_MISS_FLOWS;
1817 if (mlx5e_tc_int_port_supported(esw))
1818 nvports += MLX5E_TC_MAX_INT_PORT_NUM;
1819
1820 return nvports;
1821}
1822
8d6bd3c3 1823static int esw_create_offloads_table(struct mlx5_eswitch *esw)
c116c6ee 1824{
b3ba5149 1825 struct mlx5_flow_table_attr ft_attr = {};
c116c6ee 1826 struct mlx5_core_dev *dev = esw->dev;
b3ba5149
ES		 1827 struct mlx5_flow_table *ft_offloads;
1828 struct mlx5_flow_namespace *ns;
c116c6ee
OG		 1829 int err = 0;
1830
1831 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
1832 if (!ns) {
1833 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
eff596da 1834 return -EOPNOTSUPP;
c116c6ee
OG		 1835 }
1836
8ea7bcf6
JL		 1837 ft_attr.max_fte = esw_get_nr_ft_offloads_steering_src_ports(esw) +
1838 MLX5_ESW_FT_OFFLOADS_DROP_RULE;
11b717d6 1839 ft_attr.prio = 1;
b3ba5149
ES		 1840
1841 ft_offloads = mlx5_create_flow_table(ns, &ft_attr);
c116c6ee
OG		 1842 if (IS_ERR(ft_offloads)) {
1843 err = PTR_ERR(ft_offloads);
1844 esw_warn(esw->dev, "Failed to create offloads table, err %d\n", err);
1845 return err;
1846 }
1847
1848 esw->offloads.ft_offloads = ft_offloads;
1849 return 0;
1850}
1851
1852static void esw_destroy_offloads_table(struct mlx5_eswitch *esw)
1853{
1854 struct mlx5_esw_offload *offloads = &esw->offloads;
1855
1856 mlx5_destroy_flow_table(offloads->ft_offloads);
1857}
fed9ce22 1858
8d6bd3c3 1859static int esw_create_vport_rx_group(struct mlx5_eswitch *esw)
fed9ce22
OG		 1860{
1861 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1862 struct mlx5_flow_group *g;
fed9ce22 1863 u32 *flow_group_in;
8d6bd3c3 1864 int nvports;
fed9ce22 1865 int err = 0;
fed9ce22 1866
8ea7bcf6 1867 nvports = esw_get_nr_ft_offloads_steering_src_ports(esw);
1b9a07ee 1868 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
fed9ce22
OG		 1869 if (!flow_group_in)
1870 return -ENOMEM;
1871
1872 /* create vport rx group */
7eb197fd 1873 mlx5_esw_set_flow_group_source_port(esw, flow_group_in, 0);
fed9ce22
OG		 1874
1875 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1876 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, nvports - 1);
1877
1878 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1879
1880 if (IS_ERR(g)) {
1881 err = PTR_ERR(g);
1882 mlx5_core_warn(esw->dev, "Failed to create vport rx group err %d\n", err);
1883 goto out;
1884 }
1885
1886 esw->offloads.vport_rx_group = g;
1887out:
e574978a 1888 kvfree(flow_group_in);
fed9ce22
OG		 1889 return err;
1890}
1891
1892static void esw_destroy_vport_rx_group(struct mlx5_eswitch *esw)
1893{
1894 mlx5_destroy_flow_group(esw->offloads.vport_rx_group);
1895}
1896
8ea7bcf6
JL		 1897static int esw_create_vport_rx_drop_rule_index(struct mlx5_eswitch *esw)
1898{
1899 /* ft_offloads table is enlarged by MLX5_ESW_FT_OFFLOADS_DROP_RULE (1)
1900 * for the drop rule, which is placed at the end of the table.
1901 * So return the total of vport and int_port as rule index.
1902 */
1903 return esw_get_nr_ft_offloads_steering_src_ports(esw);
1904}
1905
1906static int esw_create_vport_rx_drop_group(struct mlx5_eswitch *esw)
1907{
1908 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1909 struct mlx5_flow_group *g;
1910 u32 *flow_group_in;
1911 int flow_index;
1912 int err = 0;
1913
1914 flow_index = esw_create_vport_rx_drop_rule_index(esw);
1915
1916 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
1917 if (!flow_group_in)
1918 return -ENOMEM;
1919
1920 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, flow_index);
1921 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, flow_index);
1922
1923 g = mlx5_create_flow_group(esw->offloads.ft_offloads, flow_group_in);
1924
1925 if (IS_ERR(g)) {
1926 err = PTR_ERR(g);
1927 mlx5_core_warn(esw->dev, "Failed to create vport rx drop group err %d\n", err);
1928 goto out;
1929 }
1930
1931 esw->offloads.vport_rx_drop_group = g;
1932out:
1933 kvfree(flow_group_in);
1934 return err;
1935}
1936
1937static void esw_destroy_vport_rx_drop_group(struct mlx5_eswitch *esw)
1938{
1939 if (esw->offloads.vport_rx_drop_group)
1940 mlx5_destroy_flow_group(esw->offloads.vport_rx_drop_group);
1941}
1942
7eb197fd
RD		 1943void
1944mlx5_esw_set_spec_source_port(struct mlx5_eswitch *esw,
1945 u16 vport,
1946 struct mlx5_flow_spec *spec)
fed9ce22 1947{
fed9ce22
OG		 1948 void *misc;
1949
a5641cb5
JL		 1950 if (mlx5_eswitch_vport_match_metadata_enabled(esw)) {
1951 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2);
1952 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1953 mlx5_eswitch_get_vport_metadata_for_match(esw, vport));
fed9ce22 1954
a5641cb5 1955 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters_2);
0f0d3827
PB		 1956 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
1957 mlx5_eswitch_get_vport_metadata_mask());
fed9ce22 1958
a5641cb5
JL		 1959 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS_2;
1960 } else {
1961 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters);
1962 MLX5_SET(fte_match_set_misc, misc, source_port, vport);
1963
1964 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
1965 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
1966
1967 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
1968 }
7eb197fd
RD		 1969}
1970
1971struct mlx5_flow_handle *
1972mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
1973 struct mlx5_flow_destination *dest)
1974{
1975 struct mlx5_flow_act flow_act = {0};
1976 struct mlx5_flow_handle *flow_rule;
1977 struct mlx5_flow_spec *spec;
1978
1979 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
1980 if (!spec) {
1981 flow_rule = ERR_PTR(-ENOMEM);
1982 goto out;
1983 }
1984
1985 mlx5_esw_set_spec_source_port(esw, vport, spec);
fed9ce22 1986
66958ed9 1987 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
74491de9 1988 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, spec,
c966f7d5 1989 &flow_act, dest, 1);
fed9ce22
OG		 1990 if (IS_ERR(flow_rule)) {
1991 esw_warn(esw->dev, "fs offloads: Failed to add vport rx rule err %ld\n", PTR_ERR(flow_rule));
1992 goto out;
1993 }
1994
1995out:
c5bb1730 1996 kvfree(spec);
fed9ce22
OG		 1997 return flow_rule;
1998}
feae9087 1999
8ea7bcf6
JL		 2000static int esw_create_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2001{
2002 struct mlx5_flow_act flow_act = {};
2003 struct mlx5_flow_handle *flow_rule;
2004
2005 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2006 flow_rule = mlx5_add_flow_rules(esw->offloads.ft_offloads, NULL,
2007 &flow_act, NULL, 0);
2008 if (IS_ERR(flow_rule)) {
2009 esw_warn(esw->dev,
2010 "fs offloads: Failed to add vport rx drop rule err %ld\n",
2011 PTR_ERR(flow_rule));
2012 return PTR_ERR(flow_rule);
2013 }
2014
2015 esw->offloads.vport_rx_drop_rule = flow_rule;
2016
2017 return 0;
2018}
2019
2020static void esw_destroy_vport_rx_drop_rule(struct mlx5_eswitch *esw)
2021{
2022 if (esw->offloads.vport_rx_drop_rule)
2023 mlx5_del_flow_rules(esw->offloads.vport_rx_drop_rule);
2024}
2025
47dd7e60 2026static int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, u8 *mode)
cc617ced
PP		 2027{
2028 u8 prev_mlx5_mode, mlx5_mode = MLX5_INLINE_MODE_L2;
2029 struct mlx5_core_dev *dev = esw->dev;
47dd7e60
PP		 2030 struct mlx5_vport *vport;
2031 unsigned long i;
cc617ced
PP		 2032
2033 if (!MLX5_CAP_GEN(dev, vport_group_manager))
2034 return -EOPNOTSUPP;
2035
f019679e 2036 if (!mlx5_esw_is_fdb_created(esw))
cc617ced
PP		 2037 return -EOPNOTSUPP;
2038
2039 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
2040 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2041 mlx5_mode = MLX5_INLINE_MODE_NONE;
2042 goto out;
2043 case MLX5_CAP_INLINE_MODE_L2:
2044 mlx5_mode = MLX5_INLINE_MODE_L2;
2045 goto out;
2046 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2047 goto query_vports;
2048 }
2049
2050query_vports:
2051 mlx5_query_nic_vport_min_inline(dev, esw->first_host_vport, &prev_mlx5_mode);
47dd7e60
PP		 2052 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
2053 mlx5_query_nic_vport_min_inline(dev, vport->vport, &mlx5_mode);
cc617ced
PP		 2054 if (prev_mlx5_mode != mlx5_mode)
2055 return -EINVAL;
2056 prev_mlx5_mode = mlx5_mode;
2057 }
2058
2059out:
2060 *mode = mlx5_mode;
2061 return 0;
e08a6832 2062}
bf3347c4 2063
11b717d6
PB		 2064static void esw_destroy_restore_table(struct mlx5_eswitch *esw)
2065{
2066 struct mlx5_esw_offload *offloads = &esw->offloads;
2067
60acc105
PB		 2068 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2069 return;
2070
6724e66b 2071 mlx5_modify_header_dealloc(esw->dev, offloads->restore_copy_hdr_id);
11b717d6
PB		 2072 mlx5_destroy_flow_group(offloads->restore_group);
2073 mlx5_destroy_flow_table(offloads->ft_offloads_restore);
2074}
2075
2076static int esw_create_restore_table(struct mlx5_eswitch *esw)
2077{
d65dbedf 2078 u8 modact[MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)] = {};
11b717d6
PB		 2079 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2080 struct mlx5_flow_table_attr ft_attr = {};
2081 struct mlx5_core_dev *dev = esw->dev;
2082 struct mlx5_flow_namespace *ns;
6724e66b 2083 struct mlx5_modify_hdr *mod_hdr;
11b717d6
PB		 2084 void *match_criteria, *misc;
2085 struct mlx5_flow_table *ft;
2086 struct mlx5_flow_group *g;
2087 u32 *flow_group_in;
2088 int err = 0;
2089
60acc105
PB		 2090 if (!mlx5_eswitch_reg_c1_loopback_supported(esw))
2091 return 0;
2092
11b717d6
PB		 2093 ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_OFFLOADS);
2094 if (!ns) {
2095 esw_warn(esw->dev, "Failed to get offloads flow namespace\n");
2096 return -EOPNOTSUPP;
2097 }
2098
2099 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2100 if (!flow_group_in) {
2101 err = -ENOMEM;
2102 goto out_free;
2103 }
2104
a91d98a0 2105 ft_attr.max_fte = 1 << ESW_REG_C0_USER_DATA_METADATA_BITS;
11b717d6
PB		 2106 ft = mlx5_create_flow_table(ns, &ft_attr);
2107 if (IS_ERR(ft)) {
2108 err = PTR_ERR(ft);
2109 esw_warn(esw->dev, "Failed to create restore table, err %d\n",
2110 err);
2111 goto out_free;
2112 }
2113
11b717d6
PB		 2114 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2115 match_criteria);
2116 misc = MLX5_ADDR_OF(fte_match_param, match_criteria,
2117 misc_parameters_2);
2118
2119 MLX5_SET(fte_match_set_misc2, misc, metadata_reg_c_0,
a91d98a0 2120 ESW_REG_C0_USER_DATA_METADATA_MASK);
11b717d6
PB		 2121 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2122 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index,
2123 ft_attr.max_fte - 1);
2124 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2125 MLX5_MATCH_MISC_PARAMETERS_2);
2126 g = mlx5_create_flow_group(ft, flow_group_in);
2127 if (IS_ERR(g)) {
2128 err = PTR_ERR(g);
2129 esw_warn(dev, "Failed to create restore flow group, err: %d\n",
2130 err);
2131 goto err_group;
2132 }
2133
6724e66b
PB		 2134 MLX5_SET(copy_action_in, modact, action_type, MLX5_ACTION_TYPE_COPY);
2135 MLX5_SET(copy_action_in, modact, src_field,
2136 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1);
2137 MLX5_SET(copy_action_in, modact, dst_field,
2138 MLX5_ACTION_IN_FIELD_METADATA_REG_B);
2139 mod_hdr = mlx5_modify_header_alloc(esw->dev,
2140 MLX5_FLOW_NAMESPACE_KERNEL, 1,
2141 modact);
2142 if (IS_ERR(mod_hdr)) {
e9864539 2143 err = PTR_ERR(mod_hdr);
6724e66b
PB		 2144 esw_warn(dev, "Failed to create restore mod header, err: %d\n",
2145 err);
6724e66b
PB		 2146 goto err_mod_hdr;
2147 }
2148
11b717d6
PB		 2149 esw->offloads.ft_offloads_restore = ft;
2150 esw->offloads.restore_group = g;
6724e66b 2151 esw->offloads.restore_copy_hdr_id = mod_hdr;
11b717d6 2152
c8508713
RD		 2153 kvfree(flow_group_in);
2154
11b717d6
PB		 2155 return 0;
2156
6724e66b
PB		 2157err_mod_hdr:
2158 mlx5_destroy_flow_group(g);
11b717d6
PB		 2159err_group:
2160 mlx5_destroy_flow_table(ft);
2161out_free:
2162 kvfree(flow_group_in);
2163
2164 return err;
cc617ced
PP		 2165}
2166
db7ff19e
EB		 2167static int esw_offloads_start(struct mlx5_eswitch *esw,
2168 struct netlink_ext_ack *extack)
c930a3ad 2169{
e12de39c 2170 int err;
c930a3ad 2171
b6f2846a
CM		 2172 esw->mode = MLX5_ESWITCH_OFFLOADS;
2173 err = mlx5_eswitch_enable_locked(esw, esw->dev->priv.sriov.num_vfs);
6c419ba8 2174 if (err) {
8c98ee77
EB		 2175 NL_SET_ERR_MSG_MOD(extack,
2176 "Failed setting eswitch to offloads");
b6f2846a 2177 esw->mode = MLX5_ESWITCH_LEGACY;
b6f2846a 2178 mlx5_rescan_drivers(esw->dev);
6c419ba8 2179 }
bffaa916
RD		 2180 if (esw->offloads.inline_mode == MLX5_INLINE_MODE_NONE) {
2181 if (mlx5_eswitch_inline_mode_get(esw,
bffaa916
RD		 2182 &esw->offloads.inline_mode)) {
2183 esw->offloads.inline_mode = MLX5_INLINE_MODE_L2;
8c98ee77
EB		 2184 NL_SET_ERR_MSG_MOD(extack,
2185 "Inline mode is different between vports");
bffaa916
RD		 2186 }
2187 }
c930a3ad
OG		 2188 return err;
2189}
2190
47dd7e60
PP		 2191static void mlx5_esw_offloads_rep_mark_set(struct mlx5_eswitch *esw,
2192 struct mlx5_eswitch_rep *rep,
2193 xa_mark_t mark)
e8d31c4d 2194{
47dd7e60
PP		 2195 bool mark_set;
2196
2197 /* Copy the mark from vport to its rep */
2198 mark_set = xa_get_mark(&esw->vports, rep->vport, mark);
2199 if (mark_set)
2200 xa_set_mark(&esw->offloads.vport_reps, rep->vport, mark);
e8d31c4d
MB		 2201}
2202
47dd7e60 2203static int mlx5_esw_offloads_rep_init(struct mlx5_eswitch *esw, const struct mlx5_vport *vport)
e8d31c4d 2204{
e8d31c4d 2205 struct mlx5_eswitch_rep *rep;
47dd7e60
PP		 2206 int rep_type;
2207 int err;
e8d31c4d 2208
47dd7e60
PP		 2209 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
2210 if (!rep)
e8d31c4d
MB		 2211 return -ENOMEM;
2212
47dd7e60
PP		 2213 rep->vport = vport->vport;
2214 rep->vport_index = vport->index;
2215 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2216 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
f121e0ea 2217
47dd7e60
PP		 2218 err = xa_insert(&esw->offloads.vport_reps, rep->vport, rep, GFP_KERNEL);
2219 if (err)
2220 goto insert_err;
2221
2222 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_HOST_FN);
2223 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_VF);
2224 mlx5_esw_offloads_rep_mark_set(esw, rep, MLX5_ESW_VPT_SF);
2225 return 0;
2226
2227insert_err:
2228 kfree(rep);
2229 return err;
2230}
2231
2232static void mlx5_esw_offloads_rep_cleanup(struct mlx5_eswitch *esw,
2233 struct mlx5_eswitch_rep *rep)
2234{
2235 xa_erase(&esw->offloads.vport_reps, rep->vport);
2236 kfree(rep);
2237}
2238
d2a651ef 2239static void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw)
47dd7e60
PP		 2240{
2241 struct mlx5_eswitch_rep *rep;
2242 unsigned long i;
e8d31c4d 2243
47dd7e60
PP		 2244 mlx5_esw_for_each_rep(esw, i, rep)
2245 mlx5_esw_offloads_rep_cleanup(esw, rep);
2246 xa_destroy(&esw->offloads.vport_reps);
2247}
2248
d2a651ef 2249static int esw_offloads_init_reps(struct mlx5_eswitch *esw)
47dd7e60
PP		 2250{
2251 struct mlx5_vport *vport;
2252 unsigned long i;
2253 int err;
2254
2255 xa_init(&esw->offloads.vport_reps);
2256
2257 mlx5_esw_for_each_vport(esw, i, vport) {
2258 err = mlx5_esw_offloads_rep_init(esw, vport);
2259 if (err)
2260 goto err;
2261 }
e8d31c4d 2262 return 0;
47dd7e60
PP		 2263
2264err:
2265 esw_offloads_cleanup_reps(esw);
2266 return err;
e8d31c4d
MB		 2267}
2268
d2a651ef
JP		 2269static int esw_port_metadata_set(struct devlink *devlink, u32 id,
2270 struct devlink_param_gset_ctx *ctx)
2271{
2272 struct mlx5_core_dev *dev = devlink_priv(devlink);
2273 struct mlx5_eswitch *esw = dev->priv.eswitch;
2274 int err = 0;
2275
2276 down_write(&esw->mode_lock);
2277 if (mlx5_esw_is_fdb_created(esw)) {
2278 err = -EBUSY;
2279 goto done;
2280 }
2281 if (!mlx5_esw_vport_match_metadata_supported(esw)) {
2282 err = -EOPNOTSUPP;
2283 goto done;
2284 }
2285 if (ctx->val.vbool)
2286 esw->flags |= MLX5_ESWITCH_VPORT_MATCH_METADATA;
2287 else
2288 esw->flags &= ~MLX5_ESWITCH_VPORT_MATCH_METADATA;
2289done:
2290 up_write(&esw->mode_lock);
2291 return err;
2292}
2293
2294static int esw_port_metadata_get(struct devlink *devlink, u32 id,
2295 struct devlink_param_gset_ctx *ctx)
2296{
2297 struct mlx5_core_dev *dev = devlink_priv(devlink);
2298
2299 ctx->val.vbool = mlx5_eswitch_vport_match_metadata_enabled(dev->priv.eswitch);
2300 return 0;
2301}
2302
2303static int esw_port_metadata_validate(struct devlink *devlink, u32 id,
2304 union devlink_param_value val,
2305 struct netlink_ext_ack *extack)
2306{
2307 struct mlx5_core_dev *dev = devlink_priv(devlink);
2308 u8 esw_mode;
2309
2310 esw_mode = mlx5_eswitch_mode(dev);
2311 if (esw_mode == MLX5_ESWITCH_OFFLOADS) {
2312 NL_SET_ERR_MSG_MOD(extack,
2313 "E-Switch must either disabled or non switchdev mode");
2314 return -EBUSY;
2315 }
2316 return 0;
2317}
2318
2319static const struct devlink_param esw_devlink_params[] = {
2320 DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_ESW_PORT_METADATA,
2321 "esw_port_metadata", DEVLINK_PARAM_TYPE_BOOL,
2322 BIT(DEVLINK_PARAM_CMODE_RUNTIME),
2323 esw_port_metadata_get,
2324 esw_port_metadata_set,
2325 esw_port_metadata_validate),
2326};
2327
2328int esw_offloads_init(struct mlx5_eswitch *esw)
2329{
2330 int err;
2331
2332 err = esw_offloads_init_reps(esw);
2333 if (err)
2334 return err;
2335
2336 err = devl_params_register(priv_to_devlink(esw->dev),
2337 esw_devlink_params,
2338 ARRAY_SIZE(esw_devlink_params));
2339 if (err)
2340 goto err_params;
2341
2342 return 0;
2343
2344err_params:
2345 esw_offloads_cleanup_reps(esw);
2346 return err;
2347}
2348
2349void esw_offloads_cleanup(struct mlx5_eswitch *esw)
2350{
2351 devl_params_unregister(priv_to_devlink(esw->dev),
2352 esw_devlink_params,
2353 ARRAY_SIZE(esw_devlink_params));
2354 esw_offloads_cleanup_reps(esw);
2355}
2356
c9b99abc
BW		 2357static void __esw_offloads_unload_rep(struct mlx5_eswitch *esw,
2358 struct mlx5_eswitch_rep *rep, u8 rep_type)
2359{
8693115a 2360 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
6f4e0219 2361 REP_LOADED, REP_REGISTERED) == REP_LOADED)
8693115a 2362 esw->offloads.rep_ops[rep_type]->unload(rep);
c9b99abc
BW		 2363}
2364
d7f33a45
VP		 2365static void __unload_reps_sf_vport(struct mlx5_eswitch *esw, u8 rep_type)
2366{
2367 struct mlx5_eswitch_rep *rep;
47dd7e60 2368 unsigned long i;
d7f33a45
VP		 2369
2370 mlx5_esw_for_each_sf_rep(esw, i, rep)
2371 __esw_offloads_unload_rep(esw, rep, rep_type);
2372}
2373
4110fc59 2374static void __unload_reps_all_vport(struct mlx5_eswitch *esw, u8 rep_type)
6ed1803a
MB		 2375{
2376 struct mlx5_eswitch_rep *rep;
47dd7e60 2377 unsigned long i;
4110fc59 2378
d7f33a45
VP		 2379 __unload_reps_sf_vport(esw, rep_type);
2380
47dd7e60 2381 mlx5_esw_for_each_vf_rep(esw, i, rep)
4110fc59 2382 __esw_offloads_unload_rep(esw, rep, rep_type);
c9b99abc 2383
81cd229c
BW		 2384 if (mlx5_ecpf_vport_exists(esw->dev)) {
2385 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_ECPF);
2386 __esw_offloads_unload_rep(esw, rep, rep_type);
2387 }
2388
2389 if (mlx5_core_is_ecpf_esw_manager(esw->dev)) {
2390 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_PF);
2391 __esw_offloads_unload_rep(esw, rep, rep_type);
2392 }
2393
879c8f84 2394 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
c9b99abc 2395 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2396}
2397
d970812b 2398int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num)
a4b97ab4 2399{
c2d7712c
BW		 2400 struct mlx5_eswitch_rep *rep;
2401 int rep_type;
a4b97ab4
MB		 2402 int err;
2403
c2d7712c
BW		 2404 rep = mlx5_eswitch_get_rep(esw, vport_num);
2405 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++)
2406 if (atomic_cmpxchg(&rep->rep_data[rep_type].state,
2407 REP_REGISTERED, REP_LOADED) == REP_REGISTERED) {
2408 err = esw->offloads.rep_ops[rep_type]->load(esw->dev, rep);
2409 if (err)
2410 goto err_reps;
2411 }
2412
2413 return 0;
a4b97ab4
MB		 2414
2415err_reps:
c2d7712c
BW		 2416 atomic_set(&rep->rep_data[rep_type].state, REP_REGISTERED);
2417 for (--rep_type; rep_type >= 0; rep_type--)
2418 __esw_offloads_unload_rep(esw, rep, rep_type);
6ed1803a
MB		 2419 return err;
2420}
2421
d970812b 2422void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num)
c2d7712c
BW		 2423{
2424 struct mlx5_eswitch_rep *rep;
2425 int rep_type;
2426
c2d7712c
BW		 2427 rep = mlx5_eswitch_get_rep(esw, vport_num);
2428 for (rep_type = NUM_REP_TYPES - 1; rep_type >= 0; rep_type--)
2429 __esw_offloads_unload_rep(esw, rep, rep_type);
2430}
2431
38679b5a
PP		 2432int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num)
2433{
2434 int err;
2435
2436 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2437 return 0;
2438
865d6d1c
RD		 2439 if (vport_num != MLX5_VPORT_UPLINK) {
2440 err = mlx5_esw_offloads_devlink_port_register(esw, vport_num);
2441 if (err)
2442 return err;
2443 }
c7eddc60 2444
38679b5a 2445 err = mlx5_esw_offloads_rep_load(esw, vport_num);
c7eddc60
PP		 2446 if (err)
2447 goto load_err;
2448 return err;
2449
2450load_err:
865d6d1c
RD		 2451 if (vport_num != MLX5_VPORT_UPLINK)
2452 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2453 return err;
2454}
2455
2456void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num)
2457{
2458 if (esw->mode != MLX5_ESWITCH_OFFLOADS)
2459 return;
2460
2461 mlx5_esw_offloads_rep_unload(esw, vport_num);
865d6d1c
RD		 2462
2463 if (vport_num != MLX5_VPORT_UPLINK)
2464 mlx5_esw_offloads_devlink_port_unregister(esw, vport_num);
38679b5a
PP		 2465}
2466
db202995
MB		 2467static int esw_set_slave_root_fdb(struct mlx5_core_dev *master,
2468 struct mlx5_core_dev *slave)
2469{
2470 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
2471 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {};
2472 struct mlx5_flow_root_namespace *root;
2473 struct mlx5_flow_namespace *ns;
2474 int err;
2475
2476 MLX5_SET(set_flow_table_root_in, in, opcode,
2477 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT);
2478 MLX5_SET(set_flow_table_root_in, in, table_type,
2479 FS_FT_FDB);
2480
2481 if (master) {
2482 ns = mlx5_get_flow_namespace(master,
2483 MLX5_FLOW_NAMESPACE_FDB);
2484 root = find_root(&ns->node);
2485 mutex_lock(&root->chain_lock);
2486 MLX5_SET(set_flow_table_root_in, in,
2487 table_eswitch_owner_vhca_id_valid, 1);
2488 MLX5_SET(set_flow_table_root_in, in,
2489 table_eswitch_owner_vhca_id,
2490 MLX5_CAP_GEN(master, vhca_id));
2491 MLX5_SET(set_flow_table_root_in, in, table_id,
2492 root->root_ft->id);
2493 } else {
2494 ns = mlx5_get_flow_namespace(slave,
2495 MLX5_FLOW_NAMESPACE_FDB);
2496 root = find_root(&ns->node);
2497 mutex_lock(&root->chain_lock);
2498 MLX5_SET(set_flow_table_root_in, in, table_id,
2499 root->root_ft->id);
2500 }
2501
2502 err = mlx5_cmd_exec(slave, in, sizeof(in), out, sizeof(out));
2503 mutex_unlock(&root->chain_lock);
2504
2505 return err;
2506}
2507
2508static int __esw_set_master_egress_rule(struct mlx5_core_dev *master,
2509 struct mlx5_core_dev *slave,
2510 struct mlx5_vport *vport,
2511 struct mlx5_flow_table *acl)
2512{
2513 struct mlx5_flow_handle *flow_rule = NULL;
2514 struct mlx5_flow_destination dest = {};
2515 struct mlx5_flow_act flow_act = {};
2516 struct mlx5_flow_spec *spec;
2517 int err = 0;
2518 void *misc;
2519
2520 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2521 if (!spec)
2522 return -ENOMEM;
2523
2524 spec->match_criteria_enable = MLX5_MATCH_MISC_PARAMETERS;
2525 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2526 misc_parameters);
2527 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK);
2528 MLX5_SET(fte_match_set_misc, misc, source_eswitch_owner_vhca_id,
2529 MLX5_CAP_GEN(slave, vhca_id));
2530
2531 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, misc_parameters);
2532 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
2533 MLX5_SET_TO_ONES(fte_match_set_misc, misc,
2534 source_eswitch_owner_vhca_id);
2535
2536 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2537 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
2538 dest.vport.num = slave->priv.eswitch->manager_vport;
2539 dest.vport.vhca_id = MLX5_CAP_GEN(slave, vhca_id);
2540 dest.vport.flags |= MLX5_FLOW_DEST_VPORT_VHCA_ID;
2541
2542 flow_rule = mlx5_add_flow_rules(acl, spec, &flow_act,
2543 &dest, 1);
2544 if (IS_ERR(flow_rule))
2545 err = PTR_ERR(flow_rule);
2546 else
2547 vport->egress.offloads.bounce_rule = flow_rule;
2548
2549 kvfree(spec);
2550 return err;
2551}
2552
2553static int esw_set_master_egress_rule(struct mlx5_core_dev *master,
2554 struct mlx5_core_dev *slave)
2555{
2556 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
2557 struct mlx5_eswitch *esw = master->priv.eswitch;
2558 struct mlx5_flow_table_attr ft_attr = {
2559 .max_fte = 1, .prio = 0, .level = 0,
43a0696f 2560 .flags = MLX5_FLOW_TABLE_OTHER_VPORT,
db202995
MB		 2561 };
2562 struct mlx5_flow_namespace *egress_ns;
2563 struct mlx5_flow_table *acl;
2564 struct mlx5_flow_group *g;
2565 struct mlx5_vport *vport;
2566 void *match_criteria;
2567 u32 *flow_group_in;
2568 int err;
2569
2570 vport = mlx5_eswitch_get_vport(esw, esw->manager_vport);
2571 if (IS_ERR(vport))
2572 return PTR_ERR(vport);
2573
2574 egress_ns = mlx5_get_flow_vport_acl_namespace(master,
2575 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
2576 vport->index);
2577 if (!egress_ns)
2578 return -EINVAL;
2579
2580 if (vport->egress.acl)
2581 return -EINVAL;
2582
2583 flow_group_in = kvzalloc(inlen, GFP_KERNEL);
2584 if (!flow_group_in)
2585 return -ENOMEM;
2586
2587 acl = mlx5_create_vport_flow_table(egress_ns, &ft_attr, vport->vport);
2588 if (IS_ERR(acl)) {
2589 err = PTR_ERR(acl);
2590 goto out;
2591 }
2592
2593 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in,
2594 match_criteria);
2595 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2596 misc_parameters.source_port);
2597 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
2598 misc_parameters.source_eswitch_owner_vhca_id);
2599 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
2600 MLX5_MATCH_MISC_PARAMETERS);
2601
2602 MLX5_SET(create_flow_group_in, flow_group_in,
2603 source_eswitch_owner_vhca_id_valid, 1);
2604 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
2605 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
2606
2607 g = mlx5_create_flow_group(acl, flow_group_in);
2608 if (IS_ERR(g)) {
2609 err = PTR_ERR(g);
2610 goto err_group;
2611 }
2612
2613 err = __esw_set_master_egress_rule(master, slave, vport, acl);
2614 if (err)
2615 goto err_rule;
2616
2617 vport->egress.acl = acl;
2618 vport->egress.offloads.bounce_grp = g;
2619
2620 kvfree(flow_group_in);
2621
2622 return 0;
2623
2624err_rule:
2625 mlx5_destroy_flow_group(g);
2626err_group:
2627 mlx5_destroy_flow_table(acl);
2628out:
2629 kvfree(flow_group_in);
2630 return err;
2631}
2632
2633static void esw_unset_master_egress_rule(struct mlx5_core_dev *dev)
2634{
2635 struct mlx5_vport *vport;
2636
2637 vport = mlx5_eswitch_get_vport(dev->priv.eswitch,
2638 dev->priv.eswitch->manager_vport);
2639
2640 esw_acl_egress_ofld_cleanup(vport);
2641}
2642
2643int mlx5_eswitch_offloads_config_single_fdb(struct mlx5_eswitch *master_esw,
2644 struct mlx5_eswitch *slave_esw)
2645{
2646 int err;
2647
db202995
MB		 2648 err = esw_set_slave_root_fdb(master_esw->dev,
2649 slave_esw->dev);
2650 if (err)
82e86a6c 2651 return err;
db202995
MB		 2652
2653 err = esw_set_master_egress_rule(master_esw->dev,
2654 slave_esw->dev);
2655 if (err)
2656 goto err_acl;
2657
2658 return err;
2659
2660err_acl:
2661 esw_set_slave_root_fdb(NULL, slave_esw->dev);
2662
db202995
MB		 2663 return err;
2664}
2665
2666void mlx5_eswitch_offloads_destroy_single_fdb(struct mlx5_eswitch *master_esw,
2667 struct mlx5_eswitch *slave_esw)
2668{
2669 esw_unset_master_egress_rule(master_esw->dev);
2670 esw_set_slave_root_fdb(NULL, slave_esw->dev);
db202995
MB		 2671}
2672
ac004b83
RD		 2673#define ESW_OFFLOADS_DEVCOM_PAIR (0)
2674#define ESW_OFFLOADS_DEVCOM_UNPAIR (1)
2675
ed7a8fe7
MB		 2676static void mlx5_esw_offloads_rep_event_unpair(struct mlx5_eswitch *esw,
2677 struct mlx5_eswitch *peer_esw)
ac004b83 2678{
c8e6a9e6
MB		 2679 const struct mlx5_eswitch_rep_ops *ops;
2680 struct mlx5_eswitch_rep *rep;
2681 unsigned long i;
2682 u8 rep_type;
2683
2684 mlx5_esw_for_each_rep(esw, i, rep) {
2685 rep_type = NUM_REP_TYPES;
2686 while (rep_type--) {
2687 ops = esw->offloads.rep_ops[rep_type];
2688 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2689 ops->event)
ed7a8fe7 2690 ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_UNPAIR, peer_esw);
c8e6a9e6
MB		 2691 }
2692 }
ac004b83
RD		 2693}
2694
ed7a8fe7
MB		 2695static void mlx5_esw_offloads_unpair(struct mlx5_eswitch *esw,
2696 struct mlx5_eswitch *peer_esw)
ac004b83 2697{
d956873f 2698#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
04de7dda 2699 mlx5e_tc_clean_fdb_peer_flows(esw);
d956873f 2700#endif
ed7a8fe7 2701 mlx5_esw_offloads_rep_event_unpair(esw, peer_esw);
ac004b83
RD		 2702 esw_del_fdb_peer_miss_rules(esw);
2703}
2704
c8e6a9e6
MB		 2705static int mlx5_esw_offloads_pair(struct mlx5_eswitch *esw,
2706 struct mlx5_eswitch *peer_esw)
2707{
2708 const struct mlx5_eswitch_rep_ops *ops;
2709 struct mlx5_eswitch_rep *rep;
2710 unsigned long i;
2711 u8 rep_type;
2712 int err;
2713
2714 err = esw_add_fdb_peer_miss_rules(esw, peer_esw->dev);
2715 if (err)
2716 return err;
2717
2718 mlx5_esw_for_each_rep(esw, i, rep) {
2719 for (rep_type = 0; rep_type < NUM_REP_TYPES; rep_type++) {
2720 ops = esw->offloads.rep_ops[rep_type];
2721 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
2722 ops->event) {
2723 err = ops->event(esw, rep, MLX5_SWITCHDEV_EVENT_PAIR, peer_esw);
2724 if (err)
2725 goto err_out;
2726 }
2727 }
2728 }
2729
2730 return 0;
2731
2732err_out:
ed7a8fe7 2733 mlx5_esw_offloads_unpair(esw, peer_esw);
c8e6a9e6
MB		 2734 return err;
2735}
2736
8463daf1
MG		 2737static int mlx5_esw_offloads_set_ns_peer(struct mlx5_eswitch *esw,
2738 struct mlx5_eswitch *peer_esw,
2739 bool pair)
2740{
2741 struct mlx5_flow_root_namespace *peer_ns;
2742 struct mlx5_flow_root_namespace *ns;
2743 int err;
2744
2745 peer_ns = peer_esw->dev->priv.steering->fdb_root_ns;
2746 ns = esw->dev->priv.steering->fdb_root_ns;
2747
2748 if (pair) {
2749 err = mlx5_flow_namespace_set_peer(ns, peer_ns);
2750 if (err)
2751 return err;
2752
e53e6655 2753 err = mlx5_flow_namespace_set_peer(peer_ns, ns);
8463daf1
MG		 2754 if (err) {
2755 mlx5_flow_namespace_set_peer(ns, NULL);
2756 return err;
2757 }
2758 } else {
2759 mlx5_flow_namespace_set_peer(ns, NULL);
2760 mlx5_flow_namespace_set_peer(peer_ns, NULL);
2761 }
2762
2763 return 0;
2764}
2765
ac004b83
RD		 2766static int mlx5_esw_offloads_devcom_event(int event,
2767 void *my_data,
2768 void *event_data)
2769{
2770 struct mlx5_eswitch *esw = my_data;
ac004b83 2771 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
8463daf1 2772 struct mlx5_eswitch *peer_esw = event_data;
ac004b83
RD		 2773 int err;
2774
2775 switch (event) {
2776 case ESW_OFFLOADS_DEVCOM_PAIR:
a5641cb5
JL		 2777 if (mlx5_eswitch_vport_match_metadata_enabled(esw) !=
2778 mlx5_eswitch_vport_match_metadata_enabled(peer_esw))
2779 break;
2780
8c253dfc
SD		 2781 if (esw->paired[mlx5_get_dev_index(peer_esw->dev)])
2782 break;
2783
8463daf1 2784 err = mlx5_esw_offloads_set_ns_peer(esw, peer_esw, true);
ac004b83
RD		 2785 if (err)
2786 goto err_out;
8463daf1
MG		 2787 err = mlx5_esw_offloads_pair(esw, peer_esw);
2788 if (err)
2789 goto err_peer;
ac004b83
RD		 2790
2791 err = mlx5_esw_offloads_pair(peer_esw, esw);
2792 if (err)
2793 goto err_pair;
2794
8c253dfc
SD		 2795 esw->paired[mlx5_get_dev_index(peer_esw->dev)] = true;
2796 peer_esw->paired[mlx5_get_dev_index(esw->dev)] = true;
ac004b83
RD		 2797 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, true);
2798 break;
2799
2800 case ESW_OFFLOADS_DEVCOM_UNPAIR:
8c253dfc 2801 if (!esw->paired[mlx5_get_dev_index(peer_esw->dev)])
ac004b83
RD		 2802 break;
2803
2804 mlx5_devcom_set_paired(devcom, MLX5_DEVCOM_ESW_OFFLOADS, false);
8c253dfc
SD		 2805 esw->paired[mlx5_get_dev_index(peer_esw->dev)] = false;
2806 peer_esw->paired[mlx5_get_dev_index(esw->dev)] = false;
ed7a8fe7
MB		 2807 mlx5_esw_offloads_unpair(peer_esw, esw);
2808 mlx5_esw_offloads_unpair(esw, peer_esw);
8463daf1 2809 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2810 break;
2811 }
2812
2813 return 0;
2814
2815err_pair:
ed7a8fe7 2816 mlx5_esw_offloads_unpair(esw, peer_esw);
8463daf1
MG		 2817err_peer:
2818 mlx5_esw_offloads_set_ns_peer(esw, peer_esw, false);
ac004b83
RD		 2819err_out:
2820 mlx5_core_err(esw->dev, "esw offloads devcom event failure, event %u err %d",
2821 event, err);
2822 return err;
2823}
2824
2be5bd42 2825void mlx5_esw_offloads_devcom_init(struct mlx5_eswitch *esw)
ac004b83
RD		 2826{
2827 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2828
04de7dda
RD		 2829 INIT_LIST_HEAD(&esw->offloads.peer_flows);
2830 mutex_init(&esw->offloads.peer_mutex);
2831
ac004b83
RD		 2832 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2833 return;
2834
3008e6a0
MB		 2835 if (!mlx5_is_lag_supported(esw->dev))
2836 return;
2837
ac004b83
RD		 2838 mlx5_devcom_register_component(devcom,
2839 MLX5_DEVCOM_ESW_OFFLOADS,
2840 mlx5_esw_offloads_devcom_event,
2841 esw);
2842
2843 mlx5_devcom_send_event(devcom,
2844 MLX5_DEVCOM_ESW_OFFLOADS,
2845 ESW_OFFLOADS_DEVCOM_PAIR, esw);
2846}
2847
2be5bd42 2848void mlx5_esw_offloads_devcom_cleanup(struct mlx5_eswitch *esw)
ac004b83
RD		 2849{
2850 struct mlx5_devcom *devcom = esw->dev->priv.devcom;
2851
2852 if (!MLX5_CAP_ESW(esw->dev, merged_eswitch))
2853 return;
2854
3008e6a0
MB		 2855 if (!mlx5_is_lag_supported(esw->dev))
2856 return;
2857
ac004b83
RD		 2858 mlx5_devcom_send_event(devcom, MLX5_DEVCOM_ESW_OFFLOADS,
2859 ESW_OFFLOADS_DEVCOM_UNPAIR, esw);
2860
2861 mlx5_devcom_unregister_component(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2862}
2863
7bf481d7 2864bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw)
92ab1eb3
JL		 2865{
2866 if (!MLX5_CAP_ESW(esw->dev, esw_uplink_ingress_acl))
2867 return false;
2868
2869 if (!(MLX5_CAP_ESW_FLOWTABLE(esw->dev, fdb_to_vport_reg_c_id) &
2870 MLX5_FDB_TO_VPORT_REG_C_0))
2871 return false;
2872
92ab1eb3
JL		 2873 return true;
2874}
2875
0b0ea3c5
SR		 2876#define MLX5_ESW_METADATA_RSVD_UPLINK 1
2877
2878/* Share the same metadata for uplink's. This is fine because:
2879 * (a) In shared FDB mode (LAG) both uplink's are treated the
2880 * same and tagged with the same metadata.
2881 * (b) In non shared FDB mode, packets from physical port0
2882 * cannot hit eswitch of PF1 and vice versa.
2883 */
2884static u32 mlx5_esw_match_metadata_reserved(struct mlx5_eswitch *esw)
2885{
2886 return MLX5_ESW_METADATA_RSVD_UPLINK;
2887}
2888
133dcfc5
VP		 2889u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw)
2890{
7cd7becd 2891 u32 vport_end_ida = (1 << ESW_VPORT_BITS) - 1;
4f4edcc2
AL		 2892 /* Reserve 0xf for internal port offload */
2893 u32 max_pf_num = (1 << ESW_PFNUM_BITS) - 2;
7cd7becd 2894 u32 pf_num;
133dcfc5
VP		 2895 int id;
2896
7cd7becd 2897 /* Only 4 bits of pf_num */
2ec16ddd 2898 pf_num = mlx5_get_dev_index(esw->dev);
7cd7becd 2899 if (pf_num > max_pf_num)
2900 return 0;
133dcfc5 2901
7cd7becd 2902 /* Metadata is 4 bits of PFNUM and 12 bits of unique id */
0b0ea3c5
SR		 2903 /* Use only non-zero vport_id (2-4095) for all PF's */
2904 id = ida_alloc_range(&esw->offloads.vport_metadata_ida,
2905 MLX5_ESW_METADATA_RSVD_UPLINK + 1,
2906 vport_end_ida, GFP_KERNEL);
7cd7becd 2907 if (id < 0)
2908 return 0;
2909 id = (pf_num << ESW_VPORT_BITS) | id;
2910 return id;
133dcfc5
VP		 2911}
2912
2913void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata)
2914{
7cd7becd 2915 u32 vport_bit_mask = (1 << ESW_VPORT_BITS) - 1;
2916
2917 /* Metadata contains only 12 bits of actual ida id */
2918 ida_free(&esw->offloads.vport_metadata_ida, metadata & vport_bit_mask);
133dcfc5
VP		 2919}
2920
2921static int esw_offloads_vport_metadata_setup(struct mlx5_eswitch *esw,
2922 struct mlx5_vport *vport)
2923{
0b0ea3c5
SR		 2924 if (vport->vport == MLX5_VPORT_UPLINK)
2925 vport->default_metadata = mlx5_esw_match_metadata_reserved(esw);
2926 else
2927 vport->default_metadata = mlx5_esw_match_metadata_alloc(esw);
2928
133dcfc5
VP		 2929 vport->metadata = vport->default_metadata;
2930 return vport->metadata ? 0 : -ENOSPC;
2931}
2932
2933static void esw_offloads_vport_metadata_cleanup(struct mlx5_eswitch *esw,
2934 struct mlx5_vport *vport)
2935{
406493a5 2936 if (!vport->default_metadata)
133dcfc5
VP		 2937 return;
2938
0b0ea3c5
SR		 2939 if (vport->vport == MLX5_VPORT_UPLINK)
2940 return;
2941
133dcfc5
VP		 2942 WARN_ON(vport->metadata != vport->default_metadata);
2943 mlx5_esw_match_metadata_free(esw, vport->default_metadata);
2944}
2945
fc99c3d6
VP		 2946static void esw_offloads_metadata_uninit(struct mlx5_eswitch *esw)
2947{
2948 struct mlx5_vport *vport;
47dd7e60 2949 unsigned long i;
fc99c3d6
VP		 2950
2951 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2952 return;
2953
47dd7e60 2954 mlx5_esw_for_each_vport(esw, i, vport)
fc99c3d6
VP		 2955 esw_offloads_vport_metadata_cleanup(esw, vport);
2956}
2957
2958static int esw_offloads_metadata_init(struct mlx5_eswitch *esw)
2959{
2960 struct mlx5_vport *vport;
47dd7e60 2961 unsigned long i;
fc99c3d6 2962 int err;
fc99c3d6
VP		 2963
2964 if (!mlx5_eswitch_vport_match_metadata_enabled(esw))
2965 return 0;
2966
47dd7e60 2967 mlx5_esw_for_each_vport(esw, i, vport) {
fc99c3d6
VP		 2968 err = esw_offloads_vport_metadata_setup(esw, vport);
2969 if (err)
2970 goto metadata_err;
2971 }
2972
2973 return 0;
2974
2975metadata_err:
2976 esw_offloads_metadata_uninit(esw);
2977 return err;
2978}
2979
748da30b 2980int
89a0f1fb
PP		 2981esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw,
2982 struct mlx5_vport *vport)
7445cfb1 2983{
7445cfb1
JL		 2984 int err;
2985
07bab950 2986 err = esw_acl_ingress_ofld_setup(esw, vport);
89a0f1fb 2987 if (err)
fc99c3d6 2988 return err;
7445cfb1 2989
2c40db2f
PP		 2990 err = esw_acl_egress_ofld_setup(esw, vport);
2991 if (err)
2992 goto egress_err;
07bab950
VP		 2993
2994 return 0;
2995
2996egress_err:
2997 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb
PP		 2998 return err;
2999}
18486737 3000
748da30b 3001void
89a0f1fb
PP		 3002esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw,
3003 struct mlx5_vport *vport)
3004{
ea651a86 3005 esw_acl_egress_ofld_cleanup(vport);
07bab950 3006 esw_acl_ingress_ofld_cleanup(esw, vport);
89a0f1fb 3007}
7445cfb1 3008
748da30b 3009static int esw_create_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
7445cfb1
JL		 3010{
3011 struct mlx5_vport *vport;
18486737 3012
748da30b 3013 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 3014 if (IS_ERR(vport))
3015 return PTR_ERR(vport);
3016
4e9a9ef7 3017 return esw_vport_create_offloads_acl_tables(esw, vport);
18486737
EB		 3018}
3019
748da30b 3020static void esw_destroy_uplink_offloads_acl_tables(struct mlx5_eswitch *esw)
18486737 3021{
786ef904 3022 struct mlx5_vport *vport;
7445cfb1 3023
748da30b 3024 vport = mlx5_eswitch_get_vport(esw, MLX5_VPORT_UPLINK);
7bef147a
SM		 3025 if (IS_ERR(vport))
3026 return;
3027
748da30b 3028 esw_vport_destroy_offloads_acl_tables(esw, vport);
18486737
EB		 3029}
3030
db202995
MB		 3031int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw)
3032{
3033 struct mlx5_eswitch_rep *rep;
3034 unsigned long i;
3035 int ret;
3036
3037 if (!esw || esw->mode != MLX5_ESWITCH_OFFLOADS)
3038 return 0;
3039
3040 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
3041 if (atomic_read(&rep->rep_data[REP_ETH].state) != REP_LOADED)
3042 return 0;
3043
3044 ret = mlx5_esw_offloads_rep_load(esw, MLX5_VPORT_UPLINK);
3045 if (ret)
3046 return ret;
3047
3048 mlx5_esw_for_each_rep(esw, i, rep) {
3049 if (atomic_read(&rep->rep_data[REP_ETH].state) == REP_LOADED)
3050 mlx5_esw_offloads_rep_load(esw, rep->vport);
3051 }
3052
3053 return 0;
3054}
3055
062f4bf4 3056static int esw_offloads_steering_init(struct mlx5_eswitch *esw)
6ed1803a 3057{
34ca6535 3058 struct mlx5_esw_indir_table *indir;
6ed1803a
MB		 3059 int err;
3060
5c1d260e 3061 memset(&esw->fdb_table.offloads, 0, sizeof(struct offloads_fdb));
f8d1edda
PP		 3062 mutex_init(&esw->fdb_table.offloads.vports.lock);
3063 hash_init(esw->fdb_table.offloads.vports.table);
7dc84de9 3064 atomic64_set(&esw->user_count, 0);
e52c2802 3065
34ca6535
VB		 3066 indir = mlx5_esw_indir_table_init();
3067 if (IS_ERR(indir)) {
3068 err = PTR_ERR(indir);
3069 goto create_indir_err;
3070 }
3071 esw->fdb_table.offloads.indir = indir;
3072
748da30b 3073 err = esw_create_uplink_offloads_acl_tables(esw);
7445cfb1 3074 if (err)
f8d1edda 3075 goto create_acl_err;
18486737 3076
8d6bd3c3 3077 err = esw_create_offloads_table(esw);
c930a3ad 3078 if (err)
11b717d6 3079 goto create_offloads_err;
c930a3ad 3080
11b717d6 3081 err = esw_create_restore_table(esw);
c930a3ad 3082 if (err)
11b717d6
PB		 3083 goto create_restore_err;
3084
0da3c12d 3085 err = esw_create_offloads_fdb_tables(esw);
11b717d6
PB		 3086 if (err)
3087 goto create_fdb_err;
c930a3ad 3088
8d6bd3c3 3089 err = esw_create_vport_rx_group(esw);
c930a3ad
OG		 3090 if (err)
3091 goto create_fg_err;
3092
8ea7bcf6
JL		 3093 err = esw_create_vport_rx_drop_group(esw);
3094 if (err)
3095 goto create_rx_drop_fg_err;
3096
3097 err = esw_create_vport_rx_drop_rule(esw);
3098 if (err)
3099 goto create_rx_drop_rule_err;
3100
c930a3ad
OG		 3101 return 0;
3102
8ea7bcf6
JL		 3103create_rx_drop_rule_err:
3104 esw_destroy_vport_rx_drop_group(esw);
3105create_rx_drop_fg_err:
3106 esw_destroy_vport_rx_group(esw);
c930a3ad 3107create_fg_err:
1967ce6e 3108 esw_destroy_offloads_fdb_tables(esw);
7445cfb1 3109create_fdb_err:
11b717d6
PB		 3110 esw_destroy_restore_table(esw);
3111create_restore_err:
3112 esw_destroy_offloads_table(esw);
3113create_offloads_err:
748da30b 3114 esw_destroy_uplink_offloads_acl_tables(esw);
f8d1edda 3115create_acl_err:
34ca6535
VB		 3116 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
3117create_indir_err:
f8d1edda 3118 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
c930a3ad
OG		 3119 return err;
3120}
3121
eca8cc38
BW		 3122static void esw_offloads_steering_cleanup(struct mlx5_eswitch *esw)
3123{
8ea7bcf6
JL		 3124 esw_destroy_vport_rx_drop_rule(esw);
3125 esw_destroy_vport_rx_drop_group(esw);
eca8cc38 3126 esw_destroy_vport_rx_group(esw);
eca8cc38 3127 esw_destroy_offloads_fdb_tables(esw);
11b717d6
PB		 3128 esw_destroy_restore_table(esw);
3129 esw_destroy_offloads_table(esw);
748da30b 3130 esw_destroy_uplink_offloads_acl_tables(esw);
34ca6535 3131 mlx5_esw_indir_table_destroy(esw->fdb_table.offloads.indir);
f8d1edda 3132 mutex_destroy(&esw->fdb_table.offloads.vports.lock);
eca8cc38
BW		 3133}
3134
7e736f9a
PP		 3135static void
3136esw_vfs_changed_event_handler(struct mlx5_eswitch *esw, const u32 *out)
a3888f33 3137{
f1bc646c 3138 struct devlink *devlink;
5ccf2770 3139 bool host_pf_disabled;
7e736f9a 3140 u16 new_num_vfs;
a3888f33 3141
7e736f9a
PP		 3142 new_num_vfs = MLX5_GET(query_esw_functions_out, out,
3143 host_params_context.host_num_of_vfs);
5ccf2770
BW		 3144 host_pf_disabled = MLX5_GET(query_esw_functions_out, out,
3145 host_params_context.host_pf_disabled);
a3888f33 3146
7e736f9a
PP		 3147 if (new_num_vfs == esw->esw_funcs.num_vfs || host_pf_disabled)
3148 return;
a3888f33 3149
f1bc646c
MS		 3150 devlink = priv_to_devlink(esw->dev);
3151 devl_lock(devlink);
a3888f33 3152 /* Number of VFs can only change from "0 to x" or "x to 0". */
cd56f929 3153 if (esw->esw_funcs.num_vfs > 0) {
23bb50cf 3154 mlx5_eswitch_unload_vf_vports(esw, esw->esw_funcs.num_vfs);
a3888f33 3155 } else {
7e736f9a 3156 int err;
a3888f33 3157
23bb50cf
BW		 3158 err = mlx5_eswitch_load_vf_vports(esw, new_num_vfs,
3159 MLX5_VPORT_UC_ADDR_CHANGE);
b868c8fe
DC		 3160 if (err) {
3161 devl_unlock(devlink);
7e736f9a 3162 return;
b868c8fe 3163 }
a3888f33 3164 }
7e736f9a 3165 esw->esw_funcs.num_vfs = new_num_vfs;
f1bc646c 3166 devl_unlock(devlink);
a3888f33
BW		 3167}
3168
7e736f9a 3169static void esw_functions_changed_event_handler(struct work_struct *work)
ac35dcd6 3170{
7e736f9a
PP		 3171 struct mlx5_host_work *host_work;
3172 struct mlx5_eswitch *esw;
dd28087c 3173 const u32 *out;
ac35dcd6 3174
7e736f9a
PP		 3175 host_work = container_of(work, struct mlx5_host_work, work);
3176 esw = host_work->esw;
a3888f33 3177
dd28087c
PP		 3178 out = mlx5_esw_query_functions(esw->dev);
3179 if (IS_ERR(out))
7e736f9a 3180 goto out;
a3888f33 3181
7e736f9a 3182 esw_vfs_changed_event_handler(esw, out);
dd28087c 3183 kvfree(out);
a3888f33 3184out:
ac35dcd6
VP		 3185 kfree(host_work);
3186}
3187
16fff98a 3188int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data)
a3888f33 3189{
cd56f929 3190 struct mlx5_esw_functions *esw_funcs;
a3888f33 3191 struct mlx5_host_work *host_work;
a3888f33
BW		 3192 struct mlx5_eswitch *esw;
3193
3194 host_work = kzalloc(sizeof(*host_work), GFP_ATOMIC);
3195 if (!host_work)
3196 return NOTIFY_DONE;
3197
cd56f929
VP		 3198 esw_funcs = mlx5_nb_cof(nb, struct mlx5_esw_functions, nb);
3199 esw = container_of(esw_funcs, struct mlx5_eswitch, esw_funcs);
a3888f33
BW		 3200
3201 host_work->esw = esw;
3202
062f4bf4 3203 INIT_WORK(&host_work->work, esw_functions_changed_event_handler);
a3888f33
BW		 3204 queue_work(esw->work_queue, &host_work->work);
3205
3206 return NOTIFY_OK;
3207}
3208
a53cf949
PP		 3209static int mlx5_esw_host_number_init(struct mlx5_eswitch *esw)
3210{
3211 const u32 *query_host_out;
3212
3213 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3214 return 0;
3215
3216 query_host_out = mlx5_esw_query_functions(esw->dev);
3217 if (IS_ERR(query_host_out))
3218 return PTR_ERR(query_host_out);
3219
3220 /* Mark non local controller with non zero controller number. */
3221 esw->offloads.host_number = MLX5_GET(query_esw_functions_out, query_host_out,
3222 host_params_context.host_number);
3223 kvfree(query_host_out);
3224 return 0;
3225}
3226
f1b9acd3
PP		 3227bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller)
3228{
3229 /* Local controller is always valid */
3230 if (controller == 0)
3231 return true;
3232
3233 if (!mlx5_core_is_ecpf_esw_manager(esw->dev))
3234 return false;
3235
3236 /* External host number starts with zero in device */
3237 return (controller == esw->offloads.host_number + 1);
3238}
3239
5896b972 3240int esw_offloads_enable(struct mlx5_eswitch *esw)
eca8cc38 3241{
c9355682 3242 struct mapping_ctx *reg_c0_obj_pool;
3b83b6c2 3243 struct mlx5_vport *vport;
47dd7e60 3244 unsigned long i;
2198b932 3245 u64 mapping_id;
47dd7e60 3246 int err;
eca8cc38 3247
2bb72e7e 3248 mutex_init(&esw->offloads.termtbl_mutex);
8463daf1 3249 mlx5_rdma_enable_roce(esw->dev);
eca8cc38 3250
a53cf949
PP		 3251 err = mlx5_esw_host_number_init(esw);
3252 if (err)
cd1ef966 3253 goto err_metadata;
a53cf949 3254
fc99c3d6
VP		 3255 err = esw_offloads_metadata_init(esw);
3256 if (err)
3257 goto err_metadata;
3258
332bd3a5
PP		 3259 err = esw_set_passing_vport_metadata(esw, true);
3260 if (err)
3261 goto err_vport_metadata;
c1286050 3262
2198b932
RD		 3263 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
3264
3265 reg_c0_obj_pool = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
3266 sizeof(struct mlx5_mapped_obj),
3267 ESW_REG_C0_USER_DATA_METADATA_MASK,
3268 true);
3269
c9355682
CM		 3270 if (IS_ERR(reg_c0_obj_pool)) {
3271 err = PTR_ERR(reg_c0_obj_pool);
3272 goto err_pool;
3273 }
3274 esw->offloads.reg_c0_obj_pool = reg_c0_obj_pool;
3275
7983a675
PB		 3276 err = esw_offloads_steering_init(esw);
3277 if (err)
3278 goto err_steering_init;
3279
3b83b6c2
DL		 3280 /* Representor will control the vport link state */
3281 mlx5_esw_for_each_vf_vport(esw, i, vport, esw->esw_funcs.num_vfs)
3282 vport->info.link_state = MLX5_VPORT_ADMIN_STATE_DOWN;
3283
c2d7712c
BW		 3284 /* Uplink vport rep must load first. */
3285 err = esw_offloads_load_rep(esw, MLX5_VPORT_UPLINK);
925a6acc 3286 if (err)
c2d7712c 3287 goto err_uplink;
c1286050 3288
c2d7712c 3289 err = mlx5_eswitch_enable_pf_vf_vports(esw, MLX5_VPORT_UC_ADDR_CHANGE);
eca8cc38 3290 if (err)
c2d7712c 3291 goto err_vports;
eca8cc38 3292
eca8cc38
BW		 3293 return 0;
3294
925a6acc 3295err_vports:
c2d7712c
BW		 3296 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
3297err_uplink:
7983a675 3298 esw_offloads_steering_cleanup(esw);
79949985 3299err_steering_init:
c9355682
CM		 3300 mapping_destroy(reg_c0_obj_pool);
3301err_pool:
79949985 3302 esw_set_passing_vport_metadata(esw, false);
7983a675 3303err_vport_metadata:
fc99c3d6
VP		 3304 esw_offloads_metadata_uninit(esw);
3305err_metadata:
8463daf1 3306 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 3307 mutex_destroy(&esw->offloads.termtbl_mutex);
eca8cc38
BW		 3308 return err;
3309}
3310
db7ff19e
EB		 3311static int esw_offloads_stop(struct mlx5_eswitch *esw,
3312 struct netlink_ext_ack *extack)
c930a3ad 3313{
e12de39c 3314 int err;
c930a3ad 3315
b6f2846a 3316 esw->mode = MLX5_ESWITCH_LEGACY;
2318b8bb
CM		 3317
3318 /* If changing from switchdev to legacy mode without sriov enabled,
3319 * no need to create legacy fdb.
3320 */
bea416c7 3321 if (!mlx5_core_is_pf(esw->dev) || !mlx5_sriov_is_enabled(esw->dev))
2318b8bb
CM		 3322 return 0;
3323
b6f2846a 3324 err = mlx5_eswitch_enable_locked(esw, MLX5_ESWITCH_IGNORE_NUM_VFS);
e12de39c 3325 if (err)
8c98ee77 3326 NL_SET_ERR_MSG_MOD(extack, "Failed setting eswitch to legacy");
c930a3ad
OG		 3327
3328 return err;
3329}
3330
5896b972 3331void esw_offloads_disable(struct mlx5_eswitch *esw)
c930a3ad 3332{
5896b972 3333 mlx5_eswitch_disable_pf_vf_vports(esw);
c2d7712c 3334 esw_offloads_unload_rep(esw, MLX5_VPORT_UPLINK);
332bd3a5 3335 esw_set_passing_vport_metadata(esw, false);
eca8cc38 3336 esw_offloads_steering_cleanup(esw);
c9355682 3337 mapping_destroy(esw->offloads.reg_c0_obj_pool);
fc99c3d6 3338 esw_offloads_metadata_uninit(esw);
8463daf1 3339 mlx5_rdma_disable_roce(esw->dev);
2bb72e7e 3340 mutex_destroy(&esw->offloads.termtbl_mutex);
c930a3ad
OG		 3341}
3342
ef78618b 3343static int esw_mode_from_devlink(u16 mode, u16 *mlx5_mode)
c930a3ad
OG		 3344{
3345 switch (mode) {
3346 case DEVLINK_ESWITCH_MODE_LEGACY:
f6455de0 3347 *mlx5_mode = MLX5_ESWITCH_LEGACY;
c930a3ad
OG		 3348 break;
3349 case DEVLINK_ESWITCH_MODE_SWITCHDEV:
f6455de0 3350 *mlx5_mode = MLX5_ESWITCH_OFFLOADS;
c930a3ad
OG		 3351 break;
3352 default:
3353 return -EINVAL;
3354 }
3355
3356 return 0;
3357}
3358
ef78618b
OG		 3359static int esw_mode_to_devlink(u16 mlx5_mode, u16 *mode)
3360{
3361 switch (mlx5_mode) {
f6455de0 3362 case MLX5_ESWITCH_LEGACY:
ef78618b
OG		 3363 *mode = DEVLINK_ESWITCH_MODE_LEGACY;
3364 break;
f6455de0 3365 case MLX5_ESWITCH_OFFLOADS:
ef78618b
OG		 3366 *mode = DEVLINK_ESWITCH_MODE_SWITCHDEV;
3367 break;
3368 default:
3369 return -EINVAL;
3370 }
3371
3372 return 0;
3373}
3374
bffaa916
RD		 3375static int esw_inline_mode_from_devlink(u8 mode, u8 *mlx5_mode)
3376{
3377 switch (mode) {
3378 case DEVLINK_ESWITCH_INLINE_MODE_NONE:
3379 *mlx5_mode = MLX5_INLINE_MODE_NONE;
3380 break;
3381 case DEVLINK_ESWITCH_INLINE_MODE_LINK:
3382 *mlx5_mode = MLX5_INLINE_MODE_L2;
3383 break;
3384 case DEVLINK_ESWITCH_INLINE_MODE_NETWORK:
3385 *mlx5_mode = MLX5_INLINE_MODE_IP;
3386 break;
3387 case DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT:
3388 *mlx5_mode = MLX5_INLINE_MODE_TCP_UDP;
3389 break;
3390 default:
3391 return -EINVAL;
3392 }
3393
3394 return 0;
3395}
3396
3397static int esw_inline_mode_to_devlink(u8 mlx5_mode, u8 *mode)
3398{
3399 switch (mlx5_mode) {
3400 case MLX5_INLINE_MODE_NONE:
3401 *mode = DEVLINK_ESWITCH_INLINE_MODE_NONE;
3402 break;
3403 case MLX5_INLINE_MODE_L2:
3404 *mode = DEVLINK_ESWITCH_INLINE_MODE_LINK;
3405 break;
3406 case MLX5_INLINE_MODE_IP:
3407 *mode = DEVLINK_ESWITCH_INLINE_MODE_NETWORK;
3408 break;
3409 case MLX5_INLINE_MODE_TCP_UDP:
3410 *mode = DEVLINK_ESWITCH_INLINE_MODE_TRANSPORT;
3411 break;
3412 default:
3413 return -EINVAL;
3414 }
3415
3416 return 0;
3417}
3418
662404b2
GL		 3419static bool esw_offloads_devlink_ns_eq_netdev_ns(struct devlink *devlink)
3420{
3421 struct net *devl_net, *netdev_net;
3422 struct mlx5_eswitch *esw;
3423
3424 esw = mlx5_devlink_eswitch_get(devlink);
3425 netdev_net = dev_net(esw->dev->mlx5e_res.uplink_netdev);
3426 devl_net = devlink_net(devlink);
3427
3428 return net_eq(devl_net, netdev_net);
3429}
3430
db7ff19e
EB		 3431int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
3432 struct netlink_ext_ack *extack)
9d1cef19 3433{
9d1cef19 3434 u16 cur_mlx5_mode, mlx5_mode = 0;
bd939753 3435 struct mlx5_eswitch *esw;
ea2128fd 3436 int err = 0;
9d1cef19 3437
bd939753
PP		 3438 esw = mlx5_devlink_eswitch_get(devlink);
3439 if (IS_ERR(esw))
3440 return PTR_ERR(esw);
9d1cef19 3441
ef78618b 3442 if (esw_mode_from_devlink(mode, &mlx5_mode))
c930a3ad
OG		 3443 return -EINVAL;
3444
662404b2
GL		 3445 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV &&
3446 !esw_offloads_devlink_ns_eq_netdev_ns(devlink)) {
3447 NL_SET_ERR_MSG_MOD(extack,
3448 "Can't change E-Switch mode to switchdev when netdev net namespace has diverged from the devlink's.");
3449 return -EPERM;
3450 }
3451
cac1eb2c 3452 mlx5_lag_disable_change(esw->dev);
7dc84de9
RD		 3453 err = mlx5_esw_try_lock(esw);
3454 if (err < 0) {
3455 NL_SET_ERR_MSG_MOD(extack, "Can't change mode, E-Switch is busy");
cac1eb2c 3456 goto enable_lag;
7dc84de9
RD		 3457 }
3458 cur_mlx5_mode = err;
3459 err = 0;
3460
c930a3ad 3461 if (cur_mlx5_mode == mlx5_mode)
8e0aa4bc 3462 goto unlock;
c930a3ad 3463
f019679e 3464 mlx5_eswitch_disable_locked(esw);
c85a6b8f
AL		 3465 if (mode == DEVLINK_ESWITCH_MODE_SWITCHDEV) {
3466 if (mlx5_devlink_trap_get_num_active(esw->dev)) {
3467 NL_SET_ERR_MSG_MOD(extack,
3468 "Can't change mode while devlink traps are active");
3469 err = -EOPNOTSUPP;
3470 goto unlock;
3471 }
8e0aa4bc 3472 err = esw_offloads_start(esw, extack);
c85a6b8f 3473 } else if (mode == DEVLINK_ESWITCH_MODE_LEGACY) {
8e0aa4bc 3474 err = esw_offloads_stop(esw, extack);
f019679e 3475 mlx5_rescan_drivers(esw->dev);
c85a6b8f 3476 } else {
8e0aa4bc 3477 err = -EINVAL;
c85a6b8f 3478 }
8e0aa4bc
PP		 3479
3480unlock:
7dc84de9 3481 mlx5_esw_unlock(esw);
cac1eb2c
MB		 3482enable_lag:
3483 mlx5_lag_enable_change(esw->dev);
8e0aa4bc 3484 return err;
feae9087
OG		 3485}
3486
3487int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode)
3488{
bd939753 3489 struct mlx5_eswitch *esw;
9d1cef19 3490 int err;
c930a3ad 3491
bd939753
PP		 3492 esw = mlx5_devlink_eswitch_get(devlink);
3493 if (IS_ERR(esw))
3494 return PTR_ERR(esw);
c930a3ad 3495
efb4879f 3496 down_read(&esw->mode_lock);
8e0aa4bc 3497 err = esw_mode_to_devlink(esw->mode, mode);
efb4879f 3498 up_read(&esw->mode_lock);
8e0aa4bc 3499 return err;
feae9087 3500}
127ea380 3501
47dd7e60
PP		 3502static int mlx5_esw_vports_inline_set(struct mlx5_eswitch *esw, u8 mlx5_mode,
3503 struct netlink_ext_ack *extack)
3504{
3505 struct mlx5_core_dev *dev = esw->dev;
3506 struct mlx5_vport *vport;
3507 u16 err_vport_num = 0;
3508 unsigned long i;
3509 int err = 0;
3510
3511 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3512 err = mlx5_modify_nic_vport_min_inline(dev, vport->vport, mlx5_mode);
3513 if (err) {
3514 err_vport_num = vport->vport;
3515 NL_SET_ERR_MSG_MOD(extack,
3516 "Failed to set min inline on vport");
3517 goto revert_inline_mode;
3518 }
3519 }
3520 return 0;
3521
3522revert_inline_mode:
3523 mlx5_esw_for_each_host_func_vport(esw, i, vport, esw->esw_funcs.num_vfs) {
3524 if (vport->vport == err_vport_num)
3525 break;
3526 mlx5_modify_nic_vport_min_inline(dev,
3527 vport->vport,
3528 esw->offloads.inline_mode);
3529 }
3530 return err;
3531}
3532
db7ff19e
EB		 3533int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
3534 struct netlink_ext_ack *extack)
bffaa916
RD		 3535{
3536 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3537 struct mlx5_eswitch *esw;
bffaa916 3538 u8 mlx5_mode;
47dd7e60 3539 int err;
bffaa916 3540
bd939753
PP		 3541 esw = mlx5_devlink_eswitch_get(devlink);
3542 if (IS_ERR(esw))
3543 return PTR_ERR(esw);
bffaa916 3544
367dfa12 3545 down_write(&esw->mode_lock);
ae24432c 3546
c415f704
OG		 3547 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) {
3548 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
bcd68c04
JC		 3549 if (mode == DEVLINK_ESWITCH_INLINE_MODE_NONE) {
3550 err = 0;
8e0aa4bc 3551 goto out;
bcd68c04
JC		 3552 }
3553
c8b838d1 3554 fallthrough;
c415f704 3555 case MLX5_CAP_INLINE_MODE_L2:
8c98ee77 3556 NL_SET_ERR_MSG_MOD(extack, "Inline mode can't be set");
8e0aa4bc
PP		 3557 err = -EOPNOTSUPP;
3558 goto out;
c415f704
OG		 3559 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3560 break;
3561 }
bffaa916 3562
525e84be 3563 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3564 NL_SET_ERR_MSG_MOD(extack,
3565 "Can't set inline mode when flows are configured");
8e0aa4bc
PP		 3566 err = -EOPNOTSUPP;
3567 goto out;
375f51e2
RD		 3568 }
3569
bffaa916
RD		 3570 err = esw_inline_mode_from_devlink(mode, &mlx5_mode);
3571 if (err)
3572 goto out;
3573
47dd7e60
PP		 3574 err = mlx5_esw_vports_inline_set(esw, mlx5_mode, extack);
3575 if (err)
3576 goto out;
bffaa916
RD		 3577
3578 esw->offloads.inline_mode = mlx5_mode;
367dfa12 3579 up_write(&esw->mode_lock);
bffaa916
RD		 3580 return 0;
3581
bffaa916 3582out:
367dfa12 3583 up_write(&esw->mode_lock);
bffaa916
RD		 3584 return err;
3585}
3586
3587int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode)
3588{
bd939753 3589 struct mlx5_eswitch *esw;
9d1cef19 3590 int err;
bffaa916 3591
bd939753
PP		 3592 esw = mlx5_devlink_eswitch_get(devlink);
3593 if (IS_ERR(esw))
3594 return PTR_ERR(esw);
bffaa916 3595
efb4879f 3596 down_read(&esw->mode_lock);
8e0aa4bc 3597 err = esw_inline_mode_to_devlink(esw->offloads.inline_mode, mode);
efb4879f 3598 up_read(&esw->mode_lock);
8e0aa4bc 3599 return err;
bffaa916
RD		 3600}
3601
acc10929
LR		 3602bool mlx5_eswitch_block_encap(struct mlx5_core_dev *dev)
3603{
3604 struct devlink *devlink = priv_to_devlink(dev);
3605 struct mlx5_eswitch *esw;
3606
3607 devl_lock(devlink);
3608 esw = mlx5_devlink_eswitch_get(devlink);
3609 if (IS_ERR(esw)) {
3610 devl_unlock(devlink);
3611 /* Failure means no eswitch => not possible to change encap */
3612 return true;
3613 }
3614
3615 down_write(&esw->mode_lock);
3616 if (esw->mode != MLX5_ESWITCH_LEGACY &&
3617 esw->offloads.encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE) {
3618 up_write(&esw->mode_lock);
3619 devl_unlock(devlink);
3620 return false;
3621 }
3622
3623 esw->offloads.num_block_encap++;
3624 up_write(&esw->mode_lock);
3625 devl_unlock(devlink);
3626 return true;
3627}
3628
3629void mlx5_eswitch_unblock_encap(struct mlx5_core_dev *dev)
3630{
3631 struct devlink *devlink = priv_to_devlink(dev);
3632 struct mlx5_eswitch *esw;
3633
3634 esw = mlx5_devlink_eswitch_get(devlink);
3635 if (IS_ERR(esw))
3636 return;
3637
3638 down_write(&esw->mode_lock);
3639 esw->offloads.num_block_encap--;
3640 up_write(&esw->mode_lock);
3641}
3642
98fdbea5
LR		 3643int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink,
3644 enum devlink_eswitch_encap_mode encap,
db7ff19e 3645 struct netlink_ext_ack *extack)
7768d197
RD		 3646{
3647 struct mlx5_core_dev *dev = devlink_priv(devlink);
bd939753 3648 struct mlx5_eswitch *esw;
f019679e 3649 int err = 0;
7768d197 3650
bd939753
PP		 3651 esw = mlx5_devlink_eswitch_get(devlink);
3652 if (IS_ERR(esw))
3653 return PTR_ERR(esw);
7768d197 3654
367dfa12 3655 down_write(&esw->mode_lock);
ae24432c 3656
7768d197 3657 if (encap != DEVLINK_ESWITCH_ENCAP_MODE_NONE &&
60786f09 3658 (!MLX5_CAP_ESW_FLOWTABLE_FDB(dev, reformat) ||
8e0aa4bc
PP		 3659 !MLX5_CAP_ESW_FLOWTABLE_FDB(dev, decap))) {
3660 err = -EOPNOTSUPP;
3661 goto unlock;
3662 }
7768d197 3663
8e0aa4bc
PP		 3664 if (encap && encap != DEVLINK_ESWITCH_ENCAP_MODE_BASIC) {
3665 err = -EOPNOTSUPP;
3666 goto unlock;
3667 }
7768d197 3668
f6455de0 3669 if (esw->mode == MLX5_ESWITCH_LEGACY) {
7768d197 3670 esw->offloads.encap = encap;
8e0aa4bc 3671 goto unlock;
7768d197
RD		 3672 }
3673
3674 if (esw->offloads.encap == encap)
8e0aa4bc 3675 goto unlock;
7768d197 3676
525e84be 3677 if (atomic64_read(&esw->offloads.num_flows) > 0) {
8c98ee77
EB		 3678 NL_SET_ERR_MSG_MOD(extack,
3679 "Can't set encapsulation when flows are configured");
8e0aa4bc
PP		 3680 err = -EOPNOTSUPP;
3681 goto unlock;
7768d197
RD		 3682 }
3683
acc10929
LR		 3684 if (esw->offloads.num_block_encap) {
3685 NL_SET_ERR_MSG_MOD(extack,
3686 "Can't set encapsulation when IPsec SA and/or policies are configured");
3687 err = -EOPNOTSUPP;
3688 goto unlock;
3689 }
3690
e52c2802 3691 esw_destroy_offloads_fdb_tables(esw);
7768d197
RD		 3692
3693 esw->offloads.encap = encap;
e52c2802 3694
0da3c12d 3695 err = esw_create_offloads_fdb_tables(esw);
e52c2802 3696
7768d197 3697 if (err) {
8c98ee77
EB		 3698 NL_SET_ERR_MSG_MOD(extack,
3699 "Failed re-creating fast FDB table");
7768d197 3700 esw->offloads.encap = !encap;
0da3c12d 3701 (void)esw_create_offloads_fdb_tables(esw);
7768d197 3702 }
e52c2802 3703
8e0aa4bc 3704unlock:
367dfa12 3705 up_write(&esw->mode_lock);
7768d197
RD		 3706 return err;
3707}
3708
98fdbea5
LR		 3709int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink,
3710 enum devlink_eswitch_encap_mode *encap)
7768d197 3711{
bd939753 3712 struct mlx5_eswitch *esw;
7768d197 3713
bd939753
PP		 3714 esw = mlx5_devlink_eswitch_get(devlink);
3715 if (IS_ERR(esw))
3716 return PTR_ERR(esw);
3717
efb4879f 3718 down_read(&esw->mode_lock);
7768d197 3719 *encap = esw->offloads.encap;
efb4879f 3720 up_read(&esw->mode_lock);
f019679e 3721 return 0;
7768d197
RD		 3722}
3723
c2d7712c
BW		 3724static bool
3725mlx5_eswitch_vport_has_rep(const struct mlx5_eswitch *esw, u16 vport_num)
3726{
3727 /* Currently, only ECPF based device has representor for host PF. */
3728 if (vport_num == MLX5_VPORT_PF &&
3729 !mlx5_core_is_ecpf_esw_manager(esw->dev))
3730 return false;
3731
3732 if (vport_num == MLX5_VPORT_ECPF &&
3733 !mlx5_ecpf_vport_exists(esw->dev))
3734 return false;
3735
3736 return true;
3737}
3738
f8e8fa02 3739void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
8693115a 3740 const struct mlx5_eswitch_rep_ops *ops,
f8e8fa02 3741 u8 rep_type)
127ea380 3742{
8693115a 3743 struct mlx5_eswitch_rep_data *rep_data;
f8e8fa02 3744 struct mlx5_eswitch_rep *rep;
47dd7e60 3745 unsigned long i;
9deb2241 3746
8693115a 3747 esw->offloads.rep_ops[rep_type] = ops;
47dd7e60
PP		 3748 mlx5_esw_for_each_rep(esw, i, rep) {
3749 if (likely(mlx5_eswitch_vport_has_rep(esw, rep->vport))) {
59c904c8 3750 rep->esw = esw;
c2d7712c
BW		 3751 rep_data = &rep->rep_data[rep_type];
3752 atomic_set(&rep_data->state, REP_REGISTERED);
3753 }
f8e8fa02 3754 }
127ea380 3755}
f8e8fa02 3756EXPORT_SYMBOL(mlx5_eswitch_register_vport_reps);
127ea380 3757
f8e8fa02 3758void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type)
127ea380 3759{
cb67b832 3760 struct mlx5_eswitch_rep *rep;
47dd7e60 3761 unsigned long i;
cb67b832 3762
f6455de0 3763 if (esw->mode == MLX5_ESWITCH_OFFLOADS)
062f4bf4 3764 __unload_reps_all_vport(esw, rep_type);
127ea380 3765
47dd7e60 3766 mlx5_esw_for_each_rep(esw, i, rep)
8693115a 3767 atomic_set(&rep->rep_data[rep_type].state, REP_UNREGISTERED);
127ea380 3768}
f8e8fa02 3769EXPORT_SYMBOL(mlx5_eswitch_unregister_vport_reps);
726293f1 3770
a4b97ab4 3771void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type)
726293f1 3772{
726293f1
HHZ		 3773 struct mlx5_eswitch_rep *rep;
3774
879c8f84 3775 rep = mlx5_eswitch_get_rep(esw, MLX5_VPORT_UPLINK);
8693115a 3776 return rep->rep_data[rep_type].priv;
726293f1 3777}
22215908
MB		 3778
3779void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
02f3afd9 3780 u16 vport,
22215908
MB		 3781 u8 rep_type)
3782{
22215908
MB		 3783 struct mlx5_eswitch_rep *rep;
3784
879c8f84 3785 rep = mlx5_eswitch_get_rep(esw, vport);
22215908 3786
8693115a
PP		 3787 if (atomic_read(&rep->rep_data[rep_type].state) == REP_LOADED &&
3788 esw->offloads.rep_ops[rep_type]->get_proto_dev)
3789 return esw->offloads.rep_ops[rep_type]->get_proto_dev(rep);
22215908
MB		 3790 return NULL;
3791}
57cbd893 3792EXPORT_SYMBOL(mlx5_eswitch_get_proto_dev);
22215908
MB		 3793
3794void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type)
3795{
879c8f84 3796 return mlx5_eswitch_get_proto_dev(esw, MLX5_VPORT_UPLINK, rep_type);
22215908 3797}
57cbd893
MB		 3798EXPORT_SYMBOL(mlx5_eswitch_uplink_get_proto_dev);
3799
3800struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
02f3afd9 3801 u16 vport)
57cbd893 3802{
879c8f84 3803 return mlx5_eswitch_get_rep(esw, vport);
57cbd893
MB		 3804}
3805EXPORT_SYMBOL(mlx5_eswitch_vport_rep);
91d6291c 3806
5b7cb745
PB		 3807bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
3808{
3809 return !!(esw->flags & MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED);
3810}
3811EXPORT_SYMBOL(mlx5_eswitch_reg_c1_loopback_enabled);
3812
7445cfb1
JL		 3813bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
3814{
3815 return !!(esw->flags & MLX5_ESWITCH_VPORT_MATCH_METADATA);
3816}
3817EXPORT_SYMBOL(mlx5_eswitch_vport_match_metadata_enabled);
3818
0f0d3827 3819u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
7445cfb1
JL		 3820 u16 vport_num)
3821{
133dcfc5 3822 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
0f0d3827 3823
133dcfc5
VP		 3824 if (WARN_ON_ONCE(IS_ERR(vport)))
3825 return 0;
0f0d3827 3826
133dcfc5 3827 return vport->metadata << (32 - ESW_SOURCE_PORT_METADATA_BITS);
7445cfb1
JL		 3828}
3829EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_match);
d970812b
PP		 3830
3831int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port,
f1b9acd3 3832 u16 vport_num, u32 controller, u32 sfnum)
d970812b
PP		 3833{
3834 int err;
3835
3836 err = mlx5_esw_vport_enable(esw, vport_num, MLX5_VPORT_UC_ADDR_CHANGE);
3837 if (err)
3838 return err;
3839
f1b9acd3 3840 err = mlx5_esw_devlink_sf_port_register(esw, dl_port, vport_num, controller, sfnum);
d970812b
PP		 3841 if (err)
3842 goto devlink_err;
3843
3844 err = mlx5_esw_offloads_rep_load(esw, vport_num);
3845 if (err)
3846 goto rep_err;
3847 return 0;
3848
3849rep_err:
3850 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3851devlink_err:
3852 mlx5_esw_vport_disable(esw, vport_num);
3853 return err;
3854}
3855
3856void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num)
3857{
3858 mlx5_esw_offloads_rep_unload(esw, vport_num);
3859 mlx5_esw_devlink_sf_port_unregister(esw, vport_num);
3860 mlx5_esw_vport_disable(esw, vport_num);
3861}
84ae9c1f
VB		 3862
3863static int mlx5_esw_query_vport_vhca_id(struct mlx5_eswitch *esw, u16 vport_num, u16 *vhca_id)
3864{
3865 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
3866 void *query_ctx;
3867 void *hca_caps;
3868 int err;
3869
3870 *vhca_id = 0;
3871 if (mlx5_esw_is_manager_vport(esw, vport_num) ||
3872 !MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
3873 return -EPERM;
3874
3875 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
3876 if (!query_ctx)
3877 return -ENOMEM;
3878
47d0c500 3879 err = mlx5_vport_get_other_func_general_cap(esw->dev, vport_num, query_ctx);
84ae9c1f
VB		 3880 if (err)
3881 goto out_free;
3882
3883 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
3884 *vhca_id = MLX5_GET(cmd_hca_cap, hca_caps, vhca_id);
3885
3886out_free:
3887 kfree(query_ctx);
3888 return err;
3889}
3890
3891int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num)
3892{
3893 u16 *old_entry, *vhca_map_entry, vhca_id;
3894 int err;
3895
3896 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3897 if (err) {
3898 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%u,err=%d)\n",
3899 vport_num, err);
3900 return err;
3901 }
3902
3903 vhca_map_entry = kmalloc(sizeof(*vhca_map_entry), GFP_KERNEL);
3904 if (!vhca_map_entry)
3905 return -ENOMEM;
3906
3907 *vhca_map_entry = vport_num;
3908 old_entry = xa_store(&esw->offloads.vhca_map, vhca_id, vhca_map_entry, GFP_KERNEL);
3909 if (xa_is_err(old_entry)) {
3910 kfree(vhca_map_entry);
3911 return xa_err(old_entry);
3912 }
3913 kfree(old_entry);
3914 return 0;
3915}
3916
3917void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num)
3918{
3919 u16 *vhca_map_entry, vhca_id;
3920 int err;
3921
3922 err = mlx5_esw_query_vport_vhca_id(esw, vport_num, &vhca_id);
3923 if (err)
3924 esw_warn(esw->dev, "Getting vhca_id for vport failed (vport=%hu,err=%d)\n",
3925 vport_num, err);
3926
3927 vhca_map_entry = xa_erase(&esw->offloads.vhca_map, vhca_id);
3928 kfree(vhca_map_entry);
3929}
3930
3931int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num)
3932{
3933 u16 *res = xa_load(&esw->offloads.vhca_map, vhca_id);
3934
3935 if (!res)
3936 return -ENOENT;
3937
3938 *vport_num = *res;
3939 return 0;
3940}
10742efc
VB		 3941
3942u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
3943 u16 vport_num)
3944{
3945 struct mlx5_vport *vport = mlx5_eswitch_get_vport(esw, vport_num);
3946
3947 if (WARN_ON_ONCE(IS_ERR(vport)))
3948 return 0;
3949
3950 return vport->metadata;
3951}
3952EXPORT_SYMBOL(mlx5_eswitch_get_vport_metadata_for_set);
e9d491a6
PP		 3953
3954static bool
3955is_port_function_supported(struct mlx5_eswitch *esw, u16 vport_num)
3956{
3957 return vport_num == MLX5_VPORT_PF ||
3958 mlx5_eswitch_is_vf_vport(esw, vport_num) ||
3959 mlx5_esw_is_sf_vport(esw, vport_num);
3960}
3961
71c93e37
JP		 3962int mlx5_devlink_port_fn_hw_addr_get(struct devlink_port *port,
3963 u8 *hw_addr, int *hw_addr_len,
3964 struct netlink_ext_ack *extack)
e9d491a6
PP		 3965{
3966 struct mlx5_eswitch *esw;
3967 struct mlx5_vport *vport;
3968 u16 vport_num;
3969
3970 esw = mlx5_devlink_eswitch_get(port->devlink);
3971 if (IS_ERR(esw))
3972 return PTR_ERR(esw);
3973
3974 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
3975 if (!is_port_function_supported(esw, vport_num))
3976 return -EOPNOTSUPP;
3977
3978 vport = mlx5_eswitch_get_vport(esw, vport_num);
3979 if (IS_ERR(vport)) {
3980 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
3981 return PTR_ERR(vport);
3982 }
3983
3984 mutex_lock(&esw->state_lock);
3985 ether_addr_copy(hw_addr, vport->info.mac);
3986 *hw_addr_len = ETH_ALEN;
3987 mutex_unlock(&esw->state_lock);
3988 return 0;
3989}
3990
71c93e37
JP		 3991int mlx5_devlink_port_fn_hw_addr_set(struct devlink_port *port,
3992 const u8 *hw_addr, int hw_addr_len,
3993 struct netlink_ext_ack *extack)
e9d491a6
PP		 3994{
3995 struct mlx5_eswitch *esw;
3996 u16 vport_num;
3997
3998 esw = mlx5_devlink_eswitch_get(port->devlink);
3999 if (IS_ERR(esw)) {
4000 NL_SET_ERR_MSG_MOD(extack, "Eswitch doesn't support set hw_addr");
4001 return PTR_ERR(esw);
4002 }
4003
4004 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4005 if (!is_port_function_supported(esw, vport_num)) {
4006 NL_SET_ERR_MSG_MOD(extack, "Port doesn't support set hw_addr");
4007 return -EINVAL;
4008 }
4009
4010 return mlx5_eswitch_set_vport_mac(esw, vport_num, hw_addr);
4011}
7db98396
YH		 4012
4013static struct mlx5_vport *
4014mlx5_devlink_port_fn_get_vport(struct devlink_port *port, struct mlx5_eswitch *esw)
4015{
4016 u16 vport_num;
4017
4018 if (!MLX5_CAP_GEN(esw->dev, vhca_resource_manager))
4019 return ERR_PTR(-EOPNOTSUPP);
4020
4021 vport_num = mlx5_esw_devlink_port_index_to_vport_num(port->index);
4022 if (!is_port_function_supported(esw, vport_num))
4023 return ERR_PTR(-EOPNOTSUPP);
4024
4025 return mlx5_eswitch_get_vport(esw, vport_num);
4026}
4027
e5b9642a
SD		 4028int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled,
4029 struct netlink_ext_ack *extack)
4030{
4031 struct mlx5_eswitch *esw;
4032 struct mlx5_vport *vport;
4033 int err = -EOPNOTSUPP;
4034
4035 esw = mlx5_devlink_eswitch_get(port->devlink);
4036 if (IS_ERR(esw))
4037 return PTR_ERR(esw);
4038
4039 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4040 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4041 return err;
4042 }
4043
4044 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4045 if (IS_ERR(vport)) {
4046 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4047 return PTR_ERR(vport);
4048 }
4049
4050 mutex_lock(&esw->state_lock);
4051 if (vport->enabled) {
4052 *is_enabled = vport->info.mig_enabled;
4053 err = 0;
4054 }
4055 mutex_unlock(&esw->state_lock);
4056 return err;
4057}
4058
4059int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable,
4060 struct netlink_ext_ack *extack)
4061{
4062 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4063 struct mlx5_eswitch *esw;
4064 struct mlx5_vport *vport;
4065 void *query_ctx;
4066 void *hca_caps;
4067 int err = -EOPNOTSUPP;
4068
4069 esw = mlx5_devlink_eswitch_get(port->devlink);
4070 if (IS_ERR(esw))
4071 return PTR_ERR(esw);
4072
4073 if (!MLX5_CAP_GEN(esw->dev, migration)) {
4074 NL_SET_ERR_MSG_MOD(extack, "Device doesn't support migration");
4075 return err;
4076 }
4077
4078 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4079 if (IS_ERR(vport)) {
4080 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4081 return PTR_ERR(vport);
4082 }
4083
4084 mutex_lock(&esw->state_lock);
4085 if (!vport->enabled) {
4086 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4087 goto out;
4088 }
4089
4090 if (vport->info.mig_enabled == enable) {
4091 err = 0;
4092 goto out;
4093 }
4094
4095 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4096 if (!query_ctx) {
4097 err = -ENOMEM;
4098 goto out;
4099 }
4100
4101 err = mlx5_vport_get_other_func_cap(esw->dev, vport->vport, query_ctx,
4102 MLX5_CAP_GENERAL_2);
4103 if (err) {
4104 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4105 goto out_free;
4106 }
4107
4108 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
e5b9642a
SD		 4109 MLX5_SET(cmd_hca_cap_2, hca_caps, migratable, 1);
4110
4111 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport->vport,
4112 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2);
4113 if (err) {
4114 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA migratable cap");
4115 goto out_free;
4116 }
4117
4118 vport->info.mig_enabled = enable;
4119
4120out_free:
4121 kfree(query_ctx);
4122out:
4123 mutex_unlock(&esw->state_lock);
4124 return err;
4125}
4126
7db98396
YH		 4127int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled,
4128 struct netlink_ext_ack *extack)
4129{
4130 struct mlx5_eswitch *esw;
4131 struct mlx5_vport *vport;
4132 int err = -EOPNOTSUPP;
4133
4134 esw = mlx5_devlink_eswitch_get(port->devlink);
4135 if (IS_ERR(esw))
4136 return PTR_ERR(esw);
4137
4138 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4139 if (IS_ERR(vport)) {
4140 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4141 return PTR_ERR(vport);
4142 }
4143
4144 mutex_lock(&esw->state_lock);
4145 if (vport->enabled) {
4146 *is_enabled = vport->info.roce_enabled;
4147 err = 0;
4148 }
4149 mutex_unlock(&esw->state_lock);
4150 return err;
4151}
4152
4153int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable,
4154 struct netlink_ext_ack *extack)
4155{
4156 int query_out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
4157 struct mlx5_eswitch *esw;
4158 struct mlx5_vport *vport;
4159 int err = -EOPNOTSUPP;
4160 void *query_ctx;
4161 void *hca_caps;
4162 u16 vport_num;
4163
4164 esw = mlx5_devlink_eswitch_get(port->devlink);
4165 if (IS_ERR(esw))
4166 return PTR_ERR(esw);
4167
4168 vport = mlx5_devlink_port_fn_get_vport(port, esw);
4169 if (IS_ERR(vport)) {
4170 NL_SET_ERR_MSG_MOD(extack, "Invalid port");
4171 return PTR_ERR(vport);
4172 }
4173 vport_num = vport->vport;
4174
4175 mutex_lock(&esw->state_lock);
4176 if (!vport->enabled) {
4177 NL_SET_ERR_MSG_MOD(extack, "Eswitch vport is disabled");
4178 goto out;
4179 }
4180
4181 if (vport->info.roce_enabled == enable) {
4182 err = 0;
4183 goto out;
4184 }
4185
4186 query_ctx = kzalloc(query_out_sz, GFP_KERNEL);
4187 if (!query_ctx) {
4188 err = -ENOMEM;
4189 goto out;
4190 }
4191
4192 err = mlx5_vport_get_other_func_cap(esw->dev, vport_num, query_ctx,
4193 MLX5_CAP_GENERAL);
4194 if (err) {
4195 NL_SET_ERR_MSG_MOD(extack, "Failed getting HCA caps");
4196 goto out_free;
4197 }
4198
4199 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, query_ctx, capability);
7db98396
YH		 4200 MLX5_SET(cmd_hca_cap, hca_caps, roce, enable);
4201
4202 err = mlx5_vport_set_other_func_cap(esw->dev, hca_caps, vport_num,
4203 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
4204 if (err) {
4205 NL_SET_ERR_MSG_MOD(extack, "Failed setting HCA roce cap");
4206 goto out_free;
4207 }
4208
4209 vport->info.roce_enabled = enable;
4210
4211out_free:
4212 kfree(query_ctx);
4213out:
4214 mutex_unlock(&esw->state_lock);
4215 return err;
4216}
Linux 6.x block layer and io_uring tree(s)