[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.h

/*
 * Copyright (c) 2015, Mellanox Technologies, Ltd.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_ESWITCH_H__
#define __MLX5_ESWITCH_H__

#include <linux/if_ether.h>
#include <linux/if_link.h>
#include <net/devlink.h>
#include <linux/mlx5/device.h>

#define MLX5_MAX_UC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))

#define MLX5_MAX_MC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))

#define MLX5_L2_ADDR_HASH_SIZE (BIT(BITS_PER_BYTE))
#define MLX5_L2_ADDR_HASH(addr) (addr[5])

#define FDB_UPLINK_VPORT 0xffff

/* L2 -mac address based- hash helpers */
struct l2addr_node {
	struct hlist_node hlist;
	u8                addr[ETH_ALEN];
};

#define for_each_l2hash_node(hn, tmp, hash, i) \
	for (i = 0; i < MLX5_L2_ADDR_HASH_SIZE; i++) \
		hlist_for_each_entry_safe(hn, tmp, &hash[i], hlist)

#define l2addr_hash_find(hash, mac, type) ({                \
	int ix = MLX5_L2_ADDR_HASH(mac);                    \
	bool found = false;                                 \
	type *ptr = NULL;                                   \
							    \
	hlist_for_each_entry(ptr, &hash[ix], node.hlist)    \
		if (ether_addr_equal(ptr->node.addr, mac)) {\
			found = true;                       \
			break;                              \
		}                                           \
	if (!found)                                         \
		ptr = NULL;                                 \
	ptr;                                                \
})

#define l2addr_hash_add(hash, mac, type, gfp) ({            \
	int ix = MLX5_L2_ADDR_HASH(mac);                    \
	type *ptr = NULL;                                   \
							    \
	ptr = kzalloc(sizeof(type), gfp);                   \
	if (ptr) {                                          \
		ether_addr_copy(ptr->node.addr, mac);       \
		hlist_add_head(&ptr->node.hlist, &hash[ix]);\
	}                                                   \
	ptr;                                                \
})

#define l2addr_hash_del(ptr) ({                             \
	hlist_del(&ptr->node.hlist);                        \
	kfree(ptr);                                         \
})

struct vport_ingress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	struct mlx5_flow_group *allow_spoofchk_only_grp;
	struct mlx5_flow_group *allow_untagged_only_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_rule  *allow_rule;
	struct mlx5_flow_rule  *drop_rule;
};

struct vport_egress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allowed_vlans_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_rule  *allowed_vlan;
	struct mlx5_flow_rule  *drop_rule;
};

struct mlx5_vport_info {
	u8                      mac[ETH_ALEN];
	u16                     vlan;
	u8                      qos;
	u64                     node_guid;
	int                     link_state;
	bool                    spoofchk;
	bool                    trusted;
};

struct mlx5_vport {
	struct mlx5_core_dev    *dev;
	int                     vport;
	struct hlist_head       uc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct hlist_head       mc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct mlx5_flow_rule   *promisc_rule;
	struct mlx5_flow_rule   *allmulti_rule;
	struct work_struct      vport_change_handler;

	struct vport_ingress    ingress;
	struct vport_egress     egress;

	struct mlx5_vport_info  info;

	bool                    enabled;
	u16                     enabled_events;
};

struct mlx5_l2_table {
	struct hlist_head l2_hash[MLX5_L2_ADDR_HASH_SIZE];
	u32                  size;
	unsigned long        *bitmap;
};

struct mlx5_eswitch_fdb {
	void *fdb;
	union {
		struct legacy_fdb {
			struct mlx5_flow_group *addr_grp;
			struct mlx5_flow_group *allmulti_grp;
			struct mlx5_flow_group *promisc_grp;
		} legacy;

		struct offloads_fdb {
			struct mlx5_flow_table *fdb;
			struct mlx5_flow_group *send_to_vport_grp;
			struct mlx5_flow_group *miss_grp;
			struct mlx5_flow_rule  *miss_rule;
			int vlan_push_pop_refcount;
		} offloads;
	};
};

enum {
	SRIOV_NONE,
	SRIOV_LEGACY,
	SRIOV_OFFLOADS
};

struct mlx5_esw_sq {
	struct mlx5_flow_rule	*send_to_vport_rule;
	struct list_head	 list;
};

struct mlx5_eswitch_rep {
	int		       (*load)(struct mlx5_eswitch *esw,
				       struct mlx5_eswitch_rep *rep);
	void		       (*unload)(struct mlx5_eswitch *esw,
					 struct mlx5_eswitch_rep *rep);
	u16		       vport;
	u8		       hw_id[ETH_ALEN];
	void		      *priv_data;

	struct mlx5_flow_rule *vport_rx_rule;
	struct list_head       vport_sqs_list;
	u16		       vlan;
	u32		       vlan_refcount;
	bool		       valid;
};

struct mlx5_esw_offload {
	struct mlx5_flow_table *ft_offloads;
	struct mlx5_flow_group *vport_rx_group;
	struct mlx5_eswitch_rep *vport_reps;
};

struct mlx5_eswitch {
	struct mlx5_core_dev    *dev;
	struct mlx5_l2_table    l2_table;
	struct mlx5_eswitch_fdb fdb_table;
	struct hlist_head       mc_table[MLX5_L2_ADDR_HASH_SIZE];
	struct workqueue_struct *work_queue;
	struct mlx5_vport       *vports;
	int                     total_vports;
	int                     enabled_vports;
	/* Synchronize between vport change events
	 * and async SRIOV admin state changes
	 */
	struct mutex            state_lock;
	struct esw_mc_addr      *mc_promisc;
	struct mlx5_esw_offload offloads;
	int                     mode;
};

void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);

/* E-Switch API */
int mlx5_eswitch_init(struct mlx5_core_dev *dev);
void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
void mlx5_eswitch_attach(struct mlx5_eswitch *esw);
void mlx5_eswitch_detach(struct mlx5_eswitch *esw);
void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe);
int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
			       int vport, u8 mac[ETH_ALEN]);
int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
				 int vport, int link_state);
int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				int vport, u16 vlan, u8 qos);
int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
				    int vport, bool spoofchk);
int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
				 int vport_num, bool setting);
int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
				  int vport, struct ifla_vf_info *ivi);
int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
				 int vport,
				 struct ifla_vf_stats *vf_stats);

struct mlx5_flow_spec;
struct mlx5_esw_flow_attr;

struct mlx5_flow_rule *
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_spec *spec,
				struct mlx5_esw_flow_attr *attr);
struct mlx5_flow_rule *
mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn);

enum {
	SET_VLAN_STRIP	= BIT(0),
	SET_VLAN_INSERT	= BIT(1)
};

#define MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  0x40
#define MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH 0x80

struct mlx5_esw_flow_attr {
	struct mlx5_eswitch_rep *in_rep;
	struct mlx5_eswitch_rep *out_rep;

	int	action;
	u16	vlan;
	bool	vlan_handled;
};

int mlx5_eswitch_sqs2vport_start(struct mlx5_eswitch *esw,
				 struct mlx5_eswitch_rep *rep,
				 u16 *sqns_array, int sqns_num);
void mlx5_eswitch_sqs2vport_stop(struct mlx5_eswitch *esw,
				 struct mlx5_eswitch_rep *rep);

int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode);
int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw,
				     int vport_index,
				     struct mlx5_eswitch_rep *rep);
void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw,
				       int vport_index);

int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				  int vport, u16 vlan, u8 qos, u8 set_flags);

#define MLX5_DEBUG_ESWITCH_MASK BIT(3)

#define esw_info(dev, format, ...)				\
	pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)

#define esw_warn(dev, format, ...)				\
	pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)

#define esw_debug(dev, format, ...)				\
	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
#endif /* __MLX5_ESWITCH_H__ */
Commit	Line	Data
073bb189 SM	1	/*
	2	* Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef __MLX5_ESWITCH_H__
	34	#define __MLX5_ESWITCH_H__
	35
77256579 SM	36	#include <linux/if_ether.h>
77256579 SM	37	#include <linux/if_link.h>
feae9087	38	#include <net/devlink.h>
073bb189 SM	39	#include <linux/mlx5/device.h>
	40
	41	#define MLX5_MAX_UC_PER_VPORT(dev) \
	42	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
	43
	44	#define MLX5_MAX_MC_PER_VPORT(dev) \
	45	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
	46
	47	#define MLX5_L2_ADDR_HASH_SIZE (BIT(BITS_PER_BYTE))
	48	#define MLX5_L2_ADDR_HASH(addr) (addr[5])
	49
cb67b832 HHZ	50	#define FDB_UPLINK_VPORT 0xffff
cb67b832 HHZ	51
073bb189 SM	52	/* L2 -mac address based- hash helpers */
	53	struct l2addr_node {
	54	struct hlist_node hlist;
	55	u8 addr[ETH_ALEN];
	56	};
	57
	58	#define for_each_l2hash_node(hn, tmp, hash, i) \
	59	for (i = 0; i < MLX5_L2_ADDR_HASH_SIZE; i++) \
	60	hlist_for_each_entry_safe(hn, tmp, &hash[i], hlist)
	61
	62	#define l2addr_hash_find(hash, mac, type) ({ \
	63	int ix = MLX5_L2_ADDR_HASH(mac); \
	64	bool found = false; \
	65	type *ptr = NULL; \
	66	\
	67	hlist_for_each_entry(ptr, &hash[ix], node.hlist) \
	68	if (ether_addr_equal(ptr->node.addr, mac)) {\
	69	found = true; \
	70	break; \
	71	} \
	72	if (!found) \
	73	ptr = NULL; \
	74	ptr; \
	75	})
	76
	77	#define l2addr_hash_add(hash, mac, type, gfp) ({ \
	78	int ix = MLX5_L2_ADDR_HASH(mac); \
	79	type *ptr = NULL; \
	80	\
	81	ptr = kzalloc(sizeof(type), gfp); \
	82	if (ptr) { \
	83	ether_addr_copy(ptr->node.addr, mac); \
	84	hlist_add_head(&ptr->node.hlist, &hash[ix]);\
	85	} \
	86	ptr; \
	87	})
	88
	89	#define l2addr_hash_del(ptr) ({ \
	90	hlist_del(&ptr->node.hlist); \
	91	kfree(ptr); \
	92	})
	93
5742df0f MHY	94	struct vport_ingress {
	95	struct mlx5_flow_table *acl;
	96	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	97	struct mlx5_flow_group *allow_spoofchk_only_grp;
	98	struct mlx5_flow_group *allow_untagged_only_grp;
	99	struct mlx5_flow_group *drop_grp;
dfcb1ed3 MHY	100	struct mlx5_flow_rule *allow_rule;
dfcb1ed3 MHY	101	struct mlx5_flow_rule *drop_rule;
5742df0f MHY	102	};
	103
	104	struct vport_egress {
	105	struct mlx5_flow_table *acl;
	106	struct mlx5_flow_group *allowed_vlans_grp;
	107	struct mlx5_flow_group *drop_grp;
dfcb1ed3 MHY	108	struct mlx5_flow_rule *allowed_vlan;
dfcb1ed3 MHY	109	struct mlx5_flow_rule *drop_rule;
5742df0f MHY	110	};
5742df0f MHY	111
1ab2068a MHY	112	struct mlx5_vport_info {
	113	u8 mac[ETH_ALEN];
	114	u16 vlan;
	115	u8 qos;
	116	u64 node_guid;
	117	int link_state;
	118	bool spoofchk;
	119	bool trusted;
	120	};
	121
073bb189 SM	122	struct mlx5_vport {
	123	struct mlx5_core_dev *dev;
	124	int vport;
	125	struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
81848731	126	struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
a35f71f2 MHY	127	struct mlx5_flow_rule *promisc_rule;
a35f71f2 MHY	128	struct mlx5_flow_rule *allmulti_rule;
073bb189 SM	129	struct work_struct vport_change_handler;
073bb189 SM	130
5742df0f MHY	131	struct vport_ingress ingress;
	132	struct vport_egress egress;
	133
1ab2068a MHY	134	struct mlx5_vport_info info;
1ab2068a MHY	135
073bb189	136	bool enabled;
81848731	137	u16 enabled_events;
073bb189 SM	138	};
	139
	140	struct mlx5_l2_table {
	141	struct hlist_head l2_hash[MLX5_L2_ADDR_HASH_SIZE];
	142	u32 size;
	143	unsigned long *bitmap;
	144	};
	145
81848731 SM	146	struct mlx5_eswitch_fdb {
81848731 SM	147	void *fdb;
6ab36e35 OG	148	union {
	149	struct legacy_fdb {
	150	struct mlx5_flow_group *addr_grp;
	151	struct mlx5_flow_group *allmulti_grp;
	152	struct mlx5_flow_group *promisc_grp;
	153	} legacy;
69697b6e OG	154
69697b6e OG	155	struct offloads_fdb {
1033665e	156	struct mlx5_flow_table *fdb;
69697b6e OG	157	struct mlx5_flow_group *send_to_vport_grp;
69697b6e OG	158	struct mlx5_flow_group *miss_grp;
3aa33572	159	struct mlx5_flow_rule *miss_rule;
f5f82476	160	int vlan_push_pop_refcount;
69697b6e	161	} offloads;
6ab36e35 OG	162	};
	163	};
	164
	165	enum {
	166	SRIOV_NONE,
	167	SRIOV_LEGACY,
	168	SRIOV_OFFLOADS
81848731 SM	169	};
81848731 SM	170
cb67b832 HHZ	171	struct mlx5_esw_sq {
	172	struct mlx5_flow_rule *send_to_vport_rule;
	173	struct list_head list;
	174	};
127ea380 HHZ	175
127ea380 HHZ	176	struct mlx5_eswitch_rep {
cb67b832 HHZ	177	int (load)(struct mlx5_eswitch esw,
	178	struct mlx5_eswitch_rep *rep);
	179	void (unload)(struct mlx5_eswitch esw,
	180	struct mlx5_eswitch_rep *rep);
127ea380	181	u16 vport;
bac9b6aa	182	u8 hw_id[ETH_ALEN];
127ea380	183	void *priv_data;
bac9b6aa OG	184
bac9b6aa OG	185	struct mlx5_flow_rule *vport_rx_rule;
cb67b832	186	struct list_head vport_sqs_list;
f5f82476 OG	187	u16 vlan;
f5f82476 OG	188	u32 vlan_refcount;
127ea380 HHZ	189	bool valid;
	190	};
	191
c116c6ee OG	192	struct mlx5_esw_offload {
c116c6ee OG	193	struct mlx5_flow_table *ft_offloads;
fed9ce22	194	struct mlx5_flow_group *vport_rx_group;
127ea380	195	struct mlx5_eswitch_rep *vport_reps;
c116c6ee OG	196	};
c116c6ee OG	197
073bb189 SM	198	struct mlx5_eswitch {
	199	struct mlx5_core_dev *dev;
	200	struct mlx5_l2_table l2_table;
81848731 SM	201	struct mlx5_eswitch_fdb fdb_table;
81848731 SM	202	struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
073bb189 SM	203	struct workqueue_struct *work_queue;
	204	struct mlx5_vport *vports;
	205	int total_vports;
81848731	206	int enabled_vports;
dfcb1ed3 MHY	207	/* Synchronize between vport change events
	208	* and async SRIOV admin state changes
	209	*/
	210	struct mutex state_lock;
a35f71f2	211	struct esw_mc_addr *mc_promisc;
c116c6ee	212	struct mlx5_esw_offload offloads;
6ab36e35	213	int mode;
073bb189 SM	214	};
073bb189 SM	215
766a0e97 BX	216	void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
	217	int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
	218
073bb189 SM	219	/* E-Switch API */
	220	int mlx5_eswitch_init(struct mlx5_core_dev *dev);
	221	void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
62a9b90a MHY	222	void mlx5_eswitch_attach(struct mlx5_eswitch *esw);
62a9b90a MHY	223	void mlx5_eswitch_detach(struct mlx5_eswitch *esw);
073bb189	224	void mlx5_eswitch_vport_event(struct mlx5_eswitch esw, struct mlx5_eqe eqe);
6ab36e35	225	int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
81848731	226	void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
77256579 SM	227	int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
	228	int vport, u8 mac[ETH_ALEN]);
	229	int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
	230	int vport, int link_state);
9e7ea352 SM	231	int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
9e7ea352 SM	232	int vport, u16 vlan, u8 qos);
f942380c MHY	233	int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
f942380c MHY	234	int vport, bool spoofchk);
1edc57e2 MHY	235	int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1edc57e2 MHY	236	int vport_num, bool setting);
77256579 SM	237	int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
77256579 SM	238	int vport, struct ifla_vf_info *ivi);
3b751a2a SM	239	int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
	240	int vport,
	241	struct ifla_vf_stats *vf_stats);
073bb189	242
3d80d1a2	243	struct mlx5_flow_spec;
776b12b6	244	struct mlx5_esw_flow_attr;
3d80d1a2 OG	245
	246	struct mlx5_flow_rule *
	247	mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
	248	struct mlx5_flow_spec *spec,
776b12b6	249	struct mlx5_esw_flow_attr *attr);
fed9ce22 OG	250	struct mlx5_flow_rule *
	251	mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn);
	252
e33dfe31 OG	253	enum {
	254	SET_VLAN_STRIP = BIT(0),
	255	SET_VLAN_INSERT = BIT(1)
	256	};
	257
f5f82476 OG	258	#define MLX5_FLOW_CONTEXT_ACTION_VLAN_POP 0x40
	259	#define MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH 0x80
	260
776b12b6 OG	261	struct mlx5_esw_flow_attr {
	262	struct mlx5_eswitch_rep *in_rep;
	263	struct mlx5_eswitch_rep *out_rep;
	264
	265	int action;
f5f82476 OG	266	u16 vlan;
f5f82476 OG	267	bool vlan_handled;
776b12b6 OG	268	};
776b12b6 OG	269
cb67b832 HHZ	270	int mlx5_eswitch_sqs2vport_start(struct mlx5_eswitch *esw,
	271	struct mlx5_eswitch_rep *rep,
	272	u16 *sqns_array, int sqns_num);
	273	void mlx5_eswitch_sqs2vport_stop(struct mlx5_eswitch *esw,
	274	struct mlx5_eswitch_rep *rep);
	275
feae9087 OG	276	int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode);
feae9087 OG	277	int mlx5_devlink_eswitch_mode_get(struct devlink devlink, u16 mode);
127ea380	278	void mlx5_eswitch_register_vport_rep(struct mlx5_eswitch *esw,
9deb2241	279	int vport_index,
127ea380 HHZ	280	struct mlx5_eswitch_rep *rep);
127ea380 HHZ	281	void mlx5_eswitch_unregister_vport_rep(struct mlx5_eswitch *esw,
9deb2241	282	int vport_index);
feae9087	283
f5f82476 OG	284	int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
	285	struct mlx5_esw_flow_attr *attr);
	286	int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
	287	struct mlx5_esw_flow_attr *attr);
	288	int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
	289	int vport, u16 vlan, u8 qos, u8 set_flags);
	290
69697b6e OG	291	#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
	292
	293	#define esw_info(dev, format, ...) \
	294	pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
	295
	296	#define esw_warn(dev, format, ...) \
	297	pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
	298
	299	#define esw_debug(dev, format, ...) \
	300	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
073bb189	301	#endif /* __MLX5_ESWITCH_H__ */