[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.h

/*
 * Copyright (c) 2015, Mellanox Technologies, Ltd.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_ESWITCH_H__
#define __MLX5_ESWITCH_H__

#include <linux/if_ether.h>
#include <linux/if_link.h>
#include <net/devlink.h>
#include <linux/mlx5/device.h>
#include <linux/mlx5/eswitch.h>
#include <linux/mlx5/vport.h>
#include <linux/mlx5/fs.h>
#include "lib/mpfs.h"

#ifdef CONFIG_MLX5_ESWITCH

#define MLX5_MAX_UC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))

#define MLX5_MAX_MC_PER_VPORT(dev) \
	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))

#define MLX5_MIN_BW_SHARE 1

#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
	min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)

#define mlx5_esw_has_fwd_fdb(dev) \
	MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)

#define FDB_MAX_CHAIN 3
#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
#define FDB_MAX_PRIO 16

struct vport_ingress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	struct mlx5_flow_group *allow_spoofchk_only_grp;
	struct mlx5_flow_group *allow_untagged_only_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_handle  *allow_rule;
	struct mlx5_flow_handle  *drop_rule;
	struct mlx5_fc           *drop_counter;
};

struct vport_egress {
	struct mlx5_flow_table *acl;
	struct mlx5_flow_group *allowed_vlans_grp;
	struct mlx5_flow_group *drop_grp;
	struct mlx5_flow_handle  *allowed_vlan;
	struct mlx5_flow_handle  *drop_rule;
	struct mlx5_fc           *drop_counter;
};

struct mlx5_vport_drop_stats {
	u64 rx_dropped;
	u64 tx_dropped;
};

struct mlx5_vport_info {
	u8                      mac[ETH_ALEN];
	u16                     vlan;
	u8                      qos;
	u64                     node_guid;
	int                     link_state;
	u32                     min_rate;
	u32                     max_rate;
	bool                    spoofchk;
	bool                    trusted;
};

struct mlx5_vport {
	struct mlx5_core_dev    *dev;
	int                     vport;
	struct hlist_head       uc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct hlist_head       mc_list[MLX5_L2_ADDR_HASH_SIZE];
	struct mlx5_flow_handle *promisc_rule;
	struct mlx5_flow_handle *allmulti_rule;
	struct work_struct      vport_change_handler;

	struct vport_ingress    ingress;
	struct vport_egress     egress;

	struct mlx5_vport_info  info;

	struct {
		bool            enabled;
		u32             esw_tsar_ix;
		u32             bw_share;
	} qos;

	bool                    enabled;
	u16                     enabled_events;
};

enum offloads_fdb_flags {
	ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
};

extern const unsigned int ESW_POOLS[4];

#define PRIO_LEVELS 2
struct mlx5_eswitch_fdb {
	union {
		struct legacy_fdb {
			struct mlx5_flow_table *fdb;
			struct mlx5_flow_group *addr_grp;
			struct mlx5_flow_group *allmulti_grp;
			struct mlx5_flow_group *promisc_grp;
			struct mlx5_flow_table *vepa_fdb;
			struct mlx5_flow_handle *vepa_uplink_rule;
			struct mlx5_flow_handle *vepa_star_rule;
		} legacy;

		struct offloads_fdb {
			struct mlx5_flow_table *slow_fdb;
			struct mlx5_flow_group *send_to_vport_grp;
			struct mlx5_flow_group *peer_miss_grp;
			struct mlx5_flow_handle **peer_miss_rules;
			struct mlx5_flow_group *miss_grp;
			struct mlx5_flow_handle *miss_rule_uni;
			struct mlx5_flow_handle *miss_rule_multi;
			int vlan_push_pop_refcount;

			struct {
				struct mlx5_flow_table *fdb;
				u32 num_rules;
			} fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
			/* Protects fdb_prio table */
			struct mutex fdb_prio_lock;

			int fdb_left[ARRAY_SIZE(ESW_POOLS)];
		} offloads;
	};
	u32 flags;
};

struct mlx5_esw_offload {
	struct mlx5_flow_table *ft_offloads;
	struct mlx5_flow_group *vport_rx_group;
	struct mlx5_eswitch_rep *vport_reps;
	struct list_head peer_flows;
	struct mutex peer_mutex;
	DECLARE_HASHTABLE(encap_tbl, 8);
	DECLARE_HASHTABLE(mod_hdr_tbl, 8);
	u8 inline_mode;
	u64 num_flows;
	u8 encap;
};

/* E-Switch MC FDB table hash node */
struct esw_mc_addr { /* SRIOV only */
	struct l2addr_node     node;
	struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
	u32                    refcnt;
};

struct mlx5_host_work {
	struct work_struct	work;
	struct mlx5_eswitch	*esw;
};

struct mlx5_host_info {
	struct mlx5_nb		nb;
	u16			num_vfs;
};

struct mlx5_eswitch {
	struct mlx5_core_dev    *dev;
	struct mlx5_nb          nb;
	struct mlx5_eswitch_fdb fdb_table;
	struct hlist_head       mc_table[MLX5_L2_ADDR_HASH_SIZE];
	struct workqueue_struct *work_queue;
	struct mlx5_vport       *vports;
	int                     total_vports;
	int                     enabled_vports;
	/* Synchronize between vport change events
	 * and async SRIOV admin state changes
	 */
	struct mutex            state_lock;
	struct esw_mc_addr	mc_promisc;

	struct {
		bool            enabled;
		u32             root_tsar_id;
	} qos;

	struct mlx5_esw_offload offloads;
	int                     mode;
	int                     nvports;
	u16                     manager_vport;
	struct mlx5_host_info	host_info;
};

void esw_offloads_cleanup(struct mlx5_eswitch *esw);
int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports,
		      int total_nvports);
void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
int esw_offloads_init_reps(struct mlx5_eswitch *esw);

/* E-Switch API */
int mlx5_eswitch_init(struct mlx5_core_dev *dev);
void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
			       int vport, u8 mac[ETH_ALEN]);
int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
				 int vport, int link_state);
int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				int vport, u16 vlan, u8 qos);
int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
				    int vport, bool spoofchk);
int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
				 int vport_num, bool setting);
int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
				u32 max_rate, u32 min_rate);
int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
				  int vport, struct ifla_vf_info *ivi);
int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
				 int vport,
				 struct ifla_vf_stats *vf_stats);
void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);

struct mlx5_flow_spec;
struct mlx5_esw_flow_attr;

struct mlx5_flow_handle *
mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_spec *spec,
				struct mlx5_esw_flow_attr *attr);
struct mlx5_flow_handle *
mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
			  struct mlx5_flow_spec *spec,
			  struct mlx5_esw_flow_attr *attr);
void
mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
				struct mlx5_flow_handle *rule,
				struct mlx5_esw_flow_attr *attr);
void
mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
			  struct mlx5_flow_handle *rule,
			  struct mlx5_esw_flow_attr *attr);

bool
mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);

u16
mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);

u32
mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);

struct mlx5_flow_handle *
mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
				  struct mlx5_flow_destination *dest);

enum {
	SET_VLAN_STRIP	= BIT(0),
	SET_VLAN_INSERT	= BIT(1)
};

enum mlx5_flow_match_level {
	MLX5_MATCH_NONE	= MLX5_INLINE_MODE_NONE,
	MLX5_MATCH_L2	= MLX5_INLINE_MODE_L2,
	MLX5_MATCH_L3	= MLX5_INLINE_MODE_IP,
	MLX5_MATCH_L4	= MLX5_INLINE_MODE_TCP_UDP,
};

/* current maximum for flow based vport multicasting */
#define MLX5_MAX_FLOW_FWD_VPORTS 2

enum {
	MLX5_ESW_DEST_ENCAP         = BIT(0),
	MLX5_ESW_DEST_ENCAP_VALID   = BIT(1),
};

struct mlx5_esw_flow_attr {
	struct mlx5_eswitch_rep *in_rep;
	struct mlx5_core_dev	*in_mdev;
	struct mlx5_core_dev    *counter_dev;

	int split_count;
	int out_count;

	int	action;
	__be16	vlan_proto[MLX5_FS_VLAN_DEPTH];
	u16	vlan_vid[MLX5_FS_VLAN_DEPTH];
	u8	vlan_prio[MLX5_FS_VLAN_DEPTH];
	u8	total_vlan;
	bool	vlan_handled;
	struct {
		u32 flags;
		struct mlx5_eswitch_rep *rep;
		struct mlx5_core_dev *mdev;
		u32 encap_id;
	} dests[MLX5_MAX_FLOW_FWD_VPORTS];
	u32	mod_hdr_id;
	u8	match_level;
	u8	tunnel_match_level;
	struct mlx5_fc *counter;
	u32	chain;
	u16	prio;
	u32	dest_chain;
	struct mlx5e_tc_flow_parse_attr *parse_attr;
};

int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
				  struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
					 struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
					struct netlink_ext_ack *extack);
int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);

int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
				 struct mlx5_esw_flow_attr *attr);
int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
				  int vport, u16 vlan, u8 qos, u8 set_flags);

static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
						       u8 vlan_depth)
{
	bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
		   MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);

	if (vlan_depth == 1)
		return ret;

	return  ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
		MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
}

bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
			 struct mlx5_core_dev *dev1);
bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
			       struct mlx5_core_dev *dev1);

#define MLX5_DEBUG_ESWITCH_MASK BIT(3)

#define esw_info(__dev, format, ...)			\
	dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)

#define esw_warn(__dev, format, ...)			\
	dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)

#define esw_debug(dev, format, ...)				\
	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)

/* The returned number is valid only when the dev is eswitch manager. */
static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
{
	return mlx5_core_is_ecpf_esw_manager(dev) ?
		MLX5_VPORT_ECPF : MLX5_VPORT_PF;
}

static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
{
	/* Uplink always locate at the last element of the array.*/
	return esw->total_vports - 1;
}

static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
{
	return esw->total_vports - 2;
}

static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
						  u16 vport_num)
{
	if (vport_num == MLX5_VPORT_ECPF) {
		if (!mlx5_ecpf_vport_exists(esw->dev))
			esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
		return mlx5_eswitch_ecpf_idx(esw);
	}

	if (vport_num == MLX5_VPORT_UPLINK)
		return mlx5_eswitch_uplink_idx(esw);

	return vport_num;
}

static inline int mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
						  int index)
{
	if (index == mlx5_eswitch_ecpf_idx(esw) &&
	    mlx5_ecpf_vport_exists(esw->dev))
		return MLX5_VPORT_ECPF;

	if (index == mlx5_eswitch_uplink_idx(esw))
		return MLX5_VPORT_UPLINK;

	return index;
}

#else  /* CONFIG_MLX5_ESWITCH */
/* eswitch API stubs */
static inline int  mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
static inline int  mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }

#define FDB_MAX_CHAIN 1
#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
#define FDB_MAX_PRIO 1

#endif /* CONFIG_MLX5_ESWITCH */

#endif /* __MLX5_ESWITCH_H__ */
Commit	Line	Data
073bb189 SM	1	/*
	2	* Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef __MLX5_ESWITCH_H__
	34	#define __MLX5_ESWITCH_H__
	35
77256579 SM	36	#include <linux/if_ether.h>
77256579 SM	37	#include <linux/if_link.h>
feae9087	38	#include <net/devlink.h>
073bb189	39	#include <linux/mlx5/device.h>
57cbd893	40	#include <linux/mlx5/eswitch.h>
a1b3839a	41	#include <linux/mlx5/vport.h>
cc495188	42	#include <linux/mlx5/fs.h>
eeb66cdb	43	#include "lib/mpfs.h"
073bb189	44
e80541ec SM	45	#ifdef CONFIG_MLX5_ESWITCH
e80541ec SM	46
073bb189 SM	47	#define MLX5_MAX_UC_PER_VPORT(dev) \
	48	(1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
	49
	50	#define MLX5_MAX_MC_PER_VPORT(dev) \
	51	(1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
	52
c9497c98 MHY	53	#define MLX5_MIN_BW_SHARE 1
	54
	55	#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
	56	min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
	57
a842dd04 CM	58	#define mlx5_esw_has_fwd_fdb(dev) \
	59	MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
	60
328edb49	61	#define FDB_MAX_CHAIN 3
c92a0b94	62	#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
328edb49 PB	63	#define FDB_MAX_PRIO 16
328edb49 PB	64
5742df0f MHY	65	struct vport_ingress {
	66	struct mlx5_flow_table *acl;
	67	struct mlx5_flow_group *allow_untagged_spoofchk_grp;
	68	struct mlx5_flow_group *allow_spoofchk_only_grp;
	69	struct mlx5_flow_group *allow_untagged_only_grp;
	70	struct mlx5_flow_group *drop_grp;
74491de9 MB	71	struct mlx5_flow_handle *allow_rule;
74491de9 MB	72	struct mlx5_flow_handle *drop_rule;
b8a0dbe3	73	struct mlx5_fc *drop_counter;
5742df0f MHY	74	};
	75
	76	struct vport_egress {
	77	struct mlx5_flow_table *acl;
	78	struct mlx5_flow_group *allowed_vlans_grp;
	79	struct mlx5_flow_group *drop_grp;
74491de9 MB	80	struct mlx5_flow_handle *allowed_vlan;
74491de9 MB	81	struct mlx5_flow_handle *drop_rule;
b8a0dbe3 EE	82	struct mlx5_fc *drop_counter;
	83	};
	84
	85	struct mlx5_vport_drop_stats {
	86	u64 rx_dropped;
	87	u64 tx_dropped;
5742df0f MHY	88	};
5742df0f MHY	89
1ab2068a MHY	90	struct mlx5_vport_info {
	91	u8 mac[ETH_ALEN];
	92	u16 vlan;
	93	u8 qos;
	94	u64 node_guid;
	95	int link_state;
c9497c98	96	u32 min_rate;
1bd27b11	97	u32 max_rate;
1ab2068a MHY	98	bool spoofchk;
	99	bool trusted;
	100	};
	101
073bb189 SM	102	struct mlx5_vport {
	103	struct mlx5_core_dev *dev;
	104	int vport;
	105	struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
81848731	106	struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
74491de9 MB	107	struct mlx5_flow_handle *promisc_rule;
74491de9 MB	108	struct mlx5_flow_handle *allmulti_rule;
073bb189 SM	109	struct work_struct vport_change_handler;
073bb189 SM	110
5742df0f MHY	111	struct vport_ingress ingress;
	112	struct vport_egress egress;
	113
1ab2068a MHY	114	struct mlx5_vport_info info;
1ab2068a MHY	115
1bd27b11 MHY	116	struct {
	117	bool enabled;
	118	u32 esw_tsar_ix;
c9497c98	119	u32 bw_share;
1bd27b11 MHY	120	} qos;
1bd27b11 MHY	121
073bb189	122	bool enabled;
81848731	123	u16 enabled_events;
073bb189 SM	124	};
073bb189 SM	125
e52c2802 PB	126	enum offloads_fdb_flags {
	127	ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
	128	};
	129
	130	extern const unsigned int ESW_POOLS[4];
	131
	132	#define PRIO_LEVELS 2
81848731	133	struct mlx5_eswitch_fdb {
6ab36e35 OG	134	union {
6ab36e35 OG	135	struct legacy_fdb {
52fff327	136	struct mlx5_flow_table *fdb;
6ab36e35 OG	137	struct mlx5_flow_group *addr_grp;
	138	struct mlx5_flow_group *allmulti_grp;
	139	struct mlx5_flow_group *promisc_grp;
8da202b2 HN	140	struct mlx5_flow_table *vepa_fdb;
	141	struct mlx5_flow_handle *vepa_uplink_rule;
	142	struct mlx5_flow_handle *vepa_star_rule;
6ab36e35	143	} legacy;
69697b6e OG	144
69697b6e OG	145	struct offloads_fdb {
52fff327	146	struct mlx5_flow_table *slow_fdb;
69697b6e	147	struct mlx5_flow_group *send_to_vport_grp;
ac004b83 RD	148	struct mlx5_flow_group *peer_miss_grp;
ac004b83 RD	149	struct mlx5_flow_handle **peer_miss_rules;
69697b6e	150	struct mlx5_flow_group *miss_grp;
f80be543 MB	151	struct mlx5_flow_handle *miss_rule_uni;
f80be543 MB	152	struct mlx5_flow_handle *miss_rule_multi;
f5f82476	153	int vlan_push_pop_refcount;
e52c2802 PB	154
	155	struct {
	156	struct mlx5_flow_table *fdb;
	157	u32 num_rules;
	158	} fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
	159	/* Protects fdb_prio table */
	160	struct mutex fdb_prio_lock;
	161
	162	int fdb_left[ARRAY_SIZE(ESW_POOLS)];
69697b6e	163	} offloads;
6ab36e35	164	};
e52c2802	165	u32 flags;
6ab36e35 OG	166	};
6ab36e35 OG	167
c116c6ee OG	168	struct mlx5_esw_offload {
c116c6ee OG	169	struct mlx5_flow_table *ft_offloads;
fed9ce22	170	struct mlx5_flow_group *vport_rx_group;
127ea380	171	struct mlx5_eswitch_rep *vport_reps;
04de7dda RD	172	struct list_head peer_flows;
04de7dda RD	173	struct mutex peer_mutex;
a54e20b4	174	DECLARE_HASHTABLE(encap_tbl, 8);
11c9c548	175	DECLARE_HASHTABLE(mod_hdr_tbl, 8);
bffaa916	176	u8 inline_mode;
375f51e2	177	u64 num_flows;
7768d197	178	u8 encap;
c116c6ee OG	179	};
c116c6ee OG	180
0a0ab1d2 EC	181	/* E-Switch MC FDB table hash node */
	182	struct esw_mc_addr { /* SRIOV only */
	183	struct l2addr_node node;
	184	struct mlx5_flow_handle uplink_rule; / Forward to uplink rule */
	185	u32 refcnt;
	186	};
	187
a3888f33 BW	188	struct mlx5_host_work {
	189	struct work_struct work;
	190	struct mlx5_eswitch *esw;
	191	};
	192
	193	struct mlx5_host_info {
	194	struct mlx5_nb nb;
	195	u16 num_vfs;
	196	};
	197
073bb189 SM	198	struct mlx5_eswitch {
073bb189 SM	199	struct mlx5_core_dev *dev;
6933a937	200	struct mlx5_nb nb;
81848731 SM	201	struct mlx5_eswitch_fdb fdb_table;
81848731 SM	202	struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
073bb189 SM	203	struct workqueue_struct *work_queue;
	204	struct mlx5_vport *vports;
	205	int total_vports;
81848731	206	int enabled_vports;
dfcb1ed3 MHY	207	/* Synchronize between vport change events
	208	* and async SRIOV admin state changes
	209	*/
	210	struct mutex state_lock;
0a0ab1d2	211	struct esw_mc_addr mc_promisc;
1bd27b11 MHY	212
	213	struct {
	214	bool enabled;
	215	u32 root_tsar_id;
	216	} qos;
	217
c116c6ee	218	struct mlx5_esw_offload offloads;
6ab36e35	219	int mode;
e52c2802	220	int nvports;
a1b3839a	221	u16 manager_vport;
a3888f33	222	struct mlx5_host_info host_info;
073bb189 SM	223	};
073bb189 SM	224
c9b99abc BW	225	void esw_offloads_cleanup(struct mlx5_eswitch *esw);
	226	int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports,
	227	int total_nvports);
e8d31c4d MB	228	void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
e8d31c4d MB	229	int esw_offloads_init_reps(struct mlx5_eswitch *esw);
766a0e97	230
073bb189 SM	231	/* E-Switch API */
	232	int mlx5_eswitch_init(struct mlx5_core_dev *dev);
	233	void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
6ab36e35	234	int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
81848731	235	void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
77256579 SM	236	int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
	237	int vport, u8 mac[ETH_ALEN]);
	238	int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
	239	int vport, int link_state);
9e7ea352 SM	240	int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
9e7ea352 SM	241	int vport, u16 vlan, u8 qos);
f942380c MHY	242	int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
f942380c MHY	243	int vport, bool spoofchk);
1edc57e2 MHY	244	int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1edc57e2 MHY	245	int vport_num, bool setting);
c9497c98 MHY	246	int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
c9497c98 MHY	247	u32 max_rate, u32 min_rate);
8da202b2 HN	248	int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
8da202b2 HN	249	int mlx5_eswitch_get_vepa(struct mlx5_eswitch esw, u8 setting);
77256579 SM	250	int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
77256579 SM	251	int vport, struct ifla_vf_info *ivi);
3b751a2a SM	252	int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
	253	int vport,
	254	struct ifla_vf_stats *vf_stats);
159fe639	255	void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
073bb189	256
3d80d1a2	257	struct mlx5_flow_spec;
776b12b6	258	struct mlx5_esw_flow_attr;
3d80d1a2	259
74491de9	260	struct mlx5_flow_handle *
3d80d1a2 OG	261	mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
3d80d1a2 OG	262	struct mlx5_flow_spec *spec,
776b12b6	263	struct mlx5_esw_flow_attr *attr);
e4ad91f2 CM	264	struct mlx5_flow_handle *
	265	mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
	266	struct mlx5_flow_spec *spec,
	267	struct mlx5_esw_flow_attr *attr);
d85cdccb OG	268	void
	269	mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
	270	struct mlx5_flow_handle *rule,
	271	struct mlx5_esw_flow_attr *attr);
48265006 OG	272	void
	273	mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
	274	struct mlx5_flow_handle *rule,
	275	struct mlx5_esw_flow_attr *attr);
d85cdccb	276
e52c2802 PB	277	bool
	278	mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
	279
	280	u16
	281	mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
	282
	283	u32
	284	mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
	285
74491de9	286	struct mlx5_flow_handle *
c966f7d5 GT	287	mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport,
c966f7d5 GT	288	struct mlx5_flow_destination *dest);
fed9ce22	289
e33dfe31 OG	290	enum {
	291	SET_VLAN_STRIP = BIT(0),
	292	SET_VLAN_INSERT = BIT(1)
	293	};
	294
d708f902 OG	295	enum mlx5_flow_match_level {
	296	MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
	297	MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
	298	MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
	299	MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
	300	};
	301
592d3651 CM	302	/* current maximum for flow based vport multicasting */
	303	#define MLX5_MAX_FLOW_FWD_VPORTS 2
	304
f493f155 EB	305	enum {
f493f155 EB	306	MLX5_ESW_DEST_ENCAP = BIT(0),
8c4dc42b	307	MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
f493f155 EB	308	};
f493f155 EB	309
776b12b6 OG	310	struct mlx5_esw_flow_attr {
776b12b6 OG	311	struct mlx5_eswitch_rep *in_rep;
10ff5359	312	struct mlx5_core_dev *in_mdev;
f9392795	313	struct mlx5_core_dev *counter_dev;
776b12b6	314
e85e02ba	315	int split_count;
592d3651 CM	316	int out_count;
592d3651 CM	317
776b12b6	318	int action;
cc495188 JL	319	__be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
	320	u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
	321	u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
	322	u8 total_vlan;
f5f82476	323	bool vlan_handled;
df65a573	324	struct {
f493f155	325	u32 flags;
df65a573 EB	326	struct mlx5_eswitch_rep *rep;
df65a573 EB	327	struct mlx5_core_dev *mdev;
8c4dc42b	328	u32 encap_id;
df65a573	329	} dests[MLX5_MAX_FLOW_FWD_VPORTS];
d7e75a32	330	u32 mod_hdr_id;
38aa51c1	331	u8 match_level;
6363651d	332	u8 tunnel_match_level;
b8aee822	333	struct mlx5_fc *counter;
e52c2802 PB	334	u32 chain;
	335	u16 prio;
	336	u32 dest_chain;
232c0013	337	struct mlx5e_tc_flow_parse_attr *parse_attr;
776b12b6 OG	338	};
776b12b6 OG	339
db7ff19e EB	340	int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
db7ff19e EB	341	struct netlink_ext_ack *extack);
feae9087	342	int mlx5_devlink_eswitch_mode_get(struct devlink devlink, u16 mode);
db7ff19e EB	343	int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
db7ff19e EB	344	struct netlink_ext_ack *extack);
bffaa916 RD	345	int mlx5_devlink_eswitch_inline_mode_get(struct devlink devlink, u8 mode);
bffaa916 RD	346	int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch esw, int nvfs, u8 mode);
db7ff19e EB	347	int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
db7ff19e EB	348	struct netlink_ext_ack *extack);
7768d197	349	int mlx5_devlink_eswitch_encap_mode_get(struct devlink devlink, u8 encap);
a4b97ab4	350	void mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch esw, u8 rep_type);
feae9087	351
f5f82476 OG	352	int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
	353	struct mlx5_esw_flow_attr *attr);
	354	int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
	355	struct mlx5_esw_flow_attr *attr);
	356	int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
	357	int vport, u16 vlan, u8 qos, u8 set_flags);
	358
cc495188 JL	359	static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
cc495188 JL	360	u8 vlan_depth)
6acfbf38	361	{
cc495188 JL	362	bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
	363	MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
	364
	365	if (vlan_depth == 1)
	366	return ret;
	367
	368	return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
	369	MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
6acfbf38 OG	370	}
6acfbf38 OG	371
eff849b2 RL	372	bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
eff849b2 RL	373	struct mlx5_core_dev *dev1);
544fe7c2 RD	374	bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
544fe7c2 RD	375	struct mlx5_core_dev *dev1);
eff849b2	376
69697b6e OG	377	#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
69697b6e OG	378
27b942fb PP	379	#define esw_info(__dev, format, ...) \
27b942fb PP	380	dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
69697b6e	381
27b942fb PP	382	#define esw_warn(__dev, format, ...) \
27b942fb PP	383	dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
69697b6e OG	384
	385	#define esw_debug(dev, format, ...) \
	386	mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
a1b3839a BW	387
	388	/* The returned number is valid only when the dev is eswitch manager. */
	389	static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
	390	{
	391	return mlx5_core_is_ecpf_esw_manager(dev) ?
	392	MLX5_VPORT_ECPF : MLX5_VPORT_PF;
	393	}
	394
5ae51620 BW	395	static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
	396	{
	397	/* Uplink always locate at the last element of the array.*/
	398	return esw->total_vports - 1;
	399	}
	400
81cd229c BW	401	static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
	402	{
	403	return esw->total_vports - 2;
	404	}
	405
5ae51620 BW	406	static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
	407	u16 vport_num)
	408	{
81cd229c BW	409	if (vport_num == MLX5_VPORT_ECPF) {
	410	if (!mlx5_ecpf_vport_exists(esw->dev))
	411	esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
	412	return mlx5_eswitch_ecpf_idx(esw);
	413	}
	414
5ae51620 BW	415	if (vport_num == MLX5_VPORT_UPLINK)
	416	return mlx5_eswitch_uplink_idx(esw);
	417
	418	return vport_num;
	419	}
	420
	421	static inline int mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
	422	int index)
	423	{
81cd229c BW	424	if (index == mlx5_eswitch_ecpf_idx(esw) &&
	425	mlx5_ecpf_vport_exists(esw->dev))
	426	return MLX5_VPORT_ECPF;
	427
5ae51620 BW	428	if (index == mlx5_eswitch_uplink_idx(esw))
	429	return MLX5_VPORT_UPLINK;
	430
	431	return index;
	432	}
	433
e80541ec SM	434	#else /* CONFIG_MLX5_ESWITCH */
	435	/* eswitch API stubs */
	436	static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
	437	static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
e80541ec SM	438	static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
e80541ec SM	439	static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
eff849b2	440	static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev dev0, struct mlx5_core_dev dev1) { return true; }
328edb49 PB	441
328edb49 PB	442	#define FDB_MAX_CHAIN 1
c92a0b94	443	#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
328edb49 PB	444	#define FDB_MAX_PRIO 1
328edb49 PB	445
e80541ec SM	446	#endif /* CONFIG_MLX5_ESWITCH */
e80541ec SM	447
073bb189	448	#endif /* __MLX5_ESWITCH_H__ */