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073bb189 SM |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies, Ltd. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef __MLX5_ESWITCH_H__ | |
34 | #define __MLX5_ESWITCH_H__ | |
35 | ||
77256579 SM |
36 | #include <linux/if_ether.h> |
37 | #include <linux/if_link.h> | |
525e84be | 38 | #include <linux/atomic.h> |
84ae9c1f | 39 | #include <linux/xarray.h> |
feae9087 | 40 | #include <net/devlink.h> |
073bb189 | 41 | #include <linux/mlx5/device.h> |
57cbd893 | 42 | #include <linux/mlx5/eswitch.h> |
a1b3839a | 43 | #include <linux/mlx5/vport.h> |
cc495188 | 44 | #include <linux/mlx5/fs.h> |
eeb66cdb | 45 | #include "lib/mpfs.h" |
ae430332 | 46 | #include "lib/fs_chains.h" |
d7f33a45 | 47 | #include "sf/sf.h" |
4c3844d9 | 48 | #include "en/tc_ct.h" |
0027d70c | 49 | #include "en/tc/sample.h" |
073bb189 | 50 | |
a91d98a0 CM |
51 | enum mlx5_mapped_obj_type { |
52 | MLX5_MAPPED_OBJ_CHAIN, | |
be9dc004 | 53 | MLX5_MAPPED_OBJ_SAMPLE, |
4f4edcc2 | 54 | MLX5_MAPPED_OBJ_INT_PORT_METADATA, |
a91d98a0 CM |
55 | }; |
56 | ||
57 | struct mlx5_mapped_obj { | |
58 | enum mlx5_mapped_obj_type type; | |
59 | union { | |
60 | u32 chain; | |
be9dc004 CM |
61 | struct { |
62 | u32 group_id; | |
63 | u32 rate; | |
64 | u32 trunc_size; | |
ee950e5d | 65 | u32 tunnel_id; |
be9dc004 | 66 | } sample; |
4f4edcc2 | 67 | u32 int_port_metadata; |
a91d98a0 CM |
68 | }; |
69 | }; | |
70 | ||
e80541ec SM |
71 | #ifdef CONFIG_MLX5_ESWITCH |
72 | ||
87dac697 JL |
73 | #define ESW_OFFLOADS_DEFAULT_NUM_GROUPS 15 |
74 | ||
073bb189 SM |
75 | #define MLX5_MAX_UC_PER_VPORT(dev) \ |
76 | (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list)) | |
77 | ||
78 | #define MLX5_MAX_MC_PER_VPORT(dev) \ | |
79 | (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list)) | |
80 | ||
a842dd04 CM |
81 | #define mlx5_esw_has_fwd_fdb(dev) \ |
82 | MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table) | |
83 | ||
ae430332 AL |
84 | #define esw_chains(esw) \ |
85 | ((esw)->fdb_table.offloads.esw_chains_priv) | |
86 | ||
2198b932 RD |
87 | enum { |
88 | MAPPING_TYPE_CHAIN, | |
89 | MAPPING_TYPE_TUNNEL, | |
90 | MAPPING_TYPE_TUNNEL_ENC_OPTS, | |
91 | MAPPING_TYPE_LABELS, | |
92 | MAPPING_TYPE_ZONE, | |
4f4edcc2 | 93 | MAPPING_TYPE_INT_PORT, |
2198b932 RD |
94 | }; |
95 | ||
5742df0f MHY |
96 | struct vport_ingress { |
97 | struct mlx5_flow_table *acl; | |
10652f39 | 98 | struct mlx5_flow_handle *allow_rule; |
853b5352 | 99 | struct { |
10652f39 PP |
100 | struct mlx5_flow_group *allow_spoofchk_only_grp; |
101 | struct mlx5_flow_group *allow_untagged_spoofchk_grp; | |
102 | struct mlx5_flow_group *allow_untagged_only_grp; | |
103 | struct mlx5_flow_group *drop_grp; | |
853b5352 PP |
104 | struct mlx5_flow_handle *drop_rule; |
105 | struct mlx5_fc *drop_counter; | |
106 | } legacy; | |
d68316b5 | 107 | struct { |
b7826076 PP |
108 | /* Optional group to add an FTE to do internal priority |
109 | * tagging on ingress packets. | |
110 | */ | |
111 | struct mlx5_flow_group *metadata_prio_tag_grp; | |
112 | /* Group to add default match-all FTE entry to tag ingress | |
113 | * packet with metadata. | |
114 | */ | |
115 | struct mlx5_flow_group *metadata_allmatch_grp; | |
1749c4c5 MB |
116 | /* Optional group to add a drop all rule */ |
117 | struct mlx5_flow_group *drop_grp; | |
d68316b5 PP |
118 | struct mlx5_modify_hdr *modify_metadata; |
119 | struct mlx5_flow_handle *modify_metadata_rule; | |
1749c4c5 | 120 | struct mlx5_flow_handle *drop_rule; |
d68316b5 | 121 | } offloads; |
5742df0f MHY |
122 | }; |
123 | ||
124 | struct vport_egress { | |
125 | struct mlx5_flow_table *acl; | |
74491de9 | 126 | struct mlx5_flow_handle *allowed_vlan; |
ea651a86 | 127 | struct mlx5_flow_group *vlan_grp; |
bf773dc0 VP |
128 | union { |
129 | struct { | |
130 | struct mlx5_flow_group *drop_grp; | |
131 | struct mlx5_flow_handle *drop_rule; | |
132 | struct mlx5_fc *drop_counter; | |
133 | } legacy; | |
134 | struct { | |
135 | struct mlx5_flow_group *fwd_grp; | |
136 | struct mlx5_flow_handle *fwd_rule; | |
db202995 MB |
137 | struct mlx5_flow_handle *bounce_rule; |
138 | struct mlx5_flow_group *bounce_grp; | |
bf773dc0 VP |
139 | } offloads; |
140 | }; | |
b8a0dbe3 EE |
141 | }; |
142 | ||
143 | struct mlx5_vport_drop_stats { | |
144 | u64 rx_dropped; | |
145 | u64 tx_dropped; | |
5742df0f MHY |
146 | }; |
147 | ||
1ab2068a MHY |
148 | struct mlx5_vport_info { |
149 | u8 mac[ETH_ALEN]; | |
150 | u16 vlan; | |
1ab2068a MHY |
151 | u64 node_guid; |
152 | int link_state; | |
cadb129f PP |
153 | u8 qos; |
154 | u8 spoofchk: 1; | |
155 | u8 trusted: 1; | |
7db98396 | 156 | u8 roce_enabled: 1; |
e5b9642a | 157 | u8 mig_enabled: 1; |
1ab2068a MHY |
158 | }; |
159 | ||
5019833d PP |
160 | /* Vport context events */ |
161 | enum mlx5_eswitch_vport_event { | |
162 | MLX5_VPORT_UC_ADDR_CHANGE = BIT(0), | |
163 | MLX5_VPORT_MC_ADDR_CHANGE = BIT(1), | |
164 | MLX5_VPORT_PROMISC_CHANGE = BIT(3), | |
165 | }; | |
166 | ||
073bb189 SM |
167 | struct mlx5_vport { |
168 | struct mlx5_core_dev *dev; | |
073bb189 | 169 | struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE]; |
81848731 | 170 | struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE]; |
74491de9 MB |
171 | struct mlx5_flow_handle *promisc_rule; |
172 | struct mlx5_flow_handle *allmulti_rule; | |
073bb189 SM |
173 | struct work_struct vport_change_handler; |
174 | ||
5742df0f MHY |
175 | struct vport_ingress ingress; |
176 | struct vport_egress egress; | |
133dcfc5 VP |
177 | u32 default_metadata; |
178 | u32 metadata; | |
5742df0f | 179 | |
1ab2068a MHY |
180 | struct mlx5_vport_info info; |
181 | ||
1bd27b11 MHY |
182 | struct { |
183 | bool enabled; | |
184 | u32 esw_tsar_ix; | |
c9497c98 | 185 | u32 bw_share; |
e591605f PP |
186 | u32 min_rate; |
187 | u32 max_rate; | |
0fe132ea | 188 | struct mlx5_esw_rate_group *group; |
1bd27b11 MHY |
189 | } qos; |
190 | ||
6308a5f0 | 191 | u16 vport; |
073bb189 | 192 | bool enabled; |
5019833d | 193 | enum mlx5_eswitch_vport_event enabled_events; |
47dd7e60 | 194 | int index; |
c7eddc60 | 195 | struct devlink_port *dl_port; |
606e6a72 | 196 | struct dentry *dbgfs; |
073bb189 SM |
197 | }; |
198 | ||
34ca6535 VB |
199 | struct mlx5_esw_indir_table; |
200 | ||
81848731 | 201 | struct mlx5_eswitch_fdb { |
6ab36e35 OG |
202 | union { |
203 | struct legacy_fdb { | |
52fff327 | 204 | struct mlx5_flow_table *fdb; |
6ab36e35 OG |
205 | struct mlx5_flow_group *addr_grp; |
206 | struct mlx5_flow_group *allmulti_grp; | |
207 | struct mlx5_flow_group *promisc_grp; | |
8da202b2 HN |
208 | struct mlx5_flow_table *vepa_fdb; |
209 | struct mlx5_flow_handle *vepa_uplink_rule; | |
210 | struct mlx5_flow_handle *vepa_star_rule; | |
6ab36e35 | 211 | } legacy; |
69697b6e OG |
212 | |
213 | struct offloads_fdb { | |
8463daf1 | 214 | struct mlx5_flow_namespace *ns; |
ec3be887 | 215 | struct mlx5_flow_table *tc_miss_table; |
52fff327 | 216 | struct mlx5_flow_table *slow_fdb; |
69697b6e | 217 | struct mlx5_flow_group *send_to_vport_grp; |
8e404fef | 218 | struct mlx5_flow_group *send_to_vport_meta_grp; |
ac004b83 RD |
219 | struct mlx5_flow_group *peer_miss_grp; |
220 | struct mlx5_flow_handle **peer_miss_rules; | |
69697b6e | 221 | struct mlx5_flow_group *miss_grp; |
8e404fef | 222 | struct mlx5_flow_handle **send_to_vport_meta_rules; |
f80be543 MB |
223 | struct mlx5_flow_handle *miss_rule_uni; |
224 | struct mlx5_flow_handle *miss_rule_multi; | |
e52c2802 | 225 | |
ae430332 | 226 | struct mlx5_fs_chains *esw_chains_priv; |
96e32687 EC |
227 | struct { |
228 | DECLARE_HASHTABLE(table, 8); | |
229 | /* Protects vports.table */ | |
230 | struct mutex lock; | |
231 | } vports; | |
232 | ||
34ca6535 VB |
233 | struct mlx5_esw_indir_table *indir; |
234 | ||
69697b6e | 235 | } offloads; |
6ab36e35 | 236 | }; |
e52c2802 | 237 | u32 flags; |
6ab36e35 OG |
238 | }; |
239 | ||
c116c6ee | 240 | struct mlx5_esw_offload { |
11b717d6 PB |
241 | struct mlx5_flow_table *ft_offloads_restore; |
242 | struct mlx5_flow_group *restore_group; | |
6724e66b | 243 | struct mlx5_modify_hdr *restore_copy_hdr_id; |
c9355682 | 244 | struct mapping_ctx *reg_c0_obj_pool; |
11b717d6 | 245 | |
c116c6ee | 246 | struct mlx5_flow_table *ft_offloads; |
fed9ce22 | 247 | struct mlx5_flow_group *vport_rx_group; |
8ea7bcf6 JL |
248 | struct mlx5_flow_group *vport_rx_drop_group; |
249 | struct mlx5_flow_handle *vport_rx_drop_rule; | |
47dd7e60 | 250 | struct xarray vport_reps; |
04de7dda RD |
251 | struct list_head peer_flows; |
252 | struct mutex peer_mutex; | |
61086f39 | 253 | struct mutex encap_tbl_lock; /* protects encap_tbl */ |
a54e20b4 | 254 | DECLARE_HASHTABLE(encap_tbl, 8); |
14e6b038 EC |
255 | struct mutex decap_tbl_lock; /* protects decap_tbl */ |
256 | DECLARE_HASHTABLE(decap_tbl, 8); | |
dd58edc3 | 257 | struct mod_hdr_tbl mod_hdr; |
10caabda OS |
258 | DECLARE_HASHTABLE(termtbl_tbl, 8); |
259 | struct mutex termtbl_mutex; /* protects termtbl hash */ | |
84ae9c1f | 260 | struct xarray vhca_map; |
8693115a | 261 | const struct mlx5_eswitch_rep_ops *rep_ops[NUM_REP_TYPES]; |
bffaa916 | 262 | u8 inline_mode; |
525e84be | 263 | atomic64_t num_flows; |
98fdbea5 | 264 | enum devlink_eswitch_encap_mode encap; |
133dcfc5 | 265 | struct ida vport_metadata_ida; |
a53cf949 | 266 | unsigned int host_number; /* ECPF supports one external host */ |
c116c6ee OG |
267 | }; |
268 | ||
0a0ab1d2 EC |
269 | /* E-Switch MC FDB table hash node */ |
270 | struct esw_mc_addr { /* SRIOV only */ | |
271 | struct l2addr_node node; | |
272 | struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */ | |
273 | u32 refcnt; | |
274 | }; | |
275 | ||
a3888f33 BW |
276 | struct mlx5_host_work { |
277 | struct work_struct work; | |
278 | struct mlx5_eswitch *esw; | |
279 | }; | |
280 | ||
cd56f929 | 281 | struct mlx5_esw_functions { |
a3888f33 BW |
282 | struct mlx5_nb nb; |
283 | u16 num_vfs; | |
284 | }; | |
285 | ||
7445cfb1 JL |
286 | enum { |
287 | MLX5_ESWITCH_VPORT_MATCH_METADATA = BIT(0), | |
5b7cb745 | 288 | MLX5_ESWITCH_REG_C1_LOOPBACK_ENABLED = BIT(1), |
ea5872dd | 289 | MLX5_ESWITCH_VPORT_ACL_NS_CREATED = BIT(2), |
7445cfb1 JL |
290 | }; |
291 | ||
19e9bfa0 VB |
292 | struct mlx5_esw_bridge_offloads; |
293 | ||
fbd43b72 CM |
294 | enum { |
295 | MLX5_ESW_FDB_CREATED = BIT(0), | |
296 | }; | |
297 | ||
073bb189 SM |
298 | struct mlx5_eswitch { |
299 | struct mlx5_core_dev *dev; | |
6933a937 | 300 | struct mlx5_nb nb; |
81848731 | 301 | struct mlx5_eswitch_fdb fdb_table; |
99ecd646 | 302 | /* legacy data structures */ |
81848731 | 303 | struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE]; |
131ce701 PP |
304 | struct esw_mc_addr mc_promisc; |
305 | /* end of legacy */ | |
073bb189 | 306 | struct workqueue_struct *work_queue; |
47dd7e60 | 307 | struct xarray vports; |
7445cfb1 | 308 | u32 flags; |
073bb189 | 309 | int total_vports; |
81848731 | 310 | int enabled_vports; |
dfcb1ed3 MHY |
311 | /* Synchronize between vport change events |
312 | * and async SRIOV admin state changes | |
313 | */ | |
314 | struct mutex state_lock; | |
1bd27b11 | 315 | |
8e0aa4bc PP |
316 | /* Protects eswitch mode change that occurs via one or more |
317 | * user commands, i.e. sriov state change, devlink commands. | |
318 | */ | |
c55479d0 | 319 | struct rw_semaphore mode_lock; |
7dc84de9 | 320 | atomic64_t user_count; |
8e0aa4bc | 321 | |
1bd27b11 | 322 | struct { |
2d116e3e | 323 | u32 root_tsar_ix; |
1ae258f8 | 324 | struct mlx5_esw_rate_group *group0; |
f47e04eb | 325 | struct list_head groups; /* Protected by esw->state_lock */ |
85c5f7c9 DL |
326 | |
327 | /* Protected by esw->state_lock. | |
328 | * Initially 0, meaning no QoS users and QoS is disabled. | |
329 | */ | |
330 | refcount_t refcnt; | |
1bd27b11 MHY |
331 | } qos; |
332 | ||
19e9bfa0 | 333 | struct mlx5_esw_bridge_offloads *br_offloads; |
c116c6ee | 334 | struct mlx5_esw_offload offloads; |
6ab36e35 | 335 | int mode; |
a1b3839a | 336 | u16 manager_vport; |
411ec9e0 | 337 | u16 first_host_vport; |
cd56f929 | 338 | struct mlx5_esw_functions esw_funcs; |
87dac697 JL |
339 | struct { |
340 | u32 large_group_num; | |
341 | } params; | |
8f010541 | 342 | struct blocking_notifier_head n_head; |
606e6a72 | 343 | struct dentry *dbgfs; |
073bb189 SM |
344 | }; |
345 | ||
5896b972 PP |
346 | void esw_offloads_disable(struct mlx5_eswitch *esw); |
347 | int esw_offloads_enable(struct mlx5_eswitch *esw); | |
d2a651ef JP |
348 | void esw_offloads_cleanup(struct mlx5_eswitch *esw); |
349 | int esw_offloads_init(struct mlx5_eswitch *esw); | |
430e2d5e RD |
350 | |
351 | struct mlx5_flow_handle * | |
352 | mlx5_eswitch_add_send_to_vport_meta_rule(struct mlx5_eswitch *esw, u16 vport_num); | |
353 | void mlx5_eswitch_del_send_to_vport_meta_rule(struct mlx5_flow_handle *rule); | |
ea651a86 | 354 | |
7bf481d7 PP |
355 | bool mlx5_esw_vport_match_metadata_supported(const struct mlx5_eswitch *esw); |
356 | int mlx5_esw_offloads_vport_metadata_set(struct mlx5_eswitch *esw, bool enable); | |
133dcfc5 VP |
357 | u32 mlx5_esw_match_metadata_alloc(struct mlx5_eswitch *esw); |
358 | void mlx5_esw_match_metadata_free(struct mlx5_eswitch *esw, u32 metadata); | |
359 | ||
2d116e3e | 360 | int mlx5_esw_qos_modify_vport_rate(struct mlx5_eswitch *esw, u16 vport_num, u32 rate_mbps); |
766a0e97 | 361 | |
073bb189 SM |
362 | /* E-Switch API */ |
363 | int mlx5_eswitch_init(struct mlx5_core_dev *dev); | |
364 | void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw); | |
ebf77bb8 PP |
365 | |
366 | #define MLX5_ESWITCH_IGNORE_NUM_VFS (-1) | |
b6f2846a | 367 | int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int num_vfs); |
8e0aa4bc | 368 | int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs); |
f019679e CM |
369 | void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf); |
370 | void mlx5_eswitch_disable_locked(struct mlx5_eswitch *esw); | |
371 | void mlx5_eswitch_disable(struct mlx5_eswitch *esw); | |
77256579 | 372 | int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw, |
fa997825 | 373 | u16 vport, const u8 *mac); |
77256579 | 374 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, |
02f3afd9 | 375 | u16 vport, int link_state); |
9e7ea352 | 376 | int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 377 | u16 vport, u16 vlan, u8 qos); |
f942380c | 378 | int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw, |
02f3afd9 | 379 | u16 vport, bool spoofchk); |
1edc57e2 | 380 | int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw, |
02f3afd9 PP |
381 | u16 vport_num, bool setting); |
382 | int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport, | |
c9497c98 | 383 | u32 max_rate, u32 min_rate); |
0fe132ea DL |
384 | int mlx5_esw_qos_vport_update_group(struct mlx5_eswitch *esw, |
385 | struct mlx5_vport *vport, | |
386 | struct mlx5_esw_rate_group *group, | |
387 | struct netlink_ext_ack *extack); | |
8da202b2 HN |
388 | int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting); |
389 | int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting); | |
77256579 | 390 | int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw, |
02f3afd9 | 391 | u16 vport, struct ifla_vf_info *ivi); |
3b751a2a | 392 | int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw, |
02f3afd9 | 393 | u16 vport, |
3b751a2a | 394 | struct ifla_vf_stats *vf_stats); |
159fe639 | 395 | void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule); |
073bb189 | 396 | |
238302fa | 397 | int mlx5_eswitch_modify_esw_vport_context(struct mlx5_core_dev *dev, u16 vport, |
e08a6832 | 398 | bool other_vport, void *in); |
57843868 | 399 | |
3d80d1a2 | 400 | struct mlx5_flow_spec; |
776b12b6 | 401 | struct mlx5_esw_flow_attr; |
10caabda OS |
402 | struct mlx5_termtbl_handle; |
403 | ||
404 | bool | |
405 | mlx5_eswitch_termtbl_required(struct mlx5_eswitch *esw, | |
c620b772 | 406 | struct mlx5_flow_attr *attr, |
10caabda OS |
407 | struct mlx5_flow_act *flow_act, |
408 | struct mlx5_flow_spec *spec); | |
409 | ||
410 | struct mlx5_flow_handle * | |
411 | mlx5_eswitch_add_termtbl_rule(struct mlx5_eswitch *esw, | |
412 | struct mlx5_flow_table *ft, | |
413 | struct mlx5_flow_spec *spec, | |
414 | struct mlx5_esw_flow_attr *attr, | |
415 | struct mlx5_flow_act *flow_act, | |
416 | struct mlx5_flow_destination *dest, | |
417 | int num_dest); | |
418 | ||
419 | void | |
420 | mlx5_eswitch_termtbl_put(struct mlx5_eswitch *esw, | |
421 | struct mlx5_termtbl_handle *tt); | |
3d80d1a2 | 422 | |
f94d6389 CM |
423 | void |
424 | mlx5_eswitch_clear_rule_source_port(struct mlx5_eswitch *esw, struct mlx5_flow_spec *spec); | |
425 | ||
74491de9 | 426 | struct mlx5_flow_handle * |
3d80d1a2 OG |
427 | mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw, |
428 | struct mlx5_flow_spec *spec, | |
c620b772 | 429 | struct mlx5_flow_attr *attr); |
e4ad91f2 CM |
430 | struct mlx5_flow_handle * |
431 | mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw, | |
432 | struct mlx5_flow_spec *spec, | |
c620b772 | 433 | struct mlx5_flow_attr *attr); |
d85cdccb OG |
434 | void |
435 | mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw, | |
436 | struct mlx5_flow_handle *rule, | |
c620b772 | 437 | struct mlx5_flow_attr *attr); |
48265006 OG |
438 | void |
439 | mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw, | |
440 | struct mlx5_flow_handle *rule, | |
c620b772 | 441 | struct mlx5_flow_attr *attr); |
d85cdccb | 442 | |
74491de9 | 443 | struct mlx5_flow_handle * |
02f3afd9 | 444 | mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport, |
c966f7d5 | 445 | struct mlx5_flow_destination *dest); |
fed9ce22 | 446 | |
e33dfe31 OG |
447 | enum { |
448 | SET_VLAN_STRIP = BIT(0), | |
449 | SET_VLAN_INSERT = BIT(1) | |
450 | }; | |
451 | ||
d708f902 OG |
452 | enum mlx5_flow_match_level { |
453 | MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE, | |
454 | MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2, | |
455 | MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP, | |
456 | MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP, | |
457 | }; | |
458 | ||
592d3651 | 459 | /* current maximum for flow based vport multicasting */ |
d40bfedd | 460 | #define MLX5_MAX_FLOW_FWD_VPORTS 32 |
592d3651 | 461 | |
f493f155 EB |
462 | enum { |
463 | MLX5_ESW_DEST_ENCAP = BIT(0), | |
8c4dc42b | 464 | MLX5_ESW_DEST_ENCAP_VALID = BIT(1), |
10742efc | 465 | MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE = BIT(2), |
f493f155 EB |
466 | }; |
467 | ||
776b12b6 OG |
468 | struct mlx5_esw_flow_attr { |
469 | struct mlx5_eswitch_rep *in_rep; | |
10ff5359 | 470 | struct mlx5_core_dev *in_mdev; |
f9392795 | 471 | struct mlx5_core_dev *counter_dev; |
27484f71 | 472 | struct mlx5e_tc_int_port *dest_int_port; |
166f431e | 473 | struct mlx5e_tc_int_port *int_port; |
776b12b6 | 474 | |
e85e02ba | 475 | int split_count; |
592d3651 CM |
476 | int out_count; |
477 | ||
cc495188 JL |
478 | __be16 vlan_proto[MLX5_FS_VLAN_DEPTH]; |
479 | u16 vlan_vid[MLX5_FS_VLAN_DEPTH]; | |
480 | u8 vlan_prio[MLX5_FS_VLAN_DEPTH]; | |
481 | u8 total_vlan; | |
df65a573 | 482 | struct { |
f493f155 | 483 | u32 flags; |
df65a573 | 484 | struct mlx5_eswitch_rep *rep; |
2b688ea5 | 485 | struct mlx5_pkt_reformat *pkt_reformat; |
df65a573 | 486 | struct mlx5_core_dev *mdev; |
10caabda | 487 | struct mlx5_termtbl_handle *termtbl; |
8914add2 | 488 | int src_port_rewrite_act_id; |
df65a573 | 489 | } dests[MLX5_MAX_FLOW_FWD_VPORTS]; |
34ca6535 | 490 | struct mlx5_rx_tun_attr *rx_tun_attr; |
697319b2 | 491 | struct ethhdr eth; |
14e6b038 | 492 | struct mlx5_pkt_reformat *decap_pkt_reformat; |
776b12b6 OG |
493 | }; |
494 | ||
db7ff19e EB |
495 | int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode, |
496 | struct netlink_ext_ack *extack); | |
feae9087 | 497 | int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode); |
db7ff19e EB |
498 | int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode, |
499 | struct netlink_ext_ack *extack); | |
bffaa916 | 500 | int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode); |
98fdbea5 LR |
501 | int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, |
502 | enum devlink_eswitch_encap_mode encap, | |
db7ff19e | 503 | struct netlink_ext_ack *extack); |
98fdbea5 LR |
504 | int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, |
505 | enum devlink_eswitch_encap_mode *encap); | |
82564f6c | 506 | int mlx5_devlink_port_function_hw_addr_get(struct devlink_port *port, |
f099fde1 PP |
507 | u8 *hw_addr, int *hw_addr_len, |
508 | struct netlink_ext_ack *extack); | |
82564f6c | 509 | int mlx5_devlink_port_function_hw_addr_set(struct devlink_port *port, |
330077d1 PP |
510 | const u8 *hw_addr, int hw_addr_len, |
511 | struct netlink_ext_ack *extack); | |
7db98396 YH |
512 | int mlx5_devlink_port_fn_roce_get(struct devlink_port *port, bool *is_enabled, |
513 | struct netlink_ext_ack *extack); | |
514 | int mlx5_devlink_port_fn_roce_set(struct devlink_port *port, bool enable, | |
515 | struct netlink_ext_ack *extack); | |
e5b9642a SD |
516 | int mlx5_devlink_port_fn_migratable_get(struct devlink_port *port, bool *is_enabled, |
517 | struct netlink_ext_ack *extack); | |
518 | int mlx5_devlink_port_fn_migratable_set(struct devlink_port *port, bool enable, | |
519 | struct netlink_ext_ack *extack); | |
a4b97ab4 | 520 | void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type); |
feae9087 | 521 | |
f5f82476 | 522 | int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw, |
02f3afd9 | 523 | u16 vport, u16 vlan, u8 qos, u8 set_flags); |
f5f82476 | 524 | |
1f0ae22a MS |
525 | static inline bool esw_vst_mode_is_steering(struct mlx5_eswitch *esw) |
526 | { | |
527 | return (MLX5_CAP_ESW_EGRESS_ACL(esw->dev, pop_vlan) && | |
528 | MLX5_CAP_ESW_INGRESS_ACL(esw->dev, push_vlan)); | |
529 | } | |
530 | ||
cc495188 JL |
531 | static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev, |
532 | u8 vlan_depth) | |
6acfbf38 | 533 | { |
cc495188 JL |
534 | bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) && |
535 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan); | |
536 | ||
537 | if (vlan_depth == 1) | |
538 | return ret; | |
539 | ||
540 | return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) && | |
541 | MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2); | |
6acfbf38 OG |
542 | } |
543 | ||
544fe7c2 RD |
544 | bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0, |
545 | struct mlx5_core_dev *dev1); | |
eff849b2 | 546 | |
dd28087c | 547 | const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev); |
cd56f929 | 548 | |
69697b6e OG |
549 | #define MLX5_DEBUG_ESWITCH_MASK BIT(3) |
550 | ||
27b942fb PP |
551 | #define esw_info(__dev, format, ...) \ |
552 | dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e | 553 | |
27b942fb PP |
554 | #define esw_warn(__dev, format, ...) \ |
555 | dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__) | |
69697b6e OG |
556 | |
557 | #define esw_debug(dev, format, ...) \ | |
558 | mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__) | |
a1b3839a | 559 | |
b16f2bb6 PP |
560 | static inline bool mlx5_esw_allowed(const struct mlx5_eswitch *esw) |
561 | { | |
562 | return esw && MLX5_ESWITCH_MANAGER(esw->dev); | |
563 | } | |
564 | ||
a1b3839a BW |
565 | /* The returned number is valid only when the dev is eswitch manager. */ |
566 | static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev) | |
567 | { | |
568 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
569 | MLX5_VPORT_ECPF : MLX5_VPORT_PF; | |
570 | } | |
571 | ||
ea2300e0 PP |
572 | static inline bool |
573 | mlx5_esw_is_manager_vport(const struct mlx5_eswitch *esw, u16 vport_num) | |
574 | { | |
575 | return esw->manager_vport == vport_num; | |
576 | } | |
577 | ||
411ec9e0 BW |
578 | static inline u16 mlx5_eswitch_first_host_vport_num(struct mlx5_core_dev *dev) |
579 | { | |
580 | return mlx5_core_is_ecpf_esw_manager(dev) ? | |
581 | MLX5_VPORT_PF : MLX5_VPORT_FIRST_VF; | |
582 | } | |
583 | ||
3d5f41ca | 584 | static inline bool mlx5_eswitch_is_funcs_handler(const struct mlx5_core_dev *dev) |
6706a3b9 | 585 | { |
3d5f41ca | 586 | return mlx5_core_is_ecpf_esw_manager(dev); |
6706a3b9 VP |
587 | } |
588 | ||
443bf36e PP |
589 | static inline unsigned int |
590 | mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, | |
591 | u16 vport_num) | |
592 | { | |
593 | return (MLX5_CAP_GEN(dev, vhca_id) << 16) | vport_num; | |
594 | } | |
595 | ||
f099fde1 PP |
596 | static inline u16 |
597 | mlx5_esw_devlink_port_index_to_vport_num(unsigned int dl_port_index) | |
598 | { | |
599 | return dl_port_index & 0xffff; | |
600 | } | |
601 | ||
fbd43b72 CM |
602 | static inline bool mlx5_esw_is_fdb_created(struct mlx5_eswitch *esw) |
603 | { | |
604 | return esw->fdb_table.flags & MLX5_ESW_FDB_CREATED; | |
605 | } | |
606 | ||
ee576ec1 SM |
607 | /* TODO: This mlx5e_tc function shouldn't be called by eswitch */ |
608 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw); | |
609 | ||
47dd7e60 PP |
610 | /* Each mark identifies eswitch vport type. |
611 | * MLX5_ESW_VPT_HOST_FN is used to identify both PF and VF ports using | |
612 | * a single mark. | |
613 | * MLX5_ESW_VPT_VF identifies a SRIOV VF vport. | |
614 | * MLX5_ESW_VPT_SF identifies SF vport. | |
786ef904 | 615 | */ |
47dd7e60 PP |
616 | #define MLX5_ESW_VPT_HOST_FN XA_MARK_0 |
617 | #define MLX5_ESW_VPT_VF XA_MARK_1 | |
618 | #define MLX5_ESW_VPT_SF XA_MARK_2 | |
619 | ||
620 | /* The vport iterator is valid only after vport are initialized in mlx5_eswitch_init. | |
621 | * Borrowed the idea from xa_for_each_marked() but with support for desired last element. | |
786ef904 | 622 | */ |
47dd7e60 PP |
623 | |
624 | #define mlx5_esw_for_each_vport(esw, index, vport) \ | |
625 | xa_for_each(&((esw)->vports), index, vport) | |
626 | ||
627 | #define mlx5_esw_for_each_entry_marked(xa, index, entry, last, filter) \ | |
628 | for (index = 0, entry = xa_find(xa, &index, last, filter); \ | |
629 | entry; entry = xa_find_after(xa, &index, last, filter)) | |
630 | ||
631 | #define mlx5_esw_for_each_vport_marked(esw, index, vport, last, filter) \ | |
632 | mlx5_esw_for_each_entry_marked(&((esw)->vports), index, vport, last, filter) | |
633 | ||
634 | #define mlx5_esw_for_each_vf_vport(esw, index, vport, last) \ | |
635 | mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_VF) | |
636 | ||
637 | #define mlx5_esw_for_each_host_func_vport(esw, index, vport, last) \ | |
638 | mlx5_esw_for_each_vport_marked(esw, index, vport, last, MLX5_ESW_VPT_HOST_FN) | |
d7f33a45 | 639 | |
bd939753 | 640 | struct mlx5_eswitch *mlx5_devlink_eswitch_get(struct devlink *devlink); |
5d9986a3 BW |
641 | struct mlx5_vport *__must_check |
642 | mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
643 | ||
47dd7e60 PP |
644 | bool mlx5_eswitch_is_vf_vport(struct mlx5_eswitch *esw, u16 vport_num); |
645 | bool mlx5_esw_is_sf_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
91d6291c | 646 | |
16fff98a | 647 | int mlx5_esw_funcs_changed_handler(struct notifier_block *nb, unsigned long type, void *data); |
062f4bf4 | 648 | |
925a6acc | 649 | int |
5019833d PP |
650 | mlx5_eswitch_enable_pf_vf_vports(struct mlx5_eswitch *esw, |
651 | enum mlx5_eswitch_vport_event enabled_events); | |
652 | void mlx5_eswitch_disable_pf_vf_vports(struct mlx5_eswitch *esw); | |
653 | ||
d970812b PP |
654 | int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, u16 vport_num, |
655 | enum mlx5_eswitch_vport_event enabled_events); | |
656 | void mlx5_esw_vport_disable(struct mlx5_eswitch *esw, u16 vport_num); | |
657 | ||
748da30b VP |
658 | int |
659 | esw_vport_create_offloads_acl_tables(struct mlx5_eswitch *esw, | |
660 | struct mlx5_vport *vport); | |
661 | void | |
662 | esw_vport_destroy_offloads_acl_tables(struct mlx5_eswitch *esw, | |
663 | struct mlx5_vport *vport); | |
664 | ||
c796bb7c CM |
665 | struct esw_vport_tbl_namespace { |
666 | int max_fte; | |
667 | int max_num_groups; | |
668 | u32 flags; | |
669 | }; | |
670 | ||
4c7f4028 | 671 | struct mlx5_vport_tbl_attr { |
740452e0 | 672 | u32 chain; |
4c7f4028 CM |
673 | u16 prio; |
674 | u16 vport; | |
c796bb7c | 675 | const struct esw_vport_tbl_namespace *vport_ns; |
4c7f4028 CM |
676 | }; |
677 | ||
678 | struct mlx5_flow_table * | |
0a9e2307 | 679 | mlx5_esw_vporttbl_get(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); |
4c7f4028 | 680 | void |
0a9e2307 | 681 | mlx5_esw_vporttbl_put(struct mlx5_eswitch *esw, struct mlx5_vport_tbl_attr *attr); |
96e32687 | 682 | |
11b717d6 PB |
683 | struct mlx5_flow_handle * |
684 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag); | |
11b717d6 | 685 | |
c2d7712c BW |
686 | int esw_offloads_load_rep(struct mlx5_eswitch *esw, u16 vport_num); |
687 | void esw_offloads_unload_rep(struct mlx5_eswitch *esw, u16 vport_num); | |
688 | ||
d970812b PP |
689 | int mlx5_esw_offloads_rep_load(struct mlx5_eswitch *esw, u16 vport_num); |
690 | void mlx5_esw_offloads_rep_unload(struct mlx5_eswitch *esw, u16 vport_num); | |
691 | ||
23bb50cf BW |
692 | int mlx5_eswitch_load_vport(struct mlx5_eswitch *esw, u16 vport_num, |
693 | enum mlx5_eswitch_vport_event enabled_events); | |
694 | void mlx5_eswitch_unload_vport(struct mlx5_eswitch *esw, u16 vport_num); | |
695 | ||
696 | int mlx5_eswitch_load_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs, | |
697 | enum mlx5_eswitch_vport_event enabled_events); | |
698 | void mlx5_eswitch_unload_vf_vports(struct mlx5_eswitch *esw, u16 num_vfs); | |
699 | ||
c7eddc60 PP |
700 | int mlx5_esw_offloads_devlink_port_register(struct mlx5_eswitch *esw, u16 vport_num); |
701 | void mlx5_esw_offloads_devlink_port_unregister(struct mlx5_eswitch *esw, u16 vport_num); | |
702 | struct devlink_port *mlx5_esw_offloads_devlink_port(struct mlx5_eswitch *esw, u16 vport_num); | |
d970812b | 703 | |
606e6a72 MG |
704 | void mlx5_esw_vport_debugfs_create(struct mlx5_eswitch *esw, u16 vport_num, bool is_sf, u16 sf_num); |
705 | void mlx5_esw_vport_debugfs_destroy(struct mlx5_eswitch *esw, u16 vport_num); | |
706 | ||
d970812b | 707 | int mlx5_esw_devlink_sf_port_register(struct mlx5_eswitch *esw, struct devlink_port *dl_port, |
f1b9acd3 | 708 | u16 vport_num, u32 controller, u32 sfnum); |
d970812b PP |
709 | void mlx5_esw_devlink_sf_port_unregister(struct mlx5_eswitch *esw, u16 vport_num); |
710 | ||
711 | int mlx5_esw_offloads_sf_vport_enable(struct mlx5_eswitch *esw, struct devlink_port *dl_port, | |
f1b9acd3 | 712 | u16 vport_num, u32 controller, u32 sfnum); |
d970812b | 713 | void mlx5_esw_offloads_sf_vport_disable(struct mlx5_eswitch *esw, u16 vport_num); |
87bd418e | 714 | int mlx5_esw_sf_max_hpf_functions(struct mlx5_core_dev *dev, u16 *max_sfs, u16 *sf_base_id); |
d970812b | 715 | |
84ae9c1f VB |
716 | int mlx5_esw_vport_vhca_id_set(struct mlx5_eswitch *esw, u16 vport_num); |
717 | void mlx5_esw_vport_vhca_id_clear(struct mlx5_eswitch *esw, u16 vport_num); | |
718 | int mlx5_eswitch_vhca_id_to_vport(struct mlx5_eswitch *esw, u16 vhca_id, u16 *vport_num); | |
719 | ||
8f010541 PP |
720 | /** |
721 | * mlx5_esw_event_info - Indicates eswitch mode changed/changing. | |
722 | * | |
723 | * @new_mode: New mode of eswitch. | |
724 | */ | |
725 | struct mlx5_esw_event_info { | |
726 | u16 new_mode; | |
727 | }; | |
728 | ||
729 | int mlx5_esw_event_notifier_register(struct mlx5_eswitch *esw, struct notifier_block *n); | |
730 | void mlx5_esw_event_notifier_unregister(struct mlx5_eswitch *esw, struct notifier_block *n); | |
7dc84de9 RD |
731 | |
732 | bool mlx5_esw_hold(struct mlx5_core_dev *dev); | |
733 | void mlx5_esw_release(struct mlx5_core_dev *dev); | |
734 | void mlx5_esw_get(struct mlx5_core_dev *dev); | |
735 | void mlx5_esw_put(struct mlx5_core_dev *dev); | |
736 | int mlx5_esw_try_lock(struct mlx5_eswitch *esw); | |
737 | void mlx5_esw_unlock(struct mlx5_eswitch *esw); | |
738 | ||
b55b3538 PP |
739 | void esw_vport_change_handle_locked(struct mlx5_vport *vport); |
740 | ||
f1b9acd3 PP |
741 | bool mlx5_esw_offloads_controller_valid(const struct mlx5_eswitch *esw, u32 controller); |
742 | ||
db202995 MB |
743 | int mlx5_eswitch_offloads_config_single_fdb(struct mlx5_eswitch *master_esw, |
744 | struct mlx5_eswitch *slave_esw); | |
745 | void mlx5_eswitch_offloads_destroy_single_fdb(struct mlx5_eswitch *master_esw, | |
746 | struct mlx5_eswitch *slave_esw); | |
747 | int mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw); | |
748 | ||
e87c6a83 CM |
749 | static inline int mlx5_eswitch_num_vfs(struct mlx5_eswitch *esw) |
750 | { | |
751 | if (mlx5_esw_allowed(esw)) | |
752 | return esw->esw_funcs.num_vfs; | |
753 | ||
754 | return 0; | |
755 | } | |
756 | ||
dcf19b9c MD |
757 | static inline struct mlx5_flow_table * |
758 | mlx5_eswitch_get_slow_fdb(struct mlx5_eswitch *esw) | |
759 | { | |
760 | return esw->fdb_table.offloads.slow_fdb; | |
761 | } | |
e80541ec SM |
762 | #else /* CONFIG_MLX5_ESWITCH */ |
763 | /* eswitch API stubs */ | |
764 | static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; } | |
765 | static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {} | |
8e0aa4bc | 766 | static inline int mlx5_eswitch_enable(struct mlx5_eswitch *esw, int num_vfs) { return 0; } |
f019679e CM |
767 | static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw, bool clear_vf) {} |
768 | static inline void mlx5_eswitch_disable(struct mlx5_eswitch *esw) {} | |
6706a3b9 | 769 | static inline bool mlx5_eswitch_is_funcs_handler(struct mlx5_core_dev *dev) { return false; } |
7d0314b1 RD |
770 | static inline |
771 | int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw, u16 vport, int link_state) { return 0; } | |
dd28087c | 772 | static inline const u32 *mlx5_esw_query_functions(struct mlx5_core_dev *dev) |
10ee82ce | 773 | { |
dd28087c | 774 | return ERR_PTR(-EOPNOTSUPP); |
10ee82ce | 775 | } |
328edb49 | 776 | |
9d3faa51 | 777 | static inline struct mlx5_flow_handle * |
11b717d6 PB |
778 | esw_add_restore_rule(struct mlx5_eswitch *esw, u32 tag) |
779 | { | |
780 | return ERR_PTR(-EOPNOTSUPP); | |
781 | } | |
5a65d85d RD |
782 | |
783 | static inline unsigned int | |
784 | mlx5_esw_vport_to_devlink_port_index(const struct mlx5_core_dev *dev, | |
785 | u16 vport_num) | |
786 | { | |
787 | return vport_num; | |
788 | } | |
db202995 MB |
789 | |
790 | static inline int | |
791 | mlx5_eswitch_offloads_config_single_fdb(struct mlx5_eswitch *master_esw, | |
792 | struct mlx5_eswitch *slave_esw) | |
793 | { | |
794 | return 0; | |
795 | } | |
796 | ||
797 | static inline void | |
798 | mlx5_eswitch_offloads_destroy_single_fdb(struct mlx5_eswitch *master_esw, | |
799 | struct mlx5_eswitch *slave_esw) {} | |
800 | ||
801 | static inline int | |
802 | mlx5_eswitch_reload_reps(struct mlx5_eswitch *esw) | |
803 | { | |
804 | return 0; | |
805 | } | |
e80541ec SM |
806 | #endif /* CONFIG_MLX5_ESWITCH */ |
807 | ||
073bb189 | 808 | #endif /* __MLX5_ESWITCH_H__ */ |