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net/mlx5: Unify and improve command interface
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.c
CommitLineData
073bb189
SM		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
86d722ad 37#include <linux/mlx5/fs.h>
073bb189
SM		 38#include "mlx5_core.h"
39#include "eswitch.h"
40
81848731
SM		 41#define UPLINK_VPORT 0xFFFF
42
073bb189
SM		 43enum {
44 MLX5_ACTION_NONE = 0,
45 MLX5_ACTION_ADD = 1,
46 MLX5_ACTION_DEL = 2,
47};
48
81848731
SM		 49/* E-Switch UC L2 table hash node */
50struct esw_uc_addr {
073bb189 51 struct l2addr_node node;
073bb189
SM		 52 u32 table_index;
53 u32 vport;
54};
55
81848731
SM		 56/* E-Switch MC FDB table hash node */
57struct esw_mc_addr { /* SRIOV only */
58 struct l2addr_node node;
59 struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */
60 u32 refcnt;
61};
62
63/* Vport UC/MC hash node */
64struct vport_addr {
65 struct l2addr_node node;
66 u8 action;
67 u32 vport;
68 struct mlx5_flow_rule *flow_rule; /* SRIOV only */
a35f71f2
MHY		 69 /* A flag indicating that mac was added due to mc promiscuous vport */
70 bool mc_promisc;
073bb189
SM		 71};
72
73enum {
74 UC_ADDR_CHANGE = BIT(0),
75 MC_ADDR_CHANGE = BIT(1),
a35f71f2 76 PROMISC_CHANGE = BIT(3),
073bb189
SM		 77};
78
81848731
SM		 79/* Vport context events */
80#define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \
a35f71f2
MHY		 81 MC_ADDR_CHANGE | \
82 PROMISC_CHANGE)
81848731 83
c930a3ad
OG		 84int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
85void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
69697b6e 86
81848731 87static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport,
073bb189
SM		 88 u32 events_mask)
89{
c4f287c4
SM		 90 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0};
91 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
073bb189 92 void *nic_vport_ctx;
073bb189
SM		 93
94 MLX5_SET(modify_nic_vport_context_in, in,
95 opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT);
96 MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1);
97 MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport);
98 if (vport)
99 MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1);
100 nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in,
101 in, nic_vport_context);
102
103 MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1);
104
105 if (events_mask & UC_ADDR_CHANGE)
106 MLX5_SET(nic_vport_context, nic_vport_ctx,
107 event_on_uc_address_change, 1);
108 if (events_mask & MC_ADDR_CHANGE)
109 MLX5_SET(nic_vport_context, nic_vport_ctx,
110 event_on_mc_address_change, 1);
a35f71f2
MHY		 111 if (events_mask & PROMISC_CHANGE)
112 MLX5_SET(nic_vport_context, nic_vport_ctx,
113 event_on_promisc_change, 1);
073bb189 114
c4f287c4 115 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 116}
117
9e7ea352
SM		 118/* E-Switch vport context HW commands */
119static int query_esw_vport_context_cmd(struct mlx5_core_dev *mdev, u32 vport,
120 u32 *out, int outlen)
121{
c4f287c4 122 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {0};
9e7ea352
SM		 123
124 MLX5_SET(query_nic_vport_context_in, in, opcode,
125 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT);
9e7ea352
SM		 126 MLX5_SET(query_esw_vport_context_in, in, vport_number, vport);
127 if (vport)
128 MLX5_SET(query_esw_vport_context_in, in, other_vport, 1);
c4f287c4 129 return mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
9e7ea352
SM		 130}
131
132static int query_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
133 u16 *vlan, u8 *qos)
134{
c4f287c4 135 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {0};
9e7ea352
SM		 136 int err;
137 bool cvlan_strip;
138 bool cvlan_insert;
139
9e7ea352
SM		 140 *vlan = 0;
141 *qos = 0;
142
143 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
144 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
145 return -ENOTSUPP;
146
147 err = query_esw_vport_context_cmd(dev, vport, out, sizeof(out));
148 if (err)
149 goto out;
150
151 cvlan_strip = MLX5_GET(query_esw_vport_context_out, out,
152 esw_vport_context.vport_cvlan_strip);
153
154 cvlan_insert = MLX5_GET(query_esw_vport_context_out, out,
155 esw_vport_context.vport_cvlan_insert);
156
157 if (cvlan_strip || cvlan_insert) {
158 *vlan = MLX5_GET(query_esw_vport_context_out, out,
159 esw_vport_context.cvlan_id);
160 *qos = MLX5_GET(query_esw_vport_context_out, out,
161 esw_vport_context.cvlan_pcp);
162 }
163
164 esw_debug(dev, "Query Vport[%d] cvlan: VLAN %d qos=%d\n",
165 vport, *vlan, *qos);
166out:
167 return err;
168}
169
170static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport,
171 void *in, int inlen)
172{
c4f287c4 173 u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0};
9e7ea352 174
c4f287c4
SM		 175 MLX5_SET(modify_esw_vport_context_in, in, opcode,
176 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT);
9e7ea352
SM		 177 MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport);
178 if (vport)
179 MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1);
c4f287c4 180 return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
9e7ea352
SM		 181}
182
183static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
184 u16 vlan, u8 qos, bool set)
185{
c4f287c4 186 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {0};
9e7ea352
SM		 187
188 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
189 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
190 return -ENOTSUPP;
191
192 esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%d\n",
193 vport, vlan, qos, set);
9e7ea352
SM		 194 if (set) {
195 MLX5_SET(modify_esw_vport_context_in, in,
196 esw_vport_context.vport_cvlan_strip, 1);
197 /* insert only if no vlan in packet */
198 MLX5_SET(modify_esw_vport_context_in, in,
199 esw_vport_context.vport_cvlan_insert, 1);
200 MLX5_SET(modify_esw_vport_context_in, in,
201 esw_vport_context.cvlan_pcp, qos);
202 MLX5_SET(modify_esw_vport_context_in, in,
203 esw_vport_context.cvlan_id, vlan);
204 }
205
206 MLX5_SET(modify_esw_vport_context_in, in,
207 field_select.vport_cvlan_strip, 1);
208 MLX5_SET(modify_esw_vport_context_in, in,
209 field_select.vport_cvlan_insert, 1);
210
211 return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in));
212}
213
073bb189
SM		 214/* HW L2 Table (MPFS) management */
215static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index,
216 u8 *mac, u8 vlan_valid, u16 vlan)
217{
c4f287c4
SM		 218 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {0};
219 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {0};
073bb189
SM		 220 u8 *in_mac_addr;
221
073bb189
SM		 222 MLX5_SET(set_l2_table_entry_in, in, opcode,
223 MLX5_CMD_OP_SET_L2_TABLE_ENTRY);
224 MLX5_SET(set_l2_table_entry_in, in, table_index, index);
225 MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid);
226 MLX5_SET(set_l2_table_entry_in, in, vlan, vlan);
227
228 in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address);
229 ether_addr_copy(&in_mac_addr[2], mac);
230
c4f287c4 231 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 232}
233
234static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index)
235{
c4f287c4
SM		 236 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {0};
237 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {0};
073bb189
SM		 238
239 MLX5_SET(delete_l2_table_entry_in, in, opcode,
240 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
241 MLX5_SET(delete_l2_table_entry_in, in, table_index, index);
c4f287c4 242 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 243}
244
245static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix)
246{
247 int err = 0;
248
249 *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size);
250 if (*ix >= l2_table->size)
251 err = -ENOSPC;
252 else
253 __set_bit(*ix, l2_table->bitmap);
254
255 return err;
256}
257
258static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix)
259{
260 __clear_bit(ix, l2_table->bitmap);
261}
262
263static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac,
264 u8 vlan_valid, u16 vlan,
265 u32 *index)
266{
267 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
268 int err;
269
270 err = alloc_l2_table_index(l2_table, index);
271 if (err)
272 return err;
273
274 err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan);
275 if (err)
276 free_l2_table_index(l2_table, *index);
277
278 return err;
279}
280
281static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index)
282{
283 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
284
285 del_l2_table_entry_cmd(dev, index);
286 free_l2_table_index(l2_table, index);
287}
288
81848731
SM		 289/* E-Switch FDB */
290static struct mlx5_flow_rule *
a35f71f2 291__esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule,
78a9199b 292 u8 mac_c[ETH_ALEN], u8 mac_v[ETH_ALEN])
81848731 293{
78a9199b
MHY		 294 int match_header = (is_zero_ether_addr(mac_c) ? 0 :
295 MLX5_MATCH_OUTER_HEADERS);
81848731 296 struct mlx5_flow_rule *flow_rule = NULL;
78a9199b 297 struct mlx5_flow_destination dest;
c5bb1730 298 struct mlx5_flow_spec *spec;
a35f71f2
MHY		 299 void *mv_misc = NULL;
300 void *mc_misc = NULL;
78a9199b
MHY		 301 u8 *dmac_v = NULL;
302 u8 *dmac_c = NULL;
81848731 303
a35f71f2
MHY		 304 if (rx_rule)
305 match_header |= MLX5_MATCH_MISC_PARAMETERS;
c5bb1730
MG		 306
307 spec = mlx5_vzalloc(sizeof(*spec));
308 if (!spec) {
81848731 309 pr_warn("FDB: Failed to alloc match parameters\n");
c5bb1730 310 return NULL;
81848731 311 }
c5bb1730 312 dmac_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
81848731 313 outer_headers.dmac_47_16);
c5bb1730 314 dmac_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
81848731
SM		 315 outer_headers.dmac_47_16);
316
a35f71f2 317 if (match_header & MLX5_MATCH_OUTER_HEADERS) {
78a9199b
MHY		 318 ether_addr_copy(dmac_v, mac_v);
319 ether_addr_copy(dmac_c, mac_c);
320 }
81848731 321
a35f71f2 322 if (match_header & MLX5_MATCH_MISC_PARAMETERS) {
c5bb1730
MG		 323 mv_misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
324 misc_parameters);
325 mc_misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
326 misc_parameters);
a35f71f2
MHY		 327 MLX5_SET(fte_match_set_misc, mv_misc, source_port, UPLINK_VPORT);
328 MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port);
329 }
330
81848731
SM		 331 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
332 dest.vport_num = vport;
333
334 esw_debug(esw->dev,
335 "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n",
336 dmac_v, dmac_c, vport);
c5bb1730 337 spec->match_criteria_enable = match_header;
81848731 338 flow_rule =
c5bb1730 339 mlx5_add_flow_rule(esw->fdb_table.fdb, spec,
81848731
SM		 340 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
341 0, &dest);
3f42ac66 342 if (IS_ERR(flow_rule)) {
81848731
SM		 343 pr_warn(
344 "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n",
345 dmac_v, dmac_c, vport, PTR_ERR(flow_rule));
346 flow_rule = NULL;
347 }
c5bb1730
MG		 348
349 kvfree(spec);
81848731
SM		 350 return flow_rule;
351}
352
78a9199b
MHY		 353static struct mlx5_flow_rule *
354esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport)
355{
356 u8 mac_c[ETH_ALEN];
357
358 eth_broadcast_addr(mac_c);
a35f71f2
MHY		 359 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac);
360}
361
362static struct mlx5_flow_rule *
363esw_fdb_set_vport_allmulti_rule(struct mlx5_eswitch *esw, u32 vport)
364{
365 u8 mac_c[ETH_ALEN];
366 u8 mac_v[ETH_ALEN];
367
368 eth_zero_addr(mac_c);
369 eth_zero_addr(mac_v);
370 mac_c[0] = 0x01;
371 mac_v[0] = 0x01;
372 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac_v);
373}
374
375static struct mlx5_flow_rule *
376esw_fdb_set_vport_promisc_rule(struct mlx5_eswitch *esw, u32 vport)
377{
378 u8 mac_c[ETH_ALEN];
379 u8 mac_v[ETH_ALEN];
380
381 eth_zero_addr(mac_c);
382 eth_zero_addr(mac_v);
383 return __esw_fdb_set_vport_rule(esw, vport, true, mac_c, mac_v);
78a9199b
MHY		 384}
385
6ab36e35 386static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw, int nvports)
81848731 387{
86d722ad 388 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
81848731 389 struct mlx5_core_dev *dev = esw->dev;
86d722ad 390 struct mlx5_flow_namespace *root_ns;
81848731 391 struct mlx5_flow_table *fdb;
86d722ad
MG		 392 struct mlx5_flow_group *g;
393 void *match_criteria;
394 int table_size;
395 u32 *flow_group_in;
81848731 396 u8 *dmac;
86d722ad 397 int err = 0;
81848731
SM		 398
399 esw_debug(dev, "Create FDB log_max_size(%d)\n",
400 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
401
86d722ad
MG		 402 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
403 if (!root_ns) {
404 esw_warn(dev, "Failed to get FDB flow namespace\n");
405 return -ENOMEM;
406 }
81848731 407
86d722ad
MG		 408 flow_group_in = mlx5_vzalloc(inlen);
409 if (!flow_group_in)
410 return -ENOMEM;
411 memset(flow_group_in, 0, inlen);
412
413 table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
d63cd286 414 fdb = mlx5_create_flow_table(root_ns, 0, table_size, 0);
3f42ac66 415 if (IS_ERR(fdb)) {
86d722ad
MG		 416 err = PTR_ERR(fdb);
417 esw_warn(dev, "Failed to create FDB Table err %d\n", err);
418 goto out;
419 }
78a9199b 420 esw->fdb_table.fdb = fdb;
81848731 421
78a9199b 422 /* Addresses group : Full match unicast/multicast addresses */
86d722ad
MG		 423 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
424 MLX5_MATCH_OUTER_HEADERS);
425 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
426 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16);
427 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
78a9199b
MHY		 428 /* Preserve 2 entries for allmulti and promisc rules*/
429 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 3);
86d722ad 430 eth_broadcast_addr(dmac);
86d722ad 431 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 432 if (IS_ERR(g)) {
86d722ad
MG		 433 err = PTR_ERR(g);
434 esw_warn(dev, "Failed to create flow group err(%d)\n", err);
435 goto out;
436 }
6ab36e35 437 esw->fdb_table.legacy.addr_grp = g;
78a9199b
MHY		 438
439 /* Allmulti group : One rule that forwards any mcast traffic */
440 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
441 MLX5_MATCH_OUTER_HEADERS);
442 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 2);
443 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 2);
444 eth_zero_addr(dmac);
445 dmac[0] = 0x01;
446 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 447 if (IS_ERR(g)) {
78a9199b
MHY		 448 err = PTR_ERR(g);
449 esw_warn(dev, "Failed to create allmulti flow group err(%d)\n", err);
450 goto out;
451 }
6ab36e35 452 esw->fdb_table.legacy.allmulti_grp = g;
78a9199b
MHY		 453
454 /* Promiscuous group :
455 * One rule that forward all unmatched traffic from previous groups
456 */
457 eth_zero_addr(dmac);
458 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
459 MLX5_MATCH_MISC_PARAMETERS);
460 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
461 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 1);
462 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1);
463 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 464 if (IS_ERR(g)) {
78a9199b
MHY		 465 err = PTR_ERR(g);
466 esw_warn(dev, "Failed to create promisc flow group err(%d)\n", err);
467 goto out;
468 }
6ab36e35 469 esw->fdb_table.legacy.promisc_grp = g;
78a9199b 470
86d722ad 471out:
78a9199b 472 if (err) {
6ab36e35
OG		 473 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.allmulti_grp)) {
474 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
475 esw->fdb_table.legacy.allmulti_grp = NULL;
78a9199b 476 }
6ab36e35
OG		 477 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.addr_grp)) {
478 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
479 esw->fdb_table.legacy.addr_grp = NULL;
78a9199b
MHY		 480 }
481 if (!IS_ERR_OR_NULL(esw->fdb_table.fdb)) {
482 mlx5_destroy_flow_table(esw->fdb_table.fdb);
483 esw->fdb_table.fdb = NULL;
484 }
485 }
486
3fe3d819 487 kvfree(flow_group_in);
86d722ad 488 return err;
81848731
SM		 489}
490
6ab36e35 491static void esw_destroy_legacy_fdb_table(struct mlx5_eswitch *esw)
81848731
SM		 492{
493 if (!esw->fdb_table.fdb)
494 return;
495
86d722ad 496 esw_debug(esw->dev, "Destroy FDB Table\n");
6ab36e35
OG		 497 mlx5_destroy_flow_group(esw->fdb_table.legacy.promisc_grp);
498 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
499 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
81848731
SM		 500 mlx5_destroy_flow_table(esw->fdb_table.fdb);
501 esw->fdb_table.fdb = NULL;
6ab36e35
OG		 502 esw->fdb_table.legacy.addr_grp = NULL;
503 esw->fdb_table.legacy.allmulti_grp = NULL;
504 esw->fdb_table.legacy.promisc_grp = NULL;
81848731
SM		 505}
506
507/* E-Switch vport UC/MC lists management */
508typedef int (*vport_addr_action)(struct mlx5_eswitch *esw,
509 struct vport_addr *vaddr);
510
511static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
512{
513 struct hlist_head *hash = esw->l2_table.l2_hash;
514 struct esw_uc_addr *esw_uc;
515 u8 *mac = vaddr->node.addr;
516 u32 vport = vaddr->vport;
517 int err;
518
519 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
520 if (esw_uc) {
073bb189
SM		 521 esw_warn(esw->dev,
522 "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n",
81848731 523 mac, vport, esw_uc->vport);
073bb189
SM		 524 return -EEXIST;
525 }
526
81848731
SM		 527 esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL);
528 if (!esw_uc)
073bb189 529 return -ENOMEM;
81848731 530 esw_uc->vport = vport;
073bb189 531
81848731 532 err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index);
073bb189 533 if (err)
81848731
SM		 534 goto abort;
535
69697b6e
OG		 536 /* SRIOV is enabled: Forward UC MAC to vport */
537 if (esw->fdb_table.fdb && esw->mode == SRIOV_LEGACY)
81848731
SM		 538 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
539
540 esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n",
541 vport, mac, esw_uc->table_index, vaddr->flow_rule);
542 return err;
543abort:
544 l2addr_hash_del(esw_uc);
073bb189
SM		 545 return err;
546}
547
81848731 548static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
073bb189 549{
81848731
SM		 550 struct hlist_head *hash = esw->l2_table.l2_hash;
551 struct esw_uc_addr *esw_uc;
552 u8 *mac = vaddr->node.addr;
553 u32 vport = vaddr->vport;
554
555 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
556 if (!esw_uc || esw_uc->vport != vport) {
557 esw_debug(esw->dev,
558 "MAC(%pM) doesn't belong to vport (%d)\n",
559 mac, vport);
560 return -EINVAL;
561 }
562 esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n",
563 vport, mac, esw_uc->table_index, vaddr->flow_rule);
564
565 del_l2_table_entry(esw->dev, esw_uc->table_index);
566
567 if (vaddr->flow_rule)
86d722ad 568 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 569 vaddr->flow_rule = NULL;
570
571 l2addr_hash_del(esw_uc);
572 return 0;
573}
574
a35f71f2
MHY		 575static void update_allmulti_vports(struct mlx5_eswitch *esw,
576 struct vport_addr *vaddr,
577 struct esw_mc_addr *esw_mc)
578{
579 u8 *mac = vaddr->node.addr;
580 u32 vport_idx = 0;
581
582 for (vport_idx = 0; vport_idx < esw->total_vports; vport_idx++) {
583 struct mlx5_vport *vport = &esw->vports[vport_idx];
584 struct hlist_head *vport_hash = vport->mc_list;
585 struct vport_addr *iter_vaddr =
586 l2addr_hash_find(vport_hash,
587 mac,
588 struct vport_addr);
589 if (IS_ERR_OR_NULL(vport->allmulti_rule) ||
590 vaddr->vport == vport_idx)
591 continue;
592 switch (vaddr->action) {
593 case MLX5_ACTION_ADD:
594 if (iter_vaddr)
595 continue;
596 iter_vaddr = l2addr_hash_add(vport_hash, mac,
597 struct vport_addr,
598 GFP_KERNEL);
599 if (!iter_vaddr) {
600 esw_warn(esw->dev,
601 "ALL-MULTI: Failed to add MAC(%pM) to vport[%d] DB\n",
602 mac, vport_idx);
603 continue;
604 }
605 iter_vaddr->vport = vport_idx;
606 iter_vaddr->flow_rule =
607 esw_fdb_set_vport_rule(esw,
608 mac,
609 vport_idx);
62e3c24a 610 iter_vaddr->mc_promisc = true;
a35f71f2
MHY		 611 break;
612 case MLX5_ACTION_DEL:
613 if (!iter_vaddr)
614 continue;
615 mlx5_del_flow_rule(iter_vaddr->flow_rule);
616 l2addr_hash_del(iter_vaddr);
617 break;
618 }
619 }
620}
621
81848731
SM		 622static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
623{
624 struct hlist_head *hash = esw->mc_table;
625 struct esw_mc_addr *esw_mc;
626 u8 *mac = vaddr->node.addr;
627 u32 vport = vaddr->vport;
628
629 if (!esw->fdb_table.fdb)
630 return 0;
631
632 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
633 if (esw_mc)
634 goto add;
635
636 esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL);
637 if (!esw_mc)
638 return -ENOMEM;
639
640 esw_mc->uplink_rule = /* Forward MC MAC to Uplink */
641 esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT);
a35f71f2
MHY		 642
643 /* Add this multicast mac to all the mc promiscuous vports */
644 update_allmulti_vports(esw, vaddr, esw_mc);
645
81848731 646add:
a35f71f2
MHY		 647 /* If the multicast mac is added as a result of mc promiscuous vport,
648 * don't increment the multicast ref count
649 */
650 if (!vaddr->mc_promisc)
651 esw_mc->refcnt++;
652
81848731
SM		 653 /* Forward MC MAC to vport */
654 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
655 esw_debug(esw->dev,
656 "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
657 vport, mac, vaddr->flow_rule,
658 esw_mc->refcnt, esw_mc->uplink_rule);
659 return 0;
660}
661
662static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
663{
664 struct hlist_head *hash = esw->mc_table;
665 struct esw_mc_addr *esw_mc;
666 u8 *mac = vaddr->node.addr;
667 u32 vport = vaddr->vport;
073bb189 668
81848731
SM		 669 if (!esw->fdb_table.fdb)
670 return 0;
671
672 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
673 if (!esw_mc) {
674 esw_warn(esw->dev,
675 "Failed to find eswitch MC addr for MAC(%pM) vport(%d)",
073bb189
SM		 676 mac, vport);
677 return -EINVAL;
678 }
81848731
SM		 679 esw_debug(esw->dev,
680 "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
681 vport, mac, vaddr->flow_rule, esw_mc->refcnt,
682 esw_mc->uplink_rule);
683
684 if (vaddr->flow_rule)
86d722ad 685 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 686 vaddr->flow_rule = NULL;
687
a35f71f2
MHY		 688 /* If the multicast mac is added as a result of mc promiscuous vport,
689 * don't decrement the multicast ref count.
690 */
691 if (vaddr->mc_promisc || (--esw_mc->refcnt > 0))
81848731 692 return 0;
073bb189 693
a35f71f2
MHY		 694 /* Remove this multicast mac from all the mc promiscuous vports */
695 update_allmulti_vports(esw, vaddr, esw_mc);
696
81848731 697 if (esw_mc->uplink_rule)
86d722ad 698 mlx5_del_flow_rule(esw_mc->uplink_rule);
81848731
SM		 699
700 l2addr_hash_del(esw_mc);
073bb189
SM		 701 return 0;
702}
703
81848731
SM		 704/* Apply vport UC/MC list to HW l2 table and FDB table */
705static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw,
706 u32 vport_num, int list_type)
073bb189
SM		 707{
708 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731
SM		 709 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
710 vport_addr_action vport_addr_add;
711 vport_addr_action vport_addr_del;
712 struct vport_addr *addr;
073bb189
SM		 713 struct l2addr_node *node;
714 struct hlist_head *hash;
715 struct hlist_node *tmp;
716 int hi;
717
81848731
SM		 718 vport_addr_add = is_uc ? esw_add_uc_addr :
719 esw_add_mc_addr;
720 vport_addr_del = is_uc ? esw_del_uc_addr :
721 esw_del_mc_addr;
722
723 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189 724 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 725 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 726 switch (addr->action) {
727 case MLX5_ACTION_ADD:
81848731 728 vport_addr_add(esw, addr);
073bb189
SM		 729 addr->action = MLX5_ACTION_NONE;
730 break;
731 case MLX5_ACTION_DEL:
81848731 732 vport_addr_del(esw, addr);
073bb189
SM		 733 l2addr_hash_del(addr);
734 break;
735 }
736 }
737}
738
81848731
SM		 739/* Sync vport UC/MC list from vport context */
740static void esw_update_vport_addr_list(struct mlx5_eswitch *esw,
741 u32 vport_num, int list_type)
073bb189
SM		 742{
743 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731 744 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
073bb189 745 u8 (*mac_list)[ETH_ALEN];
81848731
SM		 746 struct l2addr_node *node;
747 struct vport_addr *addr;
073bb189
SM		 748 struct hlist_head *hash;
749 struct hlist_node *tmp;
750 int size;
751 int err;
752 int hi;
753 int i;
754
81848731
SM		 755 size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) :
756 MLX5_MAX_MC_PER_VPORT(esw->dev);
073bb189
SM		 757
758 mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL);
759 if (!mac_list)
760 return;
761
81848731 762 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189
SM		 763
764 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 765 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 766 addr->action = MLX5_ACTION_DEL;
767 }
768
586cfa7f
MHY		 769 if (!vport->enabled)
770 goto out;
771
81848731 772 err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type,
073bb189
SM		 773 mac_list, &size);
774 if (err)
761e205b 775 goto out;
81848731
SM		 776 esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n",
777 vport_num, is_uc ? "UC" : "MC", size);
073bb189
SM		 778
779 for (i = 0; i < size; i++) {
81848731 780 if (is_uc && !is_valid_ether_addr(mac_list[i]))
073bb189
SM		 781 continue;
782
81848731
SM		 783 if (!is_uc && !is_multicast_ether_addr(mac_list[i]))
784 continue;
785
786 addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr);
073bb189
SM		 787 if (addr) {
788 addr->action = MLX5_ACTION_NONE;
a35f71f2
MHY		 789 /* If this mac was previously added because of allmulti
790 * promiscuous rx mode, its now converted to be original
791 * vport mac.
792 */
793 if (addr->mc_promisc) {
794 struct esw_mc_addr *esw_mc =
795 l2addr_hash_find(esw->mc_table,
796 mac_list[i],
797 struct esw_mc_addr);
798 if (!esw_mc) {
799 esw_warn(esw->dev,
800 "Failed to MAC(%pM) in mcast DB\n",
801 mac_list[i]);
802 continue;
803 }
804 esw_mc->refcnt++;
805 addr->mc_promisc = false;
806 }
073bb189
SM		 807 continue;
808 }
809
81848731 810 addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr,
073bb189
SM		 811 GFP_KERNEL);
812 if (!addr) {
813 esw_warn(esw->dev,
814 "Failed to add MAC(%pM) to vport[%d] DB\n",
815 mac_list[i], vport_num);
816 continue;
817 }
81848731 818 addr->vport = vport_num;
073bb189
SM		 819 addr->action = MLX5_ACTION_ADD;
820 }
761e205b 821out:
073bb189
SM		 822 kfree(mac_list);
823}
824
a35f71f2
MHY		 825/* Sync vport UC/MC list from vport context
826 * Must be called after esw_update_vport_addr_list
827 */
828static void esw_update_vport_mc_promisc(struct mlx5_eswitch *esw, u32 vport_num)
829{
830 struct mlx5_vport *vport = &esw->vports[vport_num];
831 struct l2addr_node *node;
832 struct vport_addr *addr;
833 struct hlist_head *hash;
834 struct hlist_node *tmp;
835 int hi;
836
837 hash = vport->mc_list;
838
839 for_each_l2hash_node(node, tmp, esw->mc_table, hi) {
840 u8 *mac = node->addr;
841
842 addr = l2addr_hash_find(hash, mac, struct vport_addr);
843 if (addr) {
844 if (addr->action == MLX5_ACTION_DEL)
845 addr->action = MLX5_ACTION_NONE;
846 continue;
847 }
848 addr = l2addr_hash_add(hash, mac, struct vport_addr,
849 GFP_KERNEL);
850 if (!addr) {
851 esw_warn(esw->dev,
852 "Failed to add allmulti MAC(%pM) to vport[%d] DB\n",
853 mac, vport_num);
854 continue;
855 }
856 addr->vport = vport_num;
857 addr->action = MLX5_ACTION_ADD;
858 addr->mc_promisc = true;
859 }
860}
861
862/* Apply vport rx mode to HW FDB table */
863static void esw_apply_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num,
864 bool promisc, bool mc_promisc)
865{
866 struct esw_mc_addr *allmulti_addr = esw->mc_promisc;
867 struct mlx5_vport *vport = &esw->vports[vport_num];
868
869 if (IS_ERR_OR_NULL(vport->allmulti_rule) != mc_promisc)
870 goto promisc;
871
872 if (mc_promisc) {
873 vport->allmulti_rule =
874 esw_fdb_set_vport_allmulti_rule(esw, vport_num);
875 if (!allmulti_addr->uplink_rule)
876 allmulti_addr->uplink_rule =
877 esw_fdb_set_vport_allmulti_rule(esw,
878 UPLINK_VPORT);
879 allmulti_addr->refcnt++;
880 } else if (vport->allmulti_rule) {
881 mlx5_del_flow_rule(vport->allmulti_rule);
882 vport->allmulti_rule = NULL;
883
884 if (--allmulti_addr->refcnt > 0)
885 goto promisc;
886
887 if (allmulti_addr->uplink_rule)
888 mlx5_del_flow_rule(allmulti_addr->uplink_rule);
889 allmulti_addr->uplink_rule = NULL;
890 }
891
892promisc:
893 if (IS_ERR_OR_NULL(vport->promisc_rule) != promisc)
894 return;
895
896 if (promisc) {
897 vport->promisc_rule = esw_fdb_set_vport_promisc_rule(esw,
898 vport_num);
899 } else if (vport->promisc_rule) {
900 mlx5_del_flow_rule(vport->promisc_rule);
901 vport->promisc_rule = NULL;
902 }
903}
904
905/* Sync vport rx mode from vport context */
906static void esw_update_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num)
907{
908 struct mlx5_vport *vport = &esw->vports[vport_num];
909 int promisc_all = 0;
910 int promisc_uc = 0;
911 int promisc_mc = 0;
912 int err;
913
914 err = mlx5_query_nic_vport_promisc(esw->dev,
915 vport_num,
916 &promisc_uc,
917 &promisc_mc,
918 &promisc_all);
919 if (err)
920 return;
921 esw_debug(esw->dev, "vport[%d] context update rx mode promisc_all=%d, all_multi=%d\n",
922 vport_num, promisc_all, promisc_mc);
923
924 if (!vport->trusted || !vport->enabled) {
925 promisc_uc = 0;
926 promisc_mc = 0;
927 promisc_all = 0;
928 }
929
930 esw_apply_vport_rx_mode(esw, vport_num, promisc_all,
931 (promisc_all || promisc_mc));
932}
933
1edc57e2 934static void esw_vport_change_handle_locked(struct mlx5_vport *vport)
073bb189 935{
073bb189 936 struct mlx5_core_dev *dev = vport->dev;
81848731 937 struct mlx5_eswitch *esw = dev->priv.eswitch;
073bb189
SM		 938 u8 mac[ETH_ALEN];
939
940 mlx5_query_nic_vport_mac_address(dev, vport->vport, mac);
81848731
SM		 941 esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n",
942 vport->vport, mac);
943
944 if (vport->enabled_events & UC_ADDR_CHANGE) {
945 esw_update_vport_addr_list(esw, vport->vport,
946 MLX5_NVPRT_LIST_TYPE_UC);
947 esw_apply_vport_addr_list(esw, vport->vport,
948 MLX5_NVPRT_LIST_TYPE_UC);
949 }
073bb189 950
81848731
SM		 951 if (vport->enabled_events & MC_ADDR_CHANGE) {
952 esw_update_vport_addr_list(esw, vport->vport,
953 MLX5_NVPRT_LIST_TYPE_MC);
a35f71f2
MHY		 954 }
955
956 if (vport->enabled_events & PROMISC_CHANGE) {
957 esw_update_vport_rx_mode(esw, vport->vport);
958 if (!IS_ERR_OR_NULL(vport->allmulti_rule))
959 esw_update_vport_mc_promisc(esw, vport->vport);
960 }
961
962 if (vport->enabled_events & (PROMISC_CHANGE | MC_ADDR_CHANGE)) {
81848731
SM		 963 esw_apply_vport_addr_list(esw, vport->vport,
964 MLX5_NVPRT_LIST_TYPE_MC);
965 }
073bb189 966
81848731 967 esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport);
073bb189
SM		 968 if (vport->enabled)
969 arm_vport_context_events_cmd(dev, vport->vport,
81848731 970 vport->enabled_events);
073bb189
SM		 971}
972
1edc57e2
MHY		 973static void esw_vport_change_handler(struct work_struct *work)
974{
975 struct mlx5_vport *vport =
976 container_of(work, struct mlx5_vport, vport_change_handler);
977 struct mlx5_eswitch *esw = vport->dev->priv.eswitch;
978
979 mutex_lock(&esw->state_lock);
980 esw_vport_change_handle_locked(vport);
981 mutex_unlock(&esw->state_lock);
982}
983
5742df0f
MHY		 984static void esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
985 struct mlx5_vport *vport)
986{
987 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
988 struct mlx5_flow_group *vlan_grp = NULL;
989 struct mlx5_flow_group *drop_grp = NULL;
990 struct mlx5_core_dev *dev = esw->dev;
991 struct mlx5_flow_namespace *root_ns;
992 struct mlx5_flow_table *acl;
993 void *match_criteria;
994 u32 *flow_group_in;
995 /* The egress acl table contains 2 rules:
996 * 1)Allow traffic with vlan_tag=vst_vlan_id
997 * 2)Drop all other traffic.
998 */
999 int table_size = 2;
1000 int err = 0;
1001
01f51f22
MHY		 1002 if (!MLX5_CAP_ESW_EGRESS_ACL(dev, ft_support) ||
1003 !IS_ERR_OR_NULL(vport->egress.acl))
5742df0f
MHY		 1004 return;
1005
1006 esw_debug(dev, "Create vport[%d] egress ACL log_max_size(%d)\n",
1007 vport->vport, MLX5_CAP_ESW_EGRESS_ACL(dev, log_max_ft_size));
1008
1009 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_EGRESS);
1010 if (!root_ns) {
1011 esw_warn(dev, "Failed to get E-Switch egress flow namespace\n");
1012 return;
1013 }
1014
1015 flow_group_in = mlx5_vzalloc(inlen);
1016 if (!flow_group_in)
1017 return;
1018
1019 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1020 if (IS_ERR(acl)) {
5742df0f
MHY		 1021 err = PTR_ERR(acl);
1022 esw_warn(dev, "Failed to create E-Switch vport[%d] egress flow Table, err(%d)\n",
1023 vport->vport, err);
1024 goto out;
1025 }
1026
1027 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1028 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1029 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1030 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);
1031 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1032 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1033
1034 vlan_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1035 if (IS_ERR(vlan_grp)) {
5742df0f
MHY		 1036 err = PTR_ERR(vlan_grp);
1037 esw_warn(dev, "Failed to create E-Switch vport[%d] egress allowed vlans flow group, err(%d)\n",
1038 vport->vport, err);
1039 goto out;
1040 }
1041
1042 memset(flow_group_in, 0, inlen);
1043 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1044 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1045 drop_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1046 if (IS_ERR(drop_grp)) {
5742df0f
MHY		 1047 err = PTR_ERR(drop_grp);
1048 esw_warn(dev, "Failed to create E-Switch vport[%d] egress drop flow group, err(%d)\n",
1049 vport->vport, err);
1050 goto out;
1051 }
1052
1053 vport->egress.acl = acl;
1054 vport->egress.drop_grp = drop_grp;
1055 vport->egress.allowed_vlans_grp = vlan_grp;
1056out:
3fe3d819 1057 kvfree(flow_group_in);
5742df0f
MHY		 1058 if (err && !IS_ERR_OR_NULL(vlan_grp))
1059 mlx5_destroy_flow_group(vlan_grp);
1060 if (err && !IS_ERR_OR_NULL(acl))
1061 mlx5_destroy_flow_table(acl);
1062}
1063
dfcb1ed3
MHY		 1064static void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
1065 struct mlx5_vport *vport)
1066{
1067 if (!IS_ERR_OR_NULL(vport->egress.allowed_vlan))
1068 mlx5_del_flow_rule(vport->egress.allowed_vlan);
1069
1070 if (!IS_ERR_OR_NULL(vport->egress.drop_rule))
1071 mlx5_del_flow_rule(vport->egress.drop_rule);
1072
1073 vport->egress.allowed_vlan = NULL;
1074 vport->egress.drop_rule = NULL;
1075}
1076
5742df0f
MHY		 1077static void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
1078 struct mlx5_vport *vport)
1079{
1080 if (IS_ERR_OR_NULL(vport->egress.acl))
1081 return;
1082
1083 esw_debug(esw->dev, "Destroy vport[%d] E-Switch egress ACL\n", vport->vport);
1084
dfcb1ed3 1085 esw_vport_cleanup_egress_rules(esw, vport);
5742df0f
MHY		 1086 mlx5_destroy_flow_group(vport->egress.allowed_vlans_grp);
1087 mlx5_destroy_flow_group(vport->egress.drop_grp);
1088 mlx5_destroy_flow_table(vport->egress.acl);
1089 vport->egress.allowed_vlans_grp = NULL;
1090 vport->egress.drop_grp = NULL;
1091 vport->egress.acl = NULL;
1092}
1093
1094static void esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
1095 struct mlx5_vport *vport)
1096{
1097 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1098 struct mlx5_core_dev *dev = esw->dev;
1099 struct mlx5_flow_namespace *root_ns;
1100 struct mlx5_flow_table *acl;
1101 struct mlx5_flow_group *g;
1102 void *match_criteria;
1103 u32 *flow_group_in;
1104 /* The ingress acl table contains 4 groups
1105 * (2 active rules at the same time -
1106 * 1 allow rule from one of the first 3 groups.
1107 * 1 drop rule from the last group):
1108 * 1)Allow untagged traffic with smac=original mac.
1109 * 2)Allow untagged traffic.
1110 * 3)Allow traffic with smac=original mac.
1111 * 4)Drop all other traffic.
1112 */
1113 int table_size = 4;
1114 int err = 0;
1115
01f51f22
MHY		 1116 if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support) ||
1117 !IS_ERR_OR_NULL(vport->ingress.acl))
5742df0f
MHY		 1118 return;
1119
1120 esw_debug(dev, "Create vport[%d] ingress ACL log_max_size(%d)\n",
1121 vport->vport, MLX5_CAP_ESW_INGRESS_ACL(dev, log_max_ft_size));
1122
1123 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS);
1124 if (!root_ns) {
1125 esw_warn(dev, "Failed to get E-Switch ingress flow namespace\n");
1126 return;
1127 }
1128
1129 flow_group_in = mlx5_vzalloc(inlen);
1130 if (!flow_group_in)
1131 return;
1132
1133 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1134 if (IS_ERR(acl)) {
5742df0f
MHY		 1135 err = PTR_ERR(acl);
1136 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress flow Table, err(%d)\n",
1137 vport->vport, err);
1138 goto out;
1139 }
1140 vport->ingress.acl = acl;
1141
1142 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1143
1144 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1145 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1146 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1147 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1148 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1149 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1150
1151 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1152 if (IS_ERR(g)) {
5742df0f
MHY		 1153 err = PTR_ERR(g);
1154 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged spoofchk flow group, err(%d)\n",
1155 vport->vport, err);
1156 goto out;
1157 }
1158 vport->ingress.allow_untagged_spoofchk_grp = g;
1159
1160 memset(flow_group_in, 0, inlen);
1161 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1162 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1163 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1164 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1165
1166 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1167 if (IS_ERR(g)) {
5742df0f
MHY		 1168 err = PTR_ERR(g);
1169 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged flow group, err(%d)\n",
1170 vport->vport, err);
1171 goto out;
1172 }
1173 vport->ingress.allow_untagged_only_grp = g;
1174
1175 memset(flow_group_in, 0, inlen);
1176 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1177 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1178 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1179 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 2);
1180 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 2);
1181
1182 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1183 if (IS_ERR(g)) {
5742df0f
MHY		 1184 err = PTR_ERR(g);
1185 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress spoofchk flow group, err(%d)\n",
1186 vport->vport, err);
1187 goto out;
1188 }
1189 vport->ingress.allow_spoofchk_only_grp = g;
1190
1191 memset(flow_group_in, 0, inlen);
1192 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 3);
1193 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 3);
1194
1195 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1196 if (IS_ERR(g)) {
5742df0f
MHY		 1197 err = PTR_ERR(g);
1198 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress drop flow group, err(%d)\n",
1199 vport->vport, err);
1200 goto out;
1201 }
1202 vport->ingress.drop_grp = g;
1203
1204out:
1205 if (err) {
1206 if (!IS_ERR_OR_NULL(vport->ingress.allow_spoofchk_only_grp))
1207 mlx5_destroy_flow_group(
1208 vport->ingress.allow_spoofchk_only_grp);
1209 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_only_grp))
1210 mlx5_destroy_flow_group(
1211 vport->ingress.allow_untagged_only_grp);
1212 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_spoofchk_grp))
1213 mlx5_destroy_flow_group(
1214 vport->ingress.allow_untagged_spoofchk_grp);
1215 if (!IS_ERR_OR_NULL(vport->ingress.acl))
1216 mlx5_destroy_flow_table(vport->ingress.acl);
1217 }
1218
3fe3d819 1219 kvfree(flow_group_in);
5742df0f
MHY		 1220}
1221
dfcb1ed3
MHY		 1222static void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
1223 struct mlx5_vport *vport)
1224{
1225 if (!IS_ERR_OR_NULL(vport->ingress.drop_rule))
1226 mlx5_del_flow_rule(vport->ingress.drop_rule);
f942380c
MHY		 1227
1228 if (!IS_ERR_OR_NULL(vport->ingress.allow_rule))
1229 mlx5_del_flow_rule(vport->ingress.allow_rule);
1230
dfcb1ed3 1231 vport->ingress.drop_rule = NULL;
f942380c 1232 vport->ingress.allow_rule = NULL;
dfcb1ed3
MHY		 1233}
1234
5742df0f
MHY		 1235static void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
1236 struct mlx5_vport *vport)
1237{
1238 if (IS_ERR_OR_NULL(vport->ingress.acl))
1239 return;
1240
1241 esw_debug(esw->dev, "Destroy vport[%d] E-Switch ingress ACL\n", vport->vport);
1242
dfcb1ed3 1243 esw_vport_cleanup_ingress_rules(esw, vport);
5742df0f
MHY		 1244 mlx5_destroy_flow_group(vport->ingress.allow_spoofchk_only_grp);
1245 mlx5_destroy_flow_group(vport->ingress.allow_untagged_only_grp);
1246 mlx5_destroy_flow_group(vport->ingress.allow_untagged_spoofchk_grp);
1247 mlx5_destroy_flow_group(vport->ingress.drop_grp);
1248 mlx5_destroy_flow_table(vport->ingress.acl);
1249 vport->ingress.acl = NULL;
1250 vport->ingress.drop_grp = NULL;
1251 vport->ingress.allow_spoofchk_only_grp = NULL;
1252 vport->ingress.allow_untagged_only_grp = NULL;
1253 vport->ingress.allow_untagged_spoofchk_grp = NULL;
1254}
1255
dfcb1ed3
MHY		 1256static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
1257 struct mlx5_vport *vport)
1258{
c5bb1730 1259 struct mlx5_flow_spec *spec;
f942380c 1260 u8 smac[ETH_ALEN];
dfcb1ed3 1261 int err = 0;
f942380c 1262 u8 *smac_v;
dfcb1ed3 1263
f942380c
MHY		 1264 if (vport->spoofchk) {
1265 err = mlx5_query_nic_vport_mac_address(esw->dev, vport->vport, smac);
1266 if (err) {
1267 esw_warn(esw->dev,
1268 "vport[%d] configure ingress rules failed, query smac failed, err(%d)\n",
1269 vport->vport, err);
1270 return err;
1271 }
1272
1273 if (!is_valid_ether_addr(smac)) {
1274 mlx5_core_warn(esw->dev,
1275 "vport[%d] configure ingress rules failed, illegal mac with spoofchk\n",
1276 vport->vport);
1277 return -EPERM;
1278 }
1279 }
1280
dfcb1ed3
MHY		 1281 esw_vport_cleanup_ingress_rules(esw, vport);
1282
01f51f22
MHY		 1283 if (!vport->vlan && !vport->qos && !vport->spoofchk) {
1284 esw_vport_disable_ingress_acl(esw, vport);
dfcb1ed3 1285 return 0;
01f51f22
MHY		 1286 }
1287
1288 esw_vport_enable_ingress_acl(esw, vport);
dfcb1ed3
MHY		 1289
1290 esw_debug(esw->dev,
1291 "vport[%d] configure ingress rules, vlan(%d) qos(%d)\n",
1292 vport->vport, vport->vlan, vport->qos);
1293
c5bb1730
MG		 1294 spec = mlx5_vzalloc(sizeof(*spec));
1295 if (!spec) {
dfcb1ed3
MHY		 1296 err = -ENOMEM;
1297 esw_warn(esw->dev, "vport[%d] configure ingress rules failed, err(%d)\n",
1298 vport->vport, err);
1299 goto out;
1300 }
dfcb1ed3 1301
f942380c 1302 if (vport->vlan || vport->qos)
c5bb1730 1303 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);
f942380c
MHY		 1304
1305 if (vport->spoofchk) {
c5bb1730
MG		 1306 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_47_16);
1307 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_15_0);
f942380c 1308 smac_v = MLX5_ADDR_OF(fte_match_param,
c5bb1730 1309 spec->match_value,
f942380c
MHY		 1310 outer_headers.smac_47_16);
1311 ether_addr_copy(smac_v, smac);
1312 }
1313
c5bb1730 1314 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
f942380c 1315 vport->ingress.allow_rule =
c5bb1730 1316 mlx5_add_flow_rule(vport->ingress.acl, spec,
f942380c
MHY		 1317 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1318 0, NULL);
3f42ac66 1319 if (IS_ERR(vport->ingress.allow_rule)) {
f942380c
MHY		 1320 err = PTR_ERR(vport->ingress.allow_rule);
1321 pr_warn("vport[%d] configure ingress allow rule, err(%d)\n",
1322 vport->vport, err);
1323 vport->ingress.allow_rule = NULL;
1324 goto out;
1325 }
1326
c5bb1730 1327 memset(spec, 0, sizeof(*spec));
f942380c 1328 vport->ingress.drop_rule =
c5bb1730 1329 mlx5_add_flow_rule(vport->ingress.acl, spec,
dfcb1ed3
MHY		 1330 MLX5_FLOW_CONTEXT_ACTION_DROP,
1331 0, NULL);
3f42ac66 1332 if (IS_ERR(vport->ingress.drop_rule)) {
dfcb1ed3 1333 err = PTR_ERR(vport->ingress.drop_rule);
f942380c 1334 pr_warn("vport[%d] configure ingress drop rule, err(%d)\n",
dfcb1ed3
MHY		 1335 vport->vport, err);
1336 vport->ingress.drop_rule = NULL;
f942380c 1337 goto out;
dfcb1ed3 1338 }
f942380c 1339
dfcb1ed3 1340out:
f942380c
MHY		 1341 if (err)
1342 esw_vport_cleanup_ingress_rules(esw, vport);
c5bb1730 1343 kvfree(spec);
dfcb1ed3
MHY		 1344 return err;
1345}
1346
1347static int esw_vport_egress_config(struct mlx5_eswitch *esw,
1348 struct mlx5_vport *vport)
1349{
c5bb1730 1350 struct mlx5_flow_spec *spec;
dfcb1ed3
MHY		 1351 int err = 0;
1352
dfcb1ed3
MHY		 1353 esw_vport_cleanup_egress_rules(esw, vport);
1354
01f51f22
MHY		 1355 if (!vport->vlan && !vport->qos) {
1356 esw_vport_disable_egress_acl(esw, vport);
dfcb1ed3 1357 return 0;
01f51f22
MHY		 1358 }
1359
1360 esw_vport_enable_egress_acl(esw, vport);
dfcb1ed3
MHY		 1361
1362 esw_debug(esw->dev,
1363 "vport[%d] configure egress rules, vlan(%d) qos(%d)\n",
1364 vport->vport, vport->vlan, vport->qos);
1365
c5bb1730
MG		 1366 spec = mlx5_vzalloc(sizeof(*spec));
1367 if (!spec) {
dfcb1ed3
MHY		 1368 err = -ENOMEM;
1369 esw_warn(esw->dev, "vport[%d] configure egress rules failed, err(%d)\n",
1370 vport->vport, err);
1371 goto out;
1372 }
1373
1374 /* Allowed vlan rule */
c5bb1730
MG		 1375 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);
1376 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.vlan_tag);
1377 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
1378 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vport->vlan);
dfcb1ed3 1379
c5bb1730 1380 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
dfcb1ed3 1381 vport->egress.allowed_vlan =
c5bb1730 1382 mlx5_add_flow_rule(vport->egress.acl, spec,
dfcb1ed3
MHY		 1383 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1384 0, NULL);
3f42ac66 1385 if (IS_ERR(vport->egress.allowed_vlan)) {
dfcb1ed3
MHY		 1386 err = PTR_ERR(vport->egress.allowed_vlan);
1387 pr_warn("vport[%d] configure egress allowed vlan rule failed, err(%d)\n",
1388 vport->vport, err);
1389 vport->egress.allowed_vlan = NULL;
1390 goto out;
1391 }
1392
1393 /* Drop others rule (star rule) */
c5bb1730 1394 memset(spec, 0, sizeof(*spec));
dfcb1ed3 1395 vport->egress.drop_rule =
c5bb1730 1396 mlx5_add_flow_rule(vport->egress.acl, spec,
dfcb1ed3
MHY		 1397 MLX5_FLOW_CONTEXT_ACTION_DROP,
1398 0, NULL);
3f42ac66 1399 if (IS_ERR(vport->egress.drop_rule)) {
dfcb1ed3
MHY		 1400 err = PTR_ERR(vport->egress.drop_rule);
1401 pr_warn("vport[%d] configure egress drop rule failed, err(%d)\n",
1402 vport->vport, err);
1403 vport->egress.drop_rule = NULL;
1404 }
1405out:
c5bb1730 1406 kvfree(spec);
dfcb1ed3
MHY		 1407 return err;
1408}
1409
81848731
SM		 1410static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
1411 int enable_events)
073bb189
SM		 1412{
1413 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189 1414
dfcb1ed3 1415 mutex_lock(&esw->state_lock);
81848731
SM		 1416 WARN_ON(vport->enabled);
1417
1418 esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
5742df0f
MHY		 1419
1420 if (vport_num) { /* Only VFs need ACLs for VST and spoofchk filtering */
dfcb1ed3
MHY		 1421 esw_vport_ingress_config(esw, vport);
1422 esw_vport_egress_config(esw, vport);
5742df0f
MHY		 1423 }
1424
81848731
SM		 1425 mlx5_modify_vport_admin_state(esw->dev,
1426 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1427 vport_num,
1428 MLX5_ESW_VPORT_ADMIN_STATE_AUTO);
1429
1430 /* Sync with current vport context */
1431 vport->enabled_events = enable_events;
073bb189 1432 vport->enabled = true;
073bb189 1433
a35f71f2
MHY		 1434 /* only PF is trusted by default */
1435 vport->trusted = (vport_num) ? false : true;
25fff58c 1436 esw_vport_change_handle_locked(vport);
81848731
SM		 1437
1438 esw->enabled_vports++;
1439 esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num);
dfcb1ed3 1440 mutex_unlock(&esw->state_lock);
81848731
SM		 1441}
1442
073bb189
SM		 1443static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
1444{
1445 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189
SM		 1446
1447 if (!vport->enabled)
1448 return;
1449
81848731 1450 esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num);
073bb189 1451 /* Mark this vport as disabled to discard new events */
073bb189 1452 vport->enabled = false;
831cae1d
MHY		 1453
1454 synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC));
073bb189 1455
81848731
SM		 1456 mlx5_modify_vport_admin_state(esw->dev,
1457 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1458 vport_num,
1459 MLX5_ESW_VPORT_ADMIN_STATE_DOWN);
073bb189
SM		 1460 /* Wait for current already scheduled events to complete */
1461 flush_workqueue(esw->work_queue);
073bb189
SM		 1462 /* Disable events from this vport */
1463 arm_vport_context_events_cmd(esw->dev, vport->vport, 0);
dfcb1ed3 1464 mutex_lock(&esw->state_lock);
586cfa7f
MHY		 1465 /* We don't assume VFs will cleanup after themselves.
1466 * Calling vport change handler while vport is disabled will cleanup
1467 * the vport resources.
1468 */
1edc57e2 1469 esw_vport_change_handle_locked(vport);
586cfa7f 1470 vport->enabled_events = 0;
5742df0f
MHY		 1471 if (vport_num) {
1472 esw_vport_disable_egress_acl(esw, vport);
1473 esw_vport_disable_ingress_acl(esw, vport);
1474 }
81848731 1475 esw->enabled_vports--;
dfcb1ed3 1476 mutex_unlock(&esw->state_lock);
073bb189
SM		 1477}
1478
1479/* Public E-Switch API */
6ab36e35 1480int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode)
81848731
SM		 1481{
1482 int err;
69697b6e 1483 int i, enabled_events;
81848731
SM		 1484
1485 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1486 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1487 return 0;
1488
1489 if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) ||
1490 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) {
1491 esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n");
1492 return -ENOTSUPP;
1493 }
1494
5742df0f
MHY		 1495 if (!MLX5_CAP_ESW_INGRESS_ACL(esw->dev, ft_support))
1496 esw_warn(esw->dev, "E-Switch ingress ACL is not supported by FW\n");
1497
1498 if (!MLX5_CAP_ESW_EGRESS_ACL(esw->dev, ft_support))
1499 esw_warn(esw->dev, "E-Switch engress ACL is not supported by FW\n");
1500
6ab36e35 1501 esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d) mode (%d)\n", nvfs, mode);
6ab36e35 1502 esw->mode = mode;
81848731
SM		 1503 esw_disable_vport(esw, 0);
1504
69697b6e
OG		 1505 if (mode == SRIOV_LEGACY)
1506 err = esw_create_legacy_fdb_table(esw, nvfs + 1);
1507 else
c930a3ad 1508 err = esw_offloads_init(esw, nvfs + 1);
81848731
SM		 1509 if (err)
1510 goto abort;
1511
69697b6e 1512 enabled_events = (mode == SRIOV_LEGACY) ? SRIOV_VPORT_EVENTS : UC_ADDR_CHANGE;
81848731 1513 for (i = 0; i <= nvfs; i++)
69697b6e 1514 esw_enable_vport(esw, i, enabled_events);
81848731
SM		 1515
1516 esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n",
1517 esw->enabled_vports);
1518 return 0;
1519
1520abort:
1521 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1522 return err;
1523}
1524
1525void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
1526{
a35f71f2 1527 struct esw_mc_addr *mc_promisc;
c930a3ad 1528 int nvports;
81848731
SM		 1529 int i;
1530
1531 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1532 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1533 return;
1534
6ab36e35
OG		 1535 esw_info(esw->dev, "disable SRIOV: active vports(%d) mode(%d)\n",
1536 esw->enabled_vports, esw->mode);
81848731 1537
a35f71f2 1538 mc_promisc = esw->mc_promisc;
c930a3ad 1539 nvports = esw->enabled_vports;
a35f71f2 1540
81848731
SM		 1541 for (i = 0; i < esw->total_vports; i++)
1542 esw_disable_vport(esw, i);
1543
a35f71f2
MHY		 1544 if (mc_promisc && mc_promisc->uplink_rule)
1545 mlx5_del_flow_rule(mc_promisc->uplink_rule);
1546
69697b6e
OG		 1547 if (esw->mode == SRIOV_LEGACY)
1548 esw_destroy_legacy_fdb_table(esw);
c930a3ad
OG		 1549 else if (esw->mode == SRIOV_OFFLOADS)
1550 esw_offloads_cleanup(esw, nvports);
81848731 1551
6ab36e35 1552 esw->mode = SRIOV_NONE;
81848731
SM		 1553 /* VPORT 0 (PF) must be enabled back with non-sriov configuration */
1554 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1555}
1556
073bb189
SM		 1557int mlx5_eswitch_init(struct mlx5_core_dev *dev)
1558{
1559 int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table);
efdc810b 1560 int total_vports = MLX5_TOTAL_VPORTS(dev);
a35f71f2 1561 struct esw_mc_addr *mc_promisc;
073bb189
SM		 1562 struct mlx5_eswitch *esw;
1563 int vport_num;
1564 int err;
1565
1566 if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
1567 MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1568 return 0;
1569
1570 esw_info(dev,
1571 "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n",
1572 total_vports, l2_table_size,
1573 MLX5_MAX_UC_PER_VPORT(dev),
1574 MLX5_MAX_MC_PER_VPORT(dev));
1575
1576 esw = kzalloc(sizeof(*esw), GFP_KERNEL);
1577 if (!esw)
1578 return -ENOMEM;
1579
1580 esw->dev = dev;
1581
1582 esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size),
1583 sizeof(uintptr_t), GFP_KERNEL);
1584 if (!esw->l2_table.bitmap) {
1585 err = -ENOMEM;
1586 goto abort;
1587 }
1588 esw->l2_table.size = l2_table_size;
1589
a35f71f2
MHY		 1590 mc_promisc = kzalloc(sizeof(*mc_promisc), GFP_KERNEL);
1591 if (!mc_promisc) {
1592 err = -ENOMEM;
1593 goto abort;
1594 }
1595 esw->mc_promisc = mc_promisc;
1596
073bb189
SM		 1597 esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq");
1598 if (!esw->work_queue) {
1599 err = -ENOMEM;
1600 goto abort;
1601 }
1602
1603 esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport),
1604 GFP_KERNEL);
1605 if (!esw->vports) {
1606 err = -ENOMEM;
1607 goto abort;
1608 }
1609
127ea380
HHZ		 1610 esw->offloads.vport_reps =
1611 kzalloc(total_vports * sizeof(struct mlx5_eswitch_rep),
1612 GFP_KERNEL);
1613 if (!esw->offloads.vport_reps) {
1614 err = -ENOMEM;
1615 goto abort;
1616 }
1617
dfcb1ed3
MHY		 1618 mutex_init(&esw->state_lock);
1619
073bb189
SM		 1620 for (vport_num = 0; vport_num < total_vports; vport_num++) {
1621 struct mlx5_vport *vport = &esw->vports[vport_num];
1622
1623 vport->vport = vport_num;
1624 vport->dev = dev;
1625 INIT_WORK(&vport->vport_change_handler,
1626 esw_vport_change_handler);
073bb189
SM		 1627 }
1628
81848731
SM		 1629 esw->total_vports = total_vports;
1630 esw->enabled_vports = 0;
6ab36e35 1631 esw->mode = SRIOV_NONE;
073bb189 1632
81848731
SM		 1633 dev->priv.eswitch = esw;
1634 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
073bb189
SM		 1635 /* VF Vports will be enabled when SRIOV is enabled */
1636 return 0;
1637abort:
1638 if (esw->work_queue)
1639 destroy_workqueue(esw->work_queue);
1640 kfree(esw->l2_table.bitmap);
1641 kfree(esw->vports);
127ea380 1642 kfree(esw->offloads.vport_reps);
073bb189
SM		 1643 kfree(esw);
1644 return err;
1645}
1646
1647void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw)
1648{
1649 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1650 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1651 return;
1652
1653 esw_info(esw->dev, "cleanup\n");
1654 esw_disable_vport(esw, 0);
1655
1656 esw->dev->priv.eswitch = NULL;
1657 destroy_workqueue(esw->work_queue);
1658 kfree(esw->l2_table.bitmap);
a35f71f2 1659 kfree(esw->mc_promisc);
127ea380 1660 kfree(esw->offloads.vport_reps);
073bb189
SM		 1661 kfree(esw->vports);
1662 kfree(esw);
1663}
1664
1665void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe)
1666{
1667 struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change;
1668 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
1669 struct mlx5_vport *vport;
1670
1671 if (!esw) {
1672 pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n",
1673 vport_num);
1674 return;
1675 }
1676
1677 vport = &esw->vports[vport_num];
073bb189
SM		 1678 if (vport->enabled)
1679 queue_work(esw->work_queue, &vport->vport_change_handler);
073bb189 1680}
77256579
SM		 1681
1682/* Vport Administration */
1683#define ESW_ALLOWED(esw) \
1684 (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev))
1685#define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports)
1686
23898c76
NO		 1687static void node_guid_gen_from_mac(u64 *node_guid, u8 mac[ETH_ALEN])
1688{
1689 ((u8 *)node_guid)[7] = mac[0];
1690 ((u8 *)node_guid)[6] = mac[1];
1691 ((u8 *)node_guid)[5] = mac[2];
1692 ((u8 *)node_guid)[4] = 0xff;
1693 ((u8 *)node_guid)[3] = 0xfe;
1694 ((u8 *)node_guid)[2] = mac[3];
1695 ((u8 *)node_guid)[1] = mac[4];
1696 ((u8 *)node_guid)[0] = mac[5];
1697}
1698
77256579
SM		 1699int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
1700 int vport, u8 mac[ETH_ALEN])
1701{
f942380c 1702 struct mlx5_vport *evport;
23898c76
NO		 1703 u64 node_guid;
1704 int err = 0;
77256579
SM		 1705
1706 if (!ESW_ALLOWED(esw))
1707 return -EPERM;
1708 if (!LEGAL_VPORT(esw, vport))
1709 return -EINVAL;
1710
f942380c
MHY		 1711 evport = &esw->vports[vport];
1712
1713 if (evport->spoofchk && !is_valid_ether_addr(mac)) {
1714 mlx5_core_warn(esw->dev,
1715 "MAC invalidation is not allowed when spoofchk is on, vport(%d)\n",
1716 vport);
1717 return -EPERM;
1718 }
1719
77256579
SM		 1720 err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac);
1721 if (err) {
1722 mlx5_core_warn(esw->dev,
1723 "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n",
1724 vport, err);
1725 return err;
1726 }
1727
23898c76
NO		 1728 node_guid_gen_from_mac(&node_guid, mac);
1729 err = mlx5_modify_nic_vport_node_guid(esw->dev, vport, node_guid);
1730 if (err)
1731 mlx5_core_warn(esw->dev,
1732 "Failed to set vport %d node guid, err = %d. RDMA_CM will not function properly for this VF.\n",
1733 vport, err);
1734
f942380c
MHY		 1735 mutex_lock(&esw->state_lock);
1736 if (evport->enabled)
1737 err = esw_vport_ingress_config(esw, evport);
1738 mutex_unlock(&esw->state_lock);
77256579
SM		 1739 return err;
1740}
1741
1742int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
1743 int vport, int link_state)
1744{
1745 if (!ESW_ALLOWED(esw))
1746 return -EPERM;
1747 if (!LEGAL_VPORT(esw, vport))
1748 return -EINVAL;
1749
1750 return mlx5_modify_vport_admin_state(esw->dev,
1751 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1752 vport, link_state);
1753}
1754
1755int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
1756 int vport, struct ifla_vf_info *ivi)
1757{
f942380c 1758 struct mlx5_vport *evport;
9e7ea352
SM		 1759 u16 vlan;
1760 u8 qos;
1761
77256579
SM		 1762 if (!ESW_ALLOWED(esw))
1763 return -EPERM;
1764 if (!LEGAL_VPORT(esw, vport))
1765 return -EINVAL;
1766
f942380c
MHY		 1767 evport = &esw->vports[vport];
1768
77256579
SM		 1769 memset(ivi, 0, sizeof(*ivi));
1770 ivi->vf = vport - 1;
1771
1772 mlx5_query_nic_vport_mac_address(esw->dev, vport, ivi->mac);
1773 ivi->linkstate = mlx5_query_vport_admin_state(esw->dev,
1774 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1775 vport);
9e7ea352
SM		 1776 query_esw_vport_cvlan(esw->dev, vport, &vlan, &qos);
1777 ivi->vlan = vlan;
1778 ivi->qos = qos;
f942380c 1779 ivi->spoofchk = evport->spoofchk;
77256579
SM		 1780
1781 return 0;
1782}
9e7ea352
SM		 1783
1784int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
1785 int vport, u16 vlan, u8 qos)
1786{
dfcb1ed3
MHY		 1787 struct mlx5_vport *evport;
1788 int err = 0;
9e7ea352
SM		 1789 int set = 0;
1790
1791 if (!ESW_ALLOWED(esw))
1792 return -EPERM;
1793 if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7))
1794 return -EINVAL;
1795
1796 if (vlan || qos)
1797 set = 1;
1798
dfcb1ed3
MHY		 1799 evport = &esw->vports[vport];
1800
1801 err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set);
1802 if (err)
1803 return err;
1804
1805 mutex_lock(&esw->state_lock);
1806 evport->vlan = vlan;
1807 evport->qos = qos;
1808 if (evport->enabled) {
1809 err = esw_vport_ingress_config(esw, evport);
1810 if (err)
1811 goto out;
1812 err = esw_vport_egress_config(esw, evport);
1813 }
1814
1815out:
1816 mutex_unlock(&esw->state_lock);
1817 return err;
9e7ea352 1818}
3b751a2a 1819
f942380c
MHY		 1820int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
1821 int vport, bool spoofchk)
1822{
1823 struct mlx5_vport *evport;
1824 bool pschk;
1825 int err = 0;
1826
1827 if (!ESW_ALLOWED(esw))
1828 return -EPERM;
1829 if (!LEGAL_VPORT(esw, vport))
1830 return -EINVAL;
1831
1832 evport = &esw->vports[vport];
1833
1834 mutex_lock(&esw->state_lock);
1835 pschk = evport->spoofchk;
1836 evport->spoofchk = spoofchk;
1837 if (evport->enabled)
1838 err = esw_vport_ingress_config(esw, evport);
1839 if (err)
1840 evport->spoofchk = pschk;
1841 mutex_unlock(&esw->state_lock);
1842
1843 return err;
1844}
1845
1edc57e2
MHY		 1846int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1847 int vport, bool setting)
1848{
1849 struct mlx5_vport *evport;
1850
1851 if (!ESW_ALLOWED(esw))
1852 return -EPERM;
1853 if (!LEGAL_VPORT(esw, vport))
1854 return -EINVAL;
1855
1856 evport = &esw->vports[vport];
1857
1858 mutex_lock(&esw->state_lock);
1859 evport->trusted = setting;
1860 if (evport->enabled)
1861 esw_vport_change_handle_locked(evport);
1862 mutex_unlock(&esw->state_lock);
1863
1864 return 0;
1865}
1866
3b751a2a
SM		 1867int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
1868 int vport,
1869 struct ifla_vf_stats *vf_stats)
1870{
1871 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
c4f287c4 1872 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
3b751a2a
SM		 1873 int err = 0;
1874 u32 *out;
1875
1876 if (!ESW_ALLOWED(esw))
1877 return -EPERM;
1878 if (!LEGAL_VPORT(esw, vport))
1879 return -EINVAL;
1880
1881 out = mlx5_vzalloc(outlen);
1882 if (!out)
1883 return -ENOMEM;
1884
3b751a2a
SM		 1885 MLX5_SET(query_vport_counter_in, in, opcode,
1886 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
1887 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
1888 MLX5_SET(query_vport_counter_in, in, vport_number, vport);
1889 if (vport)
1890 MLX5_SET(query_vport_counter_in, in, other_vport, 1);
1891
1892 memset(out, 0, outlen);
1893 err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen);
1894 if (err)
1895 goto free_out;
1896
1897 #define MLX5_GET_CTR(p, x) \
1898 MLX5_GET64(query_vport_counter_out, p, x)
1899
1900 memset(vf_stats, 0, sizeof(*vf_stats));
1901 vf_stats->rx_packets =
1902 MLX5_GET_CTR(out, received_eth_unicast.packets) +
1903 MLX5_GET_CTR(out, received_eth_multicast.packets) +
1904 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1905
1906 vf_stats->rx_bytes =
1907 MLX5_GET_CTR(out, received_eth_unicast.octets) +
1908 MLX5_GET_CTR(out, received_eth_multicast.octets) +
1909 MLX5_GET_CTR(out, received_eth_broadcast.octets);
1910
1911 vf_stats->tx_packets =
1912 MLX5_GET_CTR(out, transmitted_eth_unicast.packets) +
1913 MLX5_GET_CTR(out, transmitted_eth_multicast.packets) +
1914 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
1915
1916 vf_stats->tx_bytes =
1917 MLX5_GET_CTR(out, transmitted_eth_unicast.octets) +
1918 MLX5_GET_CTR(out, transmitted_eth_multicast.octets) +
1919 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
1920
1921 vf_stats->multicast =
1922 MLX5_GET_CTR(out, received_eth_multicast.packets);
1923
1924 vf_stats->broadcast =
1925 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1926
1927free_out:
1928 kvfree(out);
1929 return err;
1930}
Linux 6.x block layer and io_uring tree(s)