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net/mlx5: Introduce E-switch QoS management
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eswitch.c
CommitLineData
073bb189
SM		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/etherdevice.h>
34#include <linux/mlx5/driver.h>
35#include <linux/mlx5/mlx5_ifc.h>
36#include <linux/mlx5/vport.h>
86d722ad 37#include <linux/mlx5/fs.h>
073bb189
SM		 38#include "mlx5_core.h"
39#include "eswitch.h"
40
81848731
SM		 41#define UPLINK_VPORT 0xFFFF
42
073bb189
SM		 43enum {
44 MLX5_ACTION_NONE = 0,
45 MLX5_ACTION_ADD = 1,
46 MLX5_ACTION_DEL = 2,
47};
48
81848731
SM		 49/* E-Switch UC L2 table hash node */
50struct esw_uc_addr {
073bb189 51 struct l2addr_node node;
073bb189
SM		 52 u32 table_index;
53 u32 vport;
54};
55
81848731
SM		 56/* E-Switch MC FDB table hash node */
57struct esw_mc_addr { /* SRIOV only */
58 struct l2addr_node node;
59 struct mlx5_flow_rule *uplink_rule; /* Forward to uplink rule */
60 u32 refcnt;
61};
62
63/* Vport UC/MC hash node */
64struct vport_addr {
65 struct l2addr_node node;
66 u8 action;
67 u32 vport;
68 struct mlx5_flow_rule *flow_rule; /* SRIOV only */
a35f71f2
MHY		 69 /* A flag indicating that mac was added due to mc promiscuous vport */
70 bool mc_promisc;
073bb189
SM		 71};
72
73enum {
74 UC_ADDR_CHANGE = BIT(0),
75 MC_ADDR_CHANGE = BIT(1),
a35f71f2 76 PROMISC_CHANGE = BIT(3),
073bb189
SM		 77};
78
81848731
SM		 79/* Vport context events */
80#define SRIOV_VPORT_EVENTS (UC_ADDR_CHANGE | \
a35f71f2
MHY		 81 MC_ADDR_CHANGE | \
82 PROMISC_CHANGE)
81848731
SM		 83
84static int arm_vport_context_events_cmd(struct mlx5_core_dev *dev, u16 vport,
073bb189
SM		 85 u32 events_mask)
86{
c4f287c4
SM		 87 int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0};
88 int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
073bb189 89 void *nic_vport_ctx;
073bb189
SM		 90
91 MLX5_SET(modify_nic_vport_context_in, in,
92 opcode, MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT);
93 MLX5_SET(modify_nic_vport_context_in, in, field_select.change_event, 1);
94 MLX5_SET(modify_nic_vport_context_in, in, vport_number, vport);
95 if (vport)
96 MLX5_SET(modify_nic_vport_context_in, in, other_vport, 1);
97 nic_vport_ctx = MLX5_ADDR_OF(modify_nic_vport_context_in,
98 in, nic_vport_context);
99
100 MLX5_SET(nic_vport_context, nic_vport_ctx, arm_change_event, 1);
101
102 if (events_mask & UC_ADDR_CHANGE)
103 MLX5_SET(nic_vport_context, nic_vport_ctx,
104 event_on_uc_address_change, 1);
105 if (events_mask & MC_ADDR_CHANGE)
106 MLX5_SET(nic_vport_context, nic_vport_ctx,
107 event_on_mc_address_change, 1);
a35f71f2
MHY		 108 if (events_mask & PROMISC_CHANGE)
109 MLX5_SET(nic_vport_context, nic_vport_ctx,
110 event_on_promisc_change, 1);
073bb189 111
c4f287c4 112 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 113}
114
9e7ea352 115/* E-Switch vport context HW commands */
9e7ea352
SM		 116static int modify_esw_vport_context_cmd(struct mlx5_core_dev *dev, u16 vport,
117 void *in, int inlen)
118{
c4f287c4 119 u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0};
9e7ea352 120
c4f287c4
SM		 121 MLX5_SET(modify_esw_vport_context_in, in, opcode,
122 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT);
9e7ea352
SM		 123 MLX5_SET(modify_esw_vport_context_in, in, vport_number, vport);
124 if (vport)
125 MLX5_SET(modify_esw_vport_context_in, in, other_vport, 1);
c4f287c4 126 return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
9e7ea352
SM		 127}
128
129static int modify_esw_vport_cvlan(struct mlx5_core_dev *dev, u32 vport,
e33dfe31 130 u16 vlan, u8 qos, u8 set_flags)
9e7ea352 131{
c4f287c4 132 u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {0};
9e7ea352
SM		 133
134 if (!MLX5_CAP_ESW(dev, vport_cvlan_strip) ||
135 !MLX5_CAP_ESW(dev, vport_cvlan_insert_if_not_exist))
136 return -ENOTSUPP;
137
e33dfe31
OG		 138 esw_debug(dev, "Set Vport[%d] VLAN %d qos %d set=%x\n",
139 vport, vlan, qos, set_flags);
140
141 if (set_flags & SET_VLAN_STRIP)
9e7ea352
SM		 142 MLX5_SET(modify_esw_vport_context_in, in,
143 esw_vport_context.vport_cvlan_strip, 1);
e33dfe31
OG		 144
145 if (set_flags & SET_VLAN_INSERT) {
9e7ea352
SM		 146 /* insert only if no vlan in packet */
147 MLX5_SET(modify_esw_vport_context_in, in,
148 esw_vport_context.vport_cvlan_insert, 1);
e33dfe31 149
9e7ea352
SM		 150 MLX5_SET(modify_esw_vport_context_in, in,
151 esw_vport_context.cvlan_pcp, qos);
152 MLX5_SET(modify_esw_vport_context_in, in,
153 esw_vport_context.cvlan_id, vlan);
154 }
155
156 MLX5_SET(modify_esw_vport_context_in, in,
157 field_select.vport_cvlan_strip, 1);
158 MLX5_SET(modify_esw_vport_context_in, in,
159 field_select.vport_cvlan_insert, 1);
160
161 return modify_esw_vport_context_cmd(dev, vport, in, sizeof(in));
162}
163
073bb189
SM		 164/* HW L2 Table (MPFS) management */
165static int set_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index,
166 u8 *mac, u8 vlan_valid, u16 vlan)
167{
c4f287c4
SM		 168 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {0};
169 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {0};
073bb189
SM		 170 u8 *in_mac_addr;
171
073bb189
SM		 172 MLX5_SET(set_l2_table_entry_in, in, opcode,
173 MLX5_CMD_OP_SET_L2_TABLE_ENTRY);
174 MLX5_SET(set_l2_table_entry_in, in, table_index, index);
175 MLX5_SET(set_l2_table_entry_in, in, vlan_valid, vlan_valid);
176 MLX5_SET(set_l2_table_entry_in, in, vlan, vlan);
177
178 in_mac_addr = MLX5_ADDR_OF(set_l2_table_entry_in, in, mac_address);
179 ether_addr_copy(&in_mac_addr[2], mac);
180
c4f287c4 181 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 182}
183
184static int del_l2_table_entry_cmd(struct mlx5_core_dev *dev, u32 index)
185{
c4f287c4
SM		 186 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {0};
187 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {0};
073bb189
SM		 188
189 MLX5_SET(delete_l2_table_entry_in, in, opcode,
190 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY);
191 MLX5_SET(delete_l2_table_entry_in, in, table_index, index);
c4f287c4 192 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
073bb189
SM		 193}
194
195static int alloc_l2_table_index(struct mlx5_l2_table *l2_table, u32 *ix)
196{
197 int err = 0;
198
199 *ix = find_first_zero_bit(l2_table->bitmap, l2_table->size);
200 if (*ix >= l2_table->size)
201 err = -ENOSPC;
202 else
203 __set_bit(*ix, l2_table->bitmap);
204
205 return err;
206}
207
208static void free_l2_table_index(struct mlx5_l2_table *l2_table, u32 ix)
209{
210 __clear_bit(ix, l2_table->bitmap);
211}
212
213static int set_l2_table_entry(struct mlx5_core_dev *dev, u8 *mac,
214 u8 vlan_valid, u16 vlan,
215 u32 *index)
216{
217 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
218 int err;
219
220 err = alloc_l2_table_index(l2_table, index);
221 if (err)
222 return err;
223
224 err = set_l2_table_entry_cmd(dev, *index, mac, vlan_valid, vlan);
225 if (err)
226 free_l2_table_index(l2_table, *index);
227
228 return err;
229}
230
231static void del_l2_table_entry(struct mlx5_core_dev *dev, u32 index)
232{
233 struct mlx5_l2_table *l2_table = &dev->priv.eswitch->l2_table;
234
235 del_l2_table_entry_cmd(dev, index);
236 free_l2_table_index(l2_table, index);
237}
238
81848731
SM		 239/* E-Switch FDB */
240static struct mlx5_flow_rule *
a35f71f2 241__esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u32 vport, bool rx_rule,
78a9199b 242 u8 mac_c[ETH_ALEN], u8 mac_v[ETH_ALEN])
81848731 243{
78a9199b
MHY		 244 int match_header = (is_zero_ether_addr(mac_c) ? 0 :
245 MLX5_MATCH_OUTER_HEADERS);
81848731 246 struct mlx5_flow_rule *flow_rule = NULL;
78a9199b 247 struct mlx5_flow_destination dest;
c5bb1730 248 struct mlx5_flow_spec *spec;
a35f71f2
MHY		 249 void *mv_misc = NULL;
250 void *mc_misc = NULL;
78a9199b
MHY		 251 u8 *dmac_v = NULL;
252 u8 *dmac_c = NULL;
81848731 253
a35f71f2
MHY		 254 if (rx_rule)
255 match_header |= MLX5_MATCH_MISC_PARAMETERS;
c5bb1730
MG		 256
257 spec = mlx5_vzalloc(sizeof(*spec));
258 if (!spec) {
2974ab6e 259 esw_warn(esw->dev, "FDB: Failed to alloc match parameters\n");
c5bb1730 260 return NULL;
81848731 261 }
c5bb1730 262 dmac_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
81848731 263 outer_headers.dmac_47_16);
c5bb1730 264 dmac_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
81848731
SM		 265 outer_headers.dmac_47_16);
266
a35f71f2 267 if (match_header & MLX5_MATCH_OUTER_HEADERS) {
78a9199b
MHY		 268 ether_addr_copy(dmac_v, mac_v);
269 ether_addr_copy(dmac_c, mac_c);
270 }
81848731 271
a35f71f2 272 if (match_header & MLX5_MATCH_MISC_PARAMETERS) {
c5bb1730
MG		 273 mv_misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
274 misc_parameters);
275 mc_misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
276 misc_parameters);
a35f71f2
MHY		 277 MLX5_SET(fte_match_set_misc, mv_misc, source_port, UPLINK_VPORT);
278 MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port);
279 }
280
81848731
SM		 281 dest.type = MLX5_FLOW_DESTINATION_TYPE_VPORT;
282 dest.vport_num = vport;
283
284 esw_debug(esw->dev,
285 "\tFDB add rule dmac_v(%pM) dmac_c(%pM) -> vport(%d)\n",
286 dmac_v, dmac_c, vport);
c5bb1730 287 spec->match_criteria_enable = match_header;
81848731 288 flow_rule =
c5bb1730 289 mlx5_add_flow_rule(esw->fdb_table.fdb, spec,
81848731
SM		 290 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
291 0, &dest);
3f42ac66 292 if (IS_ERR(flow_rule)) {
2974ab6e
SM		 293 esw_warn(esw->dev,
294 "FDB: Failed to add flow rule: dmac_v(%pM) dmac_c(%pM) -> vport(%d), err(%ld)\n",
81848731
SM		 295 dmac_v, dmac_c, vport, PTR_ERR(flow_rule));
296 flow_rule = NULL;
297 }
c5bb1730
MG		 298
299 kvfree(spec);
81848731
SM		 300 return flow_rule;
301}
302
78a9199b
MHY		 303static struct mlx5_flow_rule *
304esw_fdb_set_vport_rule(struct mlx5_eswitch *esw, u8 mac[ETH_ALEN], u32 vport)
305{
306 u8 mac_c[ETH_ALEN];
307
308 eth_broadcast_addr(mac_c);
a35f71f2
MHY		 309 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac);
310}
311
312static struct mlx5_flow_rule *
313esw_fdb_set_vport_allmulti_rule(struct mlx5_eswitch *esw, u32 vport)
314{
315 u8 mac_c[ETH_ALEN];
316 u8 mac_v[ETH_ALEN];
317
318 eth_zero_addr(mac_c);
319 eth_zero_addr(mac_v);
320 mac_c[0] = 0x01;
321 mac_v[0] = 0x01;
322 return __esw_fdb_set_vport_rule(esw, vport, false, mac_c, mac_v);
323}
324
325static struct mlx5_flow_rule *
326esw_fdb_set_vport_promisc_rule(struct mlx5_eswitch *esw, u32 vport)
327{
328 u8 mac_c[ETH_ALEN];
329 u8 mac_v[ETH_ALEN];
330
331 eth_zero_addr(mac_c);
332 eth_zero_addr(mac_v);
333 return __esw_fdb_set_vport_rule(esw, vport, true, mac_c, mac_v);
78a9199b
MHY		 334}
335
6ab36e35 336static int esw_create_legacy_fdb_table(struct mlx5_eswitch *esw, int nvports)
81848731 337{
86d722ad 338 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
81848731 339 struct mlx5_core_dev *dev = esw->dev;
86d722ad 340 struct mlx5_flow_namespace *root_ns;
81848731 341 struct mlx5_flow_table *fdb;
86d722ad
MG		 342 struct mlx5_flow_group *g;
343 void *match_criteria;
344 int table_size;
345 u32 *flow_group_in;
81848731 346 u8 *dmac;
86d722ad 347 int err = 0;
81848731
SM		 348
349 esw_debug(dev, "Create FDB log_max_size(%d)\n",
350 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
351
86d722ad
MG		 352 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_FDB);
353 if (!root_ns) {
354 esw_warn(dev, "Failed to get FDB flow namespace\n");
355 return -ENOMEM;
356 }
81848731 357
86d722ad
MG		 358 flow_group_in = mlx5_vzalloc(inlen);
359 if (!flow_group_in)
360 return -ENOMEM;
361 memset(flow_group_in, 0, inlen);
362
363 table_size = BIT(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, log_max_ft_size));
d63cd286 364 fdb = mlx5_create_flow_table(root_ns, 0, table_size, 0);
3f42ac66 365 if (IS_ERR(fdb)) {
86d722ad
MG		 366 err = PTR_ERR(fdb);
367 esw_warn(dev, "Failed to create FDB Table err %d\n", err);
368 goto out;
369 }
78a9199b 370 esw->fdb_table.fdb = fdb;
81848731 371
78a9199b 372 /* Addresses group : Full match unicast/multicast addresses */
86d722ad
MG		 373 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
374 MLX5_MATCH_OUTER_HEADERS);
375 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
376 dmac = MLX5_ADDR_OF(fte_match_param, match_criteria, outer_headers.dmac_47_16);
377 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
78a9199b
MHY		 378 /* Preserve 2 entries for allmulti and promisc rules*/
379 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 3);
86d722ad 380 eth_broadcast_addr(dmac);
86d722ad 381 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 382 if (IS_ERR(g)) {
86d722ad
MG		 383 err = PTR_ERR(g);
384 esw_warn(dev, "Failed to create flow group err(%d)\n", err);
385 goto out;
386 }
6ab36e35 387 esw->fdb_table.legacy.addr_grp = g;
78a9199b
MHY		 388
389 /* Allmulti group : One rule that forwards any mcast traffic */
390 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
391 MLX5_MATCH_OUTER_HEADERS);
392 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 2);
393 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 2);
394 eth_zero_addr(dmac);
395 dmac[0] = 0x01;
396 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 397 if (IS_ERR(g)) {
78a9199b
MHY		 398 err = PTR_ERR(g);
399 esw_warn(dev, "Failed to create allmulti flow group err(%d)\n", err);
400 goto out;
401 }
6ab36e35 402 esw->fdb_table.legacy.allmulti_grp = g;
78a9199b
MHY		 403
404 /* Promiscuous group :
405 * One rule that forward all unmatched traffic from previous groups
406 */
407 eth_zero_addr(dmac);
408 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable,
409 MLX5_MATCH_MISC_PARAMETERS);
410 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port);
411 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, table_size - 1);
412 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, table_size - 1);
413 g = mlx5_create_flow_group(fdb, flow_group_in);
3f42ac66 414 if (IS_ERR(g)) {
78a9199b
MHY		 415 err = PTR_ERR(g);
416 esw_warn(dev, "Failed to create promisc flow group err(%d)\n", err);
417 goto out;
418 }
6ab36e35 419 esw->fdb_table.legacy.promisc_grp = g;
78a9199b 420
86d722ad 421out:
78a9199b 422 if (err) {
6ab36e35
OG		 423 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.allmulti_grp)) {
424 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
425 esw->fdb_table.legacy.allmulti_grp = NULL;
78a9199b 426 }
6ab36e35
OG		 427 if (!IS_ERR_OR_NULL(esw->fdb_table.legacy.addr_grp)) {
428 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
429 esw->fdb_table.legacy.addr_grp = NULL;
78a9199b
MHY		 430 }
431 if (!IS_ERR_OR_NULL(esw->fdb_table.fdb)) {
432 mlx5_destroy_flow_table(esw->fdb_table.fdb);
433 esw->fdb_table.fdb = NULL;
434 }
435 }
436
3fe3d819 437 kvfree(flow_group_in);
86d722ad 438 return err;
81848731
SM		 439}
440
6ab36e35 441static void esw_destroy_legacy_fdb_table(struct mlx5_eswitch *esw)
81848731
SM		 442{
443 if (!esw->fdb_table.fdb)
444 return;
445
86d722ad 446 esw_debug(esw->dev, "Destroy FDB Table\n");
6ab36e35
OG		 447 mlx5_destroy_flow_group(esw->fdb_table.legacy.promisc_grp);
448 mlx5_destroy_flow_group(esw->fdb_table.legacy.allmulti_grp);
449 mlx5_destroy_flow_group(esw->fdb_table.legacy.addr_grp);
81848731
SM		 450 mlx5_destroy_flow_table(esw->fdb_table.fdb);
451 esw->fdb_table.fdb = NULL;
6ab36e35
OG		 452 esw->fdb_table.legacy.addr_grp = NULL;
453 esw->fdb_table.legacy.allmulti_grp = NULL;
454 esw->fdb_table.legacy.promisc_grp = NULL;
81848731
SM		 455}
456
457/* E-Switch vport UC/MC lists management */
458typedef int (*vport_addr_action)(struct mlx5_eswitch *esw,
459 struct vport_addr *vaddr);
460
461static int esw_add_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
462{
463 struct hlist_head *hash = esw->l2_table.l2_hash;
464 struct esw_uc_addr *esw_uc;
465 u8 *mac = vaddr->node.addr;
466 u32 vport = vaddr->vport;
467 int err;
468
469 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
470 if (esw_uc) {
073bb189
SM		 471 esw_warn(esw->dev,
472 "Failed to set L2 mac(%pM) for vport(%d), mac is already in use by vport(%d)\n",
81848731 473 mac, vport, esw_uc->vport);
073bb189
SM		 474 return -EEXIST;
475 }
476
81848731
SM		 477 esw_uc = l2addr_hash_add(hash, mac, struct esw_uc_addr, GFP_KERNEL);
478 if (!esw_uc)
073bb189 479 return -ENOMEM;
81848731 480 esw_uc->vport = vport;
073bb189 481
81848731 482 err = set_l2_table_entry(esw->dev, mac, 0, 0, &esw_uc->table_index);
073bb189 483 if (err)
81848731
SM		 484 goto abort;
485
69697b6e
OG		 486 /* SRIOV is enabled: Forward UC MAC to vport */
487 if (esw->fdb_table.fdb && esw->mode == SRIOV_LEGACY)
81848731
SM		 488 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
489
490 esw_debug(esw->dev, "\tADDED UC MAC: vport[%d] %pM index:%d fr(%p)\n",
491 vport, mac, esw_uc->table_index, vaddr->flow_rule);
492 return err;
493abort:
494 l2addr_hash_del(esw_uc);
073bb189
SM		 495 return err;
496}
497
81848731 498static int esw_del_uc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
073bb189 499{
81848731
SM		 500 struct hlist_head *hash = esw->l2_table.l2_hash;
501 struct esw_uc_addr *esw_uc;
502 u8 *mac = vaddr->node.addr;
503 u32 vport = vaddr->vport;
504
505 esw_uc = l2addr_hash_find(hash, mac, struct esw_uc_addr);
506 if (!esw_uc || esw_uc->vport != vport) {
507 esw_debug(esw->dev,
508 "MAC(%pM) doesn't belong to vport (%d)\n",
509 mac, vport);
510 return -EINVAL;
511 }
512 esw_debug(esw->dev, "\tDELETE UC MAC: vport[%d] %pM index:%d fr(%p)\n",
513 vport, mac, esw_uc->table_index, vaddr->flow_rule);
514
515 del_l2_table_entry(esw->dev, esw_uc->table_index);
516
517 if (vaddr->flow_rule)
86d722ad 518 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 519 vaddr->flow_rule = NULL;
520
521 l2addr_hash_del(esw_uc);
522 return 0;
523}
524
a35f71f2
MHY		 525static void update_allmulti_vports(struct mlx5_eswitch *esw,
526 struct vport_addr *vaddr,
527 struct esw_mc_addr *esw_mc)
528{
529 u8 *mac = vaddr->node.addr;
530 u32 vport_idx = 0;
531
532 for (vport_idx = 0; vport_idx < esw->total_vports; vport_idx++) {
533 struct mlx5_vport *vport = &esw->vports[vport_idx];
534 struct hlist_head *vport_hash = vport->mc_list;
535 struct vport_addr *iter_vaddr =
536 l2addr_hash_find(vport_hash,
537 mac,
538 struct vport_addr);
539 if (IS_ERR_OR_NULL(vport->allmulti_rule) ||
540 vaddr->vport == vport_idx)
541 continue;
542 switch (vaddr->action) {
543 case MLX5_ACTION_ADD:
544 if (iter_vaddr)
545 continue;
546 iter_vaddr = l2addr_hash_add(vport_hash, mac,
547 struct vport_addr,
548 GFP_KERNEL);
549 if (!iter_vaddr) {
550 esw_warn(esw->dev,
551 "ALL-MULTI: Failed to add MAC(%pM) to vport[%d] DB\n",
552 mac, vport_idx);
553 continue;
554 }
555 iter_vaddr->vport = vport_idx;
556 iter_vaddr->flow_rule =
557 esw_fdb_set_vport_rule(esw,
558 mac,
559 vport_idx);
62e3c24a 560 iter_vaddr->mc_promisc = true;
a35f71f2
MHY		 561 break;
562 case MLX5_ACTION_DEL:
563 if (!iter_vaddr)
564 continue;
565 mlx5_del_flow_rule(iter_vaddr->flow_rule);
566 l2addr_hash_del(iter_vaddr);
567 break;
568 }
569 }
570}
571
81848731
SM		 572static int esw_add_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
573{
574 struct hlist_head *hash = esw->mc_table;
575 struct esw_mc_addr *esw_mc;
576 u8 *mac = vaddr->node.addr;
577 u32 vport = vaddr->vport;
578
579 if (!esw->fdb_table.fdb)
580 return 0;
581
582 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
583 if (esw_mc)
584 goto add;
585
586 esw_mc = l2addr_hash_add(hash, mac, struct esw_mc_addr, GFP_KERNEL);
587 if (!esw_mc)
588 return -ENOMEM;
589
590 esw_mc->uplink_rule = /* Forward MC MAC to Uplink */
591 esw_fdb_set_vport_rule(esw, mac, UPLINK_VPORT);
a35f71f2
MHY		 592
593 /* Add this multicast mac to all the mc promiscuous vports */
594 update_allmulti_vports(esw, vaddr, esw_mc);
595
81848731 596add:
a35f71f2
MHY		 597 /* If the multicast mac is added as a result of mc promiscuous vport,
598 * don't increment the multicast ref count
599 */
600 if (!vaddr->mc_promisc)
601 esw_mc->refcnt++;
602
81848731
SM		 603 /* Forward MC MAC to vport */
604 vaddr->flow_rule = esw_fdb_set_vport_rule(esw, mac, vport);
605 esw_debug(esw->dev,
606 "\tADDED MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
607 vport, mac, vaddr->flow_rule,
608 esw_mc->refcnt, esw_mc->uplink_rule);
609 return 0;
610}
611
612static int esw_del_mc_addr(struct mlx5_eswitch *esw, struct vport_addr *vaddr)
613{
614 struct hlist_head *hash = esw->mc_table;
615 struct esw_mc_addr *esw_mc;
616 u8 *mac = vaddr->node.addr;
617 u32 vport = vaddr->vport;
073bb189 618
81848731
SM		 619 if (!esw->fdb_table.fdb)
620 return 0;
621
622 esw_mc = l2addr_hash_find(hash, mac, struct esw_mc_addr);
623 if (!esw_mc) {
624 esw_warn(esw->dev,
625 "Failed to find eswitch MC addr for MAC(%pM) vport(%d)",
073bb189
SM		 626 mac, vport);
627 return -EINVAL;
628 }
81848731
SM		 629 esw_debug(esw->dev,
630 "\tDELETE MC MAC: vport[%d] %pM fr(%p) refcnt(%d) uplinkfr(%p)\n",
631 vport, mac, vaddr->flow_rule, esw_mc->refcnt,
632 esw_mc->uplink_rule);
633
634 if (vaddr->flow_rule)
86d722ad 635 mlx5_del_flow_rule(vaddr->flow_rule);
81848731
SM		 636 vaddr->flow_rule = NULL;
637
a35f71f2
MHY		 638 /* If the multicast mac is added as a result of mc promiscuous vport,
639 * don't decrement the multicast ref count.
640 */
641 if (vaddr->mc_promisc || (--esw_mc->refcnt > 0))
81848731 642 return 0;
073bb189 643
a35f71f2
MHY		 644 /* Remove this multicast mac from all the mc promiscuous vports */
645 update_allmulti_vports(esw, vaddr, esw_mc);
646
81848731 647 if (esw_mc->uplink_rule)
86d722ad 648 mlx5_del_flow_rule(esw_mc->uplink_rule);
81848731
SM		 649
650 l2addr_hash_del(esw_mc);
073bb189
SM		 651 return 0;
652}
653
81848731
SM		 654/* Apply vport UC/MC list to HW l2 table and FDB table */
655static void esw_apply_vport_addr_list(struct mlx5_eswitch *esw,
656 u32 vport_num, int list_type)
073bb189
SM		 657{
658 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731
SM		 659 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
660 vport_addr_action vport_addr_add;
661 vport_addr_action vport_addr_del;
662 struct vport_addr *addr;
073bb189
SM		 663 struct l2addr_node *node;
664 struct hlist_head *hash;
665 struct hlist_node *tmp;
666 int hi;
667
81848731
SM		 668 vport_addr_add = is_uc ? esw_add_uc_addr :
669 esw_add_mc_addr;
670 vport_addr_del = is_uc ? esw_del_uc_addr :
671 esw_del_mc_addr;
672
673 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189 674 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 675 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 676 switch (addr->action) {
677 case MLX5_ACTION_ADD:
81848731 678 vport_addr_add(esw, addr);
073bb189
SM		 679 addr->action = MLX5_ACTION_NONE;
680 break;
681 case MLX5_ACTION_DEL:
81848731 682 vport_addr_del(esw, addr);
073bb189
SM		 683 l2addr_hash_del(addr);
684 break;
685 }
686 }
687}
688
81848731
SM		 689/* Sync vport UC/MC list from vport context */
690static void esw_update_vport_addr_list(struct mlx5_eswitch *esw,
691 u32 vport_num, int list_type)
073bb189
SM		 692{
693 struct mlx5_vport *vport = &esw->vports[vport_num];
81848731 694 bool is_uc = list_type == MLX5_NVPRT_LIST_TYPE_UC;
073bb189 695 u8 (*mac_list)[ETH_ALEN];
81848731
SM		 696 struct l2addr_node *node;
697 struct vport_addr *addr;
073bb189
SM		 698 struct hlist_head *hash;
699 struct hlist_node *tmp;
700 int size;
701 int err;
702 int hi;
703 int i;
704
81848731
SM		 705 size = is_uc ? MLX5_MAX_UC_PER_VPORT(esw->dev) :
706 MLX5_MAX_MC_PER_VPORT(esw->dev);
073bb189
SM		 707
708 mac_list = kcalloc(size, ETH_ALEN, GFP_KERNEL);
709 if (!mac_list)
710 return;
711
81848731 712 hash = is_uc ? vport->uc_list : vport->mc_list;
073bb189
SM		 713
714 for_each_l2hash_node(node, tmp, hash, hi) {
81848731 715 addr = container_of(node, struct vport_addr, node);
073bb189
SM		 716 addr->action = MLX5_ACTION_DEL;
717 }
718
586cfa7f
MHY		 719 if (!vport->enabled)
720 goto out;
721
81848731 722 err = mlx5_query_nic_vport_mac_list(esw->dev, vport_num, list_type,
073bb189
SM		 723 mac_list, &size);
724 if (err)
761e205b 725 goto out;
81848731
SM		 726 esw_debug(esw->dev, "vport[%d] context update %s list size (%d)\n",
727 vport_num, is_uc ? "UC" : "MC", size);
073bb189
SM		 728
729 for (i = 0; i < size; i++) {
81848731 730 if (is_uc && !is_valid_ether_addr(mac_list[i]))
073bb189
SM		 731 continue;
732
81848731
SM		 733 if (!is_uc && !is_multicast_ether_addr(mac_list[i]))
734 continue;
735
736 addr = l2addr_hash_find(hash, mac_list[i], struct vport_addr);
073bb189
SM		 737 if (addr) {
738 addr->action = MLX5_ACTION_NONE;
a35f71f2
MHY		 739 /* If this mac was previously added because of allmulti
740 * promiscuous rx mode, its now converted to be original
741 * vport mac.
742 */
743 if (addr->mc_promisc) {
744 struct esw_mc_addr *esw_mc =
745 l2addr_hash_find(esw->mc_table,
746 mac_list[i],
747 struct esw_mc_addr);
748 if (!esw_mc) {
749 esw_warn(esw->dev,
750 "Failed to MAC(%pM) in mcast DB\n",
751 mac_list[i]);
752 continue;
753 }
754 esw_mc->refcnt++;
755 addr->mc_promisc = false;
756 }
073bb189
SM		 757 continue;
758 }
759
81848731 760 addr = l2addr_hash_add(hash, mac_list[i], struct vport_addr,
073bb189
SM		 761 GFP_KERNEL);
762 if (!addr) {
763 esw_warn(esw->dev,
764 "Failed to add MAC(%pM) to vport[%d] DB\n",
765 mac_list[i], vport_num);
766 continue;
767 }
81848731 768 addr->vport = vport_num;
073bb189
SM		 769 addr->action = MLX5_ACTION_ADD;
770 }
761e205b 771out:
073bb189
SM		 772 kfree(mac_list);
773}
774
a35f71f2
MHY		 775/* Sync vport UC/MC list from vport context
776 * Must be called after esw_update_vport_addr_list
777 */
778static void esw_update_vport_mc_promisc(struct mlx5_eswitch *esw, u32 vport_num)
779{
780 struct mlx5_vport *vport = &esw->vports[vport_num];
781 struct l2addr_node *node;
782 struct vport_addr *addr;
783 struct hlist_head *hash;
784 struct hlist_node *tmp;
785 int hi;
786
787 hash = vport->mc_list;
788
789 for_each_l2hash_node(node, tmp, esw->mc_table, hi) {
790 u8 *mac = node->addr;
791
792 addr = l2addr_hash_find(hash, mac, struct vport_addr);
793 if (addr) {
794 if (addr->action == MLX5_ACTION_DEL)
795 addr->action = MLX5_ACTION_NONE;
796 continue;
797 }
798 addr = l2addr_hash_add(hash, mac, struct vport_addr,
799 GFP_KERNEL);
800 if (!addr) {
801 esw_warn(esw->dev,
802 "Failed to add allmulti MAC(%pM) to vport[%d] DB\n",
803 mac, vport_num);
804 continue;
805 }
806 addr->vport = vport_num;
807 addr->action = MLX5_ACTION_ADD;
808 addr->mc_promisc = true;
809 }
810}
811
812/* Apply vport rx mode to HW FDB table */
813static void esw_apply_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num,
814 bool promisc, bool mc_promisc)
815{
816 struct esw_mc_addr *allmulti_addr = esw->mc_promisc;
817 struct mlx5_vport *vport = &esw->vports[vport_num];
818
819 if (IS_ERR_OR_NULL(vport->allmulti_rule) != mc_promisc)
820 goto promisc;
821
822 if (mc_promisc) {
823 vport->allmulti_rule =
824 esw_fdb_set_vport_allmulti_rule(esw, vport_num);
825 if (!allmulti_addr->uplink_rule)
826 allmulti_addr->uplink_rule =
827 esw_fdb_set_vport_allmulti_rule(esw,
828 UPLINK_VPORT);
829 allmulti_addr->refcnt++;
830 } else if (vport->allmulti_rule) {
831 mlx5_del_flow_rule(vport->allmulti_rule);
832 vport->allmulti_rule = NULL;
833
834 if (--allmulti_addr->refcnt > 0)
835 goto promisc;
836
837 if (allmulti_addr->uplink_rule)
838 mlx5_del_flow_rule(allmulti_addr->uplink_rule);
839 allmulti_addr->uplink_rule = NULL;
840 }
841
842promisc:
843 if (IS_ERR_OR_NULL(vport->promisc_rule) != promisc)
844 return;
845
846 if (promisc) {
847 vport->promisc_rule = esw_fdb_set_vport_promisc_rule(esw,
848 vport_num);
849 } else if (vport->promisc_rule) {
850 mlx5_del_flow_rule(vport->promisc_rule);
851 vport->promisc_rule = NULL;
852 }
853}
854
855/* Sync vport rx mode from vport context */
856static void esw_update_vport_rx_mode(struct mlx5_eswitch *esw, u32 vport_num)
857{
858 struct mlx5_vport *vport = &esw->vports[vport_num];
859 int promisc_all = 0;
860 int promisc_uc = 0;
861 int promisc_mc = 0;
862 int err;
863
864 err = mlx5_query_nic_vport_promisc(esw->dev,
865 vport_num,
866 &promisc_uc,
867 &promisc_mc,
868 &promisc_all);
869 if (err)
870 return;
871 esw_debug(esw->dev, "vport[%d] context update rx mode promisc_all=%d, all_multi=%d\n",
872 vport_num, promisc_all, promisc_mc);
873
1ab2068a 874 if (!vport->info.trusted || !vport->enabled) {
a35f71f2
MHY		 875 promisc_uc = 0;
876 promisc_mc = 0;
877 promisc_all = 0;
878 }
879
880 esw_apply_vport_rx_mode(esw, vport_num, promisc_all,
881 (promisc_all || promisc_mc));
882}
883
1edc57e2 884static void esw_vport_change_handle_locked(struct mlx5_vport *vport)
073bb189 885{
073bb189 886 struct mlx5_core_dev *dev = vport->dev;
81848731 887 struct mlx5_eswitch *esw = dev->priv.eswitch;
073bb189
SM		 888 u8 mac[ETH_ALEN];
889
890 mlx5_query_nic_vport_mac_address(dev, vport->vport, mac);
81848731
SM		 891 esw_debug(dev, "vport[%d] Context Changed: perm mac: %pM\n",
892 vport->vport, mac);
893
894 if (vport->enabled_events & UC_ADDR_CHANGE) {
895 esw_update_vport_addr_list(esw, vport->vport,
896 MLX5_NVPRT_LIST_TYPE_UC);
897 esw_apply_vport_addr_list(esw, vport->vport,
898 MLX5_NVPRT_LIST_TYPE_UC);
899 }
073bb189 900
81848731
SM		 901 if (vport->enabled_events & MC_ADDR_CHANGE) {
902 esw_update_vport_addr_list(esw, vport->vport,
903 MLX5_NVPRT_LIST_TYPE_MC);
a35f71f2
MHY		 904 }
905
906 if (vport->enabled_events & PROMISC_CHANGE) {
907 esw_update_vport_rx_mode(esw, vport->vport);
908 if (!IS_ERR_OR_NULL(vport->allmulti_rule))
909 esw_update_vport_mc_promisc(esw, vport->vport);
910 }
911
912 if (vport->enabled_events & (PROMISC_CHANGE | MC_ADDR_CHANGE)) {
81848731
SM		 913 esw_apply_vport_addr_list(esw, vport->vport,
914 MLX5_NVPRT_LIST_TYPE_MC);
915 }
073bb189 916
81848731 917 esw_debug(esw->dev, "vport[%d] Context Changed: Done\n", vport->vport);
073bb189
SM		 918 if (vport->enabled)
919 arm_vport_context_events_cmd(dev, vport->vport,
81848731 920 vport->enabled_events);
073bb189
SM		 921}
922
1edc57e2
MHY		 923static void esw_vport_change_handler(struct work_struct *work)
924{
925 struct mlx5_vport *vport =
926 container_of(work, struct mlx5_vport, vport_change_handler);
927 struct mlx5_eswitch *esw = vport->dev->priv.eswitch;
928
929 mutex_lock(&esw->state_lock);
930 esw_vport_change_handle_locked(vport);
931 mutex_unlock(&esw->state_lock);
932}
933
5742df0f
MHY		 934static void esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
935 struct mlx5_vport *vport)
936{
937 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
938 struct mlx5_flow_group *vlan_grp = NULL;
939 struct mlx5_flow_group *drop_grp = NULL;
940 struct mlx5_core_dev *dev = esw->dev;
941 struct mlx5_flow_namespace *root_ns;
942 struct mlx5_flow_table *acl;
943 void *match_criteria;
944 u32 *flow_group_in;
945 /* The egress acl table contains 2 rules:
946 * 1)Allow traffic with vlan_tag=vst_vlan_id
947 * 2)Drop all other traffic.
948 */
949 int table_size = 2;
950 int err = 0;
951
01f51f22
MHY		 952 if (!MLX5_CAP_ESW_EGRESS_ACL(dev, ft_support) ||
953 !IS_ERR_OR_NULL(vport->egress.acl))
5742df0f
MHY		 954 return;
955
956 esw_debug(dev, "Create vport[%d] egress ACL log_max_size(%d)\n",
957 vport->vport, MLX5_CAP_ESW_EGRESS_ACL(dev, log_max_ft_size));
958
959 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_EGRESS);
960 if (!root_ns) {
961 esw_warn(dev, "Failed to get E-Switch egress flow namespace\n");
962 return;
963 }
964
965 flow_group_in = mlx5_vzalloc(inlen);
966 if (!flow_group_in)
967 return;
968
969 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 970 if (IS_ERR(acl)) {
5742df0f
MHY		 971 err = PTR_ERR(acl);
972 esw_warn(dev, "Failed to create E-Switch vport[%d] egress flow Table, err(%d)\n",
973 vport->vport, err);
974 goto out;
975 }
976
977 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
978 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
979 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
980 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.first_vid);
981 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
982 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
983
984 vlan_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 985 if (IS_ERR(vlan_grp)) {
5742df0f
MHY		 986 err = PTR_ERR(vlan_grp);
987 esw_warn(dev, "Failed to create E-Switch vport[%d] egress allowed vlans flow group, err(%d)\n",
988 vport->vport, err);
989 goto out;
990 }
991
992 memset(flow_group_in, 0, inlen);
993 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
994 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
995 drop_grp = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 996 if (IS_ERR(drop_grp)) {
5742df0f
MHY		 997 err = PTR_ERR(drop_grp);
998 esw_warn(dev, "Failed to create E-Switch vport[%d] egress drop flow group, err(%d)\n",
999 vport->vport, err);
1000 goto out;
1001 }
1002
1003 vport->egress.acl = acl;
1004 vport->egress.drop_grp = drop_grp;
1005 vport->egress.allowed_vlans_grp = vlan_grp;
1006out:
3fe3d819 1007 kvfree(flow_group_in);
5742df0f
MHY		 1008 if (err && !IS_ERR_OR_NULL(vlan_grp))
1009 mlx5_destroy_flow_group(vlan_grp);
1010 if (err && !IS_ERR_OR_NULL(acl))
1011 mlx5_destroy_flow_table(acl);
1012}
1013
dfcb1ed3
MHY		 1014static void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
1015 struct mlx5_vport *vport)
1016{
1017 if (!IS_ERR_OR_NULL(vport->egress.allowed_vlan))
1018 mlx5_del_flow_rule(vport->egress.allowed_vlan);
1019
1020 if (!IS_ERR_OR_NULL(vport->egress.drop_rule))
1021 mlx5_del_flow_rule(vport->egress.drop_rule);
1022
1023 vport->egress.allowed_vlan = NULL;
1024 vport->egress.drop_rule = NULL;
1025}
1026
5742df0f
MHY		 1027static void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
1028 struct mlx5_vport *vport)
1029{
1030 if (IS_ERR_OR_NULL(vport->egress.acl))
1031 return;
1032
1033 esw_debug(esw->dev, "Destroy vport[%d] E-Switch egress ACL\n", vport->vport);
1034
dfcb1ed3 1035 esw_vport_cleanup_egress_rules(esw, vport);
5742df0f
MHY		 1036 mlx5_destroy_flow_group(vport->egress.allowed_vlans_grp);
1037 mlx5_destroy_flow_group(vport->egress.drop_grp);
1038 mlx5_destroy_flow_table(vport->egress.acl);
1039 vport->egress.allowed_vlans_grp = NULL;
1040 vport->egress.drop_grp = NULL;
1041 vport->egress.acl = NULL;
1042}
1043
1044static void esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
1045 struct mlx5_vport *vport)
1046{
1047 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1048 struct mlx5_core_dev *dev = esw->dev;
1049 struct mlx5_flow_namespace *root_ns;
1050 struct mlx5_flow_table *acl;
1051 struct mlx5_flow_group *g;
1052 void *match_criteria;
1053 u32 *flow_group_in;
1054 /* The ingress acl table contains 4 groups
1055 * (2 active rules at the same time -
1056 * 1 allow rule from one of the first 3 groups.
1057 * 1 drop rule from the last group):
1058 * 1)Allow untagged traffic with smac=original mac.
1059 * 2)Allow untagged traffic.
1060 * 3)Allow traffic with smac=original mac.
1061 * 4)Drop all other traffic.
1062 */
1063 int table_size = 4;
1064 int err = 0;
1065
01f51f22
MHY		 1066 if (!MLX5_CAP_ESW_INGRESS_ACL(dev, ft_support) ||
1067 !IS_ERR_OR_NULL(vport->ingress.acl))
5742df0f
MHY		 1068 return;
1069
1070 esw_debug(dev, "Create vport[%d] ingress ACL log_max_size(%d)\n",
1071 vport->vport, MLX5_CAP_ESW_INGRESS_ACL(dev, log_max_ft_size));
1072
1073 root_ns = mlx5_get_flow_namespace(dev, MLX5_FLOW_NAMESPACE_ESW_INGRESS);
1074 if (!root_ns) {
1075 esw_warn(dev, "Failed to get E-Switch ingress flow namespace\n");
1076 return;
1077 }
1078
1079 flow_group_in = mlx5_vzalloc(inlen);
1080 if (!flow_group_in)
1081 return;
1082
1083 acl = mlx5_create_vport_flow_table(root_ns, 0, table_size, 0, vport->vport);
3f42ac66 1084 if (IS_ERR(acl)) {
5742df0f
MHY		 1085 err = PTR_ERR(acl);
1086 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress flow Table, err(%d)\n",
1087 vport->vport, err);
1088 goto out;
1089 }
1090 vport->ingress.acl = acl;
1091
1092 match_criteria = MLX5_ADDR_OF(create_flow_group_in, flow_group_in, match_criteria);
1093
1094 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1095 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1096 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1097 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1098 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 0);
1099 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 0);
1100
1101 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1102 if (IS_ERR(g)) {
5742df0f
MHY		 1103 err = PTR_ERR(g);
1104 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged spoofchk flow group, err(%d)\n",
1105 vport->vport, err);
1106 goto out;
1107 }
1108 vport->ingress.allow_untagged_spoofchk_grp = g;
1109
1110 memset(flow_group_in, 0, inlen);
1111 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1112 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.vlan_tag);
1113 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 1);
1114 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 1);
1115
1116 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1117 if (IS_ERR(g)) {
5742df0f
MHY		 1118 err = PTR_ERR(g);
1119 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress untagged flow group, err(%d)\n",
1120 vport->vport, err);
1121 goto out;
1122 }
1123 vport->ingress.allow_untagged_only_grp = g;
1124
1125 memset(flow_group_in, 0, inlen);
1126 MLX5_SET(create_flow_group_in, flow_group_in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1127 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_47_16);
1128 MLX5_SET_TO_ONES(fte_match_param, match_criteria, outer_headers.smac_15_0);
1129 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 2);
1130 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 2);
1131
1132 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1133 if (IS_ERR(g)) {
5742df0f
MHY		 1134 err = PTR_ERR(g);
1135 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress spoofchk flow group, err(%d)\n",
1136 vport->vport, err);
1137 goto out;
1138 }
1139 vport->ingress.allow_spoofchk_only_grp = g;
1140
1141 memset(flow_group_in, 0, inlen);
1142 MLX5_SET(create_flow_group_in, flow_group_in, start_flow_index, 3);
1143 MLX5_SET(create_flow_group_in, flow_group_in, end_flow_index, 3);
1144
1145 g = mlx5_create_flow_group(acl, flow_group_in);
3f42ac66 1146 if (IS_ERR(g)) {
5742df0f
MHY		 1147 err = PTR_ERR(g);
1148 esw_warn(dev, "Failed to create E-Switch vport[%d] ingress drop flow group, err(%d)\n",
1149 vport->vport, err);
1150 goto out;
1151 }
1152 vport->ingress.drop_grp = g;
1153
1154out:
1155 if (err) {
1156 if (!IS_ERR_OR_NULL(vport->ingress.allow_spoofchk_only_grp))
1157 mlx5_destroy_flow_group(
1158 vport->ingress.allow_spoofchk_only_grp);
1159 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_only_grp))
1160 mlx5_destroy_flow_group(
1161 vport->ingress.allow_untagged_only_grp);
1162 if (!IS_ERR_OR_NULL(vport->ingress.allow_untagged_spoofchk_grp))
1163 mlx5_destroy_flow_group(
1164 vport->ingress.allow_untagged_spoofchk_grp);
1165 if (!IS_ERR_OR_NULL(vport->ingress.acl))
1166 mlx5_destroy_flow_table(vport->ingress.acl);
1167 }
1168
3fe3d819 1169 kvfree(flow_group_in);
5742df0f
MHY		 1170}
1171
dfcb1ed3
MHY		 1172static void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
1173 struct mlx5_vport *vport)
1174{
1175 if (!IS_ERR_OR_NULL(vport->ingress.drop_rule))
1176 mlx5_del_flow_rule(vport->ingress.drop_rule);
f942380c
MHY		 1177
1178 if (!IS_ERR_OR_NULL(vport->ingress.allow_rule))
1179 mlx5_del_flow_rule(vport->ingress.allow_rule);
1180
dfcb1ed3 1181 vport->ingress.drop_rule = NULL;
f942380c 1182 vport->ingress.allow_rule = NULL;
dfcb1ed3
MHY		 1183}
1184
5742df0f
MHY		 1185static void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
1186 struct mlx5_vport *vport)
1187{
1188 if (IS_ERR_OR_NULL(vport->ingress.acl))
1189 return;
1190
1191 esw_debug(esw->dev, "Destroy vport[%d] E-Switch ingress ACL\n", vport->vport);
1192
dfcb1ed3 1193 esw_vport_cleanup_ingress_rules(esw, vport);
5742df0f
MHY		 1194 mlx5_destroy_flow_group(vport->ingress.allow_spoofchk_only_grp);
1195 mlx5_destroy_flow_group(vport->ingress.allow_untagged_only_grp);
1196 mlx5_destroy_flow_group(vport->ingress.allow_untagged_spoofchk_grp);
1197 mlx5_destroy_flow_group(vport->ingress.drop_grp);
1198 mlx5_destroy_flow_table(vport->ingress.acl);
1199 vport->ingress.acl = NULL;
1200 vport->ingress.drop_grp = NULL;
1201 vport->ingress.allow_spoofchk_only_grp = NULL;
1202 vport->ingress.allow_untagged_only_grp = NULL;
1203 vport->ingress.allow_untagged_spoofchk_grp = NULL;
1204}
1205
dfcb1ed3
MHY		 1206static int esw_vport_ingress_config(struct mlx5_eswitch *esw,
1207 struct mlx5_vport *vport)
1208{
c5bb1730 1209 struct mlx5_flow_spec *spec;
dfcb1ed3 1210 int err = 0;
f942380c 1211 u8 *smac_v;
dfcb1ed3 1212
1ab2068a
MHY		 1213 if (vport->info.spoofchk && !is_valid_ether_addr(vport->info.mac)) {
1214 mlx5_core_warn(esw->dev,
1215 "vport[%d] configure ingress rules failed, illegal mac with spoofchk\n",
1216 vport->vport);
1217 return -EPERM;
f942380c 1218
f942380c
MHY		 1219 }
1220
dfcb1ed3
MHY		 1221 esw_vport_cleanup_ingress_rules(esw, vport);
1222
1ab2068a 1223 if (!vport->info.vlan && !vport->info.qos && !vport->info.spoofchk) {
01f51f22 1224 esw_vport_disable_ingress_acl(esw, vport);
dfcb1ed3 1225 return 0;
01f51f22
MHY		 1226 }
1227
1228 esw_vport_enable_ingress_acl(esw, vport);
dfcb1ed3
MHY		 1229
1230 esw_debug(esw->dev,
1231 "vport[%d] configure ingress rules, vlan(%d) qos(%d)\n",
1ab2068a 1232 vport->vport, vport->info.vlan, vport->info.qos);
dfcb1ed3 1233
c5bb1730
MG		 1234 spec = mlx5_vzalloc(sizeof(*spec));
1235 if (!spec) {
dfcb1ed3
MHY		 1236 err = -ENOMEM;
1237 esw_warn(esw->dev, "vport[%d] configure ingress rules failed, err(%d)\n",
1238 vport->vport, err);
1239 goto out;
1240 }
dfcb1ed3 1241
1ab2068a 1242 if (vport->info.vlan || vport->info.qos)
c5bb1730 1243 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);
f942380c 1244
1ab2068a 1245 if (vport->info.spoofchk) {
c5bb1730
MG		 1246 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_47_16);
1247 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.smac_15_0);
f942380c 1248 smac_v = MLX5_ADDR_OF(fte_match_param,
c5bb1730 1249 spec->match_value,
f942380c 1250 outer_headers.smac_47_16);
1ab2068a 1251 ether_addr_copy(smac_v, vport->info.mac);
f942380c
MHY		 1252 }
1253
c5bb1730 1254 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
f942380c 1255 vport->ingress.allow_rule =
c5bb1730 1256 mlx5_add_flow_rule(vport->ingress.acl, spec,
f942380c
MHY		 1257 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1258 0, NULL);
3f42ac66 1259 if (IS_ERR(vport->ingress.allow_rule)) {
f942380c 1260 err = PTR_ERR(vport->ingress.allow_rule);
2974ab6e
SM		 1261 esw_warn(esw->dev,
1262 "vport[%d] configure ingress allow rule, err(%d)\n",
1263 vport->vport, err);
f942380c
MHY		 1264 vport->ingress.allow_rule = NULL;
1265 goto out;
1266 }
1267
c5bb1730 1268 memset(spec, 0, sizeof(*spec));
f942380c 1269 vport->ingress.drop_rule =
c5bb1730 1270 mlx5_add_flow_rule(vport->ingress.acl, spec,
dfcb1ed3
MHY		 1271 MLX5_FLOW_CONTEXT_ACTION_DROP,
1272 0, NULL);
3f42ac66 1273 if (IS_ERR(vport->ingress.drop_rule)) {
dfcb1ed3 1274 err = PTR_ERR(vport->ingress.drop_rule);
2974ab6e
SM		 1275 esw_warn(esw->dev,
1276 "vport[%d] configure ingress drop rule, err(%d)\n",
1277 vport->vport, err);
dfcb1ed3 1278 vport->ingress.drop_rule = NULL;
f942380c 1279 goto out;
dfcb1ed3 1280 }
f942380c 1281
dfcb1ed3 1282out:
f942380c
MHY		 1283 if (err)
1284 esw_vport_cleanup_ingress_rules(esw, vport);
c5bb1730 1285 kvfree(spec);
dfcb1ed3
MHY		 1286 return err;
1287}
1288
1289static int esw_vport_egress_config(struct mlx5_eswitch *esw,
1290 struct mlx5_vport *vport)
1291{
c5bb1730 1292 struct mlx5_flow_spec *spec;
dfcb1ed3
MHY		 1293 int err = 0;
1294
dfcb1ed3
MHY		 1295 esw_vport_cleanup_egress_rules(esw, vport);
1296
1ab2068a 1297 if (!vport->info.vlan && !vport->info.qos) {
01f51f22 1298 esw_vport_disable_egress_acl(esw, vport);
dfcb1ed3 1299 return 0;
01f51f22
MHY		 1300 }
1301
1302 esw_vport_enable_egress_acl(esw, vport);
dfcb1ed3
MHY		 1303
1304 esw_debug(esw->dev,
1305 "vport[%d] configure egress rules, vlan(%d) qos(%d)\n",
1ab2068a 1306 vport->vport, vport->info.vlan, vport->info.qos);
dfcb1ed3 1307
c5bb1730
MG		 1308 spec = mlx5_vzalloc(sizeof(*spec));
1309 if (!spec) {
dfcb1ed3
MHY		 1310 err = -ENOMEM;
1311 esw_warn(esw->dev, "vport[%d] configure egress rules failed, err(%d)\n",
1312 vport->vport, err);
1313 goto out;
1314 }
1315
1316 /* Allowed vlan rule */
c5bb1730
MG		 1317 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.vlan_tag);
1318 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.vlan_tag);
1319 MLX5_SET_TO_ONES(fte_match_param, spec->match_criteria, outer_headers.first_vid);
1ab2068a 1320 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vport->info.vlan);
dfcb1ed3 1321
c5bb1730 1322 spec->match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
dfcb1ed3 1323 vport->egress.allowed_vlan =
c5bb1730 1324 mlx5_add_flow_rule(vport->egress.acl, spec,
dfcb1ed3
MHY		 1325 MLX5_FLOW_CONTEXT_ACTION_ALLOW,
1326 0, NULL);
3f42ac66 1327 if (IS_ERR(vport->egress.allowed_vlan)) {
dfcb1ed3 1328 err = PTR_ERR(vport->egress.allowed_vlan);
2974ab6e
SM		 1329 esw_warn(esw->dev,
1330 "vport[%d] configure egress allowed vlan rule failed, err(%d)\n",
1331 vport->vport, err);
dfcb1ed3
MHY		 1332 vport->egress.allowed_vlan = NULL;
1333 goto out;
1334 }
1335
1336 /* Drop others rule (star rule) */
c5bb1730 1337 memset(spec, 0, sizeof(*spec));
dfcb1ed3 1338 vport->egress.drop_rule =
c5bb1730 1339 mlx5_add_flow_rule(vport->egress.acl, spec,
dfcb1ed3
MHY		 1340 MLX5_FLOW_CONTEXT_ACTION_DROP,
1341 0, NULL);
3f42ac66 1342 if (IS_ERR(vport->egress.drop_rule)) {
dfcb1ed3 1343 err = PTR_ERR(vport->egress.drop_rule);
2974ab6e
SM		 1344 esw_warn(esw->dev,
1345 "vport[%d] configure egress drop rule failed, err(%d)\n",
1346 vport->vport, err);
dfcb1ed3
MHY		 1347 vport->egress.drop_rule = NULL;
1348 }
1349out:
c5bb1730 1350 kvfree(spec);
dfcb1ed3
MHY		 1351 return err;
1352}
1353
1bd27b11
MHY		 1354/* Vport QoS management */
1355static int esw_create_tsar(struct mlx5_eswitch *esw)
1356{
1357 u32 tsar_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
1358 struct mlx5_core_dev *dev = esw->dev;
1359 int err;
1360
1361 if (!MLX5_CAP_GEN(dev, qos) || !MLX5_CAP_QOS(dev, esw_scheduling))
1362 return 0;
1363
1364 if (esw->qos.enabled)
1365 return -EEXIST;
1366
1367 err = mlx5_create_scheduling_element_cmd(dev,
1368 SCHEDULING_HIERARCHY_E_SWITCH,
1369 &tsar_ctx,
1370 &esw->qos.root_tsar_id);
1371 if (err) {
1372 esw_warn(esw->dev, "E-Switch create TSAR failed (%d)\n", err);
1373 return err;
1374 }
1375
1376 esw->qos.enabled = true;
1377 return 0;
1378}
1379
1380static void esw_destroy_tsar(struct mlx5_eswitch *esw)
1381{
1382 int err;
1383
1384 if (!esw->qos.enabled)
1385 return;
1386
1387 err = mlx5_destroy_scheduling_element_cmd(esw->dev,
1388 SCHEDULING_HIERARCHY_E_SWITCH,
1389 esw->qos.root_tsar_id);
1390 if (err)
1391 esw_warn(esw->dev, "E-Switch destroy TSAR failed (%d)\n", err);
1392
1393 esw->qos.enabled = false;
1394}
1395
1396static int esw_vport_enable_qos(struct mlx5_eswitch *esw, int vport_num,
1397 u32 initial_max_rate)
1398{
1399 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0};
1400 struct mlx5_vport *vport = &esw->vports[vport_num];
1401 struct mlx5_core_dev *dev = esw->dev;
1402 void *vport_elem;
1403 int err = 0;
1404
1405 if (!esw->qos.enabled || !MLX5_CAP_GEN(dev, qos) ||
1406 !MLX5_CAP_QOS(dev, esw_scheduling))
1407 return 0;
1408
1409 if (vport->qos.enabled)
1410 return -EEXIST;
1411
1412 MLX5_SET(scheduling_context, &sched_ctx, element_type,
1413 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT);
1414 vport_elem = MLX5_ADDR_OF(scheduling_context, &sched_ctx,
1415 element_attributes);
1416 MLX5_SET(vport_element, vport_elem, vport_number, vport_num);
1417 MLX5_SET(scheduling_context, &sched_ctx, parent_element_id,
1418 esw->qos.root_tsar_id);
1419 MLX5_SET(scheduling_context, &sched_ctx, max_average_bw,
1420 initial_max_rate);
1421
1422 err = mlx5_create_scheduling_element_cmd(dev,
1423 SCHEDULING_HIERARCHY_E_SWITCH,
1424 &sched_ctx,
1425 &vport->qos.esw_tsar_ix);
1426 if (err) {
1427 esw_warn(esw->dev, "E-Switch create TSAR vport element failed (vport=%d,err=%d)\n",
1428 vport_num, err);
1429 return err;
1430 }
1431
1432 vport->qos.enabled = true;
1433 return 0;
1434}
1435
1436static void esw_vport_disable_qos(struct mlx5_eswitch *esw, int vport_num)
1437{
1438 struct mlx5_vport *vport = &esw->vports[vport_num];
1439 int err = 0;
1440
1441 if (!vport->qos.enabled)
1442 return;
1443
1444 err = mlx5_destroy_scheduling_element_cmd(esw->dev,
1445 SCHEDULING_HIERARCHY_E_SWITCH,
1446 vport->qos.esw_tsar_ix);
1447 if (err)
1448 esw_warn(esw->dev, "E-Switch destroy TSAR vport element failed (vport=%d,err=%d)\n",
1449 vport_num, err);
1450
1451 vport->qos.enabled = false;
1452}
1453
1ab2068a
MHY		 1454static void node_guid_gen_from_mac(u64 *node_guid, u8 mac[ETH_ALEN])
1455{
1456 ((u8 *)node_guid)[7] = mac[0];
1457 ((u8 *)node_guid)[6] = mac[1];
1458 ((u8 *)node_guid)[5] = mac[2];
1459 ((u8 *)node_guid)[4] = 0xff;
1460 ((u8 *)node_guid)[3] = 0xfe;
1461 ((u8 *)node_guid)[2] = mac[3];
1462 ((u8 *)node_guid)[1] = mac[4];
1463 ((u8 *)node_guid)[0] = mac[5];
1464}
1465
1466static void esw_apply_vport_conf(struct mlx5_eswitch *esw,
1467 struct mlx5_vport *vport)
1468{
1469 int vport_num = vport->vport;
1470
1471 if (!vport_num)
1472 return;
1473
1474 mlx5_modify_vport_admin_state(esw->dev,
1475 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1476 vport_num,
1477 vport->info.link_state);
1478 mlx5_modify_nic_vport_mac_address(esw->dev, vport_num, vport->info.mac);
1479 mlx5_modify_nic_vport_node_guid(esw->dev, vport_num, vport->info.node_guid);
1480 modify_esw_vport_cvlan(esw->dev, vport_num, vport->info.vlan, vport->info.qos,
1481 (vport->info.vlan || vport->info.qos));
1482
1483 /* Only legacy mode needs ACLs */
1484 if (esw->mode == SRIOV_LEGACY) {
1485 esw_vport_ingress_config(esw, vport);
1486 esw_vport_egress_config(esw, vport);
1487 }
1488}
1bd27b11 1489
81848731
SM		 1490static void esw_enable_vport(struct mlx5_eswitch *esw, int vport_num,
1491 int enable_events)
073bb189
SM		 1492{
1493 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189 1494
dfcb1ed3 1495 mutex_lock(&esw->state_lock);
81848731
SM		 1496 WARN_ON(vport->enabled);
1497
1498 esw_debug(esw->dev, "Enabling VPORT(%d)\n", vport_num);
5742df0f 1499
1ab2068a
MHY		 1500 /* Restore old vport configuration */
1501 esw_apply_vport_conf(esw, vport);
81848731 1502
1bd27b11
MHY		 1503 /* Attach vport to the eswitch rate limiter */
1504 if (esw_vport_enable_qos(esw, vport_num, vport->info.max_rate))
1505 esw_warn(esw->dev, "Failed to attach vport %d to eswitch rate limiter", vport_num);
1506
81848731
SM		 1507 /* Sync with current vport context */
1508 vport->enabled_events = enable_events;
073bb189 1509 vport->enabled = true;
073bb189 1510
a35f71f2 1511 /* only PF is trusted by default */
1ab2068a
MHY		 1512 if (!vport_num)
1513 vport->info.trusted = true;
1514
25fff58c 1515 esw_vport_change_handle_locked(vport);
81848731
SM		 1516
1517 esw->enabled_vports++;
1518 esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num);
dfcb1ed3 1519 mutex_unlock(&esw->state_lock);
81848731
SM		 1520}
1521
073bb189
SM		 1522static void esw_disable_vport(struct mlx5_eswitch *esw, int vport_num)
1523{
1524 struct mlx5_vport *vport = &esw->vports[vport_num];
073bb189
SM		 1525
1526 if (!vport->enabled)
1527 return;
1528
81848731 1529 esw_debug(esw->dev, "Disabling vport(%d)\n", vport_num);
073bb189 1530 /* Mark this vport as disabled to discard new events */
073bb189 1531 vport->enabled = false;
831cae1d
MHY		 1532
1533 synchronize_irq(mlx5_get_msix_vec(esw->dev, MLX5_EQ_VEC_ASYNC));
073bb189
SM		 1534 /* Wait for current already scheduled events to complete */
1535 flush_workqueue(esw->work_queue);
073bb189
SM		 1536 /* Disable events from this vport */
1537 arm_vport_context_events_cmd(esw->dev, vport->vport, 0);
dfcb1ed3 1538 mutex_lock(&esw->state_lock);
586cfa7f
MHY		 1539 /* We don't assume VFs will cleanup after themselves.
1540 * Calling vport change handler while vport is disabled will cleanup
1541 * the vport resources.
1542 */
1edc57e2 1543 esw_vport_change_handle_locked(vport);
586cfa7f 1544 vport->enabled_events = 0;
1bd27b11 1545 esw_vport_disable_qos(esw, vport_num);
f96750f8 1546 if (vport_num && esw->mode == SRIOV_LEGACY) {
1ab2068a
MHY		 1547 mlx5_modify_vport_admin_state(esw->dev,
1548 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1549 vport_num,
1550 MLX5_ESW_VPORT_ADMIN_STATE_DOWN);
5742df0f
MHY		 1551 esw_vport_disable_egress_acl(esw, vport);
1552 esw_vport_disable_ingress_acl(esw, vport);
1553 }
81848731 1554 esw->enabled_vports--;
dfcb1ed3 1555 mutex_unlock(&esw->state_lock);
073bb189
SM		 1556}
1557
1558/* Public E-Switch API */
6ab36e35 1559int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode)
81848731
SM		 1560{
1561 int err;
69697b6e 1562 int i, enabled_events;
81848731
SM		 1563
1564 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1565 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1566 return 0;
1567
1568 if (!MLX5_CAP_GEN(esw->dev, eswitch_flow_table) ||
1569 !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, ft_support)) {
1570 esw_warn(esw->dev, "E-Switch FDB is not supported, aborting ...\n");
1571 return -ENOTSUPP;
1572 }
1573
5742df0f
MHY		 1574 if (!MLX5_CAP_ESW_INGRESS_ACL(esw->dev, ft_support))
1575 esw_warn(esw->dev, "E-Switch ingress ACL is not supported by FW\n");
1576
1577 if (!MLX5_CAP_ESW_EGRESS_ACL(esw->dev, ft_support))
1578 esw_warn(esw->dev, "E-Switch engress ACL is not supported by FW\n");
1579
6ab36e35 1580 esw_info(esw->dev, "E-Switch enable SRIOV: nvfs(%d) mode (%d)\n", nvfs, mode);
6ab36e35 1581 esw->mode = mode;
81848731
SM		 1582 esw_disable_vport(esw, 0);
1583
69697b6e
OG		 1584 if (mode == SRIOV_LEGACY)
1585 err = esw_create_legacy_fdb_table(esw, nvfs + 1);
1586 else
c930a3ad 1587 err = esw_offloads_init(esw, nvfs + 1);
81848731
SM		 1588 if (err)
1589 goto abort;
1590
1bd27b11
MHY		 1591 err = esw_create_tsar(esw);
1592 if (err)
1593 esw_warn(esw->dev, "Failed to create eswitch TSAR");
1594
69697b6e 1595 enabled_events = (mode == SRIOV_LEGACY) ? SRIOV_VPORT_EVENTS : UC_ADDR_CHANGE;
81848731 1596 for (i = 0; i <= nvfs; i++)
69697b6e 1597 esw_enable_vport(esw, i, enabled_events);
81848731
SM		 1598
1599 esw_info(esw->dev, "SRIOV enabled: active vports(%d)\n",
1600 esw->enabled_vports);
1601 return 0;
1602
1603abort:
1604 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
4eea37d7 1605 esw->mode = SRIOV_NONE;
81848731
SM		 1606 return err;
1607}
1608
1609void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw)
1610{
a35f71f2 1611 struct esw_mc_addr *mc_promisc;
c930a3ad 1612 int nvports;
81848731
SM		 1613 int i;
1614
1615 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1616 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1617 return;
1618
6ab36e35
OG		 1619 esw_info(esw->dev, "disable SRIOV: active vports(%d) mode(%d)\n",
1620 esw->enabled_vports, esw->mode);
81848731 1621
a35f71f2 1622 mc_promisc = esw->mc_promisc;
c930a3ad 1623 nvports = esw->enabled_vports;
a35f71f2 1624
81848731
SM		 1625 for (i = 0; i < esw->total_vports; i++)
1626 esw_disable_vport(esw, i);
1627
a35f71f2
MHY		 1628 if (mc_promisc && mc_promisc->uplink_rule)
1629 mlx5_del_flow_rule(mc_promisc->uplink_rule);
1630
1bd27b11
MHY		 1631 esw_destroy_tsar(esw);
1632
69697b6e
OG		 1633 if (esw->mode == SRIOV_LEGACY)
1634 esw_destroy_legacy_fdb_table(esw);
c930a3ad
OG		 1635 else if (esw->mode == SRIOV_OFFLOADS)
1636 esw_offloads_cleanup(esw, nvports);
81848731 1637
6ab36e35 1638 esw->mode = SRIOV_NONE;
81848731
SM		 1639 /* VPORT 0 (PF) must be enabled back with non-sriov configuration */
1640 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1641}
1642
62a9b90a
MHY		 1643void mlx5_eswitch_attach(struct mlx5_eswitch *esw)
1644{
1645 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1646 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1647 return;
1648
1649 esw_enable_vport(esw, 0, UC_ADDR_CHANGE);
1650 /* VF Vports will be enabled when SRIOV is enabled */
1651}
1652
1653void mlx5_eswitch_detach(struct mlx5_eswitch *esw)
1654{
1655 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1656 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1657 return;
1658
1659 esw_disable_vport(esw, 0);
1660}
1661
073bb189
SM		 1662int mlx5_eswitch_init(struct mlx5_core_dev *dev)
1663{
1664 int l2_table_size = 1 << MLX5_CAP_GEN(dev, log_max_l2_table);
efdc810b 1665 int total_vports = MLX5_TOTAL_VPORTS(dev);
a35f71f2 1666 struct esw_mc_addr *mc_promisc;
073bb189
SM		 1667 struct mlx5_eswitch *esw;
1668 int vport_num;
1669 int err;
1670
1671 if (!MLX5_CAP_GEN(dev, vport_group_manager) ||
1672 MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1673 return 0;
1674
1675 esw_info(dev,
1676 "Total vports %d, l2 table size(%d), per vport: max uc(%d) max mc(%d)\n",
1677 total_vports, l2_table_size,
1678 MLX5_MAX_UC_PER_VPORT(dev),
1679 MLX5_MAX_MC_PER_VPORT(dev));
1680
1681 esw = kzalloc(sizeof(*esw), GFP_KERNEL);
1682 if (!esw)
1683 return -ENOMEM;
1684
1685 esw->dev = dev;
1686
1687 esw->l2_table.bitmap = kcalloc(BITS_TO_LONGS(l2_table_size),
1688 sizeof(uintptr_t), GFP_KERNEL);
1689 if (!esw->l2_table.bitmap) {
1690 err = -ENOMEM;
1691 goto abort;
1692 }
1693 esw->l2_table.size = l2_table_size;
1694
a35f71f2
MHY		 1695 mc_promisc = kzalloc(sizeof(*mc_promisc), GFP_KERNEL);
1696 if (!mc_promisc) {
1697 err = -ENOMEM;
1698 goto abort;
1699 }
1700 esw->mc_promisc = mc_promisc;
1701
073bb189
SM		 1702 esw->work_queue = create_singlethread_workqueue("mlx5_esw_wq");
1703 if (!esw->work_queue) {
1704 err = -ENOMEM;
1705 goto abort;
1706 }
1707
1708 esw->vports = kcalloc(total_vports, sizeof(struct mlx5_vport),
1709 GFP_KERNEL);
1710 if (!esw->vports) {
1711 err = -ENOMEM;
1712 goto abort;
1713 }
1714
127ea380
HHZ		 1715 esw->offloads.vport_reps =
1716 kzalloc(total_vports * sizeof(struct mlx5_eswitch_rep),
1717 GFP_KERNEL);
1718 if (!esw->offloads.vport_reps) {
1719 err = -ENOMEM;
1720 goto abort;
1721 }
1722
dfcb1ed3
MHY		 1723 mutex_init(&esw->state_lock);
1724
073bb189
SM		 1725 for (vport_num = 0; vport_num < total_vports; vport_num++) {
1726 struct mlx5_vport *vport = &esw->vports[vport_num];
1727
1728 vport->vport = vport_num;
1ab2068a 1729 vport->info.link_state = MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
073bb189
SM		 1730 vport->dev = dev;
1731 INIT_WORK(&vport->vport_change_handler,
1732 esw_vport_change_handler);
073bb189
SM		 1733 }
1734
81848731
SM		 1735 esw->total_vports = total_vports;
1736 esw->enabled_vports = 0;
6ab36e35 1737 esw->mode = SRIOV_NONE;
073bb189 1738
81848731 1739 dev->priv.eswitch = esw;
073bb189
SM		 1740 return 0;
1741abort:
1742 if (esw->work_queue)
1743 destroy_workqueue(esw->work_queue);
1744 kfree(esw->l2_table.bitmap);
1745 kfree(esw->vports);
127ea380 1746 kfree(esw->offloads.vport_reps);
073bb189
SM		 1747 kfree(esw);
1748 return err;
1749}
1750
1751void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw)
1752{
1753 if (!esw || !MLX5_CAP_GEN(esw->dev, vport_group_manager) ||
1754 MLX5_CAP_GEN(esw->dev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1755 return;
1756
1757 esw_info(esw->dev, "cleanup\n");
073bb189
SM		 1758
1759 esw->dev->priv.eswitch = NULL;
1760 destroy_workqueue(esw->work_queue);
1761 kfree(esw->l2_table.bitmap);
a35f71f2 1762 kfree(esw->mc_promisc);
127ea380 1763 kfree(esw->offloads.vport_reps);
073bb189
SM		 1764 kfree(esw->vports);
1765 kfree(esw);
1766}
1767
1768void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe)
1769{
1770 struct mlx5_eqe_vport_change *vc_eqe = &eqe->data.vport_change;
1771 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
1772 struct mlx5_vport *vport;
1773
1774 if (!esw) {
1775 pr_warn("MLX5 E-Switch: vport %d got an event while eswitch is not initialized\n",
1776 vport_num);
1777 return;
1778 }
1779
1780 vport = &esw->vports[vport_num];
073bb189
SM		 1781 if (vport->enabled)
1782 queue_work(esw->work_queue, &vport->vport_change_handler);
073bb189 1783}
77256579
SM		 1784
1785/* Vport Administration */
1786#define ESW_ALLOWED(esw) \
1787 (esw && MLX5_CAP_GEN(esw->dev, vport_group_manager) && mlx5_core_is_pf(esw->dev))
1788#define LEGAL_VPORT(esw, vport) (vport >= 0 && vport < esw->total_vports)
1789
1790int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
1791 int vport, u8 mac[ETH_ALEN])
1792{
f942380c 1793 struct mlx5_vport *evport;
23898c76
NO		 1794 u64 node_guid;
1795 int err = 0;
77256579
SM		 1796
1797 if (!ESW_ALLOWED(esw))
1798 return -EPERM;
1799 if (!LEGAL_VPORT(esw, vport))
1800 return -EINVAL;
1801
1ab2068a 1802 mutex_lock(&esw->state_lock);
f942380c
MHY		 1803 evport = &esw->vports[vport];
1804
1ab2068a 1805 if (evport->info.spoofchk && !is_valid_ether_addr(mac)) {
f942380c
MHY		 1806 mlx5_core_warn(esw->dev,
1807 "MAC invalidation is not allowed when spoofchk is on, vport(%d)\n",
1808 vport);
1ab2068a
MHY		 1809 err = -EPERM;
1810 goto unlock;
f942380c
MHY		 1811 }
1812
77256579
SM		 1813 err = mlx5_modify_nic_vport_mac_address(esw->dev, vport, mac);
1814 if (err) {
1815 mlx5_core_warn(esw->dev,
1816 "Failed to mlx5_modify_nic_vport_mac vport(%d) err=(%d)\n",
1817 vport, err);
1ab2068a 1818 goto unlock;
77256579
SM		 1819 }
1820
23898c76
NO		 1821 node_guid_gen_from_mac(&node_guid, mac);
1822 err = mlx5_modify_nic_vport_node_guid(esw->dev, vport, node_guid);
1823 if (err)
1824 mlx5_core_warn(esw->dev,
1825 "Failed to set vport %d node guid, err = %d. RDMA_CM will not function properly for this VF.\n",
1826 vport, err);
1827
1ab2068a
MHY		 1828 ether_addr_copy(evport->info.mac, mac);
1829 evport->info.node_guid = node_guid;
f96750f8 1830 if (evport->enabled && esw->mode == SRIOV_LEGACY)
f942380c 1831 err = esw_vport_ingress_config(esw, evport);
1ab2068a
MHY		 1832
1833unlock:
f942380c 1834 mutex_unlock(&esw->state_lock);
77256579
SM		 1835 return err;
1836}
1837
1838int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
1839 int vport, int link_state)
1840{
1ab2068a
MHY		 1841 struct mlx5_vport *evport;
1842 int err = 0;
1843
77256579
SM		 1844 if (!ESW_ALLOWED(esw))
1845 return -EPERM;
1846 if (!LEGAL_VPORT(esw, vport))
1847 return -EINVAL;
1848
1ab2068a
MHY		 1849 mutex_lock(&esw->state_lock);
1850 evport = &esw->vports[vport];
1851
1852 err = mlx5_modify_vport_admin_state(esw->dev,
1853 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT,
1854 vport, link_state);
1855 if (err) {
1856 mlx5_core_warn(esw->dev,
1857 "Failed to set vport %d link state, err = %d",
1858 vport, err);
1859 goto unlock;
1860 }
1861
1862 evport->info.link_state = link_state;
1863
1864unlock:
1865 mutex_unlock(&esw->state_lock);
1866 return 0;
77256579
SM		 1867}
1868
1869int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
1870 int vport, struct ifla_vf_info *ivi)
1871{
f942380c 1872 struct mlx5_vport *evport;
9e7ea352 1873
77256579
SM		 1874 if (!ESW_ALLOWED(esw))
1875 return -EPERM;
1876 if (!LEGAL_VPORT(esw, vport))
1877 return -EINVAL;
1878
f942380c
MHY		 1879 evport = &esw->vports[vport];
1880
77256579
SM		 1881 memset(ivi, 0, sizeof(*ivi));
1882 ivi->vf = vport - 1;
1883
1ab2068a
MHY		 1884 mutex_lock(&esw->state_lock);
1885 ether_addr_copy(ivi->mac, evport->info.mac);
1886 ivi->linkstate = evport->info.link_state;
1887 ivi->vlan = evport->info.vlan;
1888 ivi->qos = evport->info.qos;
1889 ivi->spoofchk = evport->info.spoofchk;
1890 ivi->trusted = evport->info.trusted;
1891 mutex_unlock(&esw->state_lock);
77256579
SM		 1892
1893 return 0;
1894}
9e7ea352 1895
e33dfe31
OG		 1896int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
1897 int vport, u16 vlan, u8 qos, u8 set_flags)
9e7ea352 1898{
dfcb1ed3
MHY		 1899 struct mlx5_vport *evport;
1900 int err = 0;
9e7ea352
SM		 1901
1902 if (!ESW_ALLOWED(esw))
1903 return -EPERM;
1904 if (!LEGAL_VPORT(esw, vport) || (vlan > 4095) || (qos > 7))
1905 return -EINVAL;
1906
1ab2068a 1907 mutex_lock(&esw->state_lock);
dfcb1ed3
MHY		 1908 evport = &esw->vports[vport];
1909
e33dfe31 1910 err = modify_esw_vport_cvlan(esw->dev, vport, vlan, qos, set_flags);
dfcb1ed3 1911 if (err)
1ab2068a 1912 goto unlock;
dfcb1ed3 1913
1ab2068a
MHY		 1914 evport->info.vlan = vlan;
1915 evport->info.qos = qos;
f96750f8 1916 if (evport->enabled && esw->mode == SRIOV_LEGACY) {
dfcb1ed3
MHY		 1917 err = esw_vport_ingress_config(esw, evport);
1918 if (err)
1ab2068a 1919 goto unlock;
dfcb1ed3
MHY		 1920 err = esw_vport_egress_config(esw, evport);
1921 }
1922
1ab2068a 1923unlock:
dfcb1ed3
MHY		 1924 mutex_unlock(&esw->state_lock);
1925 return err;
9e7ea352 1926}
3b751a2a 1927
e33dfe31
OG		 1928int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
1929 int vport, u16 vlan, u8 qos)
1930{
1931 u8 set_flags = 0;
1932
1933 if (vlan || qos)
1934 set_flags = SET_VLAN_STRIP | SET_VLAN_INSERT;
1935
1936 return __mlx5_eswitch_set_vport_vlan(esw, vport, vlan, qos, set_flags);
1937}
1938
f942380c
MHY		 1939int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
1940 int vport, bool spoofchk)
1941{
1942 struct mlx5_vport *evport;
1943 bool pschk;
1944 int err = 0;
1945
1946 if (!ESW_ALLOWED(esw))
1947 return -EPERM;
1948 if (!LEGAL_VPORT(esw, vport))
1949 return -EINVAL;
1950
f942380c 1951 mutex_lock(&esw->state_lock);
1ab2068a
MHY		 1952 evport = &esw->vports[vport];
1953 pschk = evport->info.spoofchk;
1954 evport->info.spoofchk = spoofchk;
1955 if (evport->enabled && esw->mode == SRIOV_LEGACY)
f942380c 1956 err = esw_vport_ingress_config(esw, evport);
1ab2068a
MHY		 1957 if (err)
1958 evport->info.spoofchk = pschk;
f942380c
MHY		 1959 mutex_unlock(&esw->state_lock);
1960
1961 return err;
1962}
1963
1edc57e2
MHY		 1964int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
1965 int vport, bool setting)
1966{
1967 struct mlx5_vport *evport;
1968
1969 if (!ESW_ALLOWED(esw))
1970 return -EPERM;
1971 if (!LEGAL_VPORT(esw, vport))
1972 return -EINVAL;
1973
1edc57e2 1974 mutex_lock(&esw->state_lock);
1ab2068a
MHY		 1975 evport = &esw->vports[vport];
1976 evport->info.trusted = setting;
1edc57e2
MHY		 1977 if (evport->enabled)
1978 esw_vport_change_handle_locked(evport);
1979 mutex_unlock(&esw->state_lock);
1980
1981 return 0;
1982}
1983
3b751a2a
SM		 1984int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
1985 int vport,
1986 struct ifla_vf_stats *vf_stats)
1987{
1988 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
c4f287c4 1989 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
3b751a2a
SM		 1990 int err = 0;
1991 u32 *out;
1992
1993 if (!ESW_ALLOWED(esw))
1994 return -EPERM;
1995 if (!LEGAL_VPORT(esw, vport))
1996 return -EINVAL;
1997
1998 out = mlx5_vzalloc(outlen);
1999 if (!out)
2000 return -ENOMEM;
2001
3b751a2a
SM		 2002 MLX5_SET(query_vport_counter_in, in, opcode,
2003 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
2004 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
2005 MLX5_SET(query_vport_counter_in, in, vport_number, vport);
2006 if (vport)
2007 MLX5_SET(query_vport_counter_in, in, other_vport, 1);
2008
2009 memset(out, 0, outlen);
2010 err = mlx5_cmd_exec(esw->dev, in, sizeof(in), out, outlen);
2011 if (err)
2012 goto free_out;
2013
2014 #define MLX5_GET_CTR(p, x) \
2015 MLX5_GET64(query_vport_counter_out, p, x)
2016
2017 memset(vf_stats, 0, sizeof(*vf_stats));
2018 vf_stats->rx_packets =
2019 MLX5_GET_CTR(out, received_eth_unicast.packets) +
2020 MLX5_GET_CTR(out, received_eth_multicast.packets) +
2021 MLX5_GET_CTR(out, received_eth_broadcast.packets);
2022
2023 vf_stats->rx_bytes =
2024 MLX5_GET_CTR(out, received_eth_unicast.octets) +
2025 MLX5_GET_CTR(out, received_eth_multicast.octets) +
2026 MLX5_GET_CTR(out, received_eth_broadcast.octets);
2027
2028 vf_stats->tx_packets =
2029 MLX5_GET_CTR(out, transmitted_eth_unicast.packets) +
2030 MLX5_GET_CTR(out, transmitted_eth_multicast.packets) +
2031 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
2032
2033 vf_stats->tx_bytes =
2034 MLX5_GET_CTR(out, transmitted_eth_unicast.octets) +
2035 MLX5_GET_CTR(out, transmitted_eth_multicast.octets) +
2036 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
2037
2038 vf_stats->multicast =
2039 MLX5_GET_CTR(out, received_eth_multicast.packets);
2040
2041 vf_stats->broadcast =
2042 MLX5_GET_CTR(out, received_eth_broadcast.packets);
2043
2044free_out:
2045 kvfree(out);
2046 return err;
2047}
Linux 6.x block layer and io_uring tree(s)