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net/mlx5: PTP code migration to driver core section
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / eq.c
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/interrupt.h>
34#include <linux/module.h>
35#include <linux/mlx5/driver.h>
36#include <linux/mlx5/cmd.h>
37#include "mlx5_core.h"
e29341fb 38#include "fpga/core.h"
073bb189 39#include "eswitch.h"
e126ba97
EC		 40
41enum {
42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
43 MLX5_EQE_OWNER_INIT_VAL = 0x1,
44};
45
46enum {
47 MLX5_EQ_STATE_ARMED = 0x9,
48 MLX5_EQ_STATE_FIRED = 0xa,
49 MLX5_EQ_STATE_ALWAYS_ARMED = 0xb,
50};
51
52enum {
53 MLX5_NUM_SPARE_EQE = 0x80,
54 MLX5_NUM_ASYNC_EQE = 0x100,
55 MLX5_NUM_CMD_EQE = 32,
d9aaed83 56 MLX5_NUM_PF_DRAIN = 64,
e126ba97
EC		 57};
58
59enum {
60 MLX5_EQ_DOORBEL_OFFSET = 0x40,
61};
62
63#define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
64 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
65 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
66 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
67 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
68 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
69 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
70 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
71 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
72 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
73 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
74 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
75
76struct map_eq_in {
77 u64 mask;
78 u32 reserved;
79 u32 unmap_eqn;
80};
81
82struct cre_des_eq {
83 u8 reserved[15];
84 u8 eqn;
85};
86
87static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
88{
73b626c1
SM		 89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
90 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
e126ba97 91
73b626c1
SM		 92 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
93 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
c4f287c4 94 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
e126ba97
EC		 95}
96
97static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
98{
99 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
100}
101
102static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
103{
104 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
105
106 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
107}
108
109static const char *eqe_type_str(u8 type)
110{
111 switch (type) {
112 case MLX5_EVENT_TYPE_COMP:
113 return "MLX5_EVENT_TYPE_COMP";
114 case MLX5_EVENT_TYPE_PATH_MIG:
115 return "MLX5_EVENT_TYPE_PATH_MIG";
116 case MLX5_EVENT_TYPE_COMM_EST:
117 return "MLX5_EVENT_TYPE_COMM_EST";
118 case MLX5_EVENT_TYPE_SQ_DRAINED:
119 return "MLX5_EVENT_TYPE_SQ_DRAINED";
120 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
121 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
122 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
123 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
124 case MLX5_EVENT_TYPE_CQ_ERROR:
125 return "MLX5_EVENT_TYPE_CQ_ERROR";
126 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
127 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
128 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
129 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
130 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
131 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
132 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
133 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
134 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
135 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
136 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
137 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
138 case MLX5_EVENT_TYPE_PORT_CHANGE:
139 return "MLX5_EVENT_TYPE_PORT_CHANGE";
140 case MLX5_EVENT_TYPE_GPIO_EVENT:
141 return "MLX5_EVENT_TYPE_GPIO_EVENT";
d4eb4cd7
HN		 142 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
143 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
e126ba97
EC		 144 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
145 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
146 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
147 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
148 case MLX5_EVENT_TYPE_STALL_EVENT:
149 return "MLX5_EVENT_TYPE_STALL_EVENT";
150 case MLX5_EVENT_TYPE_CMD:
151 return "MLX5_EVENT_TYPE_CMD";
152 case MLX5_EVENT_TYPE_PAGE_REQUEST:
153 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
e420f0c0
HE		 154 case MLX5_EVENT_TYPE_PAGE_FAULT:
155 return "MLX5_EVENT_TYPE_PAGE_FAULT";
f9a1ef72
EE		 156 case MLX5_EVENT_TYPE_PPS_EVENT:
157 return "MLX5_EVENT_TYPE_PPS_EVENT";
14160ea2
EC		 158 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
159 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
e29341fb
IT		 160 case MLX5_EVENT_TYPE_FPGA_ERROR:
161 return "MLX5_EVENT_TYPE_FPGA_ERROR";
246ac981
MG		 162 case MLX5_EVENT_TYPE_GENERAL_EVENT:
163 return "MLX5_EVENT_TYPE_GENERAL_EVENT";
e126ba97
EC		 164 default:
165 return "Unrecognized event";
166 }
167}
168
169static enum mlx5_dev_event port_subtype_event(u8 subtype)
170{
171 switch (subtype) {
172 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
173 return MLX5_DEV_EVENT_PORT_DOWN;
174 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
175 return MLX5_DEV_EVENT_PORT_UP;
176 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
177 return MLX5_DEV_EVENT_PORT_INITIALIZED;
178 case MLX5_PORT_CHANGE_SUBTYPE_LID:
179 return MLX5_DEV_EVENT_LID_CHANGE;
180 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
181 return MLX5_DEV_EVENT_PKEY_CHANGE;
182 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
183 return MLX5_DEV_EVENT_GUID_CHANGE;
184 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
185 return MLX5_DEV_EVENT_CLIENT_REREG;
186 }
187 return -1;
188}
189
190static void eq_update_ci(struct mlx5_eq *eq, int arm)
191{
192 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
193 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
3c004583 194
2fe30e23 195 __raw_writel((__force u32)cpu_to_be32(val), addr);
e126ba97
EC		 196 /* We still want ordering, just not swabbing, so add a barrier */
197 mb();
198}
199
d9aaed83
AK		 200#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
201static void eqe_pf_action(struct work_struct *work)
202{
203 struct mlx5_pagefault *pfault = container_of(work,
204 struct mlx5_pagefault,
205 work);
206 struct mlx5_eq *eq = pfault->eq;
207
208 mlx5_core_page_fault(eq->dev, pfault);
209 mempool_free(pfault, eq->pf_ctx.pool);
210}
211
212static void eq_pf_process(struct mlx5_eq *eq)
213{
214 struct mlx5_core_dev *dev = eq->dev;
215 struct mlx5_eqe_page_fault *pf_eqe;
216 struct mlx5_pagefault *pfault;
217 struct mlx5_eqe *eqe;
218 int set_ci = 0;
219
220 while ((eqe = next_eqe_sw(eq))) {
221 pfault = mempool_alloc(eq->pf_ctx.pool, GFP_ATOMIC);
222 if (!pfault) {
223 schedule_work(&eq->pf_ctx.work);
224 break;
225 }
226
227 dma_rmb();
228 pf_eqe = &eqe->data.page_fault;
229 pfault->event_subtype = eqe->sub_type;
230 pfault->bytes_committed = be32_to_cpu(pf_eqe->bytes_committed);
231
232 mlx5_core_dbg(dev,
233 "PAGE_FAULT: subtype: 0x%02x, bytes_committed: 0x%06x\n",
234 eqe->sub_type, pfault->bytes_committed);
235
236 switch (eqe->sub_type) {
237 case MLX5_PFAULT_SUBTYPE_RDMA:
238 /* RDMA based event */
239 pfault->type =
240 be32_to_cpu(pf_eqe->rdma.pftype_token) >> 24;
241 pfault->token =
242 be32_to_cpu(pf_eqe->rdma.pftype_token) &
243 MLX5_24BIT_MASK;
244 pfault->rdma.r_key =
245 be32_to_cpu(pf_eqe->rdma.r_key);
246 pfault->rdma.packet_size =
247 be16_to_cpu(pf_eqe->rdma.packet_length);
248 pfault->rdma.rdma_op_len =
249 be32_to_cpu(pf_eqe->rdma.rdma_op_len);
250 pfault->rdma.rdma_va =
251 be64_to_cpu(pf_eqe->rdma.rdma_va);
252 mlx5_core_dbg(dev,
253 "PAGE_FAULT: type:0x%x, token: 0x%06x, r_key: 0x%08x\n",
254 pfault->type, pfault->token,
255 pfault->rdma.r_key);
256 mlx5_core_dbg(dev,
257 "PAGE_FAULT: rdma_op_len: 0x%08x, rdma_va: 0x%016llx\n",
258 pfault->rdma.rdma_op_len,
259 pfault->rdma.rdma_va);
260 break;
261
262 case MLX5_PFAULT_SUBTYPE_WQE:
263 /* WQE based event */
264 pfault->type =
265 be32_to_cpu(pf_eqe->wqe.pftype_wq) >> 24;
266 pfault->token =
267 be32_to_cpu(pf_eqe->wqe.token);
268 pfault->wqe.wq_num =
269 be32_to_cpu(pf_eqe->wqe.pftype_wq) &
270 MLX5_24BIT_MASK;
271 pfault->wqe.wqe_index =
272 be16_to_cpu(pf_eqe->wqe.wqe_index);
273 pfault->wqe.packet_size =
274 be16_to_cpu(pf_eqe->wqe.packet_length);
275 mlx5_core_dbg(dev,
276 "PAGE_FAULT: type:0x%x, token: 0x%06x, wq_num: 0x%06x, wqe_index: 0x%04x\n",
277 pfault->type, pfault->token,
278 pfault->wqe.wq_num,
279 pfault->wqe.wqe_index);
280 break;
281
282 default:
283 mlx5_core_warn(dev,
284 "Unsupported page fault event sub-type: 0x%02hhx\n",
285 eqe->sub_type);
286 /* Unsupported page faults should still be
287 * resolved by the page fault handler
288 */
289 }
290
291 pfault->eq = eq;
292 INIT_WORK(&pfault->work, eqe_pf_action);
293 queue_work(eq->pf_ctx.wq, &pfault->work);
294
295 ++eq->cons_index;
296 ++set_ci;
297
298 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
299 eq_update_ci(eq, 0);
300 set_ci = 0;
301 }
302 }
303
304 eq_update_ci(eq, 1);
305}
306
307static irqreturn_t mlx5_eq_pf_int(int irq, void *eq_ptr)
308{
309 struct mlx5_eq *eq = eq_ptr;
310 unsigned long flags;
311
312 if (spin_trylock_irqsave(&eq->pf_ctx.lock, flags)) {
313 eq_pf_process(eq);
314 spin_unlock_irqrestore(&eq->pf_ctx.lock, flags);
315 } else {
316 schedule_work(&eq->pf_ctx.work);
317 }
318
319 return IRQ_HANDLED;
320}
321
322/* mempool_refill() was proposed but unfortunately wasn't accepted
323 * http://lkml.iu.edu/hypermail/linux/kernel/1512.1/05073.html
324 * Chip workaround.
325 */
326static void mempool_refill(mempool_t *pool)
327{
328 while (pool->curr_nr < pool->min_nr)
329 mempool_free(mempool_alloc(pool, GFP_KERNEL), pool);
330}
331
332static void eq_pf_action(struct work_struct *work)
333{
334 struct mlx5_eq *eq = container_of(work, struct mlx5_eq, pf_ctx.work);
335
336 mempool_refill(eq->pf_ctx.pool);
337
338 spin_lock_irq(&eq->pf_ctx.lock);
339 eq_pf_process(eq);
340 spin_unlock_irq(&eq->pf_ctx.lock);
341}
342
343static int init_pf_ctx(struct mlx5_eq_pagefault *pf_ctx, const char *name)
e126ba97 344{
d9aaed83
AK		 345 spin_lock_init(&pf_ctx->lock);
346 INIT_WORK(&pf_ctx->work, eq_pf_action);
347
348 pf_ctx->wq = alloc_ordered_workqueue(name,
349 WQ_MEM_RECLAIM);
350 if (!pf_ctx->wq)
351 return -ENOMEM;
352
353 pf_ctx->pool = mempool_create_kmalloc_pool
354 (MLX5_NUM_PF_DRAIN, sizeof(struct mlx5_pagefault));
355 if (!pf_ctx->pool)
356 goto err_wq;
357
358 return 0;
359err_wq:
360 destroy_workqueue(pf_ctx->wq);
361 return -ENOMEM;
362}
363
364int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 token,
365 u32 wq_num, u8 type, int error)
366{
367 u32 out[MLX5_ST_SZ_DW(page_fault_resume_out)] = {0};
368 u32 in[MLX5_ST_SZ_DW(page_fault_resume_in)] = {0};
369
370 MLX5_SET(page_fault_resume_in, in, opcode,
371 MLX5_CMD_OP_PAGE_FAULT_RESUME);
372 MLX5_SET(page_fault_resume_in, in, error, !!error);
373 MLX5_SET(page_fault_resume_in, in, page_fault_type, type);
374 MLX5_SET(page_fault_resume_in, in, wq_number, wq_num);
375 MLX5_SET(page_fault_resume_in, in, token, token);
376
377 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
378}
379EXPORT_SYMBOL_GPL(mlx5_core_page_fault_resume);
380#endif
381
246ac981
MG		 382static void general_event_handler(struct mlx5_core_dev *dev,
383 struct mlx5_eqe *eqe)
384{
385 switch (eqe->sub_type) {
386 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
387 if (dev->event)
388 dev->event(dev, MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT, 0);
389 break;
390 default:
391 mlx5_core_dbg(dev, "General event with unrecognized subtype: sub_type %d\n",
392 eqe->sub_type);
393 }
394}
395
d9aaed83
AK		 396static irqreturn_t mlx5_eq_int(int irq, void *eq_ptr)
397{
398 struct mlx5_eq *eq = eq_ptr;
399 struct mlx5_core_dev *dev = eq->dev;
e126ba97 400 struct mlx5_eqe *eqe;
e126ba97 401 int set_ci = 0;
94c6825e 402 u32 cqn = -1;
5903325a 403 u32 rsn;
e126ba97
EC		 404 u8 port;
405
406 while ((eqe = next_eqe_sw(eq))) {
407 /*
408 * Make sure we read EQ entry contents after we've
409 * checked the ownership bit.
410 */
12b3375f 411 dma_rmb();
e126ba97 412
1a91de28
JP		 413 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
414 eq->eqn, eqe_type_str(eqe->type));
e126ba97
EC		 415 switch (eqe->type) {
416 case MLX5_EVENT_TYPE_COMP:
417 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
418 mlx5_cq_completion(dev, cqn);
419 break;
420
421 case MLX5_EVENT_TYPE_PATH_MIG:
422 case MLX5_EVENT_TYPE_COMM_EST:
423 case MLX5_EVENT_TYPE_SQ_DRAINED:
424 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
425 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
426 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
427 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
428 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
5903325a 429 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
e2013b21 430 rsn |= (eqe->data.qp_srq.type << MLX5_USER_INDEX_LEN);
ab62924e
EC		 431 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
432 eqe_type_str(eqe->type), eqe->type, rsn);
5903325a 433 mlx5_rsc_event(dev, rsn, eqe->type);
e126ba97
EC		 434 break;
435
436 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
437 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
5903325a 438 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
e126ba97 439 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
5903325a
EC		 440 eqe_type_str(eqe->type), eqe->type, rsn);
441 mlx5_srq_event(dev, rsn, eqe->type);
e126ba97
EC		 442 break;
443
444 case MLX5_EVENT_TYPE_CMD:
73dd3a48 445 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
e126ba97
EC		 446 break;
447
448 case MLX5_EVENT_TYPE_PORT_CHANGE:
449 port = (eqe->data.port.port >> 4) & 0xf;
450 switch (eqe->sub_type) {
451 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
452 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
453 case MLX5_PORT_CHANGE_SUBTYPE_LID:
454 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
455 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
456 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
457 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
f241e749 458 if (dev->event)
4d2f9bbb
JM		 459 dev->event(dev, port_subtype_event(eqe->sub_type),
460 (unsigned long)port);
e126ba97
EC		 461 break;
462 default:
463 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
464 port, eqe->sub_type);
465 }
466 break;
467 case MLX5_EVENT_TYPE_CQ_ERROR:
468 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
469 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
470 cqn, eqe->data.cq_err.syndrome);
471 mlx5_cq_event(dev, cqn, eqe->type);
472 break;
473
474 case MLX5_EVENT_TYPE_PAGE_REQUEST:
475 {
476 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
0a324f31 477 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
e126ba97 478
1a91de28
JP		 479 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
480 func_id, npages);
e126ba97
EC		 481 mlx5_core_req_pages_handler(dev, func_id, npages);
482 }
483 break;
484
073bb189
SM		 485 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
486 mlx5_eswitch_vport_event(dev->priv.eswitch, eqe);
487 break;
d4eb4cd7
HN		 488
489 case MLX5_EVENT_TYPE_PORT_MODULE_EVENT:
490 mlx5_port_module_event(dev, eqe);
491 break;
492
f9a1ef72 493 case MLX5_EVENT_TYPE_PPS_EVENT:
7c39afb3 494 mlx5_pps_event(dev, eqe);
f9a1ef72 495 break;
e29341fb
IT		 496
497 case MLX5_EVENT_TYPE_FPGA_ERROR:
498 mlx5_fpga_event(dev, eqe->type, &eqe->data.raw);
499 break;
500
246ac981
MG		 501 case MLX5_EVENT_TYPE_GENERAL_EVENT:
502 general_event_handler(dev, eqe);
503 break;
e126ba97 504 default:
1a91de28
JP		 505 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
506 eqe->type, eq->eqn);
e126ba97
EC		 507 break;
508 }
509
510 ++eq->cons_index;
e126ba97
EC		 511 ++set_ci;
512
513 /* The HCA will think the queue has overflowed if we
514 * don't tell it we've been processing events. We
515 * create our EQs with MLX5_NUM_SPARE_EQE extra
516 * entries, so we must update our consumer index at
517 * least that often.
518 */
519 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
520 eq_update_ci(eq, 0);
521 set_ci = 0;
522 }
523 }
524
525 eq_update_ci(eq, 1);
526
94c6825e
MB		 527 if (cqn != -1)
528 tasklet_schedule(&eq->tasklet_ctx.task);
529
e126ba97
EC		 530 return IRQ_HANDLED;
531}
532
533static void init_eq_buf(struct mlx5_eq *eq)
534{
535 struct mlx5_eqe *eqe;
536 int i;
537
538 for (i = 0; i < eq->nent; i++) {
539 eqe = get_eqe(eq, i);
540 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
541 }
542}
543
544int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
d9aaed83 545 int nent, u64 mask, const char *name,
01187175 546 enum mlx5_eq_type type)
e126ba97 547{
73b626c1 548 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
db058a18 549 struct mlx5_priv *priv = &dev->priv;
d9aaed83 550 irq_handler_t handler;
73b626c1
SM		 551 __be64 *pas;
552 void *eqc;
e126ba97 553 int inlen;
73b626c1
SM		 554 u32 *in;
555 int err;
e126ba97 556
d9aaed83 557 eq->type = type;
e126ba97 558 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
a31208b1 559 eq->cons_index = 0;
64ffaa21 560 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
e126ba97
EC		 561 if (err)
562 return err;
563
d9aaed83
AK		 564#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
565 if (type == MLX5_EQ_TYPE_PF)
566 handler = mlx5_eq_pf_int;
567 else
568#endif
569 handler = mlx5_eq_int;
570
e126ba97
EC		 571 init_eq_buf(eq);
572
73b626c1
SM		 573 inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
574 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
575
1b9a07ee 576 in = kvzalloc(inlen, GFP_KERNEL);
e126ba97
EC		 577 if (!in) {
578 err = -ENOMEM;
579 goto err_buf;
580 }
e126ba97 581
73b626c1
SM		 582 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
583 mlx5_fill_page_array(&eq->buf, pas);
e126ba97 584
73b626c1
SM		 585 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
586 MLX5_SET64(create_eq_in, in, event_bitmask, mask);
e126ba97 587
73b626c1
SM		 588 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
589 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
01187175 590 MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
73b626c1
SM		 591 MLX5_SET(eqc, eqc, intr, vecidx);
592 MLX5_SET(eqc, eqc, log_page_size,
593 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
e126ba97 594
73b626c1 595 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
73b626c1 596 if (err)
e126ba97 597 goto err_in;
e126ba97 598
db058a18 599 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
ada9f5d0 600 name, pci_name(dev->pdev));
db058a18 601
73b626c1 602 eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
78249c42 603 eq->irqn = pci_irq_vector(dev->pdev, vecidx);
a158906d 604 eq->dev = dev;
01187175 605 eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
d9aaed83 606 err = request_irq(eq->irqn, handler, 0,
db058a18 607 priv->irq_info[vecidx].name, eq);
e126ba97
EC		 608 if (err)
609 goto err_eq;
610
e126ba97
EC		 611 err = mlx5_debug_eq_add(dev, eq);
612 if (err)
613 goto err_irq;
614
d9aaed83
AK		 615#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
616 if (type == MLX5_EQ_TYPE_PF) {
617 err = init_pf_ctx(&eq->pf_ctx, name);
618 if (err)
619 goto err_irq;
620 } else
621#endif
622 {
623 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
624 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
625 spin_lock_init(&eq->tasklet_ctx.lock);
626 tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
627 (unsigned long)&eq->tasklet_ctx);
628 }
94c6825e 629
e126ba97
EC		 630 /* EQs are created in ARMED state
631 */
632 eq_update_ci(eq, 1);
633
479163f4 634 kvfree(in);
e126ba97
EC		 635 return 0;
636
637err_irq:
78249c42 638 free_irq(eq->irqn, eq);
e126ba97
EC		 639
640err_eq:
641 mlx5_cmd_destroy_eq(dev, eq->eqn);
642
643err_in:
479163f4 644 kvfree(in);
e126ba97
EC		 645
646err_buf:
647 mlx5_buf_free(dev, &eq->buf);
648 return err;
649}
650EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
651
652int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
653{
e126ba97
EC		 654 int err;
655
656 mlx5_debug_eq_remove(dev, eq);
61d0e73e 657 free_irq(eq->irqn, eq);
e126ba97
EC		 658 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
659 if (err)
660 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
661 eq->eqn);
61d0e73e 662 synchronize_irq(eq->irqn);
d9aaed83
AK		 663
664 if (eq->type == MLX5_EQ_TYPE_COMP) {
665 tasklet_disable(&eq->tasklet_ctx.task);
666#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
667 } else if (eq->type == MLX5_EQ_TYPE_PF) {
668 cancel_work_sync(&eq->pf_ctx.work);
669 destroy_workqueue(eq->pf_ctx.wq);
670 mempool_destroy(eq->pf_ctx.pool);
671#endif
672 }
e126ba97
EC		 673 mlx5_buf_free(dev, &eq->buf);
674
675 return err;
676}
677EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
678
679int mlx5_eq_init(struct mlx5_core_dev *dev)
680{
681 int err;
682
683 spin_lock_init(&dev->priv.eq_table.lock);
684
685 err = mlx5_eq_debugfs_init(dev);
686
687 return err;
688}
689
e126ba97
EC		 690void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
691{
692 mlx5_eq_debugfs_cleanup(dev);
693}
694
695int mlx5_start_eqs(struct mlx5_core_dev *dev)
696{
697 struct mlx5_eq_table *table = &dev->priv.eq_table;
6887a825 698 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
e126ba97
EC		 699 int err;
700
a9f7705f 701 if (MLX5_VPORT_MANAGER(dev))
073bb189
SM		 702 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
703
246ac981
MG		 704 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
705 MLX5_CAP_GEN(dev, general_notification_event))
706 async_event_mask |= (1ull << MLX5_EVENT_TYPE_GENERAL_EVENT);
707
d4eb4cd7
HN		 708 if (MLX5_CAP_GEN(dev, port_module_event))
709 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
710 else
711 mlx5_core_dbg(dev, "port_module_event is not set\n");
712
fa367688 713 if (MLX5_PPS_CAP(dev))
f9a1ef72
EE		 714 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
715
e29341fb
IT		 716 if (MLX5_CAP_GEN(dev, fpga))
717 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR);
718
e126ba97
EC		 719 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
720 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
01187175 721 "mlx5_cmd_eq", MLX5_EQ_TYPE_ASYNC);
e126ba97
EC		 722 if (err) {
723 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
724 return err;
725 }
726
727 mlx5_cmd_use_events(dev);
728
729 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
e420f0c0 730 MLX5_NUM_ASYNC_EQE, async_event_mask,
01187175 731 "mlx5_async_eq", MLX5_EQ_TYPE_ASYNC);
e126ba97
EC		 732 if (err) {
733 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
734 goto err1;
735 }
736
737 err = mlx5_create_map_eq(dev, &table->pages_eq,
738 MLX5_EQ_VEC_PAGES,
938fe83c 739 /* TODO: sriov max_vf + */ 1,
e126ba97 740 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
d9aaed83 741 MLX5_EQ_TYPE_ASYNC);
e126ba97
EC		 742 if (err) {
743 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
744 goto err2;
745 }
746
d9aaed83
AK		 747#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
748 if (MLX5_CAP_GEN(dev, pg)) {
749 err = mlx5_create_map_eq(dev, &table->pfault_eq,
750 MLX5_EQ_VEC_PFAULT,
751 MLX5_NUM_ASYNC_EQE,
752 1 << MLX5_EVENT_TYPE_PAGE_FAULT,
753 "mlx5_page_fault_eq",
d9aaed83
AK		 754 MLX5_EQ_TYPE_PF);
755 if (err) {
756 mlx5_core_warn(dev, "failed to create page fault EQ %d\n",
757 err);
758 goto err3;
759 }
760 }
761
e126ba97 762 return err;
d9aaed83
AK		 763err3:
764 mlx5_destroy_unmap_eq(dev, &table->pages_eq);
765#else
766 return err;
767#endif
e126ba97
EC		 768
769err2:
770 mlx5_destroy_unmap_eq(dev, &table->async_eq);
771
772err1:
773 mlx5_cmd_use_polling(dev);
774 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
775 return err;
776}
777
778int mlx5_stop_eqs(struct mlx5_core_dev *dev)
779{
780 struct mlx5_eq_table *table = &dev->priv.eq_table;
781 int err;
782
d9aaed83
AK		 783#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
784 if (MLX5_CAP_GEN(dev, pg)) {
785 err = mlx5_destroy_unmap_eq(dev, &table->pfault_eq);
786 if (err)
787 return err;
788 }
789#endif
790
e126ba97
EC		 791 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
792 if (err)
793 return err;
794
795 mlx5_destroy_unmap_eq(dev, &table->async_eq);
796 mlx5_cmd_use_polling(dev);
797
798 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
799 if (err)
800 mlx5_cmd_use_events(dev);
801
802 return err;
803}
804
805int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
73b626c1 806 u32 *out, int outlen)
e126ba97 807{
73b626c1 808 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
e126ba97 809
73b626c1
SM		 810 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
811 MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
c4f287c4 812 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
e126ba97
EC		 813}
814EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
Linux 6.x block layer and io_uring tree(s)