net/mlx5e: Use struct assignment for WQE info updates
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_txrx.c
CommitLineData
e586b3b0
AV
1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
a8c2eb15 33#include <linux/irq.h>
2c8f80b3 34#include <linux/indirect_call_wrapper.h>
e586b3b0 35#include "en.h"
159d2131 36#include "en/xdp.h"
a7bd4018 37#include "en/xsk/rx.h"
db05815b 38#include "en/xsk/tx.h"
e586b3b0 39
a8c2eb15
TT
40static inline bool mlx5e_channel_no_affinity_change(struct mlx5e_channel *c)
41{
42 int current_cpu = smp_processor_id();
43 const struct cpumask *aff;
44 struct irq_data *idata;
45
46 idata = irq_desc_get_irq_data(c->irq_desc);
47 aff = irq_data_get_affinity_mask(idata);
48 return cpumask_test_cpu(current_cpu, aff);
49}
50
cbce4f44
TG
51static void mlx5e_handle_tx_dim(struct mlx5e_txqsq *sq)
52{
05909bab 53 struct mlx5e_sq_stats *stats = sq->stats;
f06d0ca4 54 struct dim_sample dim_sample = {};
cbce4f44 55
0e5c04f6 56 if (unlikely(!test_bit(MLX5E_SQ_STATE_AM, &sq->state)))
cbce4f44
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57 return;
58
8960b389 59 dim_update_sample(sq->cq.event_ctr, stats->packets, stats->bytes, &dim_sample);
cbce4f44
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60 net_dim(&sq->dim, dim_sample);
61}
62
63static void mlx5e_handle_rx_dim(struct mlx5e_rq *rq)
64{
05909bab 65 struct mlx5e_rq_stats *stats = rq->stats;
f06d0ca4 66 struct dim_sample dim_sample = {};
cbce4f44 67
0e5c04f6 68 if (unlikely(!test_bit(MLX5E_RQ_STATE_AM, &rq->state)))
cbce4f44
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69 return;
70
8960b389 71 dim_update_sample(rq->cq.event_ctr, stats->packets, stats->bytes, &dim_sample);
cbce4f44
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72 net_dim(&rq->dim, dim_sample);
73}
74
63d26b49
MM
75void mlx5e_trigger_irq(struct mlx5e_icosq *sq)
76{
77 struct mlx5_wq_cyc *wq = &sq->wq;
78 struct mlx5e_tx_wqe *nopwqe;
79 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
80
41a8e4eb
TT
81 sq->db.wqe_info[pi] = (struct mlx5e_icosq_wqe_info) {
82 .opcode = MLX5_OPCODE_NOP,
83 .num_wqebbs = 1,
84 };
85
63d26b49
MM
86 nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
87 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
88}
89
871aa189
MM
90static bool mlx5e_napi_xsk_post(struct mlx5e_xdpsq *xsksq, struct mlx5e_rq *xskrq)
91{
a7bd4018 92 bool busy_xsk = false, xsk_rx_alloc_err;
871aa189 93
a7bd4018
MM
94 /* Handle the race between the application querying need_wakeup and the
95 * driver setting it:
96 * 1. Update need_wakeup both before and after the TX. If it goes to
97 * "yes", it can only happen with the first update.
98 * 2. If the application queried need_wakeup before we set it, the
99 * packets will be transmitted anyway, even w/o a wakeup.
100 * 3. Give a chance to clear need_wakeup after new packets were queued
101 * for TX.
102 */
103 mlx5e_xsk_update_tx_wakeup(xsksq);
871aa189 104 busy_xsk |= mlx5e_xsk_tx(xsksq, MLX5E_TX_XSK_POLL_BUDGET);
a7bd4018
MM
105 mlx5e_xsk_update_tx_wakeup(xsksq);
106
2c8f80b3
TT
107 xsk_rx_alloc_err = INDIRECT_CALL_2(xskrq->post_wqes,
108 mlx5e_post_rx_mpwqes,
109 mlx5e_post_rx_wqes,
110 xskrq);
a7bd4018 111 busy_xsk |= mlx5e_xsk_update_rx_wakeup(xskrq, xsk_rx_alloc_err);
871aa189
MM
112
113 return busy_xsk;
114}
115
e586b3b0
AV
116int mlx5e_napi_poll(struct napi_struct *napi, int budget)
117{
118 struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,
119 napi);
2d7103c8 120 struct mlx5e_ch_stats *ch_stats = c->stats;
db05815b
MM
121 struct mlx5e_xdpsq *xsksq = &c->xsksq;
122 struct mlx5e_rq *xskrq = &c->xskrq;
feb2ff9d 123 struct mlx5e_rq *rq = &c->rq;
db05815b
MM
124 bool xsk_open = test_bit(MLX5E_CHANNEL_STATE_XSK, c->state);
125 bool aff_change = false;
126 bool busy_xsk = false;
e586b3b0 127 bool busy = false;
2a8d6065 128 int work_done = 0;
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129 int i;
130
2d7103c8
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131 ch_stats->poll++;
132
e586b3b0 133 for (i = 0; i < c->num_tc; i++)
8ec736e5 134 busy |= mlx5e_poll_tx_cq(&c->sq[i].cq, budget);
e586b3b0 135
b9673cf5 136 busy |= mlx5e_poll_xdpsq_cq(&c->xdpsq.cq);
58b99ee3 137
b5503b99 138 if (c->xdp)
b9673cf5 139 busy |= mlx5e_poll_xdpsq_cq(&c->rq_xdpsq.cq);
b5503b99 140
2a8d6065 141 if (likely(budget)) { /* budget=0 means: don't poll rx rings */
db05815b
MM
142 if (xsk_open)
143 work_done = mlx5e_poll_rx_cq(&xskrq->cq, budget);
144
145 if (likely(budget - work_done))
146 work_done += mlx5e_poll_rx_cq(&rq->cq, budget - work_done);
147
2a8d6065
SM
148 busy |= work_done == budget;
149 }
39e12351 150
ed084fb6
MM
151 mlx5e_poll_ico_cq(&c->icosq.cq);
152
2c8f80b3
TT
153 busy |= INDIRECT_CALL_2(rq->post_wqes,
154 mlx5e_post_rx_mpwqes,
155 mlx5e_post_rx_wqes,
156 rq);
db05815b 157 if (xsk_open) {
e7e0004a
MM
158 if (mlx5e_poll_ico_cq(&c->xskicosq.cq))
159 /* Don't clear the flag if nothing was polled to prevent
160 * queueing more WQEs and overflowing XSKICOSQ.
161 */
162 clear_bit(MLX5E_SQ_STATE_PENDING_XSK_TX, &c->xskicosq.state);
db05815b 163 busy |= mlx5e_poll_xdpsq_cq(&xsksq->cq);
871aa189 164 busy_xsk |= mlx5e_napi_xsk_post(xsksq, xskrq);
db05815b
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165 }
166
167 busy |= busy_xsk;
e586b3b0 168
a8c2eb15
TT
169 if (busy) {
170 if (likely(mlx5e_channel_no_affinity_change(c)))
171 return budget;
2d7103c8 172 ch_stats->aff_change++;
db05815b 173 aff_change = true;
2a8d6065 174 if (budget && work_done == budget)
a8c2eb15
TT
175 work_done--;
176 }
e586b3b0 177
7b33aaea 178 if (unlikely(!napi_complete_done(napi, work_done)))
44fb6fbb 179 return work_done;
e586b3b0 180
2d7103c8
TT
181 ch_stats->arm++;
182
cbce4f44
TG
183 for (i = 0; i < c->num_tc; i++) {
184 mlx5e_handle_tx_dim(&c->sq[i]);
e586b3b0 185 mlx5e_cq_arm(&c->sq[i].cq);
8115b750 186 }
cb3c7fd4 187
feb2ff9d 188 mlx5e_handle_rx_dim(rq);
cbce4f44 189
feb2ff9d 190 mlx5e_cq_arm(&rq->cq);
d3c9bc27 191 mlx5e_cq_arm(&c->icosq.cq);
58b99ee3 192 mlx5e_cq_arm(&c->xdpsq.cq);
e586b3b0 193
db05815b
MM
194 if (xsk_open) {
195 mlx5e_handle_rx_dim(xskrq);
196 mlx5e_cq_arm(&c->xskicosq.cq);
197 mlx5e_cq_arm(&xsksq->cq);
198 mlx5e_cq_arm(&xskrq->cq);
199 }
200
201 if (unlikely(aff_change && busy_xsk)) {
202 mlx5e_trigger_irq(&c->icosq);
203 ch_stats->force_irq++;
204 }
205
44fb6fbb 206 return work_done;
e586b3b0
AV
207}
208
4e0e2ea1 209void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe)
e586b3b0
AV
210{
211 struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
212
e586b3b0 213 napi_schedule(cq->napi);
a1bf74dc
TT
214 cq->event_ctr++;
215 cq->channel->stats->events++;
e586b3b0
AV
216}
217
218void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event)
219{
220 struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
221 struct mlx5e_channel *c = cq->channel;
a43b25da 222 struct net_device *netdev = c->netdev;
e586b3b0
AV
223
224 netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n",
225 __func__, mcq->cqn, event);
226}