[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_txrx.c

/*
 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include "en.h"

static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
					     struct mlx5e_icosq *sq,
					     struct mlx5_cqe64 *cqe,
					     u16 *sqcc)
{
	struct mlx5_wq_cyc *wq = &sq->wq;
	u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
	struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
	struct mlx5e_rq *rq = &sq->channel->rq;

	prefetch(rq);
	mlx5_cqwq_pop(&cq->wq);
	*sqcc += icowi->num_wqebbs;

	if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
		WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
			  cqe->op_own);
		return;
	}

	if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
		mlx5e_post_rx_mpwqe(rq);
		return;
	}

	if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
		WARN_ONCE(true,
			  "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
			  icowi->opcode);
}

static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
{
	struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
	struct mlx5_cqe64 *cqe;
	u16 sqcc;

	if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
		return;

	cqe = mlx5_cqwq_get_cqe(&cq->wq);
	if (likely(!cqe))
		return;

	/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
	 * otherwise a cq overrun may occur
	 */
	sqcc = sq->cc;

	/* by design, there's only a single cqe */
	mlx5e_poll_ico_single_cqe(cq, sq, cqe, &sqcc);

	mlx5_cqwq_update_db_record(&cq->wq);

	/* ensure cq space is freed before enabling more cqes */
	wmb();

	sq->cc = sqcc;
}

int mlx5e_napi_poll(struct napi_struct *napi, int budget)
{
	struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,
					       napi);
	bool busy = false;
	int work_done;
	int i;

	clear_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);

	for (i = 0; i < c->num_tc; i++)
		busy |= mlx5e_poll_tx_cq(&c->sq[i].cq, budget);

	if (c->xdp)
		busy |= mlx5e_poll_xdpsq_cq(&c->rq.xdpsq.cq);

	work_done = mlx5e_poll_rx_cq(&c->rq.cq, budget);
	busy |= work_done == budget;

	mlx5e_poll_ico_cq(&c->icosq.cq);

	busy |= mlx5e_post_rx_wqes(&c->rq);

	if (busy)
		return budget;

	napi_complete_done(napi, work_done);

	/* avoid losing completion event during/after polling cqs */
	if (test_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags)) {
		napi_schedule(napi);
		return work_done;
	}

	for (i = 0; i < c->num_tc; i++)
		mlx5e_cq_arm(&c->sq[i].cq);

	if (test_bit(MLX5E_RQ_STATE_AM, &c->rq.state))
		mlx5e_rx_am(&c->rq);

	mlx5e_cq_arm(&c->rq.cq);
	mlx5e_cq_arm(&c->icosq.cq);

	return work_done;
}

void mlx5e_completion_event(struct mlx5_core_cq *mcq)
{
	struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);

	cq->event_ctr++;
	set_bit(MLX5E_CHANNEL_NAPI_SCHED, &cq->channel->flags);
	napi_schedule(cq->napi);
}

void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event)
{
	struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
	struct mlx5e_channel *c = cq->channel;
	struct net_device *netdev = c->netdev;

	netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n",
		   __func__, mcq->cqn, event);
}
Commit	Line	Data
e586b3b0 AV	1	/*
	2	* Copyright (c) 2015, Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include "en.h"
	34
1f5b1e47 TT	35	static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq,
	36	struct mlx5e_icosq *sq,
	37	struct mlx5_cqe64 *cqe,
	38	u16 *sqcc)
	39	{
	40	struct mlx5_wq_cyc *wq = &sq->wq;
	41	u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1;
	42	struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci];
	43	struct mlx5e_rq *rq = &sq->channel->rq;
	44
	45	prefetch(rq);
	46	mlx5_cqwq_pop(&cq->wq);
	47	*sqcc += icowi->num_wqebbs;
	48
	49	if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) {
	50	WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
	51	cqe->op_own);
	52	return;
	53	}
	54
	55	if (likely(icowi->opcode == MLX5_OPCODE_UMR)) {
	56	mlx5e_post_rx_mpwqe(rq);
	57	return;
	58	}
	59
	60	if (unlikely(icowi->opcode != MLX5_OPCODE_NOP))
	61	WARN_ONCE(true,
	62	"mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
	63	icowi->opcode);
	64	}
	65
d3c9bc27 TT	66	static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
d3c9bc27 TT	67	{
31391048	68	struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
d3c9bc27	69	struct mlx5_cqe64 *cqe;
d3c9bc27 TT	70	u16 sqcc;
d3c9bc27 TT	71
c0f1147d	72	if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
6e8dd6d6 SM	73	return;
6e8dd6d6 SM	74
4b673793	75	cqe = mlx5_cqwq_get_cqe(&cq->wq);
d3c9bc27 TT	76	if (likely(!cqe))
	77	return;
	78
d3c9bc27 TT	79	/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
	80	* otherwise a cq overrun may occur
	81	*/
	82	sqcc = sq->cc;
	83
1f5b1e47 TT	84	/* by design, there's only a single cqe */
1f5b1e47 TT	85	mlx5e_poll_ico_single_cqe(cq, sq, cqe, &sqcc);
d3c9bc27 TT	86
	87	mlx5_cqwq_update_db_record(&cq->wq);
	88
	89	/* ensure cq space is freed before enabling more cqes */
	90	wmb();
	91
	92	sq->cc = sqcc;
	93	}
	94
e586b3b0 AV	95	int mlx5e_napi_poll(struct napi_struct *napi, int budget)
	96	{
	97	struct mlx5e_channel *c = container_of(napi, struct mlx5e_channel,
	98	napi);
	99	bool busy = false;
44fb6fbb	100	int work_done;
e586b3b0 AV	101	int i;
	102
	103	clear_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
	104
	105	for (i = 0; i < c->num_tc; i++)
8ec736e5	106	busy \|= mlx5e_poll_tx_cq(&c->sq[i].cq, budget);
e586b3b0	107
b5503b99	108	if (c->xdp)
31871f87	109	busy \|= mlx5e_poll_xdpsq_cq(&c->rq.xdpsq.cq);
b5503b99	110
39e12351 SM	111	work_done = mlx5e_poll_rx_cq(&c->rq.cq, budget);
	112	busy \|= work_done == budget;
	113
d3c9bc27 TT	114	mlx5e_poll_ico_cq(&c->icosq.cq);
d3c9bc27 TT	115
e3391054	116	busy \|= mlx5e_post_rx_wqes(&c->rq);
e586b3b0 AV	117
	118	if (busy)
	119	return budget;
	120
44fb6fbb	121	napi_complete_done(napi, work_done);
e586b3b0 AV	122
	123	/* avoid losing completion event during/after polling cqs */
	124	if (test_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags)) {
	125	napi_schedule(napi);
44fb6fbb	126	return work_done;
e586b3b0 AV	127	}
	128
	129	for (i = 0; i < c->num_tc; i++)
	130	mlx5e_cq_arm(&c->sq[i].cq);
cb3c7fd4 GR	131
	132	if (test_bit(MLX5E_RQ_STATE_AM, &c->rq.state))
	133	mlx5e_rx_am(&c->rq);
	134
e586b3b0	135	mlx5e_cq_arm(&c->rq.cq);
d3c9bc27	136	mlx5e_cq_arm(&c->icosq.cq);
e586b3b0	137
44fb6fbb	138	return work_done;
e586b3b0 AV	139	}
	140
	141	void mlx5e_completion_event(struct mlx5_core_cq *mcq)
	142	{
	143	struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
	144
cb3c7fd4	145	cq->event_ctr++;
e586b3b0	146	set_bit(MLX5E_CHANNEL_NAPI_SCHED, &cq->channel->flags);
e586b3b0 AV	147	napi_schedule(cq->napi);
	148	}
	149
	150	void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event)
	151	{
	152	struct mlx5e_cq *cq = container_of(mcq, struct mlx5e_cq, mcq);
	153	struct mlx5e_channel *c = cq->channel;
a43b25da	154	struct net_device *netdev = c->netdev;
e586b3b0 AV	155
	156	netdev_err(netdev, "%s: cqn=0x%.6x event=0x%.2x\n",
	157	__func__, mcq->cqn, event);
	158	}