[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tx.c

/*
 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include <linux/tcp.h>
#include <linux/if_vlan.h>
#include "en.h"

#define MLX5E_SQ_NOPS_ROOM  MLX5_SEND_WQE_MAX_WQEBBS
#define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
			    MLX5E_SQ_NOPS_ROOM)

void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
{
	struct mlx5_wq_cyc                *wq  = &sq->wq;

	u16 pi = sq->pc & wq->sz_m1;
	struct mlx5e_tx_wqe              *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);

	struct mlx5_wqe_ctrl_seg         *cseg = &wqe->ctrl;

	memset(cseg, 0, sizeof(*cseg));

	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
	cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | 0x01);

	sq->skb[pi] = NULL;
	sq->pc++;

	if (notify_hw) {
		cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
		mlx5e_tx_notify_hw(sq, wqe, 0);
	}
}

static void mlx5e_dma_pop_last_pushed(struct mlx5e_sq *sq, dma_addr_t *addr,
				      u32 *size)
{
	sq->dma_fifo_pc--;
	*addr = sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr;
	*size = sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size;
}

static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, struct sk_buff *skb)
{
	dma_addr_t addr;
	u32 size;
	int i;

	for (i = 0; i < MLX5E_TX_SKB_CB(skb)->num_dma; i++) {
		mlx5e_dma_pop_last_pushed(sq, &addr, &size);
		dma_unmap_single(sq->pdev, addr, size, DMA_TO_DEVICE);
	}
}

static inline void mlx5e_dma_push(struct mlx5e_sq *sq, dma_addr_t addr,
				  u32 size)
{
	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
	sq->dma_fifo_pc++;
}

static inline void mlx5e_dma_get(struct mlx5e_sq *sq, u32 i, dma_addr_t *addr,
				 u32 *size)
{
	*addr = sq->dma_fifo[i & sq->dma_fifo_mask].addr;
	*size = sq->dma_fifo[i & sq->dma_fifo_mask].size;
}

u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
		       void *accel_priv, select_queue_fallback_t fallback)
{
	struct mlx5e_priv *priv = netdev_priv(dev);
	int channel_ix = fallback(dev, skb);
	int up = skb_vlan_tag_present(skb)        ?
		 skb->vlan_tci >> VLAN_PRIO_SHIFT :
		 priv->default_vlan_prio;
	int tc = netdev_get_prio_tc_map(dev, up);

	return priv->channeltc_to_txq_map[channel_ix][tc];
}

static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
					    struct sk_buff *skb, bool bf)
{
	/* Some NIC TX decisions, e.g loopback, are based on the packet
	 * headers and occur before the data gather.
	 * Therefore these headers must be copied into the WQE
	 */
#define MLX5E_MIN_INLINE (ETH_HLEN + 2/*vlan tag*/)

	if (bf && (skb_headlen(skb) <= sq->max_inline))
		return skb_headlen(skb);

	return MLX5E_MIN_INLINE;
}

static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq *sq, struct sk_buff *skb)
{
	struct mlx5_wq_cyc       *wq   = &sq->wq;

	u16 pi = sq->pc & wq->sz_m1;
	struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);

	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
	struct mlx5_wqe_data_seg *dseg;

	u8  opcode = MLX5_OPCODE_SEND;
	dma_addr_t dma_addr = 0;
	bool bf = false;
	u16 headlen;
	u16 ds_cnt;
	u16 ihs;
	int i;

	memset(wqe, 0, sizeof(*wqe));

	if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
		eseg->cs_flags	= MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
	else
		sq->stats.csum_offload_none++;

	if (sq->cc != sq->prev_cc) {
		sq->prev_cc = sq->cc;
		sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
	}

	if (skb_is_gso(skb)) {
		u32 payload_len;

		eseg->mss    = cpu_to_be16(skb_shinfo(skb)->gso_size);
		opcode       = MLX5_OPCODE_LSO;
		ihs          = skb_transport_offset(skb) + tcp_hdrlen(skb);
		payload_len  = skb->len - ihs;
		MLX5E_TX_SKB_CB(skb)->num_bytes = skb->len +
					(skb_shinfo(skb)->gso_segs - 1) * ihs;
		sq->stats.tso_packets++;
		sq->stats.tso_bytes += payload_len;
	} else {
		bf = sq->bf_budget &&
		     !skb->xmit_more &&
		     !skb_shinfo(skb)->nr_frags;
		ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
		MLX5E_TX_SKB_CB(skb)->num_bytes = max_t(unsigned int, skb->len,
							ETH_ZLEN);
	}

	skb_copy_from_linear_data(skb, eseg->inline_hdr_start, ihs);
	skb_pull_inline(skb, ihs);

	eseg->inline_hdr_sz = cpu_to_be16(ihs);

	ds_cnt  = sizeof(*wqe) / MLX5_SEND_WQE_DS;
	ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
			       MLX5_SEND_WQE_DS);
	dseg    = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;

	MLX5E_TX_SKB_CB(skb)->num_dma = 0;

	headlen = skb_headlen(skb);
	if (headlen) {
		dma_addr = dma_map_single(sq->pdev, skb->data, headlen,
					  DMA_TO_DEVICE);
		if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
			goto dma_unmap_wqe_err;

		dseg->addr       = cpu_to_be64(dma_addr);
		dseg->lkey       = sq->mkey_be;
		dseg->byte_count = cpu_to_be32(headlen);

		mlx5e_dma_push(sq, dma_addr, headlen);
		MLX5E_TX_SKB_CB(skb)->num_dma++;

		dseg++;
	}

	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
		struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
		int fsz = skb_frag_size(frag);

		dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
					    DMA_TO_DEVICE);
		if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
			goto dma_unmap_wqe_err;

		dseg->addr       = cpu_to_be64(dma_addr);
		dseg->lkey       = sq->mkey_be;
		dseg->byte_count = cpu_to_be32(fsz);

		mlx5e_dma_push(sq, dma_addr, fsz);
		MLX5E_TX_SKB_CB(skb)->num_dma++;

		dseg++;
	}

	ds_cnt += MLX5E_TX_SKB_CB(skb)->num_dma;

	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode);
	cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | ds_cnt);

	sq->skb[pi] = skb;

	MLX5E_TX_SKB_CB(skb)->num_wqebbs = DIV_ROUND_UP(ds_cnt,
							MLX5_SEND_WQEBB_NUM_DS);
	sq->pc += MLX5E_TX_SKB_CB(skb)->num_wqebbs;

	netdev_tx_sent_queue(sq->txq, MLX5E_TX_SKB_CB(skb)->num_bytes);

	if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
		netif_tx_stop_queue(sq->txq);
		sq->stats.stopped++;
	}

	if (!skb->xmit_more || netif_xmit_stopped(sq->txq)) {
		int bf_sz = 0;

		if (bf && sq->uar_bf_map)
			bf_sz = MLX5E_TX_SKB_CB(skb)->num_wqebbs << 3;

		cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
		mlx5e_tx_notify_hw(sq, wqe, bf_sz);
	}

	/* fill sq edge with nops to avoid wqe wrap around */
	while ((sq->pc & wq->sz_m1) > sq->edge)
		mlx5e_send_nop(sq, false);

	sq->bf_budget = bf ? sq->bf_budget - 1 : 0;

	sq->stats.packets++;
	return NETDEV_TX_OK;

dma_unmap_wqe_err:
	sq->stats.dropped++;
	mlx5e_dma_unmap_wqe_err(sq, skb);

	dev_kfree_skb_any(skb);

	return NETDEV_TX_OK;
}

netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev)
{
	struct mlx5e_priv *priv = netdev_priv(dev);
	struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];

	return mlx5e_sq_xmit(sq, skb);
}

bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq)
{
	struct mlx5e_sq *sq;
	u32 dma_fifo_cc;
	u32 nbytes;
	u16 npkts;
	u16 sqcc;
	int i;

	/* avoid accessing cq (dma coherent memory) if not needed */
	if (!test_and_clear_bit(MLX5E_CQ_HAS_CQES, &cq->flags))
		return false;

	sq = container_of(cq, struct mlx5e_sq, cq);

	npkts = 0;
	nbytes = 0;

	/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
	 * otherwise a cq overrun may occur
	 */
	sqcc = sq->cc;

	/* avoid dirtying sq cache line every cqe */
	dma_fifo_cc = sq->dma_fifo_cc;

	for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
		struct mlx5_cqe64 *cqe;
		u16 wqe_counter;
		bool last_wqe;

		cqe = mlx5e_get_cqe(cq);
		if (!cqe)
			break;

		mlx5_cqwq_pop(&cq->wq);

		wqe_counter = be16_to_cpu(cqe->wqe_counter);

		do {
			struct sk_buff *skb;
			u16 ci;
			int j;

			last_wqe = (sqcc == wqe_counter);

			ci = sqcc & sq->wq.sz_m1;
			skb = sq->skb[ci];

			if (unlikely(!skb)) { /* nop */
				sq->stats.nop++;
				sqcc++;
				continue;
			}

			for (j = 0; j < MLX5E_TX_SKB_CB(skb)->num_dma; j++) {
				dma_addr_t addr;
				u32 size;

				mlx5e_dma_get(sq, dma_fifo_cc, &addr, &size);
				dma_fifo_cc++;
				dma_unmap_single(sq->pdev, addr, size,
						 DMA_TO_DEVICE);
			}

			npkts++;
			nbytes += MLX5E_TX_SKB_CB(skb)->num_bytes;
			sqcc += MLX5E_TX_SKB_CB(skb)->num_wqebbs;
			dev_kfree_skb(skb);
		} while (!last_wqe);
	}

	mlx5_cqwq_update_db_record(&cq->wq);

	/* ensure cq space is freed before enabling more cqes */
	wmb();

	sq->dma_fifo_cc = dma_fifo_cc;
	sq->cc = sqcc;

	netdev_tx_completed_queue(sq->txq, npkts, nbytes);

	if (netif_tx_queue_stopped(sq->txq) &&
	    mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
	    likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
				netif_tx_wake_queue(sq->txq);
				sq->stats.wake++;
	}
	if (i == MLX5E_TX_CQ_POLL_BUDGET) {
		set_bit(MLX5E_CQ_HAS_CQES, &cq->flags);
		return true;
	}

	return false;
}
Commit	Line	Data
e586b3b0 AV	1	/*
	2	* Copyright (c) 2015, Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include <linux/tcp.h>
	34	#include <linux/if_vlan.h>
	35	#include "en.h"
	36
12be4b21 SM	37	#define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS
	38	#define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\
	39	MLX5E_SQ_NOPS_ROOM)
	40
	41	void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw)
	42	{
	43	struct mlx5_wq_cyc *wq = &sq->wq;
	44
	45	u16 pi = sq->pc & wq->sz_m1;
	46	struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
	47
	48	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	49
	50	memset(cseg, 0, sizeof(*cseg));
	51
	52	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) \| MLX5_OPCODE_NOP);
	53	cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) \| 0x01);
	54
	55	sq->skb[pi] = NULL;
	56	sq->pc++;
	57
	58	if (notify_hw) {
	59	cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
88a85f99	60	mlx5e_tx_notify_hw(sq, wqe, 0);
12be4b21 SM	61	}
	62	}
	63
e586b3b0 AV	64	static void mlx5e_dma_pop_last_pushed(struct mlx5e_sq sq, dma_addr_t addr,
	65	u32 *size)
	66	{
	67	sq->dma_fifo_pc--;
	68	*addr = sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr;
	69	*size = sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size;
	70	}
	71
	72	static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq sq, struct sk_buff skb)
	73	{
	74	dma_addr_t addr;
	75	u32 size;
	76	int i;
	77
	78	for (i = 0; i < MLX5E_TX_SKB_CB(skb)->num_dma; i++) {
	79	mlx5e_dma_pop_last_pushed(sq, &addr, &size);
	80	dma_unmap_single(sq->pdev, addr, size, DMA_TO_DEVICE);
	81	}
	82	}
	83
	84	static inline void mlx5e_dma_push(struct mlx5e_sq *sq, dma_addr_t addr,
	85	u32 size)
	86	{
	87	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr;
	88	sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size;
	89	sq->dma_fifo_pc++;
	90	}
	91
	92	static inline void mlx5e_dma_get(struct mlx5e_sq sq, u32 i, dma_addr_t addr,
	93	u32 *size)
	94	{
	95	*addr = sq->dma_fifo[i & sq->dma_fifo_mask].addr;
	96	*size = sq->dma_fifo[i & sq->dma_fifo_mask].size;
	97	}
	98
	99	u16 mlx5e_select_queue(struct net_device dev, struct sk_buff skb,
	100	void *accel_priv, select_queue_fallback_t fallback)
	101	{
	102	struct mlx5e_priv *priv = netdev_priv(dev);
	103	int channel_ix = fallback(dev, skb);
	104	int up = skb_vlan_tag_present(skb) ?
	105	skb->vlan_tci >> VLAN_PRIO_SHIFT :
	106	priv->default_vlan_prio;
	107	int tc = netdev_get_prio_tc_map(dev, up);
	108
5283af89	109	return priv->channeltc_to_txq_map[channel_ix][tc];
e586b3b0 AV	110	}
	111
	112	static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq,
88a85f99	113	struct sk_buff *skb, bool bf)
e586b3b0	114	{
58d52291 AS	115	/* Some NIC TX decisions, e.g loopback, are based on the packet
	116	* headers and occur before the data gather.
	117	* Therefore these headers must be copied into the WQE
	118	*/
	119	#define MLX5E_MIN_INLINE (ETH_HLEN + 2/vlan tag/)
	120
88a85f99	121	if (bf && (skb_headlen(skb) <= sq->max_inline))
58d52291 AS	122	return skb_headlen(skb);
58d52291 AS	123
e586b3b0 AV	124	return MLX5E_MIN_INLINE;
	125	}
	126
e586b3b0 AV	127	static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq sq, struct sk_buff skb)
	128	{
	129	struct mlx5_wq_cyc *wq = &sq->wq;
	130
	131	u16 pi = sq->pc & wq->sz_m1;
	132	struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
	133
	134	struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
	135	struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
	136	struct mlx5_wqe_data_seg *dseg;
	137
	138	u8 opcode = MLX5_OPCODE_SEND;
	139	dma_addr_t dma_addr = 0;
88a85f99	140	bool bf = false;
e586b3b0 AV	141	u16 headlen;
	142	u16 ds_cnt;
	143	u16 ihs;
	144	int i;
	145
	146	memset(wqe, 0, sizeof(*wqe));
	147
	148	if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
	149	eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM \| MLX5_ETH_WQE_L4_CSUM;
	150	else
	151	sq->stats.csum_offload_none++;
	152
88a85f99 AS	153	if (sq->cc != sq->prev_cc) {
	154	sq->prev_cc = sq->cc;
	155	sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0;
	156	}
	157
e586b3b0 AV	158	if (skb_is_gso(skb)) {
e586b3b0 AV	159	u32 payload_len;
e586b3b0 AV	160
	161	eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size);
	162	opcode = MLX5_OPCODE_LSO;
	163	ihs = skb_transport_offset(skb) + tcp_hdrlen(skb);
	164	payload_len = skb->len - ihs;
e586b3b0	165	MLX5E_TX_SKB_CB(skb)->num_bytes = skb->len +
fb6c6f25	166	(skb_shinfo(skb)->gso_segs - 1) * ihs;
e586b3b0 AV	167	sq->stats.tso_packets++;
	168	sq->stats.tso_bytes += payload_len;
	169	} else {
88a85f99 AS	170	bf = sq->bf_budget &&
	171	!skb->xmit_more &&
	172	!skb_shinfo(skb)->nr_frags;
	173	ihs = mlx5e_get_inline_hdr_size(sq, skb, bf);
e586b3b0 AV	174	MLX5E_TX_SKB_CB(skb)->num_bytes = max_t(unsigned int, skb->len,
	175	ETH_ZLEN);
	176	}
	177
cd58c714 SM	178	skb_copy_from_linear_data(skb, eseg->inline_hdr_start, ihs);
cd58c714 SM	179	skb_pull_inline(skb, ihs);
e586b3b0	180
8ca56ce3	181	eseg->inline_hdr_sz = cpu_to_be16(ihs);
e586b3b0 AV	182
	183	ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS;
	184	ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start),
	185	MLX5_SEND_WQE_DS);
	186	dseg = (struct mlx5_wqe_data_seg *)cseg + ds_cnt;
	187
	188	MLX5E_TX_SKB_CB(skb)->num_dma = 0;
	189
	190	headlen = skb_headlen(skb);
	191	if (headlen) {
	192	dma_addr = dma_map_single(sq->pdev, skb->data, headlen,
	193	DMA_TO_DEVICE);
	194	if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
	195	goto dma_unmap_wqe_err;
	196
	197	dseg->addr = cpu_to_be64(dma_addr);
	198	dseg->lkey = sq->mkey_be;
	199	dseg->byte_count = cpu_to_be32(headlen);
	200
	201	mlx5e_dma_push(sq, dma_addr, headlen);
	202	MLX5E_TX_SKB_CB(skb)->num_dma++;
	203
	204	dseg++;
	205	}
	206
	207	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
	208	struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
	209	int fsz = skb_frag_size(frag);
	210
	211	dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz,
	212	DMA_TO_DEVICE);
	213	if (unlikely(dma_mapping_error(sq->pdev, dma_addr)))
	214	goto dma_unmap_wqe_err;
	215
	216	dseg->addr = cpu_to_be64(dma_addr);
	217	dseg->lkey = sq->mkey_be;
	218	dseg->byte_count = cpu_to_be32(fsz);
	219
	220	mlx5e_dma_push(sq, dma_addr, fsz);
	221	MLX5E_TX_SKB_CB(skb)->num_dma++;
	222
	223	dseg++;
	224	}
	225
	226	ds_cnt += MLX5E_TX_SKB_CB(skb)->num_dma;
	227
8ca56ce3 AS	228	cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) \| opcode);
8ca56ce3 AS	229	cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) \| ds_cnt);
e586b3b0 AV	230
	231	sq->skb[pi] = skb;
	232
	233	MLX5E_TX_SKB_CB(skb)->num_wqebbs = DIV_ROUND_UP(ds_cnt,
	234	MLX5_SEND_WQEBB_NUM_DS);
	235	sq->pc += MLX5E_TX_SKB_CB(skb)->num_wqebbs;
	236
	237	netdev_tx_sent_queue(sq->txq, MLX5E_TX_SKB_CB(skb)->num_bytes);
	238
12be4b21	239	if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) {
e586b3b0 AV	240	netif_tx_stop_queue(sq->txq);
	241	sq->stats.stopped++;
	242	}
	243
059ba072	244	if (!skb->xmit_more \|\| netif_xmit_stopped(sq->txq)) {
88a85f99 AS	245	int bf_sz = 0;
	246
	247	if (bf && sq->uar_bf_map)
	248	bf_sz = MLX5E_TX_SKB_CB(skb)->num_wqebbs << 3;
	249
059ba072	250	cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
88a85f99	251	mlx5e_tx_notify_hw(sq, wqe, bf_sz);
059ba072	252	}
e586b3b0	253
12be4b21 SM	254	/* fill sq edge with nops to avoid wqe wrap around */
	255	while ((sq->pc & wq->sz_m1) > sq->edge)
	256	mlx5e_send_nop(sq, false);
	257
88a85f99 AS	258	sq->bf_budget = bf ? sq->bf_budget - 1 : 0;
88a85f99 AS	259
e586b3b0 AV	260	sq->stats.packets++;
	261	return NETDEV_TX_OK;
	262
	263	dma_unmap_wqe_err:
	264	sq->stats.dropped++;
	265	mlx5e_dma_unmap_wqe_err(sq, skb);
	266
	267	dev_kfree_skb_any(skb);
	268
	269	return NETDEV_TX_OK;
	270	}
	271
	272	netdev_tx_t mlx5e_xmit(struct sk_buff skb, struct net_device dev)
	273	{
	274	struct mlx5e_priv *priv = netdev_priv(dev);
03289b88	275	struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)];
e586b3b0 AV	276
	277	return mlx5e_sq_xmit(sq, skb);
	278	}
	279
	280	bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq)
	281	{
	282	struct mlx5e_sq *sq;
	283	u32 dma_fifo_cc;
	284	u32 nbytes;
	285	u16 npkts;
	286	u16 sqcc;
	287	int i;
	288
	289	/* avoid accessing cq (dma coherent memory) if not needed */
	290	if (!test_and_clear_bit(MLX5E_CQ_HAS_CQES, &cq->flags))
	291	return false;
	292
e3391054	293	sq = container_of(cq, struct mlx5e_sq, cq);
e586b3b0 AV	294
	295	npkts = 0;
	296	nbytes = 0;
	297
	298	/* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
	299	* otherwise a cq overrun may occur
	300	*/
	301	sqcc = sq->cc;
	302
	303	/* avoid dirtying sq cache line every cqe */
	304	dma_fifo_cc = sq->dma_fifo_cc;
	305
	306	for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) {
	307	struct mlx5_cqe64 *cqe;
059ba072 AS	308	u16 wqe_counter;
059ba072 AS	309	bool last_wqe;
e586b3b0 AV	310
	311	cqe = mlx5e_get_cqe(cq);
	312	if (!cqe)
	313	break;
	314
a1f5a1a8 AS	315	mlx5_cqwq_pop(&cq->wq);
a1f5a1a8 AS	316
059ba072 AS	317	wqe_counter = be16_to_cpu(cqe->wqe_counter);
	318
	319	do {
	320	struct sk_buff *skb;
	321	u16 ci;
	322	int j;
	323
	324	last_wqe = (sqcc == wqe_counter);
	325
	326	ci = sqcc & sq->wq.sz_m1;
	327	skb = sq->skb[ci];
e586b3b0	328
059ba072 AS	329	if (unlikely(!skb)) { /* nop */
	330	sq->stats.nop++;
	331	sqcc++;
	332	continue;
	333	}
e586b3b0	334
059ba072 AS	335	for (j = 0; j < MLX5E_TX_SKB_CB(skb)->num_dma; j++) {
	336	dma_addr_t addr;
	337	u32 size;
e586b3b0	338
059ba072 AS	339	mlx5e_dma_get(sq, dma_fifo_cc, &addr, &size);
	340	dma_fifo_cc++;
	341	dma_unmap_single(sq->pdev, addr, size,
	342	DMA_TO_DEVICE);
	343	}
e586b3b0	344
059ba072 AS	345	npkts++;
	346	nbytes += MLX5E_TX_SKB_CB(skb)->num_bytes;
	347	sqcc += MLX5E_TX_SKB_CB(skb)->num_wqebbs;
	348	dev_kfree_skb(skb);
	349	} while (!last_wqe);
e586b3b0 AV	350	}
	351
	352	mlx5_cqwq_update_db_record(&cq->wq);
	353
	354	/* ensure cq space is freed before enabling more cqes */
	355	wmb();
	356
	357	sq->dma_fifo_cc = dma_fifo_cc;
	358	sq->cc = sqcc;
	359
	360	netdev_tx_completed_queue(sq->txq, npkts, nbytes);
	361
	362	if (netif_tx_queue_stopped(sq->txq) &&
12be4b21	363	mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) &&
e586b3b0 AV	364	likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) {
	365	netif_tx_wake_queue(sq->txq);
	366	sq->stats.wake++;
	367	}
	368	if (i == MLX5E_TX_CQ_POLL_BUDGET) {
	369	set_bit(MLX5E_CQ_HAS_CQES, &cq->flags);
	370	return true;
	371	}
	372
	373	return false;
	374	}