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e586b3b0 | 1 | /* |
98795158 | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
e586b3b0 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/tcp.h> | |
34 | #include <linux/if_vlan.h> | |
35 | #include "en.h" | |
36 | ||
12be4b21 SM |
37 | #define MLX5E_SQ_NOPS_ROOM MLX5_SEND_WQE_MAX_WQEBBS |
38 | #define MLX5E_SQ_STOP_ROOM (MLX5_SEND_WQE_MAX_WQEBBS +\ | |
39 | MLX5E_SQ_NOPS_ROOM) | |
40 | ||
41 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw) | |
42 | { | |
43 | struct mlx5_wq_cyc *wq = &sq->wq; | |
44 | ||
45 | u16 pi = sq->pc & wq->sz_m1; | |
46 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
47 | ||
48 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
49 | ||
50 | memset(cseg, 0, sizeof(*cseg)); | |
51 | ||
52 | cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP); | |
53 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | 0x01); | |
54 | ||
55 | sq->skb[pi] = NULL; | |
56 | sq->pc++; | |
d3c9bc27 | 57 | sq->stats.nop++; |
12be4b21 SM |
58 | |
59 | if (notify_hw) { | |
60 | cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
bc77b240 | 61 | mlx5e_tx_notify_hw(sq, &wqe->ctrl, 0); |
12be4b21 SM |
62 | } |
63 | } | |
64 | ||
d4e28cbd AS |
65 | static inline void mlx5e_tx_dma_unmap(struct device *pdev, |
66 | struct mlx5e_sq_dma *dma) | |
e586b3b0 | 67 | { |
d4e28cbd AS |
68 | switch (dma->type) { |
69 | case MLX5E_DMA_MAP_SINGLE: | |
70 | dma_unmap_single(pdev, dma->addr, dma->size, DMA_TO_DEVICE); | |
71 | break; | |
72 | case MLX5E_DMA_MAP_PAGE: | |
73 | dma_unmap_page(pdev, dma->addr, dma->size, DMA_TO_DEVICE); | |
74 | break; | |
75 | default: | |
76 | WARN_ONCE(true, "mlx5e_tx_dma_unmap unknown DMA type!\n"); | |
e586b3b0 AV |
77 | } |
78 | } | |
79 | ||
d4e28cbd AS |
80 | static inline void mlx5e_dma_push(struct mlx5e_sq *sq, |
81 | dma_addr_t addr, | |
82 | u32 size, | |
83 | enum mlx5e_dma_map_type map_type) | |
e586b3b0 AV |
84 | { |
85 | sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].addr = addr; | |
86 | sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].size = size; | |
d4e28cbd | 87 | sq->dma_fifo[sq->dma_fifo_pc & sq->dma_fifo_mask].type = map_type; |
e586b3b0 AV |
88 | sq->dma_fifo_pc++; |
89 | } | |
90 | ||
d4e28cbd AS |
91 | static inline struct mlx5e_sq_dma *mlx5e_dma_get(struct mlx5e_sq *sq, u32 i) |
92 | { | |
93 | return &sq->dma_fifo[i & sq->dma_fifo_mask]; | |
94 | } | |
95 | ||
34802a42 | 96 | static void mlx5e_dma_unmap_wqe_err(struct mlx5e_sq *sq, u8 num_dma) |
e586b3b0 | 97 | { |
d4e28cbd AS |
98 | int i; |
99 | ||
34802a42 | 100 | for (i = 0; i < num_dma; i++) { |
d4e28cbd AS |
101 | struct mlx5e_sq_dma *last_pushed_dma = |
102 | mlx5e_dma_get(sq, --sq->dma_fifo_pc); | |
103 | ||
104 | mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma); | |
105 | } | |
e586b3b0 AV |
106 | } |
107 | ||
108 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, | |
109 | void *accel_priv, select_queue_fallback_t fallback) | |
110 | { | |
111 | struct mlx5e_priv *priv = netdev_priv(dev); | |
112 | int channel_ix = fallback(dev, skb); | |
7ccdd084 RS |
113 | int up = 0; |
114 | ||
115 | if (!netdev_get_num_tc(dev)) | |
116 | return channel_ix; | |
117 | ||
118 | if (skb_vlan_tag_present(skb)) | |
119 | up = skb->vlan_tci >> VLAN_PRIO_SHIFT; | |
120 | ||
121 | /* channel_ix can be larger than num_channels since | |
122 | * dev->num_real_tx_queues = num_channels * num_tc | |
123 | */ | |
124 | if (channel_ix >= priv->params.num_channels) | |
125 | channel_ix = reciprocal_scale(channel_ix, | |
126 | priv->params.num_channels); | |
e586b3b0 | 127 | |
08fb1dac | 128 | return priv->channeltc_to_txq_map[channel_ix][up]; |
e586b3b0 AV |
129 | } |
130 | ||
131 | static inline u16 mlx5e_get_inline_hdr_size(struct mlx5e_sq *sq, | |
88a85f99 | 132 | struct sk_buff *skb, bool bf) |
e586b3b0 | 133 | { |
58d52291 AS |
134 | /* Some NIC TX decisions, e.g loopback, are based on the packet |
135 | * headers and occur before the data gather. | |
136 | * Therefore these headers must be copied into the WQE | |
137 | */ | |
e3a19b53 | 138 | #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
58d52291 | 139 | |
ba6c4c09 SM |
140 | if (bf) { |
141 | u16 ihs = skb_headlen(skb); | |
142 | ||
143 | if (skb_vlan_tag_present(skb)) | |
144 | ihs += VLAN_HLEN; | |
145 | ||
146 | if (ihs <= sq->max_inline) | |
147 | return skb_headlen(skb); | |
148 | } | |
58d52291 | 149 | |
e3a19b53 | 150 | return max(skb_network_offset(skb), MLX5E_MIN_INLINE); |
e586b3b0 AV |
151 | } |
152 | ||
34802a42 AS |
153 | static inline void mlx5e_tx_skb_pull_inline(unsigned char **skb_data, |
154 | unsigned int *skb_len, | |
155 | unsigned int len) | |
156 | { | |
157 | *skb_len -= len; | |
158 | *skb_data += len; | |
159 | } | |
160 | ||
161 | static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs, | |
162 | unsigned char **skb_data, | |
163 | unsigned int *skb_len) | |
e4cf27bd AS |
164 | { |
165 | struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start; | |
166 | int cpy1_sz = 2 * ETH_ALEN; | |
3ea4891d | 167 | int cpy2_sz = ihs - cpy1_sz; |
e4cf27bd | 168 | |
34802a42 AS |
169 | memcpy(vhdr, *skb_data, cpy1_sz); |
170 | mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy1_sz); | |
e4cf27bd AS |
171 | vhdr->h_vlan_proto = skb->vlan_proto; |
172 | vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb)); | |
34802a42 AS |
173 | memcpy(&vhdr->h_vlan_encapsulated_proto, *skb_data, cpy2_sz); |
174 | mlx5e_tx_skb_pull_inline(skb_data, skb_len, cpy2_sz); | |
e4cf27bd AS |
175 | } |
176 | ||
e586b3b0 AV |
177 | static netdev_tx_t mlx5e_sq_xmit(struct mlx5e_sq *sq, struct sk_buff *skb) |
178 | { | |
179 | struct mlx5_wq_cyc *wq = &sq->wq; | |
180 | ||
181 | u16 pi = sq->pc & wq->sz_m1; | |
182 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
34802a42 | 183 | struct mlx5e_tx_wqe_info *wi = &sq->wqe_info[pi]; |
e586b3b0 AV |
184 | |
185 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
186 | struct mlx5_wqe_eth_seg *eseg = &wqe->eth; | |
187 | struct mlx5_wqe_data_seg *dseg; | |
188 | ||
34802a42 AS |
189 | unsigned char *skb_data = skb->data; |
190 | unsigned int skb_len = skb->len; | |
e586b3b0 AV |
191 | u8 opcode = MLX5_OPCODE_SEND; |
192 | dma_addr_t dma_addr = 0; | |
b081da5e | 193 | unsigned int num_bytes; |
88a85f99 | 194 | bool bf = false; |
e586b3b0 AV |
195 | u16 headlen; |
196 | u16 ds_cnt; | |
197 | u16 ihs; | |
198 | int i; | |
199 | ||
200 | memset(wqe, 0, sizeof(*wqe)); | |
201 | ||
98795158 MF |
202 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
203 | eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM; | |
89db09eb | 204 | if (skb->encapsulation) { |
98795158 MF |
205 | eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM | |
206 | MLX5_ETH_WQE_L4_INNER_CSUM; | |
bfe6d8d1 | 207 | sq->stats.csum_partial_inner++; |
89db09eb | 208 | } else { |
98795158 | 209 | eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM; |
89db09eb | 210 | } |
98795158 | 211 | } else |
bfe6d8d1 | 212 | sq->stats.csum_none++; |
e586b3b0 | 213 | |
88a85f99 AS |
214 | if (sq->cc != sq->prev_cc) { |
215 | sq->prev_cc = sq->cc; | |
216 | sq->bf_budget = (sq->cc == sq->pc) ? MLX5E_SQ_BF_BUDGET : 0; | |
217 | } | |
218 | ||
e586b3b0 | 219 | if (skb_is_gso(skb)) { |
e586b3b0 AV |
220 | eseg->mss = cpu_to_be16(skb_shinfo(skb)->gso_size); |
221 | opcode = MLX5_OPCODE_LSO; | |
98795158 | 222 | |
89db09eb | 223 | if (skb->encapsulation) { |
98795158 | 224 | ihs = skb_inner_transport_offset(skb) + inner_tcp_hdrlen(skb); |
89db09eb MF |
225 | sq->stats.tso_inner_packets++; |
226 | sq->stats.tso_inner_bytes += skb->len - ihs; | |
227 | } else { | |
98795158 | 228 | ihs = skb_transport_offset(skb) + tcp_hdrlen(skb); |
89db09eb MF |
229 | sq->stats.tso_packets++; |
230 | sq->stats.tso_bytes += skb->len - ihs; | |
231 | } | |
98795158 | 232 | |
b081da5e | 233 | num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs; |
e586b3b0 | 234 | } else { |
88a85f99 AS |
235 | bf = sq->bf_budget && |
236 | !skb->xmit_more && | |
237 | !skb_shinfo(skb)->nr_frags; | |
238 | ihs = mlx5e_get_inline_hdr_size(sq, skb, bf); | |
b081da5e | 239 | num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
e586b3b0 AV |
240 | } |
241 | ||
b081da5e GP |
242 | wi->num_bytes = num_bytes; |
243 | ||
e4cf27bd | 244 | if (skb_vlan_tag_present(skb)) { |
34802a42 AS |
245 | mlx5e_insert_vlan(eseg->inline_hdr_start, skb, ihs, &skb_data, |
246 | &skb_len); | |
3ea4891d | 247 | ihs += VLAN_HLEN; |
e4cf27bd | 248 | } else { |
34802a42 AS |
249 | memcpy(eseg->inline_hdr_start, skb_data, ihs); |
250 | mlx5e_tx_skb_pull_inline(&skb_data, &skb_len, ihs); | |
e4cf27bd | 251 | } |
e586b3b0 | 252 | |
8ca56ce3 | 253 | eseg->inline_hdr_sz = cpu_to_be16(ihs); |
e586b3b0 AV |
254 | |
255 | ds_cnt = sizeof(*wqe) / MLX5_SEND_WQE_DS; | |
256 | ds_cnt += DIV_ROUND_UP(ihs - sizeof(eseg->inline_hdr_start), | |
257 | MLX5_SEND_WQE_DS); | |
258 | dseg = (struct mlx5_wqe_data_seg *)cseg + ds_cnt; | |
259 | ||
34802a42 | 260 | wi->num_dma = 0; |
e586b3b0 | 261 | |
34802a42 | 262 | headlen = skb_len - skb->data_len; |
e586b3b0 | 263 | if (headlen) { |
34802a42 | 264 | dma_addr = dma_map_single(sq->pdev, skb_data, headlen, |
e586b3b0 AV |
265 | DMA_TO_DEVICE); |
266 | if (unlikely(dma_mapping_error(sq->pdev, dma_addr))) | |
267 | goto dma_unmap_wqe_err; | |
268 | ||
269 | dseg->addr = cpu_to_be64(dma_addr); | |
270 | dseg->lkey = sq->mkey_be; | |
271 | dseg->byte_count = cpu_to_be32(headlen); | |
272 | ||
d4e28cbd | 273 | mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE); |
34802a42 | 274 | wi->num_dma++; |
e586b3b0 AV |
275 | |
276 | dseg++; | |
277 | } | |
278 | ||
279 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
280 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; | |
281 | int fsz = skb_frag_size(frag); | |
282 | ||
283 | dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz, | |
284 | DMA_TO_DEVICE); | |
285 | if (unlikely(dma_mapping_error(sq->pdev, dma_addr))) | |
286 | goto dma_unmap_wqe_err; | |
287 | ||
288 | dseg->addr = cpu_to_be64(dma_addr); | |
289 | dseg->lkey = sq->mkey_be; | |
290 | dseg->byte_count = cpu_to_be32(fsz); | |
291 | ||
d4e28cbd | 292 | mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE); |
34802a42 | 293 | wi->num_dma++; |
e586b3b0 AV |
294 | |
295 | dseg++; | |
296 | } | |
297 | ||
34802a42 | 298 | ds_cnt += wi->num_dma; |
e586b3b0 | 299 | |
8ca56ce3 AS |
300 | cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | opcode); |
301 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); | |
e586b3b0 AV |
302 | |
303 | sq->skb[pi] = skb; | |
304 | ||
34802a42 AS |
305 | wi->num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS); |
306 | sq->pc += wi->num_wqebbs; | |
e586b3b0 | 307 | |
34802a42 | 308 | netdev_tx_sent_queue(sq->txq, wi->num_bytes); |
e586b3b0 | 309 | |
ef9814de EBE |
310 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) |
311 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
312 | ||
12be4b21 | 313 | if (unlikely(!mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM))) { |
e586b3b0 AV |
314 | netif_tx_stop_queue(sq->txq); |
315 | sq->stats.stopped++; | |
316 | } | |
317 | ||
059ba072 | 318 | if (!skb->xmit_more || netif_xmit_stopped(sq->txq)) { |
88a85f99 AS |
319 | int bf_sz = 0; |
320 | ||
0ba42241 | 321 | if (bf && test_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state)) |
34802a42 | 322 | bf_sz = wi->num_wqebbs << 3; |
88a85f99 | 323 | |
059ba072 | 324 | cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; |
bc77b240 | 325 | mlx5e_tx_notify_hw(sq, &wqe->ctrl, bf_sz); |
059ba072 | 326 | } |
e586b3b0 | 327 | |
12be4b21 SM |
328 | /* fill sq edge with nops to avoid wqe wrap around */ |
329 | while ((sq->pc & wq->sz_m1) > sq->edge) | |
330 | mlx5e_send_nop(sq, false); | |
331 | ||
0ca00fc1 EC |
332 | if (bf) |
333 | sq->bf_budget--; | |
88a85f99 | 334 | |
e586b3b0 | 335 | sq->stats.packets++; |
b081da5e | 336 | sq->stats.bytes += num_bytes; |
e586b3b0 AV |
337 | return NETDEV_TX_OK; |
338 | ||
339 | dma_unmap_wqe_err: | |
340 | sq->stats.dropped++; | |
34802a42 | 341 | mlx5e_dma_unmap_wqe_err(sq, wi->num_dma); |
e586b3b0 AV |
342 | |
343 | dev_kfree_skb_any(skb); | |
344 | ||
345 | return NETDEV_TX_OK; | |
346 | } | |
347 | ||
348 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev) | |
349 | { | |
350 | struct mlx5e_priv *priv = netdev_priv(dev); | |
03289b88 | 351 | struct mlx5e_sq *sq = priv->txq_to_sq_map[skb_get_queue_mapping(skb)]; |
e586b3b0 AV |
352 | |
353 | return mlx5e_sq_xmit(sq, skb); | |
354 | } | |
355 | ||
29429f33 DJ |
356 | void mlx5e_free_tx_descs(struct mlx5e_sq *sq) |
357 | { | |
358 | struct mlx5e_tx_wqe_info *wi; | |
359 | struct sk_buff *skb; | |
360 | u16 ci; | |
361 | int i; | |
362 | ||
363 | while (sq->cc != sq->pc) { | |
364 | ci = sq->cc & sq->wq.sz_m1; | |
365 | skb = sq->skb[ci]; | |
366 | wi = &sq->wqe_info[ci]; | |
367 | ||
368 | if (!skb) { /* nop */ | |
369 | sq->cc++; | |
370 | continue; | |
371 | } | |
372 | ||
373 | for (i = 0; i < wi->num_dma; i++) { | |
374 | struct mlx5e_sq_dma *dma = | |
375 | mlx5e_dma_get(sq, sq->dma_fifo_cc++); | |
376 | ||
377 | mlx5e_tx_dma_unmap(sq->pdev, dma); | |
378 | } | |
379 | ||
380 | dev_kfree_skb_any(skb); | |
381 | sq->cc += wi->num_wqebbs; | |
382 | } | |
383 | } | |
384 | ||
8ec736e5 | 385 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget) |
e586b3b0 AV |
386 | { |
387 | struct mlx5e_sq *sq; | |
388 | u32 dma_fifo_cc; | |
389 | u32 nbytes; | |
390 | u16 npkts; | |
391 | u16 sqcc; | |
392 | int i; | |
393 | ||
e3391054 | 394 | sq = container_of(cq, struct mlx5e_sq, cq); |
e586b3b0 | 395 | |
29429f33 DJ |
396 | if (unlikely(test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state))) |
397 | return false; | |
398 | ||
e586b3b0 AV |
399 | npkts = 0; |
400 | nbytes = 0; | |
401 | ||
402 | /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), | |
403 | * otherwise a cq overrun may occur | |
404 | */ | |
405 | sqcc = sq->cc; | |
406 | ||
407 | /* avoid dirtying sq cache line every cqe */ | |
408 | dma_fifo_cc = sq->dma_fifo_cc; | |
409 | ||
410 | for (i = 0; i < MLX5E_TX_CQ_POLL_BUDGET; i++) { | |
411 | struct mlx5_cqe64 *cqe; | |
059ba072 AS |
412 | u16 wqe_counter; |
413 | bool last_wqe; | |
e586b3b0 AV |
414 | |
415 | cqe = mlx5e_get_cqe(cq); | |
416 | if (!cqe) | |
417 | break; | |
418 | ||
a1f5a1a8 AS |
419 | mlx5_cqwq_pop(&cq->wq); |
420 | ||
059ba072 AS |
421 | wqe_counter = be16_to_cpu(cqe->wqe_counter); |
422 | ||
423 | do { | |
34802a42 | 424 | struct mlx5e_tx_wqe_info *wi; |
059ba072 AS |
425 | struct sk_buff *skb; |
426 | u16 ci; | |
427 | int j; | |
428 | ||
429 | last_wqe = (sqcc == wqe_counter); | |
430 | ||
431 | ci = sqcc & sq->wq.sz_m1; | |
432 | skb = sq->skb[ci]; | |
34802a42 | 433 | wi = &sq->wqe_info[ci]; |
e586b3b0 | 434 | |
059ba072 | 435 | if (unlikely(!skb)) { /* nop */ |
059ba072 AS |
436 | sqcc++; |
437 | continue; | |
438 | } | |
e586b3b0 | 439 | |
ef9814de EBE |
440 | if (unlikely(skb_shinfo(skb)->tx_flags & |
441 | SKBTX_HW_TSTAMP)) { | |
442 | struct skb_shared_hwtstamps hwts = {}; | |
443 | ||
444 | mlx5e_fill_hwstamp(sq->tstamp, | |
445 | get_cqe_ts(cqe), &hwts); | |
446 | skb_tstamp_tx(skb, &hwts); | |
447 | } | |
448 | ||
34802a42 | 449 | for (j = 0; j < wi->num_dma; j++) { |
d4e28cbd AS |
450 | struct mlx5e_sq_dma *dma = |
451 | mlx5e_dma_get(sq, dma_fifo_cc++); | |
e586b3b0 | 452 | |
d4e28cbd | 453 | mlx5e_tx_dma_unmap(sq->pdev, dma); |
059ba072 | 454 | } |
e586b3b0 | 455 | |
059ba072 | 456 | npkts++; |
34802a42 AS |
457 | nbytes += wi->num_bytes; |
458 | sqcc += wi->num_wqebbs; | |
8ec736e5 | 459 | napi_consume_skb(skb, napi_budget); |
059ba072 | 460 | } while (!last_wqe); |
e586b3b0 AV |
461 | } |
462 | ||
463 | mlx5_cqwq_update_db_record(&cq->wq); | |
464 | ||
465 | /* ensure cq space is freed before enabling more cqes */ | |
466 | wmb(); | |
467 | ||
468 | sq->dma_fifo_cc = dma_fifo_cc; | |
469 | sq->cc = sqcc; | |
470 | ||
471 | netdev_tx_completed_queue(sq->txq, npkts, nbytes); | |
472 | ||
473 | if (netif_tx_queue_stopped(sq->txq) && | |
12be4b21 | 474 | mlx5e_sq_has_room_for(sq, MLX5E_SQ_STOP_ROOM) && |
e586b3b0 AV |
475 | likely(test_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state))) { |
476 | netif_tx_wake_queue(sq->txq); | |
477 | sq->stats.wake++; | |
478 | } | |
e586b3b0 | 479 | |
59a7c2fd | 480 | return (i == MLX5E_TX_CQ_POLL_BUDGET); |
e586b3b0 | 481 | } |