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e586b3b0 | 1 | /* |
98795158 | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
e586b3b0 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/tcp.h> | |
34 | #include <linux/if_vlan.h> | |
e3cfc7e6 | 35 | #include <net/geneve.h> |
fbcb127e | 36 | #include <net/dsfield.h> |
e586b3b0 | 37 | #include "en.h" |
542578c6 | 38 | #include "en/txrx.h" |
4301ba7b | 39 | #include "ipoib/ipoib.h" |
bf239741 | 40 | #include "en_accel/en_accel.h" |
428ffea0 | 41 | #include "en_accel/ipsec_rxtx.h" |
9515978e | 42 | #include "en_accel/macsec.h" |
145e5637 | 43 | #include "en/ptp.h" |
de78960e | 44 | #include <net/ipv6.h> |
e586b3b0 | 45 | |
31391048 | 46 | static void mlx5e_dma_unmap_wqe_err(struct mlx5e_txqsq *sq, u8 num_dma) |
e586b3b0 | 47 | { |
d4e28cbd AS |
48 | int i; |
49 | ||
34802a42 | 50 | for (i = 0; i < num_dma; i++) { |
d4e28cbd AS |
51 | struct mlx5e_sq_dma *last_pushed_dma = |
52 | mlx5e_dma_get(sq, --sq->dma_fifo_pc); | |
53 | ||
54 | mlx5e_tx_dma_unmap(sq->pdev, last_pushed_dma); | |
55 | } | |
e586b3b0 AV |
56 | } |
57 | ||
ae76715d HHZ |
58 | static inline int mlx5e_skb_l2_header_offset(struct sk_buff *skb) |
59 | { | |
60 | #define MLX5E_MIN_INLINE (ETH_HLEN + VLAN_HLEN) | |
61 | ||
62 | return max(skb_network_offset(skb), MLX5E_MIN_INLINE); | |
63 | } | |
64 | ||
65 | static inline int mlx5e_skb_l3_header_offset(struct sk_buff *skb) | |
66 | { | |
ae76715d HHZ |
67 | if (skb_transport_header_was_set(skb)) |
68 | return skb_transport_offset(skb); | |
ae76715d HHZ |
69 | else |
70 | return mlx5e_skb_l2_header_offset(skb); | |
71 | } | |
72 | ||
6aace17e MS |
73 | static inline u16 mlx5e_calc_min_inline(enum mlx5_inline_modes mode, |
74 | struct sk_buff *skb) | |
ae76715d | 75 | { |
6aace17e | 76 | u16 hlen; |
ae76715d HHZ |
77 | |
78 | switch (mode) { | |
a6f402e4 SM |
79 | case MLX5_INLINE_MODE_NONE: |
80 | return 0; | |
ae76715d | 81 | case MLX5_INLINE_MODE_TCP_UDP: |
c43f1255 | 82 | hlen = eth_get_headlen(skb->dev, skb->data, skb_headlen(skb)); |
ae76715d HHZ |
83 | if (hlen == ETH_HLEN && !skb_vlan_tag_present(skb)) |
84 | hlen += VLAN_HLEN; | |
6aace17e | 85 | break; |
ae76715d | 86 | case MLX5_INLINE_MODE_IP: |
3517dfe6 MM |
87 | hlen = mlx5e_skb_l3_header_offset(skb); |
88 | break; | |
ae76715d HHZ |
89 | case MLX5_INLINE_MODE_L2: |
90 | default: | |
6aace17e | 91 | hlen = mlx5e_skb_l2_header_offset(skb); |
ae76715d | 92 | } |
f600c608 | 93 | return min_t(u16, hlen, skb_headlen(skb)); |
ae76715d HHZ |
94 | } |
95 | ||
de78960e ED |
96 | #define MLX5_UNSAFE_MEMCPY_DISCLAIMER \ |
97 | "This copy has been bounds-checked earlier in " \ | |
98 | "mlx5i_sq_calc_wqe_attr() and intentionally " \ | |
99 | "crosses a flex array boundary. Since it is " \ | |
100 | "performance sensitive, splitting the copy is " \ | |
101 | "undesirable." | |
102 | ||
5e7d77a9 | 103 | static inline void mlx5e_insert_vlan(void *start, struct sk_buff *skb, u16 ihs) |
e4cf27bd AS |
104 | { |
105 | struct vlan_ethhdr *vhdr = (struct vlan_ethhdr *)start; | |
106 | int cpy1_sz = 2 * ETH_ALEN; | |
3ea4891d | 107 | int cpy2_sz = ihs - cpy1_sz; |
e4cf27bd | 108 | |
6d5c900e | 109 | memcpy(&vhdr->addrs, skb->data, cpy1_sz); |
e4cf27bd AS |
110 | vhdr->h_vlan_proto = skb->vlan_proto; |
111 | vhdr->h_vlan_TCI = cpu_to_be16(skb_vlan_tag_get(skb)); | |
de78960e ED |
112 | unsafe_memcpy(&vhdr->h_vlan_encapsulated_proto, |
113 | skb->data + cpy1_sz, | |
114 | cpy2_sz, | |
115 | MLX5_UNSAFE_MEMCPY_DISCLAIMER); | |
e4cf27bd AS |
116 | } |
117 | ||
77bdf895 | 118 | static inline void |
b336e6b2 TT |
119 | mlx5e_txwqe_build_eseg_csum(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
120 | struct mlx5e_accel_tx_state *accel, | |
121 | struct mlx5_wqe_eth_seg *eseg) | |
e586b3b0 | 122 | { |
428ffea0 | 123 | if (unlikely(mlx5e_ipsec_txwqe_build_eseg_csum(sq, skb, eseg))) |
1d000323 | 124 | return; |
1d000323 | 125 | |
98795158 MF |
126 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
127 | eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM; | |
89db09eb | 128 | if (skb->encapsulation) { |
98795158 MF |
129 | eseg->cs_flags |= MLX5_ETH_WQE_L3_INNER_CSUM | |
130 | MLX5_ETH_WQE_L4_INNER_CSUM; | |
05909bab | 131 | sq->stats->csum_partial_inner++; |
89db09eb | 132 | } else { |
98795158 | 133 | eseg->cs_flags |= MLX5_ETH_WQE_L4_CSUM; |
05909bab | 134 | sq->stats->csum_partial++; |
89db09eb | 135 | } |
b336e6b2 TT |
136 | #ifdef CONFIG_MLX5_EN_TLS |
137 | } else if (unlikely(accel && accel->tls.tls_tisn)) { | |
138 | eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM; | |
139 | sq->stats->csum_partial++; | |
140 | #endif | |
98795158 | 141 | } else |
05909bab | 142 | sq->stats->csum_none++; |
77bdf895 | 143 | } |
e586b3b0 | 144 | |
de78960e ED |
145 | /* Returns the number of header bytes that we plan |
146 | * to inline later in the transmit descriptor | |
147 | */ | |
77bdf895 | 148 | static inline u16 |
de78960e | 149 | mlx5e_tx_get_gso_ihs(struct mlx5e_txqsq *sq, struct sk_buff *skb, int *hopbyhop) |
77bdf895 | 150 | { |
05909bab | 151 | struct mlx5e_sq_stats *stats = sq->stats; |
77bdf895 | 152 | u16 ihs; |
98795158 | 153 | |
de78960e | 154 | *hopbyhop = 0; |
77bdf895 | 155 | if (skb->encapsulation) { |
ec082d31 | 156 | ihs = skb_inner_tcp_all_headers(skb); |
05909bab EBE |
157 | stats->tso_inner_packets++; |
158 | stats->tso_inner_bytes += skb->len - ihs; | |
e586b3b0 | 159 | } else { |
de78960e | 160 | if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { |
689adf0d | 161 | ihs = skb_transport_offset(skb) + sizeof(struct udphdr); |
de78960e | 162 | } else { |
504148fe | 163 | ihs = skb_tcp_all_headers(skb); |
de78960e ED |
164 | if (ipv6_has_hopopt_jumbo(skb)) { |
165 | *hopbyhop = sizeof(struct hop_jumbo_hdr); | |
166 | ihs -= sizeof(struct hop_jumbo_hdr); | |
167 | } | |
168 | } | |
05909bab | 169 | stats->tso_packets++; |
de78960e | 170 | stats->tso_bytes += skb->len - ihs - *hopbyhop; |
e586b3b0 AV |
171 | } |
172 | ||
77bdf895 SM |
173 | return ihs; |
174 | } | |
e586b3b0 | 175 | |
77bdf895 SM |
176 | static inline int |
177 | mlx5e_txwqe_build_dsegs(struct mlx5e_txqsq *sq, struct sk_buff *skb, | |
178 | unsigned char *skb_data, u16 headlen, | |
179 | struct mlx5_wqe_data_seg *dseg) | |
180 | { | |
181 | dma_addr_t dma_addr = 0; | |
182 | u8 num_dma = 0; | |
183 | int i; | |
e586b3b0 | 184 | |
e586b3b0 | 185 | if (headlen) { |
34802a42 | 186 | dma_addr = dma_map_single(sq->pdev, skb_data, headlen, |
e586b3b0 AV |
187 | DMA_TO_DEVICE); |
188 | if (unlikely(dma_mapping_error(sq->pdev, dma_addr))) | |
d9a96ec3 | 189 | goto dma_unmap_wqe_err; |
e586b3b0 AV |
190 | |
191 | dseg->addr = cpu_to_be64(dma_addr); | |
192 | dseg->lkey = sq->mkey_be; | |
193 | dseg->byte_count = cpu_to_be32(headlen); | |
194 | ||
d4e28cbd | 195 | mlx5e_dma_push(sq, dma_addr, headlen, MLX5E_DMA_MAP_SINGLE); |
77bdf895 | 196 | num_dma++; |
e586b3b0 AV |
197 | dseg++; |
198 | } | |
199 | ||
200 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
d7840976 | 201 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
e586b3b0 AV |
202 | int fsz = skb_frag_size(frag); |
203 | ||
204 | dma_addr = skb_frag_dma_map(sq->pdev, frag, 0, fsz, | |
e53eef63 | 205 | DMA_TO_DEVICE); |
e586b3b0 | 206 | if (unlikely(dma_mapping_error(sq->pdev, dma_addr))) |
d9a96ec3 | 207 | goto dma_unmap_wqe_err; |
e586b3b0 AV |
208 | |
209 | dseg->addr = cpu_to_be64(dma_addr); | |
210 | dseg->lkey = sq->mkey_be; | |
211 | dseg->byte_count = cpu_to_be32(fsz); | |
212 | ||
d4e28cbd | 213 | mlx5e_dma_push(sq, dma_addr, fsz, MLX5E_DMA_MAP_PAGE); |
77bdf895 | 214 | num_dma++; |
e586b3b0 AV |
215 | dseg++; |
216 | } | |
217 | ||
77bdf895 | 218 | return num_dma; |
d9a96ec3 TT |
219 | |
220 | dma_unmap_wqe_err: | |
221 | mlx5e_dma_unmap_wqe_err(sq, num_dma); | |
222 | return -ENOMEM; | |
77bdf895 | 223 | } |
e586b3b0 | 224 | |
8e4b53f6 MM |
225 | struct mlx5e_tx_attr { |
226 | u32 num_bytes; | |
227 | u16 headlen; | |
228 | u16 ihs; | |
229 | __be16 mss; | |
5be01904 | 230 | u16 insz; |
8e4b53f6 | 231 | u8 opcode; |
de78960e | 232 | u8 hopbyhop; |
8e4b53f6 MM |
233 | }; |
234 | ||
235 | struct mlx5e_tx_wqe_attr { | |
236 | u16 ds_cnt; | |
237 | u16 ds_cnt_inl; | |
5be01904 | 238 | u16 ds_cnt_ids; |
8e4b53f6 MM |
239 | u8 num_wqebbs; |
240 | }; | |
d02dfcd5 MM |
241 | |
242 | static u8 | |
8e4b53f6 MM |
243 | mlx5e_tx_wqe_inline_mode(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
244 | struct mlx5e_accel_tx_state *accel) | |
d02dfcd5 MM |
245 | { |
246 | u8 mode; | |
247 | ||
8e4b53f6 MM |
248 | #ifdef CONFIG_MLX5_EN_TLS |
249 | if (accel && accel->tls.tls_tisn) | |
d02dfcd5 | 250 | return MLX5_INLINE_MODE_TCP_UDP; |
8e4b53f6 | 251 | #endif |
d02dfcd5 MM |
252 | |
253 | mode = sq->min_inline_mode; | |
254 | ||
255 | if (skb_vlan_tag_present(skb) && | |
256 | test_bit(MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, &sq->state)) | |
257 | mode = max_t(u8, MLX5_INLINE_MODE_L2, mode); | |
258 | ||
259 | return mode; | |
260 | } | |
261 | ||
8e4b53f6 MM |
262 | static void mlx5e_sq_xmit_prepare(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
263 | struct mlx5e_accel_tx_state *accel, | |
264 | struct mlx5e_tx_attr *attr) | |
265 | { | |
266 | struct mlx5e_sq_stats *stats = sq->stats; | |
267 | ||
268 | if (skb_is_gso(skb)) { | |
de78960e ED |
269 | int hopbyhop; |
270 | u16 ihs = mlx5e_tx_get_gso_ihs(sq, skb, &hopbyhop); | |
8e4b53f6 MM |
271 | |
272 | *attr = (struct mlx5e_tx_attr) { | |
273 | .opcode = MLX5_OPCODE_LSO, | |
274 | .mss = cpu_to_be16(skb_shinfo(skb)->gso_size), | |
275 | .ihs = ihs, | |
276 | .num_bytes = skb->len + (skb_shinfo(skb)->gso_segs - 1) * ihs, | |
de78960e ED |
277 | .headlen = skb_headlen(skb) - ihs - hopbyhop, |
278 | .hopbyhop = hopbyhop, | |
8e4b53f6 MM |
279 | }; |
280 | ||
281 | stats->packets += skb_shinfo(skb)->gso_segs; | |
282 | } else { | |
283 | u8 mode = mlx5e_tx_wqe_inline_mode(sq, skb, accel); | |
284 | u16 ihs = mlx5e_calc_min_inline(mode, skb); | |
285 | ||
286 | *attr = (struct mlx5e_tx_attr) { | |
287 | .opcode = MLX5_OPCODE_SEND, | |
288 | .mss = cpu_to_be16(0), | |
289 | .ihs = ihs, | |
290 | .num_bytes = max_t(unsigned int, skb->len, ETH_ZLEN), | |
291 | .headlen = skb_headlen(skb) - ihs, | |
292 | }; | |
293 | ||
294 | stats->packets++; | |
295 | } | |
296 | ||
5be01904 | 297 | attr->insz = mlx5e_accel_tx_ids_len(sq, accel); |
8e4b53f6 MM |
298 | stats->bytes += attr->num_bytes; |
299 | } | |
300 | ||
301 | static void mlx5e_sq_calc_wqe_attr(struct sk_buff *skb, const struct mlx5e_tx_attr *attr, | |
302 | struct mlx5e_tx_wqe_attr *wqe_attr) | |
303 | { | |
97e3afd6 | 304 | u16 ds_cnt = MLX5E_TX_WQE_EMPTY_DS_COUNT; |
8e4b53f6 | 305 | u16 ds_cnt_inl = 0; |
5be01904 | 306 | u16 ds_cnt_ids = 0; |
8e4b53f6 | 307 | |
f9c955b4 MM |
308 | /* Sync the calculation with MLX5E_MAX_TX_WQEBBS. */ |
309 | ||
5be01904 RS |
310 | if (attr->insz) |
311 | ds_cnt_ids = DIV_ROUND_UP(sizeof(struct mlx5_wqe_inline_seg) + attr->insz, | |
312 | MLX5_SEND_WQE_DS); | |
8e4b53f6 | 313 | |
5be01904 | 314 | ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags + ds_cnt_ids; |
8e4b53f6 MM |
315 | if (attr->ihs) { |
316 | u16 inl = attr->ihs - INL_HDR_START_SZ; | |
317 | ||
318 | if (skb_vlan_tag_present(skb)) | |
319 | inl += VLAN_HLEN; | |
320 | ||
321 | ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS); | |
f9c955b4 MM |
322 | if (WARN_ON_ONCE(ds_cnt_inl > MLX5E_MAX_TX_INLINE_DS)) |
323 | netdev_warn(skb->dev, "ds_cnt_inl = %u > max %u\n", ds_cnt_inl, | |
324 | (u16)MLX5E_MAX_TX_INLINE_DS); | |
8e4b53f6 MM |
325 | ds_cnt += ds_cnt_inl; |
326 | } | |
327 | ||
328 | *wqe_attr = (struct mlx5e_tx_wqe_attr) { | |
329 | .ds_cnt = ds_cnt, | |
330 | .ds_cnt_inl = ds_cnt_inl, | |
5be01904 | 331 | .ds_cnt_ids = ds_cnt_ids, |
8e4b53f6 MM |
332 | .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS), |
333 | }; | |
334 | } | |
335 | ||
67044a88 MM |
336 | static void mlx5e_tx_skb_update_hwts_flags(struct sk_buff *skb) |
337 | { | |
338 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) | |
339 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
340 | } | |
341 | ||
342 | static void mlx5e_tx_check_stop(struct mlx5e_txqsq *sq) | |
343 | { | |
344 | if (unlikely(!mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room))) { | |
345 | netif_tx_stop_queue(sq->txq); | |
346 | sq->stats->stopped++; | |
347 | } | |
348 | } | |
349 | ||
5b759bf2 MM |
350 | static void mlx5e_tx_flush(struct mlx5e_txqsq *sq) |
351 | { | |
352 | struct mlx5e_tx_wqe_info *wi; | |
353 | struct mlx5e_tx_wqe *wqe; | |
354 | u16 pi; | |
355 | ||
356 | /* Must not be called when a MPWQE session is active but empty. */ | |
357 | mlx5e_tx_mpwqe_ensure_complete(sq); | |
358 | ||
359 | pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc); | |
360 | wi = &sq->db.wqe_info[pi]; | |
361 | ||
362 | *wi = (struct mlx5e_tx_wqe_info) { | |
363 | .num_wqebbs = 1, | |
364 | }; | |
365 | ||
366 | wqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc); | |
367 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &wqe->ctrl); | |
368 | } | |
369 | ||
77bdf895 SM |
370 | static inline void |
371 | mlx5e_txwqe_complete(struct mlx5e_txqsq *sq, struct sk_buff *skb, | |
8e4b53f6 MM |
372 | const struct mlx5e_tx_attr *attr, |
373 | const struct mlx5e_tx_wqe_attr *wqe_attr, u8 num_dma, | |
3c31ff22 FW |
374 | struct mlx5e_tx_wqe_info *wi, struct mlx5_wqe_ctrl_seg *cseg, |
375 | bool xmit_more) | |
77bdf895 SM |
376 | { |
377 | struct mlx5_wq_cyc *wq = &sq->wq; | |
ca6c7df0 | 378 | bool send_doorbell; |
e586b3b0 | 379 | |
8ba6f183 MM |
380 | *wi = (struct mlx5e_tx_wqe_info) { |
381 | .skb = skb, | |
8e4b53f6 | 382 | .num_bytes = attr->num_bytes, |
8ba6f183 | 383 | .num_dma = num_dma, |
8e4b53f6 | 384 | .num_wqebbs = wqe_attr->num_wqebbs, |
338c46c6 | 385 | .num_fifo_pkts = 0, |
8ba6f183 | 386 | }; |
e586b3b0 | 387 | |
8e4b53f6 MM |
388 | cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | attr->opcode); |
389 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | wqe_attr->ds_cnt); | |
77bdf895 | 390 | |
67044a88 | 391 | mlx5e_tx_skb_update_hwts_flags(skb); |
ef9814de | 392 | |
77bdf895 | 393 | sq->pc += wi->num_wqebbs; |
67044a88 MM |
394 | |
395 | mlx5e_tx_check_stop(sq); | |
e586b3b0 | 396 | |
1880bc4e EBE |
397 | if (unlikely(sq->ptpsq)) { |
398 | mlx5e_skb_cb_hwtstamp_init(skb); | |
399 | mlx5e_skb_fifo_push(&sq->ptpsq->skb_fifo, skb); | |
19b43a43 AL |
400 | if (!netif_tx_queue_stopped(sq->txq) && |
401 | !mlx5e_skb_fifo_has_room(&sq->ptpsq->skb_fifo)) { | |
402 | netif_tx_stop_queue(sq->txq); | |
403 | sq->stats->stopped++; | |
404 | } | |
1880bc4e EBE |
405 | skb_get(skb); |
406 | } | |
407 | ||
8e4b53f6 | 408 | send_doorbell = __netdev_tx_sent_queue(sq->txq, attr->num_bytes, xmit_more); |
ca6c7df0 | 409 | if (send_doorbell) |
864b2d71 | 410 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, cseg); |
77bdf895 SM |
411 | } |
412 | ||
8e4b53f6 MM |
413 | static void |
414 | mlx5e_sq_xmit_wqe(struct mlx5e_txqsq *sq, struct sk_buff *skb, | |
415 | const struct mlx5e_tx_attr *attr, const struct mlx5e_tx_wqe_attr *wqe_attr, | |
416 | struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more) | |
77bdf895 | 417 | { |
043dc78e TT |
418 | struct mlx5_wqe_ctrl_seg *cseg; |
419 | struct mlx5_wqe_eth_seg *eseg; | |
420 | struct mlx5_wqe_data_seg *dseg; | |
421 | struct mlx5e_tx_wqe_info *wi; | |
de78960e ED |
422 | u16 ihs = attr->ihs; |
423 | struct ipv6hdr *h6; | |
05909bab | 424 | struct mlx5e_sq_stats *stats = sq->stats; |
77bdf895 | 425 | int num_dma; |
043dc78e | 426 | |
299a1195 | 427 | stats->xmit_more += xmit_more; |
77bdf895 | 428 | |
043dc78e TT |
429 | /* fill wqe */ |
430 | wi = &sq->db.wqe_info[pi]; | |
431 | cseg = &wqe->ctrl; | |
432 | eseg = &wqe->eth; | |
433 | dseg = wqe->data; | |
434 | ||
8e4b53f6 | 435 | eseg->mss = attr->mss; |
043dc78e | 436 | |
de78960e ED |
437 | if (ihs) { |
438 | u8 *start = eseg->inline_hdr.start; | |
439 | ||
440 | if (unlikely(attr->hopbyhop)) { | |
441 | /* remove the HBH header. | |
442 | * Layout: [Ethernet header][IPv6 header][HBH][TCP header] | |
443 | */ | |
444 | if (skb_vlan_tag_present(skb)) { | |
445 | mlx5e_insert_vlan(start, skb, ETH_HLEN + sizeof(*h6)); | |
446 | ihs += VLAN_HLEN; | |
447 | h6 = (struct ipv6hdr *)(start + sizeof(struct vlan_ethhdr)); | |
448 | } else { | |
449 | unsafe_memcpy(start, skb->data, | |
450 | ETH_HLEN + sizeof(*h6), | |
451 | MLX5_UNSAFE_MEMCPY_DISCLAIMER); | |
452 | h6 = (struct ipv6hdr *)(start + ETH_HLEN); | |
453 | } | |
454 | h6->nexthdr = IPPROTO_TCP; | |
455 | /* Copy the TCP header after the IPv6 one */ | |
456 | memcpy(h6 + 1, | |
457 | skb->data + ETH_HLEN + sizeof(*h6) + | |
458 | sizeof(struct hop_jumbo_hdr), | |
459 | tcp_hdrlen(skb)); | |
460 | /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */ | |
461 | } else if (skb_vlan_tag_present(skb)) { | |
462 | mlx5e_insert_vlan(start, skb, ihs); | |
463 | ihs += VLAN_HLEN; | |
05909bab | 464 | stats->added_vlan_packets++; |
77bdf895 | 465 | } else { |
de78960e ED |
466 | unsafe_memcpy(eseg->inline_hdr.start, skb->data, |
467 | attr->ihs, | |
468 | MLX5_UNSAFE_MEMCPY_DISCLAIMER); | |
77bdf895 | 469 | } |
de78960e | 470 | eseg->inline_hdr.sz |= cpu_to_be16(ihs); |
8e4b53f6 | 471 | dseg += wqe_attr->ds_cnt_inl; |
77bdf895 SM |
472 | } else if (skb_vlan_tag_present(skb)) { |
473 | eseg->insert.type = cpu_to_be16(MLX5_ETH_WQE_INSERT_VLAN); | |
4382c7b9 GP |
474 | if (skb->vlan_proto == cpu_to_be16(ETH_P_8021AD)) |
475 | eseg->insert.type |= cpu_to_be16(MLX5_ETH_WQE_SVLAN); | |
77bdf895 | 476 | eseg->insert.vlan_tci = cpu_to_be16(skb_vlan_tag_get(skb)); |
05909bab | 477 | stats->added_vlan_packets++; |
77bdf895 SM |
478 | } |
479 | ||
5be01904 | 480 | dseg += wqe_attr->ds_cnt_ids; |
de78960e | 481 | num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr->ihs + attr->hopbyhop, |
8e4b53f6 | 482 | attr->headlen, dseg); |
77bdf895 | 483 | if (unlikely(num_dma < 0)) |
d9a96ec3 | 484 | goto err_drop; |
77bdf895 | 485 | |
8e4b53f6 | 486 | mlx5e_txwqe_complete(sq, skb, attr, wqe_attr, num_dma, wi, cseg, xmit_more); |
12be4b21 | 487 | |
3df711db | 488 | return; |
e586b3b0 | 489 | |
d9a96ec3 | 490 | err_drop: |
05909bab | 491 | stats->dropped++; |
e586b3b0 | 492 | dev_kfree_skb_any(skb); |
5b759bf2 | 493 | mlx5e_tx_flush(sq); |
e586b3b0 AV |
494 | } |
495 | ||
5af75c74 MM |
496 | static bool mlx5e_tx_skb_supports_mpwqe(struct sk_buff *skb, struct mlx5e_tx_attr *attr) |
497 | { | |
5be01904 | 498 | return !skb_is_nonlinear(skb) && !skb_vlan_tag_present(skb) && !attr->ihs && |
9515978e | 499 | !attr->insz && !mlx5e_macsec_skb_is_offload(skb); |
5af75c74 MM |
500 | } |
501 | ||
502 | static bool mlx5e_tx_mpwqe_same_eseg(struct mlx5e_txqsq *sq, struct mlx5_wqe_eth_seg *eseg) | |
503 | { | |
504 | struct mlx5e_tx_mpwqe *session = &sq->mpwqe; | |
505 | ||
506 | /* Assumes the session is already running and has at least one packet. */ | |
507 | return !memcmp(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN); | |
508 | } | |
509 | ||
510 | static void mlx5e_tx_mpwqe_session_start(struct mlx5e_txqsq *sq, | |
511 | struct mlx5_wqe_eth_seg *eseg) | |
512 | { | |
513 | struct mlx5e_tx_mpwqe *session = &sq->mpwqe; | |
514 | struct mlx5e_tx_wqe *wqe; | |
515 | u16 pi; | |
516 | ||
76c31e5f | 517 | pi = mlx5e_txqsq_get_next_pi(sq, sq->max_sq_mpw_wqebbs); |
5af75c74 | 518 | wqe = MLX5E_TX_FETCH_WQE(sq, pi); |
991b2654 | 519 | net_prefetchw(wqe->data); |
5af75c74 MM |
520 | |
521 | *session = (struct mlx5e_tx_mpwqe) { | |
522 | .wqe = wqe, | |
523 | .bytes_count = 0, | |
524 | .ds_count = MLX5E_TX_WQE_EMPTY_DS_COUNT, | |
525 | .pkt_count = 0, | |
526 | .inline_on = 0, | |
527 | }; | |
528 | ||
529 | memcpy(&session->wqe->eth, eseg, MLX5E_ACCEL_ESEG_LEN); | |
530 | ||
531 | sq->stats->mpwqe_blks++; | |
532 | } | |
533 | ||
534 | static bool mlx5e_tx_mpwqe_session_is_active(struct mlx5e_txqsq *sq) | |
535 | { | |
536 | return sq->mpwqe.wqe; | |
537 | } | |
538 | ||
539 | static void mlx5e_tx_mpwqe_add_dseg(struct mlx5e_txqsq *sq, struct mlx5e_xmit_data *txd) | |
540 | { | |
541 | struct mlx5e_tx_mpwqe *session = &sq->mpwqe; | |
542 | struct mlx5_wqe_data_seg *dseg; | |
543 | ||
544 | dseg = (struct mlx5_wqe_data_seg *)session->wqe + session->ds_count; | |
545 | ||
546 | session->pkt_count++; | |
547 | session->bytes_count += txd->len; | |
548 | ||
549 | dseg->addr = cpu_to_be64(txd->dma_addr); | |
550 | dseg->byte_count = cpu_to_be32(txd->len); | |
551 | dseg->lkey = sq->mkey_be; | |
552 | session->ds_count++; | |
553 | ||
554 | sq->stats->mpwqe_pkts++; | |
555 | } | |
556 | ||
557 | static struct mlx5_wqe_ctrl_seg *mlx5e_tx_mpwqe_session_complete(struct mlx5e_txqsq *sq) | |
558 | { | |
559 | struct mlx5e_tx_mpwqe *session = &sq->mpwqe; | |
560 | u8 ds_count = session->ds_count; | |
561 | struct mlx5_wqe_ctrl_seg *cseg; | |
562 | struct mlx5e_tx_wqe_info *wi; | |
563 | u16 pi; | |
564 | ||
565 | cseg = &session->wqe->ctrl; | |
566 | cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_ENHANCED_MPSW); | |
567 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_count); | |
568 | ||
569 | pi = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->pc); | |
570 | wi = &sq->db.wqe_info[pi]; | |
571 | *wi = (struct mlx5e_tx_wqe_info) { | |
572 | .skb = NULL, | |
573 | .num_bytes = session->bytes_count, | |
574 | .num_wqebbs = DIV_ROUND_UP(ds_count, MLX5_SEND_WQEBB_NUM_DS), | |
575 | .num_dma = session->pkt_count, | |
576 | .num_fifo_pkts = session->pkt_count, | |
577 | }; | |
578 | ||
579 | sq->pc += wi->num_wqebbs; | |
580 | ||
581 | session->wqe = NULL; | |
582 | ||
583 | mlx5e_tx_check_stop(sq); | |
584 | ||
585 | return cseg; | |
586 | } | |
587 | ||
588 | static void | |
589 | mlx5e_sq_xmit_mpwqe(struct mlx5e_txqsq *sq, struct sk_buff *skb, | |
590 | struct mlx5_wqe_eth_seg *eseg, bool xmit_more) | |
591 | { | |
592 | struct mlx5_wqe_ctrl_seg *cseg; | |
593 | struct mlx5e_xmit_data txd; | |
594 | ||
5b759bf2 MM |
595 | txd.data = skb->data; |
596 | txd.len = skb->len; | |
597 | ||
598 | txd.dma_addr = dma_map_single(sq->pdev, txd.data, txd.len, DMA_TO_DEVICE); | |
599 | if (unlikely(dma_mapping_error(sq->pdev, txd.dma_addr))) | |
600 | goto err_unmap; | |
601 | ||
5af75c74 MM |
602 | if (!mlx5e_tx_mpwqe_session_is_active(sq)) { |
603 | mlx5e_tx_mpwqe_session_start(sq, eseg); | |
604 | } else if (!mlx5e_tx_mpwqe_same_eseg(sq, eseg)) { | |
605 | mlx5e_tx_mpwqe_session_complete(sq); | |
606 | mlx5e_tx_mpwqe_session_start(sq, eseg); | |
607 | } | |
608 | ||
609 | sq->stats->xmit_more += xmit_more; | |
610 | ||
5af75c74 | 611 | mlx5e_dma_push(sq, txd.dma_addr, txd.len, MLX5E_DMA_MAP_SINGLE); |
0b676aae | 612 | mlx5e_skb_fifo_push(&sq->db.skb_fifo, skb); |
5af75c74 | 613 | mlx5e_tx_mpwqe_add_dseg(sq, &txd); |
5af75c74 MM |
614 | mlx5e_tx_skb_update_hwts_flags(skb); |
615 | ||
76c31e5f | 616 | if (unlikely(mlx5e_tx_mpwqe_is_full(&sq->mpwqe, sq->max_sq_mpw_wqebbs))) { |
5af75c74 MM |
617 | /* Might stop the queue and affect the retval of __netdev_tx_sent_queue. */ |
618 | cseg = mlx5e_tx_mpwqe_session_complete(sq); | |
619 | ||
620 | if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more)) | |
621 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg); | |
622 | } else if (__netdev_tx_sent_queue(sq->txq, txd.len, xmit_more)) { | |
623 | /* Might stop the queue, but we were asked to ring the doorbell anyway. */ | |
624 | cseg = mlx5e_tx_mpwqe_session_complete(sq); | |
625 | ||
626 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, cseg); | |
627 | } | |
628 | ||
629 | return; | |
630 | ||
631 | err_unmap: | |
632 | mlx5e_dma_unmap_wqe_err(sq, 1); | |
633 | sq->stats->dropped++; | |
634 | dev_kfree_skb_any(skb); | |
5b759bf2 | 635 | mlx5e_tx_flush(sq); |
5af75c74 MM |
636 | } |
637 | ||
638 | void mlx5e_tx_mpwqe_ensure_complete(struct mlx5e_txqsq *sq) | |
639 | { | |
640 | /* Unlikely in non-MPWQE workloads; not important in MPWQE workloads. */ | |
641 | if (unlikely(mlx5e_tx_mpwqe_session_is_active(sq))) | |
642 | mlx5e_tx_mpwqe_session_complete(sq); | |
643 | } | |
644 | ||
58a51894 AL |
645 | static void mlx5e_cqe_ts_id_eseg(struct mlx5e_ptpsq *ptpsq, struct sk_buff *skb, |
646 | struct mlx5_wqe_eth_seg *eseg) | |
647 | { | |
648 | if (ptpsq->ts_cqe_ctr_mask && unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) | |
649 | eseg->flow_table_metadata = cpu_to_be32(ptpsq->skb_fifo_pc & | |
650 | ptpsq->ts_cqe_ctr_mask); | |
651 | } | |
652 | ||
f68406ca | 653 | static void mlx5e_txwqe_build_eseg(struct mlx5e_priv *priv, struct mlx5e_txqsq *sq, |
b336e6b2 | 654 | struct sk_buff *skb, struct mlx5e_accel_tx_state *accel, |
b544011f | 655 | struct mlx5_wqe_eth_seg *eseg, u16 ihs) |
5af75c74 | 656 | { |
f68406ca | 657 | mlx5e_accel_tx_eseg(priv, skb, eseg, ihs); |
b336e6b2 | 658 | mlx5e_txwqe_build_eseg_csum(sq, skb, accel, eseg); |
58a51894 AL |
659 | if (unlikely(sq->ptpsq)) |
660 | mlx5e_cqe_ts_id_eseg(sq->ptpsq, skb, eseg); | |
5af75c74 MM |
661 | } |
662 | ||
e586b3b0 AV |
663 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev) |
664 | { | |
665 | struct mlx5e_priv *priv = netdev_priv(dev); | |
714c88a3 | 666 | struct mlx5e_accel_tx_state accel = {}; |
8e4b53f6 MM |
667 | struct mlx5e_tx_wqe_attr wqe_attr; |
668 | struct mlx5e_tx_attr attr; | |
bf239741 IL |
669 | struct mlx5e_tx_wqe *wqe; |
670 | struct mlx5e_txqsq *sq; | |
671 | u16 pi; | |
2ac9cfe7 | 672 | |
17c84cb4 MM |
673 | /* All changes to txq2sq are performed in sync with mlx5e_xmit, when the |
674 | * queue being changed is disabled, and smp_wmb guarantees that the | |
675 | * changes are visible before mlx5e_xmit tries to read from txq2sq. It | |
676 | * guarantees that the value of txq2sq[qid] doesn't change while | |
677 | * mlx5e_xmit is running on queue number qid. smb_wmb is paired with | |
678 | * HARD_TX_LOCK around ndo_start_xmit, which serves as an ACQUIRE. | |
679 | */ | |
bf239741 | 680 | sq = priv->txq2sq[skb_get_queue_mapping(skb)]; |
214baf22 | 681 | if (unlikely(!sq)) { |
17c84cb4 MM |
682 | /* Two cases when sq can be NULL: |
683 | * 1. The HTB node is registered, and mlx5e_select_queue | |
684 | * selected its queue ID, but the SQ itself is not yet created. | |
685 | * 2. HTB SQ creation failed. Similar to the previous case, but | |
686 | * the SQ won't be created. | |
687 | */ | |
214baf22 MM |
688 | dev_kfree_skb_any(skb); |
689 | return NETDEV_TX_OK; | |
690 | } | |
714c88a3 MM |
691 | |
692 | /* May send SKBs and WQEs. */ | |
693 | if (unlikely(!mlx5e_accel_tx_begin(dev, sq, skb, &accel))) | |
5af75c74 | 694 | return NETDEV_TX_OK; |
714c88a3 | 695 | |
8e4b53f6 | 696 | mlx5e_sq_xmit_prepare(sq, skb, &accel, &attr); |
5af75c74 MM |
697 | |
698 | if (test_bit(MLX5E_SQ_STATE_MPWQE, &sq->state)) { | |
699 | if (mlx5e_tx_skb_supports_mpwqe(skb, &attr)) { | |
700 | struct mlx5_wqe_eth_seg eseg = {}; | |
701 | ||
f68406ca | 702 | mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &eseg, attr.ihs); |
5af75c74 MM |
703 | mlx5e_sq_xmit_mpwqe(sq, skb, &eseg, netdev_xmit_more()); |
704 | return NETDEV_TX_OK; | |
705 | } | |
706 | ||
707 | mlx5e_tx_mpwqe_ensure_complete(sq); | |
708 | } | |
709 | ||
8e4b53f6 MM |
710 | mlx5e_sq_calc_wqe_attr(skb, &attr, &wqe_attr); |
711 | pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs); | |
fed0c6cf | 712 | wqe = MLX5E_TX_FETCH_WQE(sq, pi); |
2ac9cfe7 | 713 | |
714c88a3 | 714 | /* May update the WQE, but may not post other WQEs. */ |
5be01904 RS |
715 | mlx5e_accel_tx_finish(sq, wqe, &accel, |
716 | (struct mlx5_wqe_inline_seg *)(wqe->data + wqe_attr.ds_cnt_inl)); | |
f68406ca | 717 | mlx5e_txwqe_build_eseg(priv, sq, skb, &accel, &wqe->eth, attr.ihs); |
8e4b53f6 | 718 | mlx5e_sq_xmit_wqe(sq, skb, &attr, &wqe_attr, wqe, pi, netdev_xmit_more()); |
689adf0d | 719 | |
3df711db | 720 | return NETDEV_TX_OK; |
e586b3b0 AV |
721 | } |
722 | ||
8e4b53f6 MM |
723 | static void mlx5e_tx_wi_dma_unmap(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi, |
724 | u32 *dma_fifo_cc) | |
725 | { | |
726 | int i; | |
727 | ||
728 | for (i = 0; i < wi->num_dma; i++) { | |
729 | struct mlx5e_sq_dma *dma = mlx5e_dma_get(sq, (*dma_fifo_cc)++); | |
730 | ||
731 | mlx5e_tx_dma_unmap(sq->pdev, dma); | |
732 | } | |
733 | } | |
734 | ||
735 | static void mlx5e_consume_skb(struct mlx5e_txqsq *sq, struct sk_buff *skb, | |
736 | struct mlx5_cqe64 *cqe, int napi_budget) | |
737 | { | |
738 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { | |
739 | struct skb_shared_hwtstamps hwts = {}; | |
740 | u64 ts = get_cqe_ts(cqe); | |
741 | ||
432119de | 742 | hwts.hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, ts); |
1880bc4e EBE |
743 | if (sq->ptpsq) |
744 | mlx5e_skb_cb_hwtstamp_handler(skb, MLX5E_SKB_CB_CQE_HWTSTAMP, | |
745 | hwts.hwtstamp, sq->ptpsq->cq_stats); | |
746 | else | |
747 | skb_tstamp_tx(skb, &hwts); | |
8e4b53f6 MM |
748 | } |
749 | ||
750 | napi_consume_skb(skb, napi_budget); | |
751 | } | |
752 | ||
338c46c6 MM |
753 | static void mlx5e_tx_wi_consume_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi, |
754 | struct mlx5_cqe64 *cqe, int napi_budget) | |
755 | { | |
756 | int i; | |
757 | ||
758 | for (i = 0; i < wi->num_fifo_pkts; i++) { | |
0b676aae | 759 | struct sk_buff *skb = mlx5e_skb_fifo_pop(&sq->db.skb_fifo); |
338c46c6 MM |
760 | |
761 | mlx5e_consume_skb(sq, skb, cqe, napi_budget); | |
762 | } | |
763 | } | |
764 | ||
8ec736e5 | 765 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget) |
e586b3b0 | 766 | { |
86155656 | 767 | struct mlx5e_sq_stats *stats; |
31391048 | 768 | struct mlx5e_txqsq *sq; |
4b7dfc99 | 769 | struct mlx5_cqe64 *cqe; |
e586b3b0 AV |
770 | u32 dma_fifo_cc; |
771 | u32 nbytes; | |
772 | u16 npkts; | |
773 | u16 sqcc; | |
774 | int i; | |
775 | ||
31391048 | 776 | sq = container_of(cq, struct mlx5e_txqsq, cq); |
e586b3b0 | 777 | |
0e5c04f6 | 778 | if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) |
29429f33 DJ |
779 | return false; |
780 | ||
4b7dfc99 TT |
781 | cqe = mlx5_cqwq_get_cqe(&cq->wq); |
782 | if (!cqe) | |
783 | return false; | |
784 | ||
86155656 TT |
785 | stats = sq->stats; |
786 | ||
e586b3b0 AV |
787 | npkts = 0; |
788 | nbytes = 0; | |
789 | ||
790 | /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), | |
791 | * otherwise a cq overrun may occur | |
792 | */ | |
793 | sqcc = sq->cc; | |
794 | ||
795 | /* avoid dirtying sq cache line every cqe */ | |
796 | dma_fifo_cc = sq->dma_fifo_cc; | |
797 | ||
4b7dfc99 TT |
798 | i = 0; |
799 | do { | |
b57e66ad | 800 | struct mlx5e_tx_wqe_info *wi; |
059ba072 AS |
801 | u16 wqe_counter; |
802 | bool last_wqe; | |
b57e66ad | 803 | u16 ci; |
e586b3b0 | 804 | |
a1f5a1a8 AS |
805 | mlx5_cqwq_pop(&cq->wq); |
806 | ||
059ba072 AS |
807 | wqe_counter = be16_to_cpu(cqe->wqe_counter); |
808 | ||
809 | do { | |
059ba072 AS |
810 | last_wqe = (sqcc == wqe_counter); |
811 | ||
ddf385e3 | 812 | ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc); |
31391048 | 813 | wi = &sq->db.wqe_info[ci]; |
e586b3b0 | 814 | |
8e4b53f6 MM |
815 | sqcc += wi->num_wqebbs; |
816 | ||
338c46c6 MM |
817 | if (likely(wi->skb)) { |
818 | mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc); | |
819 | mlx5e_consume_skb(sq, wi->skb, cqe, napi_budget); | |
820 | ||
821 | npkts++; | |
822 | nbytes += wi->num_bytes; | |
059ba072 AS |
823 | continue; |
824 | } | |
e586b3b0 | 825 | |
338c46c6 MM |
826 | if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi, |
827 | &dma_fifo_cc))) | |
828 | continue; | |
e586b3b0 | 829 | |
338c46c6 MM |
830 | if (wi->num_fifo_pkts) { |
831 | mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc); | |
832 | mlx5e_tx_wi_consume_fifo_skbs(sq, wi, cqe, napi_budget); | |
833 | ||
834 | npkts += wi->num_fifo_pkts; | |
835 | nbytes += wi->num_bytes; | |
836 | } | |
059ba072 | 837 | } while (!last_wqe); |
4b7dfc99 | 838 | |
b57e66ad TT |
839 | if (unlikely(get_cqe_opcode(cqe) == MLX5_CQE_REQ_ERR)) { |
840 | if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, | |
841 | &sq->state)) { | |
f1b95753 | 842 | mlx5e_dump_error_cqe(&sq->cq, sq->sqn, |
b57e66ad TT |
843 | (struct mlx5_err_cqe *)cqe); |
844 | mlx5_wq_cyc_wqe_dump(&sq->wq, ci, wi->num_wqebbs); | |
4d0b7ef9 | 845 | queue_work(cq->priv->wq, &sq->recover_work); |
b57e66ad TT |
846 | } |
847 | stats->cqe_err++; | |
848 | } | |
849 | ||
4b7dfc99 | 850 | } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); |
e586b3b0 | 851 | |
86155656 TT |
852 | stats->cqes += i; |
853 | ||
e586b3b0 AV |
854 | mlx5_cqwq_update_db_record(&cq->wq); |
855 | ||
856 | /* ensure cq space is freed before enabling more cqes */ | |
857 | wmb(); | |
858 | ||
859 | sq->dma_fifo_cc = dma_fifo_cc; | |
860 | sq->cc = sqcc; | |
861 | ||
862 | netdev_tx_completed_queue(sq->txq, npkts, nbytes); | |
863 | ||
864 | if (netif_tx_queue_stopped(sq->txq) && | |
01614d4f | 865 | mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, sq->stop_room) && |
19b43a43 | 866 | mlx5e_ptpsq_fifo_has_room(sq) && |
db75373c | 867 | !test_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state)) { |
6e8dd6d6 | 868 | netif_tx_wake_queue(sq->txq); |
86155656 | 869 | stats->wake++; |
e586b3b0 | 870 | } |
e586b3b0 | 871 | |
59a7c2fd | 872 | return (i == MLX5E_TX_CQ_POLL_BUDGET); |
e586b3b0 | 873 | } |
6e8dd6d6 | 874 | |
338c46c6 MM |
875 | static void mlx5e_tx_wi_kfree_fifo_skbs(struct mlx5e_txqsq *sq, struct mlx5e_tx_wqe_info *wi) |
876 | { | |
877 | int i; | |
878 | ||
879 | for (i = 0; i < wi->num_fifo_pkts; i++) | |
0b676aae | 880 | dev_kfree_skb_any(mlx5e_skb_fifo_pop(&sq->db.skb_fifo)); |
338c46c6 MM |
881 | } |
882 | ||
31391048 | 883 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq) |
6e8dd6d6 SM |
884 | { |
885 | struct mlx5e_tx_wqe_info *wi; | |
5e911e2c MS |
886 | u32 dma_fifo_cc, nbytes = 0; |
887 | u16 ci, sqcc, npkts = 0; | |
6e8dd6d6 | 888 | |
2c559361 TT |
889 | sqcc = sq->cc; |
890 | dma_fifo_cc = sq->dma_fifo_cc; | |
891 | ||
892 | while (sqcc != sq->pc) { | |
893 | ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc); | |
31391048 | 894 | wi = &sq->db.wqe_info[ci]; |
6e8dd6d6 | 895 | |
8e4b53f6 MM |
896 | sqcc += wi->num_wqebbs; |
897 | ||
338c46c6 MM |
898 | if (likely(wi->skb)) { |
899 | mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc); | |
900 | dev_kfree_skb_any(wi->skb); | |
901 | ||
902 | npkts++; | |
903 | nbytes += wi->num_bytes; | |
6e8dd6d6 SM |
904 | continue; |
905 | } | |
906 | ||
338c46c6 MM |
907 | if (unlikely(mlx5e_ktls_tx_try_handle_resync_dump_comp(sq, wi, &dma_fifo_cc))) |
908 | continue; | |
8e4b53f6 | 909 | |
338c46c6 MM |
910 | if (wi->num_fifo_pkts) { |
911 | mlx5e_tx_wi_dma_unmap(sq, wi, &dma_fifo_cc); | |
912 | mlx5e_tx_wi_kfree_fifo_skbs(sq, wi); | |
913 | ||
914 | npkts += wi->num_fifo_pkts; | |
915 | nbytes += wi->num_bytes; | |
916 | } | |
6e8dd6d6 | 917 | } |
2c559361 TT |
918 | |
919 | sq->dma_fifo_cc = dma_fifo_cc; | |
920 | sq->cc = sqcc; | |
5e911e2c MS |
921 | |
922 | netdev_tx_completed_queue(sq->txq, npkts, nbytes); | |
6e8dd6d6 | 923 | } |
25854544 SM |
924 | |
925 | #ifdef CONFIG_MLX5_CORE_IPOIB | |
25854544 SM |
926 | static inline void |
927 | mlx5i_txwqe_build_datagram(struct mlx5_av *av, u32 dqpn, u32 dqkey, | |
928 | struct mlx5_wqe_datagram_seg *dseg) | |
929 | { | |
930 | memcpy(&dseg->av, av, sizeof(struct mlx5_av)); | |
931 | dseg->av.dqp_dct = cpu_to_be32(dqpn | MLX5_EXTENDED_UD_AV); | |
932 | dseg->av.key.qkey.qkey = cpu_to_be32(dqkey); | |
933 | } | |
934 | ||
8e4b53f6 MM |
935 | static void mlx5i_sq_calc_wqe_attr(struct sk_buff *skb, |
936 | const struct mlx5e_tx_attr *attr, | |
937 | struct mlx5e_tx_wqe_attr *wqe_attr) | |
938 | { | |
939 | u16 ds_cnt = sizeof(struct mlx5i_tx_wqe) / MLX5_SEND_WQE_DS; | |
940 | u16 ds_cnt_inl = 0; | |
941 | ||
942 | ds_cnt += !!attr->headlen + skb_shinfo(skb)->nr_frags; | |
943 | ||
944 | if (attr->ihs) { | |
945 | u16 inl = attr->ihs - INL_HDR_START_SZ; | |
946 | ||
947 | ds_cnt_inl = DIV_ROUND_UP(inl, MLX5_SEND_WQE_DS); | |
948 | ds_cnt += ds_cnt_inl; | |
949 | } | |
950 | ||
951 | *wqe_attr = (struct mlx5e_tx_wqe_attr) { | |
952 | .ds_cnt = ds_cnt, | |
953 | .ds_cnt_inl = ds_cnt_inl, | |
954 | .num_wqebbs = DIV_ROUND_UP(ds_cnt, MLX5_SEND_WQEBB_NUM_DS), | |
955 | }; | |
956 | } | |
957 | ||
3df711db MM |
958 | void mlx5i_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
959 | struct mlx5_av *av, u32 dqpn, u32 dqkey, bool xmit_more) | |
25854544 | 960 | { |
8e4b53f6 MM |
961 | struct mlx5e_tx_wqe_attr wqe_attr; |
962 | struct mlx5e_tx_attr attr; | |
043dc78e | 963 | struct mlx5i_tx_wqe *wqe; |
25854544 | 964 | |
043dc78e TT |
965 | struct mlx5_wqe_datagram_seg *datagram; |
966 | struct mlx5_wqe_ctrl_seg *cseg; | |
967 | struct mlx5_wqe_eth_seg *eseg; | |
968 | struct mlx5_wqe_data_seg *dseg; | |
969 | struct mlx5e_tx_wqe_info *wi; | |
25854544 | 970 | |
05909bab | 971 | struct mlx5e_sq_stats *stats = sq->stats; |
25854544 | 972 | int num_dma; |
8e4b53f6 | 973 | u16 pi; |
25854544 | 974 | |
8e4b53f6 MM |
975 | mlx5e_sq_xmit_prepare(sq, skb, NULL, &attr); |
976 | mlx5i_sq_calc_wqe_attr(skb, &attr, &wqe_attr); | |
b431302e | 977 | |
8e4b53f6 MM |
978 | pi = mlx5e_txqsq_get_next_pi(sq, wqe_attr.num_wqebbs); |
979 | wqe = MLX5I_SQ_FETCH_WQE(sq, pi); | |
25854544 | 980 | |
299a1195 | 981 | stats->xmit_more += xmit_more; |
4ec5cf78 | 982 | |
043dc78e TT |
983 | /* fill wqe */ |
984 | wi = &sq->db.wqe_info[pi]; | |
985 | cseg = &wqe->ctrl; | |
986 | datagram = &wqe->datagram; | |
987 | eseg = &wqe->eth; | |
988 | dseg = wqe->data; | |
989 | ||
990 | mlx5i_txwqe_build_datagram(av, dqpn, dqkey, datagram); | |
991 | ||
b336e6b2 | 992 | mlx5e_txwqe_build_eseg_csum(sq, skb, NULL, eseg); |
043dc78e | 993 | |
8e4b53f6 | 994 | eseg->mss = attr.mss; |
043dc78e | 995 | |
8e4b53f6 | 996 | if (attr.ihs) { |
de78960e ED |
997 | if (unlikely(attr.hopbyhop)) { |
998 | struct ipv6hdr *h6; | |
999 | ||
1000 | /* remove the HBH header. | |
1001 | * Layout: [Ethernet header][IPv6 header][HBH][TCP header] | |
1002 | */ | |
1003 | unsafe_memcpy(eseg->inline_hdr.start, skb->data, | |
1004 | ETH_HLEN + sizeof(*h6), | |
1005 | MLX5_UNSAFE_MEMCPY_DISCLAIMER); | |
1006 | h6 = (struct ipv6hdr *)((char *)eseg->inline_hdr.start + ETH_HLEN); | |
1007 | h6->nexthdr = IPPROTO_TCP; | |
1008 | /* Copy the TCP header after the IPv6 one */ | |
1009 | unsafe_memcpy(h6 + 1, | |
1010 | skb->data + ETH_HLEN + sizeof(*h6) + | |
1011 | sizeof(struct hop_jumbo_hdr), | |
1012 | tcp_hdrlen(skb), | |
1013 | MLX5_UNSAFE_MEMCPY_DISCLAIMER); | |
1014 | /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */ | |
1015 | } else { | |
1016 | unsafe_memcpy(eseg->inline_hdr.start, skb->data, | |
1017 | attr.ihs, | |
1018 | MLX5_UNSAFE_MEMCPY_DISCLAIMER); | |
1019 | } | |
8e4b53f6 MM |
1020 | eseg->inline_hdr.sz = cpu_to_be16(attr.ihs); |
1021 | dseg += wqe_attr.ds_cnt_inl; | |
25854544 SM |
1022 | } |
1023 | ||
de78960e | 1024 | num_dma = mlx5e_txwqe_build_dsegs(sq, skb, skb->data + attr.ihs + attr.hopbyhop, |
8e4b53f6 | 1025 | attr.headlen, dseg); |
25854544 | 1026 | if (unlikely(num_dma < 0)) |
d9a96ec3 | 1027 | goto err_drop; |
25854544 | 1028 | |
8e4b53f6 | 1029 | mlx5e_txwqe_complete(sq, skb, &attr, &wqe_attr, num_dma, wi, cseg, xmit_more); |
25854544 | 1030 | |
3df711db | 1031 | return; |
25854544 | 1032 | |
d9a96ec3 | 1033 | err_drop: |
05909bab | 1034 | stats->dropped++; |
25854544 | 1035 | dev_kfree_skb_any(skb); |
5b759bf2 | 1036 | mlx5e_tx_flush(sq); |
25854544 | 1037 | } |
25854544 | 1038 | #endif |