[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.h

/*
 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef __MLX5_EN_TC_H__
#define __MLX5_EN_TC_H__

#include <net/pkt_cls.h>
#include "en.h"
#include "eswitch.h"
#include "en/tc_ct.h"
#include "en/tc_tun.h"
#include "en/tc/int_port.h"
#include "en/tc/meter.h"
#include "en_rep.h"

#define MLX5E_TC_FLOW_ID_MASK 0x0000ffff

#ifdef CONFIG_MLX5_ESWITCH

#define NIC_FLOW_ATTR_SZ (sizeof(struct mlx5_flow_attr) +\
			  sizeof(struct mlx5_nic_flow_attr))
#define ESW_FLOW_ATTR_SZ (sizeof(struct mlx5_flow_attr) +\
			  sizeof(struct mlx5_esw_flow_attr))
#define ns_to_attr_sz(ns) (((ns) == MLX5_FLOW_NAMESPACE_FDB) ?\
			    ESW_FLOW_ATTR_SZ :\
			    NIC_FLOW_ATTR_SZ)

struct mlx5_fs_chains *mlx5e_nic_chains(struct mlx5e_tc_table *tc);
int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags);

struct mlx5e_tc_update_priv {
	struct net_device *fwd_dev;
	bool skb_done;
	bool forward_tx;
};

struct mlx5_nic_flow_attr {
	u32 flow_tag;
	u32 hairpin_tirn;
	struct mlx5_flow_table *hairpin_ft;
};

struct mlx5_flow_attr {
	u32 action;
	unsigned long tc_act_cookies[TCA_ACT_MAX_PRIO];
	struct mlx5_fc *counter;
	struct mlx5_modify_hdr *modify_hdr;
	struct mlx5e_mod_hdr_handle *mh; /* attached mod header instance */
	struct mlx5e_mod_hdr_handle *slow_mh; /* attached mod header instance for slow path */
	struct mlx5_ct_attr ct_attr;
	struct mlx5e_sample_attr sample_attr;
	struct mlx5e_meter_attr meter_attr;
	struct mlx5e_tc_flow_parse_attr *parse_attr;
	u32 chain;
	u16 prio;
	u16 tc_act_cookies_count;
	u32 dest_chain;
	struct mlx5_flow_table *ft;
	struct mlx5_flow_table *dest_ft;
	u8 inner_match_level;
	u8 outer_match_level;
	u8 tun_ip_version;
	int tunnel_id; /* mapped tunnel id */
	u32 flags;
	u32 exe_aso_type;
	struct list_head list;
	struct mlx5e_post_act_handle *post_act_handle;
	struct mlx5_flow_attr *branch_true;
	struct mlx5_flow_attr *branch_false;
	struct mlx5_flow_attr *jumping_attr;
	struct mlx5_flow_handle *act_id_restore_rule;
	/* keep this union last */
	union {
		DECLARE_FLEX_ARRAY(struct mlx5_esw_flow_attr, esw_attr);
		DECLARE_FLEX_ARRAY(struct mlx5_nic_flow_attr, nic_attr);
	};
};

enum {
	MLX5_ATTR_FLAG_VLAN_HANDLED  = BIT(0),
	MLX5_ATTR_FLAG_SLOW_PATH     = BIT(1),
	MLX5_ATTR_FLAG_NO_IN_PORT    = BIT(2),
	MLX5_ATTR_FLAG_SRC_REWRITE   = BIT(3),
	MLX5_ATTR_FLAG_SAMPLE        = BIT(4),
	MLX5_ATTR_FLAG_ACCEPT        = BIT(5),
	MLX5_ATTR_FLAG_CT            = BIT(6),
	MLX5_ATTR_FLAG_TERMINATING   = BIT(7),
	MLX5_ATTR_FLAG_MTU           = BIT(8),
};

/* Returns true if any of the flags that require skipping further TC/NF processing are set. */
static inline bool
mlx5e_tc_attr_flags_skip(u32 attr_flags)
{
	return attr_flags & (MLX5_ATTR_FLAG_SLOW_PATH | MLX5_ATTR_FLAG_ACCEPT);
}

struct mlx5_rx_tun_attr {
	u16 decap_vport;
	union {
		__be32 v4;
		struct in6_addr v6;
	} src_ip; /* Valid if decap_vport is not zero */
	union {
		__be32 v4;
		struct in6_addr v6;
	} dst_ip; /* Valid if decap_vport is not zero */
};

#define MLX5E_TC_TABLE_CHAIN_TAG_BITS 16
#define MLX5E_TC_TABLE_CHAIN_TAG_MASK GENMASK(MLX5E_TC_TABLE_CHAIN_TAG_BITS - 1, 0)

#define MLX5E_TC_MAX_INT_PORT_NUM (8)

#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)

struct tunnel_match_key {
	struct flow_dissector_key_control enc_control;
	struct flow_dissector_key_keyid enc_key_id;
	struct flow_dissector_key_ports enc_tp;
	struct flow_dissector_key_ip enc_ip;
	union {
		struct flow_dissector_key_ipv4_addrs enc_ipv4;
		struct flow_dissector_key_ipv6_addrs enc_ipv6;
	};

	int filter_ifindex;
};

struct tunnel_match_enc_opts {
	struct flow_dissector_key_enc_opts key;
	struct flow_dissector_key_enc_opts mask;
};

/* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
 * Upper TUNNEL_INFO_BITS for general tunnel info.
 * Lower ENC_OPTS_BITS bits for enc_opts.
 */
#define TUNNEL_INFO_BITS 12
#define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
#define ENC_OPTS_BITS 11
#define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
#define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
#define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)

enum {
	MLX5E_TC_FLAG_INGRESS_BIT,
	MLX5E_TC_FLAG_EGRESS_BIT,
	MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
	MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
	MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
	MLX5E_TC_FLAG_LAST_EXPORTED_BIT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
};

#define MLX5_TC_FLAG(flag) BIT(MLX5E_TC_FLAG_##flag##_BIT)

int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv);
void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv);

int mlx5e_tc_ht_init(struct rhashtable *tc_ht);
void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht);

int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
			   struct flow_cls_offload *f, unsigned long flags);
int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
			struct flow_cls_offload *f, unsigned long flags);

int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
		       struct flow_cls_offload *f, unsigned long flags);
int mlx5e_tc_fill_action_stats(struct mlx5e_priv *priv,
			       struct flow_offload_action *fl_act);

int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
				struct tc_cls_matchall_offload *f);
int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
			     struct tc_cls_matchall_offload *f);

struct mlx5e_encap_entry;
void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
			      struct mlx5e_encap_entry *e,
			      struct list_head *flow_list);
void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
			      struct mlx5e_encap_entry *e,
			      struct list_head *flow_list);
bool mlx5e_encap_take(struct mlx5e_encap_entry *e);
void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e);

void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list);
void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list);

struct mlx5e_neigh_hash_entry;
struct mlx5e_encap_entry *
mlx5e_get_next_init_encap(struct mlx5e_neigh_hash_entry *nhe,
			  struct mlx5e_encap_entry *e);
void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe);

void mlx5e_tc_reoffload_flows_work(struct work_struct *work);

enum mlx5e_tc_attr_to_reg {
	MAPPED_OBJ_TO_REG,
	VPORT_TO_REG,
	TUNNEL_TO_REG,
	CTSTATE_TO_REG,
	ZONE_TO_REG,
	ZONE_RESTORE_TO_REG,
	MARK_TO_REG,
	LABELS_TO_REG,
	FTEID_TO_REG,
	NIC_MAPPED_OBJ_TO_REG,
	NIC_ZONE_RESTORE_TO_REG,
	PACKET_COLOR_TO_REG,
};

struct mlx5e_tc_attr_to_reg_mapping {
	int mfield; /* rewrite field */
	int moffset; /* bit offset of mfield */
	int mlen; /* bits to rewrite/match */

	int soffset; /* byte offset of spec for match */
};

extern struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[];

#define MLX5_REG_MAPPING_MOFFSET(reg_id) (mlx5e_tc_attr_to_reg_mappings[reg_id].moffset)
#define MLX5_REG_MAPPING_MBITS(reg_id) (mlx5e_tc_attr_to_reg_mappings[reg_id].mlen)
#define MLX5_REG_MAPPING_MASK(reg_id) (GENMASK(mlx5e_tc_attr_to_reg_mappings[reg_id].mlen - 1, 0))

bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
				    struct net_device *out_dev);

int mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
			      struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
			      enum mlx5_flow_namespace_type ns,
			      enum mlx5e_tc_attr_to_reg type,
			      u32 data);

void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
					  struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
					  enum mlx5e_tc_attr_to_reg type,
					  int act_id, u32 data);

void mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
				 enum mlx5e_tc_attr_to_reg type,
				 u32 data,
				 u32 mask);

void mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
				     enum mlx5e_tc_attr_to_reg type,
				     u32 *data,
				     u32 *mask);

int mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
					 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
					 enum mlx5_flow_namespace_type ns,
					 enum mlx5e_tc_attr_to_reg type,
					 u32 data);

int mlx5e_tc_attach_mod_hdr(struct mlx5e_priv *priv,
			    struct mlx5e_tc_flow *flow,
			    struct mlx5_flow_attr *attr);

void mlx5e_tc_detach_mod_hdr(struct mlx5e_priv *priv,
			     struct mlx5e_tc_flow *flow,
			     struct mlx5_flow_attr *attr);

void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
			    struct flow_match_basic *match, bool outer,
			    void *headers_c, void *headers_v);

int mlx5e_tc_nic_init(struct mlx5e_priv *priv);
void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv);

int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
			    void *cb_priv);

struct mlx5_flow_handle *
mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
			     struct mlx5_flow_spec *spec,
			     struct mlx5_flow_attr *attr);
void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
				  struct mlx5_flow_handle *rule,
				  struct mlx5_flow_attr *attr);

struct mlx5_flow_handle *
mlx5_tc_rule_insert(struct mlx5e_priv *priv,
		    struct mlx5_flow_spec *spec,
		    struct mlx5_flow_attr *attr);
void
mlx5_tc_rule_delete(struct mlx5e_priv *priv,
		    struct mlx5_flow_handle *rule,
		    struct mlx5_flow_attr *attr);

bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev);
int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev,
			       u16 *vport);

int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
				      struct mlx5_flow_attr *attr,
				      int ifindex,
				      enum mlx5e_tc_int_port_type type,
				      u32 *action,
				      int out_index);
#else /* CONFIG_MLX5_CLS_ACT */
static inline int  mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
static inline int mlx5e_tc_ht_init(struct rhashtable *tc_ht) { return 0; }
static inline void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht) {}
static inline int
mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
{ return -EOPNOTSUPP; }

#endif /* CONFIG_MLX5_CLS_ACT */

struct mlx5_flow_attr *mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type);

struct mlx5_flow_handle *
mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
			     struct mlx5_flow_spec *spec,
			     struct mlx5_flow_attr *attr);
void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
				  struct mlx5_flow_handle *rule,
				  struct mlx5_flow_attr *attr);

#else /* CONFIG_MLX5_ESWITCH */
static inline int  mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
static inline int  mlx5e_tc_num_filters(struct mlx5e_priv *priv,
					unsigned long flags)
{
	return 0;
}

static inline int
mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, void *cb_priv)
{ return -EOPNOTSUPP; }
#endif

#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
struct mlx5e_tc_table *mlx5e_tc_table_alloc(void);
void mlx5e_tc_table_free(struct mlx5e_tc_table *tc);
static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe)
{
	u32 chain, reg_b;

	reg_b = be32_to_cpu(cqe->ft_metadata);

	if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS))
		return false;

	chain = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
	if (chain)
		return true;

	return false;
}

bool mlx5e_tc_update_skb_nic(struct mlx5_cqe64 *cqe, struct sk_buff *skb);
bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb,
			 struct mapping_ctx *mapping_ctx, u32 mapped_obj_id,
			 struct mlx5_tc_ct_priv *ct_priv,
			 u32 zone_restore_id, u32 tunnel_id,
			 struct mlx5e_tc_update_priv *tc_priv);
#else /* CONFIG_MLX5_CLS_ACT */
static inline struct mlx5e_tc_table *mlx5e_tc_table_alloc(void) { return NULL; }
static inline void mlx5e_tc_table_free(struct mlx5e_tc_table *tc) {}
static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe)
{ return false; }
static inline bool
mlx5e_tc_update_skb_nic(struct mlx5_cqe64 *cqe, struct sk_buff *skb)
{ return true; }
#endif

int mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
				     u64 act_miss_cookie, u32 *act_miss_mapping);
void mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
				      u32 act_miss_mapping);

#endif /* __MLX5_EN_TC_H__ */
Commit	Line	Data
e8f887ac AV	1	/*
	2	* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef __MLX5_EN_TC_H__
	34	#define __MLX5_EN_TC_H__
	35
de4784ca	36	#include <net/pkt_cls.h>
768c3667	37	#include "en.h"
c620b772 AL	38	#include "eswitch.h"
c620b772 AL	39	#include "en/tc_ct.h"
0d9f9647	40	#include "en/tc_tun.h"
4f4edcc2	41	#include "en/tc/int_port.h"
74e6b2a8	42	#include "en/tc/meter.h"
0d9f9647	43	#include "en_rep.h"
de4784ca	44
12185a9f AV	45	#define MLX5E_TC_FLOW_ID_MASK 0x0000ffff
12185a9f AV	46
e80541ec	47	#ifdef CONFIG_MLX5_ESWITCH
60bd4af8	48
aedd133d AL	49	#define NIC_FLOW_ATTR_SZ (sizeof(struct mlx5_flow_attr) +\
aedd133d AL	50	sizeof(struct mlx5_nic_flow_attr))
c620b772 AL	51	#define ESW_FLOW_ATTR_SZ (sizeof(struct mlx5_flow_attr) +\
c620b772 AL	52	sizeof(struct mlx5_esw_flow_attr))
aedd133d AL	53	#define ns_to_attr_sz(ns) (((ns) == MLX5_FLOW_NAMESPACE_FDB) ?\
	54	ESW_FLOW_ATTR_SZ :\
	55	NIC_FLOW_ATTR_SZ)
	56
f52f2fae	57	struct mlx5_fs_chains mlx5e_nic_chains(struct mlx5e_tc_table tc);
185901ce VB	58	int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags);
	59
	60	struct mlx5e_tc_update_priv {
189ce08e	61	struct net_device *fwd_dev;
93a1ab2c PB	62	bool skb_done;
93a1ab2c PB	63	bool forward_tx;
185901ce VB	64	};
185901ce VB	65
c620b772 AL	66	struct mlx5_nic_flow_attr {
	67	u32 flow_tag;
	68	u32 hairpin_tirn;
	69	struct mlx5_flow_table *hairpin_ft;
	70	};
	71
	72	struct mlx5_flow_attr {
	73	u32 action;
cca7eac1	74	unsigned long tc_act_cookies[TCA_ACT_MAX_PRIO];
c620b772 AL	75	struct mlx5_fc *counter;
c620b772 AL	76	struct mlx5_modify_hdr *modify_hdr;
82b56480 RD	77	struct mlx5e_mod_hdr_handle mh; / attached mod header instance */
82b56480 RD	78	struct mlx5e_mod_hdr_handle slow_mh; / attached mod header instance for slow path */
c620b772	79	struct mlx5_ct_attr ct_attr;
eeed226e	80	struct mlx5e_sample_attr sample_attr;
a8d52b02	81	struct mlx5e_meter_attr meter_attr;
c620b772 AL	82	struct mlx5e_tc_flow_parse_attr *parse_attr;
	83	u32 chain;
	84	u16 prio;
cca7eac1	85	u16 tc_act_cookies_count;
c620b772 AL	86	u32 dest_chain;
	87	struct mlx5_flow_table *ft;
	88	struct mlx5_flow_table *dest_ft;
	89	u8 inner_match_level;
	90	u8 outer_match_level;
1e74152e	91	u8 tun_ip_version;
73a3f1bc	92	int tunnel_id; /* mapped tunnel id */
c620b772	93	u32 flags;
a8d52b02	94	u32 exe_aso_type;
8300f225 RD	95	struct list_head list;
8300f225 RD	96	struct mlx5e_post_act_handle *post_act_handle;
f86488cb OS	97	struct mlx5_flow_attr *branch_true;
f86488cb OS	98	struct mlx5_flow_attr *branch_false;
c84fa1ab	99	struct mlx5_flow_attr *jumping_attr;
67027828	100	struct mlx5_flow_handle *act_id_restore_rule;
94db3317	101	/* keep this union last */
c620b772	102	union {
5df5365a GS	103	DECLARE_FLEX_ARRAY(struct mlx5_esw_flow_attr, esw_attr);
5df5365a GS	104	DECLARE_FLEX_ARRAY(struct mlx5_nic_flow_attr, nic_attr);
c620b772 AL	105	};
	106	};
	107
e5d4e1da RD	108	enum {
	109	MLX5_ATTR_FLAG_VLAN_HANDLED = BIT(0),
	110	MLX5_ATTR_FLAG_SLOW_PATH = BIT(1),
	111	MLX5_ATTR_FLAG_NO_IN_PORT = BIT(2),
	112	MLX5_ATTR_FLAG_SRC_REWRITE = BIT(3),
	113	MLX5_ATTR_FLAG_SAMPLE = BIT(4),
	114	MLX5_ATTR_FLAG_ACCEPT = BIT(5),
84ba8062	115	MLX5_ATTR_FLAG_CT = BIT(6),
c84fa1ab	116	MLX5_ATTR_FLAG_TERMINATING = BIT(7),
6fda078d	117	MLX5_ATTR_FLAG_MTU = BIT(8),
e5d4e1da RD	118	};
	119
	120	/* Returns true if any of the flags that require skipping further TC/NF processing are set. */
	121	static inline bool
	122	mlx5e_tc_attr_flags_skip(u32 attr_flags)
	123	{
	124	return attr_flags & (MLX5_ATTR_FLAG_SLOW_PATH \| MLX5_ATTR_FLAG_ACCEPT);
	125	}
	126
34ca6535 VB	127	struct mlx5_rx_tun_attr {
	128	u16 decap_vport;
	129	union {
	130	__be32 v4;
	131	struct in6_addr v6;
	132	} src_ip; /* Valid if decap_vport is not zero */
	133	union {
	134	__be32 v4;
	135	struct in6_addr v6;
	136	} dst_ip; /* Valid if decap_vport is not zero */
34ca6535 VB	137	};
34ca6535 VB	138
c7569097 AL	139	#define MLX5E_TC_TABLE_CHAIN_TAG_BITS 16
	140	#define MLX5E_TC_TABLE_CHAIN_TAG_MASK GENMASK(MLX5E_TC_TABLE_CHAIN_TAG_BITS - 1, 0)
	141
4f4edcc2 AL	142	#define MLX5E_TC_MAX_INT_PORT_NUM (8)
4f4edcc2 AL	143
185901ce VB	144	#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
185901ce VB	145
768c3667 VB	146	struct tunnel_match_key {
	147	struct flow_dissector_key_control enc_control;
	148	struct flow_dissector_key_keyid enc_key_id;
	149	struct flow_dissector_key_ports enc_tp;
	150	struct flow_dissector_key_ip enc_ip;
	151	union {
	152	struct flow_dissector_key_ipv4_addrs enc_ipv4;
	153	struct flow_dissector_key_ipv6_addrs enc_ipv6;
	154	};
	155
	156	int filter_ifindex;
	157	};
	158
	159	struct tunnel_match_enc_opts {
	160	struct flow_dissector_key_enc_opts key;
	161	struct flow_dissector_key_enc_opts mask;
	162	};
	163
	164	/* Tunnel_id mapping is TUNNEL_INFO_BITS + ENC_OPTS_BITS.
	165	* Upper TUNNEL_INFO_BITS for general tunnel info.
	166	* Lower ENC_OPTS_BITS bits for enc_opts.
	167	*/
d12f4521	168	#define TUNNEL_INFO_BITS 12
768c3667	169	#define TUNNEL_INFO_BITS_MASK GENMASK(TUNNEL_INFO_BITS - 1, 0)
b973cf32	170	#define ENC_OPTS_BITS 11
768c3667 VB	171	#define ENC_OPTS_BITS_MASK GENMASK(ENC_OPTS_BITS - 1, 0)
	172	#define TUNNEL_ID_BITS (TUNNEL_INFO_BITS + ENC_OPTS_BITS)
	173	#define TUNNEL_ID_MASK GENMASK(TUNNEL_ID_BITS - 1, 0)
	174
60bd4af8	175	enum {
226f2ca3 VB	176	MLX5E_TC_FLAG_INGRESS_BIT,
	177	MLX5E_TC_FLAG_EGRESS_BIT,
	178	MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
	179	MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 PB	180	MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
84179981 PB	181	MLX5E_TC_FLAG_LAST_EXPORTED_BIT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
60bd4af8 OG	182	};
60bd4af8 OG	183
226f2ca3 VB	184	#define MLX5_TC_FLAG(flag) BIT(MLX5E_TC_FLAG_##flag##_BIT)
226f2ca3 VB	185
d1a3138f PB	186	int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv);
	187	void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv);
	188
	189	int mlx5e_tc_ht_init(struct rhashtable *tc_ht);
	190	void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht);
e8f887ac	191
71d82d2a	192	int mlx5e_configure_flower(struct net_device dev, struct mlx5e_priv priv,
226f2ca3	193	struct flow_cls_offload *f, unsigned long flags);
71d82d2a	194	int mlx5e_delete_flower(struct net_device dev, struct mlx5e_priv priv,
226f2ca3	195	struct flow_cls_offload *f, unsigned long flags);
e3a2b7ed	196
71d82d2a	197	int mlx5e_stats_flower(struct net_device dev, struct mlx5e_priv priv,
226f2ca3	198	struct flow_cls_offload *f, unsigned long flags);
2b68d659 OS	199	int mlx5e_tc_fill_action_stats(struct mlx5e_priv *priv,
2b68d659 OS	200	struct flow_offload_action *fl_act);
aad7e08d	201
fcb64c0f EC	202	int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
	203	struct tc_cls_matchall_offload *f);
	204	int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
	205	struct tc_cls_matchall_offload *f);
fcb64c0f	206
232c0013 HHZ	207	struct mlx5e_encap_entry;
232c0013 HHZ	208	void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768 VB	209	struct mlx5e_encap_entry *e,
2a1f1768 VB	210	struct list_head *flow_list);
232c0013	211	void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768 VB	212	struct mlx5e_encap_entry *e,
2a1f1768 VB	213	struct list_head *flow_list);
948993f2 VB	214	bool mlx5e_encap_take(struct mlx5e_encap_entry *e);
948993f2 VB	215	void mlx5e_encap_put(struct mlx5e_priv priv, struct mlx5e_encap_entry e);
232c0013	216
2a1f1768	217	void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry e, struct list_head flow_list);
021905f8	218	void mlx5e_put_flow_list(struct mlx5e_priv priv, struct list_head flow_list);
2a1f1768	219
f6dfb4c3	220	struct mlx5e_neigh_hash_entry;
fb1a3132 VB	221	struct mlx5e_encap_entry *
	222	mlx5e_get_next_init_encap(struct mlx5e_neigh_hash_entry *nhe,
	223	struct mlx5e_encap_entry *e);
f6dfb4c3 HHZ	224	void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe);
f6dfb4c3 HHZ	225
b4a23329	226	void mlx5e_tc_reoffload_flows_work(struct work_struct *work);
f5bc2c5d	227
8f1e0b97	228	enum mlx5e_tc_attr_to_reg {
235ff07d	229	MAPPED_OBJ_TO_REG,
10742efc	230	VPORT_TO_REG,
0a7fcb78	231	TUNNEL_TO_REG,
4c3844d9 PB	232	CTSTATE_TO_REG,
4c3844d9 PB	233	ZONE_TO_REG,
a8eb919b	234	ZONE_RESTORE_TO_REG,
4c3844d9 PB	235	MARK_TO_REG,
	236	LABELS_TO_REG,
	237	FTEID_TO_REG,
235ff07d	238	NIC_MAPPED_OBJ_TO_REG,
aedd133d	239	NIC_ZONE_RESTORE_TO_REG,
06fe52a4	240	PACKET_COLOR_TO_REG,
8f1e0b97 PB	241	};
	242
	243	struct mlx5e_tc_attr_to_reg_mapping {
	244	int mfield; /* rewrite field */
ed2fe7ba PB	245	int moffset; /* bit offset of mfield */
ed2fe7ba PB	246	int mlen; /* bits to rewrite/match */
0a7fcb78	247
ed2fe7ba	248	int soffset; /* byte offset of spec for match */
8f1e0b97 PB	249	};
	250
	251	extern struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[];
	252
17c5da03 JL	253	#define MLX5_REG_MAPPING_MOFFSET(reg_id) (mlx5e_tc_attr_to_reg_mappings[reg_id].moffset)
	254	#define MLX5_REG_MAPPING_MBITS(reg_id) (mlx5e_tc_attr_to_reg_mappings[reg_id].mlen)
	255	#define MLX5_REG_MAPPING_MASK(reg_id) (GENMASK(mlx5e_tc_attr_to_reg_mappings[reg_id].mlen - 1, 0))
	256
f6dc1264 PB	257	bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
	258	struct net_device *out_dev);
	259
0a7fcb78 PB	260	int mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
0a7fcb78 PB	261	struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
aedd133d	262	enum mlx5_flow_namespace_type ns,
0a7fcb78 PB	263	enum mlx5e_tc_attr_to_reg type,
	264	u32 data);
	265
c7b9038d VB	266	void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
	267	struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
	268	enum mlx5e_tc_attr_to_reg type,
	269	int act_id, u32 data);
	270
0a7fcb78 PB	271	void mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
	272	enum mlx5e_tc_attr_to_reg type,
	273	u32 data,
	274	u32 mask);
	275
7e36feeb PB	276	void mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
	277	enum mlx5e_tc_attr_to_reg type,
	278	u32 *data,
	279	u32 *mask);
	280
c7b9038d VB	281	int mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
	282	struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
	283	enum mlx5_flow_namespace_type ns,
	284	enum mlx5e_tc_attr_to_reg type,
	285	u32 data);
	286
ef78b8d5 RD	287	int mlx5e_tc_attach_mod_hdr(struct mlx5e_priv *priv,
	288	struct mlx5e_tc_flow *flow,
	289	struct mlx5_flow_attr *attr);
	290
	291	void mlx5e_tc_detach_mod_hdr(struct mlx5e_priv *priv,
	292	struct mlx5e_tc_flow *flow,
	293	struct mlx5_flow_attr *attr);
c7b9038d	294
fca53304 EB	295	void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
	296	struct flow_match_basic *match, bool outer,
	297	void headers_c, void headers_v);
4a5d5d73	298
d956873f VB	299	int mlx5e_tc_nic_init(struct mlx5e_priv *priv);
	300	void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv);
	301
e2394a61 VB	302	int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
	303	void *cb_priv);
	304
08247066 AL	305	struct mlx5_flow_handle *
	306	mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
	307	struct mlx5_flow_spec *spec,
c620b772	308	struct mlx5_flow_attr *attr);
08247066	309	void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097 AL	310	struct mlx5_flow_handle *rule,
	311	struct mlx5_flow_attr *attr);
	312
aedd133d AL	313	struct mlx5_flow_handle *
	314	mlx5_tc_rule_insert(struct mlx5e_priv *priv,
	315	struct mlx5_flow_spec *spec,
	316	struct mlx5_flow_attr *attr);
	317	void
	318	mlx5_tc_rule_delete(struct mlx5e_priv *priv,
	319	struct mlx5_flow_handle *rule,
	320	struct mlx5_flow_attr *attr);
	321
a508728a VB	322	bool mlx5e_tc_is_vf_tunnel(struct net_device out_dev, struct net_device route_dev);
	323	int mlx5e_tc_query_route_vport(struct net_device out_dev, struct net_device route_dev,
	324	u16 *vport);
	325
27484f71 AL	326	int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
	327	struct mlx5_flow_attr *attr,
	328	int ifindex,
	329	enum mlx5e_tc_int_port_type type,
	330	u32 *action,
	331	int out_index);
d956873f VB	332	#else /* CONFIG_MLX5_CLS_ACT */
	333	static inline int mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
	334	static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
d1a3138f PB	335	static inline int mlx5e_tc_ht_init(struct rhashtable *tc_ht) { return 0; }
d1a3138f PB	336	static inline void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht) {}
d956873f VB	337	static inline int
	338	mlx5e_setup_tc_block_cb(enum tc_setup_type type, void type_data, void cb_priv)
	339	{ return -EOPNOTSUPP; }
c7569097	340
d956873f VB	341	#endif /* CONFIG_MLX5_CLS_ACT */
d956873f VB	342
c620b772 AL	343	struct mlx5_flow_attr *mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type);
c620b772 AL	344
aedd133d AL	345	struct mlx5_flow_handle *
	346	mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
	347	struct mlx5_flow_spec *spec,
	348	struct mlx5_flow_attr *attr);
	349	void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
	350	struct mlx5_flow_handle *rule,
	351	struct mlx5_flow_attr *attr);
	352
e80541ec	353	#else /* CONFIG_MLX5_ESWITCH */
655dc3d2 OG	354	static inline int mlx5e_tc_nic_init(struct mlx5e_priv *priv) { return 0; }
655dc3d2 OG	355	static inline void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) {}
226f2ca3 VB	356	static inline int mlx5e_tc_num_filters(struct mlx5e_priv *priv,
	357	unsigned long flags)
	358	{
	359	return 0;
	360	}
e2394a61 VB	361
	362	static inline int
	363	mlx5e_setup_tc_block_cb(enum tc_setup_type type, void type_data, void cb_priv)
	364	{ return -EOPNOTSUPP; }
e80541ec SM	365	#endif
e80541ec SM	366
c7569097	367	#if IS_ENABLED(CONFIG_MLX5_CLS_ACT)
23bde065 LK	368	struct mlx5e_tc_table *mlx5e_tc_table_alloc(void);
23bde065 LK	369	void mlx5e_tc_table_free(struct mlx5e_tc_table *tc);
c7569097 AL	370	static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe)
c7569097 AL	371	{
c7569097 AL	372	u32 chain, reg_b;
	373
	374	reg_b = be32_to_cpu(cqe->ft_metadata);
	375
48d216e5	376	if (reg_b >> (MLX5E_TC_TABLE_CHAIN_TAG_BITS + ESW_ZONE_ID_BITS))
6248ce99 HN	377	return false;
6248ce99 HN	378
c7569097 AL	379	chain = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
	380	if (chain)
	381	return true;
c7569097 AL	382
	383	return false;
	384	}
	385
93a1ab2c PB	386	bool mlx5e_tc_update_skb_nic(struct mlx5_cqe64 cqe, struct sk_buff skb);
	387	bool mlx5e_tc_update_skb(struct mlx5_cqe64 cqe, struct sk_buff skb,
	388	struct mapping_ctx *mapping_ctx, u32 mapped_obj_id,
	389	struct mlx5_tc_ct_priv *ct_priv,
	390	u32 zone_restore_id, u32 tunnel_id,
	391	struct mlx5e_tc_update_priv *tc_priv);
c7569097	392	#else /* CONFIG_MLX5_CLS_ACT */
23bde065 LK	393	static inline struct mlx5e_tc_table *mlx5e_tc_table_alloc(void) { return NULL; }
23bde065 LK	394	static inline void mlx5e_tc_table_free(struct mlx5e_tc_table *tc) {}
c7569097 AL	395	static inline bool mlx5e_cqe_regb_chain(struct mlx5_cqe64 *cqe)
	396	{ return false; }
	397	static inline bool
93a1ab2c	398	mlx5e_tc_update_skb_nic(struct mlx5_cqe64 cqe, struct sk_buff skb)
c7569097 AL	399	{ return true; }
	400	#endif
	401
67027828 PB	402	int mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv priv, struct mlx5_flow_attr attr,
	403	u64 act_miss_cookie, u32 *act_miss_mapping);
	404	void mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv priv, struct mlx5_flow_attr attr,
	405	u32 act_miss_mapping);
	406
e8f887ac	407	#endif /* __MLX5_EN_TC_H__ */