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net/mlx5e: Extend mod header entry with reference counter
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
5a7e5bcb 41#include <linux/refcount.h>
db76ca24 42#include <linux/completion.h>
03a9d11e 43#include <net/tc_act/tc_mirred.h>
776b12b6 44#include <net/tc_act/tc_vlan.h>
bbd00f7e 45#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 46#include <net/tc_act/tc_pedit.h>
26c02749 47#include <net/tc_act/tc_csum.h>
f6dfb4c3 48#include <net/arp.h>
3616d08b 49#include <net/ipv6_stubs.h>
e8f887ac 50#include "en.h"
1d447a39 51#include "en_rep.h"
232c0013 52#include "en_tc.h"
03a9d11e 53#include "eswitch.h"
3f6d08d1 54#include "fs_core.h"
2c81bfd5 55#include "en/port.h"
101f4de9 56#include "en/tc_tun.h"
04de7dda 57#include "lib/devcom.h"
9272e3df 58#include "lib/geneve.h"
e8f887ac 59
3bc4b7bf
OG		 60struct mlx5_nic_flow_attr {
61 u32 action;
62 u32 flow_tag;
2f4fe4ca 63 u32 mod_hdr_id;
5c65c564 64 u32 hairpin_tirn;
38aa51c1 65 u8 match_level;
3f6d08d1 66 struct mlx5_flow_table *hairpin_ft;
b8aee822 67 struct mlx5_fc *counter;
3bc4b7bf
OG		 68};
69
226f2ca3 70#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 71
65ba8fb7 72enum {
226f2ca3
VB		 73 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
74 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
75 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
76 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
77 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
78 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
79 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
80 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
81 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
82 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 83 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
65ba8fb7
OG		 84};
85
e4ad91f2
CM		 86#define MLX5E_TC_MAX_SPLITS 1
87
79baaec7
EB		 88/* Helper struct for accessing a struct containing list_head array.
89 * Containing struct
90 * |- Helper array
91 * [0] Helper item 0
92 * |- list_head item 0
93 * |- index (0)
94 * [1] Helper item 1
95 * |- list_head item 1
96 * |- index (1)
97 * To access the containing struct from one of the list_head items:
98 * 1. Get the helper item from the list_head item using
99 * helper item =
100 * container_of(list_head item, helper struct type, list_head field)
101 * 2. Get the contining struct from the helper item and its index in the array:
102 * containing struct =
103 * container_of(helper item, containing struct type, helper field[index])
104 */
105struct encap_flow_item {
106 struct list_head list;
107 int index;
108};
109
e8f887ac
AV		 110struct mlx5e_tc_flow {
111 struct rhash_head node;
655dc3d2 112 struct mlx5e_priv *priv;
e8f887ac 113 u64 cookie;
226f2ca3 114 unsigned long flags;
e4ad91f2 115 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 116 /* Flow can be associated with multiple encap IDs.
117 * The number of encaps is bounded by the number of supported
118 * destinations.
119 */
120 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 121 struct mlx5e_tc_flow *peer_flow;
dd58edc3 122 struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */
11c9c548 123 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
e4f9abbd 124 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 125 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 126 struct list_head peer; /* flows with peer flow */
b4a23329 127 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
5a7e5bcb 128 refcount_t refcnt;
c5d326b2 129 struct rcu_head rcu_head;
3bc4b7bf
OG		 130 union {
131 struct mlx5_esw_flow_attr esw_attr[0];
132 struct mlx5_nic_flow_attr nic_attr[0];
133 };
e8f887ac
AV		 134};
135
17091853 136struct mlx5e_tc_flow_parse_attr {
1f6da306 137 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 138 struct net_device *filter_dev;
17091853 139 struct mlx5_flow_spec spec;
d79b6df6 140 int num_mod_hdr_actions;
218d05ce 141 int max_mod_hdr_actions;
d79b6df6 142 void *mod_hdr_actions;
98b66cb1 143 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 144};
145
acff797c 146#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 147#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 148
77ab67b7
OG		 149struct mlx5e_hairpin {
150 struct mlx5_hairpin *pair;
151
152 struct mlx5_core_dev *func_mdev;
3f6d08d1 153 struct mlx5e_priv *func_priv;
77ab67b7
OG		 154 u32 tdn;
155 u32 tirn;
3f6d08d1
OG		 156
157 int num_channels;
158 struct mlx5e_rqt indir_rqt;
159 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
160 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 161};
162
5c65c564
OG		 163struct mlx5e_hairpin_entry {
164 /* a node of a hash table which keeps all the hairpin entries */
165 struct hlist_node hairpin_hlist;
166
73edca73
VB		 167 /* protects flows list */
168 spinlock_t flows_lock;
5c65c564
OG		 169 /* flows sharing the same hairpin */
170 struct list_head flows;
db76ca24
VB		 171 /* hpe's that were not fully initialized when dead peer update event
172 * function traversed them.
173 */
174 struct list_head dead_peer_wait_list;
5c65c564 175
d8822868 176 u16 peer_vhca_id;
106be53b 177 u8 prio;
5c65c564 178 struct mlx5e_hairpin *hp;
e4f9abbd 179 refcount_t refcnt;
db76ca24 180 struct completion res_ready;
5c65c564
OG		 181};
182
11c9c548
OG		 183struct mod_hdr_key {
184 int num_actions;
185 void *actions;
186};
187
188struct mlx5e_mod_hdr_entry {
189 /* a node of a hash table which keeps all the mod_hdr entries */
190 struct hlist_node mod_hdr_hlist;
191
192 /* flows sharing the same mod_hdr entry */
193 struct list_head flows;
194
195 struct mod_hdr_key key;
196
197 u32 mod_hdr_id;
dd58edc3
VB		 198
199 refcount_t refcnt;
11c9c548
OG		 200};
201
202#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
203
5a7e5bcb
VB		 204static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
205 struct mlx5e_tc_flow *flow);
206
207static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
208{
209 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
210 return ERR_PTR(-EINVAL);
211 return flow;
212}
213
214static void mlx5e_flow_put(struct mlx5e_priv *priv,
215 struct mlx5e_tc_flow *flow)
216{
217 if (refcount_dec_and_test(&flow->refcnt)) {
218 mlx5e_tc_del_flow(priv, flow);
c5d326b2 219 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 220 }
221}
222
226f2ca3
VB		 223static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
224{
225 /* Complete all memory stores before setting bit. */
226 smp_mb__before_atomic();
227 set_bit(flag, &flow->flags);
228}
229
230#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
231
c5d326b2
VB		 232static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
233 unsigned long flag)
234{
235 /* test_and_set_bit() provides all necessary barriers */
236 return test_and_set_bit(flag, &flow->flags);
237}
238
239#define flow_flag_test_and_set(flow, flag) \
240 __flow_flag_test_and_set(flow, \
241 MLX5E_TC_FLOW_FLAG_##flag)
242
226f2ca3
VB		 243static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
244{
245 /* Complete all memory stores before clearing bit. */
246 smp_mb__before_atomic();
247 clear_bit(flag, &flow->flags);
248}
249
250#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
251 MLX5E_TC_FLOW_FLAG_##flag)
252
253static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
254{
255 bool ret = test_bit(flag, &flow->flags);
256
257 /* Read fields of flow structure only after checking flags. */
258 smp_mb__after_atomic();
259 return ret;
260}
261
262#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
263 MLX5E_TC_FLOW_FLAG_##flag)
264
265static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
266{
267 return flow_flag_test(flow, ESWITCH);
268}
269
270static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
271{
272 return flow_flag_test(flow, OFFLOADED);
273}
274
11c9c548
OG		 275static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
276{
277 return jhash(key->actions,
278 key->num_actions * MLX5_MH_ACT_SZ, 0);
279}
280
281static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
282 struct mod_hdr_key *b)
283{
284 if (a->num_actions != b->num_actions)
285 return 1;
286
287 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
288}
289
dd58edc3
VB		 290static struct mod_hdr_tbl *
291get_mod_hdr_table(struct mlx5e_priv *priv, int namespace)
292{
293 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
294
295 return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr :
296 &priv->fs.tc.mod_hdr;
297}
298
299static struct mlx5e_mod_hdr_entry *
300mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key)
301{
302 struct mlx5e_mod_hdr_entry *mh, *found = NULL;
303
304 hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) {
305 if (!cmp_mod_hdr_info(&mh->key, key)) {
306 refcount_inc(&mh->refcnt);
307 found = mh;
308 break;
309 }
310 }
311
312 return found;
313}
314
315static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv,
316 struct mlx5e_mod_hdr_entry *mh)
317{
318 if (!refcount_dec_and_test(&mh->refcnt))
319 return;
320
321 WARN_ON(!list_empty(&mh->flows));
322 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
323 hash_del(&mh->mod_hdr_hlist);
324 kfree(mh);
325}
326
11c9c548
OG		 327static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
328 struct mlx5e_tc_flow *flow,
329 struct mlx5e_tc_flow_parse_attr *parse_attr)
330{
dd58edc3 331 bool is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
11c9c548
OG		 332 int num_actions, actions_size, namespace, err;
333 struct mlx5e_mod_hdr_entry *mh;
dd58edc3 334 struct mod_hdr_tbl *tbl;
11c9c548 335 struct mod_hdr_key key;
11c9c548
OG		 336 u32 hash_key;
337
338 num_actions = parse_attr->num_mod_hdr_actions;
339 actions_size = MLX5_MH_ACT_SZ * num_actions;
340
341 key.actions = parse_attr->mod_hdr_actions;
342 key.num_actions = num_actions;
343
344 hash_key = hash_mod_hdr_info(&key);
345
dd58edc3
VB		 346 namespace = is_eswitch_flow ?
347 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
348 tbl = get_mod_hdr_table(priv, namespace);
11c9c548 349
dd58edc3
VB		 350 mh = mlx5e_mod_hdr_get(tbl, &key, hash_key);
351 if (mh)
11c9c548
OG		 352 goto attach_flow;
353
354 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
355 if (!mh)
356 return -ENOMEM;
357
358 mh->key.actions = (void *)mh + sizeof(*mh);
359 memcpy(mh->key.actions, key.actions, actions_size);
360 mh->key.num_actions = num_actions;
361 INIT_LIST_HEAD(&mh->flows);
dd58edc3 362 refcount_set(&mh->refcnt, 1);
11c9c548
OG		 363
364 err = mlx5_modify_header_alloc(priv->mdev, namespace,
365 mh->key.num_actions,
366 mh->key.actions,
367 &mh->mod_hdr_id);
368 if (err)
369 goto out_err;
370
dd58edc3 371 hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key);
11c9c548
OG		 372
373attach_flow:
dd58edc3 374 flow->mh = mh;
11c9c548 375 list_add(&flow->mod_hdr, &mh->flows);
226f2ca3 376 if (is_eswitch_flow)
11c9c548
OG		 377 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
378 else
379 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
380
381 return 0;
382
383out_err:
384 kfree(mh);
385 return err;
386}
387
388static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
389 struct mlx5e_tc_flow *flow)
390{
5a7e5bcb 391 /* flow wasn't fully initialized */
dd58edc3 392 if (!flow->mh)
5a7e5bcb
VB		 393 return;
394
11c9c548
OG		 395 list_del(&flow->mod_hdr);
396
dd58edc3
VB		 397 mlx5e_mod_hdr_put(priv, flow->mh);
398 flow->mh = NULL;
11c9c548
OG		 399}
400
77ab67b7
OG		 401static
402struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
403{
404 struct net_device *netdev;
405 struct mlx5e_priv *priv;
406
407 netdev = __dev_get_by_index(net, ifindex);
408 priv = netdev_priv(netdev);
409 return priv->mdev;
410}
411
412static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
413{
414 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
415 void *tirc;
416 int err;
417
418 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
419 if (err)
420 goto alloc_tdn_err;
421
422 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
423
424 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 425 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 426 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
427
428 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
429 if (err)
430 goto create_tir_err;
431
432 return 0;
433
434create_tir_err:
435 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
436alloc_tdn_err:
437 return err;
438}
439
440static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
441{
442 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
443 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
444}
445
3f6d08d1
OG		 446static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
447{
448 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
449 struct mlx5e_priv *priv = hp->func_priv;
450 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
451
452 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
453 hp->num_channels);
454
455 for (i = 0; i < sz; i++) {
456 ix = i;
bbeb53b8 457 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 458 ix = mlx5e_bits_invert(i, ilog2(sz));
459 ix = indirection_rqt[ix];
460 rqn = hp->pair->rqn[ix];
461 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
462 }
463}
464
465static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
466{
467 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
468 struct mlx5e_priv *priv = hp->func_priv;
469 struct mlx5_core_dev *mdev = priv->mdev;
470 void *rqtc;
471 u32 *in;
472
473 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
474 in = kvzalloc(inlen, GFP_KERNEL);
475 if (!in)
476 return -ENOMEM;
477
478 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
479
480 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
481 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
482
483 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
484
485 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
486 if (!err)
487 hp->indir_rqt.enabled = true;
488
489 kvfree(in);
490 return err;
491}
492
493static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
494{
495 struct mlx5e_priv *priv = hp->func_priv;
496 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
497 int tt, i, err;
498 void *tirc;
499
500 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 501 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
502
3f6d08d1
OG		 503 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
504 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
505
506 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
507 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
508 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 509 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
510
3f6d08d1
OG		 511 err = mlx5_core_create_tir(hp->func_mdev, in,
512 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
513 if (err) {
514 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
515 goto err_destroy_tirs;
516 }
517 }
518 return 0;
519
520err_destroy_tirs:
521 for (i = 0; i < tt; i++)
522 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
523 return err;
524}
525
526static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
527{
528 int tt;
529
530 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
531 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
532}
533
534static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
535 struct ttc_params *ttc_params)
536{
537 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
538 int tt;
539
540 memset(ttc_params, 0, sizeof(*ttc_params));
541
542 ttc_params->any_tt_tirn = hp->tirn;
543
544 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
545 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
546
547 ft_attr->max_fte = MLX5E_NUM_TT;
548 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
549 ft_attr->prio = MLX5E_TC_PRIO;
550}
551
552static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
553{
554 struct mlx5e_priv *priv = hp->func_priv;
555 struct ttc_params ttc_params;
556 int err;
557
558 err = mlx5e_hairpin_create_indirect_rqt(hp);
559 if (err)
560 return err;
561
562 err = mlx5e_hairpin_create_indirect_tirs(hp);
563 if (err)
564 goto err_create_indirect_tirs;
565
566 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
567 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
568 if (err)
569 goto err_create_ttc_table;
570
571 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
572 hp->num_channels, hp->ttc.ft.t->id);
573
574 return 0;
575
576err_create_ttc_table:
577 mlx5e_hairpin_destroy_indirect_tirs(hp);
578err_create_indirect_tirs:
579 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
580
581 return err;
582}
583
584static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
585{
586 struct mlx5e_priv *priv = hp->func_priv;
587
588 mlx5e_destroy_ttc_table(priv, &hp->ttc);
589 mlx5e_hairpin_destroy_indirect_tirs(hp);
590 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
591}
592
77ab67b7
OG		 593static struct mlx5e_hairpin *
594mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
595 int peer_ifindex)
596{
597 struct mlx5_core_dev *func_mdev, *peer_mdev;
598 struct mlx5e_hairpin *hp;
599 struct mlx5_hairpin *pair;
600 int err;
601
602 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
603 if (!hp)
604 return ERR_PTR(-ENOMEM);
605
606 func_mdev = priv->mdev;
607 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
608
609 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
610 if (IS_ERR(pair)) {
611 err = PTR_ERR(pair);
612 goto create_pair_err;
613 }
614 hp->pair = pair;
615 hp->func_mdev = func_mdev;
3f6d08d1
OG		 616 hp->func_priv = priv;
617 hp->num_channels = params->num_channels;
77ab67b7
OG		 618
619 err = mlx5e_hairpin_create_transport(hp);
620 if (err)
621 goto create_transport_err;
622
3f6d08d1
OG		 623 if (hp->num_channels > 1) {
624 err = mlx5e_hairpin_rss_init(hp);
625 if (err)
626 goto rss_init_err;
627 }
628
77ab67b7
OG		 629 return hp;
630
3f6d08d1
OG		 631rss_init_err:
632 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 633create_transport_err:
634 mlx5_core_hairpin_destroy(hp->pair);
635create_pair_err:
636 kfree(hp);
637 return ERR_PTR(err);
638}
639
640static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
641{
3f6d08d1
OG		 642 if (hp->num_channels > 1)
643 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 644 mlx5e_hairpin_destroy_transport(hp);
645 mlx5_core_hairpin_destroy(hp->pair);
646 kvfree(hp);
647}
648
106be53b
OG		 649static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
650{
651 return (peer_vhca_id << 16 | prio);
652}
653
5c65c564 654static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 655 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 656{
657 struct mlx5e_hairpin_entry *hpe;
106be53b 658 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 659
660 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 661 hairpin_hlist, hash_key) {
e4f9abbd
VB		 662 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
663 refcount_inc(&hpe->refcnt);
5c65c564 664 return hpe;
e4f9abbd 665 }
5c65c564
OG		 666 }
667
668 return NULL;
669}
670
e4f9abbd
VB		 671static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
672 struct mlx5e_hairpin_entry *hpe)
673{
674 /* no more hairpin flows for us, release the hairpin pair */
b32accda 675 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 676 return;
b32accda
VB		 677 hash_del(&hpe->hairpin_hlist);
678 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 679
db76ca24
VB		 680 if (!IS_ERR_OR_NULL(hpe->hp)) {
681 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
682 dev_name(hpe->hp->pair->peer_mdev->device));
683
684 mlx5e_hairpin_destroy(hpe->hp);
685 }
e4f9abbd
VB		 686
687 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 688 kfree(hpe);
689}
690
106be53b
OG		 691#define UNKNOWN_MATCH_PRIO 8
692
693static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 694 struct mlx5_flow_spec *spec, u8 *match_prio,
695 struct netlink_ext_ack *extack)
106be53b
OG		 696{
697 void *headers_c, *headers_v;
698 u8 prio_val, prio_mask = 0;
699 bool vlan_present;
700
701#ifdef CONFIG_MLX5_CORE_EN_DCB
702 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 703 NL_SET_ERR_MSG_MOD(extack,
704 "only PCP trust state supported for hairpin");
106be53b
OG		 705 return -EOPNOTSUPP;
706 }
707#endif
708 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
709 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
710
711 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
712 if (vlan_present) {
713 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
714 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
715 }
716
717 if (!vlan_present || !prio_mask) {
718 prio_val = UNKNOWN_MATCH_PRIO;
719 } else if (prio_mask != 0x7) {
e98bedf5
EB		 720 NL_SET_ERR_MSG_MOD(extack,
721 "masked priority match not supported for hairpin");
106be53b
OG		 722 return -EOPNOTSUPP;
723 }
724
725 *match_prio = prio_val;
726 return 0;
727}
728
5c65c564
OG		 729static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
730 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 731 struct mlx5e_tc_flow_parse_attr *parse_attr,
732 struct netlink_ext_ack *extack)
5c65c564 733{
98b66cb1 734 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 735 struct mlx5_hairpin_params params;
d8822868 736 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 737 struct mlx5e_hairpin_entry *hpe;
738 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 739 u64 link_speed64;
740 u32 link_speed;
106be53b 741 u8 match_prio;
d8822868 742 u16 peer_id;
5c65c564
OG		 743 int err;
744
d8822868
OG		 745 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
746 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 747 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 748 return -EOPNOTSUPP;
749 }
750
d8822868 751 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 752 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
753 extack);
106be53b
OG		 754 if (err)
755 return err;
b32accda
VB		 756
757 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 758 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 759 if (hpe) {
760 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
761 wait_for_completion(&hpe->res_ready);
762
763 if (IS_ERR(hpe->hp)) {
764 err = -EREMOTEIO;
765 goto out_err;
766 }
5c65c564 767 goto attach_flow;
db76ca24 768 }
5c65c564
OG		 769
770 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 771 if (!hpe) {
db76ca24
VB		 772 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
773 return -ENOMEM;
b32accda 774 }
5c65c564 775
73edca73 776 spin_lock_init(&hpe->flows_lock);
5c65c564 777 INIT_LIST_HEAD(&hpe->flows);
db76ca24 778 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 779 hpe->peer_vhca_id = peer_id;
106be53b 780 hpe->prio = match_prio;
e4f9abbd 781 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 782 init_completion(&hpe->res_ready);
783
784 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
785 hash_hairpin_info(peer_id, match_prio));
786 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 787
788 params.log_data_size = 15;
789 params.log_data_size = min_t(u8, params.log_data_size,
790 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
791 params.log_data_size = max_t(u8, params.log_data_size,
792 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 793
eb9180f7
OG		 794 params.log_num_packets = params.log_data_size -
795 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
796 params.log_num_packets = min_t(u8, params.log_num_packets,
797 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
798
799 params.q_counter = priv->q_counter;
3f6d08d1 800 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 801 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 802 link_speed = max_t(u32, link_speed, 50000);
803 link_speed64 = link_speed;
804 do_div(link_speed64, 50000);
805 params.num_channels = link_speed64;
806
5c65c564 807 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 808 hpe->hp = hp;
809 complete_all(&hpe->res_ready);
5c65c564
OG		 810 if (IS_ERR(hp)) {
811 err = PTR_ERR(hp);
db76ca24 812 goto out_err;
5c65c564
OG		 813 }
814
eb9180f7 815 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 816 hp->tirn, hp->pair->rqn[0],
817 dev_name(hp->pair->peer_mdev->device),
eb9180f7 818 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 819
5c65c564 820attach_flow:
3f6d08d1 821 if (hpe->hp->num_channels > 1) {
226f2ca3 822 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 823 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
824 } else {
825 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
826 }
b32accda 827
e4f9abbd 828 flow->hpe = hpe;
73edca73 829 spin_lock(&hpe->flows_lock);
5c65c564 830 list_add(&flow->hairpin, &hpe->flows);
73edca73 831 spin_unlock(&hpe->flows_lock);
3f6d08d1 832
5c65c564
OG		 833 return 0;
834
db76ca24
VB		 835out_err:
836 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 837 return err;
838}
839
840static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
841 struct mlx5e_tc_flow *flow)
842{
5a7e5bcb 843 /* flow wasn't fully initialized */
e4f9abbd 844 if (!flow->hpe)
5a7e5bcb
VB		 845 return;
846
73edca73 847 spin_lock(&flow->hpe->flows_lock);
5c65c564 848 list_del(&flow->hairpin);
73edca73
VB		 849 spin_unlock(&flow->hpe->flows_lock);
850
e4f9abbd
VB		 851 mlx5e_hairpin_put(priv, flow->hpe);
852 flow->hpe = NULL;
5c65c564
OG		 853}
854
c83954ab 855static int
74491de9 856mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 857 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 858 struct mlx5e_tc_flow *flow,
859 struct netlink_ext_ack *extack)
e8f887ac 860{
bb0ee7dc 861 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 862 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 863 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 864 struct mlx5_flow_destination dest[2] = {};
66958ed9 865 struct mlx5_flow_act flow_act = {
3bc4b7bf 866 .action = attr->action,
60786f09 867 .reformat_id = 0,
bb0ee7dc 868 .flags = FLOW_ACT_NO_APPEND,
66958ed9 869 };
aad7e08d 870 struct mlx5_fc *counter = NULL;
5c65c564 871 int err, dest_ix = 0;
e8f887ac 872
bb0ee7dc
JL		 873 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
874 flow_context->flow_tag = attr->flow_tag;
875
226f2ca3 876 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 877 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 878 if (err)
879 return err;
880
226f2ca3 881 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 882 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
883 dest[dest_ix].ft = attr->hairpin_ft;
884 } else {
5c65c564
OG		 885 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
886 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 887 }
888 dest_ix++;
3f6d08d1
OG		 889 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
890 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
891 dest[dest_ix].ft = priv->fs.vlan.ft.t;
892 dest_ix++;
5c65c564 893 }
aad7e08d 894
5c65c564
OG		 895 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
896 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 897 if (IS_ERR(counter))
898 return PTR_ERR(counter);
899
5c65c564 900 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 901 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 902 dest_ix++;
b8aee822 903 attr->counter = counter;
aad7e08d
AV		 904 }
905
2f4fe4ca 906 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 907 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 908 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 909 kfree(parse_attr->mod_hdr_actions);
c83954ab 910 if (err)
5a7e5bcb 911 return err;
2f4fe4ca
OG		 912 }
913
b6fac0b4 914 mutex_lock(&priv->fs.tc.t_lock);
acff797c 915 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 916 int tc_grp_size, tc_tbl_size;
917 u32 max_flow_counter;
918
919 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
920 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
921
922 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
923
924 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
925 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
926
acff797c
MG		 927 priv->fs.tc.t =
928 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
929 MLX5E_TC_PRIO,
21b9c144 930 tc_tbl_size,
acff797c 931 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 932 MLX5E_TC_FT_LEVEL, 0);
acff797c 933 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 934 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5
EB		 935 NL_SET_ERR_MSG_MOD(extack,
936 "Failed to create tc offload table\n");
e8f887ac
AV		 937 netdev_err(priv->netdev,
938 "Failed to create tc offload table\n");
5a7e5bcb 939 return PTR_ERR(priv->fs.tc.t);
e8f887ac 940 }
e8f887ac
AV		 941 }
942
38aa51c1 943 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 944 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 945
c83954ab
RL		 946 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
947 &flow_act, dest, dest_ix);
b6fac0b4 948 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 949
5a7e5bcb
VB		 950 if (IS_ERR(flow->rule[0]))
951 return PTR_ERR(flow->rule[0]);
aad7e08d 952
c83954ab 953 return 0;
e8f887ac
AV		 954}
955
d85cdccb
OG		 956static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
957 struct mlx5e_tc_flow *flow)
958{
513f8f7f 959 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 960 struct mlx5_fc *counter = NULL;
961
b8aee822 962 counter = attr->counter;
5a7e5bcb
VB		 963 if (!IS_ERR_OR_NULL(flow->rule[0]))
964 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 965 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 966
b6fac0b4 967 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 968 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 969 mlx5_destroy_flow_table(priv->fs.tc.t);
970 priv->fs.tc.t = NULL;
971 }
b6fac0b4 972 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 973
513f8f7f 974 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 975 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 976
226f2ca3 977 if (flow_flag_test(flow, HAIRPIN))
5c65c564 978 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 979}
980
aa0cbbae 981static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 982 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 983
3c37745e 984static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 985 struct mlx5e_tc_flow *flow,
733d4f36
RD		 986 struct net_device *mirred_dev,
987 int out_index,
8c4dc42b 988 struct netlink_ext_ack *extack,
0ad060ee
RD		 989 struct net_device **encap_dev,
990 bool *encap_valid);
3c37745e 991
6d2a3ed0
OG		 992static struct mlx5_flow_handle *
993mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
994 struct mlx5e_tc_flow *flow,
995 struct mlx5_flow_spec *spec,
996 struct mlx5_esw_flow_attr *attr)
997{
998 struct mlx5_flow_handle *rule;
999
1000 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1001 if (IS_ERR(rule))
1002 return rule;
1003
e85e02ba 1004 if (attr->split_count) {
6d2a3ed0
OG		 1005 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1006 if (IS_ERR(flow->rule[1])) {
1007 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1008 return flow->rule[1];
1009 }
1010 }
1011
6d2a3ed0
OG		 1012 return rule;
1013}
1014
1015static void
1016mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1017 struct mlx5e_tc_flow *flow,
1018 struct mlx5_esw_flow_attr *attr)
1019{
226f2ca3 1020 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1021
e85e02ba 1022 if (attr->split_count)
6d2a3ed0
OG		 1023 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1024
1025 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1026}
1027
5dbe906f
PB		 1028static struct mlx5_flow_handle *
1029mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1030 struct mlx5e_tc_flow *flow,
1031 struct mlx5_flow_spec *spec,
1032 struct mlx5_esw_flow_attr *slow_attr)
1033{
1034 struct mlx5_flow_handle *rule;
1035
1036 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 1037 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 1038 slow_attr->split_count = 0;
154e62ab 1039 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 1040
1041 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1042 if (!IS_ERR(rule))
226f2ca3 1043 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1044
1045 return rule;
1046}
1047
1048static void
1049mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1050 struct mlx5e_tc_flow *flow,
1051 struct mlx5_esw_flow_attr *slow_attr)
1052{
1053 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 1054 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 1055 slow_attr->split_count = 0;
154e62ab 1056 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f 1057 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1058 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1059}
1060
ad86755b
VB		 1061/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1062 * function.
1063 */
1064static void unready_flow_add(struct mlx5e_tc_flow *flow,
1065 struct list_head *unready_flows)
1066{
1067 flow_flag_set(flow, NOT_READY);
1068 list_add_tail(&flow->unready, unready_flows);
1069}
1070
1071/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1072 * function.
1073 */
1074static void unready_flow_del(struct mlx5e_tc_flow *flow)
1075{
1076 list_del(&flow->unready);
1077 flow_flag_clear(flow, NOT_READY);
1078}
1079
b4a23329
RD		 1080static void add_unready_flow(struct mlx5e_tc_flow *flow)
1081{
1082 struct mlx5_rep_uplink_priv *uplink_priv;
1083 struct mlx5e_rep_priv *rpriv;
1084 struct mlx5_eswitch *esw;
1085
1086 esw = flow->priv->mdev->priv.eswitch;
1087 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1088 uplink_priv = &rpriv->uplink_priv;
1089
ad86755b
VB		 1090 mutex_lock(&uplink_priv->unready_flows_lock);
1091 unready_flow_add(flow, &uplink_priv->unready_flows);
1092 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1093}
1094
1095static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1096{
ad86755b
VB		 1097 struct mlx5_rep_uplink_priv *uplink_priv;
1098 struct mlx5e_rep_priv *rpriv;
1099 struct mlx5_eswitch *esw;
1100
1101 esw = flow->priv->mdev->priv.eswitch;
1102 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1103 uplink_priv = &rpriv->uplink_priv;
1104
1105 mutex_lock(&uplink_priv->unready_flows_lock);
1106 unready_flow_del(flow);
1107 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1108}
1109
c83954ab 1110static int
74491de9 1111mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1112 struct mlx5e_tc_flow *flow,
1113 struct netlink_ext_ack *extack)
adb4c123
OG		 1114{
1115 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 1116 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 1117 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1118 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
bf07aa73 1119 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 1120 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1121 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1122 struct mlx5e_rep_priv *rpriv;
1123 struct mlx5e_priv *out_priv;
0ad060ee
RD		 1124 bool encap_valid = true;
1125 int err = 0;
f493f155 1126 int out_index;
8b32580d 1127
d14f6f2a
OG		 1128 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
1129 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
1130 return -EOPNOTSUPP;
1131 }
bf07aa73
PB		 1132
1133 if (attr->chain > max_chain) {
1134 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
5a7e5bcb 1135 return -EOPNOTSUPP;
bf07aa73
PB		 1136 }
1137
1138 if (attr->prio > max_prio) {
1139 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
5a7e5bcb 1140 return -EOPNOTSUPP;
bf07aa73 1141 }
e52c2802 1142
f493f155 1143 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1144 int mirred_ifindex;
1145
f493f155
EB		 1146 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1147 continue;
1148
7040632d 1149 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1150 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1151 mirred_ifindex);
733d4f36 1152 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1153 extack, &encap_dev, &encap_valid);
1154 if (err)
5a7e5bcb 1155 return err;
0ad060ee 1156
3c37745e
OG		 1157 out_priv = netdev_priv(encap_dev);
1158 rpriv = out_priv->ppriv;
1cc26d74
EB		 1159 attr->dests[out_index].rep = rpriv->rep;
1160 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1161 }
1162
8b32580d 1163 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1164 if (err)
5a7e5bcb 1165 return err;
adb4c123 1166
d7e75a32 1167 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1168 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1169 kfree(parse_attr->mod_hdr_actions);
c83954ab 1170 if (err)
5a7e5bcb 1171 return err;
d7e75a32
OG		 1172 }
1173
b8aee822 1174 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1175 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1176 if (IS_ERR(counter))
1177 return PTR_ERR(counter);
b8aee822
MB		 1178
1179 attr->counter = counter;
1180 }
1181
0ad060ee
RD		 1182 /* we get here if one of the following takes place:
1183 * (1) there's no error
1184 * (2) there's an encap action and we don't have valid neigh
3c37745e 1185 */
0ad060ee 1186 if (!encap_valid) {
5dbe906f
PB		 1187 /* continue with goto slow path rule instead */
1188 struct mlx5_esw_flow_attr slow_attr;
1189
1190 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1191 } else {
6d2a3ed0 1192 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1193 }
c83954ab 1194
5a7e5bcb
VB		 1195 if (IS_ERR(flow->rule[0]))
1196 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1197 else
1198 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1199
1200 return 0;
aa0cbbae 1201}
d85cdccb 1202
9272e3df
YK		 1203static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1204{
1205 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1206 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1207 spec->match_value,
1208 misc_parameters_3);
1209 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1210 headers_v,
1211 geneve_tlv_option_0_data);
1212
1213 return !!geneve_tlv_opt_0_data;
1214}
1215
d85cdccb
OG		 1216static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1217 struct mlx5e_tc_flow *flow)
1218{
1219 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1220 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1221 struct mlx5_esw_flow_attr slow_attr;
f493f155 1222 int out_index;
d85cdccb 1223
226f2ca3 1224 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1225 remove_unready_flow(flow);
ef06c9ee
RD		 1226 kvfree(attr->parse_attr);
1227 return;
1228 }
1229
226f2ca3
VB		 1230 if (mlx5e_is_offloaded_flow(flow)) {
1231 if (flow_flag_test(flow, SLOW))
5dbe906f
PB		 1232 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1233 else
1234 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1235 }
d85cdccb 1236
9272e3df
YK		 1237 if (mlx5_flow_has_geneve_opt(flow))
1238 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1239
513f8f7f 1240 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1241
f493f155 1242 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1243 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1244 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1245 kvfree(attr->parse_attr);
d7e75a32 1246
513f8f7f 1247 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1248 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1249
1250 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1251 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1252}
1253
232c0013
HHZ		 1254void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1255 struct mlx5e_encap_entry *e)
1256{
3c37745e 1257 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1258 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
5a7e5bcb 1259 struct encap_flow_item *efi, *tmp;
6d2a3ed0
OG		 1260 struct mlx5_flow_handle *rule;
1261 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1262 struct mlx5e_tc_flow *flow;
1263 int err;
1264
54c177ca
OS		 1265 err = mlx5_packet_reformat_alloc(priv->mdev,
1266 e->reformat_type,
60786f09 1267 e->encap_size, e->encap_header,
31ca3648 1268 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1269 &e->encap_id);
232c0013
HHZ		 1270 if (err) {
1271 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1272 err);
1273 return;
1274 }
1275 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1276 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1277
5a7e5bcb 1278 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
8c4dc42b
EB		 1279 bool all_flow_encaps_valid = true;
1280 int i;
1281
79baaec7 1282 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5a7e5bcb
VB		 1283 if (IS_ERR(mlx5e_flow_get(flow)))
1284 continue;
1285
3c37745e 1286 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1287 spec = &esw_attr->parse_attr->spec;
1288
8c4dc42b
EB		 1289 esw_attr->dests[efi->index].encap_id = e->encap_id;
1290 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1291 /* Flow can be associated with multiple encap entries.
1292 * Before offloading the flow verify that all of them have
1293 * a valid neighbour.
1294 */
1295 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1296 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1297 continue;
1298 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1299 all_flow_encaps_valid = false;
1300 break;
1301 }
1302 }
1303 /* Do not offload flows with unresolved neighbors */
1304 if (!all_flow_encaps_valid)
5a7e5bcb 1305 goto loop_cont;
5dbe906f 1306 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1307 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1308 if (IS_ERR(rule)) {
1309 err = PTR_ERR(rule);
232c0013
HHZ		 1310 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1311 err);
5a7e5bcb 1312 goto loop_cont;
232c0013 1313 }
5dbe906f
PB		 1314
1315 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
6d2a3ed0 1316 flow->rule[0] = rule;
226f2ca3
VB		 1317 /* was unset when slow path rule removed */
1318 flow_flag_set(flow, OFFLOADED);
5a7e5bcb
VB		 1319
1320loop_cont:
1321 mlx5e_flow_put(priv, flow);
232c0013
HHZ		 1322 }
1323}
1324
1325void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1326 struct mlx5e_encap_entry *e)
1327{
3c37745e 1328 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1329 struct mlx5_esw_flow_attr slow_attr;
5a7e5bcb 1330 struct encap_flow_item *efi, *tmp;
5dbe906f
PB		 1331 struct mlx5_flow_handle *rule;
1332 struct mlx5_flow_spec *spec;
232c0013 1333 struct mlx5e_tc_flow *flow;
5dbe906f 1334 int err;
232c0013 1335
5a7e5bcb 1336 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7 1337 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5a7e5bcb
VB		 1338 if (IS_ERR(mlx5e_flow_get(flow)))
1339 continue;
1340
5dbe906f
PB		 1341 spec = &flow->esw_attr->parse_attr->spec;
1342
1343 /* update from encap rule to slow path rule */
1344 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1345 /* mark the flow's encap dest as non-valid */
1346 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1347
1348 if (IS_ERR(rule)) {
1349 err = PTR_ERR(rule);
1350 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1351 err);
5a7e5bcb 1352 goto loop_cont;
5dbe906f
PB		 1353 }
1354
1355 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1356 flow->rule[0] = rule;
226f2ca3
VB		 1357 /* was unset when fast path rule removed */
1358 flow_flag_set(flow, OFFLOADED);
5a7e5bcb
VB		 1359
1360loop_cont:
1361 mlx5e_flow_put(priv, flow);
232c0013
HHZ		 1362 }
1363
61c806da
OG		 1364 /* we know that the encap is valid */
1365 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1366 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1367}
1368
b8aee822
MB		 1369static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1370{
226f2ca3 1371 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1372 return flow->esw_attr->counter;
1373 else
1374 return flow->nic_attr->counter;
1375}
1376
f6dfb4c3
HHZ		 1377void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1378{
1379 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
f6dfb4c3
HHZ		 1380 struct mlx5e_tc_flow *flow;
1381 struct mlx5e_encap_entry *e;
1382 struct mlx5_fc *counter;
1383 struct neigh_table *tbl;
1384 bool neigh_used = false;
1385 struct neighbour *n;
90bb7692 1386 u64 lastuse;
f6dfb4c3
HHZ		 1387
1388 if (m_neigh->family == AF_INET)
1389 tbl = &arp_tbl;
1390#if IS_ENABLED(CONFIG_IPV6)
1391 else if (m_neigh->family == AF_INET6)
423c9db2 1392 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1393#endif
1394 else
1395 return;
1396
1397 list_for_each_entry(e, &nhe->encap_list, encap_list) {
5a7e5bcb 1398 struct encap_flow_item *efi, *tmp;
f6dfb4c3
HHZ		 1399 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1400 continue;
5a7e5bcb 1401 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1402 flow = container_of(efi, struct mlx5e_tc_flow,
1403 encaps[efi->index]);
5a7e5bcb
VB		 1404 if (IS_ERR(mlx5e_flow_get(flow)))
1405 continue;
1406
226f2ca3 1407 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1408 counter = mlx5e_tc_get_counter(flow);
90bb7692 1409 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3 1410 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
5a7e5bcb 1411 mlx5e_flow_put(netdev_priv(e->out_dev), flow);
f6dfb4c3
HHZ		 1412 neigh_used = true;
1413 break;
1414 }
1415 }
5a7e5bcb
VB		 1416
1417 mlx5e_flow_put(netdev_priv(e->out_dev), flow);
f6dfb4c3 1418 }
e36d4810
RD		 1419 if (neigh_used)
1420 break;
f6dfb4c3
HHZ		 1421 }
1422
1423 if (neigh_used) {
1424 nhe->reported_lastuse = jiffies;
1425
1426 /* find the relevant neigh according to the cached device and
1427 * dst ip pair
1428 */
1429 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1430 if (!n)
f6dfb4c3 1431 return;
f6dfb4c3
HHZ		 1432
1433 neigh_event_send(n, NULL);
1434 neigh_release(n);
1435 }
1436}
1437
d85cdccb 1438static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1439 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1440{
8c4dc42b 1441 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1442
5a7e5bcb
VB		 1443 /* flow wasn't fully initialized */
1444 if (list_empty(&flow->encaps[out_index].list))
1445 return;
1446
8c4dc42b 1447 list_del(&flow->encaps[out_index].list);
5067b602 1448 if (list_empty(next)) {
c1ae1152 1449 struct mlx5e_encap_entry *e;
5067b602 1450
c1ae1152 1451 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1452 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1453
1454 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1455 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1456
cdc5a7f3 1457 hash_del_rcu(&e->encap_hlist);
232c0013 1458 kfree(e->encap_header);
5067b602
RD		 1459 kfree(e);
1460 }
1461}
1462
04de7dda
RD		 1463static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1464{
1465 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1466
226f2ca3
VB		 1467 if (!flow_flag_test(flow, ESWITCH) ||
1468 !flow_flag_test(flow, DUP))
04de7dda
RD		 1469 return;
1470
1471 mutex_lock(&esw->offloads.peer_mutex);
1472 list_del(&flow->peer);
1473 mutex_unlock(&esw->offloads.peer_mutex);
1474
226f2ca3 1475 flow_flag_clear(flow, DUP);
04de7dda
RD		 1476
1477 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1478 kvfree(flow->peer_flow);
1479 flow->peer_flow = NULL;
1480}
1481
1482static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1483{
1484 struct mlx5_core_dev *dev = flow->priv->mdev;
1485 struct mlx5_devcom *devcom = dev->priv.devcom;
1486 struct mlx5_eswitch *peer_esw;
1487
1488 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1489 if (!peer_esw)
1490 return;
1491
1492 __mlx5e_tc_del_fdb_peer_flow(flow);
1493 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1494}
1495
e8f887ac 1496static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1497 struct mlx5e_tc_flow *flow)
e8f887ac 1498{
226f2ca3 1499 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1500 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1501 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1502 } else {
d85cdccb 1503 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1504 }
e8f887ac
AV		 1505}
1506
bbd00f7e
HHZ		 1507
1508static int parse_tunnel_attr(struct mlx5e_priv *priv,
1509 struct mlx5_flow_spec *spec,
f9e30088 1510 struct flow_cls_offload *f,
6363651d 1511 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1512{
e98bedf5 1513 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1514 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1515 outer_headers);
1516 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1517 outer_headers);
f9e30088 1518 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1519 int err;
2e72eb43 1520
101f4de9 1521 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1522 headers_c, headers_v, match_level);
54c177ca
OS		 1523 if (err) {
1524 NL_SET_ERR_MSG_MOD(extack,
1525 "failed to parse tunnel attributes");
101f4de9 1526 return err;
bbd00f7e
HHZ		 1527 }
1528
d1bda7ee 1529 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) {
8f256622
PNA		 1530 struct flow_match_ipv4_addrs match;
1531
1532 flow_rule_match_enc_ipv4_addrs(rule, &match);
bbd00f7e
HHZ		 1533 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1534 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1535 ntohl(match.mask->src));
bbd00f7e
HHZ		 1536 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1537 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1538 ntohl(match.key->src));
bbd00f7e
HHZ		 1539
1540 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1541 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1542 ntohl(match.mask->dst));
bbd00f7e
HHZ		 1543 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1544 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1545 ntohl(match.key->dst));
bbd00f7e 1546
2e72eb43
OG		 1547 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1548 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
d1bda7ee 1549 } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS)) {
8f256622 1550 struct flow_match_ipv6_addrs match;
19f44401 1551
8f256622 1552 flow_rule_match_enc_ipv6_addrs(rule, &match);
19f44401
OG		 1553 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1554 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1555 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1556 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1557 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1558 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1559
1560 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1561 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1562 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1563 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1564 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1565 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1566
1567 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1568 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1569 }
bbd00f7e 1570
8f256622
PNA		 1571 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1572 struct flow_match_ip match;
bcef735c 1573
8f256622
PNA		 1574 flow_rule_match_enc_ip(rule, &match);
1575 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1576 match.mask->tos & 0x3);
1577 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1578 match.key->tos & 0x3);
bcef735c 1579
8f256622
PNA		 1580 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1581 match.mask->tos >> 2);
1582 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1583 match.key->tos >> 2);
bcef735c 1584
8f256622
PNA		 1585 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1586 match.mask->ttl);
1587 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1588 match.key->ttl);
e98bedf5 1589
8f256622 1590 if (match.mask->ttl &&
e98bedf5
EB		 1591 !MLX5_CAP_ESW_FLOWTABLE_FDB
1592 (priv->mdev,
1593 ft_field_support.outer_ipv4_ttl)) {
1594 NL_SET_ERR_MSG_MOD(extack,
1595 "Matching on TTL is not supported");
1596 return -EOPNOTSUPP;
1597 }
1598
bcef735c
OG		 1599 }
1600
bbd00f7e
HHZ		 1601 /* Enforce DMAC when offloading incoming tunneled flows.
1602 * Flow counters require a match on the DMAC.
1603 */
1604 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1605 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1606 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1607 dmac_47_16), priv->netdev->dev_addr);
1608
1609 /* let software handle IP fragments */
1610 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1611 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1612
1613 return 0;
1614}
1615
8377629e
EB		 1616static void *get_match_headers_criteria(u32 flags,
1617 struct mlx5_flow_spec *spec)
1618{
1619 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1620 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1621 inner_headers) :
1622 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1623 outer_headers);
1624}
1625
1626static void *get_match_headers_value(u32 flags,
1627 struct mlx5_flow_spec *spec)
1628{
1629 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1630 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1631 inner_headers) :
1632 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1633 outer_headers);
1634}
1635
de0af0bf
RD		 1636static int __parse_cls_flower(struct mlx5e_priv *priv,
1637 struct mlx5_flow_spec *spec,
f9e30088 1638 struct flow_cls_offload *f,
54c177ca 1639 struct net_device *filter_dev,
6363651d 1640 u8 *match_level, u8 *tunnel_match_level)
e3a2b7ed 1641{
e98bedf5 1642 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1643 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1644 outer_headers);
1645 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1646 outer_headers);
699e96dd
JL		 1647 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1648 misc_parameters);
1649 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1650 misc_parameters);
f9e30088 1651 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1652 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1653 u16 addr_type = 0;
1654 u8 ip_proto = 0;
1655
d708f902 1656 *match_level = MLX5_MATCH_NONE;
de0af0bf 1657
8f256622 1658 if (dissector->used_keys &
3d144578
VB		 1659 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1660 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 1661 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1662 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1663 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1664 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1665 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1666 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1667 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1668 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1669 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1670 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1671 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1672 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1673 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1674 BIT(FLOW_DISSECTOR_KEY_IP) |
9272e3df
YK		 1675 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1676 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 1677 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1678 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1679 dissector->used_keys);
e3a2b7ed
AV		 1680 return -EOPNOTSUPP;
1681 }
1682
075973c7 1683 if (mlx5e_get_tc_tun(filter_dev)) {
d1bda7ee 1684 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
bbd00f7e 1685 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1686
1687 /* In decap flow, header pointers should point to the inner
1688 * headers, outer header were already set by parse_tunnel_attr
1689 */
8377629e
EB		 1690 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1691 spec);
1692 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1693 spec);
bbd00f7e
HHZ		 1694 }
1695
8f256622
PNA		 1696 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1697 struct flow_match_basic match;
1698
1699 flow_rule_match_basic(rule, &match);
d3a80bb5 1700 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1701 ntohs(match.mask->n_proto));
d3a80bb5 1702 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1703 ntohs(match.key->n_proto));
e3a2b7ed 1704
8f256622 1705 if (match.mask->n_proto)
d708f902 1706 *match_level = MLX5_MATCH_L2;
e3a2b7ed 1707 }
35a605db
EB		 1708 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1709 is_vlan_dev(filter_dev)) {
1710 struct flow_dissector_key_vlan filter_dev_mask;
1711 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 1712 struct flow_match_vlan match;
1713
35a605db
EB		 1714 if (is_vlan_dev(filter_dev)) {
1715 match.key = &filter_dev_key;
1716 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1717 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1718 match.key->vlan_priority = 0;
1719 match.mask = &filter_dev_mask;
1720 memset(match.mask, 0xff, sizeof(*match.mask));
1721 match.mask->vlan_priority = 0;
1722 } else {
1723 flow_rule_match_vlan(rule, &match);
1724 }
8f256622
PNA		 1725 if (match.mask->vlan_id ||
1726 match.mask->vlan_priority ||
1727 match.mask->vlan_tpid) {
1728 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1729 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1730 svlan_tag, 1);
1731 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1732 svlan_tag, 1);
1733 } else {
1734 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1735 cvlan_tag, 1);
1736 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1737 cvlan_tag, 1);
1738 }
095b6cfd 1739
8f256622
PNA		 1740 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1741 match.mask->vlan_id);
1742 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1743 match.key->vlan_id);
358d79a4 1744
8f256622
PNA		 1745 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1746 match.mask->vlan_priority);
1747 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1748 match.key->vlan_priority);
54782900 1749
d708f902 1750 *match_level = MLX5_MATCH_L2;
54782900 1751 }
d3a80bb5 1752 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1753 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1754 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1755 *match_level = MLX5_MATCH_L2;
54782900
OG		 1756 }
1757
8f256622
PNA		 1758 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1759 struct flow_match_vlan match;
1760
12d5cbf8 1761 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 1762 if (match.mask->vlan_id ||
1763 match.mask->vlan_priority ||
1764 match.mask->vlan_tpid) {
1765 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1766 MLX5_SET(fte_match_set_misc, misc_c,
1767 outer_second_svlan_tag, 1);
1768 MLX5_SET(fte_match_set_misc, misc_v,
1769 outer_second_svlan_tag, 1);
1770 } else {
1771 MLX5_SET(fte_match_set_misc, misc_c,
1772 outer_second_cvlan_tag, 1);
1773 MLX5_SET(fte_match_set_misc, misc_v,
1774 outer_second_cvlan_tag, 1);
1775 }
1776
1777 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1778 match.mask->vlan_id);
699e96dd 1779 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 1780 match.key->vlan_id);
699e96dd 1781 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 1782 match.mask->vlan_priority);
699e96dd 1783 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 1784 match.key->vlan_priority);
699e96dd
JL		 1785
1786 *match_level = MLX5_MATCH_L2;
1787 }
1788 }
1789
8f256622
PNA		 1790 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1791 struct flow_match_eth_addrs match;
54782900 1792
8f256622 1793 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 1794 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1795 dmac_47_16),
8f256622 1796 match.mask->dst);
d3a80bb5
OG		 1797 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1798 dmac_47_16),
8f256622 1799 match.key->dst);
d3a80bb5
OG		 1800
1801 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1802 smac_47_16),
8f256622 1803 match.mask->src);
d3a80bb5
OG		 1804 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1805 smac_47_16),
8f256622 1806 match.key->src);
d3a80bb5 1807
8f256622
PNA		 1808 if (!is_zero_ether_addr(match.mask->src) ||
1809 !is_zero_ether_addr(match.mask->dst))
d708f902 1810 *match_level = MLX5_MATCH_L2;
54782900
OG		 1811 }
1812
8f256622
PNA		 1813 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1814 struct flow_match_control match;
54782900 1815
8f256622
PNA		 1816 flow_rule_match_control(rule, &match);
1817 addr_type = match.key->addr_type;
54782900
OG		 1818
1819 /* the HW doesn't support frag first/later */
8f256622 1820 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 1821 return -EOPNOTSUPP;
1822
8f256622 1823 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 1824 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1825 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 1826 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 1827
1828 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 1829 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1830 *match_level = MLX5_MATCH_L2;
54782900
OG		 1831 /* *** L2 attributes parsing up to here *** */
1832 else
83621b7d 1833 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1834 }
1835 }
1836
8f256622
PNA		 1837 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1838 struct flow_match_basic match;
1839
1840 flow_rule_match_basic(rule, &match);
1841 ip_proto = match.key->ip_proto;
54782900
OG		 1842
1843 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 1844 match.mask->ip_proto);
54782900 1845 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 1846 match.key->ip_proto);
54782900 1847
8f256622 1848 if (match.mask->ip_proto)
d708f902 1849 *match_level = MLX5_MATCH_L3;
54782900
OG		 1850 }
1851
e3a2b7ed 1852 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 1853 struct flow_match_ipv4_addrs match;
e3a2b7ed 1854
8f256622 1855 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 1856 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1857 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1858 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1859 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1860 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1861 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1862 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1863 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1864 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1865 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1866 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1867 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1868
8f256622 1869 if (match.mask->src || match.mask->dst)
d708f902 1870 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1871 }
1872
1873 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 1874 struct flow_match_ipv6_addrs match;
e3a2b7ed 1875
8f256622 1876 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 1877 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1878 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1879 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1880 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1881 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1882 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1883
1884 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1885 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1886 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1887 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1888 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1889 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1890
8f256622
PNA		 1891 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1892 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 1893 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1894 }
1895
8f256622
PNA		 1896 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1897 struct flow_match_ip match;
1f97a526 1898
8f256622
PNA		 1899 flow_rule_match_ip(rule, &match);
1900 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1901 match.mask->tos & 0x3);
1902 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1903 match.key->tos & 0x3);
1f97a526 1904
8f256622
PNA		 1905 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1906 match.mask->tos >> 2);
1907 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1908 match.key->tos >> 2);
1f97a526 1909
8f256622
PNA		 1910 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1911 match.mask->ttl);
1912 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1913 match.key->ttl);
1f97a526 1914
8f256622 1915 if (match.mask->ttl &&
a8ade55f 1916 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1917 ft_field_support.outer_ipv4_ttl)) {
1918 NL_SET_ERR_MSG_MOD(extack,
1919 "Matching on TTL is not supported");
1f97a526 1920 return -EOPNOTSUPP;
e98bedf5 1921 }
a8ade55f 1922
8f256622 1923 if (match.mask->tos || match.mask->ttl)
d708f902 1924 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1925 }
1926
54782900
OG		 1927 /* *** L3 attributes parsing up to here *** */
1928
8f256622
PNA		 1929 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1930 struct flow_match_ports match;
1931
1932 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 1933 switch (ip_proto) {
1934 case IPPROTO_TCP:
1935 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1936 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 1937 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1938 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1939
1940 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1941 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 1942 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1943 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1944 break;
1945
1946 case IPPROTO_UDP:
1947 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1948 udp_sport, ntohs(match.mask->src));
e3a2b7ed 1949 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1950 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1951
1952 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1953 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 1954 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1955 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1956 break;
1957 default:
e98bedf5
EB		 1958 NL_SET_ERR_MSG_MOD(extack,
1959 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1960 netdev_err(priv->netdev,
1961 "Only UDP and TCP transport are supported\n");
1962 return -EINVAL;
1963 }
de0af0bf 1964
8f256622 1965 if (match.mask->src || match.mask->dst)
d708f902 1966 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1967 }
1968
8f256622
PNA		 1969 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
1970 struct flow_match_tcp match;
e77834ec 1971
8f256622 1972 flow_rule_match_tcp(rule, &match);
e77834ec 1973 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 1974 ntohs(match.mask->flags));
e77834ec 1975 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 1976 ntohs(match.key->flags));
e77834ec 1977
8f256622 1978 if (match.mask->flags)
d708f902 1979 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1980 }
1981
e3a2b7ed
AV		 1982 return 0;
1983}
1984
de0af0bf 1985static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1986 struct mlx5e_tc_flow *flow,
de0af0bf 1987 struct mlx5_flow_spec *spec,
f9e30088 1988 struct flow_cls_offload *f,
54c177ca 1989 struct net_device *filter_dev)
de0af0bf 1990{
e98bedf5 1991 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1992 struct mlx5_core_dev *dev = priv->mdev;
1993 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39 1994 struct mlx5e_rep_priv *rpriv = priv->ppriv;
6363651d 1995 u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
1d447a39 1996 struct mlx5_eswitch_rep *rep;
226f2ca3 1997 bool is_eswitch_flow;
de0af0bf
RD		 1998 int err;
1999
6363651d 2000 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
de0af0bf 2001
226f2ca3
VB		 2002 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2003 if (!err && is_eswitch_flow) {
1d447a39 2004 rep = rpriv->rep;
b05af6aa 2005 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2006 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 2007 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 2008 NL_SET_ERR_MSG_MOD(extack,
2009 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2010 netdev_warn(priv->netdev,
2011 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 2012 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2013 return -EOPNOTSUPP;
2014 }
2015 }
2016
226f2ca3 2017 if (is_eswitch_flow) {
38aa51c1 2018 flow->esw_attr->match_level = match_level;
6363651d
OG		 2019 flow->esw_attr->tunnel_match_level = tunnel_match_level;
2020 } else {
38aa51c1 2021 flow->nic_attr->match_level = match_level;
6363651d 2022 }
38aa51c1 2023
de0af0bf
RD		 2024 return err;
2025}
2026
d79b6df6
OG		 2027struct pedit_headers {
2028 struct ethhdr eth;
0eb69bb9 2029 struct vlan_hdr vlan;
d79b6df6
OG		 2030 struct iphdr ip4;
2031 struct ipv6hdr ip6;
2032 struct tcphdr tcp;
2033 struct udphdr udp;
2034};
2035
c500c86b
PNA		 2036struct pedit_headers_action {
2037 struct pedit_headers vals;
2038 struct pedit_headers masks;
2039 u32 pedits;
2040};
2041
d79b6df6 2042static int pedit_header_offsets[] = {
73867881
PNA		 2043 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2044 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2045 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2046 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2047 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2048};
2049
2050#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2051
2052static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2053 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2054{
2055 u32 *curr_pmask, *curr_pval;
2056
c500c86b
PNA		 2057 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2058 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2059
2060 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2061 goto out_err;
2062
2063 *curr_pmask |= mask;
2064 *curr_pval |= (val & mask);
2065
2066 return 0;
2067
2068out_err:
2069 return -EOPNOTSUPP;
2070}
2071
2072struct mlx5_fields {
2073 u8 field;
2074 u8 size;
2075 u32 offset;
27c11b6b 2076 u32 match_offset;
d79b6df6
OG		 2077};
2078
27c11b6b
EB		 2079#define OFFLOAD(fw_field, size, field, off, match_field) \
2080 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
2081 offsetof(struct pedit_headers, field) + (off), \
2082 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2083
2ef86872
EB		 2084/* masked values are the same and there are no rewrites that do not have a
2085 * match.
2086 */
2087#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2088 type matchmaskx = *(type *)(matchmaskp); \
2089 type matchvalx = *(type *)(matchvalp); \
2090 type maskx = *(type *)(maskp); \
2091 type valx = *(type *)(valp); \
2092 \
2093 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2094 matchmaskx)); \
2095})
2096
27c11b6b
EB		 2097static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2098 void *matchmaskp, int size)
2099{
2100 bool same = false;
2101
2102 switch (size) {
2103 case sizeof(u8):
2ef86872 2104 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2105 break;
2106 case sizeof(u16):
2ef86872 2107 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2108 break;
2109 case sizeof(u32):
2ef86872 2110 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2111 break;
2112 }
2113
2114 return same;
2115}
a8e4f0c4 2116
d79b6df6 2117static struct mlx5_fields fields[] = {
27c11b6b
EB		 2118 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
2119 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0),
2120 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
2121 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0),
2122 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype),
2123 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid),
2124
2125 OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit),
2126 OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2127 OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2128
2129 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
2130 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2131 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0,
2132 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2133 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0,
2134 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2135 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0,
2136 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2137 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
2138 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2139 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0,
2140 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2141 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0,
2142 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2143 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0,
2144 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2145 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
2146
2147 OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport),
2148 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport),
2149 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
2150
2151 OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
2152 OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport),
d79b6df6
OG		 2153};
2154
218d05ce
TZ		 2155/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2156 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2157 * says how many HW actions were actually parsed.
d79b6df6 2158 */
c500c86b 2159static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5 2160 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2161 u32 *action_flags,
e98bedf5 2162 struct netlink_ext_ack *extack)
d79b6df6
OG		 2163{
2164 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
27c11b6b
EB		 2165 void *headers_c = get_match_headers_criteria(*action_flags,
2166 &parse_attr->spec);
2167 void *headers_v = get_match_headers_value(*action_flags,
2168 &parse_attr->spec);
2b64beba 2169 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 2170 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 2171 struct mlx5_fields *f;
2172 u8 cmd, field_bsize;
e3ca4e05 2173 u32 s_mask, a_mask;
d79b6df6 2174 unsigned long mask;
2b64beba
OG		 2175 __be32 mask_be32;
2176 __be16 mask_be16;
d79b6df6
OG		 2177 void *action;
2178
73867881
PNA		 2179 set_masks = &hdrs[0].masks;
2180 add_masks = &hdrs[1].masks;
2181 set_vals = &hdrs[0].vals;
2182 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2183
2184 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 2185 action = parse_attr->mod_hdr_actions +
2186 parse_attr->num_mod_hdr_actions * action_size;
2187
2188 max_actions = parse_attr->max_mod_hdr_actions;
2189 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 2190
2191 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2192 bool skip;
2193
d79b6df6
OG		 2194 f = &fields[i];
2195 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2196 s_mask = 0;
2197 a_mask = 0;
d79b6df6
OG		 2198
2199 s_masks_p = (void *)set_masks + f->offset;
2200 a_masks_p = (void *)add_masks + f->offset;
2201
2202 memcpy(&s_mask, s_masks_p, f->size);
2203 memcpy(&a_mask, a_masks_p, f->size);
2204
2205 if (!s_mask && !a_mask) /* nothing to offload here */
2206 continue;
2207
2208 if (s_mask && a_mask) {
e98bedf5
EB		 2209 NL_SET_ERR_MSG_MOD(extack,
2210 "can't set and add to the same HW field");
d79b6df6
OG		 2211 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2212 return -EOPNOTSUPP;
2213 }
2214
2215 if (nactions == max_actions) {
e98bedf5
EB		 2216 NL_SET_ERR_MSG_MOD(extack,
2217 "too many pedit actions, can't offload");
d79b6df6
OG		 2218 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2219 return -EOPNOTSUPP;
2220 }
2221
27c11b6b 2222 skip = false;
d79b6df6 2223 if (s_mask) {
27c11b6b
EB		 2224 void *match_mask = headers_c + f->match_offset;
2225 void *match_val = headers_v + f->match_offset;
2226
d79b6df6
OG		 2227 cmd = MLX5_ACTION_TYPE_SET;
2228 mask = s_mask;
2229 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2230 /* don't rewrite if we have a match on the same value */
2231 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2232 match_mask, f->size))
2233 skip = true;
d79b6df6
OG		 2234 /* clear to denote we consumed this field */
2235 memset(s_masks_p, 0, f->size);
2236 } else {
27c11b6b
EB		 2237 u32 zero = 0;
2238
d79b6df6
OG		 2239 cmd = MLX5_ACTION_TYPE_ADD;
2240 mask = a_mask;
2241 vals_p = (void *)add_vals + f->offset;
27c11b6b
EB		 2242 /* add 0 is no change */
2243 if (!memcmp(vals_p, &zero, f->size))
2244 skip = true;
d79b6df6
OG		 2245 /* clear to denote we consumed this field */
2246 memset(a_masks_p, 0, f->size);
2247 }
27c11b6b
EB		 2248 if (skip)
2249 continue;
d79b6df6 2250
d79b6df6 2251 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 2252
2b64beba
OG		 2253 if (field_bsize == 32) {
2254 mask_be32 = *(__be32 *)&mask;
2255 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2256 } else if (field_bsize == 16) {
2257 mask_be16 = *(__be16 *)&mask;
2258 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2259 }
2260
d79b6df6 2261 first = find_first_bit(&mask, field_bsize);
2b64beba 2262 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 2263 last = find_last_bit(&mask, field_bsize);
2b64beba 2264 if (first < next_z && next_z < last) {
e98bedf5
EB		 2265 NL_SET_ERR_MSG_MOD(extack,
2266 "rewrite of few sub-fields isn't supported");
2b64beba 2267 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2268 mask);
2269 return -EOPNOTSUPP;
2270 }
2271
2272 MLX5_SET(set_action_in, action, action_type, cmd);
2273 MLX5_SET(set_action_in, action, field, f->field);
2274
2275 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2276 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2277 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2278 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2279 }
2280
2281 if (field_bsize == 32)
2b64beba 2282 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2283 else if (field_bsize == 16)
2b64beba 2284 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2285 else if (field_bsize == 8)
2b64beba 2286 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2287
2288 action += action_size;
2289 nactions++;
2290 }
2291
2292 parse_attr->num_mod_hdr_actions = nactions;
2293 return 0;
2294}
2295
2cc1cb1d
TZ		 2296static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2297 int namespace)
2298{
2299 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2300 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2301 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2302 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2303}
2304
d79b6df6 2305static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2306 struct pedit_headers_action *hdrs,
2307 int namespace,
d79b6df6
OG		 2308 struct mlx5e_tc_flow_parse_attr *parse_attr)
2309{
2310 int nkeys, action_size, max_actions;
2311
c500c86b
PNA		 2312 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2313 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2314 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2315
2cc1cb1d 2316 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
d79b6df6
OG		 2317 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2318 max_actions = min(max_actions, nkeys * 16);
2319
2320 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2321 if (!parse_attr->mod_hdr_actions)
2322 return -ENOMEM;
2323
218d05ce 2324 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2325 return 0;
2326}
2327
2328static const struct pedit_headers zero_masks = {};
2329
2330static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2331 const struct flow_action_entry *act, int namespace,
e98bedf5 2332 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2333 struct pedit_headers_action *hdrs,
e98bedf5 2334 struct netlink_ext_ack *extack)
d79b6df6 2335{
73867881
PNA		 2336 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2337 int err = -EOPNOTSUPP;
d79b6df6 2338 u32 mask, val, offset;
73867881 2339 u8 htype;
d79b6df6 2340
73867881
PNA		 2341 htype = act->mangle.htype;
2342 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2343
73867881
PNA		 2344 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2345 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2346 goto out_err;
2347 }
d79b6df6 2348
2cc1cb1d
TZ		 2349 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2350 NL_SET_ERR_MSG_MOD(extack,
2351 "The pedit offload action is not supported");
2352 goto out_err;
2353 }
2354
73867881
PNA		 2355 mask = act->mangle.mask;
2356 val = act->mangle.val;
2357 offset = act->mangle.offset;
d79b6df6 2358
73867881
PNA		 2359 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2360 if (err)
2361 goto out_err;
c500c86b 2362
73867881 2363 hdrs[cmd].pedits++;
d79b6df6 2364
c500c86b
PNA		 2365 return 0;
2366out_err:
2367 return err;
2368}
2369
2370static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2371 struct mlx5e_tc_flow_parse_attr *parse_attr,
2372 struct pedit_headers_action *hdrs,
27c11b6b 2373 u32 *action_flags,
c500c86b
PNA		 2374 struct netlink_ext_ack *extack)
2375{
2376 struct pedit_headers *cmd_masks;
2377 int err;
2378 u8 cmd;
2379
218d05ce 2380 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2381 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2382 if (err)
2383 goto out_err;
2384 }
d79b6df6 2385
27c11b6b 2386 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
d79b6df6
OG		 2387 if (err < 0)
2388 goto out_dealloc_parsed_actions;
2389
2390 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2391 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2392 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2393 NL_SET_ERR_MSG_MOD(extack,
2394 "attempt to offload an unsupported field");
b3a433de 2395 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2396 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2397 16, 1, cmd_masks, sizeof(zero_masks), true);
2398 err = -EOPNOTSUPP;
2399 goto out_dealloc_parsed_actions;
2400 }
2401 }
2402
2403 return 0;
2404
2405out_dealloc_parsed_actions:
2406 kfree(parse_attr->mod_hdr_actions);
2407out_err:
2408 return err;
2409}
2410
e98bedf5
EB		 2411static bool csum_offload_supported(struct mlx5e_priv *priv,
2412 u32 action,
2413 u32 update_flags,
2414 struct netlink_ext_ack *extack)
26c02749
OG		 2415{
2416 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2417 TCA_CSUM_UPDATE_FLAG_UDP;
2418
2419 /* The HW recalcs checksums only if re-writing headers */
2420 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2421 NL_SET_ERR_MSG_MOD(extack,
2422 "TC csum action is only offloaded with pedit");
26c02749
OG		 2423 netdev_warn(priv->netdev,
2424 "TC csum action is only offloaded with pedit\n");
2425 return false;
2426 }
2427
2428 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2429 NL_SET_ERR_MSG_MOD(extack,
2430 "can't offload TC csum action for some header/s");
26c02749
OG		 2431 netdev_warn(priv->netdev,
2432 "can't offload TC csum action for some header/s - flags %#x\n",
2433 update_flags);
2434 return false;
2435 }
2436
2437 return true;
2438}
2439
8998576b
DL		 2440struct ip_ttl_word {
2441 __u8 ttl;
2442 __u8 protocol;
2443 __sum16 check;
2444};
2445
2446struct ipv6_hoplimit_word {
2447 __be16 payload_len;
2448 __u8 nexthdr;
2449 __u8 hop_limit;
2450};
2451
2452static bool is_action_keys_supported(const struct flow_action_entry *act)
2453{
2454 u32 mask, offset;
2455 u8 htype;
2456
2457 htype = act->mangle.htype;
2458 offset = act->mangle.offset;
2459 mask = ~act->mangle.mask;
2460 /* For IPv4 & IPv6 header check 4 byte word,
2461 * to determine that modified fields
2462 * are NOT ttl & hop_limit only.
2463 */
2464 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2465 struct ip_ttl_word *ttl_word =
2466 (struct ip_ttl_word *)&mask;
2467
2468 if (offset != offsetof(struct iphdr, ttl) ||
2469 ttl_word->protocol ||
2470 ttl_word->check) {
2471 return true;
2472 }
2473 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2474 struct ipv6_hoplimit_word *hoplimit_word =
2475 (struct ipv6_hoplimit_word *)&mask;
2476
2477 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2478 hoplimit_word->payload_len ||
2479 hoplimit_word->nexthdr) {
2480 return true;
2481 }
2482 }
2483 return false;
2484}
2485
bdd66ac0 2486static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2487 struct flow_action *flow_action,
1651925d 2488 u32 actions,
e98bedf5 2489 struct netlink_ext_ack *extack)
bdd66ac0 2490{
73867881 2491 const struct flow_action_entry *act;
bdd66ac0 2492 bool modify_ip_header;
bdd66ac0
OG		 2493 void *headers_v;
2494 u16 ethertype;
8998576b 2495 u8 ip_proto;
73867881 2496 int i;
bdd66ac0 2497
8377629e 2498 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2499 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2500
2501 /* for non-IP we only re-write MACs, so we're okay */
2502 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2503 goto out_ok;
2504
2505 modify_ip_header = false;
73867881
PNA		 2506 flow_action_for_each(i, act, flow_action) {
2507 if (act->id != FLOW_ACTION_MANGLE &&
2508 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2509 continue;
2510
8998576b 2511 if (is_action_keys_supported(act)) {
73867881
PNA		 2512 modify_ip_header = true;
2513 break;
bdd66ac0
OG		 2514 }
2515 }
2516
2517 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2518 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2519 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2520 NL_SET_ERR_MSG_MOD(extack,
2521 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2522 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2523 return false;
2524 }
2525
2526out_ok:
2527 return true;
2528}
2529
2530static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2531 struct flow_action *flow_action,
bdd66ac0 2532 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2533 struct mlx5e_tc_flow *flow,
2534 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2535{
2536 u32 actions;
2537
226f2ca3 2538 if (mlx5e_is_eswitch_flow(flow))
bdd66ac0
OG		 2539 actions = flow->esw_attr->action;
2540 else
2541 actions = flow->nic_attr->action;
2542
226f2ca3 2543 if (flow_flag_test(flow, EGRESS) &&
35a605db 2544 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
6830b468
TZ		 2545 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2546 (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
7e29392e
RD		 2547 return false;
2548
bdd66ac0 2549 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2550 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2551 flow_action, actions,
e98bedf5 2552 extack);
bdd66ac0
OG		 2553
2554 return true;
2555}
2556
5c65c564
OG		 2557static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2558{
2559 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2560 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2561
2562 fmdev = priv->mdev;
2563 pmdev = peer_priv->mdev;
2564
59c9d35e
AH		 2565 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2566 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2567
816f6706 2568 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2569}
2570
bdc837ee
EB		 2571static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2572 const struct flow_action_entry *act,
2573 struct mlx5e_tc_flow_parse_attr *parse_attr,
2574 struct pedit_headers_action *hdrs,
2575 u32 *action, struct netlink_ext_ack *extack)
2576{
2577 u16 mask16 = VLAN_VID_MASK;
2578 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2579 const struct flow_action_entry pedit_act = {
2580 .id = FLOW_ACTION_MANGLE,
2581 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2582 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2583 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2584 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2585 };
6fca9d1e 2586 u8 match_prio_mask, match_prio_val;
bf2f3bca 2587 void *headers_c, *headers_v;
bdc837ee
EB		 2588 int err;
2589
bf2f3bca
EB		 2590 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2591 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2592
2593 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2594 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2595 NL_SET_ERR_MSG_MOD(extack,
2596 "VLAN rewrite action must have VLAN protocol match");
2597 return -EOPNOTSUPP;
2598 }
2599
6fca9d1e
EB		 2600 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2601 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2602 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2603 NL_SET_ERR_MSG_MOD(extack,
2604 "Changing VLAN prio is not supported");
bdc837ee
EB		 2605 return -EOPNOTSUPP;
2606 }
2607
2608 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2609 hdrs, NULL);
2610 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2611
2612 return err;
2613}
2614
0bac1194
EB		 2615static int
2616add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2617 struct mlx5e_tc_flow_parse_attr *parse_attr,
2618 struct pedit_headers_action *hdrs,
2619 u32 *action, struct netlink_ext_ack *extack)
2620{
2621 const struct flow_action_entry prio_tag_act = {
2622 .vlan.vid = 0,
2623 .vlan.prio =
2624 MLX5_GET(fte_match_set_lyr_2_4,
2625 get_match_headers_value(*action,
2626 &parse_attr->spec),
2627 first_prio) &
2628 MLX5_GET(fte_match_set_lyr_2_4,
2629 get_match_headers_criteria(*action,
2630 &parse_attr->spec),
2631 first_prio),
2632 };
2633
2634 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2635 &prio_tag_act, parse_attr, hdrs, action,
2636 extack);
2637}
2638
73867881
PNA		 2639static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2640 struct flow_action *flow_action,
aa0cbbae 2641 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2642 struct mlx5e_tc_flow *flow,
2643 struct netlink_ext_ack *extack)
e3a2b7ed 2644{
aa0cbbae 2645 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2646 struct pedit_headers_action hdrs[2] = {};
2647 const struct flow_action_entry *act;
1cab1cd7 2648 u32 action = 0;
244cd96a 2649 int err, i;
e3a2b7ed 2650
73867881 2651 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2652 return -EINVAL;
2653
3bc4b7bf 2654 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2655
73867881
PNA		 2656 flow_action_for_each(i, act, flow_action) {
2657 switch (act->id) {
2658 case FLOW_ACTION_DROP:
1cab1cd7 2659 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2660 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2661 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2662 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2663 break;
2664 case FLOW_ACTION_MANGLE:
2665 case FLOW_ACTION_ADD:
2666 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2667 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2668 if (err)
2669 return err;
2670
1cab1cd7
OG		 2671 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2672 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2673 break;
bdc837ee
EB		 2674 case FLOW_ACTION_VLAN_MANGLE:
2675 err = add_vlan_rewrite_action(priv,
2676 MLX5_FLOW_NAMESPACE_KERNEL,
2677 act, parse_attr, hdrs,
2678 &action, extack);
2679 if (err)
2680 return err;
2681
2682 break;
73867881 2683 case FLOW_ACTION_CSUM:
1cab1cd7 2684 if (csum_offload_supported(priv, action,
73867881 2685 act->csum_flags,
e98bedf5 2686 extack))
73867881 2687 break;
26c02749
OG		 2688
2689 return -EOPNOTSUPP;
73867881
PNA		 2690 case FLOW_ACTION_REDIRECT: {
2691 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2692
2693 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2694 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2695 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 2696 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 2697 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2698 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2699 } else {
e98bedf5
EB		 2700 NL_SET_ERR_MSG_MOD(extack,
2701 "device is not on same HW, can't offload");
5c65c564
OG		 2702 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2703 peer_dev->name);
2704 return -EINVAL;
2705 }
73867881
PNA		 2706 }
2707 break;
2708 case FLOW_ACTION_MARK: {
2709 u32 mark = act->mark;
e3a2b7ed
AV		 2710
2711 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2712 NL_SET_ERR_MSG_MOD(extack,
2713 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2714 return -EINVAL;
2715 }
2716
3bc4b7bf 2717 attr->flow_tag = mark;
1cab1cd7 2718 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2719 }
2720 break;
2721 default:
2cc1cb1d
TZ		 2722 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2723 return -EOPNOTSUPP;
e3a2b7ed 2724 }
e3a2b7ed
AV		 2725 }
2726
c500c86b
PNA		 2727 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2728 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2729 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 2730 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2731 if (err)
2732 return err;
27c11b6b
EB		 2733 /* in case all pedit actions are skipped, remove the MOD_HDR
2734 * flag.
2735 */
e7739a60 2736 if (parse_attr->num_mod_hdr_actions == 0) {
27c11b6b 2737 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60
EB		 2738 kfree(parse_attr->mod_hdr_actions);
2739 }
c500c86b
PNA		 2740 }
2741
1cab1cd7 2742 attr->action = action;
73867881 2743 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2744 return -EOPNOTSUPP;
2745
e3a2b7ed
AV		 2746 return 0;
2747}
2748
7f1a546e 2749struct encap_key {
1f6da306 2750 const struct ip_tunnel_key *ip_tun_key;
d386939a 2751 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 2752};
2753
2754static inline int cmp_encap_info(struct encap_key *a,
2755 struct encap_key *b)
a54e20b4 2756{
7f1a546e 2757 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 2758 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 2759}
2760
7f1a546e 2761static inline int hash_encap_info(struct encap_key *key)
a54e20b4 2762{
7f1a546e 2763 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 2764 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 2765}
2766
a54e20b4 2767
b1d90e6b
RL		 2768static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2769 struct net_device *peer_netdev)
2770{
2771 struct mlx5e_priv *peer_priv;
2772
2773 peer_priv = netdev_priv(peer_netdev);
2774
2775 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 2776 mlx5e_eswitch_rep(priv->netdev) &&
2777 mlx5e_eswitch_rep(peer_netdev) &&
2778 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 2779}
2780
32f3671f 2781
f5bc2c5d 2782
a54e20b4 2783static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 2784 struct mlx5e_tc_flow *flow,
733d4f36
RD		 2785 struct net_device *mirred_dev,
2786 int out_index,
8c4dc42b 2787 struct netlink_ext_ack *extack,
0ad060ee
RD		 2788 struct net_device **encap_dev,
2789 bool *encap_valid)
a54e20b4
HHZ		 2790{
2791 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 2792 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 2793 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 2794 const struct ip_tunnel_info *tun_info;
7f1a546e 2795 struct encap_key key, e_key;
c1ae1152 2796 struct mlx5e_encap_entry *e;
733d4f36 2797 unsigned short family;
a54e20b4
HHZ		 2798 uintptr_t hash_key;
2799 bool found = false;
54c177ca 2800 int err = 0;
a54e20b4 2801
733d4f36 2802 parse_attr = attr->parse_attr;
1f6da306 2803 tun_info = parse_attr->tun_info[out_index];
733d4f36 2804 family = ip_tunnel_info_af(tun_info);
7f1a546e 2805 key.ip_tun_key = &tun_info->key;
d386939a 2806 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 2807 if (!key.tc_tunnel) {
2808 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
2809 return -EOPNOTSUPP;
2810 }
733d4f36 2811
7f1a546e 2812 hash_key = hash_encap_info(&key);
a54e20b4
HHZ		 2813
2814 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2815 encap_hlist, hash_key) {
1f6da306 2816 e_key.ip_tun_key = &e->tun_info->key;
d386939a 2817 e_key.tc_tunnel = e->tunnel;
7f1a546e 2818 if (!cmp_encap_info(&e_key, &key)) {
a54e20b4
HHZ		 2819 found = true;
2820 break;
2821 }
2822 }
2823
b2812089 2824 /* must verify if encap is valid or not */
45247bf2
OG		 2825 if (found)
2826 goto attach_flow;
a54e20b4
HHZ		 2827
2828 e = kzalloc(sizeof(*e), GFP_KERNEL);
2829 if (!e)
2830 return -ENOMEM;
2831
1f6da306 2832 e->tun_info = tun_info;
101f4de9 2833 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2834 if (err)
2835 goto out_err;
2836
a54e20b4
HHZ		 2837 INIT_LIST_HEAD(&e->flows);
2838
ce99f6b9 2839 if (family == AF_INET)
101f4de9 2840 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2841 else if (family == AF_INET6)
101f4de9 2842 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2843
0ad060ee 2844 if (err)
a54e20b4
HHZ		 2845 goto out_err;
2846
a54e20b4
HHZ		 2847 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2848
45247bf2 2849attach_flow:
8c4dc42b
EB		 2850 list_add(&flow->encaps[out_index].list, &e->flows);
2851 flow->encaps[out_index].index = out_index;
45247bf2 2852 *encap_dev = e->out_dev;
8c4dc42b
EB		 2853 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2854 attr->dests[out_index].encap_id = e->encap_id;
2855 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 2856 *encap_valid = true;
8c4dc42b 2857 } else {
0ad060ee 2858 *encap_valid = false;
8c4dc42b 2859 }
45247bf2 2860
232c0013 2861 return err;
a54e20b4
HHZ		 2862
2863out_err:
2864 kfree(e);
2865 return err;
2866}
2867
1482bd3d 2868static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 2869 const struct flow_action_entry *act,
1482bd3d
JL		 2870 struct mlx5_esw_flow_attr *attr,
2871 u32 *action)
2872{
cc495188
JL		 2873 u8 vlan_idx = attr->total_vlan;
2874
2875 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2876 return -EOPNOTSUPP;
2877
73867881
PNA		 2878 switch (act->id) {
2879 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 2880 if (vlan_idx) {
2881 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2882 MLX5_FS_VLAN_DEPTH))
2883 return -EOPNOTSUPP;
2884
2885 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2886 } else {
2887 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2888 }
73867881
PNA		 2889 break;
2890 case FLOW_ACTION_VLAN_PUSH:
2891 attr->vlan_vid[vlan_idx] = act->vlan.vid;
2892 attr->vlan_prio[vlan_idx] = act->vlan.prio;
2893 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 2894 if (!attr->vlan_proto[vlan_idx])
2895 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2896
2897 if (vlan_idx) {
2898 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2899 MLX5_FS_VLAN_DEPTH))
2900 return -EOPNOTSUPP;
2901
2902 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2903 } else {
2904 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 2905 (act->vlan.proto != htons(ETH_P_8021Q) ||
2906 act->vlan.prio))
cc495188
JL		 2907 return -EOPNOTSUPP;
2908
2909 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 2910 }
73867881
PNA		 2911 break;
2912 default:
bdc837ee 2913 return -EINVAL;
1482bd3d
JL		 2914 }
2915
cc495188
JL		 2916 attr->total_vlan = vlan_idx + 1;
2917
1482bd3d
JL		 2918 return 0;
2919}
2920
278748a9
EB		 2921static int add_vlan_push_action(struct mlx5e_priv *priv,
2922 struct mlx5_esw_flow_attr *attr,
2923 struct net_device **out_dev,
2924 u32 *action)
2925{
2926 struct net_device *vlan_dev = *out_dev;
2927 struct flow_action_entry vlan_act = {
2928 .id = FLOW_ACTION_VLAN_PUSH,
2929 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
2930 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
2931 .vlan.prio = 0,
2932 };
2933 int err;
2934
2935 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2936 if (err)
2937 return err;
2938
2939 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
2940 dev_get_iflink(vlan_dev));
2941 if (is_vlan_dev(*out_dev))
2942 err = add_vlan_push_action(priv, attr, out_dev, action);
2943
2944 return err;
2945}
2946
35a605db
EB		 2947static int add_vlan_pop_action(struct mlx5e_priv *priv,
2948 struct mlx5_esw_flow_attr *attr,
2949 u32 *action)
2950{
2951 int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev);
2952 struct flow_action_entry vlan_act = {
2953 .id = FLOW_ACTION_VLAN_POP,
2954 };
2955 int err = 0;
2956
2957 while (nest_level--) {
2958 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2959 if (err)
2960 return err;
2961 }
2962
2963 return err;
2964}
2965
f6dc1264
PB		 2966bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
2967 struct net_device *out_dev)
2968{
2969 if (is_merged_eswitch_dev(priv, out_dev))
2970 return true;
2971
2972 return mlx5e_eswitch_rep(out_dev) &&
2973 same_hw_devs(priv, netdev_priv(out_dev));
2974}
2975
73867881
PNA		 2976static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
2977 struct flow_action *flow_action,
e98bedf5
EB		 2978 struct mlx5e_tc_flow *flow,
2979 struct netlink_ext_ack *extack)
03a9d11e 2980{
73867881 2981 struct pedit_headers_action hdrs[2] = {};
bf07aa73 2982 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2983 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 2984 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 2985 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881
PNA		 2986 const struct ip_tunnel_info *info = NULL;
2987 const struct flow_action_entry *act;
a54e20b4 2988 bool encap = false;
1cab1cd7 2989 u32 action = 0;
244cd96a 2990 int err, i;
03a9d11e 2991
73867881 2992 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 2993 return -EINVAL;
2994
73867881
PNA		 2995 flow_action_for_each(i, act, flow_action) {
2996 switch (act->id) {
2997 case FLOW_ACTION_DROP:
1cab1cd7
OG		 2998 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2999 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3000 break;
3001 case FLOW_ACTION_MANGLE:
3002 case FLOW_ACTION_ADD:
3003 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 3004 parse_attr, hdrs, extack);
d7e75a32
OG		 3005 if (err)
3006 return err;
3007
1cab1cd7 3008 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 3009 attr->split_count = attr->out_count;
73867881
PNA		 3010 break;
3011 case FLOW_ACTION_CSUM:
1cab1cd7 3012 if (csum_offload_supported(priv, action,
73867881
PNA		 3013 act->csum_flags, extack))
3014 break;
26c02749
OG		 3015
3016 return -EOPNOTSUPP;
73867881
PNA		 3017 case FLOW_ACTION_REDIRECT:
3018 case FLOW_ACTION_MIRRED: {
03a9d11e 3019 struct mlx5e_priv *out_priv;
592d3651 3020 struct net_device *out_dev;
03a9d11e 3021
73867881 3022 out_dev = act->dev;
ef381359
OS		 3023 if (!out_dev) {
3024 /* out_dev is NULL when filters with
3025 * non-existing mirred device are replayed to
3026 * the driver.
3027 */
3028 return -EINVAL;
3029 }
03a9d11e 3030
592d3651 3031 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3032 NL_SET_ERR_MSG_MOD(extack,
3033 "can't support more output ports, can't offload forwarding");
592d3651
CM		 3034 pr_err("can't support more than %d output ports, can't offload forwarding\n",
3035 attr->out_count);
3036 return -EOPNOTSUPP;
3037 }
3038
f493f155
EB		 3039 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3040 MLX5_FLOW_CONTEXT_ACTION_COUNT;
f6dc1264 3041 if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3042 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3043 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
fa833bd5 3044 struct net_device *uplink_upper;
7ba58ba7 3045
fa833bd5
VB		 3046 rcu_read_lock();
3047 uplink_upper =
3048 netdev_master_upper_dev_get_rcu(uplink_dev);
7ba58ba7
RL		 3049 if (uplink_upper &&
3050 netif_is_lag_master(uplink_upper) &&
3051 uplink_upper == out_dev)
3052 out_dev = uplink_dev;
fa833bd5 3053 rcu_read_unlock();
7ba58ba7 3054
278748a9
EB		 3055 if (is_vlan_dev(out_dev)) {
3056 err = add_vlan_push_action(priv, attr,
3057 &out_dev,
3058 &action);
3059 if (err)
3060 return err;
3061 }
f6dc1264 3062
35a605db
EB		 3063 if (is_vlan_dev(parse_attr->filter_dev)) {
3064 err = add_vlan_pop_action(priv, attr,
3065 &action);
3066 if (err)
3067 return err;
3068 }
278748a9 3069
f6dc1264
PB		 3070 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3071 NL_SET_ERR_MSG_MOD(extack,
3072 "devices are not on same switch HW, can't offload forwarding");
3073 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3074 priv->netdev->name, out_dev->name);
a0646c88 3075 return -EOPNOTSUPP;
f6dc1264 3076 }
a0646c88 3077
a54e20b4 3078 out_priv = netdev_priv(out_dev);
1d447a39 3079 rpriv = out_priv->ppriv;
df65a573
EB		 3080 attr->dests[attr->out_count].rep = rpriv->rep;
3081 attr->dests[attr->out_count].mdev = out_priv->mdev;
3082 attr->out_count++;
a54e20b4 3083 } else if (encap) {
8c4dc42b
EB		 3084 parse_attr->mirred_ifindex[attr->out_count] =
3085 out_dev->ifindex;
1f6da306 3086 parse_attr->tun_info[attr->out_count] = info;
8c4dc42b 3087 encap = false;
f493f155
EB		 3088 attr->dests[attr->out_count].flags |=
3089 MLX5_ESW_DEST_ENCAP;
1cc26d74 3090 attr->out_count++;
df65a573
EB		 3091 /* attr->dests[].rep is resolved when we
3092 * handle encap
3093 */
ef381359
OS		 3094 } else if (parse_attr->filter_dev != priv->netdev) {
3095 /* All mlx5 devices are called to configure
3096 * high level device filters. Therefore, the
3097 * *attempt* to install a filter on invalid
3098 * eswitch should not trigger an explicit error
3099 */
3100 return -EINVAL;
a54e20b4 3101 } else {
e98bedf5
EB		 3102 NL_SET_ERR_MSG_MOD(extack,
3103 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 3104 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3105 priv->netdev->name, out_dev->name);
3106 return -EINVAL;
3107 }
73867881
PNA		 3108 }
3109 break;
3110 case FLOW_ACTION_TUNNEL_ENCAP:
3111 info = act->tunnel;
a54e20b4
HHZ		 3112 if (info)
3113 encap = true;
3114 else
3115 return -EOPNOTSUPP;
1482bd3d 3116
73867881
PNA		 3117 break;
3118 case FLOW_ACTION_VLAN_PUSH:
3119 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3120 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3121 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3122 /* Replace vlan pop+push with vlan modify */
3123 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3124 err = add_vlan_rewrite_action(priv,
3125 MLX5_FLOW_NAMESPACE_FDB,
3126 act, parse_attr, hdrs,
3127 &action, extack);
3128 } else {
3129 err = parse_tc_vlan_action(priv, act, attr, &action);
3130 }
1482bd3d
JL		 3131 if (err)
3132 return err;
3133
bdc837ee
EB		 3134 attr->split_count = attr->out_count;
3135 break;
3136 case FLOW_ACTION_VLAN_MANGLE:
3137 err = add_vlan_rewrite_action(priv,
3138 MLX5_FLOW_NAMESPACE_FDB,
3139 act, parse_attr, hdrs,
3140 &action, extack);
3141 if (err)
3142 return err;
3143
e85e02ba 3144 attr->split_count = attr->out_count;
73867881
PNA		 3145 break;
3146 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 3147 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 3148 break;
3149 case FLOW_ACTION_GOTO: {
3150 u32 dest_chain = act->chain_index;
bf07aa73
PB		 3151 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
3152
3153 if (dest_chain <= attr->chain) {
3154 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
3155 return -EOPNOTSUPP;
3156 }
3157 if (dest_chain > max_chain) {
3158 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
3159 return -EOPNOTSUPP;
3160 }
e88afe75 3161 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 3162 attr->dest_chain = dest_chain;
73867881
PNA		 3163 break;
3164 }
3165 default:
2cc1cb1d
TZ		 3166 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3167 return -EOPNOTSUPP;
bf07aa73 3168 }
03a9d11e 3169 }
bdd66ac0 3170
0bac1194
EB		 3171 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3172 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3173 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3174 * tag rewrite.
3175 */
3176 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3177 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3178 &action, extack);
3179 if (err)
3180 return err;
3181 }
3182
c500c86b
PNA		 3183 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3184 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3185 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3186 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3187 if (err)
3188 return err;
27c11b6b
EB		 3189 /* in case all pedit actions are skipped, remove the MOD_HDR
3190 * flag. we might have set split_count either by pedit or
3191 * pop/push. if there is no pop/push either, reset it too.
3192 */
3193 if (parse_attr->num_mod_hdr_actions == 0) {
3194 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60 3195 kfree(parse_attr->mod_hdr_actions);
27c11b6b
EB		 3196 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3197 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3198 attr->split_count = 0;
3199 }
c500c86b
PNA		 3200 }
3201
1cab1cd7 3202 attr->action = action;
73867881 3203 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3204 return -EOPNOTSUPP;
3205
e88afe75
OG		 3206 if (attr->dest_chain) {
3207 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3208 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3209 return -EOPNOTSUPP;
3210 }
3211 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3212 }
3213
e85e02ba 3214 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3215 NL_SET_ERR_MSG_MOD(extack,
3216 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3217 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3218 return -EOPNOTSUPP;
3219 }
3220
31c8eba5 3221 return 0;
03a9d11e
OG		 3222}
3223
226f2ca3 3224static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3225{
226f2ca3 3226 unsigned long __flow_flags = 0;
60bd4af8 3227
226f2ca3
VB		 3228 if (flags & MLX5_TC_FLAG(INGRESS))
3229 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3230 if (flags & MLX5_TC_FLAG(EGRESS))
3231 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3232
226f2ca3
VB		 3233 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3234 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3235 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3236 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
d9ee0491 3237
60bd4af8
OG		 3238 *flow_flags = __flow_flags;
3239}
3240
05866c82
OG		 3241static const struct rhashtable_params tc_ht_params = {
3242 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3243 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3244 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3245 .automatic_shrinking = true,
3246};
3247
226f2ca3
VB		 3248static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3249 unsigned long flags)
05866c82 3250{
655dc3d2
OG		 3251 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3252 struct mlx5e_rep_priv *uplink_rpriv;
3253
226f2ca3 3254 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3255 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3256 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3257 } else /* NIC offload */
655dc3d2 3258 return &priv->fs.tc.ht;
05866c82
OG		 3259}
3260
04de7dda
RD		 3261static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3262{
1418ddd9 3263 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 3264 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3265 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3266 bool act_is_encap = !!(attr->action &
3267 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3268 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3269 MLX5_DEVCOM_ESW_OFFLOADS);
3270
10fbb1cd
RD		 3271 if (!esw_paired)
3272 return false;
3273
3274 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3275 mlx5_lag_is_multipath(attr->in_mdev)) &&
3276 (is_rep_ingress || act_is_encap))
3277 return true;
3278
3279 return false;
04de7dda
RD		 3280}
3281
a88780a9
RD		 3282static int
3283mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3284 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3285 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3286 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3287{
17091853 3288 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3289 struct mlx5e_tc_flow *flow;
5a7e5bcb 3290 int out_index, err;
e3a2b7ed 3291
65ba8fb7 3292 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3293 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3294 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3295 err = -ENOMEM;
3296 goto err_free;
3297 }
3298
3299 flow->cookie = f->cookie;
65ba8fb7 3300 flow->flags = flow_flags;
655dc3d2 3301 flow->priv = priv;
5a7e5bcb
VB		 3302 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3303 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3304 INIT_LIST_HEAD(&flow->mod_hdr);
3305 INIT_LIST_HEAD(&flow->hairpin);
3306 refcount_set(&flow->refcnt, 1);
e3a2b7ed 3307
a88780a9
RD		 3308 *__flow = flow;
3309 *__parse_attr = parse_attr;
3310
3311 return 0;
3312
3313err_free:
3314 kfree(flow);
3315 kvfree(parse_attr);
3316 return err;
3317}
3318
988ab9c7
TZ		 3319static void
3320mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3321 struct mlx5e_priv *priv,
3322 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3323 struct flow_cls_offload *f,
988ab9c7
TZ		 3324 struct mlx5_eswitch_rep *in_rep,
3325 struct mlx5_core_dev *in_mdev)
3326{
3327 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3328
3329 esw_attr->parse_attr = parse_attr;
3330 esw_attr->chain = f->common.chain_index;
3331 esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
3332
3333 esw_attr->in_rep = in_rep;
3334 esw_attr->in_mdev = in_mdev;
3335
3336 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3337 MLX5_COUNTER_SOURCE_ESWITCH)
3338 esw_attr->counter_dev = in_mdev;
3339 else
3340 esw_attr->counter_dev = priv->mdev;
3341}
3342
71129676 3343static struct mlx5e_tc_flow *
04de7dda 3344__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3345 struct flow_cls_offload *f,
226f2ca3 3346 unsigned long flow_flags,
04de7dda
RD		 3347 struct net_device *filter_dev,
3348 struct mlx5_eswitch_rep *in_rep,
71129676 3349 struct mlx5_core_dev *in_mdev)
a88780a9 3350{
f9e30088 3351 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3352 struct netlink_ext_ack *extack = f->common.extack;
3353 struct mlx5e_tc_flow_parse_attr *parse_attr;
3354 struct mlx5e_tc_flow *flow;
3355 int attr_size, err;
e3a2b7ed 3356
226f2ca3 3357 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3358 attr_size = sizeof(struct mlx5_esw_flow_attr);
3359 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3360 &parse_attr, &flow);
3361 if (err)
3362 goto out;
988ab9c7 3363
d11afc26 3364 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 3365 mlx5e_flow_esw_attr_init(flow->esw_attr,
3366 priv, parse_attr,
3367 f, in_rep, in_mdev);
3368
54c177ca
OS		 3369 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3370 f, filter_dev);
d11afc26
OS		 3371 if (err)
3372 goto err_free;
a88780a9 3373
6f9af8ff 3374 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3375 if (err)
3376 goto err_free;
3377
7040632d 3378 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
ef06c9ee
RD		 3379 if (err) {
3380 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3381 goto err_free;
3382
b4a23329 3383 add_unready_flow(flow);
ef06c9ee 3384 }
e3a2b7ed 3385
71129676 3386 return flow;
a88780a9
RD		 3387
3388err_free:
5a7e5bcb 3389 mlx5e_flow_put(priv, flow);
a88780a9 3390out:
71129676 3391 return ERR_PTR(err);
a88780a9
RD		 3392}
3393
f9e30088 3394static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3395 struct mlx5e_tc_flow *flow,
226f2ca3 3396 unsigned long flow_flags)
04de7dda
RD		 3397{
3398 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3399 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3400 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3401 struct mlx5e_tc_flow_parse_attr *parse_attr;
3402 struct mlx5e_rep_priv *peer_urpriv;
3403 struct mlx5e_tc_flow *peer_flow;
3404 struct mlx5_core_dev *in_mdev;
3405 int err = 0;
3406
3407 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3408 if (!peer_esw)
3409 return -ENODEV;
3410
3411 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3412 peer_priv = netdev_priv(peer_urpriv->netdev);
3413
3414 /* in_mdev is assigned of which the packet originated from.
3415 * So packets redirected to uplink use the same mdev of the
3416 * original flow and packets redirected from uplink use the
3417 * peer mdev.
3418 */
b05af6aa 3419 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3420 in_mdev = peer_priv->mdev;
3421 else
3422 in_mdev = priv->mdev;
3423
3424 parse_attr = flow->esw_attr->parse_attr;
95dc1902 3425 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 3426 parse_attr->filter_dev,
3427 flow->esw_attr->in_rep, in_mdev);
3428 if (IS_ERR(peer_flow)) {
3429 err = PTR_ERR(peer_flow);
04de7dda 3430 goto out;
71129676 3431 }
04de7dda
RD		 3432
3433 flow->peer_flow = peer_flow;
226f2ca3 3434 flow_flag_set(flow, DUP);
04de7dda
RD		 3435 mutex_lock(&esw->offloads.peer_mutex);
3436 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3437 mutex_unlock(&esw->offloads.peer_mutex);
3438
3439out:
3440 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3441 return err;
3442}
3443
3444static int
3445mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3446 struct flow_cls_offload *f,
226f2ca3 3447 unsigned long flow_flags,
04de7dda
RD		 3448 struct net_device *filter_dev,
3449 struct mlx5e_tc_flow **__flow)
3450{
3451 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3452 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3453 struct mlx5_core_dev *in_mdev = priv->mdev;
3454 struct mlx5e_tc_flow *flow;
3455 int err;
3456
71129676
JG		 3457 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3458 in_mdev);
3459 if (IS_ERR(flow))
3460 return PTR_ERR(flow);
04de7dda
RD		 3461
3462 if (is_peer_flow_needed(flow)) {
95dc1902 3463 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3464 if (err) {
3465 mlx5e_tc_del_fdb_flow(priv, flow);
3466 goto out;
3467 }
3468 }
3469
3470 *__flow = flow;
3471
3472 return 0;
3473
3474out:
3475 return err;
3476}
3477
a88780a9
RD		 3478static int
3479mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3480 struct flow_cls_offload *f,
226f2ca3 3481 unsigned long flow_flags,
d11afc26 3482 struct net_device *filter_dev,
a88780a9
RD		 3483 struct mlx5e_tc_flow **__flow)
3484{
f9e30088 3485 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3486 struct netlink_ext_ack *extack = f->common.extack;
3487 struct mlx5e_tc_flow_parse_attr *parse_attr;
3488 struct mlx5e_tc_flow *flow;
3489 int attr_size, err;
3490
bf07aa73
PB		 3491 /* multi-chain not supported for NIC rules */
3492 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3493 return -EOPNOTSUPP;
3494
226f2ca3 3495 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3496 attr_size = sizeof(struct mlx5_nic_flow_attr);
3497 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3498 &parse_attr, &flow);
3499 if (err)
3500 goto out;
3501
d11afc26 3502 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3503 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3504 f, filter_dev);
d11afc26
OS		 3505 if (err)
3506 goto err_free;
3507
73867881 3508 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3509 if (err)
3510 goto err_free;
3511
3512 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3513 if (err)
3514 goto err_free;
3515
226f2ca3 3516 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3517 kvfree(parse_attr);
3518 *__flow = flow;
3519
3520 return 0;
e3a2b7ed 3521
e3a2b7ed 3522err_free:
5a7e5bcb 3523 mlx5e_flow_put(priv, flow);
17091853 3524 kvfree(parse_attr);
a88780a9
RD		 3525out:
3526 return err;
3527}
3528
3529static int
3530mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3531 struct flow_cls_offload *f,
226f2ca3 3532 unsigned long flags,
d11afc26 3533 struct net_device *filter_dev,
a88780a9
RD		 3534 struct mlx5e_tc_flow **flow)
3535{
3536 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3537 unsigned long flow_flags;
a88780a9
RD		 3538 int err;
3539
3540 get_flags(flags, &flow_flags);
3541
bf07aa73
PB		 3542 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3543 return -EOPNOTSUPP;
3544
f6455de0 3545 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3546 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3547 filter_dev, flow);
a88780a9 3548 else
d11afc26
OS		 3549 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3550 filter_dev, flow);
a88780a9
RD		 3551
3552 return err;
3553}
3554
71d82d2a 3555int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3556 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3557{
3558 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3559 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3560 struct mlx5e_tc_flow *flow;
3561 int err = 0;
3562
c5d326b2
VB		 3563 rcu_read_lock();
3564 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3565 rcu_read_unlock();
a88780a9
RD		 3566 if (flow) {
3567 NL_SET_ERR_MSG_MOD(extack,
3568 "flow cookie already exists, ignoring");
3569 netdev_warn_once(priv->netdev,
3570 "flow cookie %lx already exists, ignoring\n",
3571 f->cookie);
0e1c1a2f 3572 err = -EEXIST;
a88780a9
RD		 3573 goto out;
3574 }
3575
d11afc26 3576 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3577 if (err)
3578 goto out;
3579
c5d326b2 3580 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 3581 if (err)
3582 goto err_free;
3583
3584 return 0;
3585
3586err_free:
5a7e5bcb 3587 mlx5e_flow_put(priv, flow);
a88780a9 3588out:
e3a2b7ed
AV		 3589 return err;
3590}
3591
8f8ae895
OG		 3592static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3593{
226f2ca3
VB		 3594 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3595 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 3596
226f2ca3
VB		 3597 return flow_flag_test(flow, INGRESS) == dir_ingress &&
3598 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 3599}
3600
71d82d2a 3601int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3602 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 3603{
d9ee0491 3604 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3605 struct mlx5e_tc_flow *flow;
c5d326b2 3606 int err;
e3a2b7ed 3607
c5d326b2 3608 rcu_read_lock();
05866c82 3609 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 3610 if (!flow || !same_flow_direction(flow, flags)) {
3611 err = -EINVAL;
3612 goto errout;
3613 }
e3a2b7ed 3614
c5d326b2
VB		 3615 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3616 * set.
3617 */
3618 if (flow_flag_test_and_set(flow, DELETED)) {
3619 err = -EINVAL;
3620 goto errout;
3621 }
05866c82 3622 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 3623 rcu_read_unlock();
e3a2b7ed 3624
5a7e5bcb 3625 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 3626
3627 return 0;
c5d326b2
VB		 3628
3629errout:
3630 rcu_read_unlock();
3631 return err;
e3a2b7ed
AV		 3632}
3633
71d82d2a 3634int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3635 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 3636{
04de7dda 3637 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3638 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3639 struct mlx5_eswitch *peer_esw;
aad7e08d 3640 struct mlx5e_tc_flow *flow;
aad7e08d 3641 struct mlx5_fc *counter;
316d5f72
RD		 3642 u64 lastuse = 0;
3643 u64 packets = 0;
3644 u64 bytes = 0;
5a7e5bcb 3645 int err = 0;
aad7e08d 3646
c5d326b2
VB		 3647 rcu_read_lock();
3648 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
3649 tc_ht_params));
3650 rcu_read_unlock();
5a7e5bcb
VB		 3651 if (IS_ERR(flow))
3652 return PTR_ERR(flow);
3653
3654 if (!same_flow_direction(flow, flags)) {
3655 err = -EINVAL;
3656 goto errout;
3657 }
aad7e08d 3658
226f2ca3 3659 if (mlx5e_is_offloaded_flow(flow)) {
316d5f72
RD		 3660 counter = mlx5e_tc_get_counter(flow);
3661 if (!counter)
5a7e5bcb 3662 goto errout;
aad7e08d 3663
316d5f72
RD		 3664 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3665 }
aad7e08d 3666
316d5f72
RD		 3667 /* Under multipath it's possible for one rule to be currently
3668 * un-offloaded while the other rule is offloaded.
3669 */
04de7dda
RD		 3670 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3671 if (!peer_esw)
3672 goto out;
3673
226f2ca3
VB		 3674 if (flow_flag_test(flow, DUP) &&
3675 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 3676 u64 bytes2;
3677 u64 packets2;
3678 u64 lastuse2;
3679
3680 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 3681 if (!counter)
3682 goto no_peer_counter;
04de7dda
RD		 3683 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3684
3685 bytes += bytes2;
3686 packets += packets2;
3687 lastuse = max_t(u64, lastuse, lastuse2);
3688 }
3689
316d5f72 3690no_peer_counter:
04de7dda 3691 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 3692out:
3b1903ef 3693 flow_stats_update(&f->stats, bytes, packets, lastuse);
5a7e5bcb
VB		 3694errout:
3695 mlx5e_flow_put(priv, flow);
3696 return err;
aad7e08d
AV		 3697}
3698
fcb64c0f
EC		 3699static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
3700 struct netlink_ext_ack *extack)
3701{
3702 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3703 struct mlx5_eswitch *esw;
3704 u16 vport_num;
3705 u32 rate_mbps;
3706 int err;
3707
3708 esw = priv->mdev->priv.eswitch;
3709 /* rate is given in bytes/sec.
3710 * First convert to bits/sec and then round to the nearest mbit/secs.
3711 * mbit means million bits.
3712 * Moreover, if rate is non zero we choose to configure to a minimum of
3713 * 1 mbit/sec.
3714 */
3715 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
3716 vport_num = rpriv->rep->vport;
3717
3718 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
3719 if (err)
3720 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
3721
3722 return err;
3723}
3724
3725static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
3726 struct flow_action *flow_action,
3727 struct netlink_ext_ack *extack)
3728{
3729 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3730 const struct flow_action_entry *act;
3731 int err;
3732 int i;
3733
3734 if (!flow_action_has_entries(flow_action)) {
3735 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
3736 return -EINVAL;
3737 }
3738
3739 if (!flow_offload_has_one_action(flow_action)) {
3740 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
3741 return -EOPNOTSUPP;
3742 }
3743
3744 flow_action_for_each(i, act, flow_action) {
3745 switch (act->id) {
3746 case FLOW_ACTION_POLICE:
3747 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
3748 if (err)
3749 return err;
3750
3751 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
3752 break;
3753 default:
3754 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
3755 return -EOPNOTSUPP;
3756 }
3757 }
3758
3759 return 0;
3760}
3761
3762int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
3763 struct tc_cls_matchall_offload *ma)
3764{
3765 struct netlink_ext_ack *extack = ma->common.extack;
3766 int prio = TC_H_MAJ(ma->common.prio) >> 16;
3767
3768 if (prio != 1) {
3769 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
3770 return -EINVAL;
3771 }
3772
3773 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
3774}
3775
3776int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
3777 struct tc_cls_matchall_offload *ma)
3778{
3779 struct netlink_ext_ack *extack = ma->common.extack;
3780
3781 return apply_police_params(priv, 0, extack);
3782}
3783
3784void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
3785 struct tc_cls_matchall_offload *ma)
3786{
3787 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3788 struct rtnl_link_stats64 cur_stats;
3789 u64 dbytes;
3790 u64 dpkts;
3791
3792 cur_stats = priv->stats.vf_vport;
3793 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
3794 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
3795 rpriv->prev_vf_vport_stats = cur_stats;
3796 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
3797}
3798
4d8fcf21
AH		 3799static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3800 struct mlx5e_priv *peer_priv)
3801{
3802 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 3803 struct mlx5e_hairpin_entry *hpe, *tmp;
3804 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 3805 u16 peer_vhca_id;
3806 int bkt;
3807
3808 if (!same_hw_devs(priv, peer_priv))
3809 return;
3810
3811 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3812
b32accda 3813 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 3814 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
3815 if (refcount_inc_not_zero(&hpe->refcnt))
3816 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
3817 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
3818
3819 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
3820 wait_for_completion(&hpe->res_ready);
3821 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 3822 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 3823
3824 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 3825 }
3826}
3827
3828static int mlx5e_tc_netdev_event(struct notifier_block *this,
3829 unsigned long event, void *ptr)
3830{
3831 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3832 struct mlx5e_flow_steering *fs;
3833 struct mlx5e_priv *peer_priv;
3834 struct mlx5e_tc_table *tc;
3835 struct mlx5e_priv *priv;
3836
3837 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3838 event != NETDEV_UNREGISTER ||
3839 ndev->reg_state == NETREG_REGISTERED)
3840 return NOTIFY_DONE;
3841
3842 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3843 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3844 priv = container_of(fs, struct mlx5e_priv, fs);
3845 peer_priv = netdev_priv(ndev);
3846 if (priv == peer_priv ||
3847 !(priv->netdev->features & NETIF_F_HW_TC))
3848 return NOTIFY_DONE;
3849
3850 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3851
3852 return NOTIFY_DONE;
3853}
3854
655dc3d2 3855int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3856{
acff797c 3857 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3858 int err;
e8f887ac 3859
b6fac0b4 3860 mutex_init(&tc->t_lock);
dd58edc3 3861 hash_init(tc->mod_hdr.hlist);
b32accda 3862 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 3863 hash_init(tc->hairpin_tbl);
11c9c548 3864
4d8fcf21
AH		 3865 err = rhashtable_init(&tc->ht, &tc_ht_params);
3866 if (err)
3867 return err;
3868
3869 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3870 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3871 tc->netdevice_nb.notifier_call = NULL;
3872 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3873 }
3874
3875 return err;
e8f887ac
AV		 3876}
3877
3878static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3879{
3880 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3881 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3882
961e8979 3883 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3884 kfree(flow);
3885}
3886
655dc3d2 3887void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3888{
acff797c 3889 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3890
4d8fcf21
AH		 3891 if (tc->netdevice_nb.notifier_call)
3892 unregister_netdevice_notifier(&tc->netdevice_nb);
3893
b32accda
VB		 3894 mutex_destroy(&tc->hairpin_tbl_lock);
3895
d9ee0491 3896 rhashtable_destroy(&tc->ht);
e8f887ac 3897
acff797c
MG		 3898 if (!IS_ERR_OR_NULL(tc->t)) {
3899 mlx5_destroy_flow_table(tc->t);
3900 tc->t = NULL;
e8f887ac 3901 }
b6fac0b4 3902 mutex_destroy(&tc->t_lock);
e8f887ac 3903}
655dc3d2
OG		 3904
3905int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3906{
3907 return rhashtable_init(tc_ht, &tc_ht_params);
3908}
3909
3910void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3911{
3912 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3913}
01252a27 3914
226f2ca3 3915int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 3916{
d9ee0491 3917 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 3918
3919 return atomic_read(&tc_ht->nelems);
3920}
04de7dda
RD		 3921
3922void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3923{
3924 struct mlx5e_tc_flow *flow, *tmp;
3925
3926 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3927 __mlx5e_tc_del_fdb_peer_flow(flow);
3928}
b4a23329
RD		 3929
3930void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
3931{
3932 struct mlx5_rep_uplink_priv *rpriv =
3933 container_of(work, struct mlx5_rep_uplink_priv,
3934 reoffload_flows_work);
3935 struct mlx5e_tc_flow *flow, *tmp;
3936
ad86755b 3937 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 3938 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
3939 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 3940 unready_flow_del(flow);
b4a23329 3941 }
ad86755b 3942 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 3943}
Linux 6.x block layer and io_uring tree(s)